Hello,
I'm using Yosys to read and make the synthesis of the Division Verilogs. However, for the verilogs inside the benchmarks folder, the "hierarchy -check -top top_module" step is not working. As so, the circuit synthesis for example is not achievable... Can you verify if everything is correct for this example?
On the other hand, I've tried as well to make the synthesis of the Division verilog inside the benchmarks2 folder (a .sv file). With that one I was able to make it and then able to convert it to a .scd file. However, when I was testing that circuit, the outputs were mostly incorrect... For example, these 2 tests:
- Dividing 73 and 05 gives 17, which is correct (decimal is 115/5 = 23)
- Dividing 82 and 05 gives E7, which is not correct (decimal is 130/5 = 231)
If you don't mind, can you also check that circuit?
Thanks for your attention.
Best regards,
André Gabriel
Hello,
I'm using Yosys to read and make the synthesis of the Division Verilogs. However, for the verilogs inside the benchmarks folder, the "hierarchy -check -top top_module" step is not working. As so, the circuit synthesis for example is not achievable... Can you verify if everything is correct for this example?
On the other hand, I've tried as well to make the synthesis of the Division verilog inside the benchmarks2 folder (a .sv file). With that one I was able to make it and then able to convert it to a .scd file. However, when I was testing that circuit, the outputs were mostly incorrect... For example, these 2 tests:
If you don't mind, can you also check that circuit?
Thanks for your attention.
Best regards,
André Gabriel