style: cargo fmt the W1a/W2 additions (rustfmt 1.95.0)

Formatting-only; fixes the format/stable CI on #203. No logic change.

https://claude.ai/code/session_017GFLBnDy23AWBqvkbHHC41

Author: claude

src/hpc/activations.rs

@@ -388,18 +388,8 @@ fn log_softmax_f32_scalar(x: ArrayView1<f32>, mut out: ArrayViewMut1<f32>) {
 /// assert!((out[[1, 0]] - 1.0 / 3.0).abs() < 1e-5);
 /// ```
 pub fn softmax_axis_f32(x: ArrayView2<f32>, mut out: ArrayViewMut2<f32>, axis: Axis) {
-    assert!(
-        axis.index() < 2,
-        "softmax_axis_f32: axis {} is out of bounds for a 2-D array",
-        axis.index()
-    );
-    assert_eq!(
-        x.shape(),
-        out.shape(),
-        "softmax_axis_f32: shape mismatch (x={:?} out={:?})",
-        x.shape(),
-        out.shape()
-    );
+    assert!(axis.index() < 2, "softmax_axis_f32: axis {} is out of bounds for a 2-D array", axis.index());
+    assert_eq!(x.shape(), out.shape(), "softmax_axis_f32: shape mismatch (x={:?} out={:?})", x.shape(), out.shape());
     // `lanes(axis)` yields 1-D views ALONG `axis`; `lanes_mut(axis)` yields
     // the corresponding mutable 1-D views of `out`. Zipping them visits every
     // lane exactly once.
@@ -450,11 +440,7 @@ pub fn softmax_axis_f32(x: ArrayView2<f32>, mut out: ArrayViewMut2<f32>, axis: A
 /// assert!((out[[1, 2]] - expected).abs() < 1e-5);
 /// ```
 pub fn log_softmax_axis_f32(x: ArrayView2<f32>, mut out: ArrayViewMut2<f32>, axis: Axis) {
-    assert!(
-        axis.index() < 2,
-        "log_softmax_axis_f32: axis {} is out of bounds for a 2-D array",
-        axis.index()
-    );
+    assert!(axis.index() < 2, "log_softmax_axis_f32: axis {} is out of bounds for a 2-D array", axis.index());
     assert_eq!(
         x.shape(),
         out.shape(),
@@ -776,7 +762,13 @@ mod tests {
         softmax_f32(row.view(), out_1d.view_mut());
 
         for j in 0..4 {
-            assert!((out_axis[[0, j]] - out_1d[j]).abs() < 1e-6, "j={}: axis={} vs 1d={}", j, out_axis[[0, j]], out_1d[j]);
+            assert!(
+                (out_axis[[0, j]] - out_1d[j]).abs() < 1e-6,
+                "j={}: axis={} vs 1d={}",
+                j,
+                out_axis[[0, j]],
+                out_1d[j]
+            );
         }
     }
 
@@ -850,7 +842,10 @@ mod tests {
                 assert!(
                     (out_axis[[i, j]] - out_1d[j]).abs() < 1e-5,
                     "row={} j={}: axis={} vs 1d={}",
-                    i, j, out_axis[[i, j]], out_1d[j]
+                    i,
+                    j,
+                    out_axis[[i, j]],
+                    out_1d[j]
                 );
             }
         }

src/simd.rs

@@ -252,8 +252,8 @@ pub use crate::simd_avx512::{
     u32x8,
     u64x4,
     u64x8,
-    u8x8,
     u8x64,
+    u8x8,
     F32Mask16,
     // 512-bit (native AVX-512, __m512/__m512d/__m512i)
     F32x16,

src/simd_avx512.rs

@@ -2529,7 +2529,12 @@ impl U16x8 {
         // Bounds validation: debug panics, release falls back to safe get()
         #[cfg(debug_assertions)]
         for &i in &idx {
-            assert!((i as usize) < table.len(), "gather_u16: index {} out of bounds (table.len() = {})", i, table.len());
+            assert!(
+                (i as usize) < table.len(),
+                "gather_u16: index {} out of bounds (table.len() = {})",
+                i,
+                table.len()
+            );
         }
         let mut out = [0u16; 8];
         for k in 0..8 {
@@ -2623,10 +2628,8 @@ impl I8x32 {
             let raw_abs = core::arch::x86_64::_mm256_abs_epi8(self.0);
             // VPMINUB: unsigned-byte minimum. 0x80 unsigned = 128 > 0x7f = 127
             // so min(0x80, 0x7f) = 0x7f.  All values < 0x80 pass through.
-            let clamped = core::arch::x86_64::_mm256_min_epu8(
-                raw_abs,
-                core::arch::x86_64::_mm256_set1_epi8(0x7f_u8 as i8),
-            );
+            let clamped =
+                core::arch::x86_64::_mm256_min_epu8(raw_abs, core::arch::x86_64::_mm256_set1_epi8(0x7f_u8 as i8));
             I8x32(clamped)
         }
         #[cfg(not(target_arch = "x86_64"))]
@@ -2688,15 +2691,19 @@ impl U64x8 {
         {
             let arr = self.to_array();
             let mut out = [0u64; 8];
-            for i in 0..8 { out[i] = arr[i].count_ones() as u64; }
+            for i in 0..8 {
+                out[i] = arr[i].count_ones() as u64;
+            }
             U64x8::from_array(out)
         }
         #[cfg(not(target_arch = "x86_64"))]
         {
             // Scalar fallback (unreachable in practice for this backend file).
             let arr = self.to_array();
             let mut out = [0u64; 8];
-            for i in 0..8 { out[i] = arr[i].count_ones() as u64; }
+            for i in 0..8 {
+                out[i] = arr[i].count_ones() as u64;
+            }
             U64x8::from_array(out)
         }
     }
@@ -2731,7 +2738,9 @@ impl U64x8 {
             let a = self.to_array();
             let b = other.to_array();
             let mut sum = 0u64;
-            for i in 0..8 { sum += (a[i] ^ b[i]).count_ones() as u64; }
+            for i in 0..8 {
+                sum += (a[i] ^ b[i]).count_ones() as u64;
+            }
             sum
         }
     }

src/simd_int_ops.rs

@@ -905,18 +905,14 @@ mod tests {
         let packed = vec![0u64; 4];
         let aux = vec![0i8; 4];
         let mut out = vec![0i8; 4];
-        batch_packed_i4_16(&packed, &aux, &mut out, |lanes, a| {
-            lanes.lane_i8::<0>().wrapping_add(a)
-        });
+        batch_packed_i4_16(&packed, &aux, &mut out, |lanes, a| lanes.lane_i8::<0>().wrapping_add(a));
         assert!(out.iter().all(|&v| v == 0), "batch_packed_i4_16 all-zero");
 
         // Non-zero nibbles
         let packed2 = vec![0x1111_1111_1111_1111u64; 2];
         let aux2 = vec![10i8; 2];
         let mut out2 = vec![0i8; 2];
-        batch_packed_i4_16(&packed2, &aux2, &mut out2, |lanes, a| {
-            lanes.lane_i8::<0>().wrapping_add(a)
-        });
+        batch_packed_i4_16(&packed2, &aux2, &mut out2, |lanes, a| lanes.lane_i8::<0>().wrapping_add(a));
         // nibble 0x1 → lane 0 = +1; +10 = 11
         assert!(out2.iter().all(|&v| v == 11), "batch_packed_i4_16 nibble=1+aux=10");
     }

src/simd_scalar.rs

@@ -1395,7 +1395,9 @@ impl I8x32 {
     #[inline(always)]
     pub fn saturating_abs(self) -> Self {
         let mut o = [0i8; 32];
-        for i in 0..32 { o[i] = self.0[i].saturating_abs(); }
+        for i in 0..32 {
+            o[i] = self.0[i].saturating_abs();
+        }
         Self(o)
     }
 }
@@ -1572,7 +1574,9 @@ impl U64x8 {
     #[inline(always)]
     pub fn popcnt(self) -> Self {
         let mut out = [0u64; 8];
-        for i in 0..8 { out[i] = self.0[i].count_ones() as u64; }
+        for i in 0..8 {
+            out[i] = self.0[i].count_ones() as u64;
+        }
         Self(out)
     }
 
@@ -1588,7 +1592,9 @@ impl U64x8 {
     #[inline(always)]
     pub fn xor_popcount(self, other: Self) -> u64 {
         let mut sum = 0u64;
-        for i in 0..8 { sum += (self.0[i] ^ other.0[i]).count_ones() as u64; }
+        for i in 0..8 {
+            sum += (self.0[i] ^ other.0[i]).count_ones() as u64;
+        }
         sum
     }
 }
@@ -1604,7 +1610,9 @@ impl U64x4 {
     #[inline(always)]
     pub fn popcnt(self) -> Self {
         let mut out = [0u64; 4];
-        for i in 0..4 { out[i] = self.0[i].count_ones() as u64; }
+        for i in 0..4 {
+            out[i] = self.0[i].count_ones() as u64;
+        }
         Self(out)
     }
 }