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Commit c8fd327

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gkasprowgkasprow
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v1.0rc1
schematics and component placement ready for review.
1 parent 32b9ff1 commit c8fd327

33 files changed

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‎AMC_Connector_k.sch‎

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‎AMC_FMC_Carrier-PcbDoc-cache.lib‎

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‎AMC_FMC_Carrier-PcbDoc-rescue.lib‎

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‎AMC_FMC_Carrier-PcbDoc.kicad_pcb‎

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‎AMC_FMC_Carrier-PcbDoc.pro‎

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update=26.02.2019 15:42:42
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=../schematic/
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=
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CopperLayerCount=8
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.102
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MinViaDiameter=0.35
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MinViaDrill=0.152
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MinMicroViaDiameter=0.35
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MinMicroViaDrill=0.127
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MinHoleToHole=0.0254
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TrackWidth1=0.102
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TrackWidth2=0.112
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TrackWidth3=0.118
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TrackWidth4=0.127
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TrackWidth5=0.15
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TrackWidth6=0.178
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TrackWidth7=0.254
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TrackWidth8=0.4
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ViaDiameter1=0.35
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ViaDrill1=0.152
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ViaDiameter2=0.35
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ViaDrill2=0.152
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ViaDiameter3=0.35
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ViaDrill3=0.152
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ViaDiameter4=0.6
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ViaDrill4=0.35
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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dPairWidth2=0.102
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dPairGap2=0.22
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dPairViaGap2=0.22
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dPairWidth3=0.112
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dPairGap3=0.22
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dPairViaGap3=0.22
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SilkLineWidth=0.15
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SilkTextSizeV=0.5
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SilkTextSizeH=0.5
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SilkTextSizeThickness=0.09999999999999999
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.09999999999999999
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.09999999999999999
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0
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SolderMaskMinWidth=0.25
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=1
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=1
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=1
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/1]
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Name=DDR
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Clearance=0.1
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TrackWidth=0.127
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ViaDiameter=0.35
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ViaDrill=0.152
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/2]
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Name=DE_SIG
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/3]
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Name=FMC1_IPMI
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/4]
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Name=FMC2_IPMI
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/5]
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Name=POWER
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Clearance=0.1
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TrackWidth=0.381
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ViaDiameter=0.35
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ViaDrill=0.152
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/6]
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Name=RTM_IO[14..0]
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/7]
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Name=SE50
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/8]
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Name=SE60DE100
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/9]
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Name=SE_SIG
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Clearance=0.127
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TrackWidth=0.254
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ViaDiameter=0.889
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ViaDrill=0.635
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25

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