From 806b16b9bc040a62b2d68ace430aa3677b804a0a Mon Sep 17 00:00:00 2001 From: Keerthana Date: Thu, 29 Jan 2026 19:09:03 +0530 Subject: [PATCH] Added documentation for IHP OpenPDK integration with eSim --- docs/IHP_OpenPDK_eSim.md | 52 + .../cmosInverter/NMOS-180nm.lib | 13 + .../cmosInverter/PMOS-180nm.lib | 11 + library/ihp integration/cmosInverter/analysis | 1 + .../cmosInverter/cmosInverter.cir | 27 + .../cmosInverter/cmosInverter.cir.out | 21 + .../cmosInverter/cmosInverter.kicad_sch | 744 ++++++++++ .../cmosInverter/cmosInverter.proj | 1 + .../cmosInverter/cmosInverter.raw | 1298 +++++++++++++++++ .../cmosInverter/cmosInverterRun.cir | 41 + .../cmosInverter_Previous_Values.xml | 1 + .../cmosInverter/cmos_fallback_fixed.cir.txt | 26 + .../cmosInverter/cmos_fixed.cir | 28 + .../ihp integration/cmosInverter/cmos_run.cir | 28 + 14 files changed, 2292 insertions(+) create mode 100644 docs/IHP_OpenPDK_eSim.md create mode 100644 library/ihp integration/cmosInverter/NMOS-180nm.lib create mode 100644 library/ihp integration/cmosInverter/PMOS-180nm.lib create mode 100644 library/ihp integration/cmosInverter/analysis create mode 100644 library/ihp integration/cmosInverter/cmosInverter.cir create mode 100644 library/ihp integration/cmosInverter/cmosInverter.cir.out create mode 100644 library/ihp integration/cmosInverter/cmosInverter.kicad_sch create mode 100644 library/ihp integration/cmosInverter/cmosInverter.proj create mode 100644 library/ihp integration/cmosInverter/cmosInverter.raw create mode 100644 library/ihp integration/cmosInverter/cmosInverterRun.cir create mode 100644 library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml create mode 100644 library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt create mode 100644 library/ihp integration/cmosInverter/cmos_fixed.cir create mode 100644 library/ihp integration/cmosInverter/cmos_run.cir diff --git a/docs/IHP_OpenPDK_eSim.md b/docs/IHP_OpenPDK_eSim.md new file mode 100644 index 000000000..541fd0a58 --- /dev/null +++ b/docs/IHP_OpenPDK_eSim.md @@ -0,0 +1,52 @@ +# Integration of IHP OpenPDK with eSim + +## Overview + +This contribution demonstrates the integration of the IHP OpenPDK with eSim +to enable CMOS circuit design and simulation using open-source EDA tools. + +## Objective + +- Integrate IHP OpenPDK MOSFET SPICE models with eSim +- Design and simulate a CMOS inverter +- Perform DC sweep and transient analysis +- Validate inverter switching behavior + +## Tools Used + +- eSim (KiCad + NgSpice) +- IHP OpenPDK +- NgSpice + +## Circuit Implemented + +- CMOS Inverter using IHP NMOS and PMOS models +- Supply voltage: 1.8V + +## Simulations Performed + +### Transient Analysis + +- `.tran 0.1ns 20ns` +- Verified correct logical inversion + +### DC Sweep Analysis + +- `.dc VIN 0 1.8 0.01` +- Verified voltage transfer characteristics + +## Results + +- Correct inverter operation observed +- Threshold voltage near mid-supply +- Stable transient and DC behavior + +## Notes + +- Absolute paths were used for SPICE model inclusion +- Convergence issues resolved by reducing timestep + +## Report and Demo + +The detailed report and demonstration video are provided via links +in the corresponding GitHub Pull Request. diff --git a/library/ihp integration/cmosInverter/NMOS-180nm.lib b/library/ihp integration/cmosInverter/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/ihp integration/cmosInverter/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/ihp integration/cmosInverter/PMOS-180nm.lib b/library/ihp integration/cmosInverter/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/ihp integration/cmosInverter/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/ihp integration/cmosInverter/analysis b/library/ihp integration/cmosInverter/analysis new file mode 100644 index 000000000..6331256ea --- /dev/null +++ b/library/ihp integration/cmosInverter/analysis @@ -0,0 +1 @@ +.tran 0.1e-00 20e-00 0e-00 \ No newline at end of file diff --git a/library/ihp integration/cmosInverter/cmosInverter.cir b/library/ihp integration/cmosInverter/cmosInverter.cir new file mode 100644 index 000000000..2cbd3c1b8 --- /dev/null +++ b/library/ihp integration/cmosInverter/cmosInverter.cir @@ -0,0 +1,27 @@ + +* CMOS inverter - Windows-safe version (no Verilog-A needed) +.title CMOS inverter (fallback models) + +.global GND + +* Power +VDD vdd GND DC 1.2 + +* Input +VIN input GND PWL(0ns 0 2ns 0 4ns 1.2 9ns 1.2 11ns 0 20ns 0) + +* Simple built-in MOS models +.model NMOS NMOS (VTO=0.6 KP=100u) +.model PMOS PMOS (VTO=-0.6 KP=40u) + +* Devices: D G S B +M1 output input GND GND NMOS W=1u L=0.13u +M2 output input vdd vdd PMOS W=2u L=0.13u + +.control +tran 0.1n 40n +run +plot v(input) v(output) +.endc + +.end diff --git a/library/ihp integration/cmosInverter/cmosInverter.cir.out b/library/ihp integration/cmosInverter/cmosInverter.cir.out new file mode 100644 index 000000000..890cac3de --- /dev/null +++ b/library/ihp integration/cmosInverter/cmosInverter.cir.out @@ -0,0 +1,21 @@ +.title kicad schematic + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ input output net-_m1-pad1_ CMOSN W=100u L=100u M=1 +m2 output input gnd gnd CMOSP W=100u L=100u M=1 +* u2 output plot_v1 +v2 net-_m1-pad1_ gnd dc 5 +* u1 input plot_v1 +v1 input gnd pwl(0 0 10 0 11 5 20 5) +.tran 0.1e-00 20e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(output) +plot v(input) +.endc +.end diff --git a/library/ihp integration/cmosInverter/cmosInverter.kicad_sch b/library/ihp integration/cmosInverter/cmosInverter.kicad_sch new file mode 100644 index 000000000..8847132bd --- /dev/null +++ b/library/ihp integration/cmosInverter/cmosInverter.kicad_sch @@ -0,0 +1,744 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 1e3c9461-7029-410b-b626-f8fc60beaa63) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Devices:eSim_MOS_N" (pin_names (offset 0) hide) (in_bom yes) (on_board yes) + (property "Reference" "M" (id 0) (at 0 -3.81 0) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property "Value" "eSim_MOS_N" (id 1) (at 2.54 -1.27 0) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property 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5.000000000000000e+00 + 2.628311625487040e+00 + -8.925314696678044e-16 + -2.332858893341339e-01 diff --git a/library/ihp integration/cmosInverter/cmosInverterRun.cir b/library/ihp integration/cmosInverter/cmosInverterRun.cir new file mode 100644 index 000000000..5f9f37c8d --- /dev/null +++ b/library/ihp integration/cmosInverter/cmosInverterRun.cir @@ -0,0 +1,41 @@ +* cmos_ihp.cir -- CMOS inverter using IHP SG13G2 PDK (try this first) +.title CMOS inverter using IHP SG13G2 PDK + +* Load the corner section from the IHP PDK (defines params, includes subckt file) +.lib "C:/Users/KEERTHANA/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt + +.global GND + +* Power rail (taken from KiCad node Net-_XM1-Pad1_) +VDD Net-_XM1-Pad1_ GND DC 1.2 + +* Input: simple PWL (toggle) +VIN input GND PWL(0ns 0 2ns 0 4ns 1.2 9ns 1.2 11ns 0 20ns 0) + +* Transistor instances (Drain Gate Source Bulk Model) +* PMOS: source & bulk -> VDD +XM2 output input Net-_XM1-Pad1_ Net-_XM1-Pad1_ sg13_lv_pmos w=2.0u l=0.13u + +* NMOS: source & bulk -> GND +XM1 output input GND GND sg13_lv_nmos w=1.0u l=0.13u + +* optional: probe nodes (not required by netlist) +* U2 output plot_v1 +* U1 input plot_v1 + +.control +* transient sim: time step 0.1ns, total 40ns +tran 0.1n 40n +run + +* plot waveforms +plot v(input) v(output) + +* print DC operating point of NMOS (optional) +op +let Id = @m.xm1[id] +print Id + +.endc + +.end diff --git a/library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml b/library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml new file mode 100644 index 000000000..9f1bcd799 --- /dev/null +++ b/library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml @@ -0,0 +1 @@ +dc5pwl0 0 10 0 11 5 20 5truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.120secsecsec \ No newline at end of file diff --git a/library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt b/library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt new file mode 100644 index 000000000..3607709ad --- /dev/null +++ b/library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt @@ -0,0 +1,26 @@ +* CMOS inverter - Windows-safe version (no Verilog-A needed) +.title CMOS inverter (fallback models) + +.global GND + +* Power +VDD vdd GND DC 1.2 + +* Input +VIN input GND PWL(0ns 0 2ns 0 4ns 1.2 9ns 1.2 11ns 0 20ns 0) + +* Simple built-in MOS models +.model NMOS NMOS (VTO=0.6 KP=100u) +.model PMOS PMOS (VTO=-0.6 KP=40u) + +* Devices: D G S B +M1 output input GND GND NMOS W=1u L=0.13u +M2 output input vdd vdd PMOS W=2u L=0.13u + +.control +tran 0.1n 40n +run +plot v(input) v(output) +.endc + +.end diff --git a/library/ihp integration/cmosInverter/cmos_fixed.cir b/library/ihp integration/cmosInverter/cmos_fixed.cir new file mode 100644 index 000000000..d5e0b99c7 --- /dev/null +++ b/library/ihp integration/cmosInverter/cmos_fixed.cir @@ -0,0 +1,28 @@ +* cir_run.cir -- NMOS DC Test using IHP SG13G2 TT Corner +.title NMOS DC Test using IHP SG13G2 TT Corner + +* Load the PDK corner (this defines the parameters and pulls in the model file) +.lib "C:/Users/KEERTHANA/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt + +* Global reference +.GLOBAL GND + +* Bias sources +Vgs net1 GND 0.4 +Vds net3 GND 1.0 +Vd net3 net2 0 + +.param temp=27 + +* Device under test +* Drain = net2, Gate = net1, Source = GND, Bulk = GND +XM1 net2 net1 GND GND sg13_lv_nmos w=1.0u l=0.13u ng=1 m=1 + +.control +* save all ; optional - you can keep or remove +op +let Id = @m.xm1[id] +print Id +.endc + +.end diff --git a/library/ihp integration/cmosInverter/cmos_run.cir b/library/ihp integration/cmosInverter/cmos_run.cir new file mode 100644 index 000000000..d5e0b99c7 --- /dev/null +++ b/library/ihp integration/cmosInverter/cmos_run.cir @@ -0,0 +1,28 @@ +* cir_run.cir -- NMOS DC Test using IHP SG13G2 TT Corner +.title NMOS DC Test using IHP SG13G2 TT Corner + +* Load the PDK corner (this defines the parameters and pulls in the model file) +.lib "C:/Users/KEERTHANA/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt + +* Global reference +.GLOBAL GND + +* Bias sources +Vgs net1 GND 0.4 +Vds net3 GND 1.0 +Vd net3 net2 0 + +.param temp=27 + +* Device under test +* Drain = net2, Gate = net1, Source = GND, Bulk = GND +XM1 net2 net1 GND GND sg13_lv_nmos w=1.0u l=0.13u ng=1 m=1 + +.control +* save all ; optional - you can keep or remove +op +let Id = @m.xm1[id] +print Id +.endc + +.end