diff --git a/library/SubcircuitLibrary/74HC107/74HC107.cir b/library/SubcircuitLibrary/74HC107/74HC107.cir
new file mode 100644
index 000000000..ed058a42e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC107/74HC107.cir
@@ -0,0 +1,13 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC107\74HC107.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/06/25 18:06:53
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad12_ Net-_U1-Pad7_ Net-_U1-Pad13_ Net-_U1-Pad3_ Net-_U1-Pad2_ d_jkff		
+U3  Net-_U1-Pad8_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad10_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_jkff		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC107/74HC107.cir.out b/library/SubcircuitLibrary/74HC107/74HC107.cir.out
new file mode 100644
index 000000000..6128fd288
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC107/74HC107.cir.out
@@ -0,0 +1,20 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc107\74hc107.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ d_jkff
+* u3  net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ d_jkff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ u2
+a2 net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ u3
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u3 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC107/74HC107.pro b/library/SubcircuitLibrary/74HC107/74HC107.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC107/74HC107.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC107/74HC107.sub b/library/SubcircuitLibrary/74HC107/74HC107.sub
new file mode 100644
index 000000000..51395ed12
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC107/74HC107.sub
@@ -0,0 +1,14 @@
+* Subcircuit 74HC107
+.subckt 74HC107 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc107\74hc107.cir
+* u2  net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ d_jkff
+* u3  net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ d_jkff
+a1 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad12_ net-_u1-pad7_ net-_u1-pad13_ net-_u1-pad3_ net-_u1-pad2_ u2
+a2 net-_u1-pad8_ net-_u1-pad11_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad5_ net-_u1-pad6_ u3
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u3 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC107
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC107/74HC107_Previous_Values.xml b/library/SubcircuitLibrary/74HC107/74HC107_Previous_Values.xml
new file mode 100644
index 000000000..a0dacc4af
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC107/74HC107_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC107/analysis b/library/SubcircuitLibrary/74HC107/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC107/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC123/analysis b/library/SubcircuitLibrary/74HC123/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator-cache.lib b/library/SubcircuitLibrary/74HC123/multivibrator-cache.lib
new file mode 100644
index 000000000..e54c4afc5
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_tff
+#
+DEF d_tff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_tff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X T 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Out 5 550 350 200 L 50 50 1 1 O
+X Nout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator.cir b/library/SubcircuitLibrary/74HC123/multivibrator.cir
new file mode 100644
index 000000000..e85a5a9f3
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator.cir
@@ -0,0 +1,27 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\multivibrator\multivibrator.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 11/24/25 10:00:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  Net-_U5-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad6_ Net-_U7-Pad4_ Net-_U11-Pad1_ ? d_tff		
+U4  Net-_U1-Pad4_ Net-_U4-Pad2_ adc_bridge_1		
+R4  Net-_C2-Pad1_ Net-_R4-Pad2_ 100k		
+C2  Net-_C2-Pad1_ Net-_C2-Pad2_ 150n		
+U11  Net-_U11-Pad1_ Net-_C2-Pad1_ dac_bridge_1		
+U5  Net-_R2-Pad2_ Net-_U5-Pad2_ adc_bridge_1		
+U9  Net-_C2-Pad2_ Net-_U7-Pad4_ adc_bridge_1		
+R2  Net-_R2-Pad1_ Net-_R2-Pad2_ 10k		
+U6  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U6-Pad4_ Net-_U10-Pad1_ ? d_tff		
+U2  Net-_U1-Pad3_ Net-_U2-Pad2_ adc_bridge_1		
+R3  Net-_C1-Pad1_ Net-_R3-Pad2_ 100k		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 150n		
+U10  Net-_U10-Pad1_ Net-_C1-Pad1_ dac_bridge_1		
+U3  Net-_R1-Pad2_ Net-_U3-Pad2_ adc_bridge_1		
+U8  Net-_C1-Pad2_ Net-_U6-Pad4_ adc_bridge_1		
+R1  Net-_R1-Pad1_ Net-_R1-Pad2_ 10k		
+U1  Net-_R2-Pad1_ Net-_R1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_C1-Pad2_ Net-_C2-Pad2_ Net-_R3-Pad2_ Net-_R4-Pad2_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator.cir.out b/library/SubcircuitLibrary/74HC123/multivibrator.cir.out
new file mode 100644
index 000000000..443aed583
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator.cir.out
@@ -0,0 +1,58 @@
+* c:\fossee\esim\library\subcircuitlibrary\multivibrator\multivibrator.cir
+
+* u7  net-_u5-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u7-pad4_ net-_u11-pad1_ ? d_tff
+* u4  net-_u1-pad4_ net-_u4-pad2_ adc_bridge_1
+r4  net-_c2-pad1_ net-_r4-pad2_ 100k
+c2  net-_c2-pad1_ net-_c2-pad2_ 150n
+* u11  net-_u11-pad1_ net-_c2-pad1_ dac_bridge_1
+* u5  net-_r2-pad2_ net-_u5-pad2_ adc_bridge_1
+* u9  net-_c2-pad2_ net-_u7-pad4_ adc_bridge_1
+r2  net-_r2-pad1_ net-_r2-pad2_ 10k
+* u6  net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u6-pad4_ net-_u10-pad1_ ? d_tff
+* u2  net-_u1-pad3_ net-_u2-pad2_ adc_bridge_1
+r3  net-_c1-pad1_ net-_r3-pad2_ 100k
+c1  net-_c1-pad1_ net-_c1-pad2_ 150n
+* u10  net-_u10-pad1_ net-_c1-pad1_ dac_bridge_1
+* u3  net-_r1-pad2_ net-_u3-pad2_ adc_bridge_1
+* u8  net-_c1-pad2_ net-_u6-pad4_ adc_bridge_1
+r1  net-_r1-pad1_ net-_r1-pad2_ 10k
+* u1  net-_r2-pad1_ net-_r1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_c2-pad2_ net-_r3-pad2_ net-_r4-pad2_ port
+a1 net-_u5-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u7-pad4_ net-_u11-pad1_ ? u7
+a2 [net-_u1-pad4_ ] [net-_u4-pad2_ ] u4
+a3 [net-_u11-pad1_ ] [net-_c2-pad1_ ] u11
+a4 [net-_r2-pad2_ ] [net-_u5-pad2_ ] u5
+a5 [net-_c2-pad2_ ] [net-_u7-pad4_ ] u9
+a6 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u6-pad4_ net-_u10-pad1_ ? u6
+a7 [net-_u1-pad3_ ] [net-_u2-pad2_ ] u2
+a8 [net-_u10-pad1_ ] [net-_c1-pad1_ ] u10
+a9 [net-_r1-pad2_ ] [net-_u3-pad2_ ] u3
+a10 [net-_c1-pad2_ ] [net-_u6-pad4_ ] u8
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator.pro b/library/SubcircuitLibrary/74HC123/multivibrator.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator.sch b/library/SubcircuitLibrary/74HC123/multivibrator.sch
new file mode 100644
index 000000000..41e211653
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator.sch
@@ -0,0 +1,411 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:multivibrator-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_tff U?
+U 1 1 6923DB31
+P 5700 4200
+F 0 "U?" H 5700 4200 60  0000 C CNN
+F 1 "d_tff" H 5700 4350 60  0000 C CNN
+F 2 "" H 5700 4200 60  0000 C CNN
+F 3 "" H 5700 4200 60  0000 C CNN
+	1    5700 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_1 U?
+U 1 1 6923DB32
+P 4450 4550
+F 0 "U?" H 4450 4550 60  0000 C CNN
+F 1 "adc_bridge_1" H 4450 4700 60  0000 C CNN
+F 2 "" H 4450 4550 60  0000 C CNN
+F 3 "" H 4450 4550 60  0000 C CNN
+	1    4450 4550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3200 4500 3850 4500
+Wire Wire Line
+	5000 4500 5150 4500
+$Comp
+L resistor R?
+U 1 1 6923DB33
+P 8250 3900
+F 0 "R?" H 8300 4030 50  0000 C CNN
+F 1 "100k" H 8300 3850 50  0000 C CNN
+F 2 "" H 8300 3880 30  0000 C CNN
+F 3 "" V 8300 3950 30  0000 C CNN
+	1    8250 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 6923DB34
+P 8000 4250
+F 0 "C?" H 8025 4350 50  0000 L CNN
+F 1 "150n" H 8025 4150 50  0000 L CNN
+F 2 "" H 8038 4100 30  0000 C CNN
+F 3 "" H 8000 4250 60  0000 C CNN
+	1    8000 4250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7550 3850 8150 3850
+Wire Wire Line
+	8000 4100 8000 3850
+Connection ~ 8000 3850
+Wire Wire Line
+	5700 4800 5700 4900
+Wire Wire Line
+	8000 5100 8000 4400
+$Comp
+L dac_bridge_1 U?
+U 1 1 6923DB35
+P 7000 3900
+F 0 "U?" H 7000 3900 60  0000 C CNN
+F 1 "dac_bridge_1" H 7000 4050 60  0000 C CNN
+F 2 "" H 7000 3900 60  0000 C CNN
+F 3 "" H 7000 3900 60  0000 C CNN
+	1    7000 3900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6250 3850 6400 3850
+$Comp
+L adc_bridge_1 U?
+U 1 1 6923DB37
+P 4500 3350
+F 0 "U?" H 4500 3350 60  0000 C CNN
+F 1 "adc_bridge_1" H 4500 3500 60  0000 C CNN
+F 2 "" H 4500 3350 60  0000 C CNN
+F 3 "" H 4500 3350 60  0000 C CNN
+	1    4500 3350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2950 3300 3500 3300
+Wire Wire Line
+	5050 3300 5150 3300
+Wire Wire Line
+	5150 3300 5150 3850
+$Comp
+L adc_bridge_1 U?
+U 1 1 6923DB3A
+P 6750 4850
+F 0 "U?" H 6750 4850 60  0000 C CNN
+F 1 "adc_bridge_1" H 6750 5000 60  0000 C CNN
+F 2 "" H 6750 4850 60  0000 C CNN
+F 3 "" H 6750 4850 60  0000 C CNN
+	1    6750 4850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7350 4900 8000 4900
+Connection ~ 8000 4900
+Wire Wire Line
+	5700 4900 6200 4900
+$Comp
+L resistor R?
+U 1 1 6923DB3B
+P 3600 3350
+F 0 "R?" H 3650 3480 50  0000 C CNN
+F 1 "10k" H 3650 3300 50  0000 C CNN
+F 2 "" H 3650 3330 30  0000 C CNN
+F 3 "" V 3650 3400 30  0000 C CNN
+	1    3600 3350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3800 3300 3900 3300
+$Comp
+L d_tff U?
+U 1 1 6923E368
+P 5500 2100
+F 0 "U?" H 5500 2100 60  0000 C CNN
+F 1 "d_tff" H 5500 2250 60  0000 C CNN
+F 2 "" H 5500 2100 60  0000 C CNN
+F 3 "" H 5500 2100 60  0000 C CNN
+	1    5500 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_1 U?
+U 1 1 6923E36E
+P 4250 2450
+F 0 "U?" H 4250 2450 60  0000 C CNN
+F 1 "adc_bridge_1" H 4250 2600 60  0000 C CNN
+F 2 "" H 4250 2450 60  0000 C CNN
+F 3 "" H 4250 2450 60  0000 C CNN
+	1    4250 2450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3200 2400 3650 2400
+Wire Wire Line
+	4800 2400 4950 2400
+$Comp
+L resistor R?
+U 1 1 6923E376
+P 8050 1800
+F 0 "R?" H 8100 1930 50  0000 C CNN
+F 1 "100k" H 8100 1750 50  0000 C CNN
+F 2 "" H 8100 1780 30  0000 C CNN
+F 3 "" V 8100 1850 30  0000 C CNN
+	1    8050 1800
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 6923E37C
+P 7800 2150
+F 0 "C?" H 7825 2250 50  0000 L CNN
+F 1 "150n" H 7825 2050 50  0000 L CNN
+F 2 "" H 7838 2000 30  0000 C CNN
+F 3 "" H 7800 2150 60  0000 C CNN
+	1    7800 2150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7350 1750 7950 1750
+Wire Wire Line
+	7800 2000 7800 1750
+Connection ~ 7800 1750
+Wire Wire Line
+	5500 2700 5500 2800
+Wire Wire Line
+	7800 3000 7800 2300
+$Comp
+L dac_bridge_1 U?
+U 1 1 6923E387
+P 6800 1800
+F 0 "U?" H 6800 1800 60  0000 C CNN
+F 1 "dac_bridge_1" H 6800 1950 60  0000 C CNN
+F 2 "" H 6800 1800 60  0000 C CNN
+F 3 "" H 6800 1800 60  0000 C CNN
+	1    6800 1800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 1750 6200 1750
+$Comp
+L adc_bridge_1 U?
+U 1 1 6923E394
+P 4300 1250
+F 0 "U?" H 4300 1250 60  0000 C CNN
+F 1 "adc_bridge_1" H 4300 1400 60  0000 C CNN
+F 2 "" H 4300 1250 60  0000 C CNN
+F 3 "" H 4300 1250 60  0000 C CNN
+	1    4300 1250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 1200 4950 1200
+Wire Wire Line
+	4950 1200 4950 1750
+$Comp
+L adc_bridge_1 U?
+U 1 1 6923E3B1
+P 6550 2750
+F 0 "U?" H 6550 2750 60  0000 C CNN
+F 1 "adc_bridge_1" H 6550 2900 60  0000 C CNN
+F 2 "" H 6550 2750 60  0000 C CNN
+F 3 "" H 6550 2750 60  0000 C CNN
+	1    6550 2750
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7150 2800 7800 2800
+Connection ~ 7800 2800
+Wire Wire Line
+	5500 2800 6000 2800
+$Comp
+L resistor R?
+U 1 1 6923E3BA
+P 3400 1250
+F 0 "R?" H 3450 1380 50  0000 C CNN
+F 1 "10k" H 3450 1200 50  0000 C CNN
+F 2 "" H 3450 1230 30  0000 C CNN
+F 3 "" V 3450 1300 30  0000 C CNN
+	1    3400 1250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3600 1200 3700 1200
+$Comp
+L PORT U?
+U 1 1 6923EC6B
+P 2900 1200
+F 0 "U?" H 2950 1300 30  0000 C CNN
+F 1 "PORT" H 2900 1200 30  0000 C CNN
+F 2 "" H 2900 1200 60  0000 C CNN
+F 3 "" H 2900 1200 60  0000 C CNN
+	1    2900 1200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U?
+U 2 1 6923EDA0
+P 2700 3300
+F 0 "U?" H 2750 3400 30  0000 C CNN
+F 1 "PORT" H 2700 3300 30  0000 C CNN
+F 2 "" H 2700 3300 60  0000 C CNN
+F 3 "" H 2700 3300 60  0000 C CNN
+	2    2700 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U?
+U 3 1 6923EE9F
+P 2950 2400
+F 0 "U?" H 3000 2500 30  0000 C CNN
+F 1 "PORT" H 2950 2400 30  0000 C CNN
+F 2 "" H 2950 2400 60  0000 C CNN
+F 3 "" H 2950 2400 60  0000 C CNN
+	3    2950 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U?
+U 4 1 6923EF7C
+P 2950 4500
+F 0 "U?" H 3000 4600 30  0000 C CNN
+F 1 "PORT" H 2950 4500 30  0000 C CNN
+F 2 "" H 2950 4500 60  0000 C CNN
+F 3 "" H 2950 4500 60  0000 C CNN
+	4    2950 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U?
+U 5 1 6923F049
+P 5500 1000
+F 0 "U?" H 5550 1100 30  0000 C CNN
+F 1 "PORT" H 5500 1000 30  0000 C CNN
+F 2 "" H 5500 1000 60  0000 C CNN
+F 3 "" H 5500 1000 60  0000 C CNN
+	5    5500 1000
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U?
+U 6 1 6923F138
+P 5700 3000
+F 0 "U?" H 5750 3100 30  0000 C CNN
+F 1 "PORT" H 5700 3000 30  0000 C CNN
+F 2 "" H 5700 3000 60  0000 C CNN
+F 3 "" H 5700 3000 60  0000 C CNN
+	6    5700 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U?
+U 7 1 6923F223
+P 8250 3000
+F 0 "U?" H 8300 3100 30  0000 C CNN
+F 1 "PORT" H 8250 3000 30  0000 C CNN
+F 2 "" H 8250 3000 60  0000 C CNN
+F 3 "" H 8250 3000 60  0000 C CNN
+	7    8250 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U?
+U 8 1 6923F301
+P 8700 1750
+F 0 "U?" H 8750 1850 30  0000 C CNN
+F 1 "PORT" H 8700 1750 30  0000 C CNN
+F 2 "" H 8700 1750 60  0000 C CNN
+F 3 "" H 8700 1750 60  0000 C CNN
+	8    8700 1750
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U?
+U 9 1 6923F404
+P 8900 3850
+F 0 "U?" H 8950 3950 30  0000 C CNN
+F 1 "PORT" H 8900 3850 30  0000 C CNN
+F 2 "" H 8900 3850 60  0000 C CNN
+F 3 "" H 8900 3850 60  0000 C CNN
+	9    8900 3850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U?
+U 10 1 6923F4A4
+P 8600 5100
+F 0 "U?" H 8650 5200 30  0000 C CNN
+F 1 "PORT" H 8600 5100 30  0000 C CNN
+F 2 "" H 8600 5100 60  0000 C CNN
+F 3 "" H 8600 5100 60  0000 C CNN
+	10   8600 5100
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	3150 1200 3300 1200
+Wire Wire Line
+	5500 1250 5500 1450
+Wire Wire Line
+	8450 3850 8650 3850
+Wire Wire Line
+	8000 5100 8350 5100
+Wire Wire Line
+	5700 3250 5700 3550
+Wire Wire Line
+	7800 3000 8000 3000
+Wire Wire Line
+	8250 1750 8450 1750
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator.sub b/library/SubcircuitLibrary/74HC123/multivibrator.sub
new file mode 100644
index 000000000..090564a6e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator.sub
@@ -0,0 +1,52 @@
+* Subcircuit multivibrator
+.subckt multivibrator net-_r2-pad1_ net-_r1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_c2-pad2_ net-_r3-pad2_ net-_r4-pad2_ 
+* c:\fossee\esim\library\subcircuitlibrary\multivibrator\multivibrator.cir
+* u7  net-_u5-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u7-pad4_ net-_u11-pad1_ ? d_tff
+* u4  net-_u1-pad4_ net-_u4-pad2_ adc_bridge_1
+r4  net-_c2-pad1_ net-_r4-pad2_ 100k
+c2  net-_c2-pad1_ net-_c2-pad2_ 150n
+* u11  net-_u11-pad1_ net-_c2-pad1_ dac_bridge_1
+* u5  net-_r2-pad2_ net-_u5-pad2_ adc_bridge_1
+* u9  net-_c2-pad2_ net-_u7-pad4_ adc_bridge_1
+r2  net-_r2-pad1_ net-_r2-pad2_ 10k
+* u6  net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u6-pad4_ net-_u10-pad1_ ? d_tff
+* u2  net-_u1-pad3_ net-_u2-pad2_ adc_bridge_1
+r3  net-_c1-pad1_ net-_r3-pad2_ 100k
+c1  net-_c1-pad1_ net-_c1-pad2_ 150n
+* u10  net-_u10-pad1_ net-_c1-pad1_ dac_bridge_1
+* u3  net-_r1-pad2_ net-_u3-pad2_ adc_bridge_1
+* u8  net-_c1-pad2_ net-_u6-pad4_ adc_bridge_1
+r1  net-_r1-pad1_ net-_r1-pad2_ 10k
+a1 net-_u5-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u7-pad4_ net-_u11-pad1_ ? u7
+a2 [net-_u1-pad4_ ] [net-_u4-pad2_ ] u4
+a3 [net-_u11-pad1_ ] [net-_c2-pad1_ ] u11
+a4 [net-_r2-pad2_ ] [net-_u5-pad2_ ] u5
+a5 [net-_c2-pad2_ ] [net-_u7-pad4_ ] u9
+a6 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u6-pad4_ net-_u10-pad1_ ? u6
+a7 [net-_u1-pad3_ ] [net-_u2-pad2_ ] u2
+a8 [net-_u10-pad1_ ] [net-_c1-pad1_ ] u10
+a9 [net-_r1-pad2_ ] [net-_u3-pad2_ ] u3
+a10 [net-_c1-pad2_ ] [net-_u6-pad4_ ] u8
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends multivibrator
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC123/multivibrator_Previous_Values.xml b/library/SubcircuitLibrary/74HC123/multivibrator_Previous_Values.xml
new file mode 100644
index 000000000..c583fc718
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC123/multivibrator_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u7 name="type">d_tff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for T Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u7><u4 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)">5</field12><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u4><u11 name="type">dac_bridge<field15 name="Enter value for out_low (default=0.0)" /><field16 name="Enter value for out_high (default=5.0)">5</field16><field17 name="Enter value for out_undef (default=0.5)" /><field18 name="Enter value for input load (default=1.0e-12)" /><field19 name="Enter the Rise Time (default=1.0e-9)" /><field20 name="Enter the Fall Time (default=1.0e-9)" /></u11><u5 name="type">adc_bridge<field21 name="Enter value for in_low (default=1.0)" /><field22 name="Enter value for in_high (default=2.0)">5</field22><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u5><u9 name="type">adc_bridge<field25 name="Enter value for in_low (default=1.0)" /><field26 name="Enter value for in_high (default=2.0)">5</field26><field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /></u9><u6 name="type">d_tff<field29 name="Enter Clk Delay (default=1.0e-9)" /><field30 name="Enter Set Delay (default=1.0e-9)" /><field31 name="Enter Reset Delay (default=1.0)" /><field32 name="Enter IC (default=0)" /><field33 name="Enter value for T Load (default=1.0e-12)" /><field34 name="Enter value for Clk Load (default=1.0e-12)" /><field35 name="Enter value for Set Load (default=1.0e-12)" /><field36 name="Enter value for Reset Load (default=1.0e-12)" /><field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /></u6><u2 name="type">adc_bridge<field39 name="Enter value for in_low (default=1.0)" /><field40 name="Enter value for in_high (default=2.0)">5</field40><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u2><u10 name="type">dac_bridge<field43 name="Enter value for out_low (default=0.0)" /><field44 name="Enter value for out_high (default=5.0)">5</field44><field45 name="Enter value for out_undef (default=0.5)" /><field46 name="Enter value for input load (default=1.0e-12)" /><field47 name="Enter the Rise Time (default=1.0e-9)" /><field48 name="Enter the Fall Time (default=1.0e-9)" /></u10><u3 name="type">adc_bridge<field49 name="Enter value for in_low (default=1.0)" /><field50 name="Enter value for in_high (default=2.0)">5</field50><field51 name="Enter Rise Delay (default=1.0e-9)" /><field52 name="Enter Fall Delay (default=1.0e-9)" /></u3><u8 name="type">adc_bridge<field53 name="Enter value for in_low (default=1.0)" /><field54 name="Enter value for in_high (default=2.0)">5</field54><field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /></u8></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC164/74HC164-cache.lib b/library/SubcircuitLibrary/74HC164/74HC164-cache.lib
new file mode 100644
index 000000000..ffd9950e2
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164-cache.lib
@@ -0,0 +1,132 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC164/74HC164.cir b/library/SubcircuitLibrary/74HC164/74HC164.cir
new file mode 100644
index 000000000..4efcd2739
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164.cir
@@ -0,0 +1,25 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC164\74HC164.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 11/29/25 10:58:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  Net-_U10-Pad7_ Net-_U11-Pad2_ VCC Net-_U11-Pad4_ Net-_U10-Pad8_ ? d_dff		
+U6  Net-_U3-Pad2_ Net-_U11-Pad2_ Net-_U1-Pad12_ Net-_U11-Pad4_ Net-_U10-Pad1_ ? d_dff		
+U8  Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U1-Pad12_ Net-_U11-Pad4_ Net-_U10-Pad2_ ? d_dff		
+U9  Net-_U10-Pad6_ Net-_U11-Pad2_ VCC Net-_U11-Pad4_ Net-_U10-Pad7_ ? d_dff		
+U11  Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U1-Pad12_ Net-_U11-Pad4_ Net-_U10-Pad3_ ? d_dff		
+U12  Net-_U10-Pad5_ Net-_U11-Pad2_ VCC Net-_U11-Pad4_ Net-_U10-Pad6_ ? d_dff		
+U13  Net-_U10-Pad3_ Net-_U11-Pad2_ Net-_U1-Pad12_ Net-_U11-Pad4_ Net-_U10-Pad4_ ? d_dff		
+U14  Net-_U10-Pad4_ Net-_U11-Pad2_ VCC Net-_U11-Pad4_ Net-_U10-Pad5_ Net-_U14-Pad6_ d_dff		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ Net-_U10-Pad7_ Net-_U10-Pad8_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ dac_bridge_8		
+U5  Net-_U1-Pad1_ Net-_U11-Pad2_ adc_bridge_1		
+U2  Net-_U1-Pad3_ Net-_U2-Pad2_ adc_bridge_1		
+U15  Net-_U10-Pad4_ Net-_U11-Pad2_ VCC Net-_U11-Pad4_ Net-_U10-Pad5_ Net-_U14-Pad6_ d_dff		
+U3  Net-_U1-Pad2_ Net-_U3-Pad2_ adc_bridge_1		
+U4  Net-_U2-Pad2_ Net-_U11-Pad4_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC164/74HC164.cir.out b/library/SubcircuitLibrary/74HC164/74HC164.cir.out
new file mode 100644
index 000000000..f86557600
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164.cir.out
@@ -0,0 +1,68 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc164\74hc164.cir
+
+* u7  net-_u10-pad7_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad8_ ? d_dff
+* u6  net-_u3-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad1_ ? d_dff
+* u8  net-_u10-pad1_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad2_ ? d_dff
+* u9  net-_u10-pad6_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad7_ ? d_dff
+* u11  net-_u10-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad3_ ? d_dff
+* u12  net-_u10-pad5_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad6_ ? d_dff
+* u13  net-_u10-pad3_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad4_ ? d_dff
+* u14  net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ d_dff
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ dac_bridge_8
+* u5  net-_u1-pad1_ net-_u11-pad2_ adc_bridge_1
+* u2  net-_u1-pad3_ net-_u2-pad2_ adc_bridge_1
+* u15  net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ d_dff
+* u3  net-_u1-pad2_ net-_u3-pad2_ adc_bridge_1
+* u4  net-_u2-pad2_ net-_u11-pad4_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+a1 net-_u10-pad7_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad8_ ? u7
+a2 net-_u3-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad1_ ? u6
+a3 net-_u10-pad1_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad2_ ? u8
+a4 net-_u10-pad6_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad7_ ? u9
+a5 net-_u10-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad3_ ? u11
+a6 net-_u10-pad5_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad6_ ? u12
+a7 net-_u10-pad3_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad4_ ? u13
+a8 net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ u14
+a9 [net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ] u10
+a10 [net-_u1-pad1_ ] [net-_u11-pad2_ ] u5
+a11 [net-_u1-pad3_ ] [net-_u2-pad2_ ] u2
+a12 net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ u15
+a13 [net-_u1-pad2_ ] [net-_u3-pad2_ ] u3
+a14 net-_u2-pad2_ net-_u11-pad4_ u4
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u14 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_8, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC164/74HC164.pro b/library/SubcircuitLibrary/74HC164/74HC164.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC164/74HC164.sch b/library/SubcircuitLibrary/74HC164/74HC164.sch
new file mode 100644
index 000000000..71eaf138a
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164.sch
@@ -0,0 +1,697 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74hc164-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U7
+U 1 1 692A8193
+P 3950 4050
+F 0 "U7" H 3950 4050 60  0000 C CNN
+F 1 "d_dff" H 3950 4200 60  0000 C CNN
+F 2 "" H 3950 4050 60  0000 C CNN
+F 3 "" H 3950 4050 60  0000 C CNN
+	1    3950 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U6
+U 1 1 692A8194
+P 3950 1400
+F 0 "U6" H 3950 1400 60  0000 C CNN
+F 1 "d_dff" H 3950 1550 60  0000 C CNN
+F 2 "" H 3950 1400 60  0000 C CNN
+F 3 "" H 3950 1400 60  0000 C CNN
+	1    3950 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U8
+U 1 1 692A8195
+P 5800 1400
+F 0 "U8" H 5800 1400 60  0000 C CNN
+F 1 "d_dff" H 5800 1550 60  0000 C CNN
+F 2 "" H 5800 1400 60  0000 C CNN
+F 3 "" H 5800 1400 60  0000 C CNN
+	1    5800 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U9
+U 1 1 692A8196
+P 5800 4050
+F 0 "U9" H 5800 4050 60  0000 C CNN
+F 1 "d_dff" H 5800 4200 60  0000 C CNN
+F 2 "" H 5800 4050 60  0000 C CNN
+F 3 "" H 5800 4050 60  0000 C CNN
+	1    5800 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U11
+U 1 1 692A8197
+P 7750 1400
+F 0 "U11" H 7750 1400 60  0000 C CNN
+F 1 "d_dff" H 7750 1550 60  0000 C CNN
+F 2 "" H 7750 1400 60  0000 C CNN
+F 3 "" H 7750 1400 60  0000 C CNN
+	1    7750 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U12
+U 1 1 692A8198
+P 7800 4050
+F 0 "U12" H 7800 4050 60  0000 C CNN
+F 1 "d_dff" H 7800 4200 60  0000 C CNN
+F 2 "" H 7800 4050 60  0000 C CNN
+F 3 "" H 7800 4050 60  0000 C CNN
+	1    7800 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U13
+U 1 1 692A8199
+P 9500 1400
+F 0 "U13" H 9500 1400 60  0000 C CNN
+F 1 "d_dff" H 9500 1550 60  0000 C CNN
+F 2 "" H 9500 1400 60  0000 C CNN
+F 3 "" H 9500 1400 60  0000 C CNN
+	1    9500 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U14
+U 1 1 692A819A
+P 9600 4050
+F 0 "U14" H 9600 4050 60  0000 C CNN
+F 1 "d_dff" H 9600 4200 60  0000 C CNN
+F 2 "" H 9600 4050 60  0000 C CNN
+F 3 "" H 9600 4050 60  0000 C CNN
+	1    9600 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_8 U10
+U 1 1 692A819B
+P 5850 5850
+F 0 "U10" H 5850 5850 60  0000 C CNN
+F 1 "dac_bridge_8" H 5850 6000 60  0000 C CNN
+F 2 "" H 5850 5850 60  0000 C CNN
+F 3 "" H 5850 5850 60  0000 C CNN
+	1    5850 5850
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_1 U5
+U 1 1 692A819E
+P 2350 1750
+F 0 "U5" H 2350 1750 60  0000 C CNN
+F 1 "adc_bridge_1" H 2350 1900 60  0000 C CNN
+F 2 "" H 2350 1750 60  0000 C CNN
+F 3 "" H 2350 1750 60  0000 C CNN
+	1    2350 1750
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_1 U2
+U 1 1 692A81A1
+P 2000 4000
+F 0 "U2" H 2000 4000 60  0000 C CNN
+F 1 "adc_bridge_1" H 2000 4150 60  0000 C CNN
+F 2 "" H 2000 4000 60  0000 C CNN
+F 3 "" H 2000 4000 60  0000 C CNN
+	1    2000 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_VCC #PWR01
+U 1 1 692A81AF
+P 9600 3400
+F 0 "#PWR01" H 9600 3250 50  0001 C CNN
+F 1 "eSim_VCC" H 9600 3550 50  0000 C CNN
+F 2 "" H 9600 3400 50  0001 C CNN
+F 3 "" H 9600 3400 50  0001 C CNN
+	1    9600 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_VCC #PWR02
+U 1 1 692A81B0
+P 7800 3400
+F 0 "#PWR02" H 7800 3250 50  0001 C CNN
+F 1 "eSim_VCC" H 7800 3550 50  0000 C CNN
+F 2 "" H 7800 3400 50  0001 C CNN
+F 3 "" H 7800 3400 50  0001 C CNN
+	1    7800 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_VCC #PWR03
+U 1 1 692A81B1
+P 5800 3400
+F 0 "#PWR03" H 5800 3250 50  0001 C CNN
+F 1 "eSim_VCC" H 5800 3550 50  0000 C CNN
+F 2 "" H 5800 3400 50  0001 C CNN
+F 3 "" H 5800 3400 50  0001 C CNN
+	1    5800 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_VCC #PWR04
+U 1 1 692A81B2
+P 3950 3400
+F 0 "#PWR04" H 3950 3250 50  0001 C CNN
+F 1 "eSim_VCC" H 3950 3550 50  0000 C CNN
+F 2 "" H 3950 3400 50  0001 C CNN
+F 3 "" H 3950 3400 50  0001 C CNN
+	1    3950 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U15
+U 1 1 692A81B4
+P 9600 4050
+F 0 "U15" H 9600 4050 60  0000 C CNN
+F 1 "d_dff" H 9600 4200 60  0000 C CNN
+F 2 "" H 9600 4050 60  0000 C CNN
+F 3 "" H 9600 4050 60  0000 C CNN
+	1    9600 4050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4500 1050 5250 1050
+Wire Wire Line
+	6350 1050 7200 1050
+Wire Wire Line
+	8300 1050 8950 1050
+Wire Wire Line
+	10050 1050 10750 1050
+Wire Wire Line
+	3300 1050 3400 1050
+Wire Wire Line
+	10750 1050 10750 5350
+Wire Wire Line
+	10750 3300 8850 3300
+Wire Wire Line
+	8850 3300 8850 3700
+Wire Wire Line
+	8850 3700 9050 3700
+Wire Wire Line
+	10150 3700 10550 3700
+Wire Wire Line
+	10350 3700 10350 3100
+Wire Wire Line
+	10350 3100 6900 3100
+Wire Wire Line
+	6900 3100 6900 3700
+Wire Wire Line
+	6900 3700 7250 3700
+Wire Wire Line
+	8350 3700 8550 3700
+Wire Wire Line
+	8550 3300 8550 5100
+Wire Wire Line
+	8550 3300 4950 3300
+Wire Wire Line
+	4950 3300 4950 3700
+Wire Wire Line
+	4950 3700 5250 3700
+Wire Wire Line
+	6350 3700 6550 3700
+Wire Wire Line
+	6550 3100 6550 5050
+Wire Wire Line
+	6550 3100 3100 3100
+Wire Wire Line
+	3100 3100 3100 3700
+Wire Wire Line
+	3100 3700 3400 3700
+Wire Wire Line
+	3950 2650 3950 2000
+Wire Wire Line
+	1900 2650 9500 2650
+Wire Wire Line
+	5800 2650 5800 2000
+Connection ~ 3950 2650
+Wire Wire Line
+	7750 2650 7750 2000
+Connection ~ 5800 2650
+Wire Wire Line
+	9500 2650 9500 2000
+Connection ~ 7750 2650
+Wire Wire Line
+	3950 4650 3950 4950
+Wire Wire Line
+	2900 4950 9600 4950
+Wire Wire Line
+	2900 4950 2900 2650
+Connection ~ 2900 2650
+Wire Wire Line
+	5800 4950 5800 4650
+Connection ~ 3950 4950
+Wire Wire Line
+	7800 4950 7800 4650
+Connection ~ 5800 4950
+Wire Wire Line
+	9600 4950 9600 4650
+Connection ~ 7800 4950
+Wire Wire Line
+	4600 5800 5250 5800
+Wire Wire Line
+	6700 1050 6700 5550
+Wire Wire Line
+	6700 5550 4500 5550
+Wire Wire Line
+	4500 5550 4500 5900
+Wire Wire Line
+	4500 5900 5250 5900
+Connection ~ 6700 1050
+Wire Wire Line
+	8650 1050 8650 5450
+Wire Wire Line
+	8650 5450 4400 5450
+Wire Wire Line
+	4400 5450 4400 6000
+Wire Wire Line
+	4400 6000 5250 6000
+Connection ~ 8650 1050
+Wire Wire Line
+	10750 5350 4300 5350
+Wire Wire Line
+	4300 5350 4300 6100
+Wire Wire Line
+	4300 6100 5250 6100
+Connection ~ 10750 3300
+Wire Wire Line
+	10550 3700 10550 5200
+Wire Wire Line
+	10550 5200 4150 5200
+Wire Wire Line
+	4150 5200 4150 6200
+Wire Wire Line
+	4150 6200 5250 6200
+Connection ~ 10350 3700
+Wire Wire Line
+	8550 5100 4000 5100
+Wire Wire Line
+	4000 5100 4000 6300
+Wire Wire Line
+	4000 6300 5250 6300
+Connection ~ 8550 3700
+Wire Wire Line
+	6550 5050 3850 5050
+Wire Wire Line
+	3850 5050 3850 6400
+Wire Wire Line
+	3850 6400 5250 6400
+Connection ~ 6550 3700
+Wire Wire Line
+	3700 5000 4650 5000
+Wire Wire Line
+	3700 5000 3700 6500
+Wire Wire Line
+	3700 6500 5250 6500
+Wire Wire Line
+	6400 5800 6500 5800
+Wire Wire Line
+	6500 5800 6500 5600
+Wire Wire Line
+	6550 5900 6400 5900
+Wire Wire Line
+	6550 5650 6550 5900
+Wire Wire Line
+	6600 6000 6400 6000
+Wire Wire Line
+	6600 5700 6600 6000
+Wire Wire Line
+	6400 6200 6750 6200
+Wire Wire Line
+	6750 6200 6750 6250
+Wire Wire Line
+	6400 6300 6700 6300
+Wire Wire Line
+	6700 6300 6700 6350
+Wire Wire Line
+	6400 6400 6650 6400
+Wire Wire Line
+	6400 6500 6550 6500
+Wire Wire Line
+	5250 2100 5250 1700
+Wire Wire Line
+	2700 2100 8950 2100
+Connection ~ 2900 1700
+Wire Wire Line
+	7200 2100 7200 1700
+Connection ~ 5250 2100
+Wire Wire Line
+	8950 2100 8950 1700
+Connection ~ 7200 2100
+Wire Wire Line
+	2700 4350 3400 4350
+Wire Wire Line
+	2700 4350 2700 2100
+Connection ~ 2900 2100
+Wire Wire Line
+	5250 4350 5250 4800
+Wire Wire Line
+	3150 4800 9050 4800
+Wire Wire Line
+	3150 4800 3150 4350
+Connection ~ 3150 4350
+Wire Wire Line
+	7250 4800 7250 4350
+Connection ~ 5250 4800
+Wire Wire Line
+	9050 4800 9050 4350
+Connection ~ 7250 4800
+Wire Wire Line
+	2900 1700 3400 1700
+Wire Wire Line
+	1100 1700 1750 1700
+Wire Wire Line
+	1900 2650 1900 3150
+Wire Wire Line
+	6500 5600 6900 5600
+Wire Wire Line
+	6900 5600 6900 5850
+Wire Wire Line
+	6550 5650 6850 5650
+Wire Wire Line
+	6850 5650 6850 5900
+Wire Wire Line
+	6600 5700 6800 5700
+Wire Wire Line
+	6800 5700 6800 5950
+Wire Wire Line
+	6400 6100 6650 6100
+Wire Wire Line
+	6650 6100 6650 5900
+Wire Wire Line
+	6650 5900 6750 5900
+Wire Wire Line
+	6750 5900 6750 6000
+Wire Wire Line
+	6750 6250 6800 6250
+Wire Wire Line
+	6700 6350 6850 6350
+Wire Wire Line
+	4500 3700 4650 3700
+Wire Wire Line
+	4650 3700 4650 5000
+Wire Wire Line
+	4850 1050 4850 5700
+Wire Wire Line
+	4850 5700 4600 5700
+Wire Wire Line
+	4600 5700 4600 5800
+Connection ~ 4850 1050
+$Comp
+L adc_bridge_1 U3
+U 1 1 692A81B7
+P 2150 1050
+F 0 "U3" H 2150 1050 60  0000 C CNN
+F 1 "adc_bridge_1" H 2150 1200 60  0000 C CNN
+F 2 "" H 2150 1050 60  0000 C CNN
+F 3 "" H 2150 1050 60  0000 C CNN
+	1    2150 1050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2700 1000 3300 1000
+Wire Wire Line
+	3300 1000 3300 1050
+$Comp
+L d_inverter U4
+U 1 1 692A81B8
+P 2200 3150
+F 0 "U4" H 2200 3050 60  0000 C CNN
+F 1 "d_inverter" H 2200 3300 60  0000 C CNN
+F 2 "" H 2250 3100 60  0000 C CNN
+F 3 "" H 2250 3100 60  0000 C CNN
+	1    2200 3150
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2500 3150 2650 3150
+Wire Wire Line
+	2650 3150 2650 3950
+Wire Wire Line
+	2650 3950 2550 3950
+Wire Wire Line
+	2900 1700 2900 2100
+$Comp
+L PORT U1
+U 2 1 692A8E04
+P 950 1000
+F 0 "U1" H 1000 1100 30  0000 C CNN
+F 1 "PORT" H 950 1000 30  0000 C CNN
+F 2 "" H 950 1000 60  0000 C CNN
+F 3 "" H 950 1000 60  0000 C CNN
+	2    950  1000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 692A8EE6
+P 850 1700
+F 0 "U1" H 900 1800 30  0000 C CNN
+F 1 "PORT" H 850 1700 30  0000 C CNN
+F 2 "" H 850 1700 60  0000 C CNN
+F 3 "" H 850 1700 60  0000 C CNN
+	1    850  1700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1200 1000 1550 1000
+$Comp
+L PORT U1
+U 3 1 692A923B
+P 950 3950
+F 0 "U1" H 1000 4050 30  0000 C CNN
+F 1 "PORT" H 950 3950 30  0000 C CNN
+F 2 "" H 950 3950 60  0000 C CNN
+F 3 "" H 950 3950 60  0000 C CNN
+	3    950  3950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1200 3950 1400 3950
+Wire Wire Line
+	6650 6400 6650 6450
+Wire Wire Line
+	6650 6450 6900 6450
+Wire Wire Line
+	6550 6500 6550 6550
+Wire Wire Line
+	6550 6550 6950 6550
+Wire Wire Line
+	6950 6550 6950 6350
+$Comp
+L PORT U1
+U 4 1 692AA014
+P 7150 5850
+F 0 "U1" H 7200 5950 30  0000 C CNN
+F 1 "PORT" H 7150 5850 30  0000 C CNN
+F 2 "" H 7150 5850 60  0000 C CNN
+F 3 "" H 7150 5850 60  0000 C CNN
+	4    7150 5850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 692AA05B
+P 7350 6000
+F 0 "U1" H 7400 6100 30  0000 C CNN
+F 1 "PORT" H 7350 6000 30  0000 C CNN
+F 2 "" H 7350 6000 60  0000 C CNN
+F 3 "" H 7350 6000 60  0000 C CNN
+	5    7350 6000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 692AA1D1
+P 7750 5850
+F 0 "U1" H 7800 5950 30  0000 C CNN
+F 1 "PORT" H 7750 5850 30  0000 C CNN
+F 2 "" H 7750 5850 60  0000 C CNN
+F 3 "" H 7750 5850 60  0000 C CNN
+	6    7750 5850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 692AA27A
+P 7850 6000
+F 0 "U1" H 7900 6100 30  0000 C CNN
+F 1 "PORT" H 7850 6000 30  0000 C CNN
+F 2 "" H 7850 6000 60  0000 C CNN
+F 3 "" H 7850 6000 60  0000 C CNN
+	7    7850 6000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 692AA2CF
+P 8250 5850
+F 0 "U1" H 8300 5950 30  0000 C CNN
+F 1 "PORT" H 8250 5850 30  0000 C CNN
+F 2 "" H 8250 5850 60  0000 C CNN
+F 3 "" H 8250 5850 60  0000 C CNN
+	8    8250 5850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 692AA5AA
+P 8300 6000
+F 0 "U1" H 8350 6100 30  0000 C CNN
+F 1 "PORT" H 8300 6000 30  0000 C CNN
+F 2 "" H 8300 6000 60  0000 C CNN
+F 3 "" H 8300 6000 60  0000 C CNN
+	9    8300 6000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 692AA5F9
+P 8700 5850
+F 0 "U1" H 8750 5950 30  0000 C CNN
+F 1 "PORT" H 8700 5850 30  0000 C CNN
+F 2 "" H 8700 5850 60  0000 C CNN
+F 3 "" H 8700 5850 60  0000 C CNN
+	10   8700 5850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 692AA660
+P 8800 6000
+F 0 "U1" H 8850 6100 30  0000 C CNN
+F 1 "PORT" H 8800 6000 30  0000 C CNN
+F 2 "" H 8800 6000 60  0000 C CNN
+F 3 "" H 8800 6000 60  0000 C CNN
+	11   8800 6000
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	6850 5900 7000 5900
+Wire Wire Line
+	7000 5900 7000 6000
+Wire Wire Line
+	7000 6000 7100 6000
+Wire Wire Line
+	6800 5950 6950 5950
+Wire Wire Line
+	6950 5950 6950 6100
+Wire Wire Line
+	6950 6100 7500 6100
+Wire Wire Line
+	7500 6100 7500 5850
+Wire Wire Line
+	6750 6000 6900 6000
+Wire Wire Line
+	6900 6000 6900 6150
+Wire Wire Line
+	6900 6150 7600 6150
+Wire Wire Line
+	7600 6150 7600 6000
+Wire Wire Line
+	6800 6250 6800 6200
+Wire Wire Line
+	6800 6200 8000 6200
+Wire Wire Line
+	8000 6200 8000 5850
+Wire Wire Line
+	6850 6350 6850 6250
+Wire Wire Line
+	6850 6250 8050 6250
+Wire Wire Line
+	8050 6250 8050 6000
+Wire Wire Line
+	6900 6450 6900 6300
+Wire Wire Line
+	6900 6300 8450 6300
+Wire Wire Line
+	8450 6300 8450 5850
+Wire Wire Line
+	6950 6350 8550 6350
+Wire Wire Line
+	8550 6350 8550 6000
+Wire Wire Line
+	9500 650  9500 750 
+Wire Wire Line
+	3650 650  9500 650 
+Wire Wire Line
+	7750 650  7750 750 
+Wire Wire Line
+	5800 750  5800 650 
+Connection ~ 7750 650 
+Wire Wire Line
+	3950 750  3950 650 
+Connection ~ 5800 650 
+$Comp
+L PORT U1
+U 12 1 692AB935
+P 3400 650
+F 0 "U1" H 3450 750 30  0000 C CNN
+F 1 "PORT" H 3400 650 30  0000 C CNN
+F 2 "" H 3400 650 60  0000 C CNN
+F 3 "" H 3400 650 60  0000 C CNN
+	12   3400 650 
+	1    0    0    -1  
+$EndComp
+Connection ~ 3950 650 
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC164/74HC164.sub b/library/SubcircuitLibrary/74HC164/74HC164.sub
new file mode 100644
index 000000000..eb208c174
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164.sub
@@ -0,0 +1,62 @@
+* Subcircuit 74HC164
+.subckt 74HC164 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc164\74hc164.cir
+* u7  net-_u10-pad7_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad8_ ? d_dff
+* u6  net-_u3-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad1_ ? d_dff
+* u8  net-_u10-pad1_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad2_ ? d_dff
+* u9  net-_u10-pad6_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad7_ ? d_dff
+* u11  net-_u10-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad3_ ? d_dff
+* u12  net-_u10-pad5_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad6_ ? d_dff
+* u13  net-_u10-pad3_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad4_ ? d_dff
+* u14  net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ d_dff
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ dac_bridge_8
+* u5  net-_u1-pad1_ net-_u11-pad2_ adc_bridge_1
+* u2  net-_u1-pad3_ net-_u2-pad2_ adc_bridge_1
+* u15  net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ d_dff
+* u3  net-_u1-pad2_ net-_u3-pad2_ adc_bridge_1
+* u4  net-_u2-pad2_ net-_u11-pad4_ d_inverter
+a1 net-_u10-pad7_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad8_ ? u7
+a2 net-_u3-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad1_ ? u6
+a3 net-_u10-pad1_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad2_ ? u8
+a4 net-_u10-pad6_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad7_ ? u9
+a5 net-_u10-pad2_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad3_ ? u11
+a6 net-_u10-pad5_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad6_ ? u12
+a7 net-_u10-pad3_ net-_u11-pad2_ net-_u1-pad12_ net-_u11-pad4_ net-_u10-pad4_ ? u13
+a8 net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ u14
+a9 [net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ net-_u10-pad8_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ] u10
+a10 [net-_u1-pad1_ ] [net-_u11-pad2_ ] u5
+a11 [net-_u1-pad3_ ] [net-_u2-pad2_ ] u2
+a12 net-_u10-pad4_ net-_u11-pad2_ vcc net-_u11-pad4_ net-_u10-pad5_ net-_u14-pad6_ u15
+a13 [net-_u1-pad2_ ] [net-_u3-pad2_ ] u3
+a14 net-_u2-pad2_ net-_u11-pad4_ u4
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u14 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_8, NgSpice Name: dac_bridge
+.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC164
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC164/74HC164_Previous_Values.xml b/library/SubcircuitLibrary/74HC164/74HC164_Previous_Values.xml
new file mode 100644
index 000000000..88df5b28a
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/74HC164_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u7><u6 name="type">d_dff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for Data Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u6><u8 name="type">d_dff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for Data Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u8><u9 name="type">d_dff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for Data Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u9><u11 name="type">d_dff<field41 name="Enter Clk Delay (default=1.0e-9)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter Reset Delay (default=1.0)" /><field44 name="Enter IC (default=0)" /><field45 name="Enter value for Data Load (default=1.0e-12)" /><field46 name="Enter value for Clk Load (default=1.0e-12)" /><field47 name="Enter value for Set Load (default=1.0e-12)" /><field48 name="Enter value for Reset Load (default=1.0e-12)" /><field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_dff<field51 name="Enter Clk Delay (default=1.0e-9)" /><field52 name="Enter Set Delay (default=1.0e-9)" /><field53 name="Enter Reset Delay (default=1.0)" /><field54 name="Enter IC (default=0)" /><field55 name="Enter value for Data Load (default=1.0e-12)" /><field56 name="Enter value for Clk Load (default=1.0e-12)" /><field57 name="Enter value for Set Load (default=1.0e-12)" /><field58 name="Enter value for Reset Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_dff<field61 name="Enter Clk Delay (default=1.0e-9)" /><field62 name="Enter Set Delay (default=1.0e-9)" /><field63 name="Enter Reset Delay (default=1.0)" /><field64 name="Enter IC (default=0)" /><field65 name="Enter value for Data Load (default=1.0e-12)" /><field66 name="Enter value for Clk Load (default=1.0e-12)" /><field67 name="Enter value for Set Load (default=1.0e-12)" /><field68 name="Enter value for Reset Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /><field70 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_dff<field71 name="Enter Clk Delay (default=1.0e-9)" /><field72 name="Enter Set Delay (default=1.0e-9)" /><field73 name="Enter Reset Delay (default=1.0)" /><field74 name="Enter IC (default=0)" /><field75 name="Enter value for Data Load (default=1.0e-12)" /><field76 name="Enter value for Clk Load (default=1.0e-12)" /><field77 name="Enter value for Set Load (default=1.0e-12)" /><field78 name="Enter value for Reset Load (default=1.0e-12)" /><field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /></u14><u10 name="type">dac_bridge<field81 name="Enter value for out_low (default=0.0)" /><field82 name="Enter value for out_high (default=5.0)" /><field83 name="Enter value for out_undef (default=0.5)" /><field84 name="Enter value for input load (default=1.0e-12)" /><field85 name="Enter the Rise Time (default=1.0e-9)" /><field86 name="Enter the Fall Time (default=1.0e-9)" /></u10><u5 name="type">adc_bridge<field87 name="Enter value for in_low (default=1.0)" /><field88 name="Enter value for in_high (default=2.0)">4</field88><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u5><u2 name="type">adc_bridge<field91 name="Enter value for in_low (default=1.0)" /><field92 name="Enter value for in_high (default=2.0)">4</field92><field93 name="Enter Rise Delay (default=1.0e-9)" /><field94 name="Enter Fall Delay (default=1.0e-9)" /></u2><u15 name="type">d_dff<field95 name="Enter Clk Delay (default=1.0e-9)" /><field96 name="Enter Set Delay (default=1.0e-9)" /><field97 name="Enter Reset Delay (default=1.0)" /><field98 name="Enter IC (default=0)" /><field99 name="Enter value for Data Load (default=1.0e-12)" /><field100 name="Enter value for Clk Load (default=1.0e-12)" /><field101 name="Enter value for Set Load (default=1.0e-12)" /><field102 name="Enter value for Reset Load (default=1.0e-12)" /><field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /></u15><u3 name="type">adc_bridge<field105 name="Enter value for in_low (default=1.0)" /><field106 name="Enter value for in_high (default=2.0)">4</field106><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC164/analysis b/library/SubcircuitLibrary/74HC164/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC164/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC174/74HC174-cache.lib b/library/SubcircuitLibrary/74HC174/74HC174-cache.lib
new file mode 100644
index 000000000..b3857f545
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174-cache.lib
@@ -0,0 +1,62 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC174/74HC174.cir b/library/SubcircuitLibrary/74HC174/74HC174.cir
new file mode 100644
index 000000000..748254a62
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174.cir
@@ -0,0 +1,13 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC174\74HC174.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/11/26 07:35:21
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_dff		
+U3  Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad7_ Net-_U1-Pad11_ Net-_U1-Pad12_ d_dff		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC174/74HC174.cir.out b/library/SubcircuitLibrary/74HC174/74HC174.cir.out
new file mode 100644
index 000000000..47e1cb4fe
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174.cir.out
@@ -0,0 +1,20 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc174\74hc174.cir
+
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad5_ net-_u1-pad6_ d_dff
+* u3  net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad7_ net-_u1-pad11_ net-_u1-pad12_ d_dff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+a1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad5_ net-_u1-pad6_ u2
+a2 net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad7_ net-_u1-pad11_ net-_u1-pad12_ u3
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u2 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC174/74HC174.pro b/library/SubcircuitLibrary/74HC174/74HC174.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC174/74HC174.sch b/library/SubcircuitLibrary/74HC174/74HC174.sch
new file mode 100644
index 000000000..73fe02e7c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174.sch
@@ -0,0 +1,240 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U2
+U 1 1 696302AE
+P 5750 1950
+F 0 "U2" H 5750 1950 60  0000 C CNN
+F 1 "d_dff" H 5750 2100 60  0000 C CNN
+F 2 "" H 5750 1950 60  0000 C CNN
+F 3 "" H 5750 1950 60  0000 C CNN
+	1    5750 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U3
+U 1 1 6963030C
+P 5750 3500
+F 0 "U3" H 5750 3500 60  0000 C CNN
+F 1 "d_dff" H 5750 3650 60  0000 C CNN
+F 2 "" H 5750 3500 60  0000 C CNN
+F 3 "" H 5750 3500 60  0000 C CNN
+	1    5750 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 69630365
+P 4750 2650
+F 0 "U1" H 4800 2750 30  0000 C CNN
+F 1 "PORT" H 4750 2650 30  0000 C CNN
+F 2 "" H 4750 2650 60  0000 C CNN
+F 3 "" H 4750 2650 60  0000 C CNN
+	1    4750 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 696303A5
+P 4750 1600
+F 0 "U1" H 4800 1700 30  0000 C CNN
+F 1 "PORT" H 4750 1600 30  0000 C CNN
+F 2 "" H 4750 1600 60  0000 C CNN
+F 3 "" H 4750 1600 60  0000 C CNN
+	2    4750 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 696303D0
+P 4750 2250
+F 0 "U1" H 4800 2350 30  0000 C CNN
+F 1 "PORT" H 4750 2250 30  0000 C CNN
+F 2 "" H 4750 2250 60  0000 C CNN
+F 3 "" H 4750 2250 60  0000 C CNN
+	3    4750 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 696303F3
+P 4750 1150
+F 0 "U1" H 4800 1250 30  0000 C CNN
+F 1 "PORT" H 4750 1150 30  0000 C CNN
+F 2 "" H 4750 1150 60  0000 C CNN
+F 3 "" H 4750 1150 60  0000 C CNN
+	4    4750 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6963041C
+P 6800 1600
+F 0 "U1" H 6850 1700 30  0000 C CNN
+F 1 "PORT" H 6800 1600 30  0000 C CNN
+F 2 "" H 6800 1600 60  0000 C CNN
+F 3 "" H 6800 1600 60  0000 C CNN
+	5    6800 1600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 69630461
+P 6800 2250
+F 0 "U1" H 6850 2350 30  0000 C CNN
+F 1 "PORT" H 6800 2250 30  0000 C CNN
+F 2 "" H 6800 2250 60  0000 C CNN
+F 3 "" H 6800 2250 60  0000 C CNN
+	6    6800 2250
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 69630490
+P 4750 4300
+F 0 "U1" H 4800 4400 30  0000 C CNN
+F 1 "PORT" H 4750 4300 30  0000 C CNN
+F 2 "" H 4750 4300 60  0000 C CNN
+F 3 "" H 4750 4300 60  0000 C CNN
+	7    4750 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 696304DD
+P 4750 3150
+F 0 "U1" H 4800 3250 30  0000 C CNN
+F 1 "PORT" H 4750 3150 30  0000 C CNN
+F 2 "" H 4750 3150 60  0000 C CNN
+F 3 "" H 4750 3150 60  0000 C CNN
+	8    4750 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6963050A
+P 4750 3800
+F 0 "U1" H 4800 3900 30  0000 C CNN
+F 1 "PORT" H 4750 3800 30  0000 C CNN
+F 2 "" H 4750 3800 60  0000 C CNN
+F 3 "" H 4750 3800 60  0000 C CNN
+	9    4750 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6963054F
+P 4750 2850
+F 0 "U1" H 4800 2950 30  0000 C CNN
+F 1 "PORT" H 4750 2850 30  0000 C CNN
+F 2 "" H 4750 2850 60  0000 C CNN
+F 3 "" H 4750 2850 60  0000 C CNN
+	10   4750 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 69630584
+P 6800 3150
+F 0 "U1" H 6850 3250 30  0000 C CNN
+F 1 "PORT" H 6800 3150 30  0000 C CNN
+F 2 "" H 6800 3150 60  0000 C CNN
+F 3 "" H 6800 3150 60  0000 C CNN
+	11   6800 3150
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 696305B9
+P 6800 3800
+F 0 "U1" H 6850 3900 30  0000 C CNN
+F 1 "PORT" H 6800 3800 30  0000 C CNN
+F 2 "" H 6800 3800 60  0000 C CNN
+F 3 "" H 6800 3800 60  0000 C CNN
+	12   6800 3800
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5750 2650 5750 2550
+Wire Wire Line
+	5000 2650 5750 2650
+Wire Wire Line
+	5000 2250 5200 2250
+Wire Wire Line
+	5000 1600 5200 1600
+Wire Wire Line
+	5000 1150 5750 1150
+Wire Wire Line
+	5750 1150 5750 1300
+Wire Wire Line
+	6300 1600 6550 1600
+Wire Wire Line
+	6300 2250 6550 2250
+Wire Wire Line
+	5000 3150 5200 3150
+Wire Wire Line
+	6300 3150 6550 3150
+Wire Wire Line
+	6550 3800 6300 3800
+Wire Wire Line
+	5000 3800 5200 3800
+Wire Wire Line
+	5750 4100 5750 4300
+Wire Wire Line
+	5750 4300 5000 4300
+Wire Wire Line
+	5000 2850 5750 2850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC174/74HC174.sub b/library/SubcircuitLibrary/74HC174/74HC174.sub
new file mode 100644
index 000000000..316c32a64
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174.sub
@@ -0,0 +1,14 @@
+* Subcircuit 74HC174
+.subckt 74HC174 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc174\74hc174.cir
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad5_ net-_u1-pad6_ d_dff
+* u3  net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad7_ net-_u1-pad11_ net-_u1-pad12_ d_dff
+a1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad5_ net-_u1-pad6_ u2
+a2 net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad7_ net-_u1-pad11_ net-_u1-pad12_ u3
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u2 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC174
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC174/74HC174_Previous_Values.xml b/library/SubcircuitLibrary/74HC174/74HC174_Previous_Values.xml
new file mode 100644
index 000000000..019b95b22
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/74HC174_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_dff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for Data Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC174/analysis b/library/SubcircuitLibrary/74HC174/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC174/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC273/74HC273-cache.lib b/library/SubcircuitLibrary/74HC273/74HC273-cache.lib
new file mode 100644
index 000000000..657dae2fe
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273-cache.lib
@@ -0,0 +1,120 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC273/74HC273.cir b/library/SubcircuitLibrary/74HC273/74HC273.cir
new file mode 100644
index 000000000..ba2dec41d
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273.cir
@@ -0,0 +1,22 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC273\74HC273.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/06/25 11:48:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5  Net-_U5-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad13_ Net-_U1-Pad11_ d_dff		
+U6  Net-_U6-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad16_ ? d_dff		
+U9  Net-_U8-Pad11_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad18_ ? d_dff		
+U11  Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad19_ ? d_dff		
+U4  Net-_U4-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad12_ ? d_dff		
+U7  Net-_U7-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad15_ ? d_dff		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad17_ ? d_dff		
+U12  Net-_U12-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U1-Pad20_ ? d_dff		
+U8  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad14_ Net-_U5-Pad1_ Net-_U6-Pad1_ Net-_U8-Pad11_ Net-_U11-Pad1_ Net-_U4-Pad1_ Net-_U7-Pad1_ Net-_U10-Pad1_ Net-_U12-Pad1_ adc_bridge_8		
+U2  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U2-Pad4_ adc_bridge_2		
+U3  Net-_U2-Pad4_ Net-_U10-Pad4_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC273/74HC273.cir.out b/library/SubcircuitLibrary/74HC273/74HC273.cir.out
new file mode 100644
index 000000000..7fbaf0a74
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273.cir.out
@@ -0,0 +1,56 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc273\74hc273.cir
+
+* u5  net-_u5-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad13_ net-_u1-pad11_ d_dff
+* u6  net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad16_ ? d_dff
+* u9  net-_u8-pad11_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad18_ ? d_dff
+* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad19_ ? d_dff
+* u4  net-_u4-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad12_ ? d_dff
+* u7  net-_u7-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad15_ ? d_dff
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad17_ ? d_dff
+* u12  net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad20_ ? d_dff
+* u8  net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad14_ net-_u5-pad1_ net-_u6-pad1_ net-_u8-pad11_ net-_u11-pad1_ net-_u4-pad1_ net-_u7-pad1_ net-_u10-pad1_ net-_u12-pad1_ adc_bridge_8
+* u2  net-_u1-pad1_ net-_u1-pad4_ net-_u10-pad2_ net-_u2-pad4_ adc_bridge_2
+* u3  net-_u2-pad4_ net-_u10-pad4_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ port
+a1 net-_u5-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad13_ net-_u1-pad11_ u5
+a2 net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad16_ ? u6
+a3 net-_u8-pad11_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad18_ ? u9
+a4 net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad19_ ? u11
+a5 net-_u4-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad12_ ? u4
+a6 net-_u7-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad15_ ? u7
+a7 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad17_ ? u10
+a8 net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad20_ ? u12
+a9 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad14_ ] [net-_u5-pad1_ net-_u6-pad1_ net-_u8-pad11_ net-_u11-pad1_ net-_u4-pad1_ net-_u7-pad1_ net-_u10-pad1_ net-_u12-pad1_ ] u8
+a10 [net-_u1-pad1_ net-_u1-pad4_ ] [net-_u10-pad2_ net-_u2-pad4_ ] u2
+a11 net-_u2-pad4_ net-_u10-pad4_ u3
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC273/74HC273.pro b/library/SubcircuitLibrary/74HC273/74HC273.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC273/74HC273.sch b/library/SubcircuitLibrary/74HC273/74HC273.sch
new file mode 100644
index 000000000..dc0b4d315
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273.sch
@@ -0,0 +1,651 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74HC273-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U5
+U 1 1 6933C8A3
+P 3300 1850
+F 0 "U5" H 3300 1850 60  0000 C CNN
+F 1 "d_dff" H 3300 2000 60  0000 C CNN
+F 2 "" H 3300 1850 60  0000 C CNN
+F 3 "" H 3300 1850 60  0000 C CNN
+	1    3300 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U6
+U 1 1 6933C8A4
+P 5200 1850
+F 0 "U6" H 5200 1850 60  0000 C CNN
+F 1 "d_dff" H 5200 2000 60  0000 C CNN
+F 2 "" H 5200 1850 60  0000 C CNN
+F 3 "" H 5200 1850 60  0000 C CNN
+	1    5200 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U9
+U 1 1 6933C8A5
+P 7200 1850
+F 0 "U9" H 7200 1850 60  0000 C CNN
+F 1 "d_dff" H 7200 2000 60  0000 C CNN
+F 2 "" H 7200 1850 60  0000 C CNN
+F 3 "" H 7200 1850 60  0000 C CNN
+	1    7200 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U11
+U 1 1 6933C8A6
+P 9300 1850
+F 0 "U11" H 9300 1850 60  0000 C CNN
+F 1 "d_dff" H 9300 2000 60  0000 C CNN
+F 2 "" H 9300 1850 60  0000 C CNN
+F 3 "" H 9300 1850 60  0000 C CNN
+	1    9300 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U4
+U 1 1 6933C8A7
+P 3250 4200
+F 0 "U4" H 3250 4200 60  0000 C CNN
+F 1 "d_dff" H 3250 4350 60  0000 C CNN
+F 2 "" H 3250 4200 60  0000 C CNN
+F 3 "" H 3250 4200 60  0000 C CNN
+	1    3250 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U7
+U 1 1 6933C8A8
+P 5200 4200
+F 0 "U7" H 5200 4200 60  0000 C CNN
+F 1 "d_dff" H 5200 4350 60  0000 C CNN
+F 2 "" H 5200 4200 60  0000 C CNN
+F 3 "" H 5200 4200 60  0000 C CNN
+	1    5200 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U10
+U 1 1 6933C8A9
+P 7200 4200
+F 0 "U10" H 7200 4200 60  0000 C CNN
+F 1 "d_dff" H 7200 4350 60  0000 C CNN
+F 2 "" H 7200 4200 60  0000 C CNN
+F 3 "" H 7200 4200 60  0000 C CNN
+	1    7200 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U12
+U 1 1 6933C8AA
+P 9350 4250
+F 0 "U12" H 9350 4250 60  0000 C CNN
+F 1 "d_dff" H 9350 4400 60  0000 C CNN
+F 2 "" H 9350 4250 60  0000 C CNN
+F 3 "" H 9350 4250 60  0000 C CNN
+	1    9350 4250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4650 2150 4450 2150
+Wire Wire Line
+	4450 2750 4450 2150
+Wire Wire Line
+	2450 2750 8450 2750
+Wire Wire Line
+	2600 1750 2600 2750
+Wire Wire Line
+	2600 2150 2750 2150
+Wire Wire Line
+	6650 2150 6450 2150
+Wire Wire Line
+	6450 2150 6450 2750
+Connection ~ 4450 2750
+Wire Wire Line
+	8750 2150 8450 2150
+Wire Wire Line
+	8450 2150 8450 2750
+Connection ~ 6450 2750
+Wire Wire Line
+	4650 4500 4400 4500
+Wire Wire Line
+	4400 4500 4400 5150
+Wire Wire Line
+	2600 5150 8500 5150
+Wire Wire Line
+	2600 5150 2600 4500
+Wire Wire Line
+	2450 4500 2700 4500
+Wire Wire Line
+	6650 4500 6400 4500
+Wire Wire Line
+	6400 4500 6400 5150
+Connection ~ 4400 5150
+Wire Wire Line
+	8800 4550 8500 4550
+Wire Wire Line
+	8500 4550 8500 5150
+Connection ~ 6400 5150
+Wire Wire Line
+	3300 2550 3300 2450
+Wire Wire Line
+	2050 2550 9300 2550
+Wire Wire Line
+	5200 2550 5200 2450
+Wire Wire Line
+	7200 2550 7200 2450
+Connection ~ 5200 2550
+Wire Wire Line
+	9300 2550 9300 2450
+Connection ~ 7200 2550
+Wire Wire Line
+	3250 4800 3250 4900
+Wire Wire Line
+	2050 4900 9350 4900
+Wire Wire Line
+	5200 4900 5200 4800
+Wire Wire Line
+	7200 4900 7200 4800
+Connection ~ 5200 4900
+Wire Wire Line
+	9350 4900 9350 4850
+Connection ~ 7200 4900
+Wire Wire Line
+	3300 1200 3300 1150
+Wire Wire Line
+	3100 1150 10100 1150
+Wire Wire Line
+	5200 1150 5200 1200
+Wire Wire Line
+	7200 1150 7200 1200
+Connection ~ 5200 1150
+Wire Wire Line
+	9300 1150 9300 1200
+Connection ~ 7200 1150
+Wire Wire Line
+	3250 3550 3250 3450
+Wire Wire Line
+	3250 3450 10100 3450
+Wire Wire Line
+	5200 3450 5200 3550
+Wire Wire Line
+	7200 3450 7200 3550
+Connection ~ 5200 3450
+Wire Wire Line
+	9350 3450 9350 3600
+Connection ~ 7200 3450
+Wire Wire Line
+	2450 4500 2450 2750
+Connection ~ 2600 2750
+Connection ~ 2600 4500
+Wire Wire Line
+	2050 4900 2050 2550
+Connection ~ 3300 2550
+Connection ~ 3250 4900
+Wire Wire Line
+	10100 3450 10100 1150
+Connection ~ 9350 3450
+Connection ~ 9300 1150
+$Comp
+L adc_bridge_8 U8
+U 1 1 6933C8AB
+P 5650 5450
+F 0 "U8" H 5650 5450 60  0000 C CNN
+F 1 "adc_bridge_8" H 5650 5600 60  0000 C CNN
+F 2 "" H 5650 5450 60  0000 C CNN
+F 3 "" H 5650 5450 60  0000 C CNN
+	1    5650 5450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	900  5400 5050 5400
+Wire Wire Line
+	1500 5500 5050 5500
+Wire Wire Line
+	2050 5600 5050 5600
+Wire Wire Line
+	2600 5700 5050 5700
+Wire Wire Line
+	3150 5800 5050 5800
+Wire Wire Line
+	3700 5900 5050 5900
+Wire Wire Line
+	4250 6000 5050 6000
+Wire Wire Line
+	4750 6100 5050 6100
+Wire Wire Line
+	6200 6100 8400 6100
+Wire Wire Line
+	8400 6100 8400 3900
+Wire Wire Line
+	8400 3900 8800 3900
+Wire Wire Line
+	6200 6000 8250 6000
+Wire Wire Line
+	8250 6000 8250 3300
+Wire Wire Line
+	8250 3300 6500 3300
+Wire Wire Line
+	6500 3300 6500 3850
+Wire Wire Line
+	6500 3850 6650 3850
+Wire Wire Line
+	8150 5900 6200 5900
+Wire Wire Line
+	8150 3250 8150 5900
+Wire Wire Line
+	8150 3250 4500 3250
+Wire Wire Line
+	4500 3250 4500 3850
+Wire Wire Line
+	4500 3850 4650 3850
+Wire Wire Line
+	6200 5800 8050 5800
+Wire Wire Line
+	8050 5800 8050 3150
+Wire Wire Line
+	8050 3150 2550 3150
+Wire Wire Line
+	2550 3150 2550 3850
+Wire Wire Line
+	2550 3850 2700 3850
+Wire Wire Line
+	6200 5700 10350 5700
+Wire Wire Line
+	10350 5700 10350 1000
+Wire Wire Line
+	10350 1000 8500 1000
+Wire Wire Line
+	8500 1000 8500 1500
+Wire Wire Line
+	8500 1500 8750 1500
+Wire Wire Line
+	6200 5600 10450 5600
+Wire Wire Line
+	10450 5600 10450 950 
+Wire Wire Line
+	10450 950  6450 950 
+Wire Wire Line
+	6450 950  6450 1500
+Wire Wire Line
+	6450 1500 6650 1500
+Wire Wire Line
+	6200 5500 10550 5500
+Wire Wire Line
+	10550 5500 10550 850 
+Wire Wire Line
+	10550 850  4450 850 
+Wire Wire Line
+	4450 850  4450 1500
+Wire Wire Line
+	4450 1500 4650 1500
+Wire Wire Line
+	6200 5400 10650 5400
+Wire Wire Line
+	10650 5400 10650 750 
+Wire Wire Line
+	10650 750  2550 750 
+Wire Wire Line
+	2550 750  2550 1500
+Wire Wire Line
+	2550 1500 2750 1500
+Connection ~ 3300 1150
+$Comp
+L adc_bridge_2 U2
+U 1 1 6933C8B6
+P 1800 1800
+F 0 "U2" H 1800 1800 60  0000 C CNN
+F 1 "adc_bridge_2" H 1800 1950 60  0000 C CNN
+F 2 "" H 1800 1800 60  0000 C CNN
+F 3 "" H 1800 1800 60  0000 C CNN
+	1    1800 1800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	900  2550 900  1750
+Wire Wire Line
+	900  1750 1200 1750
+Wire Wire Line
+	1200 1850 1050 1850
+Wire Wire Line
+	1050 1850 1050 2350
+Wire Wire Line
+	1050 2350 1750 2350
+Wire Wire Line
+	1750 2350 1750 2550
+Wire Wire Line
+	2350 1750 2600 1750
+Connection ~ 2600 2150
+Wire Wire Line
+	2350 1850 2450 1850
+Connection ~ 2450 2550
+Wire Wire Line
+	3850 1500 4150 1500
+Wire Wire Line
+	5750 1500 6150 1500
+Wire Wire Line
+	7750 1500 8200 1500
+Wire Wire Line
+	9900 3900 10150 3900
+Wire Wire Line
+	5750 3850 6050 3850
+Wire Wire Line
+	3800 3850 4050 3850
+Wire Wire Line
+	4150 1500 4150 1700
+Wire Wire Line
+	4150 1700 4200 1700
+Wire Wire Line
+	6150 1500 6150 1750
+Wire Wire Line
+	6150 1750 6300 1750
+Wire Wire Line
+	8200 1500 8200 1800
+Wire Wire Line
+	8200 1800 8300 1800
+Wire Wire Line
+	4050 3850 4050 4150
+Wire Wire Line
+	4050 4150 4100 4150
+Wire Wire Line
+	6050 3850 6050 4100
+Wire Wire Line
+	6050 4100 6150 4100
+Wire Wire Line
+	10150 3900 10150 4100
+$Comp
+L d_inverter U3
+U 1 1 6933C8C2
+P 2450 2150
+F 0 "U3" H 2450 2050 60  0000 C CNN
+F 1 "d_inverter" H 2450 2300 60  0000 C CNN
+F 2 "" H 2500 2100 60  0000 C CNN
+F 3 "" H 2500 2100 60  0000 C CNN
+	1    2450 2150
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	2450 2450 2450 2550
+$Comp
+L PORT U1
+U 4 1 6933D2AD
+P 1500 2550
+F 0 "U1" H 1550 2650 30  0000 C CNN
+F 1 "PORT" H 1500 2550 30  0000 C CNN
+F 2 "" H 1500 2550 60  0000 C CNN
+F 3 "" H 1500 2550 60  0000 C CNN
+	4    1500 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6933D4F6
+P 600 2550
+F 0 "U1" H 650 2650 30  0000 C CNN
+F 1 "PORT" H 600 2550 30  0000 C CNN
+F 2 "" H 600 2550 60  0000 C CNN
+F 3 "" H 600 2550 60  0000 C CNN
+	1    600  2550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	850  2550 900  2550
+$Comp
+L PORT U1
+U 7 1 6933D65B
+P 2850 1150
+F 0 "U1" H 2900 1250 30  0000 C CNN
+F 1 "PORT" H 2850 1150 30  0000 C CNN
+F 2 "" H 2850 1150 60  0000 C CNN
+F 3 "" H 2850 1150 60  0000 C CNN
+	7    2850 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6933D7C7
+P 650 5400
+F 0 "U1" H 700 5500 30  0000 C CNN
+F 1 "PORT" H 650 5400 30  0000 C CNN
+F 2 "" H 650 5400 60  0000 C CNN
+F 3 "" H 650 5400 60  0000 C CNN
+	2    650  5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6933D842
+P 1250 5500
+F 0 "U1" H 1300 5600 30  0000 C CNN
+F 1 "PORT" H 1250 5500 30  0000 C CNN
+F 2 "" H 1250 5500 60  0000 C CNN
+F 3 "" H 1250 5500 60  0000 C CNN
+	3    1250 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6933D89F
+P 1800 5600
+F 0 "U1" H 1850 5700 30  0000 C CNN
+F 1 "PORT" H 1800 5600 30  0000 C CNN
+F 2 "" H 1800 5600 60  0000 C CNN
+F 3 "" H 1800 5600 60  0000 C CNN
+	5    1800 5600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6933D94C
+P 2350 5700
+F 0 "U1" H 2400 5800 30  0000 C CNN
+F 1 "PORT" H 2350 5700 30  0000 C CNN
+F 2 "" H 2350 5700 60  0000 C CNN
+F 3 "" H 2350 5700 60  0000 C CNN
+	6    2350 5700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6933D991
+P 2900 5800
+F 0 "U1" H 2950 5900 30  0000 C CNN
+F 1 "PORT" H 2900 5800 30  0000 C CNN
+F 2 "" H 2900 5800 60  0000 C CNN
+F 3 "" H 2900 5800 60  0000 C CNN
+	8    2900 5800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6933D9F6
+P 3450 5900
+F 0 "U1" H 3500 6000 30  0000 C CNN
+F 1 "PORT" H 3450 5900 30  0000 C CNN
+F 2 "" H 3450 5900 60  0000 C CNN
+F 3 "" H 3450 5900 60  0000 C CNN
+	9    3450 5900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6933DA57
+P 4000 6000
+F 0 "U1" H 4050 6100 30  0000 C CNN
+F 1 "PORT" H 4000 6000 30  0000 C CNN
+F 2 "" H 4000 6000 60  0000 C CNN
+F 3 "" H 4000 6000 60  0000 C CNN
+	10   4000 6000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6933DADD
+P 4500 6100
+F 0 "U1" H 4550 6200 30  0000 C CNN
+F 1 "PORT" H 4500 6100 30  0000 C CNN
+F 2 "" H 4500 6100 60  0000 C CNN
+F 3 "" H 4500 6100 60  0000 C CNN
+	14   4500 6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6933DCAE
+P 4450 1700
+F 0 "U1" H 4500 1800 30  0000 C CNN
+F 1 "PORT" H 4450 1700 30  0000 C CNN
+F 2 "" H 4450 1700 60  0000 C CNN
+F 3 "" H 4450 1700 60  0000 C CNN
+	13   4450 1700
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6933DE32
+P 6550 1750
+F 0 "U1" H 6600 1850 30  0000 C CNN
+F 1 "PORT" H 6550 1750 30  0000 C CNN
+F 2 "" H 6550 1750 60  0000 C CNN
+F 3 "" H 6550 1750 60  0000 C CNN
+	16   6550 1750
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 18 1 6933E083
+P 8550 1800
+F 0 "U1" H 8600 1900 30  0000 C CNN
+F 1 "PORT" H 8550 1800 30  0000 C CNN
+F 2 "" H 8550 1800 60  0000 C CNN
+F 3 "" H 8550 1800 60  0000 C CNN
+	18   8550 1800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 19 1 6933E259
+P 10000 1750
+F 0 "U1" H 10050 1850 30  0000 C CNN
+F 1 "PORT" H 10000 1750 30  0000 C CNN
+F 2 "" H 10000 1750 60  0000 C CNN
+F 3 "" H 10000 1750 60  0000 C CNN
+	19   10000 1750
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	9850 1500 10000 1500
+$Comp
+L PORT U1
+U 12 1 6933E4E0
+P 4350 4150
+F 0 "U1" H 4400 4250 30  0000 C CNN
+F 1 "PORT" H 4350 4150 30  0000 C CNN
+F 2 "" H 4350 4150 60  0000 C CNN
+F 3 "" H 4350 4150 60  0000 C CNN
+	12   4350 4150
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6933E5C8
+P 6400 4100
+F 0 "U1" H 6450 4200 30  0000 C CNN
+F 1 "PORT" H 6400 4100 30  0000 C CNN
+F 2 "" H 6400 4100 60  0000 C CNN
+F 3 "" H 6400 4100 60  0000 C CNN
+	15   6400 4100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 17 1 6933E6B7
+P 7900 4100
+F 0 "U1" H 7950 4200 30  0000 C CNN
+F 1 "PORT" H 7900 4100 30  0000 C CNN
+F 2 "" H 7900 4100 60  0000 C CNN
+F 3 "" H 7900 4100 60  0000 C CNN
+	17   7900 4100
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	7750 3850 7900 3850
+$Comp
+L PORT U1
+U 20 1 6933E8E5
+P 10150 4350
+F 0 "U1" H 10200 4450 30  0000 C CNN
+F 1 "PORT" H 10150 4350 30  0000 C CNN
+F 2 "" H 10150 4350 60  0000 C CNN
+F 3 "" H 10150 4350 60  0000 C CNN
+	20   10150 4350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6933EB6A
+P 4100 2150
+F 0 "U1" H 4150 2250 30  0000 C CNN
+F 1 "PORT" H 4100 2150 30  0000 C CNN
+F 2 "" H 4100 2150 60  0000 C CNN
+F 3 "" H 4100 2150 60  0000 C CNN
+	11   4100 2150
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC273/74HC273.sub b/library/SubcircuitLibrary/74HC273/74HC273.sub
new file mode 100644
index 000000000..c66d3c02c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273.sub
@@ -0,0 +1,50 @@
+* Subcircuit 74HC273
+.subckt 74HC273 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc273\74hc273.cir
+* u5  net-_u5-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad13_ net-_u1-pad11_ d_dff
+* u6  net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad16_ ? d_dff
+* u9  net-_u8-pad11_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad18_ ? d_dff
+* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad19_ ? d_dff
+* u4  net-_u4-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad12_ ? d_dff
+* u7  net-_u7-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad15_ ? d_dff
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad17_ ? d_dff
+* u12  net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad20_ ? d_dff
+* u8  net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad14_ net-_u5-pad1_ net-_u6-pad1_ net-_u8-pad11_ net-_u11-pad1_ net-_u4-pad1_ net-_u7-pad1_ net-_u10-pad1_ net-_u12-pad1_ adc_bridge_8
+* u2  net-_u1-pad1_ net-_u1-pad4_ net-_u10-pad2_ net-_u2-pad4_ adc_bridge_2
+* u3  net-_u2-pad4_ net-_u10-pad4_ d_inverter
+a1 net-_u5-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad13_ net-_u1-pad11_ u5
+a2 net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad16_ ? u6
+a3 net-_u8-pad11_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad18_ ? u9
+a4 net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad19_ ? u11
+a5 net-_u4-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad12_ ? u4
+a6 net-_u7-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad15_ ? u7
+a7 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad17_ ? u10
+a8 net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u1-pad20_ ? u12
+a9 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad14_ ] [net-_u5-pad1_ net-_u6-pad1_ net-_u8-pad11_ net-_u11-pad1_ net-_u4-pad1_ net-_u7-pad1_ net-_u10-pad1_ net-_u12-pad1_ ] u8
+a10 [net-_u1-pad1_ net-_u1-pad4_ ] [net-_u10-pad2_ net-_u2-pad4_ ] u2
+a11 net-_u2-pad4_ net-_u10-pad4_ u3
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC273
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC273/74HC273_Previous_Values.xml b/library/SubcircuitLibrary/74HC273/74HC273_Previous_Values.xml
new file mode 100644
index 000000000..1f2383389
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/74HC273_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u5 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u5><u6 name="type">d_dff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for Data Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u6><u9 name="type">d_dff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for Data Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u9><u11 name="type">d_dff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for Data Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u11><u4 name="type">d_dff<field41 name="Enter Clk Delay (default=1.0e-9)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter Reset Delay (default=1.0)" /><field44 name="Enter IC (default=0)" /><field45 name="Enter value for Data Load (default=1.0e-12)" /><field46 name="Enter value for Clk Load (default=1.0e-12)" /><field47 name="Enter value for Set Load (default=1.0e-12)" /><field48 name="Enter value for Reset Load (default=1.0e-12)" /><field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /></u4><u7 name="type">d_dff<field51 name="Enter Clk Delay (default=1.0e-9)" /><field52 name="Enter Set Delay (default=1.0e-9)" /><field53 name="Enter Reset Delay (default=1.0)" /><field54 name="Enter IC (default=0)" /><field55 name="Enter value for Data Load (default=1.0e-12)" /><field56 name="Enter value for Clk Load (default=1.0e-12)" /><field57 name="Enter value for Set Load (default=1.0e-12)" /><field58 name="Enter value for Reset Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u7><u10 name="type">d_dff<field61 name="Enter Clk Delay (default=1.0e-9)" /><field62 name="Enter Set Delay (default=1.0e-9)" /><field63 name="Enter Reset Delay (default=1.0)" /><field64 name="Enter IC (default=0)" /><field65 name="Enter value for Data Load (default=1.0e-12)" /><field66 name="Enter value for Clk Load (default=1.0e-12)" /><field67 name="Enter value for Set Load (default=1.0e-12)" /><field68 name="Enter value for Reset Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /><field70 name="Enter Fall Delay (default=1.0e-9)" /></u10><u12 name="type">d_dff<field71 name="Enter Clk Delay (default=1.0e-9)" /><field72 name="Enter Set Delay (default=1.0e-9)" /><field73 name="Enter Reset Delay (default=1.0)" /><field74 name="Enter IC (default=0)" /><field75 name="Enter value for Data Load (default=1.0e-12)" /><field76 name="Enter value for Clk Load (default=1.0e-12)" /><field77 name="Enter value for Set Load (default=1.0e-12)" /><field78 name="Enter value for Reset Load (default=1.0e-12)" /><field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /></u12><u8 name="type">adc_bridge<field81 name="Enter value for in_low (default=1.0)" /><field82 name="Enter value for in_high (default=2.0)">4</field82><field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /></u8><u2 name="type">adc_bridge<field85 name="Enter value for in_low (default=1.0)" /><field86 name="Enter value for in_high (default=2.0)">4</field86><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u3></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC273/analysis b/library/SubcircuitLibrary/74HC273/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC273/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC393/74HC393-cache.lib b/library/SubcircuitLibrary/74HC393/74HC393-cache.lib
new file mode 100644
index 000000000..d76fc9443
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tff
+#
+DEF d_tff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_tff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X T 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Out 5 550 350 200 L 50 50 1 1 O
+X Nout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_4
+#
+DEF dac_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC393/74HC393.cir b/library/SubcircuitLibrary/74HC393/74HC393.cir
new file mode 100644
index 000000000..396efee4f
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393.cir
@@ -0,0 +1,27 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC393\74HC393.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/06/25 15:50:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9  Net-_U11-Pad1_ Net-_U5-Pad3_ Net-_U1-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad2_ ? d_tff		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U1-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ ? d_tff		
+U13  Net-_U11-Pad1_ Net-_U11-Pad5_ Net-_U1-Pad3_ Net-_U11-Pad4_ Net-_U13-Pad5_ ? d_tff		
+U15  Net-_U11-Pad1_ Net-_U13-Pad5_ Net-_U1-Pad3_ Net-_U11-Pad4_ Net-_U15-Pad5_ ? d_tff		
+U5  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U5-Pad3_ Net-_U5-Pad4_ adc_bridge_2		
+U3  Net-_U1-Pad1_ Net-_U11-Pad1_ adc_bridge_1		
+U7  Net-_U5-Pad4_ Net-_U11-Pad4_ d_inverter		
+U8  Net-_U10-Pad1_ Net-_U4-Pad3_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U10-Pad2_ ? d_tff		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U10-Pad5_ ? d_tff		
+U12  Net-_U10-Pad1_ Net-_U10-Pad5_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U12-Pad5_ ? d_tff		
+U14  Net-_U10-Pad1_ Net-_U12-Pad5_ Net-_U1-Pad7_ Net-_U10-Pad4_ Net-_U14-Pad5_ ? d_tff		
+U4  Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U4-Pad3_ Net-_U4-Pad4_ adc_bridge_2		
+U2  Net-_U1-Pad5_ Net-_U10-Pad1_ adc_bridge_1		
+U6  Net-_U4-Pad4_ Net-_U10-Pad4_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT		
+U16  Net-_U11-Pad2_ Net-_U11-Pad5_ Net-_U13-Pad5_ Net-_U15-Pad5_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ dac_bridge_4		
+U17  Net-_U10-Pad2_ Net-_U10-Pad5_ Net-_U12-Pad5_ Net-_U14-Pad5_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ dac_bridge_4		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC393/74HC393.cir.out b/library/SubcircuitLibrary/74HC393/74HC393.cir.out
new file mode 100644
index 000000000..053ad243f
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393.cir.out
@@ -0,0 +1,76 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc393\74hc393.cir
+
+* u9  net-_u11-pad1_ net-_u5-pad3_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad2_ ? d_tff
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad5_ ? d_tff
+* u13  net-_u11-pad1_ net-_u11-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u13-pad5_ ? d_tff
+* u15  net-_u11-pad1_ net-_u13-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u15-pad5_ ? d_tff
+* u5  net-_u1-pad2_ net-_u1-pad4_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2
+* u3  net-_u1-pad1_ net-_u11-pad1_ adc_bridge_1
+* u7  net-_u5-pad4_ net-_u11-pad4_ d_inverter
+* u8  net-_u10-pad1_ net-_u4-pad3_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad2_ ? d_tff
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad5_ ? d_tff
+* u12  net-_u10-pad1_ net-_u10-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u12-pad5_ ? d_tff
+* u14  net-_u10-pad1_ net-_u12-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u14-pad5_ ? d_tff
+* u4  net-_u1-pad6_ net-_u1-pad8_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2
+* u2  net-_u1-pad5_ net-_u10-pad1_ adc_bridge_1
+* u6  net-_u4-pad4_ net-_u10-pad4_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+* u16  net-_u11-pad2_ net-_u11-pad5_ net-_u13-pad5_ net-_u15-pad5_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ dac_bridge_4
+* u17  net-_u10-pad2_ net-_u10-pad5_ net-_u12-pad5_ net-_u14-pad5_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ dac_bridge_4
+a1 net-_u11-pad1_ net-_u5-pad3_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad2_ ? u9
+a2 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad5_ ? u11
+a3 net-_u11-pad1_ net-_u11-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u13-pad5_ ? u13
+a4 net-_u11-pad1_ net-_u13-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u15-pad5_ ? u15
+a5 [net-_u1-pad2_ net-_u1-pad4_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5
+a6 [net-_u1-pad1_ ] [net-_u11-pad1_ ] u3
+a7 net-_u5-pad4_ net-_u11-pad4_ u7
+a8 net-_u10-pad1_ net-_u4-pad3_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad2_ ? u8
+a9 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad5_ ? u10
+a10 net-_u10-pad1_ net-_u10-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u12-pad5_ ? u12
+a11 net-_u10-pad1_ net-_u12-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u14-pad5_ ? u14
+a12 [net-_u1-pad6_ net-_u1-pad8_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4
+a13 [net-_u1-pad5_ ] [net-_u10-pad1_ ] u2
+a14 net-_u4-pad4_ net-_u10-pad4_ u6
+a15 [net-_u11-pad2_ net-_u11-pad5_ net-_u13-pad5_ net-_u15-pad5_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ ] u16
+a16 [net-_u10-pad2_ net-_u10-pad5_ net-_u12-pad5_ net-_u14-pad5_ ] [net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u17
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u9 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u13 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u10 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u12 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u14 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC393/74HC393.pro b/library/SubcircuitLibrary/74HC393/74HC393.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC393/74HC393.sch b/library/SubcircuitLibrary/74HC393/74HC393.sch
new file mode 100644
index 000000000..53473015a
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393.sch
@@ -0,0 +1,604 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_tff U9
+U 1 1 6933FCAD
+P 3650 2300
+F 0 "U9" H 3650 2300 60  0000 C CNN
+F 1 "d_tff" H 3650 2450 60  0000 C CNN
+F 2 "" H 3650 2300 60  0000 C CNN
+F 3 "" H 3650 2300 60  0000 C CNN
+	1    3650 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tff U11
+U 1 1 6933FCAE
+P 5250 2300
+F 0 "U11" H 5250 2300 60  0000 C CNN
+F 1 "d_tff" H 5250 2450 60  0000 C CNN
+F 2 "" H 5250 2300 60  0000 C CNN
+F 3 "" H 5250 2300 60  0000 C CNN
+	1    5250 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tff U13
+U 1 1 6933FCAF
+P 6900 2300
+F 0 "U13" H 6900 2300 60  0000 C CNN
+F 1 "d_tff" H 6900 2450 60  0000 C CNN
+F 2 "" H 6900 2300 60  0000 C CNN
+F 3 "" H 6900 2300 60  0000 C CNN
+	1    6900 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tff U15
+U 1 1 6933FCB0
+P 8500 2300
+F 0 "U15" H 8500 2300 60  0000 C CNN
+F 1 "d_tff" H 8500 2450 60  0000 C CNN
+F 2 "" H 8500 2300 60  0000 C CNN
+F 3 "" H 8500 2300 60  0000 C CNN
+	1    8500 2300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4200 1950 4500 1950
+Wire Wire Line
+	4400 1950 4400 2600
+Wire Wire Line
+	4400 2600 4700 2600
+Wire Wire Line
+	5800 1950 6200 1950
+Wire Wire Line
+	6100 1950 6100 2600
+Wire Wire Line
+	6100 2600 6350 2600
+Wire Wire Line
+	7450 1950 7700 1950
+Wire Wire Line
+	7650 1950 7650 2600
+Wire Wire Line
+	7650 2600 7950 2600
+Wire Wire Line
+	3650 2900 3650 2950
+Wire Wire Line
+	5250 2950 5250 2900
+Wire Wire Line
+	6900 2950 6900 2900
+Connection ~ 5250 2950
+Wire Wire Line
+	8500 2950 8500 2900
+Connection ~ 6900 2950
+Wire Wire Line
+	3650 1650 3650 1600
+Wire Wire Line
+	3400 1600 8500 1600
+Wire Wire Line
+	5250 1600 5250 1650
+Wire Wire Line
+	6900 1600 6900 1650
+Connection ~ 5250 1600
+Wire Wire Line
+	8500 1600 8500 1650
+Connection ~ 6900 1600
+$Comp
+L adc_bridge_2 U5
+U 1 1 6933FCB2
+P 2250 2650
+F 0 "U5" H 2250 2650 60  0000 C CNN
+F 1 "adc_bridge_2" H 2250 2800 60  0000 C CNN
+F 2 "" H 2250 2650 60  0000 C CNN
+F 3 "" H 2250 2650 60  0000 C CNN
+	1    2250 2650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1400 2700 1650 2700
+Wire Wire Line
+	2800 2600 3100 2600
+Connection ~ 3650 2950
+Wire Wire Line
+	3100 1950 2900 1950
+Wire Wire Line
+	2900 1950 2900 1350
+Wire Wire Line
+	2900 1350 7950 1350
+Wire Wire Line
+	4700 1350 4700 1950
+Wire Wire Line
+	6350 1350 6350 1950
+Connection ~ 4700 1350
+Wire Wire Line
+	7950 1350 7950 1950
+Connection ~ 6350 1350
+$Comp
+L adc_bridge_1 U3
+U 1 1 6933FCB5
+P 1900 1450
+F 0 "U3" H 1900 1450 60  0000 C CNN
+F 1 "adc_bridge_1" H 1900 1600 60  0000 C CNN
+F 2 "" H 1900 1450 60  0000 C CNN
+F 3 "" H 1900 1450 60  0000 C CNN
+	1    1900 1450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2450 1400 2900 1400
+Connection ~ 2900 1400
+Connection ~ 3650 1600
+Wire Wire Line
+	9200 1950 9050 1950
+Connection ~ 4400 1950
+Wire Wire Line
+	7700 1950 7700 3300
+Connection ~ 7650 1950
+Wire Wire Line
+	6200 1950 6200 3200
+Connection ~ 6100 1950
+Wire Wire Line
+	9200 1950 9200 3150
+$Comp
+L d_inverter U7
+U 1 1 6933FCBD
+P 3200 2950
+F 0 "U7" H 3200 2850 60  0000 C CNN
+F 1 "d_inverter" H 3200 3100 60  0000 C CNN
+F 2 "" H 3250 2900 60  0000 C CNN
+F 3 "" H 3250 2900 60  0000 C CNN
+	1    3200 2950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2800 2700 2850 2700
+Wire Wire Line
+	2850 2700 2850 2950
+Wire Wire Line
+	2850 2950 2900 2950
+Wire Wire Line
+	3500 2950 8500 2950
+$Comp
+L d_tff U8
+U 1 1 69340169
+P 3300 4700
+F 0 "U8" H 3300 4700 60  0000 C CNN
+F 1 "d_tff" H 3300 4850 60  0000 C CNN
+F 2 "" H 3300 4700 60  0000 C CNN
+F 3 "" H 3300 4700 60  0000 C CNN
+	1    3300 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tff U10
+U 1 1 6934016F
+P 4900 4700
+F 0 "U10" H 4900 4700 60  0000 C CNN
+F 1 "d_tff" H 4900 4850 60  0000 C CNN
+F 2 "" H 4900 4700 60  0000 C CNN
+F 3 "" H 4900 4700 60  0000 C CNN
+	1    4900 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tff U12
+U 1 1 69340175
+P 6550 4700
+F 0 "U12" H 6550 4700 60  0000 C CNN
+F 1 "d_tff" H 6550 4850 60  0000 C CNN
+F 2 "" H 6550 4700 60  0000 C CNN
+F 3 "" H 6550 4700 60  0000 C CNN
+	1    6550 4700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_tff U14
+U 1 1 6934017B
+P 8150 4700
+F 0 "U14" H 8150 4700 60  0000 C CNN
+F 1 "d_tff" H 8150 4850 60  0000 C CNN
+F 2 "" H 8150 4700 60  0000 C CNN
+F 3 "" H 8150 4700 60  0000 C CNN
+	1    8150 4700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3850 4350 4150 4350
+Wire Wire Line
+	4050 4350 4050 5000
+Wire Wire Line
+	4050 5000 4350 5000
+Wire Wire Line
+	5450 4350 5850 4350
+Wire Wire Line
+	5750 4350 5750 5000
+Wire Wire Line
+	5750 5000 6000 5000
+Wire Wire Line
+	7100 4350 7350 4350
+Wire Wire Line
+	7300 4350 7300 5000
+Wire Wire Line
+	7300 5000 7600 5000
+Wire Wire Line
+	3300 5300 3300 5350
+Wire Wire Line
+	4900 5350 4900 5300
+Wire Wire Line
+	6550 5350 6550 5300
+Connection ~ 4900 5350
+Wire Wire Line
+	8150 5350 8150 5300
+Connection ~ 6550 5350
+Wire Wire Line
+	3300 4050 3300 4000
+Wire Wire Line
+	3050 4000 8150 4000
+Wire Wire Line
+	4900 4000 4900 4050
+Wire Wire Line
+	6550 4000 6550 4050
+Connection ~ 4900 4000
+Wire Wire Line
+	8150 4000 8150 4050
+Connection ~ 6550 4000
+$Comp
+L adc_bridge_2 U4
+U 1 1 69340197
+P 1900 5050
+F 0 "U4" H 1900 5050 60  0000 C CNN
+F 1 "adc_bridge_2" H 1900 5200 60  0000 C CNN
+F 2 "" H 1900 5050 60  0000 C CNN
+F 3 "" H 1900 5050 60  0000 C CNN
+	1    1900 5050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1050 5100 1300 5100
+Wire Wire Line
+	2450 5000 2750 5000
+Connection ~ 3300 5350
+Wire Wire Line
+	2750 4350 2550 4350
+Wire Wire Line
+	2550 4350 2550 3750
+Wire Wire Line
+	2550 3750 7600 3750
+Wire Wire Line
+	4350 3750 4350 4350
+Wire Wire Line
+	6000 3750 6000 4350
+Connection ~ 4350 3750
+Wire Wire Line
+	7600 3750 7600 4350
+Connection ~ 6000 3750
+$Comp
+L adc_bridge_1 U2
+U 1 1 693401A8
+P 1550 3850
+F 0 "U2" H 1550 3850 60  0000 C CNN
+F 1 "adc_bridge_1" H 1550 4000 60  0000 C CNN
+F 2 "" H 1550 3850 60  0000 C CNN
+F 3 "" H 1550 3850 60  0000 C CNN
+	1    1550 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2100 3800 2550 3800
+Connection ~ 2550 3800
+Connection ~ 3300 4000
+Wire Wire Line
+	8850 4350 8700 4350
+Connection ~ 4050 4350
+Wire Wire Line
+	7350 4350 7350 5700
+Connection ~ 7300 4350
+Wire Wire Line
+	5850 4350 5850 5600
+Connection ~ 5750 4350
+Wire Wire Line
+	8850 4350 8850 5800
+$Comp
+L d_inverter U6
+U 1 1 693401B9
+P 2850 5350
+F 0 "U6" H 2850 5250 60  0000 C CNN
+F 1 "d_inverter" H 2850 5500 60  0000 C CNN
+F 2 "" H 2900 5300 60  0000 C CNN
+F 3 "" H 2900 5300 60  0000 C CNN
+	1    2850 5350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2450 5100 2500 5100
+Wire Wire Line
+	2500 5100 2500 5350
+Wire Wire Line
+	2500 5350 2550 5350
+Wire Wire Line
+	3150 5350 8150 5350
+$Comp
+L PORT U1
+U 3 1 69340323
+P 3150 1600
+F 0 "U1" H 3200 1700 30  0000 C CNN
+F 1 "PORT" H 3150 1600 30  0000 C CNN
+F 2 "" H 3150 1600 60  0000 C CNN
+F 3 "" H 3150 1600 60  0000 C CNN
+	3    3150 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6934043F
+P 1050 5000
+F 0 "U1" H 1100 5100 30  0000 C CNN
+F 1 "PORT" H 1050 5000 30  0000 C CNN
+F 2 "" H 1050 5000 60  0000 C CNN
+F 3 "" H 1050 5000 60  0000 C CNN
+	6    1050 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 693405E2
+P 700 3800
+F 0 "U1" H 750 3900 30  0000 C CNN
+F 1 "PORT" H 700 3800 30  0000 C CNN
+F 2 "" H 700 3800 60  0000 C CNN
+F 3 "" H 700 3800 60  0000 C CNN
+	5    700  3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 693408B7
+P 800 5100
+F 0 "U1" H 850 5200 30  0000 C CNN
+F 1 "PORT" H 800 5100 30  0000 C CNN
+F 2 "" H 800 5100 60  0000 C CNN
+F 3 "" H 800 5100 60  0000 C CNN
+	8    800  5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 693409D0
+P 10650 2950
+F 0 "U1" H 10700 3050 30  0000 C CNN
+F 1 "PORT" H 10650 2950 30  0000 C CNN
+F 2 "" H 10650 2950 60  0000 C CNN
+F 3 "" H 10650 2950 60  0000 C CNN
+	10   10650 2950
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4500 1950 4500 3100
+$Comp
+L PORT U1
+U 12 1 69340AD4
+P 10650 3150
+F 0 "U1" H 10700 3250 30  0000 C CNN
+F 1 "PORT" H 10650 3150 30  0000 C CNN
+F 2 "" H 10650 3150 60  0000 C CNN
+F 3 "" H 10650 3150 60  0000 C CNN
+	12   10650 3150
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 693415EC
+P 10650 5600
+F 0 "U1" H 10700 5700 30  0000 C CNN
+F 1 "PORT" H 10650 5600 30  0000 C CNN
+F 2 "" H 10650 5600 60  0000 C CNN
+F 3 "" H 10650 5600 60  0000 C CNN
+	14   10650 5600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6934164E
+P 10650 5800
+F 0 "U1" H 10700 5900 30  0000 C CNN
+F 1 "PORT" H 10650 5800 30  0000 C CNN
+F 2 "" H 10650 5800 60  0000 C CNN
+F 3 "" H 10650 5800 60  0000 C CNN
+	16   10650 5800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 69341803
+P 1050 1400
+F 0 "U1" H 1100 1500 30  0000 C CNN
+F 1 "PORT" H 1050 1400 30  0000 C CNN
+F 2 "" H 1050 1400 60  0000 C CNN
+F 3 "" H 1050 1400 60  0000 C CNN
+	1    1050 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 69341898
+P 1150 2700
+F 0 "U1" H 1200 2800 30  0000 C CNN
+F 1 "PORT" H 1150 2700 30  0000 C CNN
+F 2 "" H 1150 2700 60  0000 C CNN
+F 3 "" H 1150 2700 60  0000 C CNN
+	4    1150 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 69341923
+P 1400 2600
+F 0 "U1" H 1450 2700 30  0000 C CNN
+F 1 "PORT" H 1400 2600 30  0000 C CNN
+F 2 "" H 1400 2600 60  0000 C CNN
+F 3 "" H 1400 2600 60  0000 C CNN
+	2    1400 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 69341997
+P 2800 4000
+F 0 "U1" H 2850 4100 30  0000 C CNN
+F 1 "PORT" H 2800 4000 30  0000 C CNN
+F 2 "" H 2800 4000 60  0000 C CNN
+F 3 "" H 2800 4000 60  0000 C CNN
+	7    2800 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 69341A98
+P 10650 2850
+F 0 "U1" H 10700 2950 30  0000 C CNN
+F 1 "PORT" H 10650 2850 30  0000 C CNN
+F 2 "" H 10650 2850 60  0000 C CNN
+F 3 "" H 10650 2850 60  0000 C CNN
+	9    10650 2850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 69341B27
+P 10650 3050
+F 0 "U1" H 10700 3150 30  0000 C CNN
+F 1 "PORT" H 10650 3050 30  0000 C CNN
+F 2 "" H 10650 3050 60  0000 C CNN
+F 3 "" H 10650 3050 60  0000 C CNN
+	11   10650 3050
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 13 1 69341BFA
+P 10650 5500
+F 0 "U1" H 10700 5600 30  0000 C CNN
+F 1 "PORT" H 10650 5500 30  0000 C CNN
+F 2 "" H 10650 5500 60  0000 C CNN
+F 3 "" H 10650 5500 60  0000 C CNN
+	13   10650 5500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 15 1 69341C91
+P 10650 5700
+F 0 "U1" H 10700 5800 30  0000 C CNN
+F 1 "PORT" H 10650 5700 30  0000 C CNN
+F 2 "" H 10650 5700 60  0000 C CNN
+F 3 "" H 10650 5700 60  0000 C CNN
+	15   10650 5700
+	-1   0    0    1   
+$EndComp
+$Comp
+L dac_bridge_4 U16
+U 1 1 69342B60
+P 9850 3050
+F 0 "U16" H 9850 3050 60  0000 C CNN
+F 1 "dac_bridge_4" H 9850 3350 60  0000 C CNN
+F 2 "" H 9850 3050 60  0000 C CNN
+F 3 "" H 9850 3050 60  0000 C CNN
+	1    9850 3050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4500 3100 8750 3100
+Wire Wire Line
+	8750 3100 8750 2850
+Wire Wire Line
+	8750 2850 9300 2850
+Wire Wire Line
+	6200 3200 8850 3200
+Wire Wire Line
+	8850 3200 8850 2950
+Wire Wire Line
+	8850 2950 9300 2950
+Wire Wire Line
+	7700 3300 8950 3300
+Wire Wire Line
+	8950 3300 8950 3050
+Wire Wire Line
+	8950 3050 9300 3050
+Wire Wire Line
+	9200 3150 9300 3150
+$Comp
+L dac_bridge_4 U17
+U 1 1 69343713
+P 9850 5700
+F 0 "U17" H 9850 5700 60  0000 C CNN
+F 1 "dac_bridge_4" H 9850 6000 60  0000 C CNN
+F 2 "" H 9850 5700 60  0000 C CNN
+F 3 "" H 9850 5700 60  0000 C CNN
+	1    9850 5700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4150 4350 4150 5500
+Wire Wire Line
+	4150 5500 9300 5500
+Wire Wire Line
+	5850 5600 9300 5600
+Wire Wire Line
+	7350 5700 9300 5700
+Wire Wire Line
+	8850 5800 9300 5800
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC393/74HC393.sub b/library/SubcircuitLibrary/74HC393/74HC393.sub
new file mode 100644
index 000000000..c6a11ad9e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393.sub
@@ -0,0 +1,70 @@
+* Subcircuit 74HC393
+.subckt 74HC393 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc393\74hc393.cir
+* u9  net-_u11-pad1_ net-_u5-pad3_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad2_ ? d_tff
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad5_ ? d_tff
+* u13  net-_u11-pad1_ net-_u11-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u13-pad5_ ? d_tff
+* u15  net-_u11-pad1_ net-_u13-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u15-pad5_ ? d_tff
+* u5  net-_u1-pad2_ net-_u1-pad4_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2
+* u3  net-_u1-pad1_ net-_u11-pad1_ adc_bridge_1
+* u7  net-_u5-pad4_ net-_u11-pad4_ d_inverter
+* u8  net-_u10-pad1_ net-_u4-pad3_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad2_ ? d_tff
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad5_ ? d_tff
+* u12  net-_u10-pad1_ net-_u10-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u12-pad5_ ? d_tff
+* u14  net-_u10-pad1_ net-_u12-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u14-pad5_ ? d_tff
+* u4  net-_u1-pad6_ net-_u1-pad8_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2
+* u2  net-_u1-pad5_ net-_u10-pad1_ adc_bridge_1
+* u6  net-_u4-pad4_ net-_u10-pad4_ d_inverter
+* u16  net-_u11-pad2_ net-_u11-pad5_ net-_u13-pad5_ net-_u15-pad5_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ dac_bridge_4
+* u17  net-_u10-pad2_ net-_u10-pad5_ net-_u12-pad5_ net-_u14-pad5_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ dac_bridge_4
+a1 net-_u11-pad1_ net-_u5-pad3_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad2_ ? u9
+a2 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad3_ net-_u11-pad4_ net-_u11-pad5_ ? u11
+a3 net-_u11-pad1_ net-_u11-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u13-pad5_ ? u13
+a4 net-_u11-pad1_ net-_u13-pad5_ net-_u1-pad3_ net-_u11-pad4_ net-_u15-pad5_ ? u15
+a5 [net-_u1-pad2_ net-_u1-pad4_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5
+a6 [net-_u1-pad1_ ] [net-_u11-pad1_ ] u3
+a7 net-_u5-pad4_ net-_u11-pad4_ u7
+a8 net-_u10-pad1_ net-_u4-pad3_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad2_ ? u8
+a9 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad7_ net-_u10-pad4_ net-_u10-pad5_ ? u10
+a10 net-_u10-pad1_ net-_u10-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u12-pad5_ ? u12
+a11 net-_u10-pad1_ net-_u12-pad5_ net-_u1-pad7_ net-_u10-pad4_ net-_u14-pad5_ ? u14
+a12 [net-_u1-pad6_ net-_u1-pad8_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4
+a13 [net-_u1-pad5_ ] [net-_u10-pad1_ ] u2
+a14 net-_u4-pad4_ net-_u10-pad4_ u6
+a15 [net-_u11-pad2_ net-_u11-pad5_ net-_u13-pad5_ net-_u15-pad5_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ ] u16
+a16 [net-_u10-pad2_ net-_u10-pad5_ net-_u12-pad5_ net-_u14-pad5_ ] [net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u17
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u9 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u13 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u10 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u12 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u14 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends 74HC393
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC393/74HC393_Previous_Values.xml b/library/SubcircuitLibrary/74HC393/74HC393_Previous_Values.xml
new file mode 100644
index 000000000..67c17c3cd
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/74HC393_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u9 name="type">d_tff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for T Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u9><u11 name="type">d_tff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for T Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u11><u13 name="type">d_tff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for T Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u13><u15 name="type">d_tff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for T Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u15><u5 name="type">adc_bridge<field41 name="Enter value for in_low (default=1.0)" /><field42 name="Enter value for in_high (default=2.0)" /><field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /></u5><u3 name="type">adc_bridge<field45 name="Enter value for in_low (default=1.0)" /><field46 name="Enter value for in_high (default=2.0)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /></u3><u7 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_tff<field52 name="Enter Clk Delay (default=1.0e-9)" /><field53 name="Enter Set Delay (default=1.0e-9)" /><field54 name="Enter Reset Delay (default=1.0)" /><field55 name="Enter IC (default=0)" /><field56 name="Enter value for T Load (default=1.0e-12)" /><field57 name="Enter value for Clk Load (default=1.0e-12)" /><field58 name="Enter value for Set Load (default=1.0e-12)" /><field59 name="Enter value for Reset Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /><field61 name="Enter Fall Delay (default=1.0e-9)" /></u8><u10 name="type">d_tff<field62 name="Enter Clk Delay (default=1.0e-9)" /><field63 name="Enter Set Delay (default=1.0e-9)" /><field64 name="Enter Reset Delay (default=1.0)" /><field65 name="Enter IC (default=0)" /><field66 name="Enter value for T Load (default=1.0e-12)" /><field67 name="Enter value for Clk Load (default=1.0e-12)" /><field68 name="Enter value for Set Load (default=1.0e-12)" /><field69 name="Enter value for Reset Load (default=1.0e-12)" /><field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /></u10><u12 name="type">d_tff<field72 name="Enter Clk Delay (default=1.0e-9)" /><field73 name="Enter Set Delay (default=1.0e-9)" /><field74 name="Enter Reset Delay (default=1.0)" /><field75 name="Enter IC (default=0)" /><field76 name="Enter value for T Load (default=1.0e-12)" /><field77 name="Enter value for Clk Load (default=1.0e-12)" /><field78 name="Enter value for Set Load (default=1.0e-12)" /><field79 name="Enter value for Reset Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /></u12><u14 name="type">d_tff<field82 name="Enter Clk Delay (default=1.0e-9)" /><field83 name="Enter Set Delay (default=1.0e-9)" /><field84 name="Enter Reset Delay (default=1.0)" /><field85 name="Enter IC (default=0)" /><field86 name="Enter value for T Load (default=1.0e-12)" /><field87 name="Enter value for Clk Load (default=1.0e-12)" /><field88 name="Enter value for Set Load (default=1.0e-12)" /><field89 name="Enter value for Reset Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /><field91 name="Enter Fall Delay (default=1.0e-9)" /></u14><u4 name="type">adc_bridge<field92 name="Enter value for in_low (default=1.0)" /><field93 name="Enter value for in_high (default=2.0)">4</field93><field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /></u4><u2 name="type">adc_bridge<field96 name="Enter value for in_low (default=1.0)" /><field97 name="Enter value for in_high (default=2.0)">4</field97><field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /></u2><u6 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u6><u16 name="type">dac_bridge<field103 name="Enter value for out_low (default=0.0)" /><field104 name="Enter value for out_high (default=5.0)" /><field105 name="Enter value for out_undef (default=0.5)" /><field106 name="Enter value for input load (default=1.0e-12)" /><field107 name="Enter the Rise Time (default=1.0e-9)" /><field108 name="Enter the Fall Time (default=1.0e-9)" /></u16><u17 name="type">dac_bridge<field109 name="Enter value for out_low (default=0.0)" /><field110 name="Enter value for out_high (default=5.0)" /><field111 name="Enter value for out_undef (default=0.5)" /><field112 name="Enter value for input load (default=1.0e-12)" /><field113 name="Enter the Rise Time (default=1.0e-9)" /><field114 name="Enter the Fall Time (default=1.0e-9)" /></u17></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC393/analysis b/library/SubcircuitLibrary/74HC393/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC393/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049-cache.lib b/library/SubcircuitLibrary/74HC4049/74HC4049-cache.lib
new file mode 100644
index 000000000..a50418f6b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049-cache.lib
@@ -0,0 +1,58 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049.cir b/library/SubcircuitLibrary/74HC4049/74HC4049.cir
new file mode 100644
index 000000000..67534a6f4
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC4049\74HC4049.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/23/26 10:14:31
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad7_ d_inverter		
+U3  Net-_U1-Pad2_ Net-_U1-Pad8_ d_inverter		
+U4  Net-_U1-Pad3_ Net-_U1-Pad9_ d_inverter		
+U5  Net-_U1-Pad4_ Net-_U1-Pad10_ d_inverter		
+U6  Net-_U1-Pad5_ Net-_U1-Pad11_ d_inverter		
+U7  Net-_U1-Pad6_ Net-_U1-Pad12_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049.cir.out b/library/SubcircuitLibrary/74HC4049/74HC4049.cir.out
new file mode 100644
index 000000000..f55c8411c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049.cir.out
@@ -0,0 +1,36 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc4049\74hc4049.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad7_ d_inverter
+* u3  net-_u1-pad2_ net-_u1-pad8_ d_inverter
+* u4  net-_u1-pad3_ net-_u1-pad9_ d_inverter
+* u5  net-_u1-pad4_ net-_u1-pad10_ d_inverter
+* u6  net-_u1-pad5_ net-_u1-pad11_ d_inverter
+* u7  net-_u1-pad6_ net-_u1-pad12_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+a1 net-_u1-pad1_ net-_u1-pad7_ u2
+a2 net-_u1-pad2_ net-_u1-pad8_ u3
+a3 net-_u1-pad3_ net-_u1-pad9_ u4
+a4 net-_u1-pad4_ net-_u1-pad10_ u5
+a5 net-_u1-pad5_ net-_u1-pad11_ u6
+a6 net-_u1-pad6_ net-_u1-pad12_ u7
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049.pro b/library/SubcircuitLibrary/74HC4049/74HC4049.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049.sch b/library/SubcircuitLibrary/74HC4049/74HC4049.sch
new file mode 100644
index 000000000..f1b662e2c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049.sch
@@ -0,0 +1,278 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U2
+U 1 1 693D6079
+P 5800 1850
+F 0 "U2" H 5800 1750 60  0000 C CNN
+F 1 "d_inverter" H 5800 2000 60  0000 C CNN
+F 2 "" H 5850 1800 60  0000 C CNN
+F 3 "" H 5850 1800 60  0000 C CNN
+	1    5800 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 693D610C
+P 5800 2350
+F 0 "U3" H 5800 2250 60  0000 C CNN
+F 1 "d_inverter" H 5800 2500 60  0000 C CNN
+F 2 "" H 5850 2300 60  0000 C CNN
+F 3 "" H 5850 2300 60  0000 C CNN
+	1    5800 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 693D613F
+P 5800 2850
+F 0 "U4" H 5800 2750 60  0000 C CNN
+F 1 "d_inverter" H 5800 3000 60  0000 C CNN
+F 2 "" H 5850 2800 60  0000 C CNN
+F 3 "" H 5850 2800 60  0000 C CNN
+	1    5800 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 693D616D
+P 5800 3300
+F 0 "U5" H 5800 3200 60  0000 C CNN
+F 1 "d_inverter" H 5800 3450 60  0000 C CNN
+F 2 "" H 5850 3250 60  0000 C CNN
+F 3 "" H 5850 3250 60  0000 C CNN
+	1    5800 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 693D61B0
+P 5800 3800
+F 0 "U6" H 5800 3700 60  0000 C CNN
+F 1 "d_inverter" H 5800 3950 60  0000 C CNN
+F 2 "" H 5850 3750 60  0000 C CNN
+F 3 "" H 5850 3750 60  0000 C CNN
+	1    5800 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 693D621B
+P 5800 4300
+F 0 "U7" H 5800 4200 60  0000 C CNN
+F 1 "d_inverter" H 5800 4450 60  0000 C CNN
+F 2 "" H 5850 4250 60  0000 C CNN
+F 3 "" H 5850 4250 60  0000 C CNN
+	1    5800 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 693D62D6
+P 5050 1850
+F 0 "U1" H 5100 1950 30  0000 C CNN
+F 1 "PORT" H 5050 1850 30  0000 C CNN
+F 2 "" H 5050 1850 60  0000 C CNN
+F 3 "" H 5050 1850 60  0000 C CNN
+	1    5050 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 693D6312
+P 5050 2350
+F 0 "U1" H 5100 2450 30  0000 C CNN
+F 1 "PORT" H 5050 2350 30  0000 C CNN
+F 2 "" H 5050 2350 60  0000 C CNN
+F 3 "" H 5050 2350 60  0000 C CNN
+	2    5050 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 693D6345
+P 5050 2850
+F 0 "U1" H 5100 2950 30  0000 C CNN
+F 1 "PORT" H 5050 2850 30  0000 C CNN
+F 2 "" H 5050 2850 60  0000 C CNN
+F 3 "" H 5050 2850 60  0000 C CNN
+	3    5050 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 693D63B1
+P 5050 3300
+F 0 "U1" H 5100 3400 30  0000 C CNN
+F 1 "PORT" H 5050 3300 30  0000 C CNN
+F 2 "" H 5050 3300 60  0000 C CNN
+F 3 "" H 5050 3300 60  0000 C CNN
+	4    5050 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 693D63E6
+P 5050 3800
+F 0 "U1" H 5100 3900 30  0000 C CNN
+F 1 "PORT" H 5050 3800 30  0000 C CNN
+F 2 "" H 5050 3800 60  0000 C CNN
+F 3 "" H 5050 3800 60  0000 C CNN
+	5    5050 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 693D6456
+P 5050 4300
+F 0 "U1" H 5100 4400 30  0000 C CNN
+F 1 "PORT" H 5050 4300 30  0000 C CNN
+F 2 "" H 5050 4300 60  0000 C CNN
+F 3 "" H 5050 4300 60  0000 C CNN
+	6    5050 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 693D64DB
+P 6600 1850
+F 0 "U1" H 6650 1950 30  0000 C CNN
+F 1 "PORT" H 6600 1850 30  0000 C CNN
+F 2 "" H 6600 1850 60  0000 C CNN
+F 3 "" H 6600 1850 60  0000 C CNN
+	7    6600 1850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 693D6520
+P 6600 2350
+F 0 "U1" H 6650 2450 30  0000 C CNN
+F 1 "PORT" H 6600 2350 30  0000 C CNN
+F 2 "" H 6600 2350 60  0000 C CNN
+F 3 "" H 6600 2350 60  0000 C CNN
+	8    6600 2350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 693D6563
+P 6600 2850
+F 0 "U1" H 6650 2950 30  0000 C CNN
+F 1 "PORT" H 6600 2850 30  0000 C CNN
+F 2 "" H 6600 2850 60  0000 C CNN
+F 3 "" H 6600 2850 60  0000 C CNN
+	9    6600 2850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 693D65DC
+P 6600 3300
+F 0 "U1" H 6650 3400 30  0000 C CNN
+F 1 "PORT" H 6600 3300 30  0000 C CNN
+F 2 "" H 6600 3300 60  0000 C CNN
+F 3 "" H 6600 3300 60  0000 C CNN
+	10   6600 3300
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 693D6657
+P 6600 3800
+F 0 "U1" H 6650 3900 30  0000 C CNN
+F 1 "PORT" H 6600 3800 30  0000 C CNN
+F 2 "" H 6600 3800 60  0000 C CNN
+F 3 "" H 6600 3800 60  0000 C CNN
+	11   6600 3800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 693D669E
+P 6600 4300
+F 0 "U1" H 6650 4400 30  0000 C CNN
+F 1 "PORT" H 6600 4300 30  0000 C CNN
+F 2 "" H 6600 4300 60  0000 C CNN
+F 3 "" H 6600 4300 60  0000 C CNN
+	12   6600 4300
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5300 1850 5500 1850
+Wire Wire Line
+	5300 2350 5500 2350
+Wire Wire Line
+	5300 2850 5500 2850
+Wire Wire Line
+	5300 3300 5500 3300
+Wire Wire Line
+	5300 3800 5500 3800
+Wire Wire Line
+	5300 4300 5500 4300
+Wire Wire Line
+	6350 4300 6100 4300
+Wire Wire Line
+	6100 3800 6350 3800
+Wire Wire Line
+	6100 3300 6350 3300
+Wire Wire Line
+	6100 2850 6350 2850
+Wire Wire Line
+	6100 2350 6350 2350
+Wire Wire Line
+	6100 1850 6350 1850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049.sub b/library/SubcircuitLibrary/74HC4049/74HC4049.sub
new file mode 100644
index 000000000..6ebd4110e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049.sub
@@ -0,0 +1,30 @@
+* Subcircuit 74HC4049
+.subckt 74HC4049 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc4049\74hc4049.cir
+* u2  net-_u1-pad1_ net-_u1-pad7_ d_inverter
+* u3  net-_u1-pad2_ net-_u1-pad8_ d_inverter
+* u4  net-_u1-pad3_ net-_u1-pad9_ d_inverter
+* u5  net-_u1-pad4_ net-_u1-pad10_ d_inverter
+* u6  net-_u1-pad5_ net-_u1-pad11_ d_inverter
+* u7  net-_u1-pad6_ net-_u1-pad12_ d_inverter
+a1 net-_u1-pad1_ net-_u1-pad7_ u2
+a2 net-_u1-pad2_ net-_u1-pad8_ u3
+a3 net-_u1-pad3_ net-_u1-pad9_ u4
+a4 net-_u1-pad4_ net-_u1-pad10_ u5
+a5 net-_u1-pad5_ net-_u1-pad11_ u6
+a6 net-_u1-pad6_ net-_u1-pad12_ u7
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC4049
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC4049/74HC4049_Previous_Values.xml b/library/SubcircuitLibrary/74HC4049/74HC4049_Previous_Values.xml
new file mode 100644
index 000000000..9bceeacdc
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/74HC4049_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC4049/analysis b/library/SubcircuitLibrary/74HC4049/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4049/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC85/74HC85-cache.lib b/library/SubcircuitLibrary/74HC85/74HC85-cache.lib
new file mode 100644
index 000000000..84765a496
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85-cache.lib
@@ -0,0 +1,160 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_3
+#
+DEF dac_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC85/74HC85.cir b/library/SubcircuitLibrary/74HC85/74HC85.cir
new file mode 100644
index 000000000..8cf19bc4b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85.cir
@@ -0,0 +1,54 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC85\74HC85.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/13/26 10:05:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5  Net-_U11-Pad1_ Net-_U2-Pad10_ Net-_U27-Pad1_ d_xor		
+U6  Net-_U12-Pad1_ Net-_U2-Pad12_ Net-_U27-Pad2_ d_xor		
+U3  Net-_U13-Pad1_ Net-_U2-Pad14_ Net-_U28-Pad1_ d_xor		
+U4  Net-_U14-Pad1_ Net-_U10-Pad1_ Net-_U28-Pad2_ d_xor		
+U2  Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U11-Pad1_ Net-_U2-Pad10_ Net-_U12-Pad1_ Net-_U2-Pad12_ Net-_U13-Pad1_ Net-_U2-Pad14_ Net-_U14-Pad1_ Net-_U10-Pad1_ adc_bridge_8		
+U15  Net-_U11-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and		
+U16  Net-_U12-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and		
+U17  Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and		
+U21  Net-_U2-Pad10_ Net-_U11-Pad2_ Net-_U21-Pad3_ d_and		
+U22  Net-_U2-Pad12_ Net-_U12-Pad2_ Net-_U22-Pad3_ d_and		
+U23  Net-_U2-Pad14_ Net-_U13-Pad2_ Net-_U23-Pad3_ d_and		
+U18  Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and		
+U19  Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad3_ d_and		
+U20  Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U20-Pad3_ d_and		
+U29  Net-_U16-Pad3_ Net-_U18-Pad1_ Net-_U29-Pad3_ d_and		
+U30  Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U30-Pad3_ d_and		
+U31  Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U31-Pad3_ d_and		
+U24  Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U24-Pad3_ d_and		
+U25  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U25-Pad3_ d_and		
+U26  Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U26-Pad3_ d_and		
+U33  Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U33-Pad3_ d_and		
+U32  Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U32-Pad3_ d_and		
+U34  Net-_U22-Pad3_ Net-_U18-Pad1_ Net-_U34-Pad3_ d_and		
+U7  Net-_U2-Pad10_ Net-_U15-Pad2_ d_inverter		
+U8  Net-_U2-Pad12_ Net-_U16-Pad2_ d_inverter		
+U9  Net-_U2-Pad14_ Net-_U17-Pad2_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter		
+U14  Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter		
+U35  Net-_U15-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_or		
+U42  Net-_U35-Pad3_ Net-_U38-Pad3_ Net-_U42-Pad3_ d_or		
+U36  Net-_U31-Pad3_ Net-_U36-Pad2_ Net-_U36-Pad3_ d_and		
+U38  Net-_U30-Pad3_ Net-_U36-Pad3_ Net-_U38-Pad3_ d_or		
+U40  Net-_U21-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_or		
+U37  Net-_U33-Pad3_ Net-_U36-Pad2_ Net-_U37-Pad3_ d_and		
+U41  Net-_U32-Pad3_ Net-_U37-Pad3_ Net-_U41-Pad3_ d_or		
+U43  Net-_U40-Pad3_ Net-_U41-Pad3_ Net-_U43-Pad3_ d_or		
+U27  Net-_U27-Pad1_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_and		
+U28  Net-_U28-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and		
+U39  Net-_U27-Pad3_ Net-_U28-Pad3_ Net-_U39-Pad3_ d_and		
+U44  Net-_U42-Pad3_ Net-_U39-Pad3_ Net-_U43-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ dac_bridge_3		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/74HC85/74HC85.cir.out b/library/SubcircuitLibrary/74HC85/74HC85.cir.out
new file mode 100644
index 000000000..58d66c78c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85.cir.out
@@ -0,0 +1,184 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc85\74hc85.cir
+
+* u5  net-_u11-pad1_ net-_u2-pad10_ net-_u27-pad1_ d_xor
+* u6  net-_u12-pad1_ net-_u2-pad12_ net-_u27-pad2_ d_xor
+* u3  net-_u13-pad1_ net-_u2-pad14_ net-_u28-pad1_ d_xor
+* u4  net-_u14-pad1_ net-_u10-pad1_ net-_u28-pad2_ d_xor
+* u2  net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u11-pad1_ net-_u2-pad10_ net-_u12-pad1_ net-_u2-pad12_ net-_u13-pad1_ net-_u2-pad14_ net-_u14-pad1_ net-_u10-pad1_ adc_bridge_8
+* u15  net-_u11-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16  net-_u12-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
+* u17  net-_u13-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
+* u21  net-_u2-pad10_ net-_u11-pad2_ net-_u21-pad3_ d_and
+* u22  net-_u2-pad12_ net-_u12-pad2_ net-_u22-pad3_ d_and
+* u23  net-_u2-pad14_ net-_u13-pad2_ net-_u23-pad3_ d_and
+* u18  net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
+* u19  net-_u14-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and
+* u20  net-_u18-pad1_ net-_u18-pad2_ net-_u20-pad3_ d_and
+* u29  net-_u16-pad3_ net-_u18-pad1_ net-_u29-pad3_ d_and
+* u30  net-_u17-pad3_ net-_u18-pad3_ net-_u30-pad3_ d_and
+* u31  net-_u19-pad3_ net-_u20-pad3_ net-_u31-pad3_ d_and
+* u24  net-_u18-pad1_ net-_u18-pad2_ net-_u24-pad3_ d_and
+* u25  net-_u10-pad1_ net-_u14-pad2_ net-_u25-pad3_ d_and
+* u26  net-_u18-pad1_ net-_u18-pad2_ net-_u26-pad3_ d_and
+* u33  net-_u25-pad3_ net-_u26-pad3_ net-_u33-pad3_ d_and
+* u32  net-_u23-pad3_ net-_u24-pad3_ net-_u32-pad3_ d_and
+* u34  net-_u22-pad3_ net-_u18-pad1_ net-_u34-pad3_ d_and
+* u7  net-_u2-pad10_ net-_u15-pad2_ d_inverter
+* u8  net-_u2-pad12_ net-_u16-pad2_ d_inverter
+* u9  net-_u2-pad14_ net-_u17-pad2_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12  net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14  net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u35  net-_u15-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or
+* u42  net-_u35-pad3_ net-_u38-pad3_ net-_u42-pad3_ d_or
+* u36  net-_u31-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_and
+* u38  net-_u30-pad3_ net-_u36-pad3_ net-_u38-pad3_ d_or
+* u40  net-_u21-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_or
+* u37  net-_u33-pad3_ net-_u36-pad2_ net-_u37-pad3_ d_and
+* u41  net-_u32-pad3_ net-_u37-pad3_ net-_u41-pad3_ d_or
+* u43  net-_u40-pad3_ net-_u41-pad3_ net-_u43-pad3_ d_or
+* u27  net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_and
+* u28  net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and
+* u39  net-_u27-pad3_ net-_u28-pad3_ net-_u39-pad3_ d_and
+* u44  net-_u42-pad3_ net-_u39-pad3_ net-_u43-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ dac_bridge_3
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? port
+a1 [net-_u11-pad1_ net-_u2-pad10_ ] net-_u27-pad1_ u5
+a2 [net-_u12-pad1_ net-_u2-pad12_ ] net-_u27-pad2_ u6
+a3 [net-_u13-pad1_ net-_u2-pad14_ ] net-_u28-pad1_ u3
+a4 [net-_u14-pad1_ net-_u10-pad1_ ] net-_u28-pad2_ u4
+a5 [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ ] [net-_u11-pad1_ net-_u2-pad10_ net-_u12-pad1_ net-_u2-pad12_ net-_u13-pad1_ net-_u2-pad14_ net-_u14-pad1_ net-_u10-pad1_ ] u2
+a6 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a7 [net-_u12-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a8 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a9 [net-_u2-pad10_ net-_u11-pad2_ ] net-_u21-pad3_ u21
+a10 [net-_u2-pad12_ net-_u12-pad2_ ] net-_u22-pad3_ u22
+a11 [net-_u2-pad14_ net-_u13-pad2_ ] net-_u23-pad3_ u23
+a12 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a13 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19
+a14 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u20-pad3_ u20
+a15 [net-_u16-pad3_ net-_u18-pad1_ ] net-_u29-pad3_ u29
+a16 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u30-pad3_ u30
+a17 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u31-pad3_ u31
+a18 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u25-pad3_ u25
+a20 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u26-pad3_ u26
+a21 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u33-pad3_ u33
+a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u32-pad3_ u32
+a23 [net-_u22-pad3_ net-_u18-pad1_ ] net-_u34-pad3_ u34
+a24 net-_u2-pad10_ net-_u15-pad2_ u7
+a25 net-_u2-pad12_ net-_u16-pad2_ u8
+a26 net-_u2-pad14_ net-_u17-pad2_ u9
+a27 net-_u10-pad1_ net-_u10-pad2_ u10
+a28 net-_u11-pad1_ net-_u11-pad2_ u11
+a29 net-_u12-pad1_ net-_u12-pad2_ u12
+a30 net-_u13-pad1_ net-_u13-pad2_ u13
+a31 net-_u14-pad1_ net-_u14-pad2_ u14
+a32 [net-_u15-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a33 [net-_u35-pad3_ net-_u38-pad3_ ] net-_u42-pad3_ u42
+a34 [net-_u31-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36
+a35 [net-_u30-pad3_ net-_u36-pad3_ ] net-_u38-pad3_ u38
+a36 [net-_u21-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40
+a37 [net-_u33-pad3_ net-_u36-pad2_ ] net-_u37-pad3_ u37
+a38 [net-_u32-pad3_ net-_u37-pad3_ ] net-_u41-pad3_ u41
+a39 [net-_u40-pad3_ net-_u41-pad3_ ] net-_u43-pad3_ u43
+a40 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a41 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a42 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u39-pad3_ u39
+a43 [net-_u42-pad3_ net-_u39-pad3_ net-_u43-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ] u44
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_3, NgSpice Name: dac_bridge
+.model u44 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC85/74HC85.pro b/library/SubcircuitLibrary/74HC85/74HC85.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC85/74HC85.sch b/library/SubcircuitLibrary/74HC85/74HC85.sch
new file mode 100644
index 000000000..fd3f3487e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85.sch
@@ -0,0 +1,1044 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74HC85-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U5
+U 1 1 6965CB00
+P 3650 2700
+F 0 "U5" H 3650 2700 60  0000 C CNN
+F 1 "d_xor" H 3700 2800 47  0000 C CNN
+F 2 "" H 3650 2700 60  0000 C CNN
+F 3 "" H 3650 2700 60  0000 C CNN
+	1    3650 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U6
+U 1 1 6965CB01
+P 3650 3150
+F 0 "U6" H 3650 3150 60  0000 C CNN
+F 1 "d_xor" H 3700 3250 47  0000 C CNN
+F 2 "" H 3650 3150 60  0000 C CNN
+F 3 "" H 3650 3150 60  0000 C CNN
+	1    3650 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U3
+U 1 1 6965CB02
+P 3600 3600
+F 0 "U3" H 3600 3600 60  0000 C CNN
+F 1 "d_xor" H 3650 3700 47  0000 C CNN
+F 2 "" H 3600 3600 60  0000 C CNN
+F 3 "" H 3600 3600 60  0000 C CNN
+	1    3600 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U4
+U 1 1 6965CB03
+P 3600 4200
+F 0 "U4" H 3600 4200 60  0000 C CNN
+F 1 "d_xor" H 3650 4300 47  0000 C CNN
+F 2 "" H 3600 4200 60  0000 C CNN
+F 3 "" H 3600 4200 60  0000 C CNN
+	1    3600 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_8 U2
+U 1 1 6965CB04
+P 1750 3050
+F 0 "U2" H 1750 3050 60  0000 C CNN
+F 1 "adc_bridge_8" H 1750 3200 60  0000 C CNN
+F 2 "" H 1750 3050 60  0000 C CNN
+F 3 "" H 1750 3050 60  0000 C CNN
+	1    1750 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U15
+U 1 1 6965CB05
+P 6200 850
+F 0 "U15" H 6200 850 60  0000 C CNN
+F 1 "d_and" H 6250 950 60  0000 C CNN
+F 2 "" H 6200 850 60  0000 C CNN
+F 3 "" H 6200 850 60  0000 C CNN
+	1    6200 850 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U16
+U 1 1 6965CB06
+P 6200 1300
+F 0 "U16" H 6200 1300 60  0000 C CNN
+F 1 "d_and" H 6250 1400 60  0000 C CNN
+F 2 "" H 6200 1300 60  0000 C CNN
+F 3 "" H 6200 1300 60  0000 C CNN
+	1    6200 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U17
+U 1 1 6965CB07
+P 6200 2050
+F 0 "U17" H 6200 2050 60  0000 C CNN
+F 1 "d_and" H 6250 2150 60  0000 C CNN
+F 2 "" H 6200 2050 60  0000 C CNN
+F 3 "" H 6200 2050 60  0000 C CNN
+	1    6200 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U21
+U 1 1 6965CB08
+P 6250 4400
+F 0 "U21" H 6250 4400 60  0000 C CNN
+F 1 "d_and" H 6300 4500 60  0000 C CNN
+F 2 "" H 6250 4400 60  0000 C CNN
+F 3 "" H 6250 4400 60  0000 C CNN
+	1    6250 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U22
+U 1 1 6965CB09
+P 6250 4800
+F 0 "U22" H 6250 4800 60  0000 C CNN
+F 1 "d_and" H 6300 4900 60  0000 C CNN
+F 2 "" H 6250 4800 60  0000 C CNN
+F 3 "" H 6250 4800 60  0000 C CNN
+	1    6250 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U23
+U 1 1 6965CB0A
+P 6250 5500
+F 0 "U23" H 6250 5500 60  0000 C CNN
+F 1 "d_and" H 6300 5600 60  0000 C CNN
+F 2 "" H 6250 5500 60  0000 C CNN
+F 3 "" H 6250 5500 60  0000 C CNN
+	1    6250 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U18
+U 1 1 6965CB14
+P 6200 2300
+F 0 "U18" H 6200 2300 60  0000 C CNN
+F 1 "d_and" H 6250 2400 60  0000 C CNN
+F 2 "" H 6200 2300 60  0000 C CNN
+F 3 "" H 6200 2300 60  0000 C CNN
+	1    6200 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U19
+U 1 1 6965CB15
+P 6200 2800
+F 0 "U19" H 6200 2800 60  0000 C CNN
+F 1 "d_and" H 6250 2900 60  0000 C CNN
+F 2 "" H 6200 2800 60  0000 C CNN
+F 3 "" H 6200 2800 60  0000 C CNN
+	1    6200 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U20
+U 1 1 6965CB16
+P 6200 3050
+F 0 "U20" H 6200 3050 60  0000 C CNN
+F 1 "d_and" H 6250 3150 60  0000 C CNN
+F 2 "" H 6200 3050 60  0000 C CNN
+F 3 "" H 6200 3050 60  0000 C CNN
+	1    6200 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U29
+U 1 1 6965CB17
+P 7400 1400
+F 0 "U29" H 7400 1400 60  0000 C CNN
+F 1 "d_and" H 7450 1500 60  0000 C CNN
+F 2 "" H 7400 1400 60  0000 C CNN
+F 3 "" H 7400 1400 60  0000 C CNN
+	1    7400 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U30
+U 1 1 6965CB18
+P 7450 2150
+F 0 "U30" H 7450 2150 60  0000 C CNN
+F 1 "d_and" H 7500 2250 60  0000 C CNN
+F 2 "" H 7450 2150 60  0000 C CNN
+F 3 "" H 7450 2150 60  0000 C CNN
+	1    7450 2150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U31
+U 1 1 6965CB19
+P 7450 2900
+F 0 "U31" H 7450 2900 60  0000 C CNN
+F 1 "d_and" H 7500 3000 60  0000 C CNN
+F 2 "" H 7450 2900 60  0000 C CNN
+F 3 "" H 7450 2900 60  0000 C CNN
+	1    7450 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U24
+U 1 1 6965CB1A
+P 6250 5750
+F 0 "U24" H 6250 5750 60  0000 C CNN
+F 1 "d_and" H 6300 5850 60  0000 C CNN
+F 2 "" H 6250 5750 60  0000 C CNN
+F 3 "" H 6250 5750 60  0000 C CNN
+	1    6250 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U25
+U 1 1 6965CB1B
+P 6250 6150
+F 0 "U25" H 6250 6150 60  0000 C CNN
+F 1 "d_and" H 6300 6250 60  0000 C CNN
+F 2 "" H 6250 6150 60  0000 C CNN
+F 3 "" H 6250 6150 60  0000 C CNN
+	1    6250 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U26
+U 1 1 6965CB1C
+P 6250 6400
+F 0 "U26" H 6250 6400 60  0000 C CNN
+F 1 "d_and" H 6300 6500 60  0000 C CNN
+F 2 "" H 6250 6400 60  0000 C CNN
+F 3 "" H 6250 6400 60  0000 C CNN
+	1    6250 6400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U33
+U 1 1 6965CB1D
+P 7450 6250
+F 0 "U33" H 7450 6250 60  0000 C CNN
+F 1 "d_and" H 7500 6350 60  0000 C CNN
+F 2 "" H 7450 6250 60  0000 C CNN
+F 3 "" H 7450 6250 60  0000 C CNN
+	1    7450 6250
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U32
+U 1 1 6965CB1E
+P 7450 5600
+F 0 "U32" H 7450 5600 60  0000 C CNN
+F 1 "d_and" H 7500 5700 60  0000 C CNN
+F 2 "" H 7450 5600 60  0000 C CNN
+F 3 "" H 7450 5600 60  0000 C CNN
+	1    7450 5600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U34
+U 1 1 6965CB1F
+P 7500 4900
+F 0 "U34" H 7500 4900 60  0000 C CNN
+F 1 "d_and" H 7550 5000 60  0000 C CNN
+F 2 "" H 7500 4900 60  0000 C CNN
+F 3 "" H 7500 4900 60  0000 C CNN
+	1    7500 4900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 6965CB20
+P 5150 850
+F 0 "U7" H 5150 750 60  0000 C CNN
+F 1 "d_inverter" H 5150 1000 60  0000 C CNN
+F 2 "" H 5200 800 60  0000 C CNN
+F 3 "" H 5200 800 60  0000 C CNN
+	1    5150 850 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 6965CB21
+P 5150 1300
+F 0 "U8" H 5150 1200 60  0000 C CNN
+F 1 "d_inverter" H 5150 1450 60  0000 C CNN
+F 2 "" H 5200 1250 60  0000 C CNN
+F 3 "" H 5200 1250 60  0000 C CNN
+	1    5150 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 6965CB22
+P 5150 2050
+F 0 "U9" H 5150 1950 60  0000 C CNN
+F 1 "d_inverter" H 5150 2200 60  0000 C CNN
+F 2 "" H 5200 2000 60  0000 C CNN
+F 3 "" H 5200 2000 60  0000 C CNN
+	1    5150 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 6965CB23
+P 5150 2800
+F 0 "U10" H 5150 2700 60  0000 C CNN
+F 1 "d_inverter" H 5150 2950 60  0000 C CNN
+F 2 "" H 5200 2750 60  0000 C CNN
+F 3 "" H 5200 2750 60  0000 C CNN
+	1    5150 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 6965CB24
+P 5150 4400
+F 0 "U11" H 5150 4300 60  0000 C CNN
+F 1 "d_inverter" H 5150 4550 60  0000 C CNN
+F 2 "" H 5200 4350 60  0000 C CNN
+F 3 "" H 5200 4350 60  0000 C CNN
+	1    5150 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 6965CB25
+P 5150 4800
+F 0 "U12" H 5150 4700 60  0000 C CNN
+F 1 "d_inverter" H 5150 4950 60  0000 C CNN
+F 2 "" H 5200 4750 60  0000 C CNN
+F 3 "" H 5200 4750 60  0000 C CNN
+	1    5150 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 6965CB26
+P 5150 5500
+F 0 "U13" H 5150 5400 60  0000 C CNN
+F 1 "d_inverter" H 5150 5650 60  0000 C CNN
+F 2 "" H 5200 5450 60  0000 C CNN
+F 3 "" H 5200 5450 60  0000 C CNN
+	1    5150 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 6965CB27
+P 5150 6150
+F 0 "U14" H 5150 6050 60  0000 C CNN
+F 1 "d_inverter" H 5150 6300 60  0000 C CNN
+F 2 "" H 5200 6100 60  0000 C CNN
+F 3 "" H 5200 6100 60  0000 C CNN
+	1    5150 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U35
+U 1 1 6965CB28
+P 8500 900
+F 0 "U35" H 8500 900 60  0000 C CNN
+F 1 "d_or" H 8500 1000 60  0000 C CNN
+F 2 "" H 8500 900 60  0000 C CNN
+F 3 "" H 8500 900 60  0000 C CNN
+	1    8500 900 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U42
+U 1 1 6965CB29
+P 9800 1400
+F 0 "U42" H 9800 1400 60  0000 C CNN
+F 1 "d_or" H 9800 1500 60  0000 C CNN
+F 2 "" H 9800 1400 60  0000 C CNN
+F 3 "" H 9800 1400 60  0000 C CNN
+	1    9800 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U36
+U 1 1 6965CB2A
+P 8650 2950
+F 0 "U36" H 8650 2950 60  0000 C CNN
+F 1 "d_and" H 8700 3050 60  0000 C CNN
+F 2 "" H 8650 2950 60  0000 C CNN
+F 3 "" H 8650 2950 60  0000 C CNN
+	1    8650 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U38
+U 1 1 6965CB2B
+P 8700 2200
+F 0 "U38" H 8700 2200 60  0000 C CNN
+F 1 "d_or" H 8700 2300 60  0000 C CNN
+F 2 "" H 8700 2200 60  0000 C CNN
+F 3 "" H 8700 2200 60  0000 C CNN
+	1    8700 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U40
+U 1 1 6965CB2C
+P 8700 4500
+F 0 "U40" H 8700 4500 60  0000 C CNN
+F 1 "d_or" H 8700 4600 60  0000 C CNN
+F 2 "" H 8700 4500 60  0000 C CNN
+F 3 "" H 8700 4500 60  0000 C CNN
+	1    8700 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U37
+U 1 1 6965CB2D
+P 8650 6300
+F 0 "U37" H 8650 6300 60  0000 C CNN
+F 1 "d_and" H 8700 6400 60  0000 C CNN
+F 2 "" H 8650 6300 60  0000 C CNN
+F 3 "" H 8650 6300 60  0000 C CNN
+	1    8650 6300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U41
+U 1 1 6965CB2E
+P 8700 5600
+F 0 "U41" H 8700 5600 60  0000 C CNN
+F 1 "d_or" H 8700 5700 60  0000 C CNN
+F 2 "" H 8700 5600 60  0000 C CNN
+F 3 "" H 8700 5600 60  0000 C CNN
+	1    8700 5600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U43
+U 1 1 6965CB2F
+P 9900 5000
+F 0 "U43" H 9900 5000 60  0000 C CNN
+F 1 "d_or" H 9900 5100 60  0000 C CNN
+F 2 "" H 9900 5000 60  0000 C CNN
+F 3 "" H 9900 5000 60  0000 C CNN
+	1    9900 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U27
+U 1 1 6965CB30
+P 6950 3500
+F 0 "U27" H 6950 3500 60  0000 C CNN
+F 1 "d_and" H 7000 3600 60  0000 C CNN
+F 2 "" H 6950 3500 60  0000 C CNN
+F 3 "" H 6950 3500 60  0000 C CNN
+	1    6950 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U28
+U 1 1 6965CB31
+P 7000 4000
+F 0 "U28" H 7000 4000 60  0000 C CNN
+F 1 "d_and" H 7050 4100 60  0000 C CNN
+F 2 "" H 7000 4000 60  0000 C CNN
+F 3 "" H 7000 4000 60  0000 C CNN
+	1    7000 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U39
+U 1 1 6965CB32
+P 8700 3750
+F 0 "U39" H 8700 3750 60  0000 C CNN
+F 1 "d_and" H 8750 3850 60  0000 C CNN
+F 2 "" H 8700 3750 60  0000 C CNN
+F 3 "" H 8700 3750 60  0000 C CNN
+	1    8700 3750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2600 3000 2300 3000
+Wire Wire Line
+	2600 550  2600 4400
+Wire Wire Line
+	2600 2600 3200 2600
+Wire Wire Line
+	2650 3100 2300 3100
+Wire Wire Line
+	2650 2700 3200 2700
+Wire Wire Line
+	2700 3200 2300 3200
+Wire Wire Line
+	2700 1050 2700 4800
+Wire Wire Line
+	2700 3050 3200 3050
+Wire Wire Line
+	2800 3300 2300 3300
+Wire Wire Line
+	2800 1300 2800 4700
+Wire Wire Line
+	2800 3150 3200 3150
+Wire Wire Line
+	2300 3400 3000 3400
+Wire Wire Line
+	3000 1750 3000 5500
+Wire Wire Line
+	3000 3500 3150 3500
+Wire Wire Line
+	2300 3500 2900 3500
+Wire Wire Line
+	2900 2050 2900 5400
+Wire Wire Line
+	2900 3600 3150 3600
+Wire Wire Line
+	2300 3600 2400 3600
+Wire Wire Line
+	5450 6150 5800 6150
+Wire Wire Line
+	5450 5500 5800 5500
+Wire Wire Line
+	5450 4800 5800 4800
+Wire Wire Line
+	5450 4400 5800 4400
+Wire Wire Line
+	5450 2800 5750 2800
+Wire Wire Line
+	5450 2050 5750 2050
+Wire Wire Line
+	5450 1300 5750 1300
+Wire Wire Line
+	5450 850  5750 850 
+Wire Wire Line
+	7850 1350 7950 1350
+Wire Wire Line
+	7950 1350 7950 900 
+Wire Wire Line
+	7950 900  8050 900 
+Wire Wire Line
+	6650 800  8050 800 
+Wire Wire Line
+	7900 2100 8250 2100
+Wire Wire Line
+	9100 2900 9300 2900
+Wire Wire Line
+	9300 2900 9300 2600
+Wire Wire Line
+	9300 2600 8000 2600
+Wire Wire Line
+	8000 2600 8000 2200
+Wire Wire Line
+	8000 2200 8250 2200
+Wire Wire Line
+	7900 2850 8200 2850
+Wire Wire Line
+	8950 850  9350 850 
+Wire Wire Line
+	9350 850  9350 1300
+Wire Wire Line
+	9150 2150 9350 2150
+Wire Wire Line
+	9350 2150 9350 1400
+Wire Wire Line
+	7900 6200 8200 6200
+Wire Wire Line
+	9100 6250 9250 6250
+Wire Wire Line
+	9250 6250 9250 5950
+Wire Wire Line
+	9250 5950 8100 5950
+Wire Wire Line
+	8100 5950 8100 5600
+Wire Wire Line
+	8100 5600 8250 5600
+Wire Wire Line
+	7900 5550 8100 5550
+Wire Wire Line
+	8100 5550 8100 5500
+Wire Wire Line
+	8100 5500 8250 5500
+Wire Wire Line
+	9150 5550 9450 5550
+Wire Wire Line
+	9450 5550 9450 5000
+Wire Wire Line
+	9150 4450 9450 4450
+Wire Wire Line
+	9450 4450 9450 4900
+Wire Wire Line
+	7950 4850 8250 4850
+Wire Wire Line
+	8250 4850 8250 4500
+Wire Wire Line
+	6700 4350 8250 4350
+Wire Wire Line
+	8250 4350 8250 4400
+Wire Wire Line
+	8200 6300 8000 6300
+Wire Wire Line
+	8000 6300 8000 2950
+Wire Wire Line
+	8000 2950 8200 2950
+Wire Wire Line
+	4100 2650 4450 2650
+Wire Wire Line
+	4450 2650 4450 3400
+Wire Wire Line
+	4450 3400 6500 3400
+Wire Wire Line
+	4100 3100 4300 3100
+Wire Wire Line
+	4300 3100 4300 3500
+Wire Wire Line
+	4300 3500 6500 3500
+Wire Wire Line
+	4050 3550 4250 3550
+Wire Wire Line
+	4250 3550 4250 3900
+Wire Wire Line
+	4250 3900 6550 3900
+Wire Wire Line
+	4050 4150 6550 4150
+Wire Wire Line
+	6550 4150 6550 4000
+Wire Wire Line
+	7400 3450 8250 3450
+Wire Wire Line
+	8250 3450 8250 3650
+Wire Wire Line
+	7450 3950 8250 3950
+Wire Wire Line
+	8250 3950 8250 3750
+Wire Wire Line
+	6650 1250 6950 1250
+Wire Wire Line
+	6950 1250 6950 1300
+Wire Wire Line
+	5600 1500 6950 1500
+Wire Wire Line
+	6950 1500 6950 1400
+Wire Wire Line
+	6650 2000 7000 2000
+Wire Wire Line
+	7000 2000 7000 2050
+Wire Wire Line
+	6650 2250 7000 2250
+Wire Wire Line
+	7000 2250 7000 2150
+Wire Wire Line
+	6650 2750 7000 2750
+Wire Wire Line
+	7000 2750 7000 2800
+Wire Wire Line
+	6650 3000 7000 3000
+Wire Wire Line
+	7000 3000 7000 2900
+Wire Wire Line
+	6700 4750 7050 4750
+Wire Wire Line
+	7050 4750 7050 4800
+Wire Wire Line
+	5600 5000 7050 5000
+Wire Wire Line
+	7050 5000 7050 4900
+Wire Wire Line
+	6700 5450 7000 5450
+Wire Wire Line
+	7000 5450 7000 5500
+Wire Wire Line
+	6700 5700 7000 5700
+Wire Wire Line
+	7000 5700 7000 5600
+Wire Wire Line
+	6700 6100 7000 6100
+Wire Wire Line
+	7000 6100 7000 6150
+Wire Wire Line
+	6700 6350 7000 6350
+Wire Wire Line
+	7000 6350 7000 6250
+Wire Wire Line
+	2600 550  5750 550 
+Wire Wire Line
+	5750 550  5750 750 
+Connection ~ 2600 2600
+Wire Wire Line
+	2650 850  4850 850 
+Connection ~ 2650 2700
+Wire Wire Line
+	2700 1050 5750 1050
+Wire Wire Line
+	5750 1050 5750 1200
+Connection ~ 2700 3050
+Wire Wire Line
+	2800 1300 4850 1300
+Connection ~ 2800 3150
+Wire Wire Line
+	3000 1750 5750 1750
+Wire Wire Line
+	5750 1750 5750 1950
+Connection ~ 3000 3400
+Wire Wire Line
+	2900 2050 4850 2050
+Connection ~ 2900 3500
+Wire Wire Line
+	2400 3600 2400 3700
+Wire Wire Line
+	2400 3700 3150 3700
+Wire Wire Line
+	3150 2350 3150 6150
+Wire Wire Line
+	2300 3700 2350 3700
+Wire Wire Line
+	2350 3700 2350 3800
+Wire Wire Line
+	2350 3800 3100 3800
+Wire Wire Line
+	3100 2200 3100 6050
+Wire Wire Line
+	3100 4200 3150 4200
+Wire Wire Line
+	3150 2350 5750 2350
+Wire Wire Line
+	5750 2350 5750 2700
+Connection ~ 3150 3700
+Wire Wire Line
+	3100 2200 4850 2200
+Wire Wire Line
+	4850 2200 4850 2800
+Connection ~ 3100 3800
+Connection ~ 2600 3000
+Connection ~ 2650 3100
+Wire Wire Line
+	2600 4400 4850 4400
+Wire Wire Line
+	2650 850  2650 4300
+Wire Wire Line
+	2650 4300 5800 4300
+Wire Wire Line
+	2700 4800 4850 4800
+Connection ~ 2700 3200
+Wire Wire Line
+	2800 4700 5800 4700
+Connection ~ 2800 3300
+Wire Wire Line
+	3000 5500 4850 5500
+Connection ~ 3000 3500
+Wire Wire Line
+	2900 5400 5800 5400
+Connection ~ 2900 3600
+Wire Wire Line
+	3150 6150 4850 6150
+Connection ~ 3150 4100
+Wire Wire Line
+	3100 6050 5800 6050
+Connection ~ 3100 4200
+Wire Wire Line
+	5750 2200 5600 2200
+Wire Wire Line
+	5600 1500 5600 6300
+Wire Wire Line
+	5600 2950 5750 2950
+Connection ~ 5600 2200
+Connection ~ 5600 2950
+Wire Wire Line
+	5600 5650 5800 5650
+Connection ~ 5600 5000
+Wire Wire Line
+	5600 6300 5800 6300
+Connection ~ 5600 5650
+Wire Wire Line
+	5750 2300 5650 2300
+Wire Wire Line
+	5650 2300 5650 6400
+Wire Wire Line
+	5650 3050 5750 3050
+Wire Wire Line
+	5650 5750 5800 5750
+Connection ~ 5650 3050
+Wire Wire Line
+	5650 6400 5800 6400
+Connection ~ 5650 5750
+$Comp
+L dac_bridge_3 U44
+U 1 1 6965CB33
+P 11750 3250
+F 0 "U44" H 11750 3250 60  0000 C CNN
+F 1 "dac_bridge_3" H 11750 3400 60  0000 C CNN
+F 2 "" H 11750 3250 60  0000 C CNN
+F 3 "" H 11750 3250 60  0000 C CNN
+	1    11750 3250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9150 3700 10650 3700
+Wire Wire Line
+	10650 3700 10650 3300
+Wire Wire Line
+	10650 3300 11150 3300
+Wire Wire Line
+	10350 4950 10800 4950
+Wire Wire Line
+	10800 4950 10800 3400
+Wire Wire Line
+	10800 3400 11150 3400
+Wire Wire Line
+	10250 1350 10600 1350
+Wire Wire Line
+	10600 1350 10600 3200
+Wire Wire Line
+	10600 3200 11150 3200
+$Comp
+L PORT U1
+U 1 1 6965D9F4
+P 650 4050
+F 0 "U1" H 700 4150 30  0000 C CNN
+F 1 "PORT" H 650 4050 30  0000 C CNN
+F 2 "" H 650 4050 60  0000 C CNN
+F 3 "" H 650 4050 60  0000 C CNN
+	1    650  4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6965DA67
+P 650 3850
+F 0 "U1" H 700 3950 30  0000 C CNN
+F 1 "PORT" H 650 3850 30  0000 C CNN
+F 2 "" H 650 3850 60  0000 C CNN
+F 3 "" H 650 3850 60  0000 C CNN
+	2    650  3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6965DC22
+P 650 3650
+F 0 "U1" H 700 3750 30  0000 C CNN
+F 1 "PORT" H 650 3650 30  0000 C CNN
+F 2 "" H 650 3650 60  0000 C CNN
+F 3 "" H 650 3650 60  0000 C CNN
+	3    650  3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6965DCA1
+P 650 3450
+F 0 "U1" H 700 3550 30  0000 C CNN
+F 1 "PORT" H 650 3450 30  0000 C CNN
+F 2 "" H 650 3450 60  0000 C CNN
+F 3 "" H 650 3450 60  0000 C CNN
+	4    650  3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6965DD18
+P 650 3250
+F 0 "U1" H 700 3350 30  0000 C CNN
+F 1 "PORT" H 650 3250 30  0000 C CNN
+F 2 "" H 650 3250 60  0000 C CNN
+F 3 "" H 650 3250 60  0000 C CNN
+	5    650  3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6965DD9D
+P 650 3050
+F 0 "U1" H 700 3150 30  0000 C CNN
+F 1 "PORT" H 650 3050 30  0000 C CNN
+F 2 "" H 650 3050 60  0000 C CNN
+F 3 "" H 650 3050 60  0000 C CNN
+	6    650  3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6965DE16
+P 650 2850
+F 0 "U1" H 700 2950 30  0000 C CNN
+F 1 "PORT" H 650 2850 30  0000 C CNN
+F 2 "" H 650 2850 60  0000 C CNN
+F 3 "" H 650 2850 60  0000 C CNN
+	7    650  2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6965DE99
+P 650 2650
+F 0 "U1" H 700 2750 30  0000 C CNN
+F 1 "PORT" H 650 2650 30  0000 C CNN
+F 2 "" H 650 2650 60  0000 C CNN
+F 3 "" H 650 2650 60  0000 C CNN
+	8    650  2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6965E2C0
+P 12800 3300
+F 0 "U1" H 12850 3400 30  0000 C CNN
+F 1 "PORT" H 12800 3300 30  0000 C CNN
+F 2 "" H 12800 3300 60  0000 C CNN
+F 3 "" H 12800 3300 60  0000 C CNN
+	10   12800 3300
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6965E3F5
+P 12800 3500
+F 0 "U1" H 12850 3600 30  0000 C CNN
+F 1 "PORT" H 12800 3500 30  0000 C CNN
+F 2 "" H 12800 3500 60  0000 C CNN
+F 3 "" H 12800 3500 60  0000 C CNN
+	11   12800 3500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6965E482
+P 13800 3350
+F 0 "U1" H 13850 3450 30  0000 C CNN
+F 1 "PORT" H 13800 3350 30  0000 C CNN
+F 2 "" H 13800 3350 60  0000 C CNN
+F 3 "" H 13800 3350 60  0000 C CNN
+	12   13800 3350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6965EB15
+P 12800 3100
+F 0 "U1" H 12850 3200 30  0000 C CNN
+F 1 "PORT" H 12800 3100 30  0000 C CNN
+F 2 "" H 12800 3100 60  0000 C CNN
+F 3 "" H 12800 3100 60  0000 C CNN
+	9    12800 3100
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	900  2650 1100 2650
+Wire Wire Line
+	1100 2650 1100 3000
+Wire Wire Line
+	1100 3000 1150 3000
+Wire Wire Line
+	900  2850 1050 2850
+Wire Wire Line
+	1050 2850 1050 3100
+Wire Wire Line
+	1050 3100 1150 3100
+Wire Wire Line
+	900  3050 1000 3050
+Wire Wire Line
+	1000 3050 1000 3200
+Wire Wire Line
+	1000 3200 1150 3200
+Wire Wire Line
+	900  3250 950  3250
+Wire Wire Line
+	950  3250 950  3300
+Wire Wire Line
+	950  3300 1150 3300
+Wire Wire Line
+	900  3450 950  3450
+Wire Wire Line
+	950  3450 950  3400
+Wire Wire Line
+	950  3400 1150 3400
+Wire Wire Line
+	900  3650 1000 3650
+Wire Wire Line
+	1000 3650 1000 3500
+Wire Wire Line
+	1000 3500 1150 3500
+Wire Wire Line
+	900  3850 1050 3850
+Wire Wire Line
+	1050 3850 1050 3600
+Wire Wire Line
+	1050 3600 1150 3600
+Wire Wire Line
+	900  4050 1100 4050
+Wire Wire Line
+	1100 4050 1100 3700
+Wire Wire Line
+	1100 3700 1150 3700
+Wire Wire Line
+	12300 3200 12400 3200
+Wire Wire Line
+	12400 3200 12400 3100
+Wire Wire Line
+	12400 3100 12550 3100
+Wire Wire Line
+	12300 3300 12550 3300
+Wire Wire Line
+	12300 3400 12400 3400
+Wire Wire Line
+	12400 3400 12400 3500
+Wire Wire Line
+	12400 3500 12550 3500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC85/74HC85.sub b/library/SubcircuitLibrary/74HC85/74HC85.sub
new file mode 100644
index 000000000..43f4bc4ad
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85.sub
@@ -0,0 +1,178 @@
+* Subcircuit 74HC85
+.subckt 74HC85 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? 
+* c:\fossee\esim\library\subcircuitlibrary\74hc85\74hc85.cir
+* u5  net-_u11-pad1_ net-_u2-pad10_ net-_u27-pad1_ d_xor
+* u6  net-_u12-pad1_ net-_u2-pad12_ net-_u27-pad2_ d_xor
+* u3  net-_u13-pad1_ net-_u2-pad14_ net-_u28-pad1_ d_xor
+* u4  net-_u14-pad1_ net-_u10-pad1_ net-_u28-pad2_ d_xor
+* u2  net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u11-pad1_ net-_u2-pad10_ net-_u12-pad1_ net-_u2-pad12_ net-_u13-pad1_ net-_u2-pad14_ net-_u14-pad1_ net-_u10-pad1_ adc_bridge_8
+* u15  net-_u11-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16  net-_u12-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
+* u17  net-_u13-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
+* u21  net-_u2-pad10_ net-_u11-pad2_ net-_u21-pad3_ d_and
+* u22  net-_u2-pad12_ net-_u12-pad2_ net-_u22-pad3_ d_and
+* u23  net-_u2-pad14_ net-_u13-pad2_ net-_u23-pad3_ d_and
+* u18  net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
+* u19  net-_u14-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and
+* u20  net-_u18-pad1_ net-_u18-pad2_ net-_u20-pad3_ d_and
+* u29  net-_u16-pad3_ net-_u18-pad1_ net-_u29-pad3_ d_and
+* u30  net-_u17-pad3_ net-_u18-pad3_ net-_u30-pad3_ d_and
+* u31  net-_u19-pad3_ net-_u20-pad3_ net-_u31-pad3_ d_and
+* u24  net-_u18-pad1_ net-_u18-pad2_ net-_u24-pad3_ d_and
+* u25  net-_u10-pad1_ net-_u14-pad2_ net-_u25-pad3_ d_and
+* u26  net-_u18-pad1_ net-_u18-pad2_ net-_u26-pad3_ d_and
+* u33  net-_u25-pad3_ net-_u26-pad3_ net-_u33-pad3_ d_and
+* u32  net-_u23-pad3_ net-_u24-pad3_ net-_u32-pad3_ d_and
+* u34  net-_u22-pad3_ net-_u18-pad1_ net-_u34-pad3_ d_and
+* u7  net-_u2-pad10_ net-_u15-pad2_ d_inverter
+* u8  net-_u2-pad12_ net-_u16-pad2_ d_inverter
+* u9  net-_u2-pad14_ net-_u17-pad2_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12  net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14  net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u35  net-_u15-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or
+* u42  net-_u35-pad3_ net-_u38-pad3_ net-_u42-pad3_ d_or
+* u36  net-_u31-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_and
+* u38  net-_u30-pad3_ net-_u36-pad3_ net-_u38-pad3_ d_or
+* u40  net-_u21-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_or
+* u37  net-_u33-pad3_ net-_u36-pad2_ net-_u37-pad3_ d_and
+* u41  net-_u32-pad3_ net-_u37-pad3_ net-_u41-pad3_ d_or
+* u43  net-_u40-pad3_ net-_u41-pad3_ net-_u43-pad3_ d_or
+* u27  net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_and
+* u28  net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and
+* u39  net-_u27-pad3_ net-_u28-pad3_ net-_u39-pad3_ d_and
+* u44  net-_u42-pad3_ net-_u39-pad3_ net-_u43-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ dac_bridge_3
+a1 [net-_u11-pad1_ net-_u2-pad10_ ] net-_u27-pad1_ u5
+a2 [net-_u12-pad1_ net-_u2-pad12_ ] net-_u27-pad2_ u6
+a3 [net-_u13-pad1_ net-_u2-pad14_ ] net-_u28-pad1_ u3
+a4 [net-_u14-pad1_ net-_u10-pad1_ ] net-_u28-pad2_ u4
+a5 [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ ] [net-_u11-pad1_ net-_u2-pad10_ net-_u12-pad1_ net-_u2-pad12_ net-_u13-pad1_ net-_u2-pad14_ net-_u14-pad1_ net-_u10-pad1_ ] u2
+a6 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a7 [net-_u12-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a8 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a9 [net-_u2-pad10_ net-_u11-pad2_ ] net-_u21-pad3_ u21
+a10 [net-_u2-pad12_ net-_u12-pad2_ ] net-_u22-pad3_ u22
+a11 [net-_u2-pad14_ net-_u13-pad2_ ] net-_u23-pad3_ u23
+a12 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a13 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19
+a14 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u20-pad3_ u20
+a15 [net-_u16-pad3_ net-_u18-pad1_ ] net-_u29-pad3_ u29
+a16 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u30-pad3_ u30
+a17 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u31-pad3_ u31
+a18 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u25-pad3_ u25
+a20 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u26-pad3_ u26
+a21 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u33-pad3_ u33
+a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u32-pad3_ u32
+a23 [net-_u22-pad3_ net-_u18-pad1_ ] net-_u34-pad3_ u34
+a24 net-_u2-pad10_ net-_u15-pad2_ u7
+a25 net-_u2-pad12_ net-_u16-pad2_ u8
+a26 net-_u2-pad14_ net-_u17-pad2_ u9
+a27 net-_u10-pad1_ net-_u10-pad2_ u10
+a28 net-_u11-pad1_ net-_u11-pad2_ u11
+a29 net-_u12-pad1_ net-_u12-pad2_ u12
+a30 net-_u13-pad1_ net-_u13-pad2_ u13
+a31 net-_u14-pad1_ net-_u14-pad2_ u14
+a32 [net-_u15-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a33 [net-_u35-pad3_ net-_u38-pad3_ ] net-_u42-pad3_ u42
+a34 [net-_u31-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36
+a35 [net-_u30-pad3_ net-_u36-pad3_ ] net-_u38-pad3_ u38
+a36 [net-_u21-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40
+a37 [net-_u33-pad3_ net-_u36-pad2_ ] net-_u37-pad3_ u37
+a38 [net-_u32-pad3_ net-_u37-pad3_ ] net-_u41-pad3_ u41
+a39 [net-_u40-pad3_ net-_u41-pad3_ ] net-_u43-pad3_ u43
+a40 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a41 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a42 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u39-pad3_ u39
+a43 [net-_u42-pad3_ net-_u39-pad3_ net-_u43-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ] u44
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_3, NgSpice Name: dac_bridge
+.model u44 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends 74HC85
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC85/74HC85_Previous_Values.xml b/library/SubcircuitLibrary/74HC85/74HC85_Previous_Values.xml
new file mode 100644
index 000000000..9c0fa42d9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/74HC85_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u5 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_xor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u6><u3 name="type">d_xor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_xor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u2><u15 name="type">d_and<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_and<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u17><u21 name="type">d_and<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_and<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_and<field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /><field34 name="Enter Input Load (default=1.0e-12)" /></u23><u18 name="type">d_and<field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /><field37 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /><field40 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_and<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u20><u29 name="type">d_and<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_and<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_and<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u31><u24 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_and<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_and<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u26><u33 name="type">d_and<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u33><u32 name="type">d_and<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u32><u34 name="type">d_and<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u34><u7 name="type">d_inverter<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u14><u35 name="type">d_or<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u35><u42 name="type">d_or<field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /></u42><u36 name="type">d_and<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u36><u38 name="type">d_or<field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /><field106 name="Enter Input Load (default=1.0e-12)" /></u38><u40 name="type">d_or<field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /><field109 name="Enter Input Load (default=1.0e-12)" /></u40><u37 name="type">d_and<field110 name="Enter Rise Delay (default=1.0e-9)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /><field112 name="Enter Input Load (default=1.0e-12)" /></u37><u41 name="type">d_or<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u41><u43 name="type">d_or<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u43><u27 name="type">d_and<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_and<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u28><u39 name="type">d_and<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u39><u44 name="type">dac_bridge<field128 name="Enter value for out_low (default=0.0)" /><field129 name="Enter value for out_high (default=5.0)" /><field130 name="Enter value for out_undef (default=0.5)" /><field131 name="Enter value for input load (default=1.0e-12)" /><field132 name="Enter the Rise Time (default=1.0e-9)" /><field133 name="Enter the Fall Time (default=1.0e-9)" /></u44></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC85/analysis b/library/SubcircuitLibrary/74HC85/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC85/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD520b/CD520B.proj b/library/SubcircuitLibrary/CD520b/CD520B.proj
new file mode 100644
index 000000000..9f4f9f4f8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520B.proj
@@ -0,0 +1 @@
+schematicFile CD520B.sch
diff --git a/library/SubcircuitLibrary/CD520b/CD520b-cache.lib b/library/SubcircuitLibrary/CD520b/CD520b-cache.lib
new file mode 100644
index 000000000..5dcf7bb5e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b-cache.lib
@@ -0,0 +1,143 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_4
+#
+DEF dac_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD520b/CD520b.cir b/library/SubcircuitLibrary/CD520b/CD520b.cir
new file mode 100644
index 000000000..596f89da9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b.cir
@@ -0,0 +1,24 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD520b\CD520b.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 11/26/25 14:49:37
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  Net-_U7-Pad1_ Net-_U5-Pad3_ Net-_U1-Pad7_ Net-_U11-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad1_ d_dff		
+U9  Net-_U11-Pad2_ Net-_U7-Pad1_ Net-_U1-Pad7_ Net-_U11-Pad4_ Net-_U10-Pad1_ Net-_U11-Pad2_ d_dff		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U1-Pad7_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad1_ d_dff		
+U13  Net-_U13-Pad1_ Net-_U11-Pad1_ Net-_U1-Pad7_ Net-_U11-Pad4_ Net-_U13-Pad5_ Net-_U13-Pad1_ d_dff		
+U8  Net-_U7-Pad5_ Net-_U6-Pad1_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter		
+U12  Net-_U11-Pad5_ Net-_U12-Pad2_ d_inverter		
+U14  Net-_U13-Pad5_ Net-_U14-Pad2_ d_inverter		
+U5  Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U5-Pad3_ d_nand		
+U6  Net-_U6-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U14-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ dac_bridge_4		
+U2  Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U2-Pad3_ Net-_U2-Pad4_ adc_bridge_2		
+U3  Net-_U1-Pad1_ Net-_U3-Pad2_ adc_bridge_1		
+U4  Net-_U3-Pad2_ Net-_U11-Pad4_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD520b/CD520b.cir.out b/library/SubcircuitLibrary/CD520b/CD520b.cir.out
new file mode 100644
index 000000000..d7c89d723
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b.cir.out
@@ -0,0 +1,64 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd520b\cd520b.cir
+
+* u7  net-_u7-pad1_ net-_u5-pad3_ net-_u1-pad7_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad1_ d_dff
+* u9  net-_u11-pad2_ net-_u7-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u10-pad1_ net-_u11-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad7_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad1_ d_dff
+* u13  net-_u13-pad1_ net-_u11-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u13-pad5_ net-_u13-pad1_ d_dff
+* u8  net-_u7-pad5_ net-_u6-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u12  net-_u11-pad5_ net-_u12-pad2_ d_inverter
+* u14  net-_u13-pad5_ net-_u14-pad2_ d_inverter
+* u5  net-_u2-pad3_ net-_u2-pad4_ net-_u5-pad3_ d_nand
+* u6  net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ net-_u14-pad2_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ dac_bridge_4
+* u2  net-_u1-pad6_ net-_u1-pad8_ net-_u2-pad3_ net-_u2-pad4_ adc_bridge_2
+* u3  net-_u1-pad1_ net-_u3-pad2_ adc_bridge_1
+* u4  net-_u3-pad2_ net-_u11-pad4_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
+a1 net-_u7-pad1_ net-_u5-pad3_ net-_u1-pad7_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad1_ u7
+a2 net-_u11-pad2_ net-_u7-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u10-pad1_ net-_u11-pad2_ u9
+a3 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad7_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad1_ u11
+a4 net-_u13-pad1_ net-_u11-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u13-pad5_ net-_u13-pad1_ u13
+a5 net-_u7-pad5_ net-_u6-pad1_ u8
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad5_ net-_u12-pad2_ u12
+a8 net-_u13-pad5_ net-_u14-pad2_ u14
+a9 [net-_u2-pad3_ net-_u2-pad4_ ] net-_u5-pad3_ u5
+a10 [net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ net-_u14-pad2_ ] [net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ ] u6
+a11 [net-_u1-pad6_ net-_u1-pad8_ ] [net-_u2-pad3_ net-_u2-pad4_ ] u2
+a12 [net-_u1-pad1_ ] [net-_u3-pad2_ ] u3
+a13 net-_u3-pad2_ net-_u11-pad4_ u4
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD520b/CD520b.pro b/library/SubcircuitLibrary/CD520b/CD520b.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD520b/CD520b.sch b/library/SubcircuitLibrary/CD520b/CD520b.sch
new file mode 100644
index 000000000..758eade6b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b.sch
@@ -0,0 +1,475 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:test2-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U7
+U 1 1 6926C50A
+P 4150 2850
+F 0 "U7" H 4150 2850 60  0000 C CNN
+F 1 "d_dff" H 4150 3000 60  0000 C CNN
+F 2 "" H 4150 2850 60  0000 C CNN
+F 3 "" H 4150 2850 60  0000 C CNN
+	1    4150 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U9
+U 1 1 6926C50B
+P 5800 2850
+F 0 "U9" H 5800 2850 60  0000 C CNN
+F 1 "d_dff" H 5800 3000 60  0000 C CNN
+F 2 "" H 5800 2850 60  0000 C CNN
+F 3 "" H 5800 2850 60  0000 C CNN
+	1    5800 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U11
+U 1 1 6926C50C
+P 7550 2850
+F 0 "U11" H 7550 2850 60  0000 C CNN
+F 1 "d_dff" H 7550 3000 60  0000 C CNN
+F 2 "" H 7550 2850 60  0000 C CNN
+F 3 "" H 7550 2850 60  0000 C CNN
+	1    7550 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U13
+U 1 1 6926C50D
+P 9350 2850
+F 0 "U13" H 9350 2850 60  0000 C CNN
+F 1 "d_dff" H 9350 3000 60  0000 C CNN
+F 2 "" H 9350 2850 60  0000 C CNN
+F 3 "" H 9350 2850 60  0000 C CNN
+	1    9350 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 6926C50E
+P 4700 1950
+F 0 "U8" H 4700 1850 60  0000 C CNN
+F 1 "d_inverter" H 4700 2100 60  0000 C CNN
+F 2 "" H 4750 1900 60  0000 C CNN
+F 3 "" H 4750 1900 60  0000 C CNN
+	1    4700 1950
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 6926C50F
+P 6450 1950
+F 0 "U10" H 6450 1850 60  0000 C CNN
+F 1 "d_inverter" H 6450 2100 60  0000 C CNN
+F 2 "" H 6500 1900 60  0000 C CNN
+F 3 "" H 6500 1900 60  0000 C CNN
+	1    6450 1950
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 6926C510
+P 8150 1900
+F 0 "U12" H 8150 1800 60  0000 C CNN
+F 1 "d_inverter" H 8150 2050 60  0000 C CNN
+F 2 "" H 8200 1850 60  0000 C CNN
+F 3 "" H 8200 1850 60  0000 C CNN
+	1    8150 1900
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 6926C511
+P 10000 1850
+F 0 "U14" H 10000 1750 60  0000 C CNN
+F 1 "d_inverter" H 10000 2000 60  0000 C CNN
+F 2 "" H 10050 1800 60  0000 C CNN
+F 3 "" H 10050 1800 60  0000 C CNN
+	1    10000 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 6926C512
+P 3000 4100
+F 0 "U5" H 3000 4100 60  0000 C CNN
+F 1 "d_nand" H 3050 4200 60  0000 C CNN
+F 2 "" H 3000 4100 60  0000 C CNN
+F 3 "" H 3000 4100 60  0000 C CNN
+	1    3000 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_4 U6
+U 1 1 6926C513
+P 3200 1100
+F 0 "U6" H 3200 1100 60  0000 C CNN
+F 1 "dac_bridge_4" H 3200 1400 60  0000 C CNN
+F 2 "" H 3200 1100 60  0000 C CNN
+F 3 "" H 3200 1100 60  0000 C CNN
+	1    3200 1100
+	-1   0    0    1   
+$EndComp
+$Comp
+L adc_bridge_2 U2
+U 1 1 6926C51D
+P 1750 4950
+F 0 "U2" H 1750 4950 60  0000 C CNN
+F 1 "adc_bridge_2" H 1750 5100 60  0000 C CNN
+F 2 "" H 1750 4950 60  0000 C CNN
+F 3 "" H 1750 4950 60  0000 C CNN
+	1    1750 4950
+	-1   0    0    1   
+$EndComp
+$Comp
+L adc_bridge_1 U3
+U 1 1 6926C524
+P 2150 2200
+F 0 "U3" H 2150 2200 60  0000 C CNN
+F 1 "adc_bridge_1" H 2150 2350 60  0000 C CNN
+F 2 "" H 2150 2200 60  0000 C CNN
+F 3 "" H 2150 2200 60  0000 C CNN
+	1    2150 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 6926C525
+P 3000 2800
+F 0 "U4" H 3000 2700 60  0000 C CNN
+F 1 "d_inverter" H 3000 2950 60  0000 C CNN
+F 2 "" H 3050 2750 60  0000 C CNN
+F 3 "" H 3050 2750 60  0000 C CNN
+	1    3000 2800
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	3600 2500 3300 2500
+Wire Wire Line
+	3300 2500 3300 3700
+Wire Wire Line
+	3300 3700 4850 3700
+Wire Wire Line
+	4850 3150 4700 3150
+Wire Wire Line
+	5250 2500 5000 2500
+Wire Wire Line
+	5000 2500 5000 3700
+Wire Wire Line
+	5000 3700 6600 3700
+Wire Wire Line
+	6600 3150 6350 3150
+Wire Wire Line
+	7000 2500 6750 2500
+Wire Wire Line
+	6750 2500 6750 3700
+Wire Wire Line
+	6750 3700 8400 3700
+Wire Wire Line
+	8400 3150 8100 3150
+Wire Wire Line
+	8800 2500 8500 2500
+Wire Wire Line
+	8500 2500 8500 3700
+Wire Wire Line
+	8500 3700 10200 3700
+Wire Wire Line
+	10200 3700 10200 3150
+Wire Wire Line
+	10200 3150 9900 3150
+Wire Wire Line
+	4700 2250 4700 2500
+Wire Wire Line
+	6450 2250 6450 2500
+Wire Wire Line
+	6450 2500 6350 2500
+Wire Wire Line
+	8150 2200 8150 2500
+Wire Wire Line
+	8150 2500 8100 2500
+Wire Wire Line
+	10000 2150 10000 2500
+Wire Wire Line
+	10000 2500 9900 2500
+Wire Wire Line
+	3600 3150 3500 3150
+Wire Wire Line
+	1050 4100 2550 4100
+Wire Wire Line
+	7550 3450 7550 3550
+Wire Wire Line
+	3000 3550 9350 3550
+Wire Wire Line
+	9350 3550 9350 3450
+Wire Wire Line
+	5800 3450 5800 3550
+Connection ~ 7550 3550
+Wire Wire Line
+	4150 3450 4150 3550
+Connection ~ 5800 3550
+Wire Wire Line
+	5250 3150 5250 4050
+Wire Wire Line
+	4700 1650 4700 1450
+Wire Wire Line
+	7000 3150 7000 3900
+Wire Wire Line
+	8800 3150 8800 3900
+Connection ~ 3500 4050
+Connection ~ 6600 3700
+Connection ~ 8400 3700
+Wire Wire Line
+	3750 1300 4800 1300
+Wire Wire Line
+	4800 1300 4800 1450
+Connection ~ 4800 1450
+Wire Wire Line
+	3750 1100 8150 1100
+Wire Wire Line
+	8150 1100 8150 1600
+Wire Wire Line
+	3750 1000 10000 1000
+Wire Wire Line
+	10000 1000 10000 1550
+Wire Wire Line
+	2350 5000 2950 5000
+Wire Wire Line
+	2350 4900 3850 4900
+Wire Wire Line
+	1200 4900 1050 4900
+Wire Wire Line
+	1050 4900 1050 4100
+Wire Wire Line
+	1200 5000 900  5000
+Wire Wire Line
+	900  5000 900  3600
+Wire Wire Line
+	900  3600 2300 3600
+Wire Wire Line
+	2300 3600 2300 4000
+Wire Wire Line
+	2300 4000 2550 4000
+Wire Wire Line
+	1050 2150 1550 2150
+Wire Wire Line
+	2700 2150 3000 2150
+Connection ~ 4150 3550
+Wire Wire Line
+	3000 3100 3000 3550
+Wire Wire Line
+	3000 2150 3000 2500
+Wire Wire Line
+	6450 1200 6450 1650
+Wire Wire Line
+	3750 1200 6450 1200
+Connection ~ 6450 1450
+Connection ~ 5250 3750
+Wire Wire Line
+	4800 1450 4700 1450
+Connection ~ 4850 3700
+Wire Wire Line
+	3450 4050 3500 4050
+Wire Wire Line
+	4850 3150 4850 4050
+Wire Wire Line
+	4850 4050 5250 4050
+Wire Wire Line
+	6600 3150 6600 3900
+Wire Wire Line
+	6600 3900 7000 3900
+Wire Wire Line
+	8400 3150 8400 3900
+Wire Wire Line
+	8400 3900 8800 3900
+Wire Wire Line
+	3500 4050 3500 3150
+Wire Wire Line
+	9350 2200 8300 2200
+Wire Wire Line
+	8300 2200 8300 2300
+Wire Wire Line
+	8300 2300 7750 2300
+Wire Wire Line
+	7750 2300 7750 2200
+Wire Wire Line
+	7750 2200 6800 2200
+Wire Wire Line
+	5150 2200 6200 2200
+Wire Wire Line
+	6200 2200 6200 2350
+Wire Wire Line
+	6200 2350 6800 2350
+Wire Wire Line
+	6800 2350 6800 2200
+Connection ~ 7550 2200
+Wire Wire Line
+	3900 2200 4500 2200
+Wire Wire Line
+	4500 2200 4500 2350
+Wire Wire Line
+	4500 2350 5150 2350
+Wire Wire Line
+	5150 2350 5150 2200
+Connection ~ 5800 2200
+$Comp
+L PORT U1
+U 7 1 6926CEAB
+P 3650 2200
+F 0 "U1" H 3700 2300 30  0000 C CNN
+F 1 "PORT" H 3650 2200 30  0000 C CNN
+F 2 "" H 3650 2200 60  0000 C CNN
+F 3 "" H 3650 2200 60  0000 C CNN
+	7    3650 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6926CFC6
+P 4100 4900
+F 0 "U1" H 4150 5000 30  0000 C CNN
+F 1 "PORT" H 4100 4900 30  0000 C CNN
+F 2 "" H 4100 4900 60  0000 C CNN
+F 3 "" H 4100 4900 60  0000 C CNN
+	8    4100 4900
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6926D028
+P 3200 5000
+F 0 "U1" H 3250 5100 30  0000 C CNN
+F 1 "PORT" H 3200 5000 30  0000 C CNN
+F 2 "" H 3200 5000 60  0000 C CNN
+F 3 "" H 3200 5000 60  0000 C CNN
+	6    3200 5000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6926D097
+P 800 2150
+F 0 "U1" H 850 2250 30  0000 C CNN
+F 1 "PORT" H 800 2150 30  0000 C CNN
+F 2 "" H 800 2150 60  0000 C CNN
+F 3 "" H 800 2150 60  0000 C CNN
+	1    800  2150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6926D13E
+P 2050 1500
+F 0 "U1" H 2100 1600 30  0000 C CNN
+F 1 "PORT" H 2050 1500 30  0000 C CNN
+F 2 "" H 2050 1500 60  0000 C CNN
+F 3 "" H 2050 1500 60  0000 C CNN
+	5    2050 1500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6926D1A1
+P 2050 1300
+F 0 "U1" H 2100 1400 30  0000 C CNN
+F 1 "PORT" H 2050 1300 30  0000 C CNN
+F 2 "" H 2050 1300 60  0000 C CNN
+F 3 "" H 2050 1300 60  0000 C CNN
+	4    2050 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6926D1E6
+P 2050 1100
+F 0 "U1" H 2100 1200 30  0000 C CNN
+F 1 "PORT" H 2050 1100 30  0000 C CNN
+F 2 "" H 2050 1100 60  0000 C CNN
+F 3 "" H 2050 1100 60  0000 C CNN
+	3    2050 1100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6926D231
+P 2050 900
+F 0 "U1" H 2100 1000 30  0000 C CNN
+F 1 "PORT" H 2050 900 30  0000 C CNN
+F 2 "" H 2050 900 60  0000 C CNN
+F 3 "" H 2050 900 60  0000 C CNN
+	2    2050 900 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2300 900  2650 900 
+Wire Wire Line
+	2650 900  2650 1000
+Wire Wire Line
+	2300 1100 2650 1100
+Wire Wire Line
+	2300 1300 2450 1300
+Wire Wire Line
+	2450 1300 2450 1200
+Wire Wire Line
+	2450 1200 2650 1200
+Wire Wire Line
+	2300 1500 2550 1500
+Wire Wire Line
+	2550 1500 2550 1300
+Wire Wire Line
+	2550 1300 2650 1300
+Connection ~ 4150 2200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD520b/CD520b.sub b/library/SubcircuitLibrary/CD520b/CD520b.sub
new file mode 100644
index 000000000..c59e5d6f2
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b.sub
@@ -0,0 +1,58 @@
+* Subcircuit CD520b
+.subckt CD520b net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
+* c:\fossee\esim\library\subcircuitlibrary\cd520b\cd520b.cir
+* u7  net-_u7-pad1_ net-_u5-pad3_ net-_u1-pad7_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad1_ d_dff
+* u9  net-_u11-pad2_ net-_u7-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u10-pad1_ net-_u11-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad7_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad1_ d_dff
+* u13  net-_u13-pad1_ net-_u11-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u13-pad5_ net-_u13-pad1_ d_dff
+* u8  net-_u7-pad5_ net-_u6-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u12  net-_u11-pad5_ net-_u12-pad2_ d_inverter
+* u14  net-_u13-pad5_ net-_u14-pad2_ d_inverter
+* u5  net-_u2-pad3_ net-_u2-pad4_ net-_u5-pad3_ d_nand
+* u6  net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ net-_u14-pad2_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ dac_bridge_4
+* u2  net-_u1-pad6_ net-_u1-pad8_ net-_u2-pad3_ net-_u2-pad4_ adc_bridge_2
+* u3  net-_u1-pad1_ net-_u3-pad2_ adc_bridge_1
+* u4  net-_u3-pad2_ net-_u11-pad4_ d_inverter
+a1 net-_u7-pad1_ net-_u5-pad3_ net-_u1-pad7_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad1_ u7
+a2 net-_u11-pad2_ net-_u7-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u10-pad1_ net-_u11-pad2_ u9
+a3 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad7_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad1_ u11
+a4 net-_u13-pad1_ net-_u11-pad1_ net-_u1-pad7_ net-_u11-pad4_ net-_u13-pad5_ net-_u13-pad1_ u13
+a5 net-_u7-pad5_ net-_u6-pad1_ u8
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad5_ net-_u12-pad2_ u12
+a8 net-_u13-pad5_ net-_u14-pad2_ u14
+a9 [net-_u2-pad3_ net-_u2-pad4_ ] net-_u5-pad3_ u5
+a10 [net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ net-_u14-pad2_ ] [net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ ] u6
+a11 [net-_u1-pad6_ net-_u1-pad8_ ] [net-_u2-pad3_ net-_u2-pad4_ ] u2
+a12 [net-_u1-pad1_ ] [net-_u3-pad2_ ] u3
+a13 net-_u3-pad2_ net-_u11-pad4_ u4
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=4 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends CD520b
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD520b/CD520b_Previous_Values.xml b/library/SubcircuitLibrary/CD520b/CD520b_Previous_Values.xml
new file mode 100644
index 000000000..1eaad65b7
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/CD520b_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u7 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">d_dff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for Data Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u9><u11 name="type">d_dff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for Data Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u11><u13 name="type">d_dff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for Data Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u13><u8 name="type">d_inverter<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_inverter<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_inverter<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_inverter<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u14><u5 name="type">d_nand<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">dac_bridge<field56 name="Enter value for out_low (default=0.0)" /><field57 name="Enter value for out_high (default=5.0)" /><field58 name="Enter value for out_undef (default=0.5)" /><field59 name="Enter value for input load (default=1.0e-12)" /><field60 name="Enter the Rise Time (default=1.0e-9)" /><field61 name="Enter the Fall Time (default=1.0e-9)" /></u6><u2 name="type">adc_bridge<field62 name="Enter value for in_low (default=1.0)" /><field63 name="Enter value for in_high (default=2.0)">4</field63><field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">adc_bridge<field66 name="Enter value for in_low (default=1.0)" /><field67 name="Enter value for in_high (default=2.0)">4</field67><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD520b/analysis b/library/SubcircuitLibrary/CD520b/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD520b/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LS90/74LS90-cache.lib b/library/SubcircuitLibrary/LS90/74LS90-cache.lib
new file mode 100644
index 000000000..b519a8e26
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90-cache.lib
@@ -0,0 +1,160 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_jkff
+#
+DEF d_jkff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_jkff" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 600 550 -600 -600 0 1 0 N
+X J 1 -800 400 200 R 50 50 1 1 I
+X K 2 -800 -450 200 R 50 50 1 1 I
+X Clk 3 -800 0 200 R 50 50 1 1 I C
+X Set 4 0 750 200 D 50 50 1 1 I
+X Reset 5 0 -800 200 U 50 50 1 1 I
+X Out 6 800 400 200 L 50 50 1 1 O
+X Nout 7 800 -450 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_srff
+#
+DEF d_srff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_srff" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 600 550 -600 -600 0 1 0 N
+X S 1 -800 400 200 R 50 50 1 1 I
+X R 2 -800 -450 200 R 50 50 1 1 I
+X Clk 3 -800 0 200 R 50 50 1 1 I C
+X Set 4 0 750 200 D 50 50 1 1 I
+X Reset 5 0 -800 200 U 50 50 1 1 I
+X Out 6 800 400 200 L 50 50 1 1 O
+X Nout 7 800 -450 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LS90/74LS90.cir b/library/SubcircuitLibrary/LS90/74LS90.cir
new file mode 100644
index 000000000..2ed393f7c
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90.cir
@@ -0,0 +1,26 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74LS90\74LS90.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 11/24/25 17:57:37
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  ? ? Net-_U5-Pad2_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U7-Pad6_ ? d_jkff		
+U12  ? ? Net-_U10-Pad6_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U12-Pad6_ ? d_jkff		
+U10  Net-_U10-Pad1_ ? Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ ? d_jkff		
+U3  Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U10-Pad5_ d_nand		
+U6  Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U10-Pad4_ d_nand		
+U15  Net-_U14-Pad3_ Net-_U15-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U15-Pad2_ Net-_U10-Pad1_ d_srff		
+U5  Net-_U1-Pad1_ Net-_U5-Pad2_ adc_bridge_1		
+U8  Net-_U1-Pad6_ Net-_U10-Pad3_ adc_bridge_1		
+U14  Net-_U10-Pad6_ Net-_U12-Pad6_ Net-_U14-Pad3_ d_and		
+U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ Net-_U2-Pad4_ adc_bridge_2		
+U4  Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_U3-Pad1_ Net-_U3-Pad2_ adc_bridge_2		
+U9  Net-_U7-Pad6_ Net-_U1-Pad7_ dac_bridge_1		
+U11  Net-_U10-Pad6_ Net-_U1-Pad8_ dac_bridge_1		
+U16  Net-_U15-Pad2_ Net-_U1-Pad10_ dac_bridge_1		
+U13  Net-_U12-Pad6_ Net-_U1-Pad9_ dac_bridge_1		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/LS90/74LS90.cir.out b/library/SubcircuitLibrary/LS90/74LS90.cir.out
new file mode 100644
index 000000000..909f85f29
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90.cir.out
@@ -0,0 +1,72 @@
+* c:\fossee\esim\library\subcircuitlibrary\74ls90\74ls90.cir
+
+* u7  ? ? net-_u5-pad2_ net-_u10-pad4_ net-_u10-pad5_ net-_u7-pad6_ ? d_jkff
+* u12  ? ? net-_u10-pad6_ net-_u10-pad4_ net-_u10-pad5_ net-_u12-pad6_ ? d_jkff
+* u10  net-_u10-pad1_ ? net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ? d_jkff
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u10-pad5_ d_nand
+* u6  net-_u2-pad3_ net-_u2-pad4_ net-_u10-pad4_ d_nand
+* u15  net-_u14-pad3_ net-_u15-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u15-pad2_ net-_u10-pad1_ d_srff
+* u5  net-_u1-pad1_ net-_u5-pad2_ adc_bridge_1
+* u8  net-_u1-pad6_ net-_u10-pad3_ adc_bridge_1
+* u14  net-_u10-pad6_ net-_u12-pad6_ net-_u14-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ net-_u2-pad4_ adc_bridge_2
+* u4  net-_u1-pad3_ net-_u1-pad5_ net-_u3-pad1_ net-_u3-pad2_ adc_bridge_2
+* u9  net-_u7-pad6_ net-_u1-pad7_ dac_bridge_1
+* u11  net-_u10-pad6_ net-_u1-pad8_ dac_bridge_1
+* u16  net-_u15-pad2_ net-_u1-pad10_ dac_bridge_1
+* u13  net-_u12-pad6_ net-_u1-pad9_ dac_bridge_1
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port
+a1 ? ? net-_u5-pad2_ net-_u10-pad4_ net-_u10-pad5_ net-_u7-pad6_ ? u7
+a2 ? ? net-_u10-pad6_ net-_u10-pad4_ net-_u10-pad5_ net-_u12-pad6_ ? u12
+a3 net-_u10-pad1_ ? net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ? u10
+a4 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u10-pad5_ u3
+a5 [net-_u2-pad3_ net-_u2-pad4_ ] net-_u10-pad4_ u6
+a6 net-_u14-pad3_ net-_u15-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u15-pad2_ net-_u10-pad1_ u15
+a7 [net-_u1-pad1_ ] [net-_u5-pad2_ ] u5
+a8 [net-_u1-pad6_ ] [net-_u10-pad3_ ] u8
+a9 [net-_u10-pad6_ net-_u12-pad6_ ] net-_u14-pad3_ u14
+a10 [net-_u1-pad2_ net-_u1-pad4_ ] [net-_u2-pad3_ net-_u2-pad4_ ] u2
+a11 [net-_u1-pad3_ net-_u1-pad5_ ] [net-_u3-pad1_ net-_u3-pad2_ ] u4
+a12 [net-_u7-pad6_ ] [net-_u1-pad7_ ] u9
+a13 [net-_u10-pad6_ ] [net-_u1-pad8_ ] u11
+a14 [net-_u15-pad2_ ] [net-_u1-pad10_ ] u16
+a15 [net-_u12-pad6_ ] [net-_u1-pad9_ ] u13
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u7 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u12 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u10 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u15 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LS90/74LS90.pro b/library/SubcircuitLibrary/LS90/74LS90.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LS90/74LS90.sch b/library/SubcircuitLibrary/LS90/74LS90.sch
new file mode 100644
index 000000000..bfce193c0
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90.sch
@@ -0,0 +1,494 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:ls90-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_jkff U7
+U 1 1 69244D7F
+P 2900 2900
+F 0 "U7" H 2900 2900 60  0000 C CNN
+F 1 "d_jkff" H 2950 3050 60  0000 C CNN
+F 2 "" H 2900 2900 60  0000 C CNN
+F 3 "" H 2900 2900 60  0000 C CNN
+	1    2900 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_jkff U12
+U 1 1 69244D80
+P 7650 3000
+F 0 "U12" H 7650 3000 60  0000 C CNN
+F 1 "d_jkff" H 7700 3150 60  0000 C CNN
+F 2 "" H 7650 3000 60  0000 C CNN
+F 3 "" H 7650 3000 60  0000 C CNN
+	1    7650 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_jkff U10
+U 1 1 69244D81
+P 5200 2950
+F 0 "U10" H 5200 2950 60  0000 C CNN
+F 1 "d_jkff" H 5250 3100 60  0000 C CNN
+F 2 "" H 5200 2950 60  0000 C CNN
+F 3 "" H 5200 2950 60  0000 C CNN
+	1    5200 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U3
+U 1 1 69244D82
+P 1400 4350
+F 0 "U3" H 1400 4350 60  0000 C CNN
+F 1 "d_nand" H 1450 4450 60  0000 C CNN
+F 2 "" H 1400 4350 60  0000 C CNN
+F 3 "" H 1400 4350 60  0000 C CNN
+	1    1400 4350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U6
+U 1 1 69244D83
+P 2350 1150
+F 0 "U6" H 2350 1150 60  0000 C CNN
+F 1 "d_nand" H 2400 1250 60  0000 C CNN
+F 2 "" H 2350 1150 60  0000 C CNN
+F 3 "" H 2350 1150 60  0000 C CNN
+	1    2350 1150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2900 1100 2900 2150
+Wire Wire Line
+	5200 1100 5200 2200
+Connection ~ 2900 1100
+Wire Wire Line
+	7650 1100 7650 2250
+Connection ~ 5200 1100
+Wire Wire Line
+	10050 1100 10050 2250
+Connection ~ 7650 1100
+Wire Wire Line
+	1850 4300 10050 4300
+Wire Wire Line
+	2900 4300 2900 3700
+Wire Wire Line
+	5200 4300 5200 3750
+Connection ~ 2900 4300
+Wire Wire Line
+	7650 4300 7650 3800
+Connection ~ 5200 4300
+Wire Wire Line
+	10050 4300 10050 3800
+Connection ~ 7650 4300
+Wire Wire Line
+	9250 3000 8900 3000
+Wire Wire Line
+	8900 3000 8900 5000
+Wire Wire Line
+	4400 2950 4250 2950
+Wire Wire Line
+	4250 2950 4250 5000
+Wire Wire Line
+	8900 5000 3750 5000
+$Comp
+L d_srff U15
+U 1 1 69244D84
+P 10050 3000
+F 0 "U15" H 10050 3000 60  0000 C CNN
+F 1 "d_srff" H 10100 3150 60  0000 C CNN
+F 2 "" H 10050 3000 60  0000 C CNN
+F 3 "" H 10050 3000 60  0000 C CNN
+	1    10050 3000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4400 2550 4100 2550
+Wire Wire Line
+	4100 2550 4100 5250
+Wire Wire Line
+	11000 5250 11000 3450
+Wire Wire Line
+	11000 3450 10850 3450
+Wire Wire Line
+	6000 2550 6650 2550
+Wire Wire Line
+	6200 3000 6850 3000
+$Comp
+L adc_bridge_1 U5
+U 1 1 69244D86
+P 1500 2950
+F 0 "U5" H 1500 2950 60  0000 C CNN
+F 1 "adc_bridge_1" H 1500 3100 60  0000 C CNN
+F 2 "" H 1500 2950 60  0000 C CNN
+F 3 "" H 1500 2950 60  0000 C CNN
+	1    1500 2950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2050 2900 2100 2900
+$Comp
+L adc_bridge_1 U8
+U 1 1 69244D88
+P 3200 5050
+F 0 "U8" H 3200 5050 60  0000 C CNN
+F 1 "adc_bridge_1" H 3200 5200 60  0000 C CNN
+F 2 "" H 3200 5050 60  0000 C CNN
+F 3 "" H 3200 5050 60  0000 C CNN
+	1    3200 5050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2600 5000 2350 5000
+Wire Wire Line
+	2350 5000 2350 5150
+Wire Wire Line
+	4100 5250 11000 5250
+Connection ~ 4250 5000
+Wire Wire Line
+	4500 1900 4650 1900
+Connection ~ 6200 2550
+$Comp
+L d_and U14
+U 1 1 69244D8D
+P 9050 2100
+F 0 "U14" H 9050 2100 60  0000 C CNN
+F 1 "d_and" H 9100 2200 60  0000 C CNN
+F 2 "" H 9050 2100 60  0000 C CNN
+F 3 "" H 9050 2100 60  0000 C CNN
+	1    9050 2100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6650 2550 6650 2000
+Wire Wire Line
+	6650 2000 8600 2000
+Wire Wire Line
+	9250 2600 9000 2600
+Wire Wire Line
+	9000 2600 9000 2300
+Wire Wire Line
+	9000 2300 9850 2300
+Wire Wire Line
+	9850 2300 9850 2050
+Wire Wire Line
+	9850 2050 9500 2050
+Wire Wire Line
+	9250 3450 9050 3450
+Wire Wire Line
+	9050 3450 9050 3950
+Wire Wire Line
+	9050 3950 11050 3950
+Wire Wire Line
+	11050 2600 10850 2600
+Connection ~ 11050 2600
+$Comp
+L adc_bridge_2 U2
+U 1 1 69244D90
+P 1250 1100
+F 0 "U2" H 1250 1100 60  0000 C CNN
+F 1 "adc_bridge_2" H 1250 1250 60  0000 C CNN
+F 2 "" H 1250 1100 60  0000 C CNN
+F 3 "" H 1250 1100 60  0000 C CNN
+	1    1250 1100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2800 1100 10050 1100
+Wire Wire Line
+	1900 1050 1800 1050
+Wire Wire Line
+	1900 1150 1800 1150
+$Comp
+L adc_bridge_2 U4
+U 1 1 69244D91
+P 1450 5100
+F 0 "U4" H 1450 5100 60  0000 C CNN
+F 1 "adc_bridge_2" H 1450 5250 60  0000 C CNN
+F 2 "" H 1450 5100 60  0000 C CNN
+F 3 "" H 1450 5100 60  0000 C CNN
+	1    1450 5100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2000 5050 2150 5050
+Wire Wire Line
+	2150 5050 2150 4800
+Wire Wire Line
+	2150 4800 650  4800
+Wire Wire Line
+	650  4800 650  4250
+Wire Wire Line
+	650  4250 950  4250
+Wire Wire Line
+	2000 5150 2250 5150
+Wire Wire Line
+	2250 5150 2250 4700
+Wire Wire Line
+	2250 4700 750  4700
+Wire Wire Line
+	750  4700 750  4350
+Wire Wire Line
+	750  4350 950  4350
+Wire Wire Line
+	850  5050 550  5050
+Wire Wire Line
+	550  5050 550  5500
+Wire Wire Line
+	550  5500 900  5500
+Wire Wire Line
+	850  5150 750  5150
+Wire Wire Line
+	750  5150 750  5350
+Wire Wire Line
+	750  5350 1550 5350
+Wire Wire Line
+	750  1600 450  1600
+Wire Wire Line
+	450  1600 450  1050
+Wire Wire Line
+	450  1050 650  1050
+Wire Wire Line
+	650  1150 550  1150
+Wire Wire Line
+	550  1150 550  1500
+Wire Wire Line
+	550  1500 1300 1500
+$Comp
+L dac_bridge_1 U9
+U 1 1 69244D9A
+P 3950 1950
+F 0 "U9" H 3950 1950 60  0000 C CNN
+F 1 "dac_bridge_1" H 3950 2100 60  0000 C CNN
+F 2 "" H 3950 1950 60  0000 C CNN
+F 3 "" H 3950 1950 60  0000 C CNN
+	1    3950 1950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3350 1900 3200 1900
+Wire Wire Line
+	3200 1900 3200 2200
+Wire Wire Line
+	3200 2200 3900 2200
+Wire Wire Line
+	3900 2200 3900 2500
+Wire Wire Line
+	3900 2500 3700 2500
+$Comp
+L dac_bridge_1 U11
+U 1 1 69244D9B
+P 6800 1750
+F 0 "U11" H 6800 1750 60  0000 C CNN
+F 1 "dac_bridge_1" H 6800 1900 60  0000 C CNN
+F 2 "" H 6800 1750 60  0000 C CNN
+F 3 "" H 6800 1750 60  0000 C CNN
+	1    6800 1750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6200 1700 6200 3000
+Wire Wire Line
+	7350 1700 7500 1700
+Wire Wire Line
+	8600 2100 8550 2100
+Wire Wire Line
+	8550 2100 8550 2600
+Wire Wire Line
+	8550 2600 8450 2600
+Wire Wire Line
+	11050 3950 11050 2350
+$Comp
+L dac_bridge_1 U16
+U 1 1 69245575
+P 11100 1750
+F 0 "U16" H 11100 1750 60  0000 C CNN
+F 1 "dac_bridge_1" H 11100 1900 60  0000 C CNN
+F 2 "" H 11100 1750 60  0000 C CNN
+F 3 "" H 11100 1750 60  0000 C CNN
+	1    11100 1750
+	0    -1   -1   0   
+$EndComp
+$Comp
+L dac_bridge_1 U13
+U 1 1 6924568D
+P 8700 1600
+F 0 "U13" H 8700 1600 60  0000 C CNN
+F 1 "dac_bridge_1" H 8700 1750 60  0000 C CNN
+F 2 "" H 8700 1600 60  0000 C CNN
+F 3 "" H 8700 1600 60  0000 C CNN
+	1    8700 1600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8100 1550 8000 1550
+Wire Wire Line
+	8000 1550 8000 2250
+Wire Wire Line
+	8000 2250 8550 2250
+Connection ~ 8550 2250
+$Comp
+L PORT U1
+U 2 1 692457C8
+P 1000 1600
+F 0 "U1" H 1050 1700 30  0000 C CNN
+F 1 "PORT" H 1000 1600 30  0000 C CNN
+F 2 "" H 1000 1600 60  0000 C CNN
+F 3 "" H 1000 1600 60  0000 C CNN
+	2    1000 1600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 69245997
+P 1550 1500
+F 0 "U1" H 1600 1600 30  0000 C CNN
+F 1 "PORT" H 1550 1500 30  0000 C CNN
+F 2 "" H 1550 1500 60  0000 C CNN
+F 3 "" H 1550 1500 60  0000 C CNN
+	4    1550 1500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 69245A68
+P 600 2900
+F 0 "U1" H 650 3000 30  0000 C CNN
+F 1 "PORT" H 600 2900 30  0000 C CNN
+F 2 "" H 600 2900 60  0000 C CNN
+F 3 "" H 600 2900 60  0000 C CNN
+	1    600  2900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	850  2900 900  2900
+$Comp
+L PORT U1
+U 7 1 69245DC2
+P 4900 1900
+F 0 "U1" H 4950 2000 30  0000 C CNN
+F 1 "PORT" H 4900 1900 30  0000 C CNN
+F 2 "" H 4900 1900 60  0000 C CNN
+F 3 "" H 4900 1900 60  0000 C CNN
+	7    4900 1900
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 69245FF7
+P 7750 1700
+F 0 "U1" H 7800 1800 30  0000 C CNN
+F 1 "PORT" H 7750 1700 30  0000 C CNN
+F 2 "" H 7750 1700 60  0000 C CNN
+F 3 "" H 7750 1700 60  0000 C CNN
+	8    7750 1700
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6924619A
+P 1150 5500
+F 0 "U1" H 1200 5600 30  0000 C CNN
+F 1 "PORT" H 1150 5500 30  0000 C CNN
+F 2 "" H 1150 5500 60  0000 C CNN
+F 3 "" H 1150 5500 60  0000 C CNN
+	3    1150 5500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 692461F8
+P 1800 5350
+F 0 "U1" H 1850 5450 30  0000 C CNN
+F 1 "PORT" H 1800 5350 30  0000 C CNN
+F 2 "" H 1800 5350 60  0000 C CNN
+F 3 "" H 1800 5350 60  0000 C CNN
+	5    1800 5350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6924634B
+P 2600 5150
+F 0 "U1" H 2650 5250 30  0000 C CNN
+F 1 "PORT" H 2600 5150 30  0000 C CNN
+F 2 "" H 2600 5150 60  0000 C CNN
+F 3 "" H 2600 5150 60  0000 C CNN
+	6    2600 5150
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 692469DB
+P 9500 1550
+F 0 "U1" H 9550 1650 30  0000 C CNN
+F 1 "PORT" H 9500 1550 30  0000 C CNN
+F 2 "" H 9500 1550 60  0000 C CNN
+F 3 "" H 9500 1550 60  0000 C CNN
+	9    9500 1550
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 69246E26
+P 10800 1200
+F 0 "U1" H 10850 1300 30  0000 C CNN
+F 1 "PORT" H 10800 1200 30  0000 C CNN
+F 2 "" H 10800 1200 60  0000 C CNN
+F 3 "" H 10800 1200 60  0000 C CNN
+	10   10800 1200
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LS90/74LS90.sub b/library/SubcircuitLibrary/LS90/74LS90.sub
new file mode 100644
index 000000000..99ee20c09
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90.sub
@@ -0,0 +1,66 @@
+* Subcircuit 74LS90
+.subckt 74LS90 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ 
+* c:\fossee\esim\library\subcircuitlibrary\74ls90\74ls90.cir
+* u7  ? ? net-_u5-pad2_ net-_u10-pad4_ net-_u10-pad5_ net-_u7-pad6_ ? d_jkff
+* u12  ? ? net-_u10-pad6_ net-_u10-pad4_ net-_u10-pad5_ net-_u12-pad6_ ? d_jkff
+* u10  net-_u10-pad1_ ? net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ? d_jkff
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u10-pad5_ d_nand
+* u6  net-_u2-pad3_ net-_u2-pad4_ net-_u10-pad4_ d_nand
+* u15  net-_u14-pad3_ net-_u15-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u15-pad2_ net-_u10-pad1_ d_srff
+* u5  net-_u1-pad1_ net-_u5-pad2_ adc_bridge_1
+* u8  net-_u1-pad6_ net-_u10-pad3_ adc_bridge_1
+* u14  net-_u10-pad6_ net-_u12-pad6_ net-_u14-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ net-_u2-pad4_ adc_bridge_2
+* u4  net-_u1-pad3_ net-_u1-pad5_ net-_u3-pad1_ net-_u3-pad2_ adc_bridge_2
+* u9  net-_u7-pad6_ net-_u1-pad7_ dac_bridge_1
+* u11  net-_u10-pad6_ net-_u1-pad8_ dac_bridge_1
+* u16  net-_u15-pad2_ net-_u1-pad10_ dac_bridge_1
+* u13  net-_u12-pad6_ net-_u1-pad9_ dac_bridge_1
+a1 ? ? net-_u5-pad2_ net-_u10-pad4_ net-_u10-pad5_ net-_u7-pad6_ ? u7
+a2 ? ? net-_u10-pad6_ net-_u10-pad4_ net-_u10-pad5_ net-_u12-pad6_ ? u12
+a3 net-_u10-pad1_ ? net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ? u10
+a4 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u10-pad5_ u3
+a5 [net-_u2-pad3_ net-_u2-pad4_ ] net-_u10-pad4_ u6
+a6 net-_u14-pad3_ net-_u15-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u15-pad2_ net-_u10-pad1_ u15
+a7 [net-_u1-pad1_ ] [net-_u5-pad2_ ] u5
+a8 [net-_u1-pad6_ ] [net-_u10-pad3_ ] u8
+a9 [net-_u10-pad6_ net-_u12-pad6_ ] net-_u14-pad3_ u14
+a10 [net-_u1-pad2_ net-_u1-pad4_ ] [net-_u2-pad3_ net-_u2-pad4_ ] u2
+a11 [net-_u1-pad3_ net-_u1-pad5_ ] [net-_u3-pad1_ net-_u3-pad2_ ] u4
+a12 [net-_u7-pad6_ ] [net-_u1-pad7_ ] u9
+a13 [net-_u10-pad6_ ] [net-_u1-pad8_ ] u11
+a14 [net-_u15-pad2_ ] [net-_u1-pad10_ ] u16
+a15 [net-_u12-pad6_ ] [net-_u1-pad9_ ] u13
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u7 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u12 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_jkff, NgSpice Name: d_jkff
+.model u10 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_srff, NgSpice Name: d_srff
+.model u15 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends 74LS90
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LS90/74LS90_Previous_Values.xml b/library/SubcircuitLibrary/LS90/74LS90_Previous_Values.xml
new file mode 100644
index 000000000..b34083c0d
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/74LS90_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u7 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u7><u12 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u12><u10 name="type">d_jkff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for JK Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u10><u3 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u6><u15 name="type">d_srff<field37 name="Enter Clk Delay (default=1.0e-9)" /><field38 name="Enter Set Delay (default=1.0e-9)" /><field39 name="Enter Reset Delay (default=1.0)" /><field40 name="Enter IC (default=0)" /><field41 name="Enter value for SR Load (default=1.0e-12)" /><field42 name="Enter value for Clk Load (default=1.0e-12)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter value for Reset Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /></u15><u5 name="type">adc_bridge<field47 name="Enter value for in_low (default=1.0)" /><field48 name="Enter value for in_high (default=2.0)">5</field48><field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /></u5><u8 name="type">adc_bridge<field51 name="Enter value for in_low (default=1.0)" /><field52 name="Enter value for in_high (default=2.0)">5</field52><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /></u8><u14 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u14><u2 name="type">adc_bridge<field58 name="Enter value for in_low (default=1.0)" /><field59 name="Enter value for in_high (default=2.0)">5</field59><field60 name="Enter Rise Delay (default=1.0e-9)" /><field61 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">adc_bridge<field62 name="Enter value for in_low (default=1.0)" /><field63 name="Enter value for in_high (default=2.0)">5</field63><field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /></u4><u9 name="type">dac_bridge<field66 name="Enter value for out_low (default=0.0)" /><field67 name="Enter value for out_high (default=5.0)" /><field68 name="Enter value for out_undef (default=0.5)" /><field69 name="Enter value for input load (default=1.0e-12)" /><field70 name="Enter the Rise Time (default=1.0e-9)" /><field71 name="Enter the Fall Time (default=1.0e-9)" /></u9><u11 name="type">dac_bridge<field72 name="Enter value for out_low (default=0.0)" /><field73 name="Enter value for out_high (default=5.0)" /><field74 name="Enter value for out_undef (default=0.5)" /><field75 name="Enter value for input load (default=1.0e-12)" /><field76 name="Enter the Rise Time (default=1.0e-9)" /><field77 name="Enter the Fall Time (default=1.0e-9)" /></u11><u16 name="type">dac_bridge<field78 name="Enter value for out_low (default=0.0)" /><field79 name="Enter value for out_high (default=5.0)" /><field80 name="Enter value for out_undef (default=0.5)" /><field81 name="Enter value for input load (default=1.0e-12)" /><field82 name="Enter the Rise Time (default=1.0e-9)" /><field83 name="Enter the Fall Time (default=1.0e-9)" /></u16><u13 name="type">dac_bridge<field84 name="Enter value for out_low (default=0.0)" /><field85 name="Enter value for out_high (default=5.0)" /><field86 name="Enter value for out_undef (default=0.5)" /><field87 name="Enter value for input load (default=1.0e-12)" /><field88 name="Enter the Rise Time (default=1.0e-9)" /><field89 name="Enter the Fall Time (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LS90/analysis b/library/SubcircuitLibrary/LS90/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/LS90/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file