diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.cir b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.cir
new file mode 100644
index 000000000..66fc460af
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+U9 Net-_U1-Pad5_ Net-_U13-Pad2_ d_inverter
+U4 Net-_U1-Pad9_ Net-_U11-Pad1_ d_inverter
+U7 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter
+U8 Net-_U1-Pad13_ Net-_U12-Pad2_ d_inverter
+U5 Net-_U1-Pad12_ Net-_U12-Pad1_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U3 Net-_U1-Pad2_ Net-_U10-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter
+U6 Net-_U1-Pad4_ Net-_U13-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nor
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor
+U14 Net-_U10-Pad3_ Net-_U1-Pad3_ d_inverter
+U17 Net-_U13-Pad3_ Net-_U1-Pad6_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U16 Net-_U12-Pad3_ Net-_U1-Pad11_ d_inverter
+U15 Net-_U11-Pad3_ Net-_U1-Pad8_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.cir.out b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.cir.out
new file mode 100644
index 000000000..a08fb9c53
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.cir.out
@@ -0,0 +1,76 @@
+.title kicad schematic
+
+* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad9_ net-_u11-pad1_ d_inverter
+* u7 net-_u1-pad10_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u12-pad1_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u3 net-_u1-pad2_ net-_u10-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u6 net-_u1-pad4_ net-_u13-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u14 net-_u10-pad3_ net-_u1-pad3_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad6_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u16 net-_u12-pad3_ net-_u1-pad11_ d_inverter
+* u15 net-_u11-pad3_ net-_u1-pad8_ d_inverter
+a1 net-_u1-pad5_ net-_u13-pad2_ u9
+a2 net-_u1-pad9_ net-_u11-pad1_ u4
+a3 net-_u1-pad10_ net-_u11-pad2_ u7
+a4 net-_u1-pad13_ net-_u12-pad2_ u8
+a5 net-_u1-pad12_ net-_u12-pad1_ u5
+a6 net-_u1-pad2_ net-_u10-pad2_ u3
+a7 net-_u1-pad1_ net-_u10-pad1_ u2
+a8 net-_u1-pad4_ net-_u13-pad1_ u6
+a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a10 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a11 net-_u10-pad3_ net-_u1-pad3_ u14
+a12 net-_u13-pad3_ net-_u1-pad6_ u17
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a15 net-_u12-pad3_ net-_u1-pad11_ u16
+a16 net-_u11-pad3_ net-_u1-pad8_ u15
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.kicad_sch b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.kicad_sch
new file mode 100644
index 000000000..2dc47b761
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.kicad_sch
@@ -0,0 +1,1504 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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+    (pin "5" (uuid f2d238c3-c533-472b-9c25-729e507b92fa))
+    (pin "6" (uuid 877f7865-2e4d-490c-b1e0-4025848b915a))
+    (pin "7" (uuid 45479a02-e354-4bd9-a053-3bdd060bf859))
+    (pin "8" (uuid 2b5a393f-234b-418b-8382-d913319a489f))
+    (pin "9" (uuid adab0527-b433-4d54-bd0b-8e632d17b326))
+    (pin "10" (uuid a7f390f5-7d9d-488b-aaa3-df4e8a47fd71))
+    (pin "11" (uuid 418d20c3-0e7a-47dc-83a0-720d3510f63f))
+    (pin "12" (uuid b1ba3da3-0994-4a2e-8fe3-6b85ec63aa03))
+    (pin "13" (uuid 71286d83-4b6f-4cf4-abe9-3fedd459bc31))
+    (pin "14" (uuid 97245f02-165d-4639-bce0-86b42225badc))
+    (pin "15" (uuid 4e404b3d-fd77-4814-822a-67737006f064))
+    (pin "16" (uuid 0914cc6e-459f-4d74-b17a-34680f9fc3bc))
+    (pin "17" (uuid c5290a9d-ad87-4cd3-8154-fbd482242234))
+    (pin "18" (uuid 3ab481bb-5494-4e5a-a8c7-e6fb933c702d))
+    (pin "19" (uuid 22baceab-283c-4f8d-853e-1a9c0e862314))
+    (pin "20" (uuid efa87e26-5cd6-44a5-9ddd-60f146261741))
+    (pin "21" (uuid 7e10306c-8d49-4241-b78a-ec792953ffe4))
+    (pin "22" (uuid de2154f8-368e-409a-a2a2-ed607eb3a3a8))
+    (pin "23" (uuid 543191ed-504c-495a-ad50-7791206ccebb))
+    (pin "24" (uuid 065679f2-0b96-401d-967f-115859191515))
+    (pin "25" (uuid 8b7bde45-ec07-4cdc-bc19-f4f8ca8e02b1))
+    (pin "26" (uuid 2acb65e2-20ca-427f-bbdd-98b9e7cf57b0))
+  )
+
+  (symbol (lib_id "eSim_Miscellaneous:PORT") (at 48.895 46.355 0) (unit 2)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f9525c0e-dfd7-4783-a72f-b17961cc6176)
+    (property "Reference" "U1" (id 0) (at 49.53 41.91 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Value" "PORT" (id 1) (at 49.53 44.45 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Footprint" "" (id 2) (at 48.895 46.355 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 48.895 46.355 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 0797454c-5e95-41af-93a1-f5a5273aa3fd))
+    (pin "2" (uuid 1222545e-2635-4d4c-bb9d-211ae25b415d))
+    (pin "3" (uuid 4903a448-089d-4f40-8c7c-e6df00b94a0a))
+    (pin "4" (uuid e678a2ed-7715-4d7e-8174-3cf06ea7fb5c))
+    (pin "5" (uuid 56026fc5-4821-4a48-9b84-775dadce3a59))
+    (pin "6" (uuid 4f3fcce6-837d-4054-b0fc-fa7063d51154))
+    (pin "7" (uuid 4263bc44-68cd-4e88-884f-343ca58656c2))
+    (pin "8" (uuid 4a1bd0f0-f51f-486a-a08a-67d7e5004153))
+    (pin "9" (uuid 6fffb48a-8387-49eb-8e3f-2bb2fd603363))
+    (pin "10" (uuid aacd11bc-9bde-4a03-aae4-bde2ffabd484))
+    (pin "11" (uuid 677a5859-295d-4f3c-90fe-e71166d77f73))
+    (pin "12" (uuid 48ae6870-bbfe-42b1-a1eb-28a1447d242d))
+    (pin "13" (uuid 23d1e0c0-f8f1-4aab-a76c-3a0963e0c958))
+    (pin "14" (uuid 6539c8f7-4da1-4fde-ac5c-7c09efb9c565))
+    (pin "15" (uuid e258e0b2-eff7-4ff7-bb5c-030d9d216e70))
+    (pin "16" (uuid ba21ef9d-12dd-48e8-b2e2-cade26b579f7))
+    (pin "17" (uuid 5ae413b0-5542-47df-8aff-1ecc94a2ce57))
+    (pin "18" (uuid e6a1ef4b-54df-40bc-9212-24ee2c241d6b))
+    (pin "19" (uuid 92ae9133-8aaa-458d-8239-91fcc838f384))
+    (pin "20" (uuid 221efd6a-0255-478e-b76d-4915b319f651))
+    (pin "21" (uuid d065e423-adfe-4cfa-8d20-d371187ed95a))
+    (pin "22" (uuid 439045c7-caae-4bc4-aca7-98215d81e11b))
+    (pin "23" (uuid 26893d1d-5a36-4acc-b27a-75dd1a236de9))
+    (pin "24" (uuid 70e0c370-e7df-4a6a-b9a2-d1c2d4274612))
+    (pin "25" (uuid 48bda12c-8d6c-4558-8535-fcf4b7c0da4a))
+    (pin "26" (uuid a4cdc9cf-0bba-4b12-a7ac-0ef756bf4ec6))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/7eb5c9f5-551d-4327-bf56-85576febd59a"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/a7a71067-45f2-4ea9-a654-d68a8f878533"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/7cd14f5f-3d8f-4163-b4b1-5e5df8b0a175"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/f9525c0e-dfd7-4783-a72f-b17961cc6176"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/e84252f0-1425-4088-af08-0d99c4652573"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/ca5e1a7e-9375-4a44-87a0-5ffb72fad886"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/4586937d-82c1-485d-8729-cc502c126694"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/1d6b660b-5749-4598-bb2f-1713feaf462e"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/4b423cc8-98be-44a4-ae32-e8f73d281fb4"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/463e0108-0db7-4447-a14b-4f137207d2ff"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/ad8aa295-0307-4cf2-8741-07183c6ce00b"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/9ea42e8c-1d4d-42f6-ad2a-f82a4bac207b"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/010bd60a-25cf-4a95-a9b4-a27d5921c0ac"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/0f487a5f-ca90-443a-8b26-fe7d9a45613f"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/13694810-12b2-48e2-8f05-c052b924d2a5"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/4587ad98-a58a-4d7a-81f6-aafe0145d45e"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/55e57318-fa93-4ea8-9acd-5a563a3f379b"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/dae827d5-f728-4ed4-bb22-68c08c13fdb4"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5ca7b100-943e-4aac-9a06-efaaec72c6fa"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/89f22c4d-347f-4b84-8002-958dbe15b8fd"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/b3f59df7-c59a-414a-bb12-8e20e6e09bc3"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/65bd34f1-882e-427c-acdb-b416c5149d88"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1df60684-6d63-4467-9a0c-e44c46800ed2"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c129fd14-c481-4898-8f27-11d73f91b13a"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8159241f-5c72-43a5-8ccd-d81721180b4f"
+      (reference "U10") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b86c4970-8fe8-4ec1-b640-cdf372ad640b"
+      (reference "U11") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/060e624a-9937-463c-9822-c256483cfdc7"
+      (reference "U12") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/44843df8-23d3-4da4-a090-17a977e57298"
+      (reference "U13") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b1e82f59-c715-4b82-93a1-4dc91bb206df"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9493e4cf-2eeb-4cba-9ce7-4fbc74b7ea5e"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8a4498be-5471-4a56-af53-708fb93195d5"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/766ceae5-484d-4ea8-9fd8-e56192237332"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.sub b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.sub
new file mode 100644
index 000000000..3bd3de818
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00.sub
@@ -0,0 +1,70 @@
+* Subcircuit 74HC00
+.subckt 74HC00 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad9_ net-_u11-pad1_ d_inverter
+* u7 net-_u1-pad10_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u12-pad1_ d_inverter
+* u3 net-_u1-pad2_ net-_u10-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u6 net-_u1-pad4_ net-_u13-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u14 net-_u10-pad3_ net-_u1-pad3_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad6_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u16 net-_u12-pad3_ net-_u1-pad11_ d_inverter
+* u15 net-_u11-pad3_ net-_u1-pad8_ d_inverter
+a1 net-_u1-pad5_ net-_u13-pad2_ u9
+a2 net-_u1-pad9_ net-_u11-pad1_ u4
+a3 net-_u1-pad10_ net-_u11-pad2_ u7
+a4 net-_u1-pad13_ net-_u12-pad2_ u8
+a5 net-_u1-pad12_ net-_u12-pad1_ u5
+a6 net-_u1-pad2_ net-_u10-pad2_ u3
+a7 net-_u1-pad1_ net-_u10-pad1_ u2
+a8 net-_u1-pad4_ net-_u13-pad1_ u6
+a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a10 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a11 net-_u10-pad3_ net-_u1-pad3_ u14
+a12 net-_u13-pad3_ net-_u1-pad6_ u17
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a15 net-_u12-pad3_ net-_u1-pad11_ u16
+a16 net-_u11-pad3_ net-_u1-pad8_ u15
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Previous_Values.xml
new file mode 100644
index 000000000..e9af746f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u9 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u9><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u8><u5 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u5><u3 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u6><u11 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u14><u17 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u13><u10 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u10><u16 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u15 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.cir b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.cir
new file mode 100644
index 000000000..66fc460af
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+U9 Net-_U1-Pad5_ Net-_U13-Pad2_ d_inverter
+U4 Net-_U1-Pad9_ Net-_U11-Pad1_ d_inverter
+U7 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter
+U8 Net-_U1-Pad13_ Net-_U12-Pad2_ d_inverter
+U5 Net-_U1-Pad12_ Net-_U12-Pad1_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U3 Net-_U1-Pad2_ Net-_U10-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter
+U6 Net-_U1-Pad4_ Net-_U13-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nor
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor
+U14 Net-_U10-Pad3_ Net-_U1-Pad3_ d_inverter
+U17 Net-_U13-Pad3_ Net-_U1-Pad6_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U16 Net-_U12-Pad3_ Net-_U1-Pad11_ d_inverter
+U15 Net-_U11-Pad3_ Net-_U1-Pad8_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.cir.out b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.cir.out
new file mode 100644
index 000000000..a08fb9c53
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.cir.out
@@ -0,0 +1,76 @@
+.title kicad schematic
+
+* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad9_ net-_u11-pad1_ d_inverter
+* u7 net-_u1-pad10_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u12-pad1_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u3 net-_u1-pad2_ net-_u10-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u6 net-_u1-pad4_ net-_u13-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u14 net-_u10-pad3_ net-_u1-pad3_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad6_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u16 net-_u12-pad3_ net-_u1-pad11_ d_inverter
+* u15 net-_u11-pad3_ net-_u1-pad8_ d_inverter
+a1 net-_u1-pad5_ net-_u13-pad2_ u9
+a2 net-_u1-pad9_ net-_u11-pad1_ u4
+a3 net-_u1-pad10_ net-_u11-pad2_ u7
+a4 net-_u1-pad13_ net-_u12-pad2_ u8
+a5 net-_u1-pad12_ net-_u12-pad1_ u5
+a6 net-_u1-pad2_ net-_u10-pad2_ u3
+a7 net-_u1-pad1_ net-_u10-pad1_ u2
+a8 net-_u1-pad4_ net-_u13-pad1_ u6
+a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a10 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a11 net-_u10-pad3_ net-_u1-pad3_ u14
+a12 net-_u13-pad3_ net-_u1-pad6_ u17
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a15 net-_u12-pad3_ net-_u1-pad11_ u16
+a16 net-_u11-pad3_ net-_u1-pad8_ u15
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.kicad_sch b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.kicad_sch
new file mode 100644
index 000000000..2dc47b761
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.kicad_sch
@@ -0,0 +1,1504 @@
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+    (pin "2" (uuid 94cd5c0d-553d-40c3-b124-5e5ef665c9fc))
+    (pin "3" (uuid 9bbfab0a-c672-4221-821d-57fe24f1f732))
+    (pin "4" (uuid f1d468b7-6ca0-4cee-b751-e6f544aa9e4e))
+    (pin "5" (uuid f2d238c3-c533-472b-9c25-729e507b92fa))
+    (pin "6" (uuid 877f7865-2e4d-490c-b1e0-4025848b915a))
+    (pin "7" (uuid 45479a02-e354-4bd9-a053-3bdd060bf859))
+    (pin "8" (uuid 2b5a393f-234b-418b-8382-d913319a489f))
+    (pin "9" (uuid adab0527-b433-4d54-bd0b-8e632d17b326))
+    (pin "10" (uuid a7f390f5-7d9d-488b-aaa3-df4e8a47fd71))
+    (pin "11" (uuid 418d20c3-0e7a-47dc-83a0-720d3510f63f))
+    (pin "12" (uuid b1ba3da3-0994-4a2e-8fe3-6b85ec63aa03))
+    (pin "13" (uuid 71286d83-4b6f-4cf4-abe9-3fedd459bc31))
+    (pin "14" (uuid 97245f02-165d-4639-bce0-86b42225badc))
+    (pin "15" (uuid 4e404b3d-fd77-4814-822a-67737006f064))
+    (pin "16" (uuid 0914cc6e-459f-4d74-b17a-34680f9fc3bc))
+    (pin "17" (uuid c5290a9d-ad87-4cd3-8154-fbd482242234))
+    (pin "18" (uuid 3ab481bb-5494-4e5a-a8c7-e6fb933c702d))
+    (pin "19" (uuid 22baceab-283c-4f8d-853e-1a9c0e862314))
+    (pin "20" (uuid efa87e26-5cd6-44a5-9ddd-60f146261741))
+    (pin "21" (uuid 7e10306c-8d49-4241-b78a-ec792953ffe4))
+    (pin "22" (uuid de2154f8-368e-409a-a2a2-ed607eb3a3a8))
+    (pin "23" (uuid 543191ed-504c-495a-ad50-7791206ccebb))
+    (pin "24" (uuid 065679f2-0b96-401d-967f-115859191515))
+    (pin "25" (uuid 8b7bde45-ec07-4cdc-bc19-f4f8ca8e02b1))
+    (pin "26" (uuid 2acb65e2-20ca-427f-bbdd-98b9e7cf57b0))
+  )
+
+  (symbol (lib_id "eSim_Miscellaneous:PORT") (at 48.895 46.355 0) (unit 2)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f9525c0e-dfd7-4783-a72f-b17961cc6176)
+    (property "Reference" "U1" (id 0) (at 49.53 41.91 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Value" "PORT" (id 1) (at 49.53 44.45 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Footprint" "" (id 2) (at 48.895 46.355 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 48.895 46.355 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 0797454c-5e95-41af-93a1-f5a5273aa3fd))
+    (pin "2" (uuid 1222545e-2635-4d4c-bb9d-211ae25b415d))
+    (pin "3" (uuid 4903a448-089d-4f40-8c7c-e6df00b94a0a))
+    (pin "4" (uuid e678a2ed-7715-4d7e-8174-3cf06ea7fb5c))
+    (pin "5" (uuid 56026fc5-4821-4a48-9b84-775dadce3a59))
+    (pin "6" (uuid 4f3fcce6-837d-4054-b0fc-fa7063d51154))
+    (pin "7" (uuid 4263bc44-68cd-4e88-884f-343ca58656c2))
+    (pin "8" (uuid 4a1bd0f0-f51f-486a-a08a-67d7e5004153))
+    (pin "9" (uuid 6fffb48a-8387-49eb-8e3f-2bb2fd603363))
+    (pin "10" (uuid aacd11bc-9bde-4a03-aae4-bde2ffabd484))
+    (pin "11" (uuid 677a5859-295d-4f3c-90fe-e71166d77f73))
+    (pin "12" (uuid 48ae6870-bbfe-42b1-a1eb-28a1447d242d))
+    (pin "13" (uuid 23d1e0c0-f8f1-4aab-a76c-3a0963e0c958))
+    (pin "14" (uuid 6539c8f7-4da1-4fde-ac5c-7c09efb9c565))
+    (pin "15" (uuid e258e0b2-eff7-4ff7-bb5c-030d9d216e70))
+    (pin "16" (uuid ba21ef9d-12dd-48e8-b2e2-cade26b579f7))
+    (pin "17" (uuid 5ae413b0-5542-47df-8aff-1ecc94a2ce57))
+    (pin "18" (uuid e6a1ef4b-54df-40bc-9212-24ee2c241d6b))
+    (pin "19" (uuid 92ae9133-8aaa-458d-8239-91fcc838f384))
+    (pin "20" (uuid 221efd6a-0255-478e-b76d-4915b319f651))
+    (pin "21" (uuid d065e423-adfe-4cfa-8d20-d371187ed95a))
+    (pin "22" (uuid 439045c7-caae-4bc4-aca7-98215d81e11b))
+    (pin "23" (uuid 26893d1d-5a36-4acc-b27a-75dd1a236de9))
+    (pin "24" (uuid 70e0c370-e7df-4a6a-b9a2-d1c2d4274612))
+    (pin "25" (uuid 48bda12c-8d6c-4558-8535-fcf4b7c0da4a))
+    (pin "26" (uuid a4cdc9cf-0bba-4b12-a7ac-0ef756bf4ec6))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/7eb5c9f5-551d-4327-bf56-85576febd59a"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/a7a71067-45f2-4ea9-a654-d68a8f878533"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/7cd14f5f-3d8f-4163-b4b1-5e5df8b0a175"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/f9525c0e-dfd7-4783-a72f-b17961cc6176"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/e84252f0-1425-4088-af08-0d99c4652573"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/ca5e1a7e-9375-4a44-87a0-5ffb72fad886"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/4586937d-82c1-485d-8729-cc502c126694"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/1d6b660b-5749-4598-bb2f-1713feaf462e"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/4b423cc8-98be-44a4-ae32-e8f73d281fb4"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/463e0108-0db7-4447-a14b-4f137207d2ff"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/ad8aa295-0307-4cf2-8741-07183c6ce00b"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/9ea42e8c-1d4d-42f6-ad2a-f82a4bac207b"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/010bd60a-25cf-4a95-a9b4-a27d5921c0ac"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/0f487a5f-ca90-443a-8b26-fe7d9a45613f"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/13694810-12b2-48e2-8f05-c052b924d2a5"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/4587ad98-a58a-4d7a-81f6-aafe0145d45e"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/55e57318-fa93-4ea8-9acd-5a563a3f379b"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/dae827d5-f728-4ed4-bb22-68c08c13fdb4"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5ca7b100-943e-4aac-9a06-efaaec72c6fa"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/89f22c4d-347f-4b84-8002-958dbe15b8fd"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/b3f59df7-c59a-414a-bb12-8e20e6e09bc3"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/65bd34f1-882e-427c-acdb-b416c5149d88"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1df60684-6d63-4467-9a0c-e44c46800ed2"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c129fd14-c481-4898-8f27-11d73f91b13a"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8159241f-5c72-43a5-8ccd-d81721180b4f"
+      (reference "U10") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b86c4970-8fe8-4ec1-b640-cdf372ad640b"
+      (reference "U11") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/060e624a-9937-463c-9822-c256483cfdc7"
+      (reference "U12") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/44843df8-23d3-4da4-a090-17a977e57298"
+      (reference "U13") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b1e82f59-c715-4b82-93a1-4dc91bb206df"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9493e4cf-2eeb-4cba-9ce7-4fbc74b7ea5e"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8a4498be-5471-4a56-af53-708fb93195d5"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/766ceae5-484d-4ea8-9fd8-e56192237332"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.sub b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.sub
new file mode 100644
index 000000000..3bd3de818
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00.sub
@@ -0,0 +1,70 @@
+* Subcircuit 74HC00
+.subckt 74HC00 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad9_ net-_u11-pad1_ d_inverter
+* u7 net-_u1-pad10_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u12-pad1_ d_inverter
+* u3 net-_u1-pad2_ net-_u10-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u6 net-_u1-pad4_ net-_u13-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u14 net-_u10-pad3_ net-_u1-pad3_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad6_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u16 net-_u12-pad3_ net-_u1-pad11_ d_inverter
+* u15 net-_u11-pad3_ net-_u1-pad8_ d_inverter
+a1 net-_u1-pad5_ net-_u13-pad2_ u9
+a2 net-_u1-pad9_ net-_u11-pad1_ u4
+a3 net-_u1-pad10_ net-_u11-pad2_ u7
+a4 net-_u1-pad13_ net-_u12-pad2_ u8
+a5 net-_u1-pad12_ net-_u12-pad1_ u5
+a6 net-_u1-pad2_ net-_u10-pad2_ u3
+a7 net-_u1-pad1_ net-_u10-pad1_ u2
+a8 net-_u1-pad4_ net-_u13-pad1_ u6
+a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a10 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a11 net-_u10-pad3_ net-_u1-pad3_ u14
+a12 net-_u13-pad3_ net-_u1-pad6_ u17
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a15 net-_u12-pad3_ net-_u1-pad11_ u16
+a16 net-_u11-pad3_ net-_u1-pad8_ u15
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_Previous_Values.xml
new file mode 100644
index 000000000..e9af746f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u9 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u9><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u8><u5 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u5><u3 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u6><u11 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u14><u17 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u13><u10 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u10><u16 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u15 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.cir b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.cir
new file mode 100644
index 000000000..41340b2f5
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ Net-_U4-Pad4_ V_Y2 V_Y1 V_Y4 V_Y3 dac_bridge_4
+U5 V_Y3 plot_v1
+U6 V_Y4 plot_v1
+v1 Net-_X1-Pad14_ GND 5
+U7 Net-_V_B4-Pad1_ Net-_V_A4-Pad1_ Net-_V_B3-Pad1_ Net-_V_A3-Pad1_ Net-_U7-Pad5_ Net-_U7-Pad6_ Net-_U7-Pad7_ Net-_U7-Pad8_ adc_bridge_4
+V_A1 Net-_V_A1-Pad1_ GND DC
+V_A2 Net-_V_A2-Pad1_ GND DC
+V_B1 Net-_V_B1-Pad1_ GND DC
+V_B2 Net-_V_B2-Pad1_ GND DC
+U2 Net-_V_A1-Pad1_ Net-_V_B1-Pad1_ Net-_V_A2-Pad1_ Net-_V_B2-Pad1_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ adc_bridge_4
+V_A3 Net-_V_A3-Pad1_ GND DC
+V_B3 Net-_V_B3-Pad1_ GND DC
+V_B4 Net-_V_B4-Pad1_ GND DC
+V_A4 Net-_V_A4-Pad1_ GND DC
+X1 Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U4-Pad2_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U4-Pad1_ GND Net-_U4-Pad4_ Net-_U7-Pad8_ Net-_U7-Pad7_ Net-_U4-Pad3_ Net-_U7-Pad6_ Net-_U7-Pad5_ Net-_X1-Pad14_ 74HC00
+U1 V_Y1 plot_v1
+U3 V_Y2 plot_v1
+.end
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.cir.out b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.cir.out
new file mode 100644
index 000000000..79c15b439
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.cir.out
@@ -0,0 +1,42 @@
+.title kicad schematic
+
+.include 74HC00.sub
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ v_y2 v_y1 v_y4 v_y3 dac_bridge_4
+* u5 v_y3 plot_v1
+* u6 v_y4 plot_v1
+v1 net-_x1-pad14_ gnd 5
+* u7 net-_v_b4-pad1_ net-_v_a4-pad1_ net-_v_b3-pad1_ net-_v_a3-pad1_ net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ adc_bridge_4
+v_a1 net-_v_a1-pad1_ gnd  dc 5
+v_a2 net-_v_a2-pad1_ gnd  dc 5
+v_b1 net-_v_b1-pad1_ gnd  dc 5
+v_b2 net-_v_b2-pad1_ gnd  dc 0
+* u2 net-_v_a1-pad1_ net-_v_b1-pad1_ net-_v_a2-pad1_ net-_v_b2-pad1_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4
+v_a3 net-_v_a3-pad1_ gnd  dc 5
+v_b3 net-_v_b3-pad1_ gnd  dc 5
+v_b4 net-_v_b4-pad1_ gnd  dc 0
+v_a4 net-_v_a4-pad1_ gnd  dc 5
+x1 net-_u2-pad5_ net-_u2-pad6_ net-_u4-pad2_ net-_u2-pad7_ net-_u2-pad8_ net-_u4-pad1_ gnd net-_u4-pad4_ net-_u7-pad8_ net-_u7-pad7_ net-_u4-pad3_ net-_u7-pad6_ net-_u7-pad5_ net-_x1-pad14_ 74HC00
+* u1 v_y1 plot_v1
+* u3 v_y2 plot_v1
+a1 [net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ ] [v_y2 v_y1 v_y4 v_y3 ] u4
+a2 [net-_v_b4-pad1_ net-_v_a4-pad1_ net-_v_b3-pad1_ net-_v_a3-pad1_ ] [net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ ] u7
+a3 [net-_v_a1-pad1_ net-_v_b1-pad1_ net-_v_a2-pad1_ net-_v_b2-pad1_ ] [net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-00 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_y3)
+plot v(v_y4)
+plot v(v_y1)
+plot v(v_y2)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.kicad_sch b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.kicad_sch
new file mode 100644
index 000000000..eef3715af
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.kicad_sch
@@ -0,0 +1,1117 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 78423387-4339-47ed-a173-c8c66d547b05)
+
+  (paper "A2")
+
+  (lib_symbols
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+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_4" (id 1) (at 0 7.62 0)
+        (effects (font (size 1.524 1.524)))
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+      (property "Footprint" "" (id 2) (at 0 0 0)
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+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
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+    (uuid f544594a-1d49-45e7-98fa-719f2bb0be39)
+    (property "Reference" "V_A1" (id 0) (at 209.55 222.25 0)
+      (effects (font (size 1.524 1.524)) (justify left))
+    )
+    (property "Value" "DC" (id 1) (at 209.55 226.06 0)
+      (effects (font (size 1.524 1.524)) (justify left))
+    )
+    (property "Footprint" "R1" (id 2) (at 209.55 229.87 0)
+      (effects (font (size 1.524 1.524)) (justify left))
+    )
+    (property "Datasheet" "" (id 3) (at 204.47 225.425 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid df3d7c63-15be-409e-99e0-68539bb8ba50))
+    (pin "2" (uuid 8ae98603-8532-4cf1-a210-4b078e91de7f))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/e2ea518c-d198-4c72-b22b-2b1c920dbddc"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/99d791cf-785f-4f6a-8936-844859ef5df4"
+      (reference "U1") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/020716ce-c8aa-4306-ba0c-b9bce58f9d97"
+      (reference "U2") (unit 1) (value "adc_bridge_4") (footprint "")
+    )
+    (path "/94636d0e-b8d0-44be-ba62-c01b58a4ad86"
+      (reference "U3") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/891cf154-1833-4cce-9d23-dad8f8169959"
+      (reference "U4") (unit 1) (value "dac_bridge_4") (footprint "")
+    )
+    (path "/6c45ccdf-be4c-4657-aa77-1370d4d62d8b"
+      (reference "U5") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/0c33839f-dfef-4213-8eb6-707621a97872"
+      (reference "U6") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/98b2b2d8-711a-4e64-9887-5291e286e47f"
+      (reference "U7") (unit 1) (value "adc_bridge_4") (footprint "")
+    )
+    (path "/f544594a-1d49-45e7-98fa-719f2bb0be39"
+      (reference "V_A1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/88f7d6b4-82ab-4f8c-acf9-60de3b04da5d"
+      (reference "V_A2") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/cb71206c-e3a3-472c-aa1a-4e09ca4d2401"
+      (reference "V_A3") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/15a32f01-99d6-40c0-887e-64588f02f2cb"
+      (reference "V_A4") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/444173aa-8b43-4892-98ab-f5ca416ebbb8"
+      (reference "V_B1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/c46ccf24-8c2b-445b-9696-11e790582595"
+      (reference "V_B2") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/909cf5ab-349b-4610-964c-bf785537b4b2"
+      (reference "V_B3") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/0ad96dcb-d740-4413-98a6-4fadb65837d0"
+      (reference "V_B4") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/8c2d0cbe-2f71-461e-9a51-5e71af1d1c9f"
+      (reference "X1") (unit 1) (value "74HC00") (footprint "")
+    )
+    (path "/94f3a165-24e3-45fd-bb6a-7edca5c8ea3c"
+      (reference "v1") (unit 1) (value "5") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.proj b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.proj
new file mode 100644
index 000000000..ab06b5483
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.proj
@@ -0,0 +1 @@
+schematicFile 74HC00_TEST_CIRCUIT.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.raw b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.raw
new file mode 100644
index 000000000..fec665171
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT.raw
@@ -0,0 +1,1628 @@
+Title: kicad schematic
+Date: Sun Dec 14 19:09:03  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 27
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(net-_x1-pad14_)	voltage
+	2	v(net-_v_a1-pad1_)	voltage
+	3	v(net-_v_a2-pad1_)	voltage
+	4	v(net-_v_b1-pad1_)	voltage
+	5	v(net-_v_b2-pad1_)	voltage
+	6	v(net-_v_a3-pad1_)	voltage
+	7	v(net-_v_b3-pad1_)	voltage
+	8	v(net-_v_b4-pad1_)	voltage
+	9	v(net-_v_a4-pad1_)	voltage
+	10	v(v_y2)	voltage
+	11	v(v_y1)	voltage
+	12	v(v_y4)	voltage
+	13	v(v_y3)	voltage
+	14	i(v_a4)	current
+	15	i(v_b4)	current
+	16	i(v_b3)	current
+	17	i(v_a3)	current
+	18	i(v_b2)	current
+	19	i(v_b1)	current
+	20	i(v_a2)	current
+	21	i(v_a1)	current
+	22	i(v1)	current
+	23	i(a1)	current
+	24	i(a1)	current
+	25	i(a1)	current
+	26	i(a1)	current
+Values:
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diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT_Previous_Values.xml
new file mode 100644
index 000000000..3856bf590
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/74HC00_TEST_CIRCUIT_Previous_Values.xml
@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/_autosave-74HC00.sch b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/_autosave-74HC00.sch
new file mode 100644
index 000000000..528ab0b91
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/_autosave-74HC00.sch
@@ -0,0 +1,437 @@
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+F 3 "" H 2925 1775 60  0000 C CNN
+	1    2875 1825
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2925 3500
+F 0 "U?" H 2925 3750 60  0000 C CNN
+F 1 "d_inverter" H 2925 3600 60  0000 C CNN
+F 2 "" H 2975 3450 60  0000 C CNN
+F 3 "" H 2975 3450 60  0000 C CNN
+	1    2925 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2925 4575
+F 0 "U?" H 2925 4825 60  0000 C CNN
+F 1 "d_inverter" H 2925 4675 60  0000 C CNN
+F 2 "" H 2975 4525 60  0000 C CNN
+F 3 "" H 2975 4525 60  0000 C CNN
+	1    2925 4575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2950 2475
+F 0 "U?" H 2950 2725 60  0000 C CNN
+F 1 "d_inverter" H 2950 2575 60  0000 C CNN
+F 2 "" H 3000 2425 60  0000 C CNN
+F 3 "" H 3000 2425 60  0000 C CNN
+	1    2950 2475
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2975 3975
+F 0 "U?" H 2975 4250 60  0000 C CNN
+F 1 "d_inverter" H 2975 4100 60  0000 C CNN
+F 2 "" H 3025 3925 60  0000 C CNN
+F 3 "" H 3025 3925 60  0000 C CNN
+	1    2975 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2975 5050
+F 0 "U?" H 2975 5325 60  0000 C CNN
+F 1 "d_inverter" H 2975 5175 60  0000 C CNN
+F 2 "" H 3025 5000 60  0000 C CNN
+F 3 "" H 3025 5000 60  0000 C CNN
+	1    2975 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 3000 2950
+F 0 "U?" H 3000 3225 60  0000 C CNN
+F 1 "d_inverter" H 3000 3075 60  0000 C CNN
+F 2 "" H 3050 2900 60  0000 C CNN
+F 3 "" H 3050 2900 60  0000 C CNN
+	1    3000 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5050 1575
+F 0 "U?" H 5050 1850 60  0000 C CNN
+F 1 "d_inverter" H 5050 1700 60  0000 C CNN
+F 2 "" H 5100 1525 60  0000 C CNN
+F 3 "" H 5100 1525 60  0000 C CNN
+	1    5050 1575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5150 3725
+F 0 "U?" H 5150 4000 60  0000 C CNN
+F 1 "d_inverter" H 5150 3850 60  0000 C CNN
+F 2 "" H 5200 3675 60  0000 C CNN
+F 3 "" H 5200 3675 60  0000 C CNN
+	1    5150 3725
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5150 4800
+F 0 "U?" H 5150 5075 60  0000 C CNN
+F 1 "d_inverter" H 5150 4925 60  0000 C CNN
+F 2 "" H 5200 4750 60  0000 C CNN
+F 3 "" H 5200 4750 60  0000 C CNN
+	1    5150 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5175 2700
+F 0 "U?" H 5175 2975 60  0000 C CNN
+F 1 "d_inverter" H 5175 2825 60  0000 C CNN
+F 2 "" H 5225 2650 60  0000 C CNN
+F 3 "" H 5225 2650 60  0000 C CNN
+	1    5175 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 3950 1625
+F 0 "U?" H 3950 2000 60  0000 C CNN
+F 1 "d_nor" H 3950 1850 60  0000 C CNN
+F 2 "" H 3950 1625 60  0000 C CNN
+F 3 "" H 3950 1625 60  0000 C CNN
+	1    3950 1625
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 4050 3775
+F 0 "U?" H 4050 4150 60  0000 C CNN
+F 1 "d_nor" H 4050 4000 60  0000 C CNN
+F 2 "" H 4050 3775 60  0000 C CNN
+F 3 "" H 4050 3775 60  0000 C CNN
+	1    4050 3775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 4050 4850
+F 0 "U?" H 4050 5225 60  0000 C CNN
+F 1 "d_nor" H 4050 5075 60  0000 C CNN
+F 2 "" H 4050 4850 60  0000 C CNN
+F 3 "" H 4050 4850 60  0000 C CNN
+	1    4050 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 4075 2750
+F 0 "U?" H 4075 3125 60  0000 C CNN
+F 1 "d_nor" H 4075 2975 60  0000 C CNN
+F 2 "" H 4075 2750 60  0000 C CNN
+F 3 "" H 4075 2750 60  0000 C CNN
+	1    4075 2750
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/analysis b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/analysis
new file mode 100644
index 000000000..14a32166e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/74HC00_Test_Circuit/74HC00_TEST_CIRCUIT/analysis
@@ -0,0 +1 @@
+.tran 1e-00 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/_autosave-74HC00.sch b/library/SubcircuitLibrary/IC74HC00/74HC00/_autosave-74HC00.sch
new file mode 100644
index 000000000..528ab0b91
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/_autosave-74HC00.sch
@@ -0,0 +1,437 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Wire Wire Line
+	2125 1350 2525 1350
+Wire Wire Line
+	2125 3975 2675 3975
+Wire Wire Line
+	2150 2475 2650 2475
+Wire Wire Line
+	2150 2950 2700 2950
+Wire Wire Line
+	2175 1825 2575 1825
+Wire Wire Line
+	2225 4575 2625 4575
+Wire Wire Line
+	2225 5050 2675 5050
+Wire Wire Line
+	2625 3500 2100 3500
+Wire Wire Line
+	3125 1350 3500 1350
+Wire Wire Line
+	3175 1825 3500 1825
+Wire Wire Line
+	3275 3975 3600 3975
+Wire Wire Line
+	3275 5050 3600 5050
+Wire Wire Line
+	3300 2950 3625 2950
+Wire Wire Line
+	3500 1350 3500 1525
+Wire Wire Line
+	3500 1825 3500 1625
+Wire Wire Line
+	3600 3500 3225 3500
+Wire Wire Line
+	3600 3675 3600 3500
+Wire Wire Line
+	3600 3975 3600 3775
+Wire Wire Line
+	3600 4575 3225 4575
+Wire Wire Line
+	3600 4750 3600 4575
+Wire Wire Line
+	3600 5050 3600 4850
+Wire Wire Line
+	3625 2475 3250 2475
+Wire Wire Line
+	3625 2650 3625 2475
+Wire Wire Line
+	3625 2950 3625 2750
+Wire Wire Line
+	4400 1575 4750 1575
+Wire Wire Line
+	4500 3725 4850 3725
+Wire Wire Line
+	4500 4800 4850 4800
+Wire Wire Line
+	4525 2700 4875 2700
+Wire Wire Line
+	5350 1575 5950 1575
+Wire Wire Line
+	5450 3725 5825 3725
+Wire Wire Line
+	5450 4800 5850 4800
+Wire Wire Line
+	5475 2700 5900 2700
+$Comp
+L eSim_Power:eSim_GND #PWR?
+U 1 1 00000000
+P 8225 2725
+F 0 "#PWR?" H 8225 2475 50  0001 C CNN
+F 1 "eSim_GND" H 8225 2550 50  0000 C CNN
+F 2 "" H 8225 2725 50  0001 C CNN
+F 3 "" H 8225 2725 50  0001 C CNN
+	1    8225 2725
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Power:eSim_GND #PWR?
+U 1 1 00000000
+P 8250 3175
+F 0 "#PWR?" H 8250 2925 50  0001 C CNN
+F 1 "eSim_GND" H 8250 3000 50  0000 C CNN
+F 2 "" H 8250 3175 50  0001 C CNN
+F 3 "" H 8250 3175 50  0001 C CNN
+	1    8250 3175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 9 1 00000000
+P 1850 3500
+F 0 "U?" H 1875 3675 30  0000 C CNN
+F 1 "PORT" H 1875 3575 30  0000 C CNN
+F 2 "" H 1850 3500 60  0000 C CNN
+F 3 "" H 1850 3500 60  0000 C CNN
+	9    1850 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 1 1 00000000
+P 1875 1350
+F 0 "U?" H 1900 1550 30  0000 C CNN
+F 1 "PORT" H 1900 1450 30  0000 C CNN
+F 2 "" H 1875 1350 60  0000 C CNN
+F 3 "" H 1875 1350 60  0000 C CNN
+	1    1875 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 10 1 00000000
+P 1875 3975
+F 0 "U?" H 1900 4175 30  0000 C CNN
+F 1 "PORT" H 1900 4075 30  0000 C CNN
+F 2 "" H 1875 3975 60  0000 C CNN
+F 3 "" H 1875 3975 60  0000 C CNN
+	10   1875 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 4 1 00000000
+P 1900 2475
+F 0 "U?" H 1925 2650 30  0000 C CNN
+F 1 "PORT" H 1925 2550 30  0000 C CNN
+F 2 "" H 1900 2475 60  0000 C CNN
+F 3 "" H 1900 2475 60  0000 C CNN
+	4    1900 2475
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 5 1 00000000
+P 1900 2950
+F 0 "U?" H 1925 3125 30  0000 C CNN
+F 1 "PORT" H 1925 3025 30  0000 C CNN
+F 2 "" H 1900 2950 60  0000 C CNN
+F 3 "" H 1900 2950 60  0000 C CNN
+	5    1900 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 2 1 00000000
+P 1925 1825
+F 0 "U?" H 1950 2000 30  0000 C CNN
+F 1 "PORT" H 1950 1900 30  0000 C CNN
+F 2 "" H 1925 1825 60  0000 C CNN
+F 3 "" H 1925 1825 60  0000 C CNN
+	2    1925 1825
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 12 1 00000000
+P 1975 4575
+F 0 "U?" H 2000 4750 30  0000 C CNN
+F 1 "PORT" H 2000 4650 30  0000 C CNN
+F 2 "" H 1975 4575 60  0000 C CNN
+F 3 "" H 1975 4575 60  0000 C CNN
+	12   1975 4575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 13 1 00000000
+P 1975 5050
+F 0 "U?" H 2000 5225 30  0000 C CNN
+F 1 "PORT" H 2000 5125 30  0000 C CNN
+F 2 "" H 1975 5050 60  0000 C CNN
+F 3 "" H 1975 5050 60  0000 C CNN
+	13   1975 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 8 1 00000000
+P 6075 3725
+F 0 "U?" H 6100 3900 30  0000 C CNN
+F 1 "PORT" H 6100 3800 30  0000 C CNN
+F 2 "" H 6075 3725 60  0000 C CNN
+F 3 "" H 6075 3725 60  0000 C CNN
+	8    6075 3725
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 11 1 00000000
+P 6100 4800
+F 0 "U?" H 5950 4825 30  0000 R CNN
+F 1 "PORT" H 5950 4725 30  0000 R CNN
+F 2 "" H 6100 4800 60  0000 C CNN
+F 3 "" H 6100 4800 60  0000 C CNN
+	11   6100 4800
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 6 1 00000000
+P 6150 2700
+F 0 "U?" H 6000 2725 30  0000 R CNN
+F 1 "PORT" H 6000 2625 30  0000 R CNN
+F 2 "" H 6150 2700 60  0000 C CNN
+F 3 "" H 6150 2700 60  0000 C CNN
+	6    6150 2700
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 3 1 00000000
+P 6200 1575
+F 0 "U?" H 6050 1600 30  0000 R CNN
+F 1 "PORT" H 6050 1500 30  0000 R CNN
+F 2 "" H 6200 1575 60  0000 C CNN
+F 3 "" H 6200 1575 60  0000 C CNN
+	3    6200 1575
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 7 1 00000000
+P 7500 2725
+F 0 "U?" H 7525 2900 30  0000 C CNN
+F 1 "PORT" H 7525 2800 30  0000 C CNN
+F 2 "" H 7500 2725 60  0000 C CNN
+F 3 "" H 7500 2725 60  0000 C CNN
+	7    7500 2725
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 14 1 00000000
+P 7525 3175
+F 0 "U?" H 7550 3350 30  0000 C CNN
+F 1 "PORT" H 7550 3250 30  0000 C CNN
+F 2 "" H 7525 3175 60  0000 C CNN
+F 3 "" H 7525 3175 60  0000 C CNN
+	14   7525 3175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2825 1350
+F 0 "U?" H 2825 1600 60  0000 C CNN
+F 1 "d_inverter" H 2825 1450 60  0000 C CNN
+F 2 "" H 2875 1300 60  0000 C CNN
+F 3 "" H 2875 1300 60  0000 C CNN
+	1    2825 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2875 1825
+F 0 "U?" H 2875 2100 60  0000 C CNN
+F 1 "d_inverter" H 2875 1950 60  0000 C CNN
+F 2 "" H 2925 1775 60  0000 C CNN
+F 3 "" H 2925 1775 60  0000 C CNN
+	1    2875 1825
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2925 3500
+F 0 "U?" H 2925 3750 60  0000 C CNN
+F 1 "d_inverter" H 2925 3600 60  0000 C CNN
+F 2 "" H 2975 3450 60  0000 C CNN
+F 3 "" H 2975 3450 60  0000 C CNN
+	1    2925 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2925 4575
+F 0 "U?" H 2925 4825 60  0000 C CNN
+F 1 "d_inverter" H 2925 4675 60  0000 C CNN
+F 2 "" H 2975 4525 60  0000 C CNN
+F 3 "" H 2975 4525 60  0000 C CNN
+	1    2925 4575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2950 2475
+F 0 "U?" H 2950 2725 60  0000 C CNN
+F 1 "d_inverter" H 2950 2575 60  0000 C CNN
+F 2 "" H 3000 2425 60  0000 C CNN
+F 3 "" H 3000 2425 60  0000 C CNN
+	1    2950 2475
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2975 3975
+F 0 "U?" H 2975 4250 60  0000 C CNN
+F 1 "d_inverter" H 2975 4100 60  0000 C CNN
+F 2 "" H 3025 3925 60  0000 C CNN
+F 3 "" H 3025 3925 60  0000 C CNN
+	1    2975 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2975 5050
+F 0 "U?" H 2975 5325 60  0000 C CNN
+F 1 "d_inverter" H 2975 5175 60  0000 C CNN
+F 2 "" H 3025 5000 60  0000 C CNN
+F 3 "" H 3025 5000 60  0000 C CNN
+	1    2975 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 3000 2950
+F 0 "U?" H 3000 3225 60  0000 C CNN
+F 1 "d_inverter" H 3000 3075 60  0000 C CNN
+F 2 "" H 3050 2900 60  0000 C CNN
+F 3 "" H 3050 2900 60  0000 C CNN
+	1    3000 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5050 1575
+F 0 "U?" H 5050 1850 60  0000 C CNN
+F 1 "d_inverter" H 5050 1700 60  0000 C CNN
+F 2 "" H 5100 1525 60  0000 C CNN
+F 3 "" H 5100 1525 60  0000 C CNN
+	1    5050 1575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5150 3725
+F 0 "U?" H 5150 4000 60  0000 C CNN
+F 1 "d_inverter" H 5150 3850 60  0000 C CNN
+F 2 "" H 5200 3675 60  0000 C CNN
+F 3 "" H 5200 3675 60  0000 C CNN
+	1    5150 3725
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5150 4800
+F 0 "U?" H 5150 5075 60  0000 C CNN
+F 1 "d_inverter" H 5150 4925 60  0000 C CNN
+F 2 "" H 5200 4750 60  0000 C CNN
+F 3 "" H 5200 4750 60  0000 C CNN
+	1    5150 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5175 2700
+F 0 "U?" H 5175 2975 60  0000 C CNN
+F 1 "d_inverter" H 5175 2825 60  0000 C CNN
+F 2 "" H 5225 2650 60  0000 C CNN
+F 3 "" H 5225 2650 60  0000 C CNN
+	1    5175 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 3950 1625
+F 0 "U?" H 3950 2000 60  0000 C CNN
+F 1 "d_nor" H 3950 1850 60  0000 C CNN
+F 2 "" H 3950 1625 60  0000 C CNN
+F 3 "" H 3950 1625 60  0000 C CNN
+	1    3950 1625
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 4050 3775
+F 0 "U?" H 4050 4150 60  0000 C CNN
+F 1 "d_nor" H 4050 4000 60  0000 C CNN
+F 2 "" H 4050 3775 60  0000 C CNN
+F 3 "" H 4050 3775 60  0000 C CNN
+	1    4050 3775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 4050 4850
+F 0 "U?" H 4050 5225 60  0000 C CNN
+F 1 "d_nor" H 4050 5075 60  0000 C CNN
+F 2 "" H 4050 4850 60  0000 C CNN
+F 3 "" H 4050 4850 60  0000 C CNN
+	1    4050 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U?
+U 1 1 00000000
+P 4075 2750
+F 0 "U?" H 4075 3125 60  0000 C CNN
+F 1 "d_nor" H 4075 2975 60  0000 C CNN
+F 2 "" H 4075 2750 60  0000 C CNN
+F 3 "" H 4075 2750 60  0000 C CNN
+	1    4075 2750
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC00/74HC00/analysis b/library/SubcircuitLibrary/IC74HC00/74HC00/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC00/74HC00/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.cir b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.cir
new file mode 100644
index 000000000..ce4462055
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U15 Net-_U12-Pad3_ Net-_U1-Pad13_ d_inverter
+U17 Net-_U13-Pad3_ Net-_U1-Pad10_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand
+U9 Net-_U1-Pad9_ Net-_U13-Pad2_ d_inverter
+U3 Net-_U1-Pad12_ Net-_U12-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand
+U2 Net-_U1-Pad11_ Net-_U12-Pad1_ d_inverter
+U8 Net-_U1-Pad8_ Net-_U13-Pad1_ d_inverter
+U5 Net-_U1-Pad6_ Net-_U11-Pad2_ d_inverter
+U7 Net-_U1-Pad5_ Net-_U11-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand
+U14 Net-_U11-Pad3_ Net-_U1-Pad4_ d_inverter
+U16 Net-_U10-Pad3_ Net-_U1-Pad1_ d_inverter
+U4 Net-_U1-Pad3_ Net-_U10-Pad2_ d_inverter
+U6 Net-_U1-Pad2_ Net-_U10-Pad1_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.cir.out b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.cir.out
new file mode 100644
index 000000000..2b75cd23c
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.cir.out
@@ -0,0 +1,76 @@
+.title kicad schematic
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u15 net-_u12-pad3_ net-_u1-pad13_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad10_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u9 net-_u1-pad9_ net-_u13-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u12-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand
+* u2 net-_u1-pad11_ net-_u12-pad1_ d_inverter
+* u8 net-_u1-pad8_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad6_ net-_u11-pad2_ d_inverter
+* u7 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand
+* u14 net-_u11-pad3_ net-_u1-pad4_ d_inverter
+* u16 net-_u10-pad3_ net-_u1-pad1_ d_inverter
+* u4 net-_u1-pad3_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad2_ net-_u10-pad1_ d_inverter
+a1 net-_u12-pad3_ net-_u1-pad13_ u15
+a2 net-_u13-pad3_ net-_u1-pad10_ u17
+a3 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a4 net-_u1-pad9_ net-_u13-pad2_ u9
+a5 net-_u1-pad12_ net-_u12-pad2_ u3
+a6 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a7 net-_u1-pad11_ net-_u12-pad1_ u2
+a8 net-_u1-pad8_ net-_u13-pad1_ u8
+a9 net-_u1-pad6_ net-_u11-pad2_ u5
+a10 net-_u1-pad5_ net-_u11-pad1_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a13 net-_u11-pad3_ net-_u1-pad4_ u14
+a14 net-_u10-pad3_ net-_u1-pad1_ u16
+a15 net-_u1-pad3_ net-_u10-pad2_ u4
+a16 net-_u1-pad2_ net-_u10-pad1_ u6
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.kicad_sch b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.kicad_sch
new file mode 100644
index 000000000..d4d705e50
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.kicad_sch
@@ -0,0 +1,1495 @@
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+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid ff575a73-394f-4cdc-87dc-909c007881eb)
+    (property "Reference" "U1" (id 0) (at 90.17 51.435 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Value" "PORT" (id 1) (at 90.17 53.975 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Footprint" "" (id 2) (at 89.535 55.88 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 89.535 55.88 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 43b6e897-cf55-4f70-b1cb-13a5d85e3076))
+    (pin "2" (uuid 06cbbc3a-1bc8-4ec3-90d1-1a26276b44b8))
+    (pin "3" (uuid 2fdf46dd-3ffb-45fe-97fa-bad7d478770e))
+    (pin "4" (uuid 2e45e203-0cae-4765-95f8-1cbac5f07ebb))
+    (pin "5" (uuid e9c60a37-9ce7-42ba-9863-ed595312340b))
+    (pin "6" (uuid d348b4f3-0a84-4bea-8a04-17cf0b596c8a))
+    (pin "7" (uuid 8b67b1ba-1d57-43ee-9bcd-6246ce05734d))
+    (pin "8" (uuid 20c49264-41aa-43b7-8442-305d770941da))
+    (pin "9" (uuid 482c2f1e-5344-4271-80ec-39467c922c26))
+    (pin "10" (uuid 35967762-0e5d-4c89-a77d-3e2284b56e72))
+    (pin "11" (uuid 1177c388-b7a6-4a2e-b95e-65897c4f2233))
+    (pin "12" (uuid 0f9f2a6f-4ebe-4a46-b445-8b9a665621bb))
+    (pin "13" (uuid 70769dbb-2f66-4c81-8b25-fa4ffb6a9311))
+    (pin "14" (uuid e79d7592-b53f-4ee5-8358-3059eb85cf96))
+    (pin "15" (uuid f9e5addf-ff7d-4875-a52a-b9cb42ebed53))
+    (pin "16" (uuid cb29453b-f260-44f6-9064-742de35f949a))
+    (pin "17" (uuid 7e9cd2a6-463f-447f-b1dd-85e8800aca01))
+    (pin "18" (uuid 0b2bca9b-8435-4fd3-a6bf-ae2815c4db24))
+    (pin "19" (uuid d55b9a96-aecc-4515-8dfa-eebbe6d3989f))
+    (pin "20" (uuid 8d7d6fc2-8524-4b87-ada2-72a5fc795dbf))
+    (pin "21" (uuid 4adf5064-7775-4ca5-8093-24a7820a20c6))
+    (pin "22" (uuid f0c8e3ab-154a-4dac-a5a3-ea4b115a71cc))
+    (pin "23" (uuid 6d3d41c2-9c69-48e9-ab58-5b3acefcfd25))
+    (pin "24" (uuid e63d0325-7d39-41a3-ae6f-ec0b15352a5d))
+    (pin "25" (uuid 7c538b00-da75-4b40-84f5-7c82792cf95e))
+    (pin "26" (uuid e20292a3-ee0d-4b67-87cf-8593fed4f2e4))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/d01198a6-6d5e-4d26-95ce-9d6854b5fc17"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/ba4cb49b-95c3-4766-a059-a0803cc69f76"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/aa641c99-890a-4e19-8878-c77ecf386195"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/ff575a73-394f-4cdc-87dc-909c007881eb"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/e710a593-72cc-4634-8e53-dbce3085e794"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/2afdff51-93ce-4feb-a21e-2b4be939b9d1"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/828f5009-7875-461c-a3c0-0d3db04a5770"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/689b31b0-5ebe-47bb-adde-6867dd34683c"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/0a75af44-1a47-4f7c-9952-6912bf3e9c7a"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/f60017a2-cec5-4cce-9840-b0e3590cb4a4"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/d3fe08a9-4c96-4ef6-b896-fbb113b395ef"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/d22edfa2-3048-4e08-831b-c68a9172a0a4"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/1123973e-a4ff-41ec-aadb-9a6b571fe679"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/e1603269-0137-4df7-8058-0caac94b8853"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/e1831bcd-9c67-4245-b421-bd07be01b0b2"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/6677d4a4-999d-40a2-82e2-cf01d33bc5b5"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/017e4c11-4fd1-4e0b-96c6-87ab8f5784bb"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/d4e40cf5-113f-4829-844d-65b2724200cc"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/74c56c6c-609d-4e1d-be02-ace5922e652a"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c22182fa-ade5-40a7-9ad6-86759bad1e9c"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a7e0c458-0329-41c6-9897-fe60f9099c12"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f04cb64e-f1e1-4288-8f3f-0573bc941f6e"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c0b4a19b-329f-4a0c-af6c-88f8cdd5fa62"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/cdae6aa8-480e-49b1-a6ed-6e896bf3d15f"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3799d047-f53b-4e58-b2d5-60aa00074bbc"
+      (reference "U10") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/d81ec92e-ad2d-45cc-a0ac-f4c77804e087"
+      (reference "U11") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/8bc1b53f-83e7-463d-8389-b9f281fd9df7"
+      (reference "U12") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/6703219f-bcf7-4e2a-81af-46e57c74af11"
+      (reference "U13") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/911df9f2-06f3-4eee-9974-3e5525592765"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f5fe6cfc-d26f-4d9b-8b79-9348ce969dfb"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/26822983-4961-4f4d-b55f-64afc56e56bf"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c1392fd9-8125-488d-9e8b-dae324e95abb"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.sub b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.sub
new file mode 100644
index 000000000..ea80c9b9e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02.sub
@@ -0,0 +1,70 @@
+* Subcircuit 74HC02
+.subckt 74HC02 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u15 net-_u12-pad3_ net-_u1-pad13_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad10_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u9 net-_u1-pad9_ net-_u13-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u12-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand
+* u2 net-_u1-pad11_ net-_u12-pad1_ d_inverter
+* u8 net-_u1-pad8_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad6_ net-_u11-pad2_ d_inverter
+* u7 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand
+* u14 net-_u11-pad3_ net-_u1-pad4_ d_inverter
+* u16 net-_u10-pad3_ net-_u1-pad1_ d_inverter
+* u4 net-_u1-pad3_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad2_ net-_u10-pad1_ d_inverter
+a1 net-_u12-pad3_ net-_u1-pad13_ u15
+a2 net-_u13-pad3_ net-_u1-pad10_ u17
+a3 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a4 net-_u1-pad9_ net-_u13-pad2_ u9
+a5 net-_u1-pad12_ net-_u12-pad2_ u3
+a6 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a7 net-_u1-pad11_ net-_u12-pad1_ u2
+a8 net-_u1-pad8_ net-_u13-pad1_ u8
+a9 net-_u1-pad6_ net-_u11-pad2_ u5
+a10 net-_u1-pad5_ net-_u11-pad1_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a13 net-_u11-pad3_ net-_u1-pad4_ u14
+a14 net-_u10-pad3_ net-_u1-pad1_ u16
+a15 net-_u1-pad3_ net-_u10-pad2_ u4
+a16 net-_u1-pad2_ net-_u10-pad1_ u6
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC02
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Previous_Values.xml
new file mode 100644
index 000000000..c32949aae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u15 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u13><u9 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u9><u3 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u12><u2 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u2><u8 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8><u5 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u11 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u16 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u16><u4 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u6></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.cir b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.cir
new file mode 100644
index 000000000..ce4462055
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U15 Net-_U12-Pad3_ Net-_U1-Pad13_ d_inverter
+U17 Net-_U13-Pad3_ Net-_U1-Pad10_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand
+U9 Net-_U1-Pad9_ Net-_U13-Pad2_ d_inverter
+U3 Net-_U1-Pad12_ Net-_U12-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand
+U2 Net-_U1-Pad11_ Net-_U12-Pad1_ d_inverter
+U8 Net-_U1-Pad8_ Net-_U13-Pad1_ d_inverter
+U5 Net-_U1-Pad6_ Net-_U11-Pad2_ d_inverter
+U7 Net-_U1-Pad5_ Net-_U11-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand
+U14 Net-_U11-Pad3_ Net-_U1-Pad4_ d_inverter
+U16 Net-_U10-Pad3_ Net-_U1-Pad1_ d_inverter
+U4 Net-_U1-Pad3_ Net-_U10-Pad2_ d_inverter
+U6 Net-_U1-Pad2_ Net-_U10-Pad1_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.cir.out b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.cir.out
new file mode 100644
index 000000000..2b75cd23c
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.cir.out
@@ -0,0 +1,76 @@
+.title kicad schematic
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u15 net-_u12-pad3_ net-_u1-pad13_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad10_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u9 net-_u1-pad9_ net-_u13-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u12-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand
+* u2 net-_u1-pad11_ net-_u12-pad1_ d_inverter
+* u8 net-_u1-pad8_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad6_ net-_u11-pad2_ d_inverter
+* u7 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand
+* u14 net-_u11-pad3_ net-_u1-pad4_ d_inverter
+* u16 net-_u10-pad3_ net-_u1-pad1_ d_inverter
+* u4 net-_u1-pad3_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad2_ net-_u10-pad1_ d_inverter
+a1 net-_u12-pad3_ net-_u1-pad13_ u15
+a2 net-_u13-pad3_ net-_u1-pad10_ u17
+a3 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a4 net-_u1-pad9_ net-_u13-pad2_ u9
+a5 net-_u1-pad12_ net-_u12-pad2_ u3
+a6 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a7 net-_u1-pad11_ net-_u12-pad1_ u2
+a8 net-_u1-pad8_ net-_u13-pad1_ u8
+a9 net-_u1-pad6_ net-_u11-pad2_ u5
+a10 net-_u1-pad5_ net-_u11-pad1_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a13 net-_u11-pad3_ net-_u1-pad4_ u14
+a14 net-_u10-pad3_ net-_u1-pad1_ u16
+a15 net-_u1-pad3_ net-_u10-pad2_ u4
+a16 net-_u1-pad2_ net-_u10-pad1_ u6
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.kicad_sch b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.kicad_sch
new file mode 100644
index 000000000..d4d705e50
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.kicad_sch
@@ -0,0 +1,1495 @@
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+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid ff575a73-394f-4cdc-87dc-909c007881eb)
+    (property "Reference" "U1" (id 0) (at 90.17 51.435 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Value" "PORT" (id 1) (at 90.17 53.975 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Footprint" "" (id 2) (at 89.535 55.88 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 89.535 55.88 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 43b6e897-cf55-4f70-b1cb-13a5d85e3076))
+    (pin "2" (uuid 06cbbc3a-1bc8-4ec3-90d1-1a26276b44b8))
+    (pin "3" (uuid 2fdf46dd-3ffb-45fe-97fa-bad7d478770e))
+    (pin "4" (uuid 2e45e203-0cae-4765-95f8-1cbac5f07ebb))
+    (pin "5" (uuid e9c60a37-9ce7-42ba-9863-ed595312340b))
+    (pin "6" (uuid d348b4f3-0a84-4bea-8a04-17cf0b596c8a))
+    (pin "7" (uuid 8b67b1ba-1d57-43ee-9bcd-6246ce05734d))
+    (pin "8" (uuid 20c49264-41aa-43b7-8442-305d770941da))
+    (pin "9" (uuid 482c2f1e-5344-4271-80ec-39467c922c26))
+    (pin "10" (uuid 35967762-0e5d-4c89-a77d-3e2284b56e72))
+    (pin "11" (uuid 1177c388-b7a6-4a2e-b95e-65897c4f2233))
+    (pin "12" (uuid 0f9f2a6f-4ebe-4a46-b445-8b9a665621bb))
+    (pin "13" (uuid 70769dbb-2f66-4c81-8b25-fa4ffb6a9311))
+    (pin "14" (uuid e79d7592-b53f-4ee5-8358-3059eb85cf96))
+    (pin "15" (uuid f9e5addf-ff7d-4875-a52a-b9cb42ebed53))
+    (pin "16" (uuid cb29453b-f260-44f6-9064-742de35f949a))
+    (pin "17" (uuid 7e9cd2a6-463f-447f-b1dd-85e8800aca01))
+    (pin "18" (uuid 0b2bca9b-8435-4fd3-a6bf-ae2815c4db24))
+    (pin "19" (uuid d55b9a96-aecc-4515-8dfa-eebbe6d3989f))
+    (pin "20" (uuid 8d7d6fc2-8524-4b87-ada2-72a5fc795dbf))
+    (pin "21" (uuid 4adf5064-7775-4ca5-8093-24a7820a20c6))
+    (pin "22" (uuid f0c8e3ab-154a-4dac-a5a3-ea4b115a71cc))
+    (pin "23" (uuid 6d3d41c2-9c69-48e9-ab58-5b3acefcfd25))
+    (pin "24" (uuid e63d0325-7d39-41a3-ae6f-ec0b15352a5d))
+    (pin "25" (uuid 7c538b00-da75-4b40-84f5-7c82792cf95e))
+    (pin "26" (uuid e20292a3-ee0d-4b67-87cf-8593fed4f2e4))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/d01198a6-6d5e-4d26-95ce-9d6854b5fc17"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/ba4cb49b-95c3-4766-a059-a0803cc69f76"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/aa641c99-890a-4e19-8878-c77ecf386195"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/ff575a73-394f-4cdc-87dc-909c007881eb"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/e710a593-72cc-4634-8e53-dbce3085e794"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/2afdff51-93ce-4feb-a21e-2b4be939b9d1"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/828f5009-7875-461c-a3c0-0d3db04a5770"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/689b31b0-5ebe-47bb-adde-6867dd34683c"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/0a75af44-1a47-4f7c-9952-6912bf3e9c7a"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/f60017a2-cec5-4cce-9840-b0e3590cb4a4"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/d3fe08a9-4c96-4ef6-b896-fbb113b395ef"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/d22edfa2-3048-4e08-831b-c68a9172a0a4"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/1123973e-a4ff-41ec-aadb-9a6b571fe679"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/e1603269-0137-4df7-8058-0caac94b8853"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/e1831bcd-9c67-4245-b421-bd07be01b0b2"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/6677d4a4-999d-40a2-82e2-cf01d33bc5b5"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/017e4c11-4fd1-4e0b-96c6-87ab8f5784bb"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/d4e40cf5-113f-4829-844d-65b2724200cc"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/74c56c6c-609d-4e1d-be02-ace5922e652a"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c22182fa-ade5-40a7-9ad6-86759bad1e9c"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a7e0c458-0329-41c6-9897-fe60f9099c12"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f04cb64e-f1e1-4288-8f3f-0573bc941f6e"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c0b4a19b-329f-4a0c-af6c-88f8cdd5fa62"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/cdae6aa8-480e-49b1-a6ed-6e896bf3d15f"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3799d047-f53b-4e58-b2d5-60aa00074bbc"
+      (reference "U10") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/d81ec92e-ad2d-45cc-a0ac-f4c77804e087"
+      (reference "U11") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/8bc1b53f-83e7-463d-8389-b9f281fd9df7"
+      (reference "U12") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/6703219f-bcf7-4e2a-81af-46e57c74af11"
+      (reference "U13") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/911df9f2-06f3-4eee-9974-3e5525592765"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f5fe6cfc-d26f-4d9b-8b79-9348ce969dfb"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/26822983-4961-4f4d-b55f-64afc56e56bf"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c1392fd9-8125-488d-9e8b-dae324e95abb"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.sub b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.sub
new file mode 100644
index 000000000..ea80c9b9e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02.sub
@@ -0,0 +1,70 @@
+* Subcircuit 74HC02
+.subckt 74HC02 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u15 net-_u12-pad3_ net-_u1-pad13_ d_inverter
+* u17 net-_u13-pad3_ net-_u1-pad10_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u9 net-_u1-pad9_ net-_u13-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u12-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand
+* u2 net-_u1-pad11_ net-_u12-pad1_ d_inverter
+* u8 net-_u1-pad8_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad6_ net-_u11-pad2_ d_inverter
+* u7 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand
+* u14 net-_u11-pad3_ net-_u1-pad4_ d_inverter
+* u16 net-_u10-pad3_ net-_u1-pad1_ d_inverter
+* u4 net-_u1-pad3_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad2_ net-_u10-pad1_ d_inverter
+a1 net-_u12-pad3_ net-_u1-pad13_ u15
+a2 net-_u13-pad3_ net-_u1-pad10_ u17
+a3 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a4 net-_u1-pad9_ net-_u13-pad2_ u9
+a5 net-_u1-pad12_ net-_u12-pad2_ u3
+a6 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a7 net-_u1-pad11_ net-_u12-pad1_ u2
+a8 net-_u1-pad8_ net-_u13-pad1_ u8
+a9 net-_u1-pad6_ net-_u11-pad2_ u5
+a10 net-_u1-pad5_ net-_u11-pad1_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a13 net-_u11-pad3_ net-_u1-pad4_ u14
+a14 net-_u10-pad3_ net-_u1-pad1_ u16
+a15 net-_u1-pad3_ net-_u10-pad2_ u4
+a16 net-_u1-pad2_ net-_u10-pad1_ u6
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC02
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_Previous_Values.xml
new file mode 100644
index 000000000..c32949aae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u15 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u13><u9 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u9><u3 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u12><u2 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u2><u8 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8><u5 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u11 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u16 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u16><u4 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u6></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.cir b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.cir
new file mode 100644
index 000000000..2ba561c60
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad6_ Net-_U7-Pad7_ Net-_U7-Pad8_ adc_bridge_4
+v5 Net-_X1-Pad14_ GND 5
+V_4B1 Net-_U7-Pad1_ GND DC
+V_4A1 Net-_U7-Pad2_ GND DC
+V_3B1 Net-_U7-Pad3_ GND DC
+V_3A1 Net-_U7-Pad4_ GND DC
+X1 Net-_U4-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ GND Net-_U7-Pad8_ Net-_U7-Pad7_ Net-_U4-Pad2_ Net-_U7-Pad6_ Net-_U7-Pad5_ Net-_U4-Pad1_ Net-_X1-Pad14_ 74HC02
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4
+V_2A1 Net-_U1-Pad3_ GND DC
+V_1B1 Net-_U1-Pad2_ GND DC
+V_1A1 Net-_U1-Pad1_ GND DC
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ Net-_U4-Pad4_ V_4Y V_3Y V_2Y V_1Y dac_bridge_4
+U5 V_3Y plot_v1
+U6 V_4Y plot_v1
+U2 V_1Y plot_v1
+U3 V_2Y plot_v1
+V_2B1 Net-_U1-Pad4_ GND DC
+.end
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.cir.out b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.cir.out
new file mode 100644
index 000000000..9e998a8bb
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.cir.out
@@ -0,0 +1,42 @@
+.title kicad schematic
+
+.include 74HC02.sub
+* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u7-pad3_ net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ adc_bridge_4
+v5 net-_x1-pad14_ gnd 5
+v_4b1 net-_u7-pad1_ gnd  dc 5
+v_4a1 net-_u7-pad2_ gnd  dc 5
+v_3b1 net-_u7-pad3_ gnd  dc 0
+v_3a1 net-_u7-pad4_ gnd  dc 5
+x1 net-_u4-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ net-_u1-pad7_ net-_u1-pad8_ gnd net-_u7-pad8_ net-_u7-pad7_ net-_u4-pad2_ net-_u7-pad6_ net-_u7-pad5_ net-_u4-pad1_ net-_x1-pad14_ 74HC02
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
+v_2a1 net-_u1-pad3_ gnd  dc 0
+v_1b1 net-_u1-pad2_ gnd  dc 0
+v_1a1 net-_u1-pad1_ gnd  dc 0
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ v_4y v_3y v_2y v_1y dac_bridge_4
+* u5 v_3y plot_v1
+* u6 v_4y plot_v1
+* u2 v_1y plot_v1
+* u3 v_2y plot_v1
+v_2b1 net-_u1-pad4_ gnd  dc 5
+a1 [net-_u7-pad1_ net-_u7-pad2_ net-_u7-pad3_ net-_u7-pad4_ ] [net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ ] u7
+a2 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+a3 [net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ ] [v_4y v_3y v_2y v_1y ] u4
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 1e-00 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_3y)
+plot v(v_4y)
+plot v(v_1y)
+plot v(v_2y)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.kicad_sch b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.kicad_sch
new file mode 100644
index 000000000..9e92dc2de
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.kicad_sch
@@ -0,0 +1,1125 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.proj b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.proj
new file mode 100644
index 000000000..73f8971d8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.proj
@@ -0,0 +1 @@
+schematicFile 74HC02_TEST.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.raw b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.raw
new file mode 100644
index 000000000..17152ec34
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST.raw
@@ -0,0 +1,1628 @@
+Title: kicad schematic
+Date: Mon Jan 26 17:02:29  2026
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 27
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(net-_x1-pad14_)	voltage
+	2	v(net-_u7-pad1_)	voltage
+	3	v(net-_u7-pad2_)	voltage
+	4	v(net-_u7-pad3_)	voltage
+	5	v(net-_u7-pad4_)	voltage
+	6	v(net-_u1-pad3_)	voltage
+	7	v(net-_u1-pad2_)	voltage
+	8	v(net-_u1-pad1_)	voltage
+	9	v(net-_u1-pad4_)	voltage
+	10	v(v_4y)	voltage
+	11	v(v_3y)	voltage
+	12	v(v_2y)	voltage
+	13	v(v_1y)	voltage
+	14	i(v_2b1)	current
+	15	i(v_1a1)	current
+	16	i(v_1b1)	current
+	17	i(v_2a1)	current
+	18	i(v_3a1)	current
+	19	i(v_3b1)	current
+	20	i(v_4a1)	current
+	21	i(v_4b1)	current
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diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST_Previous_Values.xml
new file mode 100644
index 000000000..0de9cc799
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/74HC02_TEST_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source><v5 name="Source type">5</v5><v_4b1 name="Source type">dc<field1 name="Value">5</field1></v_4b1><v_4a1 name="Source type">dc<field1 name="Value">5</field1></v_4a1><v_3b1 name="Source type">dc<field1 name="Value">0</field1></v_3b1><v_3a1 name="Source type">dc<field1 name="Value">5</field1></v_3a1><v_2a1 name="Source type">dc<field1 name="Value">0</field1></v_2a1><v_1b1 name="Source type">dc<field1 name="Value">0</field1></v_1b1><v_1a1 name="Source type">dc<field1 name="Value">0</field1></v_1a1><v_2b1 name="Source type">dc<field1 name="Value">5</field1></v_2b1></source><model><u7 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u7><u1 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u1><u4 name="type">dac_bridge<field9 name="Enter value for out_low (default=0.0)" /><field10 name="Enter value for out_high (default=5.0)" /><field11 name="Enter value for out_undef (default=0.5)" /><field12 name="Enter value for input load (default=1.0e-12)" /><field13 name="Enter the Rise Time (default=1.0e-9)" /><field14 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC02</field></x1></subcircuit><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/_autosave-74HC02.sch b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/_autosave-74HC02.sch
new file mode 100644
index 000000000..d5ca9849f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/_autosave-74HC02.sch
@@ -0,0 +1,441 @@
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diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/analysis b/library/SubcircuitLibrary/IC74HC02/74HC02/74HC02_Test_Circuit/74HC02_TEST/analysis
new file mode 100644
index 000000000..14a32166e
--- /dev/null
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\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/_autosave-74HC02.sch b/library/SubcircuitLibrary/IC74HC02/74HC02/_autosave-74HC02.sch
new file mode 100644
index 000000000..d5ca9849f
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+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Wire Wire Line
+	3600 7550 3975 7550
+Wire Wire Line
+	3650 4075 4025 4075
+Wire Wire Line
+	3725 8375 3975 8375
+Wire Wire Line
+	3750 4875 4000 4875
+Wire Wire Line
+	3750 5825 4025 5825
+Wire Wire Line
+	3750 6725 4025 6725
+Wire Wire Line
+	3775 2200 4025 2200
+Wire Wire Line
+	3775 3000 4000 3000
+Wire Wire Line
+	5575 2200 4625 2200
+Wire Wire Line
+	5575 2500 5575 2200
+Wire Wire Line
+	5575 2600 5575 3000
+Wire Wire Line
+	5575 3000 4600 3000
+Wire Wire Line
+	5600 4075 4625 4075
+Wire Wire Line
+	5600 4350 5600 4075
+Wire Wire Line
+	5600 4450 5600 4875
+Wire Wire Line
+	5600 4875 4600 4875
+Wire Wire Line
+	5625 7550 4575 7550
+Wire Wire Line
+	5625 7850 5625 7550
+Wire Wire Line
+	5625 7950 5625 8375
+Wire Wire Line
+	5625 8375 4575 8375
+Wire Wire Line
+	5650 5825 4625 5825
+Wire Wire Line
+	5650 6175 5650 5825
+Wire Wire Line
+	5650 6275 5650 6725
+Wire Wire Line
+	5650 6725 4625 6725
+Wire Wire Line
+	6475 2550 7550 2550
+Wire Wire Line
+	6500 4400 7450 4400
+Wire Wire Line
+	6525 7900 7475 7900
+Wire Wire Line
+	6550 6225 7575 6225
+Wire Wire Line
+	8050 4400 8325 4400
+Wire Wire Line
+	8075 7900 8475 7900
+Wire Wire Line
+	8150 2550 8450 2550
+Wire Wire Line
+	8175 6225 8625 6225
+Wire Wire Line
+	10550 6075 10850 6075
+Wire Wire Line
+	10550 6700 10875 6700
+$Comp
+L eSim_Power:eSim_GND #PWR01
+U 1 1 00000000
+P 10850 6075
+F 0 "#PWR01" H 10850 5825 50  0001 C CNN
+F 1 "eSim_GND" H 10850 5900 50  0000 C CNN
+F 2 "" H 10850 6075 50  0001 C CNN
+F 3 "" H 10850 6075 50  0001 C CNN
+	1    10850 6075
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Power:eSim_GND #PWR02
+U 1 1 00000000
+P 10875 6700
+F 0 "#PWR02" H 10875 6450 50  0001 C CNN
+F 1 "eSim_GND" H 10875 6500 50  0000 C CNN
+F 2 "" H 10875 6700 50  0001 C CNN
+F 3 "" H 10875 6700 50  0001 C CNN
+	1    10875 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 11 1 00000000
+P 3350 7550
+F 0 "U1" H 3375 7725 30  0000 C CNN
+F 1 "PORT" H 3375 7625 30  0000 C CNN
+F 2 "" H 3350 7550 60  0000 C CNN
+F 3 "" H 3350 7550 60  0000 C CNN
+	11   3350 7550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 5 1 00000000
+P 3400 4075
+F 0 "U1" H 3425 4275 30  0000 C CNN
+F 1 "PORT" H 3425 4175 30  0000 C CNN
+F 2 "" H 3400 4075 60  0000 C CNN
+F 3 "" H 3400 4075 60  0000 C CNN
+	5    3400 4075
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 12 1 00000000
+P 3475 8375
+F 0 "U1" H 3500 8575 30  0000 C CNN
+F 1 "PORT" H 3500 8475 30  0000 C CNN
+F 2 "" H 3475 8375 60  0000 C CNN
+F 3 "" H 3475 8375 60  0000 C CNN
+	12   3475 8375
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 6 1 00000000
+P 3500 4875
+F 0 "U1" H 3525 5075 30  0000 C CNN
+F 1 "PORT" H 3525 4975 30  0000 C CNN
+F 2 "" H 3500 4875 60  0000 C CNN
+F 3 "" H 3500 4875 60  0000 C CNN
+	6    3500 4875
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 8 1 00000000
+P 3500 5825
+F 0 "U1" H 3525 6000 30  0000 C CNN
+F 1 "PORT" H 3525 5900 30  0000 C CNN
+F 2 "" H 3500 5825 60  0000 C CNN
+F 3 "" H 3500 5825 60  0000 C CNN
+	8    3500 5825
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 9 1 00000000
+P 3500 6725
+F 0 "U1" H 3525 6925 30  0000 C CNN
+F 1 "PORT" H 3525 6825 30  0000 C CNN
+F 2 "" H 3500 6725 60  0000 C CNN
+F 3 "" H 3500 6725 60  0000 C CNN
+	9    3500 6725
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 2 1 00000000
+P 3525 2200
+F 0 "U1" H 3550 2375 30  0000 C CNN
+F 1 "PORT" H 3550 2275 30  0000 C CNN
+F 2 "" H 3525 2200 60  0000 C CNN
+F 3 "" H 3525 2200 60  0000 C CNN
+	2    3525 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 3 1 00000000
+P 3525 3000
+F 0 "U1" H 3550 3200 30  0000 C CNN
+F 1 "PORT" H 3550 3100 30  0000 C CNN
+F 2 "" H 3525 3000 60  0000 C CNN
+F 3 "" H 3525 3000 60  0000 C CNN
+	3    3525 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 4 1 00000000
+P 8575 4400
+F 0 "U1" H 8450 4425 30  0000 R CNN
+F 1 "PORT" H 8450 4325 30  0000 R CNN
+F 2 "" H 8575 4400 60  0000 C CNN
+F 3 "" H 8575 4400 60  0000 C CNN
+	4    8575 4400
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 1 1 00000000
+P 8700 2550
+F 0 "U1" H 8575 2575 30  0000 R CNN
+F 1 "PORT" H 8575 2475 30  0000 R CNN
+F 2 "" H 8700 2550 60  0000 C CNN
+F 3 "" H 8700 2550 60  0000 C CNN
+	1    8700 2550
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 13 1 00000000
+P 8725 7900
+F 0 "U1" H 8600 7925 30  0000 R CNN
+F 1 "PORT" H 8600 7825 30  0000 R CNN
+F 2 "" H 8725 7900 60  0000 C CNN
+F 3 "" H 8725 7900 60  0000 C CNN
+	13   8725 7900
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 10 1 00000000
+P 8875 6225
+F 0 "U1" H 8750 6250 30  0000 R CNN
+F 1 "PORT" H 8750 6150 30  0000 R CNN
+F 2 "" H 8875 6225 60  0000 C CNN
+F 3 "" H 8875 6225 60  0000 C CNN
+	10   8875 6225
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 7 1 00000000
+P 10300 6075
+F 0 "U1" H 10325 6250 30  0000 C CNN
+F 1 "PORT" H 10325 6150 30  0000 C CNN
+F 2 "" H 10300 6075 60  0000 C CNN
+F 3 "" H 10300 6075 60  0000 C CNN
+	7    10300 6075
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 14 1 00000000
+P 10300 6700
+F 0 "U1" H 10325 6900 30  0000 C CNN
+F 1 "PORT" H 10325 6800 30  0000 C CNN
+F 2 "" H 10300 6700 60  0000 C CNN
+F 3 "" H 10300 6700 60  0000 C CNN
+	14   10300 6700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U2
+U 1 1 00000000
+P 4275 7550
+F 0 "U2" H 4275 7800 60  0000 C CNN
+F 1 "d_inverter" H 4275 7650 60  0000 C CNN
+F 2 "" H 4325 7500 60  0000 C CNN
+F 3 "" H 4325 7500 60  0000 C CNN
+	1    4275 7550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U3
+U 1 1 00000000
+P 4275 8375
+F 0 "U3" H 4275 8650 60  0000 C CNN
+F 1 "d_inverter" H 4275 8500 60  0000 C CNN
+F 2 "" H 4325 8325 60  0000 C CNN
+F 3 "" H 4325 8325 60  0000 C CNN
+	1    4275 8375
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U4
+U 1 1 00000000
+P 4300 3000
+F 0 "U4" H 4300 3250 60  0000 C CNN
+F 1 "d_inverter" H 4300 3100 60  0000 C CNN
+F 2 "" H 4350 2950 60  0000 C CNN
+F 3 "" H 4350 2950 60  0000 C CNN
+	1    4300 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U5
+U 1 1 00000000
+P 4300 4875
+F 0 "U5" H 4300 5150 60  0000 C CNN
+F 1 "d_inverter" H 4300 5000 60  0000 C CNN
+F 2 "" H 4350 4825 60  0000 C CNN
+F 3 "" H 4350 4825 60  0000 C CNN
+	1    4300 4875
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U6
+U 1 1 00000000
+P 4325 2200
+F 0 "U6" H 4325 2450 60  0000 C CNN
+F 1 "d_inverter" H 4325 2300 60  0000 C CNN
+F 2 "" H 4375 2150 60  0000 C CNN
+F 3 "" H 4375 2150 60  0000 C CNN
+	1    4325 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U7
+U 1 1 00000000
+P 4325 4075
+F 0 "U7" H 4325 4350 60  0000 C CNN
+F 1 "d_inverter" H 4325 4200 60  0000 C CNN
+F 2 "" H 4375 4025 60  0000 C CNN
+F 3 "" H 4375 4025 60  0000 C CNN
+	1    4325 4075
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U8
+U 1 1 00000000
+P 4325 5825
+F 0 "U8" H 4325 6100 60  0000 C CNN
+F 1 "d_inverter" H 4325 5950 60  0000 C CNN
+F 2 "" H 4375 5775 60  0000 C CNN
+F 3 "" H 4375 5775 60  0000 C CNN
+	1    4325 5825
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U9
+U 1 1 00000000
+P 4325 6725
+F 0 "U9" H 4325 7000 60  0000 C CNN
+F 1 "d_inverter" H 4325 6850 60  0000 C CNN
+F 2 "" H 4375 6675 60  0000 C CNN
+F 3 "" H 4375 6675 60  0000 C CNN
+	1    4325 6725
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 7750 4400
+F 0 "U14" H 7750 4675 60  0000 C CNN
+F 1 "d_inverter" H 7750 4525 60  0000 C CNN
+F 2 "" H 7800 4350 60  0000 C CNN
+F 3 "" H 7800 4350 60  0000 C CNN
+	1    7750 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U15
+U 1 1 00000000
+P 7775 7900
+F 0 "U15" H 7775 8150 60  0000 C CNN
+F 1 "d_inverter" H 7775 8000 60  0000 C CNN
+F 2 "" H 7825 7850 60  0000 C CNN
+F 3 "" H 7825 7850 60  0000 C CNN
+	1    7775 7900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U16
+U 1 1 00000000
+P 7850 2550
+F 0 "U16" H 7850 2800 60  0000 C CNN
+F 1 "d_inverter" H 7850 2650 60  0000 C CNN
+F 2 "" H 7900 2500 60  0000 C CNN
+F 3 "" H 7900 2500 60  0000 C CNN
+	1    7850 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U17
+U 1 1 00000000
+P 7875 6225
+F 0 "U17" H 7875 6500 60  0000 C CNN
+F 1 "d_inverter" H 7875 6350 60  0000 C CNN
+F 2 "" H 7925 6175 60  0000 C CNN
+F 3 "" H 7925 6175 60  0000 C CNN
+	1    7875 6225
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U10
+U 1 1 00000000
+P 6025 2600
+F 0 "U10" H 6025 2950 60  0000 C CNN
+F 1 "d_nand" H 6025 2800 60  0000 C CNN
+F 2 "" H 6025 2600 60  0000 C CNN
+F 3 "" H 6025 2600 60  0000 C CNN
+	1    6025 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U11
+U 1 1 00000000
+P 6050 4450
+F 0 "U11" H 6050 4800 60  0000 C CNN
+F 1 "d_nand" H 6050 4650 60  0000 C CNN
+F 2 "" H 6050 4450 60  0000 C CNN
+F 3 "" H 6050 4450 60  0000 C CNN
+	1    6050 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U12
+U 1 1 00000000
+P 6075 7950
+F 0 "U12" H 6075 8300 60  0000 C CNN
+F 1 "d_nand" H 6075 8150 60  0000 C CNN
+F 2 "" H 6075 7950 60  0000 C CNN
+F 3 "" H 6075 7950 60  0000 C CNN
+	1    6075 7950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U13
+U 1 1 00000000
+P 6100 6275
+F 0 "U13" H 6100 6650 60  0000 C CNN
+F 1 "d_nand" H 6100 6500 60  0000 C CNN
+F 2 "" H 6100 6275 60  0000 C CNN
+F 3 "" H 6100 6275 60  0000 C CNN
+	1    6100 6275
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC02/74HC02/analysis b/library/SubcircuitLibrary/IC74HC02/74HC02/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC02/74HC02/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.cir b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.cir
new file mode 100644
index 000000000..da0d22682
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.cir
@@ -0,0 +1,56 @@
+.title KiCad schematic
+M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N
+U35 Net-_U21-Pad3_ Net-_M3-Pad2_ dac_bridge_1
+U34 Net-_U30-Pad3_ Net-_M1-Pad2_ dac_bridge_1
+U30 Net-_U28-Pad2_ Net-_U20-Pad2_ Net-_U30-Pad3_ d_and
+U40 Net-_U32-Pad3_ Net-_M4-Pad2_ dac_bridge_1
+M4 Net-_M4-Pad1_ Net-_M4-Pad2_ GND GND eSim_MOS_N
+M7 Net-_M4-Pad1_ Net-_M7-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+U38 Net-_U23-Pad3_ Net-_M7-Pad2_ dac_bridge_1
+M6 Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+U19 Net-_U16-Pad2_ Net-_U19-Pad2_ d_inverter
+U27 Net-_U11-Pad2_ Net-_U27-Pad2_ d_inverter
+U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter
+U24 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U24-Pad3_ d_nand
+U22 Net-_U15-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_nand
+U26 Net-_U22-Pad2_ Net-_U26-Pad2_ d_inverter
+U18 Net-_U15-Pad2_ Net-_U18-Pad2_ d_inverter
+U36 Net-_U31-Pad3_ Net-_M2-Pad2_ dac_bridge_1
+U32 Net-_U27-Pad2_ Net-_U19-Pad2_ Net-_U32-Pad3_ d_and
+U37 Net-_U22-Pad3_ Net-_M6-Pad2_ dac_bridge_1
+U31 Net-_U26-Pad2_ Net-_U18-Pad2_ Net-_U31-Pad3_ d_and
+U29 Net-_U13-Pad2_ Net-_U29-Pad2_ d_inverter
+U33 Net-_U29-Pad2_ Net-_U25-Pad2_ Net-_U33-Pad3_ d_and
+U39 Net-_U24-Pad3_ Net-_M8-Pad2_ dac_bridge_1
+U41 Net-_U33-Pad3_ Net-_M5-Pad2_ dac_bridge_1
+U7 Net-_U2-Pad2_ Net-_U21-Pad2_ d_inverter
+U10 Net-_U1-Pad4_ Net-_U10-Pad2_ d_inverter
+U6 Net-_U1-Pad1_ Net-_U14-Pad1_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+U23 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_nand
+U28 Net-_U21-Pad2_ Net-_U28-Pad2_ d_inverter
+U21 Net-_U14-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_nand
+U20 Net-_U14-Pad2_ Net-_U20-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U12 Net-_U1-Pad13_ Net-_U12-Pad2_ d_inverter
+U17 Net-_U12-Pad2_ Net-_U17-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U5 Net-_U1-Pad12_ Net-_U13-Pad1_ d_inverter
+M5 Net-_M5-Pad1_ Net-_M5-Pad2_ GND GND eSim_MOS_N
+M8 Net-_M5-Pad1_ Net-_M8-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ GND GND eSim_MOS_N
+U45 Net-_M2-Pad1_ Net-_U1-Pad8_ adc_bridge_1
+U44 Net-_M5-Pad1_ Net-_U1-Pad11_ adc_bridge_1
+U4 Net-_U1-Pad5_ Net-_U11-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U8 Net-_U1-Pad10_ Net-_U15-Pad1_ d_inverter
+U3 Net-_U1-Pad9_ Net-_U3-Pad2_ d_inverter
+U9 Net-_U3-Pad2_ Net-_U22-Pad2_ d_inverter
+U16 Net-_U10-Pad2_ Net-_U16-Pad2_ d_inverter
+U42 Net-_M1-Pad1_ Net-_U1-Pad3_ adc_bridge_1
+v1 Net-_M3-Pad3_ GND 5
+U43 Net-_M4-Pad1_ Net-_U1-Pad6_ adc_bridge_1
+.end
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.cir.out b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.cir.out
new file mode 100644
index 000000000..dc9d4e11e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.cir.out
@@ -0,0 +1,199 @@
+.title kicad schematic
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m3 net-_m1-pad1_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u35 net-_u21-pad3_ net-_m3-pad2_ dac_bridge_1
+* u34 net-_u30-pad3_ net-_m1-pad2_ dac_bridge_1
+* u30 net-_u28-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and
+* u40 net-_u32-pad3_ net-_m4-pad2_ dac_bridge_1
+m4 net-_m4-pad1_ net-_m4-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m7 net-_m4-pad1_ net-_m7-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u38 net-_u23-pad3_ net-_m7-pad2_ dac_bridge_1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u19 net-_u16-pad2_ net-_u19-pad2_ d_inverter
+* u27 net-_u11-pad2_ net-_u27-pad2_ d_inverter
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_nand
+* u22 net-_u15-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand
+* u26 net-_u22-pad2_ net-_u26-pad2_ d_inverter
+* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter
+* u36 net-_u31-pad3_ net-_m2-pad2_ dac_bridge_1
+* u32 net-_u27-pad2_ net-_u19-pad2_ net-_u32-pad3_ d_and
+* u37 net-_u22-pad3_ net-_m6-pad2_ dac_bridge_1
+* u31 net-_u26-pad2_ net-_u18-pad2_ net-_u31-pad3_ d_and
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u33 net-_u29-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and
+* u39 net-_u24-pad3_ net-_m8-pad2_ dac_bridge_1
+* u41 net-_u33-pad3_ net-_m5-pad2_ dac_bridge_1
+* u7 net-_u2-pad2_ net-_u21-pad2_ d_inverter
+* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad1_ net-_u14-pad1_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_nand
+* u28 net-_u21-pad2_ net-_u28-pad2_ d_inverter
+* u21 net-_u14-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_nand
+* u20 net-_u14-pad2_ net-_u20-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u12 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u17 net-_u12-pad2_ net-_u17-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u13-pad1_ d_inverter
+m5 net-_m5-pad1_ net-_m5-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m8 net-_m5-pad1_ net-_m8-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u45 net-_m2-pad1_ net-_u1-pad8_ adc_bridge_1
+* u44 net-_m5-pad1_ net-_u1-pad11_ adc_bridge_1
+* u4 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u3 net-_u1-pad9_ net-_u3-pad2_ d_inverter
+* u9 net-_u3-pad2_ net-_u22-pad2_ d_inverter
+* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter
+* u42 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+v1 net-_m3-pad3_ gnd 5
+* u43 net-_m4-pad1_ net-_u1-pad6_ adc_bridge_1
+a1 [net-_u21-pad3_ ] [net-_m3-pad2_ ] u35
+a2 [net-_u30-pad3_ ] [net-_m1-pad2_ ] u34
+a3 [net-_u28-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30
+a4 [net-_u32-pad3_ ] [net-_m4-pad2_ ] u40
+a5 [net-_u23-pad3_ ] [net-_m7-pad2_ ] u38
+a6 net-_u16-pad2_ net-_u19-pad2_ u19
+a7 net-_u11-pad2_ net-_u27-pad2_ u27
+a8 net-_u17-pad2_ net-_u25-pad2_ u25
+a9 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
+a10 [net-_u15-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a11 net-_u22-pad2_ net-_u26-pad2_ u26
+a12 net-_u15-pad2_ net-_u18-pad2_ u18
+a13 [net-_u31-pad3_ ] [net-_m2-pad2_ ] u36
+a14 [net-_u27-pad2_ net-_u19-pad2_ ] net-_u32-pad3_ u32
+a15 [net-_u22-pad3_ ] [net-_m6-pad2_ ] u37
+a16 [net-_u26-pad2_ net-_u18-pad2_ ] net-_u31-pad3_ u31
+a17 net-_u13-pad2_ net-_u29-pad2_ u29
+a18 [net-_u29-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33
+a19 [net-_u24-pad3_ ] [net-_m8-pad2_ ] u39
+a20 [net-_u33-pad3_ ] [net-_m5-pad2_ ] u41
+a21 net-_u2-pad2_ net-_u21-pad2_ u7
+a22 net-_u1-pad4_ net-_u10-pad2_ u10
+a23 net-_u1-pad1_ net-_u14-pad1_ u6
+a24 net-_u14-pad1_ net-_u14-pad2_ u14
+a25 net-_u1-pad2_ net-_u2-pad2_ u2
+a26 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a27 net-_u21-pad2_ net-_u28-pad2_ u28
+a28 [net-_u14-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a29 net-_u14-pad2_ net-_u20-pad2_ u20
+a30 net-_u13-pad1_ net-_u13-pad2_ u13
+a31 net-_u1-pad13_ net-_u12-pad2_ u12
+a32 net-_u12-pad2_ net-_u17-pad2_ u17
+a33 net-_u15-pad1_ net-_u15-pad2_ u15
+a34 net-_u1-pad12_ net-_u13-pad1_ u5
+a35 [net-_m2-pad1_ ] [net-_u1-pad8_ ] u45
+a36 [net-_m5-pad1_ ] [net-_u1-pad11_ ] u44
+a37 net-_u1-pad5_ net-_u11-pad1_ u4
+a38 net-_u11-pad1_ net-_u11-pad2_ u11
+a39 net-_u1-pad10_ net-_u15-pad1_ u8
+a40 net-_u1-pad9_ net-_u3-pad2_ u3
+a41 net-_u3-pad2_ net-_u22-pad2_ u9
+a42 net-_u10-pad2_ net-_u16-pad2_ u16
+a43 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u42
+a44 [net-_m4-pad1_ ] [net-_u1-pad6_ ] u43
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u40 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u36 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u39 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u41 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u45 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u44 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u43 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.kicad_sch b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.kicad_sch
new file mode 100644
index 000000000..312e69cfe
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.kicad_sch
@@ -0,0 +1,3312 @@
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+      (reference "v1") (unit 1) (value "5") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.sub b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.sub
new file mode 100644
index 000000000..b540ebaa5
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125.sub
@@ -0,0 +1,193 @@
+* Subcircuit 74HC125
+.subckt 74HC125 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m3 net-_m1-pad1_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u35 net-_u21-pad3_ net-_m3-pad2_ dac_bridge_1
+* u34 net-_u30-pad3_ net-_m1-pad2_ dac_bridge_1
+* u30 net-_u28-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and
+* u40 net-_u32-pad3_ net-_m4-pad2_ dac_bridge_1
+m4 net-_m4-pad1_ net-_m4-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m7 net-_m4-pad1_ net-_m7-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u38 net-_u23-pad3_ net-_m7-pad2_ dac_bridge_1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u19 net-_u16-pad2_ net-_u19-pad2_ d_inverter
+* u27 net-_u11-pad2_ net-_u27-pad2_ d_inverter
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_nand
+* u22 net-_u15-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand
+* u26 net-_u22-pad2_ net-_u26-pad2_ d_inverter
+* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter
+* u36 net-_u31-pad3_ net-_m2-pad2_ dac_bridge_1
+* u32 net-_u27-pad2_ net-_u19-pad2_ net-_u32-pad3_ d_and
+* u37 net-_u22-pad3_ net-_m6-pad2_ dac_bridge_1
+* u31 net-_u26-pad2_ net-_u18-pad2_ net-_u31-pad3_ d_and
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u33 net-_u29-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and
+* u39 net-_u24-pad3_ net-_m8-pad2_ dac_bridge_1
+* u41 net-_u33-pad3_ net-_m5-pad2_ dac_bridge_1
+* u7 net-_u2-pad2_ net-_u21-pad2_ d_inverter
+* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad1_ net-_u14-pad1_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_nand
+* u28 net-_u21-pad2_ net-_u28-pad2_ d_inverter
+* u21 net-_u14-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_nand
+* u20 net-_u14-pad2_ net-_u20-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u12 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u17 net-_u12-pad2_ net-_u17-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u13-pad1_ d_inverter
+m5 net-_m5-pad1_ net-_m5-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m8 net-_m5-pad1_ net-_m8-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u45 net-_m2-pad1_ net-_u1-pad8_ adc_bridge_1
+* u44 net-_m5-pad1_ net-_u1-pad11_ adc_bridge_1
+* u4 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u3 net-_u1-pad9_ net-_u3-pad2_ d_inverter
+* u9 net-_u3-pad2_ net-_u22-pad2_ d_inverter
+* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter
+* u42 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+v1 net-_m3-pad3_ gnd 5
+* u43 net-_m4-pad1_ net-_u1-pad6_ adc_bridge_1
+a1 [net-_u21-pad3_ ] [net-_m3-pad2_ ] u35
+a2 [net-_u30-pad3_ ] [net-_m1-pad2_ ] u34
+a3 [net-_u28-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30
+a4 [net-_u32-pad3_ ] [net-_m4-pad2_ ] u40
+a5 [net-_u23-pad3_ ] [net-_m7-pad2_ ] u38
+a6 net-_u16-pad2_ net-_u19-pad2_ u19
+a7 net-_u11-pad2_ net-_u27-pad2_ u27
+a8 net-_u17-pad2_ net-_u25-pad2_ u25
+a9 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
+a10 [net-_u15-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a11 net-_u22-pad2_ net-_u26-pad2_ u26
+a12 net-_u15-pad2_ net-_u18-pad2_ u18
+a13 [net-_u31-pad3_ ] [net-_m2-pad2_ ] u36
+a14 [net-_u27-pad2_ net-_u19-pad2_ ] net-_u32-pad3_ u32
+a15 [net-_u22-pad3_ ] [net-_m6-pad2_ ] u37
+a16 [net-_u26-pad2_ net-_u18-pad2_ ] net-_u31-pad3_ u31
+a17 net-_u13-pad2_ net-_u29-pad2_ u29
+a18 [net-_u29-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33
+a19 [net-_u24-pad3_ ] [net-_m8-pad2_ ] u39
+a20 [net-_u33-pad3_ ] [net-_m5-pad2_ ] u41
+a21 net-_u2-pad2_ net-_u21-pad2_ u7
+a22 net-_u1-pad4_ net-_u10-pad2_ u10
+a23 net-_u1-pad1_ net-_u14-pad1_ u6
+a24 net-_u14-pad1_ net-_u14-pad2_ u14
+a25 net-_u1-pad2_ net-_u2-pad2_ u2
+a26 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a27 net-_u21-pad2_ net-_u28-pad2_ u28
+a28 [net-_u14-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a29 net-_u14-pad2_ net-_u20-pad2_ u20
+a30 net-_u13-pad1_ net-_u13-pad2_ u13
+a31 net-_u1-pad13_ net-_u12-pad2_ u12
+a32 net-_u12-pad2_ net-_u17-pad2_ u17
+a33 net-_u15-pad1_ net-_u15-pad2_ u15
+a34 net-_u1-pad12_ net-_u13-pad1_ u5
+a35 [net-_m2-pad1_ ] [net-_u1-pad8_ ] u45
+a36 [net-_m5-pad1_ ] [net-_u1-pad11_ ] u44
+a37 net-_u1-pad5_ net-_u11-pad1_ u4
+a38 net-_u11-pad1_ net-_u11-pad2_ u11
+a39 net-_u1-pad10_ net-_u15-pad1_ u8
+a40 net-_u1-pad9_ net-_u3-pad2_ u3
+a41 net-_u3-pad2_ net-_u22-pad2_ u9
+a42 net-_u10-pad2_ net-_u16-pad2_ u16
+a43 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u42
+a44 [net-_m4-pad1_ ] [net-_u1-pad6_ ] u43
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u40 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u36 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u39 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u41 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u45 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u44 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u43 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC125
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Previous_Values.xml
new file mode 100644
index 000000000..26c7067cb
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source><v1 name="Source type">5</v1></source><model><u35 name="type">dac_bridge<field1 name="Enter value for out_low (default=0.0)" /><field2 name="Enter value for out_high (default=5.0)" /><field3 name="Enter value for out_undef (default=0.5)" /><field4 name="Enter value for input load (default=1.0e-12)" /><field5 name="Enter the Rise Time (default=1.0e-9)" /><field6 name="Enter the Fall Time (default=1.0e-9)" /></u35><u34 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u34><u30 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u30><u40 name="type">dac_bridge<field16 name="Enter value for out_low (default=0.0)" /><field17 name="Enter value for out_high (default=5.0)" /><field18 name="Enter value for out_undef (default=0.5)" /><field19 name="Enter value for input load (default=1.0e-12)" /><field20 name="Enter the Rise Time (default=1.0e-9)" /><field21 name="Enter the Fall Time (default=1.0e-9)" /></u40><u38 name="type">dac_bridge<field22 name="Enter value for out_low (default=0.0)" /><field23 name="Enter value for out_high (default=5.0)" /><field24 name="Enter value for out_undef (default=0.5)" /><field25 name="Enter value for input load (default=1.0e-12)" /><field26 name="Enter the Rise Time (default=1.0e-9)" /><field27 name="Enter the Fall Time (default=1.0e-9)" /></u38><u19 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u19><u27 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u27><u25 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u25><u24 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u26><u18 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u18><u36 name="type">dac_bridge<field49 name="Enter value for out_low (default=0.0)" /><field50 name="Enter value for out_high (default=5.0)" /><field51 name="Enter value for out_undef (default=0.5)" /><field52 name="Enter value for input load (default=1.0e-12)" /><field53 name="Enter the Rise Time (default=1.0e-9)" /><field54 name="Enter the Fall Time (default=1.0e-9)" /></u36><u32 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u32><u37 name="type">dac_bridge<field58 name="Enter value for out_low (default=0.0)" /><field59 name="Enter value for out_high (default=5.0)" /><field60 name="Enter value for out_undef (default=0.5)" /><field61 name="Enter value for input load (default=1.0e-12)" /><field62 name="Enter the Rise Time (default=1.0e-9)" /><field63 name="Enter the Fall Time (default=1.0e-9)" /></u37><u31 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u31><u29 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u29><u33 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u33><u39 name="type">dac_bridge<field73 name="Enter value for out_low (default=0.0)" /><field74 name="Enter value for out_high (default=5.0)" /><field75 name="Enter value for out_undef (default=0.5)" /><field76 name="Enter value for input load (default=1.0e-12)" /><field77 name="Enter the Rise Time (default=1.0e-9)" /><field78 name="Enter the Fall Time (default=1.0e-9)" /></u39><u41 name="type">dac_bridge<field79 name="Enter value for out_low (default=0.0)" /><field80 name="Enter value for out_high (default=5.0)" /><field81 name="Enter value for out_undef (default=0.5)" /><field82 name="Enter value for input load (default=1.0e-12)" /><field83 name="Enter the Rise Time (default=1.0e-9)" /><field84 name="Enter the Fall Time (default=1.0e-9)" /></u41><u7 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u10><u6 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u6><u14 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u14><u2 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u2><u23 name="type">d_nand<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u23><u28 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u28><u21 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u20><u13 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u12><u17 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u17><u15 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u15><u5 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u5><u45 name="type">adc_bridge<field127 name="Enter value for in_low (default=1.0)" /><field128 name="Enter value for in_high (default=2.0)" /><field129 name="Enter Rise Delay (default=1.0e-9)" /><field130 name="Enter Fall Delay (default=1.0e-9)" /></u45><u44 name="type">adc_bridge<field131 name="Enter value for in_low (default=1.0)" /><field132 name="Enter value for in_high (default=2.0)" /><field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /></u44><u4 name="type">d_inverter<field135 name="Enter Rise Delay (default=1.0e-9)" /><field136 name="Enter Fall Delay (default=1.0e-9)" /><field137 name="Enter Input Load (default=1.0e-12)" /></u4><u11 name="type">d_inverter<field138 name="Enter Rise Delay (default=1.0e-9)" /><field139 name="Enter Fall Delay (default=1.0e-9)" /><field140 name="Enter Input Load (default=1.0e-12)" /></u11><u8 name="type">d_inverter<field141 name="Enter Rise Delay (default=1.0e-9)" /><field142 name="Enter Fall Delay (default=1.0e-9)" /><field143 name="Enter Input Load (default=1.0e-12)" /></u8><u3 name="type">d_inverter<field144 name="Enter Rise Delay (default=1.0e-9)" /><field145 name="Enter Fall Delay (default=1.0e-9)" /><field146 name="Enter Input Load (default=1.0e-12)" /></u3><u9 name="type">d_inverter<field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /><field149 name="Enter Input Load (default=1.0e-12)" /></u9><u16 name="type">d_inverter<field150 name="Enter Rise Delay (default=1.0e-9)" /><field151 name="Enter Fall Delay (default=1.0e-9)" /><field152 name="Enter Input Load (default=1.0e-12)" /></u16><u42 name="type">adc_bridge<field153 name="Enter value for in_low (default=1.0)" /><field154 name="Enter value for in_high (default=2.0)" /><field155 name="Enter Rise Delay (default=1.0e-9)" /><field156 name="Enter Fall Delay (default=1.0e-9)" /></u42><u43 name="type">adc_bridge<field157 name="Enter value for in_low (default=1.0)" /><field158 name="Enter value for in_high (default=2.0)" /><field159 name="Enter Rise Delay (default=1.0e-9)" /><field160 name="Enter Fall Delay (default=1.0e-9)" /></u43></model><devicemodel><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.cir b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.cir
new file mode 100644
index 000000000..da0d22682
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.cir
@@ -0,0 +1,56 @@
+.title KiCad schematic
+M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N
+U35 Net-_U21-Pad3_ Net-_M3-Pad2_ dac_bridge_1
+U34 Net-_U30-Pad3_ Net-_M1-Pad2_ dac_bridge_1
+U30 Net-_U28-Pad2_ Net-_U20-Pad2_ Net-_U30-Pad3_ d_and
+U40 Net-_U32-Pad3_ Net-_M4-Pad2_ dac_bridge_1
+M4 Net-_M4-Pad1_ Net-_M4-Pad2_ GND GND eSim_MOS_N
+M7 Net-_M4-Pad1_ Net-_M7-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+U38 Net-_U23-Pad3_ Net-_M7-Pad2_ dac_bridge_1
+M6 Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+U19 Net-_U16-Pad2_ Net-_U19-Pad2_ d_inverter
+U27 Net-_U11-Pad2_ Net-_U27-Pad2_ d_inverter
+U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter
+U24 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U24-Pad3_ d_nand
+U22 Net-_U15-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_nand
+U26 Net-_U22-Pad2_ Net-_U26-Pad2_ d_inverter
+U18 Net-_U15-Pad2_ Net-_U18-Pad2_ d_inverter
+U36 Net-_U31-Pad3_ Net-_M2-Pad2_ dac_bridge_1
+U32 Net-_U27-Pad2_ Net-_U19-Pad2_ Net-_U32-Pad3_ d_and
+U37 Net-_U22-Pad3_ Net-_M6-Pad2_ dac_bridge_1
+U31 Net-_U26-Pad2_ Net-_U18-Pad2_ Net-_U31-Pad3_ d_and
+U29 Net-_U13-Pad2_ Net-_U29-Pad2_ d_inverter
+U33 Net-_U29-Pad2_ Net-_U25-Pad2_ Net-_U33-Pad3_ d_and
+U39 Net-_U24-Pad3_ Net-_M8-Pad2_ dac_bridge_1
+U41 Net-_U33-Pad3_ Net-_M5-Pad2_ dac_bridge_1
+U7 Net-_U2-Pad2_ Net-_U21-Pad2_ d_inverter
+U10 Net-_U1-Pad4_ Net-_U10-Pad2_ d_inverter
+U6 Net-_U1-Pad1_ Net-_U14-Pad1_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+U23 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_nand
+U28 Net-_U21-Pad2_ Net-_U28-Pad2_ d_inverter
+U21 Net-_U14-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_nand
+U20 Net-_U14-Pad2_ Net-_U20-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U12 Net-_U1-Pad13_ Net-_U12-Pad2_ d_inverter
+U17 Net-_U12-Pad2_ Net-_U17-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U5 Net-_U1-Pad12_ Net-_U13-Pad1_ d_inverter
+M5 Net-_M5-Pad1_ Net-_M5-Pad2_ GND GND eSim_MOS_N
+M8 Net-_M5-Pad1_ Net-_M8-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_P
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ GND GND eSim_MOS_N
+U45 Net-_M2-Pad1_ Net-_U1-Pad8_ adc_bridge_1
+U44 Net-_M5-Pad1_ Net-_U1-Pad11_ adc_bridge_1
+U4 Net-_U1-Pad5_ Net-_U11-Pad1_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U8 Net-_U1-Pad10_ Net-_U15-Pad1_ d_inverter
+U3 Net-_U1-Pad9_ Net-_U3-Pad2_ d_inverter
+U9 Net-_U3-Pad2_ Net-_U22-Pad2_ d_inverter
+U16 Net-_U10-Pad2_ Net-_U16-Pad2_ d_inverter
+U42 Net-_M1-Pad1_ Net-_U1-Pad3_ adc_bridge_1
+v1 Net-_M3-Pad3_ GND 5
+U43 Net-_M4-Pad1_ Net-_U1-Pad6_ adc_bridge_1
+.end
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.cir.out b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.cir.out
new file mode 100644
index 000000000..dc9d4e11e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.cir.out
@@ -0,0 +1,199 @@
+.title kicad schematic
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m3 net-_m1-pad1_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u35 net-_u21-pad3_ net-_m3-pad2_ dac_bridge_1
+* u34 net-_u30-pad3_ net-_m1-pad2_ dac_bridge_1
+* u30 net-_u28-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and
+* u40 net-_u32-pad3_ net-_m4-pad2_ dac_bridge_1
+m4 net-_m4-pad1_ net-_m4-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m7 net-_m4-pad1_ net-_m7-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u38 net-_u23-pad3_ net-_m7-pad2_ dac_bridge_1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u19 net-_u16-pad2_ net-_u19-pad2_ d_inverter
+* u27 net-_u11-pad2_ net-_u27-pad2_ d_inverter
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_nand
+* u22 net-_u15-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand
+* u26 net-_u22-pad2_ net-_u26-pad2_ d_inverter
+* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter
+* u36 net-_u31-pad3_ net-_m2-pad2_ dac_bridge_1
+* u32 net-_u27-pad2_ net-_u19-pad2_ net-_u32-pad3_ d_and
+* u37 net-_u22-pad3_ net-_m6-pad2_ dac_bridge_1
+* u31 net-_u26-pad2_ net-_u18-pad2_ net-_u31-pad3_ d_and
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u33 net-_u29-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and
+* u39 net-_u24-pad3_ net-_m8-pad2_ dac_bridge_1
+* u41 net-_u33-pad3_ net-_m5-pad2_ dac_bridge_1
+* u7 net-_u2-pad2_ net-_u21-pad2_ d_inverter
+* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad1_ net-_u14-pad1_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_nand
+* u28 net-_u21-pad2_ net-_u28-pad2_ d_inverter
+* u21 net-_u14-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_nand
+* u20 net-_u14-pad2_ net-_u20-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u12 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u17 net-_u12-pad2_ net-_u17-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u13-pad1_ d_inverter
+m5 net-_m5-pad1_ net-_m5-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m8 net-_m5-pad1_ net-_m8-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u45 net-_m2-pad1_ net-_u1-pad8_ adc_bridge_1
+* u44 net-_m5-pad1_ net-_u1-pad11_ adc_bridge_1
+* u4 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u3 net-_u1-pad9_ net-_u3-pad2_ d_inverter
+* u9 net-_u3-pad2_ net-_u22-pad2_ d_inverter
+* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter
+* u42 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+v1 net-_m3-pad3_ gnd 5
+* u43 net-_m4-pad1_ net-_u1-pad6_ adc_bridge_1
+a1 [net-_u21-pad3_ ] [net-_m3-pad2_ ] u35
+a2 [net-_u30-pad3_ ] [net-_m1-pad2_ ] u34
+a3 [net-_u28-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30
+a4 [net-_u32-pad3_ ] [net-_m4-pad2_ ] u40
+a5 [net-_u23-pad3_ ] [net-_m7-pad2_ ] u38
+a6 net-_u16-pad2_ net-_u19-pad2_ u19
+a7 net-_u11-pad2_ net-_u27-pad2_ u27
+a8 net-_u17-pad2_ net-_u25-pad2_ u25
+a9 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
+a10 [net-_u15-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a11 net-_u22-pad2_ net-_u26-pad2_ u26
+a12 net-_u15-pad2_ net-_u18-pad2_ u18
+a13 [net-_u31-pad3_ ] [net-_m2-pad2_ ] u36
+a14 [net-_u27-pad2_ net-_u19-pad2_ ] net-_u32-pad3_ u32
+a15 [net-_u22-pad3_ ] [net-_m6-pad2_ ] u37
+a16 [net-_u26-pad2_ net-_u18-pad2_ ] net-_u31-pad3_ u31
+a17 net-_u13-pad2_ net-_u29-pad2_ u29
+a18 [net-_u29-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33
+a19 [net-_u24-pad3_ ] [net-_m8-pad2_ ] u39
+a20 [net-_u33-pad3_ ] [net-_m5-pad2_ ] u41
+a21 net-_u2-pad2_ net-_u21-pad2_ u7
+a22 net-_u1-pad4_ net-_u10-pad2_ u10
+a23 net-_u1-pad1_ net-_u14-pad1_ u6
+a24 net-_u14-pad1_ net-_u14-pad2_ u14
+a25 net-_u1-pad2_ net-_u2-pad2_ u2
+a26 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a27 net-_u21-pad2_ net-_u28-pad2_ u28
+a28 [net-_u14-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a29 net-_u14-pad2_ net-_u20-pad2_ u20
+a30 net-_u13-pad1_ net-_u13-pad2_ u13
+a31 net-_u1-pad13_ net-_u12-pad2_ u12
+a32 net-_u12-pad2_ net-_u17-pad2_ u17
+a33 net-_u15-pad1_ net-_u15-pad2_ u15
+a34 net-_u1-pad12_ net-_u13-pad1_ u5
+a35 [net-_m2-pad1_ ] [net-_u1-pad8_ ] u45
+a36 [net-_m5-pad1_ ] [net-_u1-pad11_ ] u44
+a37 net-_u1-pad5_ net-_u11-pad1_ u4
+a38 net-_u11-pad1_ net-_u11-pad2_ u11
+a39 net-_u1-pad10_ net-_u15-pad1_ u8
+a40 net-_u1-pad9_ net-_u3-pad2_ u3
+a41 net-_u3-pad2_ net-_u22-pad2_ u9
+a42 net-_u10-pad2_ net-_u16-pad2_ u16
+a43 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u42
+a44 [net-_m4-pad1_ ] [net-_u1-pad6_ ] u43
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u40 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u36 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u39 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u41 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u45 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u44 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u43 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.kicad_sch b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.kicad_sch
new file mode 100644
index 000000000..312e69cfe
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.kicad_sch
@@ -0,0 +1,3312 @@
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+    )
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+    )
+    (path "/7ba76070-eca2-4aa5-8d94-23cbeae24583"
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+    )
+    (path "/61a877a5-01ed-44d5-bc7a-a21e5389681a"
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+    )
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+    )
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+    )
+    (path "/2f009d38-321e-498c-873d-ec5e19ce538d"
+      (reference "U31") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/5aa967e0-c528-41da-aa30-e654f70b5f8c"
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+    )
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+    )
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+    )
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+    )
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+    )
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+    )
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+    )
+    (path "/454a5e43-e994-4aa0-8152-abfa16036cdc"
+      (reference "U42") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
+    (path "/28d1fb1d-6aeb-4ce4-830a-2fd103c8f6cc"
+      (reference "U43") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
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+      (reference "U44") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
+    (path "/a513698e-ea10-4e47-8c50-ac1731d5e305"
+      (reference "U45") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
+    (path "/13b5fafb-5195-4e6a-b647-fe5722d4a74a"
+      (reference "v1") (unit 1) (value "5") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.sub b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.sub
new file mode 100644
index 000000000..b540ebaa5
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125.sub
@@ -0,0 +1,193 @@
+* Subcircuit 74HC125
+.subckt 74HC125 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m3 net-_m1-pad1_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u35 net-_u21-pad3_ net-_m3-pad2_ dac_bridge_1
+* u34 net-_u30-pad3_ net-_m1-pad2_ dac_bridge_1
+* u30 net-_u28-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and
+* u40 net-_u32-pad3_ net-_m4-pad2_ dac_bridge_1
+m4 net-_m4-pad1_ net-_m4-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m7 net-_m4-pad1_ net-_m7-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u38 net-_u23-pad3_ net-_m7-pad2_ dac_bridge_1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+* u19 net-_u16-pad2_ net-_u19-pad2_ d_inverter
+* u27 net-_u11-pad2_ net-_u27-pad2_ d_inverter
+* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
+* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_nand
+* u22 net-_u15-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand
+* u26 net-_u22-pad2_ net-_u26-pad2_ d_inverter
+* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter
+* u36 net-_u31-pad3_ net-_m2-pad2_ dac_bridge_1
+* u32 net-_u27-pad2_ net-_u19-pad2_ net-_u32-pad3_ d_and
+* u37 net-_u22-pad3_ net-_m6-pad2_ dac_bridge_1
+* u31 net-_u26-pad2_ net-_u18-pad2_ net-_u31-pad3_ d_and
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u33 net-_u29-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and
+* u39 net-_u24-pad3_ net-_m8-pad2_ dac_bridge_1
+* u41 net-_u33-pad3_ net-_m5-pad2_ dac_bridge_1
+* u7 net-_u2-pad2_ net-_u21-pad2_ d_inverter
+* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter
+* u6 net-_u1-pad1_ net-_u14-pad1_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_nand
+* u28 net-_u21-pad2_ net-_u28-pad2_ d_inverter
+* u21 net-_u14-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_nand
+* u20 net-_u14-pad2_ net-_u20-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u12 net-_u1-pad13_ net-_u12-pad2_ d_inverter
+* u17 net-_u12-pad2_ net-_u17-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u5 net-_u1-pad12_ net-_u13-pad1_ d_inverter
+m5 net-_m5-pad1_ net-_m5-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m8 net-_m5-pad1_ net-_m8-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u45 net-_m2-pad1_ net-_u1-pad8_ adc_bridge_1
+* u44 net-_m5-pad1_ net-_u1-pad11_ adc_bridge_1
+* u4 net-_u1-pad5_ net-_u11-pad1_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u3 net-_u1-pad9_ net-_u3-pad2_ d_inverter
+* u9 net-_u3-pad2_ net-_u22-pad2_ d_inverter
+* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter
+* u42 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+v1 net-_m3-pad3_ gnd 5
+* u43 net-_m4-pad1_ net-_u1-pad6_ adc_bridge_1
+a1 [net-_u21-pad3_ ] [net-_m3-pad2_ ] u35
+a2 [net-_u30-pad3_ ] [net-_m1-pad2_ ] u34
+a3 [net-_u28-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30
+a4 [net-_u32-pad3_ ] [net-_m4-pad2_ ] u40
+a5 [net-_u23-pad3_ ] [net-_m7-pad2_ ] u38
+a6 net-_u16-pad2_ net-_u19-pad2_ u19
+a7 net-_u11-pad2_ net-_u27-pad2_ u27
+a8 net-_u17-pad2_ net-_u25-pad2_ u25
+a9 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
+a10 [net-_u15-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a11 net-_u22-pad2_ net-_u26-pad2_ u26
+a12 net-_u15-pad2_ net-_u18-pad2_ u18
+a13 [net-_u31-pad3_ ] [net-_m2-pad2_ ] u36
+a14 [net-_u27-pad2_ net-_u19-pad2_ ] net-_u32-pad3_ u32
+a15 [net-_u22-pad3_ ] [net-_m6-pad2_ ] u37
+a16 [net-_u26-pad2_ net-_u18-pad2_ ] net-_u31-pad3_ u31
+a17 net-_u13-pad2_ net-_u29-pad2_ u29
+a18 [net-_u29-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33
+a19 [net-_u24-pad3_ ] [net-_m8-pad2_ ] u39
+a20 [net-_u33-pad3_ ] [net-_m5-pad2_ ] u41
+a21 net-_u2-pad2_ net-_u21-pad2_ u7
+a22 net-_u1-pad4_ net-_u10-pad2_ u10
+a23 net-_u1-pad1_ net-_u14-pad1_ u6
+a24 net-_u14-pad1_ net-_u14-pad2_ u14
+a25 net-_u1-pad2_ net-_u2-pad2_ u2
+a26 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a27 net-_u21-pad2_ net-_u28-pad2_ u28
+a28 [net-_u14-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a29 net-_u14-pad2_ net-_u20-pad2_ u20
+a30 net-_u13-pad1_ net-_u13-pad2_ u13
+a31 net-_u1-pad13_ net-_u12-pad2_ u12
+a32 net-_u12-pad2_ net-_u17-pad2_ u17
+a33 net-_u15-pad1_ net-_u15-pad2_ u15
+a34 net-_u1-pad12_ net-_u13-pad1_ u5
+a35 [net-_m2-pad1_ ] [net-_u1-pad8_ ] u45
+a36 [net-_m5-pad1_ ] [net-_u1-pad11_ ] u44
+a37 net-_u1-pad5_ net-_u11-pad1_ u4
+a38 net-_u11-pad1_ net-_u11-pad2_ u11
+a39 net-_u1-pad10_ net-_u15-pad1_ u8
+a40 net-_u1-pad9_ net-_u3-pad2_ u3
+a41 net-_u3-pad2_ net-_u22-pad2_ u9
+a42 net-_u10-pad2_ net-_u16-pad2_ u16
+a43 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u42
+a44 [net-_m4-pad1_ ] [net-_u1-pad6_ ] u43
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u40 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u36 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u39 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u41 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u45 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u44 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u43 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC125
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_Previous_Values.xml
new file mode 100644
index 000000000..26c7067cb
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source><v1 name="Source type">5</v1></source><model><u35 name="type">dac_bridge<field1 name="Enter value for out_low (default=0.0)" /><field2 name="Enter value for out_high (default=5.0)" /><field3 name="Enter value for out_undef (default=0.5)" /><field4 name="Enter value for input load (default=1.0e-12)" /><field5 name="Enter the Rise Time (default=1.0e-9)" /><field6 name="Enter the Fall Time (default=1.0e-9)" /></u35><u34 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u34><u30 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u30><u40 name="type">dac_bridge<field16 name="Enter value for out_low (default=0.0)" /><field17 name="Enter value for out_high (default=5.0)" /><field18 name="Enter value for out_undef (default=0.5)" /><field19 name="Enter value for input load (default=1.0e-12)" /><field20 name="Enter the Rise Time (default=1.0e-9)" /><field21 name="Enter the Fall Time (default=1.0e-9)" /></u40><u38 name="type">dac_bridge<field22 name="Enter value for out_low (default=0.0)" /><field23 name="Enter value for out_high (default=5.0)" /><field24 name="Enter value for out_undef (default=0.5)" /><field25 name="Enter value for input load (default=1.0e-12)" /><field26 name="Enter the Rise Time (default=1.0e-9)" /><field27 name="Enter the Fall Time (default=1.0e-9)" /></u38><u19 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u19><u27 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u27><u25 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u25><u24 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u26><u18 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u18><u36 name="type">dac_bridge<field49 name="Enter value for out_low (default=0.0)" /><field50 name="Enter value for out_high (default=5.0)" /><field51 name="Enter value for out_undef (default=0.5)" /><field52 name="Enter value for input load (default=1.0e-12)" /><field53 name="Enter the Rise Time (default=1.0e-9)" /><field54 name="Enter the Fall Time (default=1.0e-9)" /></u36><u32 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u32><u37 name="type">dac_bridge<field58 name="Enter value for out_low (default=0.0)" /><field59 name="Enter value for out_high (default=5.0)" /><field60 name="Enter value for out_undef (default=0.5)" /><field61 name="Enter value for input load (default=1.0e-12)" /><field62 name="Enter the Rise Time (default=1.0e-9)" /><field63 name="Enter the Fall Time (default=1.0e-9)" /></u37><u31 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u31><u29 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u29><u33 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u33><u39 name="type">dac_bridge<field73 name="Enter value for out_low (default=0.0)" /><field74 name="Enter value for out_high (default=5.0)" /><field75 name="Enter value for out_undef (default=0.5)" /><field76 name="Enter value for input load (default=1.0e-12)" /><field77 name="Enter the Rise Time (default=1.0e-9)" /><field78 name="Enter the Fall Time (default=1.0e-9)" /></u39><u41 name="type">dac_bridge<field79 name="Enter value for out_low (default=0.0)" /><field80 name="Enter value for out_high (default=5.0)" /><field81 name="Enter value for out_undef (default=0.5)" /><field82 name="Enter value for input load (default=1.0e-12)" /><field83 name="Enter the Rise Time (default=1.0e-9)" /><field84 name="Enter the Fall Time (default=1.0e-9)" /></u41><u7 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u10><u6 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u6><u14 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u14><u2 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u2><u23 name="type">d_nand<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u23><u28 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u28><u21 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u20><u13 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u12><u17 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u17><u15 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u15><u5 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u5><u45 name="type">adc_bridge<field127 name="Enter value for in_low (default=1.0)" /><field128 name="Enter value for in_high (default=2.0)" /><field129 name="Enter Rise Delay (default=1.0e-9)" /><field130 name="Enter Fall Delay (default=1.0e-9)" /></u45><u44 name="type">adc_bridge<field131 name="Enter value for in_low (default=1.0)" /><field132 name="Enter value for in_high (default=2.0)" /><field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /></u44><u4 name="type">d_inverter<field135 name="Enter Rise Delay (default=1.0e-9)" /><field136 name="Enter Fall Delay (default=1.0e-9)" /><field137 name="Enter Input Load (default=1.0e-12)" /></u4><u11 name="type">d_inverter<field138 name="Enter Rise Delay (default=1.0e-9)" /><field139 name="Enter Fall Delay (default=1.0e-9)" /><field140 name="Enter Input Load (default=1.0e-12)" /></u11><u8 name="type">d_inverter<field141 name="Enter Rise Delay (default=1.0e-9)" /><field142 name="Enter Fall Delay (default=1.0e-9)" /><field143 name="Enter Input Load (default=1.0e-12)" /></u8><u3 name="type">d_inverter<field144 name="Enter Rise Delay (default=1.0e-9)" /><field145 name="Enter Fall Delay (default=1.0e-9)" /><field146 name="Enter Input Load (default=1.0e-12)" /></u3><u9 name="type">d_inverter<field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /><field149 name="Enter Input Load (default=1.0e-12)" /></u9><u16 name="type">d_inverter<field150 name="Enter Rise Delay (default=1.0e-9)" /><field151 name="Enter Fall Delay (default=1.0e-9)" /><field152 name="Enter Input Load (default=1.0e-12)" /></u16><u42 name="type">adc_bridge<field153 name="Enter value for in_low (default=1.0)" /><field154 name="Enter value for in_high (default=2.0)" /><field155 name="Enter Rise Delay (default=1.0e-9)" /><field156 name="Enter Fall Delay (default=1.0e-9)" /></u42><u43 name="type">adc_bridge<field157 name="Enter value for in_low (default=1.0)" /><field158 name="Enter value for in_high (default=2.0)" /><field159 name="Enter Rise Delay (default=1.0e-9)" /><field160 name="Enter Fall Delay (default=1.0e-9)" /></u43></model><devicemodel><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.cir b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.cir
new file mode 100644
index 000000000..23d3066a5
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+V_OE_N2 Net-_V_OE_N2-Pad1_ GND DC
+V_A1 Net-_V_A1-Pad1_ GND DC
+V_OE_N1 Net-_V_OE_N1-Pad1_ GND DC
+U2 Net-_V_OE_N1-Pad1_ Net-_V_A1-Pad1_ Net-_V_OE_N2-Pad1_ Net-_V_A2-Pad1_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ adc_bridge_4
+V_A2 Net-_V_A2-Pad1_ GND DC
+U6 Net-_V_OE_N4-Pad1_ Net-_V_A4-Pad1_ Net-_V_OE_N3-Pad1_ Net-_V_A3-Pad1_ Net-_U6-Pad5_ Net-_U6-Pad6_ Net-_U6-Pad7_ Net-_U6-Pad8_ adc_bridge_4
+X1 Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U4-Pad2_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U4-Pad1_ GND Net-_U4-Pad4_ Net-_U6-Pad8_ Net-_U6-Pad7_ Net-_U4-Pad3_ Net-_U6-Pad6_ Net-_U6-Pad5_ Net-_X1-Pad14_ 74HC125
+v1 Net-_X1-Pad14_ GND DC
+V_OE_N3 Net-_V_OE_N3-Pad1_ GND DC
+V_A3 Net-_V_A3-Pad1_ GND DC
+V_A4 Net-_V_A4-Pad1_ GND DC
+V_OE_N4 Net-_V_OE_N4-Pad1_ GND DC
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ Net-_U4-Pad4_ V_Y2 V_Y1 V_Y4 V_Y3 dac_bridge_4
+U3 V_Y2 plot_v1
+U1 V_Y1 plot_v1
+U7 V_Y4 plot_v1
+U5 V_Y3 plot_v1
+.end
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.cir.out b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.cir.out
new file mode 100644
index 000000000..69a6c37d0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.cir.out
@@ -0,0 +1,42 @@
+.title kicad schematic
+
+.include 74HC125.sub
+v_oe_n2 net-_v_oe_n2-pad1_ gnd  dc 0
+v_a1 net-_v_a1-pad1_ gnd  dc 0
+v_oe_n1 net-_v_oe_n1-pad1_ gnd  dc 0
+* u2 net-_v_oe_n1-pad1_ net-_v_a1-pad1_ net-_v_oe_n2-pad1_ net-_v_a2-pad1_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4
+v_a2 net-_v_a2-pad1_ gnd  dc 5
+* u6 net-_v_oe_n4-pad1_ net-_v_a4-pad1_ net-_v_oe_n3-pad1_ net-_v_a3-pad1_ net-_u6-pad5_ net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ adc_bridge_4
+x1 net-_u2-pad5_ net-_u2-pad6_ net-_u4-pad2_ net-_u2-pad7_ net-_u2-pad8_ net-_u4-pad1_ gnd net-_u4-pad4_ net-_u6-pad8_ net-_u6-pad7_ net-_u4-pad3_ net-_u6-pad6_ net-_u6-pad5_ net-_x1-pad14_ 74HC125
+v1 net-_x1-pad14_ gnd  dc 5
+v_oe_n3 net-_v_oe_n3-pad1_ gnd  dc 0
+v_a3 net-_v_a3-pad1_ gnd  dc 5
+v_a4 net-_v_a4-pad1_ gnd  dc 5
+v_oe_n4 net-_v_oe_n4-pad1_ gnd  dc 0
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ v_y2 v_y1 v_y4 v_y3 dac_bridge_4
+* u3 v_y2 plot_v1
+* u1 v_y1 plot_v1
+* u7 v_y4 plot_v1
+* u5 v_y3 plot_v1
+a1 [net-_v_oe_n1-pad1_ net-_v_a1-pad1_ net-_v_oe_n2-pad1_ net-_v_a2-pad1_ ] [net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2
+a2 [net-_v_oe_n4-pad1_ net-_v_a4-pad1_ net-_v_oe_n3-pad1_ net-_v_a3-pad1_ ] [net-_u6-pad5_ net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ ] u6
+a3 [net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ ] [v_y2 v_y1 v_y4 v_y3 ] u4
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 1e-00 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_y2)
+plot v(v_y1)
+plot v(v_y4)
+plot v(v_y3)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.kicad_sch b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.kicad_sch
new file mode 100644
index 000000000..9da3d0bcf
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.kicad_sch
@@ -0,0 +1,1137 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 4ff45f67-e7e4-4ec8-9eb8-8990e952005b)
+
+  (paper "A3")
+
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+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid d91ce1ac-2626-4ba6-8608-e2df10fa4f3a)
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+  (symbol_instances
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+      (reference "v1") (unit 1) (value "DC") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.proj b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.proj
new file mode 100644
index 000000000..a7743d4bc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.proj
@@ -0,0 +1 @@
+schematicFile 74HC125_TEST_CIRCUIT.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.raw b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.raw
new file mode 100644
index 000000000..3692b3bbf
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT.raw
@@ -0,0 +1,2948 @@
+Title: kicad schematic
+Date: Sun Dec 14 19:36:12  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 49
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(net-_v_oe_n2-pad1_)	voltage
+	2	v(net-_v_a1-pad1_)	voltage
+	3	v(net-_v_oe_n1-pad1_)	voltage
+	4	v(net-_v_a2-pad1_)	voltage
+	5	v(x1.net-_m1-pad1_)	voltage
+	6	v(x1.net-_m3-pad2_)	voltage
+	7	v(x1.net-_m3-pad3_)	voltage
+	8	v(x1.net-_m1-pad2_)	voltage
+	9	v(x1.net-_m4-pad1_)	voltage
+	10	v(x1.net-_m4-pad2_)	voltage
+	11	v(x1.net-_m7-pad2_)	voltage
+	12	v(x1.net-_m2-pad1_)	voltage
+	13	v(x1.net-_m6-pad2_)	voltage
+	14	v(x1.net-_m5-pad1_)	voltage
+	15	v(x1.net-_m5-pad2_)	voltage
+	16	v(x1.net-_m8-pad2_)	voltage
+	17	v(x1.net-_m2-pad2_)	voltage
+	18	v(net-_x1-pad14_)	voltage
+	19	v(net-_v_oe_n3-pad1_)	voltage
+	20	v(net-_v_a3-pad1_)	voltage
+	21	v(net-_v_a4-pad1_)	voltage
+	22	v(net-_v_oe_n4-pad1_)	voltage
+	23	v(v_y2)	voltage
+	24	v(v_y1)	voltage
+	25	v(v_y4)	voltage
+	26	v(v_y3)	voltage
+	27	i(v_oe_n4)	current
+	28	i(v_a4)	current
+	29	i(v_a3)	current
+	30	i(v_oe_n3)	current
+	31	i(v1)	current
+	32	i(v.x1.v1)	current
+	33	i(v_a2)	current
+	34	i(v_oe_n1)	current
+	35	i(v_a1)	current
+	36	i(v_oe_n2)	current
+	37	i(a3)	current
+	38	i(a3)	current
+	39	i(a3)	current
+	40	i(a3)	current
+	41	i(a.x1.a20)	current
+	42	i(a.x1.a19)	current
+	43	i(a.x1.a15)	current
+	44	i(a.x1.a13)	current
+	45	i(a.x1.a5)	current
+	46	i(a.x1.a4)	current
+	47	i(a.x1.a2)	current
+	48	i(a.x1.a1)	current
+Values:
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diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT_Previous_Values.xml
new file mode 100644
index 000000000..eb286bf60
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/74HC125_TEST_CIRCUIT_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v_oe_n2 name="Source type">dc<field1 name="Value">0</field1></v_oe_n2><v_a1 name="Source type">dc<field1 name="Value">0</field1></v_a1><v_oe_n1 name="Source type">dc<field1 name="Value">0</field1></v_oe_n1><v_a2 name="Source type">dc<field1 name="Value">5</field1></v_a2><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v_oe_n3 name="Source type">dc<field1 name="Value">0</field1></v_oe_n3><v_a3 name="Source type">dc<field1 name="Value">5</field1></v_a3><v_a4 name="Source type">dc<field1 name="Value">5</field1></v_a4><v_oe_n4 name="Source type">dc<field1 name="Value">0</field1></v_oe_n4></source><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u6 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u6><u4 name="type">dac_bridge<field9 name="Enter value for out_low (default=0.0)" /><field10 name="Enter value for out_high (default=5.0)" /><field11 name="Enter value for out_undef (default=0.5)" /><field12 name="Enter value for input load (default=1.0e-12)" /><field13 name="Enter the Rise Time (default=1.0e-9)" /><field14 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC125</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/NMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/PMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/_autosave-74HC125.sch b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/_autosave-74HC125.sch
new file mode 100644
index 000000000..9023ab11f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/_autosave-74HC125.sch
@@ -0,0 +1,613 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 4625 1475
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+Connection ~ 4700 3000
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+Wire Wire Line
+	2450 1500 3825 1500
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+U 1 1 00000000
+P 2800 2000
+F 0 "U?" H 2800 2250 60  0000 C CNN
+F 1 "d_inverter" H 2800 2100 60  0000 C CNN
+F 2 "" H 2850 1950 60  0000 C CNN
+F 3 "" H 2850 1950 60  0000 C CNN
+	1    2800 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2825 5175
+F 0 "U?" H 2825 5425 60  0000 C CNN
+F 1 "d_inverter" H 2825 5275 60  0000 C CNN
+F 2 "" H 2875 5125 60  0000 C CNN
+F 3 "" H 2875 5125 60  0000 C CNN
+	1    2825 5175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2875 3525
+F 0 "U?" H 2875 3775 60  0000 C CNN
+F 1 "d_inverter" H 2875 3625 60  0000 C CNN
+F 2 "" H 2925 3475 60  0000 C CNN
+F 3 "" H 2925 3475 60  0000 C CNN
+	1    2875 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2875 6925
+F 0 "U?" H 2875 7175 60  0000 C CNN
+F 1 "d_inverter" H 2875 7025 60  0000 C CNN
+F 2 "" H 2925 6875 60  0000 C CNN
+F 3 "" H 2925 6875 60  0000 C CNN
+	1    2875 6925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4125 1500
+F 0 "U?" H 4125 1750 60  0000 C CNN
+F 1 "d_inverter" H 4125 1600 60  0000 C CNN
+F 2 "" H 4175 1450 60  0000 C CNN
+F 3 "" H 4175 1450 60  0000 C CNN
+	1    4125 1500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4125 2000
+F 0 "U?" H 4125 2250 60  0000 C CNN
+F 1 "d_inverter" H 4125 2100 60  0000 C CNN
+F 2 "" H 4175 1950 60  0000 C CNN
+F 3 "" H 4175 1950 60  0000 C CNN
+	1    4125 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4150 4675
+F 0 "U?" H 4150 4925 60  0000 C CNN
+F 1 "d_inverter" H 4150 4775 60  0000 C CNN
+F 2 "" H 4200 4625 60  0000 C CNN
+F 3 "" H 4200 4625 60  0000 C CNN
+	1    4150 4675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4150 5175
+F 0 "U?" H 4150 5425 60  0000 C CNN
+F 1 "d_inverter" H 4150 5275 60  0000 C CNN
+F 2 "" H 4200 5125 60  0000 C CNN
+F 3 "" H 4200 5125 60  0000 C CNN
+	1    4150 5175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 3025
+F 0 "U?" H 4200 3275 60  0000 C CNN
+F 1 "d_inverter" H 4200 3125 60  0000 C CNN
+F 2 "" H 4250 2975 60  0000 C CNN
+F 3 "" H 4250 2975 60  0000 C CNN
+	1    4200 3025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 3525
+F 0 "U?" H 4200 3775 60  0000 C CNN
+F 1 "d_inverter" H 4200 3625 60  0000 C CNN
+F 2 "" H 4250 3475 60  0000 C CNN
+F 3 "" H 4250 3475 60  0000 C CNN
+	1    4200 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 6425
+F 0 "U?" H 4200 6675 60  0000 C CNN
+F 1 "d_inverter" H 4200 6525 60  0000 C CNN
+F 2 "" H 4250 6375 60  0000 C CNN
+F 3 "" H 4250 6375 60  0000 C CNN
+	1    4200 6425
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 6925
+F 0 "U?" H 4200 7175 60  0000 C CNN
+F 1 "d_inverter" H 4200 7025 60  0000 C CNN
+F 2 "" H 4250 6875 60  0000 C CNN
+F 3 "" H 4250 6875 60  0000 C CNN
+	1    4200 6925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5225 2250
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+F 2 "" H 5275 2200 60  0000 C CNN
+F 3 "" H 5275 2200 60  0000 C CNN
+	1    5225 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5250 5425
+F 0 "U?" H 5250 5675 60  0000 C CNN
+F 1 "d_inverter" H 5250 5525 60  0000 C CNN
+F 2 "" H 5300 5375 60  0000 C CNN
+F 3 "" H 5300 5375 60  0000 C CNN
+	1    5250 5425
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5300 3775
+F 0 "U?" H 5300 4025 60  0000 C CNN
+F 1 "d_inverter" H 5300 3875 60  0000 C CNN
+F 2 "" H 5350 3725 60  0000 C CNN
+F 3 "" H 5350 3725 60  0000 C CNN
+	1    5300 3775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5300 7175
+F 0 "U?" H 5300 7425 60  0000 C CNN
+F 1 "d_inverter" H 5300 7275 60  0000 C CNN
+F 2 "" H 5350 7125 60  0000 C CNN
+F 3 "" H 5350 7125 60  0000 C CNN
+	1    5300 7175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7100 2000
+F 0 "M?" H 7450 1850 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7450 1750 50  0000 L CNN
+F 2 "" H 7400 1700 29  0000 C CNN
+F 3 "" H 7200 1800 60  0000 C CNN
+	1    7100 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7125 5175
+F 0 "M?" H 7475 5025 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7475 4925 50  0000 L CNN
+F 2 "" H 7425 4875 29  0000 C CNN
+F 3 "" H 7225 4975 60  0000 C CNN
+	1    7125 5175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7175 1525
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+F 2 "" H 7425 1625 29  0000 C CNN
+F 3 "" H 7225 1525 60  0000 C CNN
+	1    7175 1525
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7175 3525
+F 0 "M?" H 7525 3375 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7525 3275 50  0000 L CNN
+F 2 "" H 7475 3225 29  0000 C CNN
+F 3 "" H 7275 3325 60  0000 C CNN
+	1    7175 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7175 6925
+F 0 "M?" H 7525 6775 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7525 6675 50  0000 L CNN
+F 2 "" H 7475 6625 29  0000 C CNN
+F 3 "" H 7275 6725 60  0000 C CNN
+	1    7175 6925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7200 4700
+F 0 "M?" H 7475 4650 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7475 4750 50  0000 L CNN
+F 2 "" H 7450 4800 29  0000 C CNN
+F 3 "" H 7250 4700 60  0000 C CNN
+	1    7200 4700
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7250 3050
+F 0 "M?" H 7525 3000 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7525 3100 50  0000 L CNN
+F 2 "" H 7500 3150 29  0000 C CNN
+F 3 "" H 7300 3050 60  0000 C CNN
+	1    7250 3050
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7250 6450
+F 0 "M?" H 7525 6400 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7525 6500 50  0000 L CNN
+F 2 "" H 7500 6550 29  0000 C CNN
+F 3 "" H 7300 6450 60  0000 C CNN
+	1    7250 6450
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6250 2250
+F 0 "U?" H 6250 2600 60  0000 C CNN
+F 1 "d_nand" H 6250 2450 60  0000 C CNN
+F 2 "" H 6250 2250 60  0000 C CNN
+F 3 "" H 6250 2250 60  0000 C CNN
+	1    6250 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6275 1575
+F 0 "U?" H 6275 1950 60  0000 C CNN
+F 1 "d_nand" H 6275 1800 60  0000 C CNN
+F 2 "" H 6275 1575 60  0000 C CNN
+F 3 "" H 6275 1575 60  0000 C CNN
+	1    6275 1575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6275 5425
+F 0 "U?" H 6275 5775 60  0000 C CNN
+F 1 "d_nand" H 6275 5625 60  0000 C CNN
+F 2 "" H 6275 5425 60  0000 C CNN
+F 3 "" H 6275 5425 60  0000 C CNN
+	1    6275 5425
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6300 4750
+F 0 "U?" H 6300 5125 60  0000 C CNN
+F 1 "d_nand" H 6300 4975 60  0000 C CNN
+F 2 "" H 6300 4750 60  0000 C CNN
+F 3 "" H 6300 4750 60  0000 C CNN
+	1    6300 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6325 3775
+F 0 "U?" H 6325 4125 60  0000 C CNN
+F 1 "d_nand" H 6325 3975 60  0000 C CNN
+F 2 "" H 6325 3775 60  0000 C CNN
+F 3 "" H 6325 3775 60  0000 C CNN
+	1    6325 3775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6325 7175
+F 0 "U?" H 6325 7525 60  0000 C CNN
+F 1 "d_nand" H 6325 7375 60  0000 C CNN
+F 2 "" H 6325 7175 60  0000 C CNN
+F 3 "" H 6325 7175 60  0000 C CNN
+	1    6325 7175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6350 3100
+F 0 "U?" H 6350 3475 60  0000 C CNN
+F 1 "d_nand" H 6350 3325 60  0000 C CNN
+F 2 "" H 6350 3100 60  0000 C CNN
+F 3 "" H 6350 3100 60  0000 C CNN
+	1    6350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6350 6500
+F 0 "U?" H 6350 6875 60  0000 C CNN
+F 1 "d_nand" H 6350 6725 60  0000 C CNN
+F 2 "" H 6350 6500 60  0000 C CNN
+F 3 "" H 6350 6500 60  0000 C CNN
+	1    6350 6500
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/analysis b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/analysis
new file mode 100644
index 000000000..14a32166e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/74HC125_Test_Circuit/74HC125_TEST_CIRCUIT/analysis
@@ -0,0 +1 @@
+.tran 1e-00 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/NMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC125/74HC125/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/PMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC125/74HC125/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/_autosave-74HC125.sch b/library/SubcircuitLibrary/IC74HC125/74HC125/_autosave-74HC125.sch
new file mode 100644
index 000000000..9023ab11f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/_autosave-74HC125.sch
@@ -0,0 +1,613 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 4625 1475
+Connection ~ 4650 4650
+Connection ~ 4700 3000
+Connection ~ 4700 6400
+Connection ~ 5725 1825
+Connection ~ 5750 5000
+Connection ~ 5800 3350
+Connection ~ 5800 6750
+Connection ~ 7400 2575
+Connection ~ 7425 1250
+Connection ~ 7425 5750
+Connection ~ 7450 4425
+Connection ~ 7475 4100
+Connection ~ 7475 7500
+Connection ~ 7500 2775
+Connection ~ 7500 6175
+Connection ~ 8250 2775
+Connection ~ 8250 4425
+Connection ~ 8900 4100
+Connection ~ 8900 5750
+Wire Wire Line
+	2450 1500 3825 1500
+Wire Wire Line
+	2475 4675 3850 4675
+Wire Wire Line
+	2525 3025 3900 3025
+Wire Wire Line
+	2525 6425 3900 6425
+Wire Wire Line
+	3100 2000 3825 2000
+Wire Wire Line
+	3125 5175 3850 5175
+Wire Wire Line
+	3175 3525 3900 3525
+Wire Wire Line
+	3175 6925 3900 6925
+Wire Wire Line
+	4425 1475 4425 1500
+Wire Wire Line
+	4425 1825 5725 1825
+Wire Wire Line
+	4425 2000 4425 1825
+Wire Wire Line
+	4450 4650 4450 4675
+Wire Wire Line
+	4450 5000 5750 5000
+Wire Wire Line
+	4450 5175 4450 5000
+Wire Wire Line
+	4500 3000 4500 3025
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4500 6925 4500 6750
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4700 3000 4500 3000
+Wire Wire Line
+	4700 3775 4700 3000
+Wire Wire Line
+	4700 6400 4500 6400
+Wire Wire Line
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+Wire Wire Line
+	4925 2250 4625 2250
+Wire Wire Line
+	4950 5425 4650 5425
+Wire Wire Line
+	5000 3775 4700 3775
+Wire Wire Line
+	5000 7175 4700 7175
+Wire Wire Line
+	5525 2250 5800 2250
+Wire Wire Line
+	5550 5425 5825 5425
+Wire Wire Line
+	5600 3775 5875 3775
+Wire Wire Line
+	5600 7175 5875 7175
+Wire Wire Line
+	5725 1575 5825 1575
+Wire Wire Line
+	5725 1825 5725 1575
+Wire Wire Line
+	5725 2150 5725 1825
+Wire Wire Line
+	5750 4750 5850 4750
+Wire Wire Line
+	5750 5000 5750 4750
+Wire Wire Line
+	5750 5325 5750 5000
+Wire Wire Line
+	5800 2150 5725 2150
+Wire Wire Line
+	5800 3100 5900 3100
+Wire Wire Line
+	5800 3350 5800 3100
+Wire Wire Line
+	5800 3675 5800 3350
+Wire Wire Line
+	5800 6500 5900 6500
+Wire Wire Line
+	5800 6750 5800 6500
+Wire Wire Line
+	5800 7075 5800 6750
+Wire Wire Line
+	5825 1475 4625 1475
+Wire Wire Line
+	5825 5325 5750 5325
+Wire Wire Line
+	5850 4650 4650 4650
+Wire Wire Line
+	5875 3675 5800 3675
+Wire Wire Line
+	5875 7075 5800 7075
+Wire Wire Line
+	5900 3000 4700 3000
+Wire Wire Line
+	5900 6400 4700 6400
+Wire Wire Line
+	6700 2200 7000 2200
+Wire Wire Line
+	6725 1525 7025 1525
+Wire Wire Line
+	6725 5375 7025 5375
+Wire Wire Line
+	6750 4700 7050 4700
+Wire Wire Line
+	6775 3725 7075 3725
+Wire Wire Line
+	6775 7125 7075 7125
+Wire Wire Line
+	6800 3050 7100 3050
+Wire Wire Line
+	6800 6450 7100 6450
+Wire Wire Line
+	7300 1725 7325 1725
+Wire Wire Line
+	7300 2000 7300 1725
+Wire Wire Line
+	7300 2400 7300 2575
+Wire Wire Line
+	7300 2575 7400 2575
+Wire Wire Line
+	7325 1250 7325 1325
+Wire Wire Line
+	7325 4900 7350 4900
+Wire Wire Line
+	7325 5175 7325 4900
+Wire Wire Line
+	7325 5575 7325 5750
+Wire Wire Line
+	7325 5750 7425 5750
+Wire Wire Line
+	7350 4425 7350 4500
+Wire Wire Line
+	7375 3250 7400 3250
+Wire Wire Line
+	7375 3525 7375 3250
+Wire Wire Line
+	7375 3925 7375 4100
+Wire Wire Line
+	7375 4100 7475 4100
+Wire Wire Line
+	7375 6650 7400 6650
+Wire Wire Line
+	7375 6925 7375 6650
+Wire Wire Line
+	7375 7325 7375 7500
+Wire Wire Line
+	7375 7500 7475 7500
+Wire Wire Line
+	7400 2575 7400 2350
+Wire Wire Line
+	7400 2575 8900 2575
+Wire Wire Line
+	7400 2775 7400 2850
+Wire Wire Line
+	7400 6175 7400 6250
+Wire Wire Line
+	7425 1250 7325 1250
+Wire Wire Line
+	7425 1250 8250 1250
+Wire Wire Line
+	7425 1375 7425 1250
+Wire Wire Line
+	7425 5750 7425 5525
+Wire Wire Line
+	7425 5750 8900 5750
+Wire Wire Line
+	7450 4425 7350 4425
+Wire Wire Line
+	7450 4425 8250 4425
+Wire Wire Line
+	7450 4550 7450 4425
+Wire Wire Line
+	7475 4100 7475 3875
+Wire Wire Line
+	7475 4100 8900 4100
+Wire Wire Line
+	7475 7500 7475 7275
+Wire Wire Line
+	7500 2775 7400 2775
+Wire Wire Line
+	7500 2775 8250 2775
+Wire Wire Line
+	7500 2900 7500 2775
+Wire Wire Line
+	7500 6175 7400 6175
+Wire Wire Line
+	7500 6300 7500 6175
+Wire Wire Line
+	8250 1250 8250 2775
+Wire Wire Line
+	8250 2775 8250 4425
+Wire Wire Line
+	8250 4425 8250 6175
+Wire Wire Line
+	8250 6175 7500 6175
+Wire Wire Line
+	8900 2575 8900 4100
+Wire Wire Line
+	8900 4100 8900 5750
+Wire Wire Line
+	8900 5750 8900 7500
+Wire Wire Line
+	8900 7500 7475 7500
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2800 2000
+F 0 "U?" H 2800 2250 60  0000 C CNN
+F 1 "d_inverter" H 2800 2100 60  0000 C CNN
+F 2 "" H 2850 1950 60  0000 C CNN
+F 3 "" H 2850 1950 60  0000 C CNN
+	1    2800 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2825 5175
+F 0 "U?" H 2825 5425 60  0000 C CNN
+F 1 "d_inverter" H 2825 5275 60  0000 C CNN
+F 2 "" H 2875 5125 60  0000 C CNN
+F 3 "" H 2875 5125 60  0000 C CNN
+	1    2825 5175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2875 3525
+F 0 "U?" H 2875 3775 60  0000 C CNN
+F 1 "d_inverter" H 2875 3625 60  0000 C CNN
+F 2 "" H 2925 3475 60  0000 C CNN
+F 3 "" H 2925 3475 60  0000 C CNN
+	1    2875 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 2875 6925
+F 0 "U?" H 2875 7175 60  0000 C CNN
+F 1 "d_inverter" H 2875 7025 60  0000 C CNN
+F 2 "" H 2925 6875 60  0000 C CNN
+F 3 "" H 2925 6875 60  0000 C CNN
+	1    2875 6925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4125 1500
+F 0 "U?" H 4125 1750 60  0000 C CNN
+F 1 "d_inverter" H 4125 1600 60  0000 C CNN
+F 2 "" H 4175 1450 60  0000 C CNN
+F 3 "" H 4175 1450 60  0000 C CNN
+	1    4125 1500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4125 2000
+F 0 "U?" H 4125 2250 60  0000 C CNN
+F 1 "d_inverter" H 4125 2100 60  0000 C CNN
+F 2 "" H 4175 1950 60  0000 C CNN
+F 3 "" H 4175 1950 60  0000 C CNN
+	1    4125 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4150 4675
+F 0 "U?" H 4150 4925 60  0000 C CNN
+F 1 "d_inverter" H 4150 4775 60  0000 C CNN
+F 2 "" H 4200 4625 60  0000 C CNN
+F 3 "" H 4200 4625 60  0000 C CNN
+	1    4150 4675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4150 5175
+F 0 "U?" H 4150 5425 60  0000 C CNN
+F 1 "d_inverter" H 4150 5275 60  0000 C CNN
+F 2 "" H 4200 5125 60  0000 C CNN
+F 3 "" H 4200 5125 60  0000 C CNN
+	1    4150 5175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 3025
+F 0 "U?" H 4200 3275 60  0000 C CNN
+F 1 "d_inverter" H 4200 3125 60  0000 C CNN
+F 2 "" H 4250 2975 60  0000 C CNN
+F 3 "" H 4250 2975 60  0000 C CNN
+	1    4200 3025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 3525
+F 0 "U?" H 4200 3775 60  0000 C CNN
+F 1 "d_inverter" H 4200 3625 60  0000 C CNN
+F 2 "" H 4250 3475 60  0000 C CNN
+F 3 "" H 4250 3475 60  0000 C CNN
+	1    4200 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 6425
+F 0 "U?" H 4200 6675 60  0000 C CNN
+F 1 "d_inverter" H 4200 6525 60  0000 C CNN
+F 2 "" H 4250 6375 60  0000 C CNN
+F 3 "" H 4250 6375 60  0000 C CNN
+	1    4200 6425
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 4200 6925
+F 0 "U?" H 4200 7175 60  0000 C CNN
+F 1 "d_inverter" H 4200 7025 60  0000 C CNN
+F 2 "" H 4250 6875 60  0000 C CNN
+F 3 "" H 4250 6875 60  0000 C CNN
+	1    4200 6925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5225 2250
+F 0 "U?" H 5225 2500 60  0000 C CNN
+F 1 "d_inverter" H 5225 2350 60  0000 C CNN
+F 2 "" H 5275 2200 60  0000 C CNN
+F 3 "" H 5275 2200 60  0000 C CNN
+	1    5225 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5250 5425
+F 0 "U?" H 5250 5675 60  0000 C CNN
+F 1 "d_inverter" H 5250 5525 60  0000 C CNN
+F 2 "" H 5300 5375 60  0000 C CNN
+F 3 "" H 5300 5375 60  0000 C CNN
+	1    5250 5425
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5300 3775
+F 0 "U?" H 5300 4025 60  0000 C CNN
+F 1 "d_inverter" H 5300 3875 60  0000 C CNN
+F 2 "" H 5350 3725 60  0000 C CNN
+F 3 "" H 5350 3725 60  0000 C CNN
+	1    5300 3775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 5300 7175
+F 0 "U?" H 5300 7425 60  0000 C CNN
+F 1 "d_inverter" H 5300 7275 60  0000 C CNN
+F 2 "" H 5350 7125 60  0000 C CNN
+F 3 "" H 5350 7125 60  0000 C CNN
+	1    5300 7175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7100 2000
+F 0 "M?" H 7450 1850 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7450 1750 50  0000 L CNN
+F 2 "" H 7400 1700 29  0000 C CNN
+F 3 "" H 7200 1800 60  0000 C CNN
+	1    7100 2000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7125 5175
+F 0 "M?" H 7475 5025 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7475 4925 50  0000 L CNN
+F 2 "" H 7425 4875 29  0000 C CNN
+F 3 "" H 7225 4975 60  0000 C CNN
+	1    7125 5175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7175 1525
+F 0 "M?" H 7450 1475 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7450 1575 50  0000 L CNN
+F 2 "" H 7425 1625 29  0000 C CNN
+F 3 "" H 7225 1525 60  0000 C CNN
+	1    7175 1525
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7175 3525
+F 0 "M?" H 7525 3375 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7525 3275 50  0000 L CNN
+F 2 "" H 7475 3225 29  0000 C CNN
+F 3 "" H 7275 3325 60  0000 C CNN
+	1    7175 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_N M?
+U 1 1 00000000
+P 7175 6925
+F 0 "M?" H 7525 6775 50  0000 L CNN
+F 1 "eSim_MOS_N" H 7525 6675 50  0000 L CNN
+F 2 "" H 7475 6625 29  0000 C CNN
+F 3 "" H 7275 6725 60  0000 C CNN
+	1    7175 6925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7200 4700
+F 0 "M?" H 7475 4650 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7475 4750 50  0000 L CNN
+F 2 "" H 7450 4800 29  0000 C CNN
+F 3 "" H 7250 4700 60  0000 C CNN
+	1    7200 4700
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7250 3050
+F 0 "M?" H 7525 3000 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7525 3100 50  0000 L CNN
+F 2 "" H 7500 3150 29  0000 C CNN
+F 3 "" H 7300 3050 60  0000 C CNN
+	1    7250 3050
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_MOS_P M?
+U 1 1 00000000
+P 7250 6450
+F 0 "M?" H 7525 6400 50  0000 L CNN
+F 1 "eSim_MOS_P" H 7525 6500 50  0000 L CNN
+F 2 "" H 7500 6550 29  0000 C CNN
+F 3 "" H 7300 6450 60  0000 C CNN
+	1    7250 6450
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6250 2250
+F 0 "U?" H 6250 2600 60  0000 C CNN
+F 1 "d_nand" H 6250 2450 60  0000 C CNN
+F 2 "" H 6250 2250 60  0000 C CNN
+F 3 "" H 6250 2250 60  0000 C CNN
+	1    6250 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6275 1575
+F 0 "U?" H 6275 1950 60  0000 C CNN
+F 1 "d_nand" H 6275 1800 60  0000 C CNN
+F 2 "" H 6275 1575 60  0000 C CNN
+F 3 "" H 6275 1575 60  0000 C CNN
+	1    6275 1575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6275 5425
+F 0 "U?" H 6275 5775 60  0000 C CNN
+F 1 "d_nand" H 6275 5625 60  0000 C CNN
+F 2 "" H 6275 5425 60  0000 C CNN
+F 3 "" H 6275 5425 60  0000 C CNN
+	1    6275 5425
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6300 4750
+F 0 "U?" H 6300 5125 60  0000 C CNN
+F 1 "d_nand" H 6300 4975 60  0000 C CNN
+F 2 "" H 6300 4750 60  0000 C CNN
+F 3 "" H 6300 4750 60  0000 C CNN
+	1    6300 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6325 3775
+F 0 "U?" H 6325 4125 60  0000 C CNN
+F 1 "d_nand" H 6325 3975 60  0000 C CNN
+F 2 "" H 6325 3775 60  0000 C CNN
+F 3 "" H 6325 3775 60  0000 C CNN
+	1    6325 3775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6325 7175
+F 0 "U?" H 6325 7525 60  0000 C CNN
+F 1 "d_nand" H 6325 7375 60  0000 C CNN
+F 2 "" H 6325 7175 60  0000 C CNN
+F 3 "" H 6325 7175 60  0000 C CNN
+	1    6325 7175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6350 3100
+F 0 "U?" H 6350 3475 60  0000 C CNN
+F 1 "d_nand" H 6350 3325 60  0000 C CNN
+F 2 "" H 6350 3100 60  0000 C CNN
+F 3 "" H 6350 3100 60  0000 C CNN
+	1    6350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 6350 6500
+F 0 "U?" H 6350 6875 60  0000 C CNN
+F 1 "d_nand" H 6350 6725 60  0000 C CNN
+F 2 "" H 6350 6500 60  0000 C CNN
+F 3 "" H 6350 6500 60  0000 C CNN
+	1    6350 6500
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC125/74HC125/analysis b/library/SubcircuitLibrary/IC74HC125/74HC125/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC125/74HC125/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and-cache.lib b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.pro b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.pro
new file mode 100644
index 000000000..da3e199e2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 20:00:16 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.sch b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.sub b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and-cache.lib b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and-rescue.lib b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.pro b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.sch b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.sub b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/5_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.cir
new file mode 100644
index 000000000..abdebf964
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.cir
@@ -0,0 +1,26 @@
+.title KiCad schematic
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ GND Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND PORT
+X4 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U6-Pad2_ Net-_U11-Pad2_ 5_and
+X3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U11-Pad1_ 5_and
+X1 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U9-Pad1_ 5_and
+X2 Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U6-Pad2_ Net-_U9-Pad2_ 5_and
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U10-Pad1_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad2_ d_nor
+U12 Net-_U1-Pad6_ Net-_U1-Pad5_ d_inverter
+X5 Net-_U1-Pad15_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad1_ 5_and
+X6 Net-_U1-Pad14_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ 5_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor
+U15 Net-_U14-Pad3_ Net-_U15-Pad2_ Net-_U13-Pad2_ d_nor
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U15-Pad2_ d_nor
+U13 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_nor
+U7 Net-_U4-Pad2_ Net-_U7-Pad2_ d_inverter
+U6 Net-_U1-Pad7_ Net-_U6-Pad2_ d_inverter
+U8 Net-_U3-Pad2_ Net-_U8-Pad2_ d_inverter
+U5 Net-_U2-Pad2_ Net-_U5-Pad2_ d_inverter
+U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+U4 Net-_U1-Pad10_ Net-_U4-Pad2_ d_inverter
+X7 Net-_U1-Pad13_ Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U16-Pad1_ 5_and
+X8 Net-_U1-Pad12_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U16-Pad2_ 5_and
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.cir.out
new file mode 100644
index 000000000..613923c0b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.cir.out
@@ -0,0 +1,81 @@
+.title kicad schematic
+
+.include 5_and.sub
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd port
+* u7 net-_u4-pad2_ net-_u7-pad2_ d_inverter
+* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter
+* u8 net-_u3-pad2_ net-_u8-pad2_ d_inverter
+* u5 net-_u2-pad2_ net-_u5-pad2_ d_inverter
+* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad10_ net-_u4-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x4 net-_u1-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u11-pad2_ 5_and
+x3 net-_u1-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u11-pad1_ 5_and
+x1 net-_u1-pad4_ net-_u2-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u9-pad1_ 5_and
+x2 net-_u1-pad3_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u9-pad2_ 5_and
+* u12 net-_u1-pad6_ net-_u1-pad5_ d_inverter
+x8 net-_u1-pad12_ net-_u7-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u16-pad2_ 5_and
+x7 net-_u1-pad13_ net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u16-pad1_ 5_and
+x6 net-_u1-pad14_ net-_u4-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u14-pad2_ 5_and
+x5 net-_u1-pad15_ net-_u4-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u14-pad1_ 5_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
+* u15 net-_u14-pad3_ net-_u15-pad2_ net-_u13-pad2_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u15-pad2_ d_nor
+* u13 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad6_ d_nor
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u10-pad1_ d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+a1 net-_u4-pad2_ net-_u7-pad2_ u7
+a2 net-_u1-pad7_ net-_u6-pad2_ u6
+a3 net-_u3-pad2_ net-_u8-pad2_ u8
+a4 net-_u2-pad2_ net-_u5-pad2_ u5
+a5 net-_u1-pad11_ net-_u3-pad2_ u3
+a6 net-_u1-pad10_ net-_u4-pad2_ u4
+a7 net-_u1-pad9_ net-_u2-pad2_ u2
+a8 net-_u1-pad6_ net-_u1-pad5_ u12
+a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a10 [net-_u14-pad3_ net-_u15-pad2_ ] net-_u13-pad2_ u15
+a11 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u15-pad2_ u16
+a12 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad6_ u13
+a13 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u10-pad1_ u9
+a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.kicad_sch b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.kicad_sch
new file mode 100644
index 000000000..268f77787
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.kicad_sch
@@ -0,0 +1,2298 @@
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+    (pin "14" (uuid f59a1420-37a7-466e-a633-13b647095f47))
+    (pin "15" (uuid b41e7dd2-d8cf-428d-864d-394b071e3e3e))
+    (pin "16" (uuid 8b004c34-ef5c-4665-912f-56b30bbd7c2a))
+    (pin "17" (uuid 681d422c-6546-4553-b899-9ca551433a5f))
+    (pin "18" (uuid ba39ca36-8143-4971-9eeb-967eb6c71051))
+    (pin "19" (uuid 10479527-926b-41f8-a570-ddffaef68820))
+    (pin "20" (uuid f8ec0b21-1df6-4795-82ac-c55bc9f0545b))
+    (pin "21" (uuid 50579da2-6fcf-437d-8198-4c93f801ec41))
+    (pin "22" (uuid 59619400-570c-4e17-bc2c-70a3ebb022c1))
+    (pin "23" (uuid 688d432a-9300-4f5a-beb9-9d8fcc3e8737))
+    (pin "24" (uuid cf6ab02c-ebf0-413f-b4d3-deec415c1f31))
+    (pin "25" (uuid ebd1d1e6-a3e1-45c2-a227-031e67eaae4a))
+    (pin "26" (uuid 9d1d67ce-0b2c-4ea5-b75d-8b515bffb5fe))
+  )
+
+  (symbol (lib_id "eSim_Subckt:5_and") (at 434.34 186.69 90) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid e24860fa-5c61-4389-8a65-f9313093e035)
+    (property "Reference" "X8" (id 0) (at 441.96 186.7529 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Value" "5_and" (id 1) (at 441.96 190.5629 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Footprint" "" (id 2) (at 434.34 186.69 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 434.34 186.69 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 9188c5b0-a314-4f78-9267-d5eb980f9f1c))
+    (pin "2" (uuid 0a3bad64-7208-46ac-aadc-1b1287e5630b))
+    (pin "3" (uuid a76f3dc1-669a-4d51-9ffa-baddb2bbd102))
+    (pin "4" (uuid 192764ba-728b-4889-ba59-454d3b62f6c8))
+    (pin "5" (uuid 69deabd0-4da9-4aff-a844-8ab6a61a3bac))
+    (pin "6" (uuid 418ae302-1ccf-478a-86fc-cd929f0a5324))
+  )
+
+  (symbol (lib_id "eSim_Digital:d_nor") (at 387.35 259.08 90) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid e5a21fd7-84da-4eb8-8312-c6b96048a36b)
+    (property "Reference" "U15" (id 0) (at 389.89 257.81 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Value" "d_nor" (id 1) (at 389.89 261.62 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Footprint" "" (id 2) (at 387.35 259.08 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 387.35 259.08 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 7544f96c-a160-41e3-a3b1-353ed23a1ff4))
+    (pin "2" (uuid 6a443de9-7e37-40d9-a0a3-f7940c95a695))
+    (pin "3" (uuid a269c919-3a4b-4646-ad9c-5e97a9256b61))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/dde152ed-3c9a-4d98-818d-1bb6380a2bda"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/8e858c60-159a-4c0c-865b-4bf1e5970601"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/4e229321-8992-4fae-b463-67e903c809cf"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/199944cc-08b1-4860-9500-f5b6c83127cb"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/592a4060-58e5-4225-8e66-dc14a9b6f66e"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/a8b01f27-50a7-41b9-bbaa-24d649eac624"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/e0162d8f-937e-4f30-bab2-5b89ca9e726a"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/2379ef3f-4876-4f2f-86a2-f82eafa9c565"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/d1e140eb-e0ea-4f77-a618-d2d1ae34d82e"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/537379ea-fa54-496e-8535-e5dc8e53d133"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/67f71ab2-c058-4bf1-8fcf-273781407d41"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/9e0202d8-0e7c-4582-b8c8-0744686f03e1"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/ceaf4925-42c6-4bee-bf37-a399981e7568"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/77ed2dbf-1638-427f-8ed9-f6bc75653296"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/c3276754-ccfc-4fa1-abca-ae041ef72bdc"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/892b45ef-204c-40f3-a8e8-9bfe4d160caa"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/877a252e-1dcc-43a4-b6f7-f2b0701fd97b"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/82937949-341e-483c-87f3-a1193aec57d9"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/8e8870ec-967a-406d-910e-3de478f515c4"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3254cfb9-f3cb-47f4-b05a-2722fa6d3ba9"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/4f230d91-2e5a-456c-b965-978d18776012"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/2fdc79cc-6547-4e06-a631-c5daac042626"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a19b86ed-6386-4f35-9112-082103008a83"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/81bb25de-21a7-476d-b476-f00762b70ea7"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/cf2dfa2e-a791-4af9-a4b2-6039e1fd62a5"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/312b99ad-3390-46b4-b225-4f4f8f89e3a5"
+      (reference "U9") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/5f4d7c6b-c70f-455f-84bb-10f141a361ff"
+      (reference "U10") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0930e516-1128-4a18-8db9-f1d1e7740231"
+      (reference "U11") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/588bdc6b-632a-4a58-843d-09990174f72e"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8d553549-b9b6-47da-adec-1da7bc56be60"
+      (reference "U13") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/822d692a-8215-4946-ada3-806abd53e467"
+      (reference "U14") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/e5a21fd7-84da-4eb8-8312-c6b96048a36b"
+      (reference "U15") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/3e5c0c79-b461-40b2-a754-7dec4431afcb"
+      (reference "U16") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0993137b-93eb-4bcf-9c10-a5557b4c128b"
+      (reference "X1") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/8f592d50-f22c-4baf-a769-430368029d8a"
+      (reference "X2") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/92a3f1ad-ea86-477b-bad8-9169a58fc540"
+      (reference "X3") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/12862a47-9608-49f9-98ad-3346ea3c0c53"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/2c02c095-a3ce-4aca-b474-5bdc4049b1f3"
+      (reference "X5") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/08a2230b-2142-4fd5-8ef0-4418875a903d"
+      (reference "X6") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/94a95dfc-6b30-40a5-8129-d2ec63474536"
+      (reference "X7") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/e24860fa-5c61-4389-8a65-f9313093e035"
+      (reference "X8") (unit 1) (value "5_and") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.sub b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.sub
new file mode 100644
index 000000000..559f14a52
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151.sub
@@ -0,0 +1,75 @@
+* Subcircuit 74HC151
+.subckt 74HC151 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd 
+.title kicad schematic
+.include 5_and.sub
+* u7 net-_u4-pad2_ net-_u7-pad2_ d_inverter
+* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter
+* u8 net-_u3-pad2_ net-_u8-pad2_ d_inverter
+* u5 net-_u2-pad2_ net-_u5-pad2_ d_inverter
+* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad10_ net-_u4-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x4 net-_u1-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u11-pad2_ 5_and
+x3 net-_u1-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u11-pad1_ 5_and
+x1 net-_u1-pad4_ net-_u2-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u9-pad1_ 5_and
+x2 net-_u1-pad3_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u9-pad2_ 5_and
+* u12 net-_u1-pad6_ net-_u1-pad5_ d_inverter
+x8 net-_u1-pad12_ net-_u7-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u16-pad2_ 5_and
+x7 net-_u1-pad13_ net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u16-pad1_ 5_and
+x6 net-_u1-pad14_ net-_u4-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u14-pad2_ 5_and
+x5 net-_u1-pad15_ net-_u4-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u14-pad1_ 5_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
+* u15 net-_u14-pad3_ net-_u15-pad2_ net-_u13-pad2_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u15-pad2_ d_nor
+* u13 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad6_ d_nor
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u10-pad1_ d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+a1 net-_u4-pad2_ net-_u7-pad2_ u7
+a2 net-_u1-pad7_ net-_u6-pad2_ u6
+a3 net-_u3-pad2_ net-_u8-pad2_ u8
+a4 net-_u2-pad2_ net-_u5-pad2_ u5
+a5 net-_u1-pad11_ net-_u3-pad2_ u3
+a6 net-_u1-pad10_ net-_u4-pad2_ u4
+a7 net-_u1-pad9_ net-_u2-pad2_ u2
+a8 net-_u1-pad6_ net-_u1-pad5_ u12
+a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a10 [net-_u14-pad3_ net-_u15-pad2_ ] net-_u13-pad2_ u15
+a11 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u15-pad2_ u16
+a12 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad6_ u13
+a13 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u10-pad1_ u9
+a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC151
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Previous_Values.xml
new file mode 100644
index 000000000..8e9898616
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">5</v1><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model><u9 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u9><u11 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u13><u16 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u16><u15 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_nor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u3><u8 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u6><u5 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u7><u4 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u2><u26 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u26><u23 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u23><u17 name="type">adc_bridge<field9 name="Enter value for in_low (default=1.0)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u17><u19 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u19><u25 name="type">d_nor<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u25><u29 name="type">d_nor<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u29><u27 name="type">d_nor<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u27><u15 name="type">adc_bridge<field26 name="Enter value for in_low (default=1.0)" /><field27 name="Enter value for in_high (default=2.0)" /><field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /></u15><u13 name="type">adc_bridge<field30 name="Enter value for in_low (default=1.0)" /><field31 name="Enter value for in_high (default=2.0)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u13><u18 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">dac_bridge<field49 name="Enter value for out_low (default=0.0)" /><field50 name="Enter value for out_high (default=5.0)" /><field51 name="Enter value for out_undef (default=0.5)" /><field52 name="Enter value for input load (default=1.0e-12)" /><field53 name="Enter the Rise Time (default=1.0e-9)" /><field54 name="Enter the Fall Time (default=1.0e-9)" /></u24><u22 name="type">dac_bridge<field55 name="Enter value for out_low (default=0.0)" /><field56 name="Enter value for out_high (default=5.0)" /><field57 name="Enter value for out_undef (default=0.5)" /><field58 name="Enter value for input load (default=1.0e-12)" /><field59 name="Enter the Rise Time (default=1.0e-9)" /><field60 name="Enter the Fall Time (default=1.0e-9)" /></u22><u11 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">adc_bridge<field82 name="Enter value for in_low (default=1.0)" /><field83 name="Enter value for in_high (default=2.0)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /><field85 name="Enter Fall Delay (default=1.0e-9)" /></u5><u4 name="type">adc_bridge<field86 name="Enter value for in_low (default=1.0)" /><field87 name="Enter value for in_high (default=2.0)" /><field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /></u4><u2 name="type">adc_bridge<field90 name="Enter value for in_low (default=1.0)" /><field91 name="Enter value for in_high (default=2.0)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">adc_bridge<field94 name="Enter value for in_low (default=1.0)" /><field95 name="Enter value for in_high (default=2.0)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /></u3><u28 name="type">adc_bridge<field98 name="Enter value for in_low (default=1.0)" /><field99 name="Enter value for in_high (default=2.0)" /><field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /></u28><u30 name="type">adc_bridge<field102 name="Enter value for in_low (default=1.0)" /><field103 name="Enter value for in_high (default=2.0)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u30></model><devicemodel /><subcircuit><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and-cache.lib b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.pro b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.pro
new file mode 100644
index 000000000..da3e199e2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 20:00:16 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.sch b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.sub b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and-cache.lib b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and-rescue.lib b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.pro b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.sch b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.sub b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.cir
new file mode 100644
index 000000000..abdebf964
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.cir
@@ -0,0 +1,26 @@
+.title KiCad schematic
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ GND Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND PORT
+X4 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U6-Pad2_ Net-_U11-Pad2_ 5_and
+X3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U11-Pad1_ 5_and
+X1 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U9-Pad1_ 5_and
+X2 Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U6-Pad2_ Net-_U9-Pad2_ 5_and
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U10-Pad1_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad2_ d_nor
+U12 Net-_U1-Pad6_ Net-_U1-Pad5_ d_inverter
+X5 Net-_U1-Pad15_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad1_ 5_and
+X6 Net-_U1-Pad14_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ 5_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor
+U15 Net-_U14-Pad3_ Net-_U15-Pad2_ Net-_U13-Pad2_ d_nor
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U15-Pad2_ d_nor
+U13 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_nor
+U7 Net-_U4-Pad2_ Net-_U7-Pad2_ d_inverter
+U6 Net-_U1-Pad7_ Net-_U6-Pad2_ d_inverter
+U8 Net-_U3-Pad2_ Net-_U8-Pad2_ d_inverter
+U5 Net-_U2-Pad2_ Net-_U5-Pad2_ d_inverter
+U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+U4 Net-_U1-Pad10_ Net-_U4-Pad2_ d_inverter
+X7 Net-_U1-Pad13_ Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad2_ Net-_U6-Pad2_ Net-_U16-Pad1_ 5_and
+X8 Net-_U1-Pad12_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U16-Pad2_ 5_and
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.cir.out
new file mode 100644
index 000000000..613923c0b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.cir.out
@@ -0,0 +1,81 @@
+.title kicad schematic
+
+.include 5_and.sub
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd port
+* u7 net-_u4-pad2_ net-_u7-pad2_ d_inverter
+* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter
+* u8 net-_u3-pad2_ net-_u8-pad2_ d_inverter
+* u5 net-_u2-pad2_ net-_u5-pad2_ d_inverter
+* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad10_ net-_u4-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x4 net-_u1-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u11-pad2_ 5_and
+x3 net-_u1-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u11-pad1_ 5_and
+x1 net-_u1-pad4_ net-_u2-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u9-pad1_ 5_and
+x2 net-_u1-pad3_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u9-pad2_ 5_and
+* u12 net-_u1-pad6_ net-_u1-pad5_ d_inverter
+x8 net-_u1-pad12_ net-_u7-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u16-pad2_ 5_and
+x7 net-_u1-pad13_ net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u16-pad1_ 5_and
+x6 net-_u1-pad14_ net-_u4-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u14-pad2_ 5_and
+x5 net-_u1-pad15_ net-_u4-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u14-pad1_ 5_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
+* u15 net-_u14-pad3_ net-_u15-pad2_ net-_u13-pad2_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u15-pad2_ d_nor
+* u13 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad6_ d_nor
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u10-pad1_ d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+a1 net-_u4-pad2_ net-_u7-pad2_ u7
+a2 net-_u1-pad7_ net-_u6-pad2_ u6
+a3 net-_u3-pad2_ net-_u8-pad2_ u8
+a4 net-_u2-pad2_ net-_u5-pad2_ u5
+a5 net-_u1-pad11_ net-_u3-pad2_ u3
+a6 net-_u1-pad10_ net-_u4-pad2_ u4
+a7 net-_u1-pad9_ net-_u2-pad2_ u2
+a8 net-_u1-pad6_ net-_u1-pad5_ u12
+a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a10 [net-_u14-pad3_ net-_u15-pad2_ ] net-_u13-pad2_ u15
+a11 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u15-pad2_ u16
+a12 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad6_ u13
+a13 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u10-pad1_ u9
+a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.kicad_sch b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.kicad_sch
new file mode 100644
index 000000000..268f77787
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.kicad_sch
@@ -0,0 +1,2298 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 3019b4d2-5f03-4e25-9d1a-aeb78c8597dd)
+
+  (paper "A2")
+
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+    (pin "26" (uuid 0bacf324-8e3d-45c7-aba3-c7f4f778fc6a))
+  )
+
+  (symbol (lib_id "eSim_Power:eSim_GND") (at 519.43 147.32 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid dde152ed-3c9a-4d98-818d-1bb6380a2bda)
+    (property "Reference" "#PWR01" (id 0) (at 519.43 153.67 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "eSim_GND" (id 1) (at 519.43 152.4 0))
+    (property "Footprint" "" (id 2) (at 519.43 147.32 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 519.43 147.32 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 57703024-9e60-4ee1-b5d5-c998e331564b))
+  )
+
+  (symbol (lib_id "eSim_Miscellaneous:PORT") (at 308.61 350.52 90) (unit 5)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid e0162d8f-937e-4f30-bab2-5b89ca9e726a)
+    (property "Reference" "U1" (id 0) (at 311.15 349.25 90)
+      (effects (font (size 0.762 0.762)) (justify right))
+    )
+    (property "Value" "PORT" (id 1) (at 311.15 351.79 90)
+      (effects (font (size 0.762 0.762)) (justify right))
+    )
+    (property "Footprint" "" (id 2) (at 308.61 350.52 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 308.61 350.52 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 4f589ea7-c3f1-461c-ae13-39d523749c2c))
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+    (pin "6" (uuid c90f1c0e-5b39-4569-a36c-8b00c545ed8c))
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+    (pin "11" (uuid 3b2cb344-e532-41c1-9863-3b38f0031d1b))
+    (pin "12" (uuid d1ad429c-3cc4-4d62-ae09-6f146783c490))
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+    (pin "16" (uuid 8b004c34-ef5c-4665-912f-56b30bbd7c2a))
+    (pin "17" (uuid 681d422c-6546-4553-b899-9ca551433a5f))
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+    (pin "19" (uuid 10479527-926b-41f8-a570-ddffaef68820))
+    (pin "20" (uuid f8ec0b21-1df6-4795-82ac-c55bc9f0545b))
+    (pin "21" (uuid 50579da2-6fcf-437d-8198-4c93f801ec41))
+    (pin "22" (uuid 59619400-570c-4e17-bc2c-70a3ebb022c1))
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+    (pin "25" (uuid ebd1d1e6-a3e1-45c2-a227-031e67eaae4a))
+    (pin "26" (uuid 9d1d67ce-0b2c-4ea5-b75d-8b515bffb5fe))
+  )
+
+  (symbol (lib_id "eSim_Subckt:5_and") (at 434.34 186.69 90) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid e24860fa-5c61-4389-8a65-f9313093e035)
+    (property "Reference" "X8" (id 0) (at 441.96 186.7529 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Value" "5_and" (id 1) (at 441.96 190.5629 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Footprint" "" (id 2) (at 434.34 186.69 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 434.34 186.69 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 9188c5b0-a314-4f78-9267-d5eb980f9f1c))
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+    (pin "6" (uuid 418ae302-1ccf-478a-86fc-cd929f0a5324))
+  )
+
+  (symbol (lib_id "eSim_Digital:d_nor") (at 387.35 259.08 90) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid e5a21fd7-84da-4eb8-8312-c6b96048a36b)
+    (property "Reference" "U15" (id 0) (at 389.89 257.81 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Value" "d_nor" (id 1) (at 389.89 261.62 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Footprint" "" (id 2) (at 387.35 259.08 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 387.35 259.08 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 7544f96c-a160-41e3-a3b1-353ed23a1ff4))
+    (pin "2" (uuid 6a443de9-7e37-40d9-a0a3-f7940c95a695))
+    (pin "3" (uuid a269c919-3a4b-4646-ad9c-5e97a9256b61))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/dde152ed-3c9a-4d98-818d-1bb6380a2bda"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/8e858c60-159a-4c0c-865b-4bf1e5970601"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/4e229321-8992-4fae-b463-67e903c809cf"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/199944cc-08b1-4860-9500-f5b6c83127cb"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/592a4060-58e5-4225-8e66-dc14a9b6f66e"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/a8b01f27-50a7-41b9-bbaa-24d649eac624"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/e0162d8f-937e-4f30-bab2-5b89ca9e726a"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/2379ef3f-4876-4f2f-86a2-f82eafa9c565"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/d1e140eb-e0ea-4f77-a618-d2d1ae34d82e"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/537379ea-fa54-496e-8535-e5dc8e53d133"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/67f71ab2-c058-4bf1-8fcf-273781407d41"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/9e0202d8-0e7c-4582-b8c8-0744686f03e1"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/ceaf4925-42c6-4bee-bf37-a399981e7568"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/77ed2dbf-1638-427f-8ed9-f6bc75653296"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/c3276754-ccfc-4fa1-abca-ae041ef72bdc"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/892b45ef-204c-40f3-a8e8-9bfe4d160caa"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/877a252e-1dcc-43a4-b6f7-f2b0701fd97b"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/82937949-341e-483c-87f3-a1193aec57d9"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/8e8870ec-967a-406d-910e-3de478f515c4"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3254cfb9-f3cb-47f4-b05a-2722fa6d3ba9"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/4f230d91-2e5a-456c-b965-978d18776012"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/2fdc79cc-6547-4e06-a631-c5daac042626"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a19b86ed-6386-4f35-9112-082103008a83"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/81bb25de-21a7-476d-b476-f00762b70ea7"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/cf2dfa2e-a791-4af9-a4b2-6039e1fd62a5"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/312b99ad-3390-46b4-b225-4f4f8f89e3a5"
+      (reference "U9") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/5f4d7c6b-c70f-455f-84bb-10f141a361ff"
+      (reference "U10") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0930e516-1128-4a18-8db9-f1d1e7740231"
+      (reference "U11") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/588bdc6b-632a-4a58-843d-09990174f72e"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8d553549-b9b6-47da-adec-1da7bc56be60"
+      (reference "U13") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/822d692a-8215-4946-ada3-806abd53e467"
+      (reference "U14") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/e5a21fd7-84da-4eb8-8312-c6b96048a36b"
+      (reference "U15") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/3e5c0c79-b461-40b2-a754-7dec4431afcb"
+      (reference "U16") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0993137b-93eb-4bcf-9c10-a5557b4c128b"
+      (reference "X1") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/8f592d50-f22c-4baf-a769-430368029d8a"
+      (reference "X2") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/92a3f1ad-ea86-477b-bad8-9169a58fc540"
+      (reference "X3") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/12862a47-9608-49f9-98ad-3346ea3c0c53"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/2c02c095-a3ce-4aca-b474-5bdc4049b1f3"
+      (reference "X5") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/08a2230b-2142-4fd5-8ef0-4418875a903d"
+      (reference "X6") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/94a95dfc-6b30-40a5-8129-d2ec63474536"
+      (reference "X7") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/e24860fa-5c61-4389-8a65-f9313093e035"
+      (reference "X8") (unit 1) (value "5_and") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.sub b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.sub
new file mode 100644
index 000000000..559f14a52
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151.sub
@@ -0,0 +1,75 @@
+* Subcircuit 74HC151
+.subckt 74HC151 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd 
+.title kicad schematic
+.include 5_and.sub
+* u7 net-_u4-pad2_ net-_u7-pad2_ d_inverter
+* u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter
+* u8 net-_u3-pad2_ net-_u8-pad2_ d_inverter
+* u5 net-_u2-pad2_ net-_u5-pad2_ d_inverter
+* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad10_ net-_u4-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x4 net-_u1-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u11-pad2_ 5_and
+x3 net-_u1-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u11-pad1_ 5_and
+x1 net-_u1-pad4_ net-_u2-pad2_ net-_u4-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u9-pad1_ 5_and
+x2 net-_u1-pad3_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad2_ net-_u9-pad2_ 5_and
+* u12 net-_u1-pad6_ net-_u1-pad5_ d_inverter
+x8 net-_u1-pad12_ net-_u7-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u16-pad2_ 5_and
+x7 net-_u1-pad13_ net-_u7-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u16-pad1_ 5_and
+x6 net-_u1-pad14_ net-_u4-pad2_ net-_u8-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u14-pad2_ 5_and
+x5 net-_u1-pad15_ net-_u4-pad2_ net-_u5-pad2_ net-_u3-pad2_ net-_u6-pad2_ net-_u14-pad1_ 5_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
+* u15 net-_u14-pad3_ net-_u15-pad2_ net-_u13-pad2_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u15-pad2_ d_nor
+* u13 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad6_ d_nor
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u10-pad1_ d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+a1 net-_u4-pad2_ net-_u7-pad2_ u7
+a2 net-_u1-pad7_ net-_u6-pad2_ u6
+a3 net-_u3-pad2_ net-_u8-pad2_ u8
+a4 net-_u2-pad2_ net-_u5-pad2_ u5
+a5 net-_u1-pad11_ net-_u3-pad2_ u3
+a6 net-_u1-pad10_ net-_u4-pad2_ u4
+a7 net-_u1-pad9_ net-_u2-pad2_ u2
+a8 net-_u1-pad6_ net-_u1-pad5_ u12
+a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a10 [net-_u14-pad3_ net-_u15-pad2_ ] net-_u13-pad2_ u15
+a11 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u15-pad2_ u16
+a12 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad6_ u13
+a13 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u10-pad1_ u9
+a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC151
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_Previous_Values.xml
new file mode 100644
index 000000000..8e9898616
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">5</v1><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model><u9 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u9><u11 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u13><u16 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u16><u15 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_nor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u3><u8 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u6><u5 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u7><u4 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u2><u26 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u26><u23 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u23><u17 name="type">adc_bridge<field9 name="Enter value for in_low (default=1.0)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u17><u19 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u19><u25 name="type">d_nor<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u25><u29 name="type">d_nor<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u29><u27 name="type">d_nor<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u27><u15 name="type">adc_bridge<field26 name="Enter value for in_low (default=1.0)" /><field27 name="Enter value for in_high (default=2.0)" /><field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /></u15><u13 name="type">adc_bridge<field30 name="Enter value for in_low (default=1.0)" /><field31 name="Enter value for in_high (default=2.0)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u13><u18 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">dac_bridge<field49 name="Enter value for out_low (default=0.0)" /><field50 name="Enter value for out_high (default=5.0)" /><field51 name="Enter value for out_undef (default=0.5)" /><field52 name="Enter value for input load (default=1.0e-12)" /><field53 name="Enter the Rise Time (default=1.0e-9)" /><field54 name="Enter the Fall Time (default=1.0e-9)" /></u24><u22 name="type">dac_bridge<field55 name="Enter value for out_low (default=0.0)" /><field56 name="Enter value for out_high (default=5.0)" /><field57 name="Enter value for out_undef (default=0.5)" /><field58 name="Enter value for input load (default=1.0e-12)" /><field59 name="Enter the Rise Time (default=1.0e-9)" /><field60 name="Enter the Fall Time (default=1.0e-9)" /></u22><u11 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">adc_bridge<field82 name="Enter value for in_low (default=1.0)" /><field83 name="Enter value for in_high (default=2.0)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /><field85 name="Enter Fall Delay (default=1.0e-9)" /></u5><u4 name="type">adc_bridge<field86 name="Enter value for in_low (default=1.0)" /><field87 name="Enter value for in_high (default=2.0)" /><field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /></u4><u2 name="type">adc_bridge<field90 name="Enter value for in_low (default=1.0)" /><field91 name="Enter value for in_high (default=2.0)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">adc_bridge<field94 name="Enter value for in_low (default=1.0)" /><field95 name="Enter value for in_high (default=2.0)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /><field97 name="Enter Fall Delay (default=1.0e-9)" /></u3><u28 name="type">adc_bridge<field98 name="Enter value for in_low (default=1.0)" /><field99 name="Enter value for in_high (default=2.0)" /><field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /></u28><u30 name="type">adc_bridge<field102 name="Enter value for in_low (default=1.0)" /><field103 name="Enter value for in_high (default=2.0)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u30></model><devicemodel /><subcircuit><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.cir b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.cir
new file mode 100644
index 000000000..d021450e4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.cir
@@ -0,0 +1,34 @@
+.title KiCad schematic
+U14 I6 plot_v1
+U10 S2 plot_v1
+U12 S0 plot_v1
+U13 I7 plot_v1
+U15 I5 plot_v1
+U16 I4 plot_v1
+U11 S1 plot_v1
+VEN1 Net-_U5-Pad5_ GND 0
+U6 Y plot_v1
+VI2 I2 GND pulse
+VI1 I1 GND pulse
+VI0 I0 GND pulse
+U9 I4 I5 I6 I7 S0 S1 S2 Net-_U9-Pad8_ Net-_U9-Pad9_ Net-_U9-Pad10_ Net-_U9-Pad11_ Net-_U9-Pad12_ Net-_U9-Pad13_ Net-_U9-Pad14_ adc_bridge_7
+v1 Net-_X1-Pad16_ GND 5
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Y YC dac_bridge_2
+U8 YC plot_v1
+R1 GND Y 1k
+R2 YC GND 1k
+VS0 S0 GND pulse
+VS1 S1 GND pulse
+VI5 I5 GND pulse
+VI6 I6 GND pulse
+VI7 I7 GND pulse
+VS2 S2 GND pulse
+U2 I2 plot_v1
+U1 I3 plot_v1
+VI3 I3 GND pulse
+U3 I1 plot_v1
+U4 I0 plot_v1
+X1 Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ Net-_U5-Pad9_ Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U5-Pad10_ GND Net-_U9-Pad14_ Net-_U9-Pad13_ Net-_U9-Pad12_ Net-_U9-Pad11_ Net-_U9-Pad10_ Net-_U9-Pad9_ Net-_U9-Pad8_ Net-_X1-Pad16_ 74HC151
+U5 I3 I2 I1 I0 Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ Net-_U5-Pad9_ Net-_U5-Pad10_ adc_bridge_5
+VI4 I4 GND pulse
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.cir.out b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.cir.out
new file mode 100644
index 000000000..24d612525
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.cir.out
@@ -0,0 +1,66 @@
+.title kicad schematic
+
+.include 74HC151.sub
+* u14 i6 plot_v1
+* u10 s2 plot_v1
+* u12 s0 plot_v1
+* u13 i7 plot_v1
+* u15 i5 plot_v1
+* u16 i4 plot_v1
+* u11 s1 plot_v1
+ven1 net-_u5-pad5_ gnd 0
+* u6 y plot_v1
+vi2 i2 gnd pulse(0 5 20 1n 1n 10 100)
+vi1 i1 gnd pulse(0 5 10 1n 1n 10 100)
+vi0 i0 gnd pulse(0 5 0 1n 1n 10 100)
+* u9 i4 i5 i6 i7 s0 s1 s2 net-_u9-pad8_ net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ adc_bridge_7
+v1 net-_x1-pad16_ gnd 5
+* u7 net-_u7-pad1_ net-_u7-pad2_ y yc dac_bridge_2
+* u8 yc plot_v1
+r1 gnd y 1k
+r2 yc gnd 1k
+vs0 s0 gnd pulse(0 5 0 1n 1n 10 20)
+vs1 s1 gnd pulse(0 5 0 1n 1n 20 40)
+vi5 i5 gnd pulse(0 5 20 1n 1n 10 100)
+vi6 i6 gnd pulse(0 5 60 1n 1n 10 100)
+vi7 i7 gnd pulse(0 5 70 1n 1n 10 100)
+vs2 s2 gnd pulse(0 5 20 1n 1n 30 60)
+* u2 i2 plot_v1
+* u1 i3 plot_v1
+vi3 i3 gnd pulse(0 5 30 1n 1n 10 100)
+* u3 i1 plot_v1
+* u4 i0 plot_v1
+x1 net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ net-_u5-pad9_ net-_u7-pad1_ net-_u7-pad2_ net-_u5-pad10_ gnd net-_u9-pad14_ net-_u9-pad13_ net-_u9-pad12_ net-_u9-pad11_ net-_u9-pad10_ net-_u9-pad9_ net-_u9-pad8_ net-_x1-pad16_ 74HC151
+* u5 i3 i2 i1 i0 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ net-_u5-pad9_ net-_u5-pad10_ adc_bridge_5
+vi4 i4 gnd pulse(0 5 40 1n 1n 10 100)
+a1 [i4 i5 i6 i7 s0 s1 s2 ] [net-_u9-pad8_ net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ ] u9
+a2 [net-_u7-pad1_ net-_u7-pad2_ ] [y yc ] u7
+a3 [i3 i2 i1 i0 net-_u5-pad5_ ] [net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ net-_u5-pad9_ net-_u5-pad10_ ] u5
+* Schematic Name:                             adc_bridge_7, Ngspice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_2, Ngspice Name: dac_bridge
+.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_5, Ngspice Name: adc_bridge
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 5e-00 100e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(i6)
+plot v(s2)
+plot v(s0)
+plot v(i7)
+plot v(i5)
+plot v(i4)
+plot v(s1)
+plot v(y)
+plot v(yc)
+plot v(i2)
+plot v(i3)
+plot v(i1)
+plot v(i0)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.kicad_sch b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.kicad_sch
new file mode 100644
index 000000000..33e3b3557
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.kicad_sch
@@ -0,0 +1,2055 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 8e25e331-5748-45bb-bb37-2a6a4d8bbad8)
+
+  (paper "A2")
+
+  (lib_symbols
+    (symbol "DC_1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "VEN" (id 0) (at 5.08 3.175 0)
+        (effects (font (size 1.524 1.524)) (justify left))
+      )
+      (property "Value" "DC_1" (id 1) (at 5.08 -0.635 0)
+        (effects (font (size 1.524 1.524)) (justify left))
+      )
+      (property "Footprint" "R1" (id 2) (at 5.08 -4.445 0)
+        (effects (font (size 1.524 1.524)) (justify left))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "ki_fp_filters" "1_pin" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "DC_1_0_1"
+        (circle (center 0 0) (radius 3.81)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "DC_1_1_1"
+        (pin power_out line (at 0 11.43 270) (length 7.62)
+          (name "+" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin power_in line (at 0 -11.43 90) (length 7.62)
+          (name "-" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Devices:resistor" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "R" (id 0) (at 1.27 3.302 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "resistor" (id 1) (at 1.27 -1.27 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -0.508 0)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 1.27 90)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "ki_fp_filters" "R_* Resistor_*" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "resistor_0_1"
+        (rectangle (start 3.81 0.254) (end -1.27 2.286)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "resistor_1_1"
+        (pin passive line (at -2.54 1.27 0) (length 1.27)
+          (name "~" (effects (font (size 1.524 1.524))))
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diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.proj b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.proj
new file mode 100644
index 000000000..1d6260266
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.proj
@@ -0,0 +1 @@
+schematicFile 74HC151_TEST_CIR_2.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.raw b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.raw
new file mode 100644
index 000000000..ad5bcf42a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2.raw
@@ -0,0 +1,14268 @@
+Title: kicad schematic
+Date: Thu Nov 13 19:37:17  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 31
+No. Points: 459     
+Variables:
+	0	time	time
+	1	v(net-_u5-pad5_)	voltage
+	2	v(i2)	voltage
+	3	v(i1)	voltage
+	4	v(i0)	voltage
+	5	v(net-_x1-pad16_)	voltage
+	6	v(y)	voltage
+	7	v(yc)	voltage
+	8	v(s0)	voltage
+	9	v(s1)	voltage
+	10	v(i5)	voltage
+	11	v(i6)	voltage
+	12	v(i7)	voltage
+	13	v(s2)	voltage
+	14	v(i3)	voltage
+	15	v(i4)	voltage
+	16	i(vi4)	current
+	17	i(vi3)	current
+	18	i(vs2)	current
+	19	i(vi7)	current
+	20	i(vi6)	current
+	21	i(vi5)	current
+	22	i(vs1)	current
+	23	i(vs0)	current
+	24	i(v1)	current
+	25	i(vi0)	current
+	26	i(vi1)	current
+	27	i(vi2)	current
+	28	i(ven1)	current
+	29	i(a2)	current
+	30	i(a2)	current
+Values:
+0		0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
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diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2_Previous_Values.xml
new file mode 100644
index 000000000..02ab3a304
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/74HC151_TEST_CIR_2_Previous_Values.xml
@@ -0,0 +1 @@
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Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10</field5><field5 name="Period">20</field5></vs0><vs2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">20</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">30</field5><field5 name="Period">60</field5></vs2><v1 name="Source type">5</v1><vs1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">20</field5><field5 name="Period">40</field5></vs1><vi6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">60</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10</field5><field5 name="Period">100</field5></vi6><vi3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">30</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10</field5><field5 name="Period">100</field5></vi3><vi2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">20</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10</field5><field5 name="Period">100</field5></vi2><ven1 name="Source type">0</ven1><vi0 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10</field5><field5 name="Period">100</field5></vi0><vi1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">10</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10</field5><field5 name="Period">100</field5></vi1><ven1 name="Source type">5</ven1></source><model><u9 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u9><u7 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u7><u5 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u5></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC151</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/_autosave-74HC151.kicad_sch b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/_autosave-74HC151.kicad_sch
new file mode 100644
index 000000000..cd9d182b3
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/_autosave-74HC151.kicad_sch
@@ -0,0 +1,2350 @@
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+    )
+    (path "/36689ee5-f331-4b17-86d2-0b914ae70d67"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a0b673e3-7661-41c1-a8e7-7d324da7afe3"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f888cebb-2760-4fb9-a821-f9e2bcbc6c88"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5b7a13cb-7dc4-4e19-8692-6161848ac2fe"
+      (reference "U11") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/13f98901-ae38-4b55-b52d-da2bbceb9dca"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/142f0711-d40d-4a0a-a011-a395619d043a"
+      (reference "U14") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/73f5c6a8-8400-4459-a512-9e3d8a434d57"
+      (reference "U16") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/a0059c46-ee49-436a-9f13-ae5883c4ab5f"
+      (reference "U18") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/733ef5b5-448a-4bb0-ae72-04a3522f6df0"
+      (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/07e0c196-8ff1-4081-beac-c428de5b1665"
+      (reference "U21") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/2772f24b-6877-4567-9ea2-04b5e6e2e8be"
+      (reference "U25") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/aad11b0b-d81c-47cf-847e-6934f19b5ec7"
+      (reference "U27") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/55d39632-9f7c-40f1-a3a3-6f0bcd488131"
+      (reference "U29") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0a20b4a5-cdc9-4b3c-aab1-e2c8ab6d781b"
+      (reference "X1") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/9aa8ebb3-42fc-4937-9e67-6b8d96604d97"
+      (reference "X2") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/9dbd8746-14ed-41f3-9b4e-1aa725c2b10f"
+      (reference "X3") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/628766a7-aa03-49b1-a0bd-815996172608"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/bbd22df4-58a9-42c0-96b2-2d1a8242083e"
+      (reference "X5") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/23dce224-ef57-4b7d-bdfc-5cda87347625"
+      (reference "X6") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/87fd601f-61dc-4449-a870-f23c6c81c2cd"
+      (reference "X7") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/dd25f4a0-cfb0-4269-8f01-ff5340b520c5"
+      (reference "X8") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/87601897-697f-44e9-b7c5-b7e486f8d6fc"
+      (reference "v1") (unit 1) (value "DC") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/analysis b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/analysis
new file mode 100644
index 000000000..ef45c15d2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/74HC151_Test_Circuit/74HC151_TEST_CIR_2/analysis
@@ -0,0 +1 @@
+.tran 5e-00 100e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC151/74HC151/analysis b/library/SubcircuitLibrary/IC74HC151/74HC151/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC151/74HC151/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and-cache.lib b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.pro b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.pro
new file mode 100644
index 000000000..da3e199e2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 20:00:16 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.sch b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.sub b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and-cache.lib b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and-rescue.lib b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.pro b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.sch b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.sub b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/5_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and-cache.lib b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.pro b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.pro
new file mode 100644
index 000000000..da3e199e2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 20:00:16 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.sch b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.sub b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and-cache.lib b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and-rescue.lib b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.pro b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.sch b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.sub b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.cir
new file mode 100644
index 000000000..399cf632b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.cir
@@ -0,0 +1,46 @@
+.title KiCad schematic
+R8 GND V_Y7n 1k
+U12 V_Y7n plot_v1
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ V_Y8n V_Y9n V_Y10n dac_bridge_3
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ V_Y0n V_Y1n V_Y2n V_Y3n V_Y4n V_Y5n V_Y6n V_Y7n dac_bridge_8
+U9 V_Y0n plot_v1
+U5 V_Y2n plot_v1
+U7 V_Y1n plot_v1
+U6 V_Y3n plot_v1
+U8 V_Y4n plot_v1
+U11 V_Y6n plot_v1
+U10 V_Y5n plot_v1
+R10 GND V_Y9n 1k
+R11 GND V_Y10n 1k
+R1 GND V_Y0n 1k
+R3 GND V_Y2n 1k
+R2 GND V_Y1n 1k
+R7 GND V_Y6n 1k
+R6 GND V_Y5n 1k
+R5 GND V_Y4n 1k
+R4 GND V_Y3n 1k
+R9 GND V_Y8n 1k
+R15 GND V_Y14n 1k
+U13 V_Y10n plot_v1
+U14 V_Y9n plot_v1
+U15 V_Y8n plot_v1
+R14 GND V_Y13n 1k
+V_A0 Net-_V_A0-Pad1_ GND DC
+V_A2 Net-_V_A2-Pad1_ GND DC
+V_A1 Net-_V_A1-Pad1_ GND DC
+V_E1n1 Net-_V_E1n1-Pad1_ GND DC
+V_A3 Net-_V_A3-Pad1_ GND DC
+U20 V_Y12n plot_v1
+U19 V_Y13n plot_v1
+U17 V_Y11n plot_v1
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ GND Net-_U3-Pad5_ Net-_U3-Pad4_ Net-_U3-Pad3_ Net-_U3-Pad2_ Net-_U3-Pad1_ Net-_U4-Pad12_ Net-_U4-Pad11_ Net-_U4-Pad10_ Net-_U4-Pad9_ Net-_U4-Pad8_ Net-_U4-Pad7_ Net-_v1-Pad1_ 74LS154
+v1 Net-_v1-Pad1_ GND 5
+R12 GND V_Y11n 1k
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ V_Y15n V_Y14n V_Y13n V_Y12n V_Y11n dac_bridge_5
+U4 Net-_V_A0-Pad1_ Net-_V_A1-Pad1_ Net-_V_A2-Pad1_ Net-_V_A3-Pad1_ Net-_V_E1n1-Pad1_ Net-_V_E0n1-Pad1_ Net-_U4-Pad7_ Net-_U4-Pad8_ Net-_U4-Pad9_ Net-_U4-Pad10_ Net-_U4-Pad11_ Net-_U4-Pad12_ adc_bridge_6
+V_E0n1 Net-_V_E0n1-Pad1_ GND DC
+U16 V_Y15n plot_v1
+R16 GND V_Y15n 1k
+U18 V_Y14n plot_v1
+R13 GND V_Y12n 1k
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.cir.out
new file mode 100644
index 000000000..fcbbc955b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.cir.out
@@ -0,0 +1,84 @@
+.title kicad schematic
+
+.include 74LS154.sub
+r8 gnd v_y7n 1k
+* u12 v_y7n plot_v1
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ v_y8n v_y9n v_y10n dac_bridge_3
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ v_y0n v_y1n v_y2n v_y3n v_y4n v_y5n v_y6n v_y7n dac_bridge_8
+* u9 v_y0n plot_v1
+* u5 v_y2n plot_v1
+* u7 v_y1n plot_v1
+* u6 v_y3n plot_v1
+* u8 v_y4n plot_v1
+* u11 v_y6n plot_v1
+* u10 v_y5n plot_v1
+r10 gnd v_y9n 1k
+r11 gnd v_y10n 1k
+r1 gnd v_y0n 1k
+r3 gnd v_y2n 1k
+r2 gnd v_y1n 1k
+r7 gnd v_y6n 1k
+r6 gnd v_y5n 1k
+r5 gnd v_y4n 1k
+r4 gnd v_y3n 1k
+r9 gnd v_y8n 1k
+r15 gnd v_y14n 1k
+* u13 v_y10n plot_v1
+* u14 v_y9n plot_v1
+* u15 v_y8n plot_v1
+r14 gnd v_y13n 1k
+v_a0 net-_v_a0-pad1_ gnd  dc 5
+v_a2 net-_v_a2-pad1_ gnd  dc 0
+v_a1 net-_v_a1-pad1_ gnd  dc 5
+v_e1n1 net-_v_e1n1-pad1_ gnd  dc 0
+v_a3 net-_v_a3-pad1_ gnd  dc 0
+* u20 v_y12n plot_v1
+* u19 v_y13n plot_v1
+* u17 v_y11n plot_v1
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ gnd net-_u3-pad5_ net-_u3-pad4_ net-_u3-pad3_ net-_u3-pad2_ net-_u3-pad1_ net-_u4-pad12_ net-_u4-pad11_ net-_u4-pad10_ net-_u4-pad9_ net-_u4-pad8_ net-_u4-pad7_ net-_v1-pad1_ 74LS154
+v1 net-_v1-pad1_ gnd 5
+r12 gnd v_y11n 1k
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ v_y15n v_y14n v_y13n v_y12n v_y11n dac_bridge_5
+* u4 net-_v_a0-pad1_ net-_v_a1-pad1_ net-_v_a2-pad1_ net-_v_a3-pad1_ net-_v_e1n1-pad1_ net-_v_e0n1-pad1_ net-_u4-pad7_ net-_u4-pad8_ net-_u4-pad9_ net-_u4-pad10_ net-_u4-pad11_ net-_u4-pad12_ adc_bridge_6
+v_e0n1 net-_v_e0n1-pad1_ gnd  dc 0
+* u16 v_y15n plot_v1
+r16 gnd v_y15n 1k
+* u18 v_y14n plot_v1
+r13 gnd v_y12n 1k
+a1 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ ] [v_y8n v_y9n v_y10n ] u2
+a2 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [v_y0n v_y1n v_y2n v_y3n v_y4n v_y5n v_y6n v_y7n ] u1
+a3 [net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ ] [v_y15n v_y14n v_y13n v_y12n v_y11n ] u3
+a4 [net-_v_a0-pad1_ net-_v_a1-pad1_ net-_v_a2-pad1_ net-_v_a3-pad1_ net-_v_e1n1-pad1_ net-_v_e0n1-pad1_ ] [net-_u4-pad7_ net-_u4-pad8_ net-_u4-pad9_ net-_u4-pad10_ net-_u4-pad11_ net-_u4-pad12_ ] u4
+* Schematic Name:                             dac_bridge_3, Ngspice Name: dac_bridge
+.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_8, Ngspice Name: dac_bridge
+.model u1 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_5, Ngspice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_6, Ngspice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 5e-00 100e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_y7n)
+plot v(v_y0n)
+plot v(v_y2n)
+plot v(v_y1n)
+plot v(v_y3n)
+plot v(v_y4n)
+plot v(v_y6n)
+plot v(v_y5n)
+plot v(v_y10n)
+plot v(v_y9n)
+plot v(v_y8n)
+plot v(v_y12n)
+plot v(v_y13n)
+plot v(v_y11n)
+plot v(v_y15n)
+plot v(v_y14n)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.kicad_sch b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.kicad_sch
new file mode 100644
index 000000000..a707b97fe
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.kicad_sch
@@ -0,0 +1,2711 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 61bc50a4-3abf-494f-8714-6f401308e230)
+
+  (paper "A3")
+
+  (lib_symbols
+    (symbol "eSim_Devices:resistor" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "R" (id 0) (at 1.27 3.302 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "resistor" (id 1) (at 1.27 -1.27 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -0.508 0)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 1.27 90)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "ki_fp_filters" "R_* Resistor_*" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "resistor_0_1"
+        (rectangle (start 3.81 0.254) (end -1.27 2.286)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "resistor_1_1"
+        (pin passive line (at -2.54 1.27 0) (length 1.27)
+          (name "~" (effects (font (size 1.524 1.524))))
+          (number "1" (effects (font (size 1.524 1.524))))
+        )
+        (pin passive line (at 5.08 1.27 180) (length 1.27)
+          (name "~" (effects (font (size 1.524 1.524))))
+          (number "2" (effects (font (size 1.524 1.524))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:adc_bridge_6" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_6" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_6_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -12.7)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "adc_bridge_6_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -6.35 180) (length 5.08)
+          (name "OUT4" (effects (font (size 1.27 1.27))))
+          (number "10" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -8.89 180) (length 5.08)
+          (name "OUT5" (effects (font (size 1.27 1.27))))
+          (number "11" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -11.43 180) (length 5.08)
+          (name "OUT6" (effects (font (size 1.27 1.27))))
+          (number "12" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -1.27 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -3.81 0) (length 5.08)
+          (name "IN3" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -6.35 0) (length 5.08)
+          (name "IN4" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -8.89 0) (length 5.08)
+          (name "IN5" (effects (font (size 1.27 1.27))))
+          (number "5" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -11.43 0) (length 5.08)
+          (name "IN6" (effects (font (size 1.27 1.27))))
+          (number "6" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 1.27 180) (length 5.08)
+          (name "OUT1" (effects (font (size 1.27 1.27))))
+          (number "7" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -1.27 180) (length 5.08)
+          (name "OUT2" (effects (font (size 1.27 1.27))))
+          (number "8" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -3.81 180) (length 5.08)
+          (name "OUT3" (effects (font (size 1.27 1.27))))
+          (number "9" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:dac_bridge_3" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "dac_bridge_3" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "dac_bridge_3_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -5.08)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "dac_bridge_3_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -1.27 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -3.81 0) (length 5.08)
+          (name "IN3" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 1.27 180) (length 5.08)
+          (name "OUT1" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -1.27 180) (length 5.08)
+          (name "OUT2" (effects (font (size 1.27 1.27))))
+          (number "5" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -3.81 180) (length 5.08)
+          (name "OUT3" (effects (font (size 1.27 1.27))))
+          (number "6" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:dac_bridge_5" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "dac_bridge_5" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "dac_bridge_5_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -10.16)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "dac_bridge_5_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -8.89 180) (length 5.08)
+          (name "OUT5" (effects (font (size 1.27 1.27))))
+          (number "10" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -1.27 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -3.81 0) (length 5.08)
+          (name "IN3" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -6.35 0) (length 5.08)
+          (name "IN4" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -8.89 0) (length 5.08)
+          (name "IN5" (effects (font (size 1.27 1.27))))
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+    (path "/75ba2137-63de-425d-bf2b-523a9e8bd4e4"
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+    )
+    (path "/30f44d04-f731-4e5c-8d34-8926d64d0827"
+      (reference "V_A1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/5acb8fc7-962d-419a-a3ae-a866a422a053"
+      (reference "V_A2") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/949093a6-21f4-4455-b8ff-f0d1dcede852"
+      (reference "V_A3") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/2e464373-3986-414e-8e89-71b5711ba2e3"
+      (reference "V_E0n1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/3643a06a-f98c-4ddb-afd1-aef768ccad26"
+      (reference "V_E1n1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/08a8b017-d22d-45df-bff4-a6d932fccd01"
+      (reference "X1") (unit 1) (value "74LS154") (footprint "")
+    )
+    (path "/f16095f7-b542-4393-bab4-dbc7b9c81802"
+      (reference "v1") (unit 1) (value "5") (footprint "R1")
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+  )
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diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.proj b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.proj
new file mode 100644
index 000000000..fcf2410e9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.proj
@@ -0,0 +1 @@
+schematicFile 74HC154_TEST.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.raw b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.raw
new file mode 100644
index 000000000..b9f558e6b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST.raw
@@ -0,0 +1,2828 @@
+Title: kicad schematic
+Date: Sat Nov 29 21:45:33  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 47
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(v_y7n)	voltage
+	2	v(v_y9n)	voltage
+	3	v(v_y10n)	voltage
+	4	v(v_y0n)	voltage
+	5	v(v_y2n)	voltage
+	6	v(v_y1n)	voltage
+	7	v(v_y6n)	voltage
+	8	v(v_y5n)	voltage
+	9	v(v_y4n)	voltage
+	10	v(v_y3n)	voltage
+	11	v(v_y8n)	voltage
+	12	v(v_y14n)	voltage
+	13	v(v_y13n)	voltage
+	14	v(net-_v_a0-pad1_)	voltage
+	15	v(net-_v_a2-pad1_)	voltage
+	16	v(net-_v_a1-pad1_)	voltage
+	17	v(net-_v_e1n1-pad1_)	voltage
+	18	v(net-_v_a3-pad1_)	voltage
+	19	v(net-_v1-pad1_)	voltage
+	20	v(v_y11n)	voltage
+	21	v(net-_v_e0n1-pad1_)	voltage
+	22	v(v_y15n)	voltage
+	23	v(v_y12n)	voltage
+	24	i(v_e0n1)	current
+	25	i(v1)	current
+	26	i(v_a3)	current
+	27	i(v_e1n1)	current
+	28	i(v_a1)	current
+	29	i(v_a2)	current
+	30	i(v_a0)	current
+	31	i(a3)	current
+	32	i(a3)	current
+	33	i(a3)	current
+	34	i(a3)	current
+	35	i(a3)	current
+	36	i(a2)	current
+	37	i(a2)	current
+	38	i(a2)	current
+	39	i(a2)	current
+	40	i(a2)	current
+	41	i(a2)	current
+	42	i(a2)	current
+	43	i(a2)	current
+	44	i(a1)	current
+	45	i(a1)	current
+	46	i(a1)	current
+Values:
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+	-5.000000000000000e-03
+	-5.000000000000000e-03
+55		9.456000000000000e+01
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+56		9.656000000000000e+01
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+57		9.856000000000000e+01
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+58		1.000000000000000e+02
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	0.000000000000000e+00
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
+	-5.000000000000000e-03
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST_Previous_Values.xml
new file mode 100644
index 000000000..6b257fe48
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74HC154_TEST_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v_a0 name="Source type">dc<field1 name="Value">5</field1></v_a0><v_a2 name="Source type">dc<field1 name="Value">0</field1></v_a2><v_a1 name="Source type">dc<field1 name="Value">5</field1></v_a1><v_e1n1 name="Source type">dc<field1 name="Value">0</field1></v_e1n1><v_a3 name="Source type">dc<field1 name="Value">0</field1></v_a3><v1 name="Source type">5</v1><v_e0n1 name="Source type">dc<field1 name="Value">0</field1></v_e0n1></source><model><u2 name="type">dac_bridge<field1 name="Enter value for out_low (default=0.0)" /><field2 name="Enter value for out_high (default=5.0)" /><field3 name="Enter value for out_undef (default=0.5)" /><field4 name="Enter value for input load (default=1.0e-12)" /><field5 name="Enter the Rise Time (default=1.0e-9)" /><field6 name="Enter the Fall Time (default=1.0e-9)" /></u2><u1 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u1><u3 name="type">dac_bridge<field13 name="Enter value for out_low (default=0.0)" /><field14 name="Enter value for out_high (default=5.0)" /><field15 name="Enter value for out_undef (default=0.5)" /><field16 name="Enter value for input load (default=1.0e-12)" /><field17 name="Enter the Rise Time (default=1.0e-9)" /><field18 name="Enter the Fall Time (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field19 name="Enter value for in_low (default=1.0)" /><field20 name="Enter value for in_high (default=2.0)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74LS154</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.cir
new file mode 100644
index 000000000..b447a24cb
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.cir
@@ -0,0 +1,46 @@
+.title KiCad schematic
+U11 Net-_X1-Pad5_ Net-_U11-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_X1-Pad5_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad2_ Net-_U2-Pad10_ Net-_U2-Pad11_ GND Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U2-Pad17_ Net-_U2-Pad18_ Net-_U2-Pad19_ Net-_U2-Pad20_ Net-_U17-Pad1_ Net-_U14-Pad1_ Net-_U10-Pad1_ GND PORT
+U14 Net-_U14-Pad1_ Net-_X1-Pad4_ d_inverter
+U21 Net-_U2-Pad20_ Net-_U21-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_X1-Pad3_ d_inverter
+U3 Net-_U2-Pad18_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U2-Pad19_ Net-_U4-Pad2_ d_inverter
+U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_and
+U9 Net-_U9-Pad1_ Net-_U2-Pad5_ d_inverter
+X6 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_U18-Pad2_ Net-_U12-Pad1_ 5_and
+X5 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad4_ Net-_U21-Pad2_ Net-_U18-Pad2_ Net-_U9-Pad1_ 5_and
+X1 Net-_U4-Pad3_ Net-_U21-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U1-Pad1_ 5_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+X2 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad3_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_U6-Pad1_ 5_and
+U6 Net-_U6-Pad1_ Net-_U2-Pad2_ d_inverter
+U7 Net-_U7-Pad1_ Net-_U2-Pad3_ d_inverter
+U8 Net-_U8-Pad1_ Net-_U2-Pad4_ d_inverter
+X3 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad3_ Net-_U21-Pad2_ Net-_X11-Pad4_ Net-_U7-Pad1_ 5_and
+X4 Net-_U4-Pad3_ Net-_X1-Pad3_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U8-Pad1_ 5_and
+U22 Net-_U21-Pad2_ Net-_U22-Pad2_ d_inverter
+U15 Net-_X1-Pad4_ Net-_X11-Pad4_ d_inverter
+U18 Net-_X1-Pad3_ Net-_U18-Pad2_ d_inverter
+U26 Net-_U26-Pad1_ Net-_U2-Pad15_ d_inverter
+X14 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_U11-Pad2_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U26-Pad1_ 5_and
+X15 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U27-Pad1_ 5_and
+U27 Net-_U27-Pad1_ Net-_U2-Pad16_ d_inverter
+X16 Net-_U4-Pad3_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U28-Pad1_ 5_and
+U28 Net-_U28-Pad1_ Net-_U2-Pad17_ d_inverter
+X12 Net-_U4-Pad3_ Net-_X1-Pad3_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U22-Pad2_ Net-_U24-Pad1_ 5_and
+X13 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad4_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U25-Pad1_ 5_and
+U25 Net-_U25-Pad1_ Net-_U2-Pad14_ d_inverter
+U24 Net-_U24-Pad1_ Net-_U2-Pad13_ d_inverter
+X7 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_U21-Pad2_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U13-Pad1_ 5_and
+X8 Net-_U4-Pad3_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U16-Pad1_ 5_and
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U20 Net-_U20-Pad1_ Net-_U2-Pad10_ d_inverter
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter
+X10 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad3_ Net-_U11-Pad2_ Net-_U22-Pad2_ Net-_U20-Pad1_ 5_and
+X11 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad3_ Net-_X11-Pad4_ Net-_U22-Pad2_ Net-_U23-Pad1_ 5_and
+X9 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad4_ Net-_X1-Pad3_ Net-_U22-Pad2_ Net-_U19-Pad1_ 5_and
+U23 Net-_U23-Pad1_ Net-_U2-Pad11_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.cir.out
new file mode 100644
index 000000000..200270867
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.cir.out
@@ -0,0 +1,137 @@
+.title kicad schematic
+
+.include 5_and.sub
+* u11 net-_x1-pad5_ net-_u11-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_x1-pad5_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u2-pad10_ net-_u2-pad11_ gnd net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u17-pad1_ net-_u14-pad1_ net-_u10-pad1_ gnd port
+* u14 net-_u14-pad1_ net-_x1-pad4_ d_inverter
+* u21 net-_u2-pad20_ net-_u21-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_x1-pad3_ d_inverter
+* u3 net-_u2-pad18_ net-_u3-pad2_ d_inverter
+* u5 net-_u2-pad19_ net-_u4-pad2_ d_inverter
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_and
+* u9 net-_u9-pad1_ net-_u2-pad5_ d_inverter
+x6 net-_u4-pad3_ net-_x1-pad4_ net-_u21-pad2_ net-_u11-pad2_ net-_u18-pad2_ net-_u12-pad1_ 5_and
+x5 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u21-pad2_ net-_u18-pad2_ net-_u9-pad1_ 5_and
+x1 net-_u4-pad3_ net-_u21-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u1-pad1_ 5_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+x2 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_u6-pad1_ 5_and
+* u6 net-_u6-pad1_ net-_u2-pad2_ d_inverter
+* u7 net-_u7-pad1_ net-_u2-pad3_ d_inverter
+* u8 net-_u8-pad1_ net-_u2-pad4_ d_inverter
+x3 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_u21-pad2_ net-_x11-pad4_ net-_u7-pad1_ 5_and
+x4 net-_u4-pad3_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u8-pad1_ 5_and
+* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter
+* u15 net-_x1-pad4_ net-_x11-pad4_ d_inverter
+* u18 net-_x1-pad3_ net-_u18-pad2_ d_inverter
+* u26 net-_u26-pad1_ net-_u2-pad15_ d_inverter
+x14 net-_u4-pad3_ net-_x1-pad4_ net-_u11-pad2_ net-_u18-pad2_ net-_u22-pad2_ net-_u26-pad1_ 5_and
+x15 net-_u4-pad3_ net-_x1-pad5_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u27-pad1_ 5_and
+* u27 net-_u27-pad1_ net-_u2-pad16_ d_inverter
+x16 net-_u4-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u28-pad1_ 5_and
+* u28 net-_u28-pad1_ net-_u2-pad17_ d_inverter
+x12 net-_u4-pad3_ net-_x1-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u22-pad2_ net-_u24-pad1_ 5_and
+x13 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u25-pad1_ 5_and
+* u25 net-_u25-pad1_ net-_u2-pad14_ d_inverter
+* u24 net-_u24-pad1_ net-_u2-pad13_ d_inverter
+x7 net-_u4-pad3_ net-_x1-pad5_ net-_u21-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u13-pad1_ 5_and
+x8 net-_u4-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u16-pad1_ 5_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u2-pad10_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+x10 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u11-pad2_ net-_u22-pad2_ net-_u20-pad1_ 5_and
+x11 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_x11-pad4_ net-_u22-pad2_ net-_u23-pad1_ 5_and
+x9 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_x1-pad3_ net-_u22-pad2_ net-_u19-pad1_ 5_and
+* u23 net-_u23-pad1_ net-_u2-pad11_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+a1 net-_x1-pad5_ net-_u11-pad2_ u11
+a2 net-_u10-pad1_ net-_x1-pad5_ u10
+a3 net-_u14-pad1_ net-_x1-pad4_ u14
+a4 net-_u2-pad20_ net-_u21-pad2_ u21
+a5 net-_u17-pad1_ net-_x1-pad3_ u17
+a6 net-_u2-pad18_ net-_u3-pad2_ u3
+a7 net-_u2-pad19_ net-_u4-pad2_ u5
+a8 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a9 net-_u9-pad1_ net-_u2-pad5_ u9
+a10 net-_u1-pad1_ net-_u1-pad2_ u1
+a11 net-_u6-pad1_ net-_u2-pad2_ u6
+a12 net-_u7-pad1_ net-_u2-pad3_ u7
+a13 net-_u8-pad1_ net-_u2-pad4_ u8
+a14 net-_u21-pad2_ net-_u22-pad2_ u22
+a15 net-_x1-pad4_ net-_x11-pad4_ u15
+a16 net-_x1-pad3_ net-_u18-pad2_ u18
+a17 net-_u26-pad1_ net-_u2-pad15_ u26
+a18 net-_u27-pad1_ net-_u2-pad16_ u27
+a19 net-_u28-pad1_ net-_u2-pad17_ u28
+a20 net-_u25-pad1_ net-_u2-pad14_ u25
+a21 net-_u24-pad1_ net-_u2-pad13_ u24
+a22 net-_u12-pad1_ net-_u12-pad2_ u12
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u20-pad1_ net-_u2-pad10_ u20
+a25 net-_u19-pad1_ net-_u19-pad2_ u19
+a26 net-_u23-pad1_ net-_u2-pad11_ u23
+a27 net-_u16-pad1_ net-_u16-pad2_ u16
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.kicad_sch b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.kicad_sch
new file mode 100644
index 000000000..6ad7f9bd9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.kicad_sch
@@ -0,0 +1,3660 @@
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+      (reference "U2") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/32efc54c-12e5-412b-82b7-0463e9eeec3f"
+      (reference "U2") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/b54b7632-753a-4385-b9b4-fe54527a4c20"
+      (reference "U2") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/fe438628-712d-4a79-8cfa-dc4042645deb"
+      (reference "U2") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/cbf07ddb-65fc-42e1-a940-c035fe5911e6"
+      (reference "U2") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/03252d6f-6fe3-4951-b30d-6c6e80297972"
+      (reference "U2") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/71abea7c-cc69-4f4b-b3a9-afef6cacf3e0"
+      (reference "U2") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/36c156c8-c075-40a0-b0bb-fb014f09859c"
+      (reference "U2") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/128e6bc6-b749-4481-9af0-49ecdff1a7e6"
+      (reference "U2") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/19098f9f-2811-422d-a749-c8d196ef6b64"
+      (reference "U2") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/9e6af913-4156-4ef3-82de-ee0c8a7a505a"
+      (reference "U2") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/0f80092a-7a84-4e6a-8545-8f5f7437eaf2"
+      (reference "U2") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/36665f2e-85de-427c-ba41-97986be307e3"
+      (reference "U2") (unit 17) (value "PORT") (footprint "")
+    )
+    (path "/a4503e44-6fce-4f09-b142-5fa5cd6950ba"
+      (reference "U2") (unit 18) (value "PORT") (footprint "")
+    )
+    (path "/0e053a5a-79fd-4ce3-8106-1f142adc70be"
+      (reference "U2") (unit 19) (value "PORT") (footprint "")
+    )
+    (path "/9321a2ad-04e0-47d1-9542-bb9d06ab7f13"
+      (reference "U2") (unit 20) (value "PORT") (footprint "")
+    )
+    (path "/be3e3dba-e215-4ea0-a6da-3d0a6096aeed"
+      (reference "U2") (unit 21) (value "PORT") (footprint "")
+    )
+    (path "/445d2190-b6a0-4419-b935-29d5e13462f6"
+      (reference "U2") (unit 22) (value "PORT") (footprint "")
+    )
+    (path "/64f8c99c-d7e0-4268-a447-9aa4729c284f"
+      (reference "U2") (unit 23) (value "PORT") (footprint "")
+    )
+    (path "/2e39d81a-7ef7-4fd1-90f5-b244b4d7a557"
+      (reference "U2") (unit 24) (value "PORT") (footprint "")
+    )
+    (path "/3f6e31b4-2296-46a4-b6d9-3561bc63c9c1"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9ef067bb-b49e-440d-9596-ac97f65bd341"
+      (reference "U4") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/16eda697-bc15-4dd0-9099-9a916e9547c5"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/bb6dfb37-1e8e-4872-b421-317f09379713"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1c6004d5-9bdb-4d49-b4de-992385c8ca82"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/4422caff-9166-4403-8a2d-8eadbe8797c5"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/4499e820-8541-4c87-86fb-b6ee39d744c7"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/0bd7dc6e-d887-492c-b1be-5ac12f8dfa47"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3f217173-13c7-4fc1-88e4-ef54a4f36b87"
+      (reference "U11") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/4a503311-b5da-4676-9a7b-c115f36eae13"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6fc5ca11-33f7-4da3-a1d5-8cb489d7b68c"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c6ad19a6-47f4-4da0-bdd4-d06f68f51280"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9889b8d1-9bbe-4d8d-93d8-be0be6640d27"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/b21f7c54-d086-4857-a536-b8c88bdfdf25"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5ecd1eb8-eaf5-4f83-bef4-d04031a0d2a7"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f9f49f3a-5198-4671-b5fc-9f69ab5b95b6"
+      (reference "U18") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/12dce332-dd48-4fc4-b3c0-533ceec5b9ed"
+      (reference "U19") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/af487c1e-146a-41fd-aa2f-cff32d28f075"
+      (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/0ee44fe5-dc17-4d06-a42d-eb273d2d5ed1"
+      (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3ff42c3b-f79c-4f1f-b4dd-c938331b892c"
+      (reference "U22") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1f212231-ba7b-478e-85c3-b8094c07c45e"
+      (reference "U23") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6285dcdf-b865-40d3-8f90-a2fba9083383"
+      (reference "U24") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/80befffb-4ecc-4698-8099-a9ac268c2546"
+      (reference "U25") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/faa42990-0143-4163-8d64-b9af777a2cd2"
+      (reference "U26") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/376cbe51-1573-41af-953a-c7371fb1681d"
+      (reference "U27") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/178f8765-a5ce-46cb-8bcd-34eb1df74b59"
+      (reference "U28") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6f5365b6-e565-4b85-99e0-138fd40dc311"
+      (reference "X1") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/cef3355b-8bd0-4873-9435-77a36eef0690"
+      (reference "X2") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/ec346ea0-d69a-4d56-9a7d-95b1b2275538"
+      (reference "X3") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/20cf08ea-b100-4ac3-a619-22c906f477e6"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/64f208a5-c1d1-4b3f-a41f-0b624f780098"
+      (reference "X5") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/881f6348-2b83-42a6-adcb-c7fccc7ecb7f"
+      (reference "X6") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/0374ec46-9712-4b19-81c9-267f1f8aab82"
+      (reference "X7") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/31c39bfc-b198-45af-b380-220bd9e3ac81"
+      (reference "X8") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/1789ec57-1b50-46e5-8c53-a8cd3420ee17"
+      (reference "X9") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/c9566a68-5686-429d-ba34-c23a6f24d890"
+      (reference "X10") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/b024f3d2-a346-4696-97bb-4f785fe2ae86"
+      (reference "X11") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/312ef13e-3aee-40f7-b65d-f53ef02d77b0"
+      (reference "X12") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/3de2ed1d-f7a5-443b-847d-cdb4fbbcf718"
+      (reference "X13") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/8ecc4f08-9a53-433e-a215-5c2734dc1643"
+      (reference "X14") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/cf7c0078-f48c-430a-b086-e166b7a686ed"
+      (reference "X15") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/105a6b2c-c1bd-4133-95db-51e4ae1e42ae"
+      (reference "X16") (unit 1) (value "5_and") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.sub b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.sub
new file mode 100644
index 000000000..3d8cde22d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154.sub
@@ -0,0 +1,131 @@
+* Subcircuit 74LS154
+.subckt 74LS154 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u2-pad10_ net-_u2-pad11_ gnd net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u17-pad1_ net-_u14-pad1_ net-_u10-pad1_ gnd 
+.title kicad schematic
+.include 5_and.sub
+* u11 net-_x1-pad5_ net-_u11-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_x1-pad5_ d_inverter
+* u14 net-_u14-pad1_ net-_x1-pad4_ d_inverter
+* u21 net-_u2-pad20_ net-_u21-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_x1-pad3_ d_inverter
+* u3 net-_u2-pad18_ net-_u3-pad2_ d_inverter
+* u5 net-_u2-pad19_ net-_u4-pad2_ d_inverter
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_and
+* u9 net-_u9-pad1_ net-_u2-pad5_ d_inverter
+x6 net-_u4-pad3_ net-_x1-pad4_ net-_u21-pad2_ net-_u11-pad2_ net-_u18-pad2_ net-_u12-pad1_ 5_and
+x5 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u21-pad2_ net-_u18-pad2_ net-_u9-pad1_ 5_and
+x1 net-_u4-pad3_ net-_u21-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u1-pad1_ 5_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+x2 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_u6-pad1_ 5_and
+* u6 net-_u6-pad1_ net-_u2-pad2_ d_inverter
+* u7 net-_u7-pad1_ net-_u2-pad3_ d_inverter
+* u8 net-_u8-pad1_ net-_u2-pad4_ d_inverter
+x3 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_u21-pad2_ net-_x11-pad4_ net-_u7-pad1_ 5_and
+x4 net-_u4-pad3_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u8-pad1_ 5_and
+* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter
+* u15 net-_x1-pad4_ net-_x11-pad4_ d_inverter
+* u18 net-_x1-pad3_ net-_u18-pad2_ d_inverter
+* u26 net-_u26-pad1_ net-_u2-pad15_ d_inverter
+x14 net-_u4-pad3_ net-_x1-pad4_ net-_u11-pad2_ net-_u18-pad2_ net-_u22-pad2_ net-_u26-pad1_ 5_and
+x15 net-_u4-pad3_ net-_x1-pad5_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u27-pad1_ 5_and
+* u27 net-_u27-pad1_ net-_u2-pad16_ d_inverter
+x16 net-_u4-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u28-pad1_ 5_and
+* u28 net-_u28-pad1_ net-_u2-pad17_ d_inverter
+x12 net-_u4-pad3_ net-_x1-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u22-pad2_ net-_u24-pad1_ 5_and
+x13 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u25-pad1_ 5_and
+* u25 net-_u25-pad1_ net-_u2-pad14_ d_inverter
+* u24 net-_u24-pad1_ net-_u2-pad13_ d_inverter
+x7 net-_u4-pad3_ net-_x1-pad5_ net-_u21-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u13-pad1_ 5_and
+x8 net-_u4-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u16-pad1_ 5_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u2-pad10_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+x10 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u11-pad2_ net-_u22-pad2_ net-_u20-pad1_ 5_and
+x11 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_x11-pad4_ net-_u22-pad2_ net-_u23-pad1_ 5_and
+x9 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_x1-pad3_ net-_u22-pad2_ net-_u19-pad1_ 5_and
+* u23 net-_u23-pad1_ net-_u2-pad11_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+a1 net-_x1-pad5_ net-_u11-pad2_ u11
+a2 net-_u10-pad1_ net-_x1-pad5_ u10
+a3 net-_u14-pad1_ net-_x1-pad4_ u14
+a4 net-_u2-pad20_ net-_u21-pad2_ u21
+a5 net-_u17-pad1_ net-_x1-pad3_ u17
+a6 net-_u2-pad18_ net-_u3-pad2_ u3
+a7 net-_u2-pad19_ net-_u4-pad2_ u5
+a8 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a9 net-_u9-pad1_ net-_u2-pad5_ u9
+a10 net-_u1-pad1_ net-_u1-pad2_ u1
+a11 net-_u6-pad1_ net-_u2-pad2_ u6
+a12 net-_u7-pad1_ net-_u2-pad3_ u7
+a13 net-_u8-pad1_ net-_u2-pad4_ u8
+a14 net-_u21-pad2_ net-_u22-pad2_ u22
+a15 net-_x1-pad4_ net-_x11-pad4_ u15
+a16 net-_x1-pad3_ net-_u18-pad2_ u18
+a17 net-_u26-pad1_ net-_u2-pad15_ u26
+a18 net-_u27-pad1_ net-_u2-pad16_ u27
+a19 net-_u28-pad1_ net-_u2-pad17_ u28
+a20 net-_u25-pad1_ net-_u2-pad14_ u25
+a21 net-_u24-pad1_ net-_u2-pad13_ u24
+a22 net-_u12-pad1_ net-_u12-pad2_ u12
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u20-pad1_ net-_u2-pad10_ u20
+a25 net-_u19-pad1_ net-_u19-pad2_ u19
+a26 net-_u23-pad1_ net-_u2-pad11_ u23
+a27 net-_u16-pad1_ net-_u16-pad2_ u16
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74LS154
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154_Previous_Values.xml
new file mode 100644
index 000000000..a9eb5b618
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/74LS154_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u11 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u14><u21 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u17><u4 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u1 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u1><u6 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u8><u22 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u18 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u18><u15 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u26 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u28><u24 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u13 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u12><u20 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u20><u19 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u23><u16 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u16></model><devicemodel /><subcircuit><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x14><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x14><x15><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x15><x16><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x16><x12><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x12><x13><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x13><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x10><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x11><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x9></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/_autosave-74LS154.sch b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/_autosave-74LS154.sch
new file mode 100644
index 000000000..ab3ad1a54
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/_autosave-74LS154.sch
@@ -0,0 +1,1287 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 2975 6250
+Connection ~ 3650 6250
+Connection ~ 3750 8200
+Connection ~ 3850 7975
+Connection ~ 3950 7725
+Connection ~ 4775 6250
+Connection ~ 4975 7975
+Connection ~ 5075 7725
+Connection ~ 5925 6250
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+Connection ~ 6125 7725
+Connection ~ 6225 7500
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+Connection ~ 7575 7725
+Connection ~ 8550 6250
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+Connection ~ 8850 7500
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+Connection ~ 11425 7250
+Connection ~ 11525 7000
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+Connection ~ 12550 7000
+Connection ~ 12600 8450
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+Wire Wire Line
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+$Comp
+L eSim_Power:eSim_GND #PWR01
+U 1 1 00000000
+P 18925 3175
+F 0 "#PWR01" H 18925 2925 50  0001 C CNN
+F 1 "eSim_GND" H 18925 3000 50  0000 C CNN
+F 2 "" H 18925 3175 50  0001 C CNN
+F 3 "" H 18925 3175 50  0001 C CNN
+	1    18925 3175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Power:eSim_GND #PWR02
+U 1 1 00000000
+P 18975 3975
+F 0 "#PWR02" H 18975 3725 50  0001 C CNN
+F 1 "eSim_GND" H 18975 3800 50  0000 C CNN
+F 2 "" H 18975 3975 50  0001 C CNN
+F 3 "" H 18975 3975 50  0001 C CNN
+	1    18975 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 1 1 00000000
+P 2550 11500
+F 0 "U2" V 2600 11400 30  0000 R CNN
+F 1 "PORT" V 2500 11400 30  0000 R CNN
+F 2 "" H 2550 11500 60  0000 C CNN
+F 3 "" H 2550 11500 60  0000 C CNN
+	1    2550 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 18 1 00000000
+P 2925 2900
+F 0 "U2" H 2950 3100 30  0000 C CNN
+F 1 "PORT" H 2950 3000 30  0000 C CNN
+F 2 "" H 2925 2900 60  0000 C CNN
+F 3 "" H 2925 2900 60  0000 C CNN
+	18   2925 2900
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 19 1 00000000
+P 3050 3325
+F 0 "U2" H 3075 3525 30  0000 C CNN
+F 1 "PORT" H 3075 3425 30  0000 C CNN
+F 2 "" H 3050 3325 60  0000 C CNN
+F 3 "" H 3050 3325 60  0000 C CNN
+	19   3050 3325
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 2 1 00000000
+P 3850 11500
+F 0 "U2" V 3900 11400 30  0000 R CNN
+F 1 "PORT" V 3800 11400 30  0000 R CNN
+F 2 "" H 3850 11500 60  0000 C CNN
+F 3 "" H 3850 11500 60  0000 C CNN
+	2    3850 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 3 1 00000000
+P 4975 11475
+F 0 "U2" V 5025 11400 30  0000 R CNN
+F 1 "PORT" V 4925 11400 30  0000 R CNN
+F 2 "" H 4975 11475 60  0000 C CNN
+F 3 "" H 4975 11475 60  0000 C CNN
+	3    4975 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 4 1 00000000
+P 6125 11475
+F 0 "U2" V 6175 11375 30  0000 R CNN
+F 1 "PORT" V 6075 11375 30  0000 R CNN
+F 2 "" H 6125 11475 60  0000 C CNN
+F 3 "" H 6125 11475 60  0000 C CNN
+	4    6125 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 5 1 00000000
+P 7475 11450
+F 0 "U2" V 7525 11350 30  0000 R CNN
+F 1 "PORT" V 7425 11350 30  0000 R CNN
+F 2 "" H 7475 11450 60  0000 C CNN
+F 3 "" H 7475 11450 60  0000 C CNN
+	5    7475 11450
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 23 1 00000000
+P 7500 2500
+F 0 "U2" V 7500 2400 30  0000 R CNN
+F 1 "PORT" V 7600 2400 30  0000 R CNN
+F 2 "" H 7500 2500 60  0000 C CNN
+F 3 "" H 7500 2500 60  0000 C CNN
+	23   7500 2500
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 6 1 00000000
+P 8750 11475
+F 0 "U2" V 8800 11375 30  0000 R CNN
+F 1 "PORT" V 8700 11375 30  0000 R CNN
+F 2 "" H 8750 11475 60  0000 C CNN
+F 3 "" H 8750 11475 60  0000 C CNN
+	6    8750 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 7 1 00000000
+P 9975 11475
+F 0 "U2" V 10025 11375 30  0000 R CNN
+F 1 "PORT" V 9925 11375 30  0000 R CNN
+F 2 "" H 9975 11475 60  0000 C CNN
+F 3 "" H 9975 11475 60  0000 C CNN
+	7    9975 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 22 1 00000000
+P 10000 2550
+F 0 "U2" V 10000 2475 30  0000 R CNN
+F 1 "PORT" V 10100 2475 30  0000 R CNN
+F 2 "" H 10000 2550 60  0000 C CNN
+F 3 "" H 10000 2550 60  0000 C CNN
+	22   10000 2550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 8 1 00000000
+P 11325 11500
+F 0 "U2" V 11375 11425 30  0000 R CNN
+F 1 "PORT" V 11275 11425 30  0000 R CNN
+F 2 "" H 11325 11500 60  0000 C CNN
+F 3 "" H 11325 11500 60  0000 C CNN
+	8    11325 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 21 1 00000000
+P 12550 2525
+F 0 "U2" V 12550 2450 30  0000 R CNN
+F 1 "PORT" V 12650 2450 30  0000 R CNN
+F 2 "" H 12550 2525 60  0000 C CNN
+F 3 "" H 12550 2525 60  0000 C CNN
+	21   12550 2525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 9 1 00000000
+P 12700 11500
+F 0 "U2" V 12750 11425 30  0000 R CNN
+F 1 "PORT" V 12650 11425 30  0000 R CNN
+F 2 "" H 12700 11500 60  0000 C CNN
+F 3 "" H 12700 11500 60  0000 C CNN
+	9    12700 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 10 1 00000000
+P 14150 11500
+F 0 "U2" V 14200 11400 30  0000 R CNN
+F 1 "PORT" V 14100 11400 30  0000 R CNN
+F 2 "" H 14150 11500 60  0000 C CNN
+F 3 "" H 14150 11500 60  0000 C CNN
+	10   14150 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 20 1 00000000
+P 15525 2525
+F 0 "U2" V 15525 2425 30  0000 R CNN
+F 1 "PORT" V 15625 2425 30  0000 R CNN
+F 2 "" H 15525 2525 60  0000 C CNN
+F 3 "" H 15525 2525 60  0000 C CNN
+	20   15525 2525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 11 1 00000000
+P 15550 11525
+F 0 "U2" V 15600 11425 30  0000 R CNN
+F 1 "PORT" V 15500 11425 30  0000 R CNN
+F 2 "" H 15550 11525 60  0000 C CNN
+F 3 "" H 15550 11525 60  0000 C CNN
+	11   15550 11525
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 13 1 00000000
+P 16975 11500
+F 0 "U2" V 17025 11425 30  0000 R CNN
+F 1 "PORT" V 16925 11425 30  0000 R CNN
+F 2 "" H 16975 11500 60  0000 C CNN
+F 3 "" H 16975 11500 60  0000 C CNN
+	13   16975 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 14 1 00000000
+P 18225 11500
+F 0 "U2" V 18275 11400 30  0000 R CNN
+F 1 "PORT" V 18175 11400 30  0000 R CNN
+F 2 "" H 18225 11500 60  0000 C CNN
+F 3 "" H 18225 11500 60  0000 C CNN
+	14   18225 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 24 1 00000000
+P 18250 3125
+F 0 "U2" H 18275 3300 30  0000 C CNN
+F 1 "PORT" H 18275 3200 30  0000 C CNN
+F 2 "" H 18250 3125 60  0000 C CNN
+F 3 "" H 18250 3125 60  0000 C CNN
+	24   18250 3125
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 12 1 00000000
+P 18250 3950
+F 0 "U2" H 18275 4125 30  0000 C CNN
+F 1 "PORT" H 18275 4025 30  0000 C CNN
+F 2 "" H 18250 3950 60  0000 C CNN
+F 3 "" H 18250 3950 60  0000 C CNN
+	12   18250 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 15 1 00000000
+P 19625 11475
+F 0 "U2" V 19675 11400 30  0000 R CNN
+F 1 "PORT" V 19575 11400 30  0000 R CNN
+F 2 "" H 19625 11475 60  0000 C CNN
+F 3 "" H 19625 11475 60  0000 C CNN
+	15   19625 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 16 1 00000000
+P 21025 11475
+F 0 "U2" V 21075 11375 30  0000 R CNN
+F 1 "PORT" V 20975 11375 30  0000 R CNN
+F 2 "" H 21025 11475 60  0000 C CNN
+F 3 "" H 21025 11475 60  0000 C CNN
+	16   21025 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 17 1 00000000
+P 22300 11475
+F 0 "U2" V 22350 11375 30  0000 R CNN
+F 1 "PORT" V 22250 11375 30  0000 R CNN
+F 2 "" H 22300 11475 60  0000 C CNN
+F 3 "" H 22300 11475 60  0000 C CNN
+	17   22300 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U1
+U 1 1 00000000
+P 2550 10625
+F 0 "U1" V 2500 10525 60  0000 R CNN
+F 1 "d_inverter" V 2650 10525 60  0000 R CNN
+F 2 "" H 2600 10575 60  0000 C CNN
+F 3 "" H 2600 10575 60  0000 C CNN
+	1    2550 10625
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U3
+U 1 1 00000000
+P 2925 4250
+F 0 "U3" V 2925 4475 60  0000 R CNN
+F 1 "d_inverter" V 3025 4725 60  0000 R CNN
+F 2 "" H 2975 4200 60  0000 C CNN
+F 3 "" H 2975 4200 60  0000 C CNN
+	1    2925 4250
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U5
+U 1 1 00000000
+P 3050 4250
+F 0 "U5" V 2950 4125 60  0000 R CNN
+F 1 "d_inverter" V 2825 4175 60  0000 R CNN
+F 2 "" H 3100 4200 60  0000 C CNN
+F 3 "" H 3100 4200 60  0000 C CNN
+	1    3050 4250
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U6
+U 1 1 00000000
+P 3850 10575
+F 0 "U6" V 3800 10475 60  0000 R CNN
+F 1 "d_inverter" V 3950 10475 60  0000 R CNN
+F 2 "" H 3900 10525 60  0000 C CNN
+F 3 "" H 3900 10525 60  0000 C CNN
+	1    3850 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U7
+U 1 1 00000000
+P 4975 10575
+F 0 "U7" V 4925 10500 60  0000 R CNN
+F 1 "d_inverter" V 5075 10500 60  0000 R CNN
+F 2 "" H 5025 10525 60  0000 C CNN
+F 3 "" H 5025 10525 60  0000 C CNN
+	1    4975 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U8
+U 1 1 00000000
+P 6125 10550
+F 0 "U8" V 6075 10475 60  0000 R CNN
+F 1 "d_inverter" V 6225 10475 60  0000 R CNN
+F 2 "" H 6175 10500 60  0000 C CNN
+F 3 "" H 6175 10500 60  0000 C CNN
+	1    6125 10550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U9
+U 1 1 00000000
+P 7475 10525
+F 0 "U9" V 7425 10450 60  0000 R CNN
+F 1 "d_inverter" V 7575 10450 60  0000 R CNN
+F 2 "" H 7525 10475 60  0000 C CNN
+F 3 "" H 7525 10475 60  0000 C CNN
+	1    7475 10525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U10
+U 1 1 00000000
+P 7500 3775
+F 0 "U10" V 7450 3675 60  0000 R CNN
+F 1 "d_inverter" V 7600 3675 60  0000 R CNN
+F 2 "" H 7550 3725 60  0000 C CNN
+F 3 "" H 7550 3725 60  0000 C CNN
+	1    7500 3775
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U11
+U 1 1 00000000
+P 7500 5000
+F 0 "U11" V 7450 4900 60  0000 R CNN
+F 1 "d_inverter" V 7600 4900 60  0000 R CNN
+F 2 "" H 7550 4950 60  0000 C CNN
+F 3 "" H 7550 4950 60  0000 C CNN
+	1    7500 5000
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U12
+U 1 1 00000000
+P 8750 10575
+F 0 "U12" V 8700 10475 60  0000 R CNN
+F 1 "d_inverter" V 8850 10475 60  0000 R CNN
+F 2 "" H 8800 10525 60  0000 C CNN
+F 3 "" H 8800 10525 60  0000 C CNN
+	1    8750 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U13
+U 1 1 00000000
+P 9975 10550
+F 0 "U13" V 9925 10450 60  0000 R CNN
+F 1 "d_inverter" V 10075 10450 60  0000 R CNN
+F 2 "" H 10025 10500 60  0000 C CNN
+F 3 "" H 10025 10500 60  0000 C CNN
+	1    9975 10550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 10000 3825
+F 0 "U14" V 9950 3725 60  0000 R CNN
+F 1 "d_inverter" V 10100 3725 60  0000 R CNN
+F 2 "" H 10050 3775 60  0000 C CNN
+F 3 "" H 10050 3775 60  0000 C CNN
+	1    10000 3825
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U15
+U 1 1 00000000
+P 10000 4925
+F 0 "U15" V 9950 4825 60  0000 R CNN
+F 1 "d_inverter" V 10100 4825 60  0000 R CNN
+F 2 "" H 10050 4875 60  0000 C CNN
+F 3 "" H 10050 4875 60  0000 C CNN
+	1    10000 4925
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U16
+U 1 1 00000000
+P 11325 10625
+F 0 "U16" V 11275 10550 60  0000 R CNN
+F 1 "d_inverter" V 11425 10550 60  0000 R CNN
+F 2 "" H 11375 10575 60  0000 C CNN
+F 3 "" H 11375 10575 60  0000 C CNN
+	1    11325 10625
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U17
+U 1 1 00000000
+P 12550 3775
+F 0 "U17" V 12500 3675 60  0000 R CNN
+F 1 "d_inverter" V 12650 3675 60  0000 R CNN
+F 2 "" H 12600 3725 60  0000 C CNN
+F 3 "" H 12600 3725 60  0000 C CNN
+	1    12550 3775
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U18
+U 1 1 00000000
+P 12550 4875
+F 0 "U18" V 12500 4775 60  0000 R CNN
+F 1 "d_inverter" V 12650 4775 60  0000 R CNN
+F 2 "" H 12600 4825 60  0000 C CNN
+F 3 "" H 12600 4825 60  0000 C CNN
+	1    12550 4875
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U19
+U 1 1 00000000
+P 12700 10600
+F 0 "U19" V 12650 10500 60  0000 R CNN
+F 1 "d_inverter" V 12800 10500 60  0000 R CNN
+F 2 "" H 12750 10550 60  0000 C CNN
+F 3 "" H 12750 10550 60  0000 C CNN
+	1    12700 10600
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U20
+U 1 1 00000000
+P 14150 10525
+F 0 "U20" V 14100 10425 60  0000 R CNN
+F 1 "d_inverter" V 14250 10425 60  0000 R CNN
+F 2 "" H 14200 10475 60  0000 C CNN
+F 3 "" H 14200 10475 60  0000 C CNN
+	1    14150 10525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U21
+U 1 1 00000000
+P 15525 3725
+F 0 "U21" V 15475 3650 60  0000 R CNN
+F 1 "d_inverter" V 15625 3650 60  0000 R CNN
+F 2 "" H 15575 3675 60  0000 C CNN
+F 3 "" H 15575 3675 60  0000 C CNN
+	1    15525 3725
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U22
+U 1 1 00000000
+P 15525 4875
+F 0 "U22" V 15475 4775 60  0000 R CNN
+F 1 "d_inverter" V 15625 4775 60  0000 R CNN
+F 2 "" H 15575 4825 60  0000 C CNN
+F 3 "" H 15575 4825 60  0000 C CNN
+	1    15525 4875
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U23
+U 1 1 00000000
+P 15550 10550
+F 0 "U23" V 15500 10450 60  0000 R CNN
+F 1 "d_inverter" V 15650 10450 60  0000 R CNN
+F 2 "" H 15600 10500 60  0000 C CNN
+F 3 "" H 15600 10500 60  0000 C CNN
+	1    15550 10550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U24
+U 1 1 00000000
+P 16975 10575
+F 0 "U24" V 16925 10475 60  0000 R CNN
+F 1 "d_inverter" V 17075 10475 60  0000 R CNN
+F 2 "" H 17025 10525 60  0000 C CNN
+F 3 "" H 17025 10525 60  0000 C CNN
+	1    16975 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U25
+U 1 1 00000000
+P 18225 10600
+F 0 "U25" V 18175 10500 60  0000 R CNN
+F 1 "d_inverter" V 18325 10500 60  0000 R CNN
+F 2 "" H 18275 10550 60  0000 C CNN
+F 3 "" H 18275 10550 60  0000 C CNN
+	1    18225 10600
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U26
+U 1 1 00000000
+P 19625 10500
+F 0 "U26" V 19575 10425 60  0000 R CNN
+F 1 "d_inverter" V 19725 10425 60  0000 R CNN
+F 2 "" H 19675 10450 60  0000 C CNN
+F 3 "" H 19675 10450 60  0000 C CNN
+	1    19625 10500
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U27
+U 1 1 00000000
+P 21025 10500
+F 0 "U27" V 20975 10425 60  0000 R CNN
+F 1 "d_inverter" V 21125 10425 60  0000 R CNN
+F 2 "" H 21075 10450 60  0000 C CNN
+F 3 "" H 21075 10450 60  0000 C CNN
+	1    21025 10500
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U28
+U 1 1 00000000
+P 22300 10525
+F 0 "U28" V 22250 10425 60  0000 R CNN
+F 1 "d_inverter" V 22400 10425 60  0000 R CNN
+F 2 "" H 22350 10475 60  0000 C CNN
+F 3 "" H 22350 10475 60  0000 C CNN
+	1    22300 10525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_and U4
+U 1 1 00000000
+P 3025 5300
+F 0 "U4" V 2975 5225 60  0000 R CNN
+F 1 "d_and" V 3125 5225 60  0000 R CNN
+F 2 "" H 3025 5300 60  0000 C CNN
+F 3 "" H 3025 5300 60  0000 C CNN
+	1    3025 5300
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X1
+U 1 1 00000000
+P 2550 9475
+F 0 "X1" V 2552 9200 60  0000 R CNN
+F 1 "5_and" V 2702 9200 60  0000 R CNN
+F 2 "" H 2550 9475 60  0000 C CNN
+F 3 "" H 2550 9475 60  0000 C CNN
+	1    2550 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X2
+U 1 1 00000000
+P 3850 9475
+F 0 "X2" V 3852 9175 60  0000 R CNN
+F 1 "5_and" V 4002 9175 60  0000 R CNN
+F 2 "" H 3850 9475 60  0000 C CNN
+F 3 "" H 3850 9475 60  0000 C CNN
+	1    3850 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X3
+U 1 1 00000000
+P 4975 9475
+F 0 "X3" V 4977 9200 60  0000 R CNN
+F 1 "5_and" V 5127 9200 60  0000 R CNN
+F 2 "" H 4975 9475 60  0000 C CNN
+F 3 "" H 4975 9475 60  0000 C CNN
+	1    4975 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X4
+U 1 1 00000000
+P 6125 9475
+F 0 "X4" V 6127 9200 60  0000 R CNN
+F 1 "5_and" V 6277 9200 60  0000 R CNN
+F 2 "" H 6125 9475 60  0000 C CNN
+F 3 "" H 6125 9475 60  0000 C CNN
+	1    6125 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X5
+U 1 1 00000000
+P 7475 9475
+F 0 "X5" V 7477 9200 60  0000 R CNN
+F 1 "5_and" V 7627 9200 60  0000 R CNN
+F 2 "" H 7475 9475 60  0000 C CNN
+F 3 "" H 7475 9475 60  0000 C CNN
+	1    7475 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X6
+U 1 1 00000000
+P 8750 9450
+F 0 "X6" V 8752 9175 60  0000 R CNN
+F 1 "5_and" V 8902 9175 60  0000 R CNN
+F 2 "" H 8750 9450 60  0000 C CNN
+F 3 "" H 8750 9450 60  0000 C CNN
+	1    8750 9450
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X7
+U 1 1 00000000
+P 9975 9450
+F 0 "X7" V 9977 9150 60  0000 R CNN
+F 1 "5_and" V 10127 9150 60  0000 R CNN
+F 2 "" H 9975 9450 60  0000 C CNN
+F 3 "" H 9975 9450 60  0000 C CNN
+	1    9975 9450
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X8
+U 1 1 00000000
+P 11325 9475
+F 0 "X8" V 11327 9200 60  0000 R CNN
+F 1 "5_and" V 11477 9200 60  0000 R CNN
+F 2 "" H 11325 9475 60  0000 C CNN
+F 3 "" H 11325 9475 60  0000 C CNN
+	1    11325 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X9
+U 1 1 00000000
+P 12700 9475
+F 0 "X9" V 12702 9175 60  0000 R CNN
+F 1 "5_and" V 12852 9175 60  0000 R CNN
+F 2 "" H 12700 9475 60  0000 C CNN
+F 3 "" H 12700 9475 60  0000 C CNN
+	1    12700 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X10
+U 1 1 00000000
+P 14150 9475
+F 0 "X10" V 14152 9200 60  0000 R CNN
+F 1 "5_and" V 14302 9200 60  0000 R CNN
+F 2 "" H 14150 9475 60  0000 C CNN
+F 3 "" H 14150 9475 60  0000 C CNN
+	1    14150 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X11
+U 1 1 00000000
+P 15550 9475
+F 0 "X11" V 15552 9200 60  0000 R CNN
+F 1 "5_and" V 15702 9200 60  0000 R CNN
+F 2 "" H 15550 9475 60  0000 C CNN
+F 3 "" H 15550 9475 60  0000 C CNN
+	1    15550 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X12
+U 1 1 00000000
+P 16975 9475
+F 0 "X12" V 16977 9175 60  0000 R CNN
+F 1 "5_and" V 17127 9175 60  0000 R CNN
+F 2 "" H 16975 9475 60  0000 C CNN
+F 3 "" H 16975 9475 60  0000 C CNN
+	1    16975 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X13
+U 1 1 00000000
+P 18225 9450
+F 0 "X13" V 18227 9150 60  0000 R CNN
+F 1 "5_and" V 18377 9150 60  0000 R CNN
+F 2 "" H 18225 9450 60  0000 C CNN
+F 3 "" H 18225 9450 60  0000 C CNN
+	1    18225 9450
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X14
+U 1 1 00000000
+P 19625 9425
+F 0 "X14" V 19627 9125 60  0000 R CNN
+F 1 "5_and" V 19777 9125 60  0000 R CNN
+F 2 "" H 19625 9425 60  0000 C CNN
+F 3 "" H 19625 9425 60  0000 C CNN
+	1    19625 9425
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X15
+U 1 1 00000000
+P 21025 9425
+F 0 "X15" V 21027 9125 60  0000 R CNN
+F 1 "5_and" V 21177 9125 60  0000 R CNN
+F 2 "" H 21025 9425 60  0000 C CNN
+F 3 "" H 21025 9425 60  0000 C CNN
+	1    21025 9425
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X16
+U 1 1 00000000
+P 22300 9450
+F 0 "X16" V 22302 9175 60  0000 R CNN
+F 1 "5_and" V 22452 9175 60  0000 R CNN
+F 2 "" H 22300 9450 60  0000 C CNN
+F 3 "" H 22300 9450 60  0000 C CNN
+	1    22300 9450
+	0    -1   1    0   
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/analysis b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/analysis
new file mode 100644
index 000000000..ef45c15d2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74HC154_Test_Circuit/74HC154_TEST/analysis
@@ -0,0 +1 @@
+.tran 5e-00 100e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.cir b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.cir
new file mode 100644
index 000000000..b447a24cb
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.cir
@@ -0,0 +1,46 @@
+.title KiCad schematic
+U11 Net-_X1-Pad5_ Net-_U11-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_X1-Pad5_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U16-Pad2_ Net-_U19-Pad2_ Net-_U2-Pad10_ Net-_U2-Pad11_ GND Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U2-Pad17_ Net-_U2-Pad18_ Net-_U2-Pad19_ Net-_U2-Pad20_ Net-_U17-Pad1_ Net-_U14-Pad1_ Net-_U10-Pad1_ GND PORT
+U14 Net-_U14-Pad1_ Net-_X1-Pad4_ d_inverter
+U21 Net-_U2-Pad20_ Net-_U21-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_X1-Pad3_ d_inverter
+U3 Net-_U2-Pad18_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U2-Pad19_ Net-_U4-Pad2_ d_inverter
+U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_and
+U9 Net-_U9-Pad1_ Net-_U2-Pad5_ d_inverter
+X6 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_U18-Pad2_ Net-_U12-Pad1_ 5_and
+X5 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad4_ Net-_U21-Pad2_ Net-_U18-Pad2_ Net-_U9-Pad1_ 5_and
+X1 Net-_U4-Pad3_ Net-_U21-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U1-Pad1_ 5_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+X2 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad3_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_U6-Pad1_ 5_and
+U6 Net-_U6-Pad1_ Net-_U2-Pad2_ d_inverter
+U7 Net-_U7-Pad1_ Net-_U2-Pad3_ d_inverter
+U8 Net-_U8-Pad1_ Net-_U2-Pad4_ d_inverter
+X3 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad3_ Net-_U21-Pad2_ Net-_X11-Pad4_ Net-_U7-Pad1_ 5_and
+X4 Net-_U4-Pad3_ Net-_X1-Pad3_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U8-Pad1_ 5_and
+U22 Net-_U21-Pad2_ Net-_U22-Pad2_ d_inverter
+U15 Net-_X1-Pad4_ Net-_X11-Pad4_ d_inverter
+U18 Net-_X1-Pad3_ Net-_U18-Pad2_ d_inverter
+U26 Net-_U26-Pad1_ Net-_U2-Pad15_ d_inverter
+X14 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_U11-Pad2_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U26-Pad1_ 5_and
+X15 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U27-Pad1_ 5_and
+U27 Net-_U27-Pad1_ Net-_U2-Pad16_ d_inverter
+X16 Net-_U4-Pad3_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U28-Pad1_ 5_and
+U28 Net-_U28-Pad1_ Net-_U2-Pad17_ d_inverter
+X12 Net-_U4-Pad3_ Net-_X1-Pad3_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U22-Pad2_ Net-_U24-Pad1_ 5_and
+X13 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad4_ Net-_U18-Pad2_ Net-_U22-Pad2_ Net-_U25-Pad1_ 5_and
+U25 Net-_U25-Pad1_ Net-_U2-Pad14_ d_inverter
+U24 Net-_U24-Pad1_ Net-_U2-Pad13_ d_inverter
+X7 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_U21-Pad2_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U13-Pad1_ 5_and
+X8 Net-_U4-Pad3_ Net-_U21-Pad2_ Net-_U11-Pad2_ Net-_X11-Pad4_ Net-_U18-Pad2_ Net-_U16-Pad1_ 5_and
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U20 Net-_U20-Pad1_ Net-_U2-Pad10_ d_inverter
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter
+X10 Net-_U4-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad3_ Net-_U11-Pad2_ Net-_U22-Pad2_ Net-_U20-Pad1_ 5_and
+X11 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad3_ Net-_X11-Pad4_ Net-_U22-Pad2_ Net-_U23-Pad1_ 5_and
+X9 Net-_U4-Pad3_ Net-_X1-Pad5_ Net-_X1-Pad4_ Net-_X1-Pad3_ Net-_U22-Pad2_ Net-_U19-Pad1_ 5_and
+U23 Net-_U23-Pad1_ Net-_U2-Pad11_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.cir.out b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.cir.out
new file mode 100644
index 000000000..200270867
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.cir.out
@@ -0,0 +1,137 @@
+.title kicad schematic
+
+.include 5_and.sub
+* u11 net-_x1-pad5_ net-_u11-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_x1-pad5_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u2-pad10_ net-_u2-pad11_ gnd net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u17-pad1_ net-_u14-pad1_ net-_u10-pad1_ gnd port
+* u14 net-_u14-pad1_ net-_x1-pad4_ d_inverter
+* u21 net-_u2-pad20_ net-_u21-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_x1-pad3_ d_inverter
+* u3 net-_u2-pad18_ net-_u3-pad2_ d_inverter
+* u5 net-_u2-pad19_ net-_u4-pad2_ d_inverter
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_and
+* u9 net-_u9-pad1_ net-_u2-pad5_ d_inverter
+x6 net-_u4-pad3_ net-_x1-pad4_ net-_u21-pad2_ net-_u11-pad2_ net-_u18-pad2_ net-_u12-pad1_ 5_and
+x5 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u21-pad2_ net-_u18-pad2_ net-_u9-pad1_ 5_and
+x1 net-_u4-pad3_ net-_u21-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u1-pad1_ 5_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+x2 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_u6-pad1_ 5_and
+* u6 net-_u6-pad1_ net-_u2-pad2_ d_inverter
+* u7 net-_u7-pad1_ net-_u2-pad3_ d_inverter
+* u8 net-_u8-pad1_ net-_u2-pad4_ d_inverter
+x3 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_u21-pad2_ net-_x11-pad4_ net-_u7-pad1_ 5_and
+x4 net-_u4-pad3_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u8-pad1_ 5_and
+* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter
+* u15 net-_x1-pad4_ net-_x11-pad4_ d_inverter
+* u18 net-_x1-pad3_ net-_u18-pad2_ d_inverter
+* u26 net-_u26-pad1_ net-_u2-pad15_ d_inverter
+x14 net-_u4-pad3_ net-_x1-pad4_ net-_u11-pad2_ net-_u18-pad2_ net-_u22-pad2_ net-_u26-pad1_ 5_and
+x15 net-_u4-pad3_ net-_x1-pad5_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u27-pad1_ 5_and
+* u27 net-_u27-pad1_ net-_u2-pad16_ d_inverter
+x16 net-_u4-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u28-pad1_ 5_and
+* u28 net-_u28-pad1_ net-_u2-pad17_ d_inverter
+x12 net-_u4-pad3_ net-_x1-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u22-pad2_ net-_u24-pad1_ 5_and
+x13 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u25-pad1_ 5_and
+* u25 net-_u25-pad1_ net-_u2-pad14_ d_inverter
+* u24 net-_u24-pad1_ net-_u2-pad13_ d_inverter
+x7 net-_u4-pad3_ net-_x1-pad5_ net-_u21-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u13-pad1_ 5_and
+x8 net-_u4-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u16-pad1_ 5_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u2-pad10_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+x10 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u11-pad2_ net-_u22-pad2_ net-_u20-pad1_ 5_and
+x11 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_x11-pad4_ net-_u22-pad2_ net-_u23-pad1_ 5_and
+x9 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_x1-pad3_ net-_u22-pad2_ net-_u19-pad1_ 5_and
+* u23 net-_u23-pad1_ net-_u2-pad11_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+a1 net-_x1-pad5_ net-_u11-pad2_ u11
+a2 net-_u10-pad1_ net-_x1-pad5_ u10
+a3 net-_u14-pad1_ net-_x1-pad4_ u14
+a4 net-_u2-pad20_ net-_u21-pad2_ u21
+a5 net-_u17-pad1_ net-_x1-pad3_ u17
+a6 net-_u2-pad18_ net-_u3-pad2_ u3
+a7 net-_u2-pad19_ net-_u4-pad2_ u5
+a8 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a9 net-_u9-pad1_ net-_u2-pad5_ u9
+a10 net-_u1-pad1_ net-_u1-pad2_ u1
+a11 net-_u6-pad1_ net-_u2-pad2_ u6
+a12 net-_u7-pad1_ net-_u2-pad3_ u7
+a13 net-_u8-pad1_ net-_u2-pad4_ u8
+a14 net-_u21-pad2_ net-_u22-pad2_ u22
+a15 net-_x1-pad4_ net-_x11-pad4_ u15
+a16 net-_x1-pad3_ net-_u18-pad2_ u18
+a17 net-_u26-pad1_ net-_u2-pad15_ u26
+a18 net-_u27-pad1_ net-_u2-pad16_ u27
+a19 net-_u28-pad1_ net-_u2-pad17_ u28
+a20 net-_u25-pad1_ net-_u2-pad14_ u25
+a21 net-_u24-pad1_ net-_u2-pad13_ u24
+a22 net-_u12-pad1_ net-_u12-pad2_ u12
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u20-pad1_ net-_u2-pad10_ u20
+a25 net-_u19-pad1_ net-_u19-pad2_ u19
+a26 net-_u23-pad1_ net-_u2-pad11_ u23
+a27 net-_u16-pad1_ net-_u16-pad2_ u16
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.kicad_sch b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.kicad_sch
new file mode 100644
index 000000000..6ad7f9bd9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.kicad_sch
@@ -0,0 +1,3660 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid ae4e3b24-ddc2-4653-bba9-f14c3aa0c549)
+
+  (paper "A2")
+
+  (lib_symbols
+    (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
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+      (reference "U23") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6285dcdf-b865-40d3-8f90-a2fba9083383"
+      (reference "U24") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/80befffb-4ecc-4698-8099-a9ac268c2546"
+      (reference "U25") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/faa42990-0143-4163-8d64-b9af777a2cd2"
+      (reference "U26") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/376cbe51-1573-41af-953a-c7371fb1681d"
+      (reference "U27") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/178f8765-a5ce-46cb-8bcd-34eb1df74b59"
+      (reference "U28") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6f5365b6-e565-4b85-99e0-138fd40dc311"
+      (reference "X1") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/cef3355b-8bd0-4873-9435-77a36eef0690"
+      (reference "X2") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/ec346ea0-d69a-4d56-9a7d-95b1b2275538"
+      (reference "X3") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/20cf08ea-b100-4ac3-a619-22c906f477e6"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/64f208a5-c1d1-4b3f-a41f-0b624f780098"
+      (reference "X5") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/881f6348-2b83-42a6-adcb-c7fccc7ecb7f"
+      (reference "X6") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/0374ec46-9712-4b19-81c9-267f1f8aab82"
+      (reference "X7") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/31c39bfc-b198-45af-b380-220bd9e3ac81"
+      (reference "X8") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/1789ec57-1b50-46e5-8c53-a8cd3420ee17"
+      (reference "X9") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/c9566a68-5686-429d-ba34-c23a6f24d890"
+      (reference "X10") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/b024f3d2-a346-4696-97bb-4f785fe2ae86"
+      (reference "X11") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/312ef13e-3aee-40f7-b65d-f53ef02d77b0"
+      (reference "X12") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/3de2ed1d-f7a5-443b-847d-cdb4fbbcf718"
+      (reference "X13") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/8ecc4f08-9a53-433e-a215-5c2734dc1643"
+      (reference "X14") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/cf7c0078-f48c-430a-b086-e166b7a686ed"
+      (reference "X15") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/105a6b2c-c1bd-4133-95db-51e4ae1e42ae"
+      (reference "X16") (unit 1) (value "5_and") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.sub b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.sub
new file mode 100644
index 000000000..3d8cde22d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154.sub
@@ -0,0 +1,131 @@
+* Subcircuit 74LS154
+.subckt 74LS154 net-_u1-pad2_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u12-pad2_ net-_u13-pad2_ net-_u16-pad2_ net-_u19-pad2_ net-_u2-pad10_ net-_u2-pad11_ gnd net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u17-pad1_ net-_u14-pad1_ net-_u10-pad1_ gnd 
+.title kicad schematic
+.include 5_and.sub
+* u11 net-_x1-pad5_ net-_u11-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_x1-pad5_ d_inverter
+* u14 net-_u14-pad1_ net-_x1-pad4_ d_inverter
+* u21 net-_u2-pad20_ net-_u21-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_x1-pad3_ d_inverter
+* u3 net-_u2-pad18_ net-_u3-pad2_ d_inverter
+* u5 net-_u2-pad19_ net-_u4-pad2_ d_inverter
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_and
+* u9 net-_u9-pad1_ net-_u2-pad5_ d_inverter
+x6 net-_u4-pad3_ net-_x1-pad4_ net-_u21-pad2_ net-_u11-pad2_ net-_u18-pad2_ net-_u12-pad1_ 5_and
+x5 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u21-pad2_ net-_u18-pad2_ net-_u9-pad1_ 5_and
+x1 net-_u4-pad3_ net-_u21-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u1-pad1_ 5_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+x2 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_u6-pad1_ 5_and
+* u6 net-_u6-pad1_ net-_u2-pad2_ d_inverter
+* u7 net-_u7-pad1_ net-_u2-pad3_ d_inverter
+* u8 net-_u8-pad1_ net-_u2-pad4_ d_inverter
+x3 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_u21-pad2_ net-_x11-pad4_ net-_u7-pad1_ 5_and
+x4 net-_u4-pad3_ net-_x1-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u8-pad1_ 5_and
+* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter
+* u15 net-_x1-pad4_ net-_x11-pad4_ d_inverter
+* u18 net-_x1-pad3_ net-_u18-pad2_ d_inverter
+* u26 net-_u26-pad1_ net-_u2-pad15_ d_inverter
+x14 net-_u4-pad3_ net-_x1-pad4_ net-_u11-pad2_ net-_u18-pad2_ net-_u22-pad2_ net-_u26-pad1_ 5_and
+x15 net-_u4-pad3_ net-_x1-pad5_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u27-pad1_ 5_and
+* u27 net-_u27-pad1_ net-_u2-pad16_ d_inverter
+x16 net-_u4-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u28-pad1_ 5_and
+* u28 net-_u28-pad1_ net-_u2-pad17_ d_inverter
+x12 net-_u4-pad3_ net-_x1-pad3_ net-_u11-pad2_ net-_x11-pad4_ net-_u22-pad2_ net-_u24-pad1_ 5_and
+x13 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_u18-pad2_ net-_u22-pad2_ net-_u25-pad1_ 5_and
+* u25 net-_u25-pad1_ net-_u2-pad14_ d_inverter
+* u24 net-_u24-pad1_ net-_u2-pad13_ d_inverter
+x7 net-_u4-pad3_ net-_x1-pad5_ net-_u21-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u13-pad1_ 5_and
+x8 net-_u4-pad3_ net-_u21-pad2_ net-_u11-pad2_ net-_x11-pad4_ net-_u18-pad2_ net-_u16-pad1_ 5_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u2-pad10_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+x10 net-_u4-pad3_ net-_x1-pad4_ net-_x1-pad3_ net-_u11-pad2_ net-_u22-pad2_ net-_u20-pad1_ 5_and
+x11 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad3_ net-_x11-pad4_ net-_u22-pad2_ net-_u23-pad1_ 5_and
+x9 net-_u4-pad3_ net-_x1-pad5_ net-_x1-pad4_ net-_x1-pad3_ net-_u22-pad2_ net-_u19-pad1_ 5_and
+* u23 net-_u23-pad1_ net-_u2-pad11_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+a1 net-_x1-pad5_ net-_u11-pad2_ u11
+a2 net-_u10-pad1_ net-_x1-pad5_ u10
+a3 net-_u14-pad1_ net-_x1-pad4_ u14
+a4 net-_u2-pad20_ net-_u21-pad2_ u21
+a5 net-_u17-pad1_ net-_x1-pad3_ u17
+a6 net-_u2-pad18_ net-_u3-pad2_ u3
+a7 net-_u2-pad19_ net-_u4-pad2_ u5
+a8 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a9 net-_u9-pad1_ net-_u2-pad5_ u9
+a10 net-_u1-pad1_ net-_u1-pad2_ u1
+a11 net-_u6-pad1_ net-_u2-pad2_ u6
+a12 net-_u7-pad1_ net-_u2-pad3_ u7
+a13 net-_u8-pad1_ net-_u2-pad4_ u8
+a14 net-_u21-pad2_ net-_u22-pad2_ u22
+a15 net-_x1-pad4_ net-_x11-pad4_ u15
+a16 net-_x1-pad3_ net-_u18-pad2_ u18
+a17 net-_u26-pad1_ net-_u2-pad15_ u26
+a18 net-_u27-pad1_ net-_u2-pad16_ u27
+a19 net-_u28-pad1_ net-_u2-pad17_ u28
+a20 net-_u25-pad1_ net-_u2-pad14_ u25
+a21 net-_u24-pad1_ net-_u2-pad13_ u24
+a22 net-_u12-pad1_ net-_u12-pad2_ u12
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u20-pad1_ net-_u2-pad10_ u20
+a25 net-_u19-pad1_ net-_u19-pad2_ u19
+a26 net-_u23-pad1_ net-_u2-pad11_ u23
+a27 net-_u16-pad1_ net-_u16-pad2_ u16
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74LS154
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154_Previous_Values.xml
new file mode 100644
index 000000000..a9eb5b618
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/74LS154_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u11 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u10 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u14><u21 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u17><u4 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u1 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u1><u6 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u8><u22 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u18 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u18><u15 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u26 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u28><u24 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u13 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u12><u20 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u20><u19 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u23><u16 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u16></model><devicemodel /><subcircuit><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x14><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x14><x15><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x15><x16><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x16><x12><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x12><x13><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x13><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x10><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x11><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x9></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/_autosave-74LS154.sch b/library/SubcircuitLibrary/IC74HC154/74HC154/_autosave-74LS154.sch
new file mode 100644
index 000000000..ab3ad1a54
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/_autosave-74LS154.sch
@@ -0,0 +1,1287 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
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+$EndDescr
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+F 3 "" H 12700 11500 60  0000 C CNN
+	9    12700 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 10 1 00000000
+P 14150 11500
+F 0 "U2" V 14200 11400 30  0000 R CNN
+F 1 "PORT" V 14100 11400 30  0000 R CNN
+F 2 "" H 14150 11500 60  0000 C CNN
+F 3 "" H 14150 11500 60  0000 C CNN
+	10   14150 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 20 1 00000000
+P 15525 2525
+F 0 "U2" V 15525 2425 30  0000 R CNN
+F 1 "PORT" V 15625 2425 30  0000 R CNN
+F 2 "" H 15525 2525 60  0000 C CNN
+F 3 "" H 15525 2525 60  0000 C CNN
+	20   15525 2525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 11 1 00000000
+P 15550 11525
+F 0 "U2" V 15600 11425 30  0000 R CNN
+F 1 "PORT" V 15500 11425 30  0000 R CNN
+F 2 "" H 15550 11525 60  0000 C CNN
+F 3 "" H 15550 11525 60  0000 C CNN
+	11   15550 11525
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 13 1 00000000
+P 16975 11500
+F 0 "U2" V 17025 11425 30  0000 R CNN
+F 1 "PORT" V 16925 11425 30  0000 R CNN
+F 2 "" H 16975 11500 60  0000 C CNN
+F 3 "" H 16975 11500 60  0000 C CNN
+	13   16975 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 14 1 00000000
+P 18225 11500
+F 0 "U2" V 18275 11400 30  0000 R CNN
+F 1 "PORT" V 18175 11400 30  0000 R CNN
+F 2 "" H 18225 11500 60  0000 C CNN
+F 3 "" H 18225 11500 60  0000 C CNN
+	14   18225 11500
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 24 1 00000000
+P 18250 3125
+F 0 "U2" H 18275 3300 30  0000 C CNN
+F 1 "PORT" H 18275 3200 30  0000 C CNN
+F 2 "" H 18250 3125 60  0000 C CNN
+F 3 "" H 18250 3125 60  0000 C CNN
+	24   18250 3125
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 12 1 00000000
+P 18250 3950
+F 0 "U2" H 18275 4125 30  0000 C CNN
+F 1 "PORT" H 18275 4025 30  0000 C CNN
+F 2 "" H 18250 3950 60  0000 C CNN
+F 3 "" H 18250 3950 60  0000 C CNN
+	12   18250 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 15 1 00000000
+P 19625 11475
+F 0 "U2" V 19675 11400 30  0000 R CNN
+F 1 "PORT" V 19575 11400 30  0000 R CNN
+F 2 "" H 19625 11475 60  0000 C CNN
+F 3 "" H 19625 11475 60  0000 C CNN
+	15   19625 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 16 1 00000000
+P 21025 11475
+F 0 "U2" V 21075 11375 30  0000 R CNN
+F 1 "PORT" V 20975 11375 30  0000 R CNN
+F 2 "" H 21025 11475 60  0000 C CNN
+F 3 "" H 21025 11475 60  0000 C CNN
+	16   21025 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U2
+U 17 1 00000000
+P 22300 11475
+F 0 "U2" V 22350 11375 30  0000 R CNN
+F 1 "PORT" V 22250 11375 30  0000 R CNN
+F 2 "" H 22300 11475 60  0000 C CNN
+F 3 "" H 22300 11475 60  0000 C CNN
+	17   22300 11475
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U1
+U 1 1 00000000
+P 2550 10625
+F 0 "U1" V 2500 10525 60  0000 R CNN
+F 1 "d_inverter" V 2650 10525 60  0000 R CNN
+F 2 "" H 2600 10575 60  0000 C CNN
+F 3 "" H 2600 10575 60  0000 C CNN
+	1    2550 10625
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U3
+U 1 1 00000000
+P 2925 4250
+F 0 "U3" V 2925 4475 60  0000 R CNN
+F 1 "d_inverter" V 3025 4725 60  0000 R CNN
+F 2 "" H 2975 4200 60  0000 C CNN
+F 3 "" H 2975 4200 60  0000 C CNN
+	1    2925 4250
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U5
+U 1 1 00000000
+P 3050 4250
+F 0 "U5" V 2950 4125 60  0000 R CNN
+F 1 "d_inverter" V 2825 4175 60  0000 R CNN
+F 2 "" H 3100 4200 60  0000 C CNN
+F 3 "" H 3100 4200 60  0000 C CNN
+	1    3050 4250
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U6
+U 1 1 00000000
+P 3850 10575
+F 0 "U6" V 3800 10475 60  0000 R CNN
+F 1 "d_inverter" V 3950 10475 60  0000 R CNN
+F 2 "" H 3900 10525 60  0000 C CNN
+F 3 "" H 3900 10525 60  0000 C CNN
+	1    3850 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U7
+U 1 1 00000000
+P 4975 10575
+F 0 "U7" V 4925 10500 60  0000 R CNN
+F 1 "d_inverter" V 5075 10500 60  0000 R CNN
+F 2 "" H 5025 10525 60  0000 C CNN
+F 3 "" H 5025 10525 60  0000 C CNN
+	1    4975 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U8
+U 1 1 00000000
+P 6125 10550
+F 0 "U8" V 6075 10475 60  0000 R CNN
+F 1 "d_inverter" V 6225 10475 60  0000 R CNN
+F 2 "" H 6175 10500 60  0000 C CNN
+F 3 "" H 6175 10500 60  0000 C CNN
+	1    6125 10550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U9
+U 1 1 00000000
+P 7475 10525
+F 0 "U9" V 7425 10450 60  0000 R CNN
+F 1 "d_inverter" V 7575 10450 60  0000 R CNN
+F 2 "" H 7525 10475 60  0000 C CNN
+F 3 "" H 7525 10475 60  0000 C CNN
+	1    7475 10525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U10
+U 1 1 00000000
+P 7500 3775
+F 0 "U10" V 7450 3675 60  0000 R CNN
+F 1 "d_inverter" V 7600 3675 60  0000 R CNN
+F 2 "" H 7550 3725 60  0000 C CNN
+F 3 "" H 7550 3725 60  0000 C CNN
+	1    7500 3775
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U11
+U 1 1 00000000
+P 7500 5000
+F 0 "U11" V 7450 4900 60  0000 R CNN
+F 1 "d_inverter" V 7600 4900 60  0000 R CNN
+F 2 "" H 7550 4950 60  0000 C CNN
+F 3 "" H 7550 4950 60  0000 C CNN
+	1    7500 5000
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U12
+U 1 1 00000000
+P 8750 10575
+F 0 "U12" V 8700 10475 60  0000 R CNN
+F 1 "d_inverter" V 8850 10475 60  0000 R CNN
+F 2 "" H 8800 10525 60  0000 C CNN
+F 3 "" H 8800 10525 60  0000 C CNN
+	1    8750 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U13
+U 1 1 00000000
+P 9975 10550
+F 0 "U13" V 9925 10450 60  0000 R CNN
+F 1 "d_inverter" V 10075 10450 60  0000 R CNN
+F 2 "" H 10025 10500 60  0000 C CNN
+F 3 "" H 10025 10500 60  0000 C CNN
+	1    9975 10550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 10000 3825
+F 0 "U14" V 9950 3725 60  0000 R CNN
+F 1 "d_inverter" V 10100 3725 60  0000 R CNN
+F 2 "" H 10050 3775 60  0000 C CNN
+F 3 "" H 10050 3775 60  0000 C CNN
+	1    10000 3825
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U15
+U 1 1 00000000
+P 10000 4925
+F 0 "U15" V 9950 4825 60  0000 R CNN
+F 1 "d_inverter" V 10100 4825 60  0000 R CNN
+F 2 "" H 10050 4875 60  0000 C CNN
+F 3 "" H 10050 4875 60  0000 C CNN
+	1    10000 4925
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U16
+U 1 1 00000000
+P 11325 10625
+F 0 "U16" V 11275 10550 60  0000 R CNN
+F 1 "d_inverter" V 11425 10550 60  0000 R CNN
+F 2 "" H 11375 10575 60  0000 C CNN
+F 3 "" H 11375 10575 60  0000 C CNN
+	1    11325 10625
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U17
+U 1 1 00000000
+P 12550 3775
+F 0 "U17" V 12500 3675 60  0000 R CNN
+F 1 "d_inverter" V 12650 3675 60  0000 R CNN
+F 2 "" H 12600 3725 60  0000 C CNN
+F 3 "" H 12600 3725 60  0000 C CNN
+	1    12550 3775
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U18
+U 1 1 00000000
+P 12550 4875
+F 0 "U18" V 12500 4775 60  0000 R CNN
+F 1 "d_inverter" V 12650 4775 60  0000 R CNN
+F 2 "" H 12600 4825 60  0000 C CNN
+F 3 "" H 12600 4825 60  0000 C CNN
+	1    12550 4875
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U19
+U 1 1 00000000
+P 12700 10600
+F 0 "U19" V 12650 10500 60  0000 R CNN
+F 1 "d_inverter" V 12800 10500 60  0000 R CNN
+F 2 "" H 12750 10550 60  0000 C CNN
+F 3 "" H 12750 10550 60  0000 C CNN
+	1    12700 10600
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U20
+U 1 1 00000000
+P 14150 10525
+F 0 "U20" V 14100 10425 60  0000 R CNN
+F 1 "d_inverter" V 14250 10425 60  0000 R CNN
+F 2 "" H 14200 10475 60  0000 C CNN
+F 3 "" H 14200 10475 60  0000 C CNN
+	1    14150 10525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U21
+U 1 1 00000000
+P 15525 3725
+F 0 "U21" V 15475 3650 60  0000 R CNN
+F 1 "d_inverter" V 15625 3650 60  0000 R CNN
+F 2 "" H 15575 3675 60  0000 C CNN
+F 3 "" H 15575 3675 60  0000 C CNN
+	1    15525 3725
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U22
+U 1 1 00000000
+P 15525 4875
+F 0 "U22" V 15475 4775 60  0000 R CNN
+F 1 "d_inverter" V 15625 4775 60  0000 R CNN
+F 2 "" H 15575 4825 60  0000 C CNN
+F 3 "" H 15575 4825 60  0000 C CNN
+	1    15525 4875
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U23
+U 1 1 00000000
+P 15550 10550
+F 0 "U23" V 15500 10450 60  0000 R CNN
+F 1 "d_inverter" V 15650 10450 60  0000 R CNN
+F 2 "" H 15600 10500 60  0000 C CNN
+F 3 "" H 15600 10500 60  0000 C CNN
+	1    15550 10550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U24
+U 1 1 00000000
+P 16975 10575
+F 0 "U24" V 16925 10475 60  0000 R CNN
+F 1 "d_inverter" V 17075 10475 60  0000 R CNN
+F 2 "" H 17025 10525 60  0000 C CNN
+F 3 "" H 17025 10525 60  0000 C CNN
+	1    16975 10575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U25
+U 1 1 00000000
+P 18225 10600
+F 0 "U25" V 18175 10500 60  0000 R CNN
+F 1 "d_inverter" V 18325 10500 60  0000 R CNN
+F 2 "" H 18275 10550 60  0000 C CNN
+F 3 "" H 18275 10550 60  0000 C CNN
+	1    18225 10600
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U26
+U 1 1 00000000
+P 19625 10500
+F 0 "U26" V 19575 10425 60  0000 R CNN
+F 1 "d_inverter" V 19725 10425 60  0000 R CNN
+F 2 "" H 19675 10450 60  0000 C CNN
+F 3 "" H 19675 10450 60  0000 C CNN
+	1    19625 10500
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U27
+U 1 1 00000000
+P 21025 10500
+F 0 "U27" V 20975 10425 60  0000 R CNN
+F 1 "d_inverter" V 21125 10425 60  0000 R CNN
+F 2 "" H 21075 10450 60  0000 C CNN
+F 3 "" H 21075 10450 60  0000 C CNN
+	1    21025 10500
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U28
+U 1 1 00000000
+P 22300 10525
+F 0 "U28" V 22250 10425 60  0000 R CNN
+F 1 "d_inverter" V 22400 10425 60  0000 R CNN
+F 2 "" H 22350 10475 60  0000 C CNN
+F 3 "" H 22350 10475 60  0000 C CNN
+	1    22300 10525
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_and U4
+U 1 1 00000000
+P 3025 5300
+F 0 "U4" V 2975 5225 60  0000 R CNN
+F 1 "d_and" V 3125 5225 60  0000 R CNN
+F 2 "" H 3025 5300 60  0000 C CNN
+F 3 "" H 3025 5300 60  0000 C CNN
+	1    3025 5300
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X1
+U 1 1 00000000
+P 2550 9475
+F 0 "X1" V 2552 9200 60  0000 R CNN
+F 1 "5_and" V 2702 9200 60  0000 R CNN
+F 2 "" H 2550 9475 60  0000 C CNN
+F 3 "" H 2550 9475 60  0000 C CNN
+	1    2550 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X2
+U 1 1 00000000
+P 3850 9475
+F 0 "X2" V 3852 9175 60  0000 R CNN
+F 1 "5_and" V 4002 9175 60  0000 R CNN
+F 2 "" H 3850 9475 60  0000 C CNN
+F 3 "" H 3850 9475 60  0000 C CNN
+	1    3850 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X3
+U 1 1 00000000
+P 4975 9475
+F 0 "X3" V 4977 9200 60  0000 R CNN
+F 1 "5_and" V 5127 9200 60  0000 R CNN
+F 2 "" H 4975 9475 60  0000 C CNN
+F 3 "" H 4975 9475 60  0000 C CNN
+	1    4975 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X4
+U 1 1 00000000
+P 6125 9475
+F 0 "X4" V 6127 9200 60  0000 R CNN
+F 1 "5_and" V 6277 9200 60  0000 R CNN
+F 2 "" H 6125 9475 60  0000 C CNN
+F 3 "" H 6125 9475 60  0000 C CNN
+	1    6125 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X5
+U 1 1 00000000
+P 7475 9475
+F 0 "X5" V 7477 9200 60  0000 R CNN
+F 1 "5_and" V 7627 9200 60  0000 R CNN
+F 2 "" H 7475 9475 60  0000 C CNN
+F 3 "" H 7475 9475 60  0000 C CNN
+	1    7475 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X6
+U 1 1 00000000
+P 8750 9450
+F 0 "X6" V 8752 9175 60  0000 R CNN
+F 1 "5_and" V 8902 9175 60  0000 R CNN
+F 2 "" H 8750 9450 60  0000 C CNN
+F 3 "" H 8750 9450 60  0000 C CNN
+	1    8750 9450
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X7
+U 1 1 00000000
+P 9975 9450
+F 0 "X7" V 9977 9150 60  0000 R CNN
+F 1 "5_and" V 10127 9150 60  0000 R CNN
+F 2 "" H 9975 9450 60  0000 C CNN
+F 3 "" H 9975 9450 60  0000 C CNN
+	1    9975 9450
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X8
+U 1 1 00000000
+P 11325 9475
+F 0 "X8" V 11327 9200 60  0000 R CNN
+F 1 "5_and" V 11477 9200 60  0000 R CNN
+F 2 "" H 11325 9475 60  0000 C CNN
+F 3 "" H 11325 9475 60  0000 C CNN
+	1    11325 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X9
+U 1 1 00000000
+P 12700 9475
+F 0 "X9" V 12702 9175 60  0000 R CNN
+F 1 "5_and" V 12852 9175 60  0000 R CNN
+F 2 "" H 12700 9475 60  0000 C CNN
+F 3 "" H 12700 9475 60  0000 C CNN
+	1    12700 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X10
+U 1 1 00000000
+P 14150 9475
+F 0 "X10" V 14152 9200 60  0000 R CNN
+F 1 "5_and" V 14302 9200 60  0000 R CNN
+F 2 "" H 14150 9475 60  0000 C CNN
+F 3 "" H 14150 9475 60  0000 C CNN
+	1    14150 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X11
+U 1 1 00000000
+P 15550 9475
+F 0 "X11" V 15552 9200 60  0000 R CNN
+F 1 "5_and" V 15702 9200 60  0000 R CNN
+F 2 "" H 15550 9475 60  0000 C CNN
+F 3 "" H 15550 9475 60  0000 C CNN
+	1    15550 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X12
+U 1 1 00000000
+P 16975 9475
+F 0 "X12" V 16977 9175 60  0000 R CNN
+F 1 "5_and" V 17127 9175 60  0000 R CNN
+F 2 "" H 16975 9475 60  0000 C CNN
+F 3 "" H 16975 9475 60  0000 C CNN
+	1    16975 9475
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X13
+U 1 1 00000000
+P 18225 9450
+F 0 "X13" V 18227 9150 60  0000 R CNN
+F 1 "5_and" V 18377 9150 60  0000 R CNN
+F 2 "" H 18225 9450 60  0000 C CNN
+F 3 "" H 18225 9450 60  0000 C CNN
+	1    18225 9450
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X14
+U 1 1 00000000
+P 19625 9425
+F 0 "X14" V 19627 9125 60  0000 R CNN
+F 1 "5_and" V 19777 9125 60  0000 R CNN
+F 2 "" H 19625 9425 60  0000 C CNN
+F 3 "" H 19625 9425 60  0000 C CNN
+	1    19625 9425
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X15
+U 1 1 00000000
+P 21025 9425
+F 0 "X15" V 21027 9125 60  0000 R CNN
+F 1 "5_and" V 21177 9125 60  0000 R CNN
+F 2 "" H 21025 9425 60  0000 C CNN
+F 3 "" H 21025 9425 60  0000 C CNN
+	1    21025 9425
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Subckt:5_and X16
+U 1 1 00000000
+P 22300 9450
+F 0 "X16" V 22302 9175 60  0000 R CNN
+F 1 "5_and" V 22452 9175 60  0000 R CNN
+F 2 "" H 22300 9450 60  0000 C CNN
+F 3 "" H 22300 9450 60  0000 C CNN
+	1    22300 9450
+	0    -1   1    0   
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC154/74HC154/analysis b/library/SubcircuitLibrary/IC74HC154/74HC154/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC154/74HC154/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.cir b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.cir
new file mode 100644
index 000000000..901876de6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.cir
@@ -0,0 +1,23 @@
+.title KiCad schematic
+U19 Net-_U18-Pad2_ Net-_U11-Pad2_ unconnected-_U19-Pad3_ Net-_U11-Pad4_ Net-_U19-Pad5_ Net-_U19-Pad6_ d_dff
+U16 Net-_U15-Pad6_ Net-_U1-Pad10_ d_inverter
+U17 Net-_U15-Pad5_ Net-_U1-Pad11_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ GND Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U21-Pad2_ Net-_U20-Pad2_ GND PORT
+U18 Net-_U1-Pad13_ Net-_U18-Pad2_ d_inverter
+U20 Net-_U19-Pad6_ Net-_U20-Pad2_ d_inverter
+U21 Net-_U19-Pad5_ Net-_U21-Pad2_ d_inverter
+U15 Net-_U14-Pad2_ Net-_U11-Pad2_ unconnected-_U15-Pad3_ Net-_U11-Pad4_ Net-_U15-Pad5_ Net-_U15-Pad6_ d_dff
+U13 Net-_U11-Pad5_ Net-_U1-Pad6_ d_inverter
+U12 Net-_U11-Pad6_ Net-_U1-Pad7_ d_inverter
+U10 Net-_U1-Pad5_ Net-_U10-Pad2_ d_inverter
+U14 Net-_U1-Pad12_ Net-_U14-Pad2_ d_inverter
+U11 Net-_U10-Pad2_ Net-_U11-Pad2_ unconnected-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ d_dff
+U8 Net-_U7-Pad6_ Net-_U1-Pad2_ d_inverter
+U9 Net-_U7-Pad5_ Net-_U1-Pad3_ d_inverter
+U6 Net-_U3-Pad2_ Net-_U11-Pad4_ d_inverter
+U5 Net-_U2-Pad2_ Net-_U11-Pad2_ d_inverter
+U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+U4 Net-_U1-Pad4_ Net-_U4-Pad2_ d_inverter
+U7 Net-_U4-Pad2_ Net-_U11-Pad2_ unconnected-_U7-Pad3_ Net-_U11-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad6_ d_dff
+.end
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.cir.out b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.cir.out
new file mode 100644
index 000000000..893dc9ac0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.cir.out
@@ -0,0 +1,92 @@
+.title kicad schematic
+
+* u19 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ d_dff
+* u16 net-_u15-pad6_ net-_u1-pad10_ d_inverter
+* u17 net-_u15-pad5_ net-_u1-pad11_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u21-pad2_ net-_u20-pad2_ gnd port
+* u18 net-_u1-pad13_ net-_u18-pad2_ d_inverter
+* u20 net-_u19-pad6_ net-_u20-pad2_ d_inverter
+* u21 net-_u19-pad5_ net-_u21-pad2_ d_inverter
+* u15 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_dff
+* u13 net-_u11-pad5_ net-_u1-pad6_ d_inverter
+* u12 net-_u11-pad6_ net-_u1-pad7_ d_inverter
+* u10 net-_u1-pad5_ net-_u10-pad2_ d_inverter
+* u14 net-_u1-pad12_ net-_u14-pad2_ d_inverter
+* u11 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_dff
+* u8 net-_u7-pad6_ net-_u1-pad2_ d_inverter
+* u9 net-_u7-pad5_ net-_u1-pad3_ d_inverter
+* u6 net-_u3-pad2_ net-_u11-pad4_ d_inverter
+* u5 net-_u2-pad2_ net-_u11-pad2_ d_inverter
+* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u4 net-_u1-pad4_ net-_u4-pad2_ d_inverter
+* u7 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ d_dff
+a1 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ u19
+a2 net-_u15-pad6_ net-_u1-pad10_ u16
+a3 net-_u15-pad5_ net-_u1-pad11_ u17
+a4 net-_u1-pad13_ net-_u18-pad2_ u18
+a5 net-_u19-pad6_ net-_u20-pad2_ u20
+a6 net-_u19-pad5_ net-_u21-pad2_ u21
+a7 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15
+a8 net-_u11-pad5_ net-_u1-pad6_ u13
+a9 net-_u11-pad6_ net-_u1-pad7_ u12
+a10 net-_u1-pad5_ net-_u10-pad2_ u10
+a11 net-_u1-pad12_ net-_u14-pad2_ u14
+a12 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11
+a13 net-_u7-pad6_ net-_u1-pad2_ u8
+a14 net-_u7-pad5_ net-_u1-pad3_ u9
+a15 net-_u3-pad2_ net-_u11-pad4_ u6
+a16 net-_u2-pad2_ net-_u11-pad2_ u5
+a17 net-_u1-pad1_ net-_u3-pad2_ u3
+a18 net-_u1-pad9_ net-_u2-pad2_ u2
+a19 net-_u1-pad4_ net-_u4-pad2_ u4
+a20 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ u7
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u19 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.kicad_sch b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.kicad_sch
new file mode 100644
index 000000000..0b1d348d4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.kicad_sch
@@ -0,0 +1,1941 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 6957dcfd-8c33-489d-9409-7ae1db0d37ae)
+
+  (paper "A4")
+
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+  )
+
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+    (in_bom yes) (on_board yes) (fields_autoplaced)
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+    )
+    (property "Value" "d_inverter" (id 1) (at 218.44 48.26 90)
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+    )
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+  )
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+    )
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+  )
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+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+
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+    (path "/" (page "1"))
+  )
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+    )
+    (path "/f8bac145-7d62-466b-9a88-dda830a8dbb5"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/0b7e9abc-5a81-4f58-b151-9456acbb0cce"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/0c76cdd6-b5bf-4a87-a3ab-bac5bf36d263"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/ab330272-c9c8-4a53-8b79-744e7e15c315"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
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+    )
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+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/48c236d7-92d0-4a12-ab7d-b0d05a245a74"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/e5a318a0-b24e-411e-be3e-784b4066bc28"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/7501fad9-cd80-497f-ad77-c98aeffd8712"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/dbdadaac-c561-44f3-9792-cfe65bde1af1"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/c62b9f5c-b8a0-4406-816a-83b30997103c"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/6042aede-43e0-4d48-be1e-5d2cf213b1ef"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/0e96f6a6-9ce7-4703-9db5-48ffd1bdce24"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/2cef7bc4-3c35-4521-9949-7623d21b3da4"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/21d6a7cd-c8b1-41ea-98fd-aace6210c5f7"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/c38155c5-1f69-4969-9119-73a693ae4d16"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/61fb3525-4e51-47f4-8de4-d2deb3a3dac0"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/2a78165c-80b3-4c0a-82d5-a3e422880f71"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/839c198a-b872-400e-934c-608bdb53402f"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/adea3196-2cf2-41e9-95b8-363ccc73e76c"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/b7fe52fd-30ca-42d8-a5c8-8e884b0221d9"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/da769909-adb9-4050-bc7c-6b04a5bf2bf7"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/db63c4a5-488a-4c73-b7c4-5e7c934960d5"
+      (reference "U7") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/446e6e11-316c-4f38-ba51-e4c94879af97"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a6507eb9-a339-423d-8faa-983a6c11b554"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3d646cf4-394c-4e1a-bedd-f85694f99585"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/ebe1817e-b97e-4fb4-a00c-2cd7497457d4"
+      (reference "U11") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/6ca6239c-bb5b-4031-9e4b-824201fb60db"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/59d73813-fd8e-4273-b307-053010994ac9"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/98c7afd4-97e7-481c-b7ac-b54c3be564e8"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3aec90bc-0e89-4973-ac8e-b13373bd9369"
+      (reference "U15") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/e47972e5-e896-4a31-8511-e713981ef45e"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8fa10b8e-a0f2-46c9-a129-3cea4ecff966"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/e7efb678-2f84-41fc-8957-ef7207266418"
+      (reference "U18") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/263d3fe5-3260-46ec-a291-ddd6c530f86e"
+      (reference "U19") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/ad7eb8de-5a92-4b6d-bc81-1ccfdfb12967"
+      (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a493cdec-12c9-4458-845a-45669fa02805"
+      (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.sub b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.sub
new file mode 100644
index 000000000..2dd965992
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175.sub
@@ -0,0 +1,86 @@
+* Subcircuit 74HC175
+.subckt 74HC175 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u21-pad2_ net-_u20-pad2_ gnd 
+.title kicad schematic
+* u19 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ d_dff
+* u16 net-_u15-pad6_ net-_u1-pad10_ d_inverter
+* u17 net-_u15-pad5_ net-_u1-pad11_ d_inverter
+* u18 net-_u1-pad13_ net-_u18-pad2_ d_inverter
+* u20 net-_u19-pad6_ net-_u20-pad2_ d_inverter
+* u21 net-_u19-pad5_ net-_u21-pad2_ d_inverter
+* u15 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_dff
+* u13 net-_u11-pad5_ net-_u1-pad6_ d_inverter
+* u12 net-_u11-pad6_ net-_u1-pad7_ d_inverter
+* u10 net-_u1-pad5_ net-_u10-pad2_ d_inverter
+* u14 net-_u1-pad12_ net-_u14-pad2_ d_inverter
+* u11 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_dff
+* u8 net-_u7-pad6_ net-_u1-pad2_ d_inverter
+* u9 net-_u7-pad5_ net-_u1-pad3_ d_inverter
+* u6 net-_u3-pad2_ net-_u11-pad4_ d_inverter
+* u5 net-_u2-pad2_ net-_u11-pad2_ d_inverter
+* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u4 net-_u1-pad4_ net-_u4-pad2_ d_inverter
+* u7 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ d_dff
+a1 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ u19
+a2 net-_u15-pad6_ net-_u1-pad10_ u16
+a3 net-_u15-pad5_ net-_u1-pad11_ u17
+a4 net-_u1-pad13_ net-_u18-pad2_ u18
+a5 net-_u19-pad6_ net-_u20-pad2_ u20
+a6 net-_u19-pad5_ net-_u21-pad2_ u21
+a7 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15
+a8 net-_u11-pad5_ net-_u1-pad6_ u13
+a9 net-_u11-pad6_ net-_u1-pad7_ u12
+a10 net-_u1-pad5_ net-_u10-pad2_ u10
+a11 net-_u1-pad12_ net-_u14-pad2_ u14
+a12 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11
+a13 net-_u7-pad6_ net-_u1-pad2_ u8
+a14 net-_u7-pad5_ net-_u1-pad3_ u9
+a15 net-_u3-pad2_ net-_u11-pad4_ u6
+a16 net-_u2-pad2_ net-_u11-pad2_ u5
+a17 net-_u1-pad1_ net-_u3-pad2_ u3
+a18 net-_u1-pad9_ net-_u2-pad2_ u2
+a19 net-_u1-pad4_ net-_u4-pad2_ u4
+a20 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ u7
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u19 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC175
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Previous_Values.xml
new file mode 100644
index 000000000..fa06fcd98
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u19 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u19><u16 name="type">d_inverter<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_inverter<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_inverter<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u21><u15 name="type">d_dff<field26 name="Enter Clk Delay (default=1.0e-9)" /><field27 name="Enter Set Delay (default=1.0e-9)" /><field28 name="Enter Reset Delay (default=1.0)" /><field29 name="Enter IC (default=0)" /><field30 name="Enter value for Data Load (default=1.0e-12)" /><field31 name="Enter value for Clk Load (default=1.0e-12)" /><field32 name="Enter value for Set Load (default=1.0e-12)" /><field33 name="Enter value for Reset Load (default=1.0e-12)" /><field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /></u15><u13 name="type">d_inverter<field36 name="Enter Rise Delay (default=1.0e-9)" /><field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /></u12><u10 name="type">d_inverter<field42 name="Enter Rise Delay (default=1.0e-9)" /><field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_dff<field48 name="Enter Clk Delay (default=1.0e-9)" /><field49 name="Enter Set Delay (default=1.0e-9)" /><field50 name="Enter Reset Delay (default=1.0)" /><field51 name="Enter IC (default=0)" /><field52 name="Enter value for Data Load (default=1.0e-12)" /><field53 name="Enter value for Clk Load (default=1.0e-12)" /><field54 name="Enter value for Set Load (default=1.0e-12)" /><field55 name="Enter value for Reset Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /></u11><u8 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u9><u6 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u6><u5 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u5><u3 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_dff<field79 name="Enter Clk Delay (default=1.0e-9)" /><field80 name="Enter Set Delay (default=1.0e-9)" /><field81 name="Enter Reset Delay (default=1.0)" /><field82 name="Enter IC (default=0)" /><field83 name="Enter value for Data Load (default=1.0e-12)" /><field84 name="Enter value for Clk Load (default=1.0e-12)" /><field85 name="Enter value for Set Load (default=1.0e-12)" /><field86 name="Enter value for Reset Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.cir b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.cir
new file mode 100644
index 000000000..901876de6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.cir
@@ -0,0 +1,23 @@
+.title KiCad schematic
+U19 Net-_U18-Pad2_ Net-_U11-Pad2_ unconnected-_U19-Pad3_ Net-_U11-Pad4_ Net-_U19-Pad5_ Net-_U19-Pad6_ d_dff
+U16 Net-_U15-Pad6_ Net-_U1-Pad10_ d_inverter
+U17 Net-_U15-Pad5_ Net-_U1-Pad11_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ GND Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U21-Pad2_ Net-_U20-Pad2_ GND PORT
+U18 Net-_U1-Pad13_ Net-_U18-Pad2_ d_inverter
+U20 Net-_U19-Pad6_ Net-_U20-Pad2_ d_inverter
+U21 Net-_U19-Pad5_ Net-_U21-Pad2_ d_inverter
+U15 Net-_U14-Pad2_ Net-_U11-Pad2_ unconnected-_U15-Pad3_ Net-_U11-Pad4_ Net-_U15-Pad5_ Net-_U15-Pad6_ d_dff
+U13 Net-_U11-Pad5_ Net-_U1-Pad6_ d_inverter
+U12 Net-_U11-Pad6_ Net-_U1-Pad7_ d_inverter
+U10 Net-_U1-Pad5_ Net-_U10-Pad2_ d_inverter
+U14 Net-_U1-Pad12_ Net-_U14-Pad2_ d_inverter
+U11 Net-_U10-Pad2_ Net-_U11-Pad2_ unconnected-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ d_dff
+U8 Net-_U7-Pad6_ Net-_U1-Pad2_ d_inverter
+U9 Net-_U7-Pad5_ Net-_U1-Pad3_ d_inverter
+U6 Net-_U3-Pad2_ Net-_U11-Pad4_ d_inverter
+U5 Net-_U2-Pad2_ Net-_U11-Pad2_ d_inverter
+U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+U4 Net-_U1-Pad4_ Net-_U4-Pad2_ d_inverter
+U7 Net-_U4-Pad2_ Net-_U11-Pad2_ unconnected-_U7-Pad3_ Net-_U11-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad6_ d_dff
+.end
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.cir.out b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.cir.out
new file mode 100644
index 000000000..893dc9ac0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.cir.out
@@ -0,0 +1,92 @@
+.title kicad schematic
+
+* u19 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ d_dff
+* u16 net-_u15-pad6_ net-_u1-pad10_ d_inverter
+* u17 net-_u15-pad5_ net-_u1-pad11_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u21-pad2_ net-_u20-pad2_ gnd port
+* u18 net-_u1-pad13_ net-_u18-pad2_ d_inverter
+* u20 net-_u19-pad6_ net-_u20-pad2_ d_inverter
+* u21 net-_u19-pad5_ net-_u21-pad2_ d_inverter
+* u15 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_dff
+* u13 net-_u11-pad5_ net-_u1-pad6_ d_inverter
+* u12 net-_u11-pad6_ net-_u1-pad7_ d_inverter
+* u10 net-_u1-pad5_ net-_u10-pad2_ d_inverter
+* u14 net-_u1-pad12_ net-_u14-pad2_ d_inverter
+* u11 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_dff
+* u8 net-_u7-pad6_ net-_u1-pad2_ d_inverter
+* u9 net-_u7-pad5_ net-_u1-pad3_ d_inverter
+* u6 net-_u3-pad2_ net-_u11-pad4_ d_inverter
+* u5 net-_u2-pad2_ net-_u11-pad2_ d_inverter
+* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u4 net-_u1-pad4_ net-_u4-pad2_ d_inverter
+* u7 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ d_dff
+a1 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ u19
+a2 net-_u15-pad6_ net-_u1-pad10_ u16
+a3 net-_u15-pad5_ net-_u1-pad11_ u17
+a4 net-_u1-pad13_ net-_u18-pad2_ u18
+a5 net-_u19-pad6_ net-_u20-pad2_ u20
+a6 net-_u19-pad5_ net-_u21-pad2_ u21
+a7 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15
+a8 net-_u11-pad5_ net-_u1-pad6_ u13
+a9 net-_u11-pad6_ net-_u1-pad7_ u12
+a10 net-_u1-pad5_ net-_u10-pad2_ u10
+a11 net-_u1-pad12_ net-_u14-pad2_ u14
+a12 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11
+a13 net-_u7-pad6_ net-_u1-pad2_ u8
+a14 net-_u7-pad5_ net-_u1-pad3_ u9
+a15 net-_u3-pad2_ net-_u11-pad4_ u6
+a16 net-_u2-pad2_ net-_u11-pad2_ u5
+a17 net-_u1-pad1_ net-_u3-pad2_ u3
+a18 net-_u1-pad9_ net-_u2-pad2_ u2
+a19 net-_u1-pad4_ net-_u4-pad2_ u4
+a20 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ u7
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u19 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.kicad_sch b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.kicad_sch
new file mode 100644
index 000000000..0b1d348d4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.kicad_sch
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+    (pin "20" (uuid 2b6640a3-d212-4928-9a27-033833d6606c))
+    (pin "21" (uuid 854eb5ef-4f50-4f4e-95d3-0ccd2ae1a7cd))
+    (pin "22" (uuid fb3fe3ac-c51a-425d-acd5-180e4a24d706))
+    (pin "23" (uuid 7aac0dbf-469a-4ca6-a932-124f46608858))
+    (pin "24" (uuid 8ff9294b-be95-472a-86a7-97921b929958))
+    (pin "25" (uuid f031b646-c0bf-4fd9-b61a-4a4eb29975fa))
+    (pin "26" (uuid dafc79ed-d702-4993-a6ba-d6b80d6d0aad))
+  )
+
+  (symbol (lib_id "eSim_Power:eSim_GND") (at 33.02 156.21 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f8bac145-7d62-466b-9a88-dda830a8dbb5)
+    (property "Reference" "#PWR02" (id 0) (at 33.02 162.56 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "eSim_GND" (id 1) (at 33.02 161.29 0))
+    (property "Footprint" "" (id 2) (at 33.02 156.21 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 33.02 156.21 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 698bc2c1-d111-4d40-9fdb-1b027dafac6d))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/579463f7-e237-4121-8400-51bf54a01773"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/f8bac145-7d62-466b-9a88-dda830a8dbb5"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/0b7e9abc-5a81-4f58-b151-9456acbb0cce"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/0c76cdd6-b5bf-4a87-a3ab-bac5bf36d263"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/ab330272-c9c8-4a53-8b79-744e7e15c315"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/a9faa5bb-19a3-403e-bd70-c0d7ca035948"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/f3a30cba-cc4e-4587-9b04-db6549bbc481"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/48c236d7-92d0-4a12-ab7d-b0d05a245a74"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/e5a318a0-b24e-411e-be3e-784b4066bc28"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/7501fad9-cd80-497f-ad77-c98aeffd8712"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/dbdadaac-c561-44f3-9792-cfe65bde1af1"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/c62b9f5c-b8a0-4406-816a-83b30997103c"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/6042aede-43e0-4d48-be1e-5d2cf213b1ef"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/0e96f6a6-9ce7-4703-9db5-48ffd1bdce24"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/2cef7bc4-3c35-4521-9949-7623d21b3da4"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/21d6a7cd-c8b1-41ea-98fd-aace6210c5f7"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/c38155c5-1f69-4969-9119-73a693ae4d16"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/61fb3525-4e51-47f4-8de4-d2deb3a3dac0"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/2a78165c-80b3-4c0a-82d5-a3e422880f71"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/839c198a-b872-400e-934c-608bdb53402f"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/adea3196-2cf2-41e9-95b8-363ccc73e76c"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/b7fe52fd-30ca-42d8-a5c8-8e884b0221d9"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/da769909-adb9-4050-bc7c-6b04a5bf2bf7"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/db63c4a5-488a-4c73-b7c4-5e7c934960d5"
+      (reference "U7") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/446e6e11-316c-4f38-ba51-e4c94879af97"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a6507eb9-a339-423d-8faa-983a6c11b554"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3d646cf4-394c-4e1a-bedd-f85694f99585"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/ebe1817e-b97e-4fb4-a00c-2cd7497457d4"
+      (reference "U11") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/6ca6239c-bb5b-4031-9e4b-824201fb60db"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/59d73813-fd8e-4273-b307-053010994ac9"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/98c7afd4-97e7-481c-b7ac-b54c3be564e8"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3aec90bc-0e89-4973-ac8e-b13373bd9369"
+      (reference "U15") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/e47972e5-e896-4a31-8511-e713981ef45e"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8fa10b8e-a0f2-46c9-a129-3cea4ecff966"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/e7efb678-2f84-41fc-8957-ef7207266418"
+      (reference "U18") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/263d3fe5-3260-46ec-a291-ddd6c530f86e"
+      (reference "U19") (unit 1) (value "d_dff") (footprint "")
+    )
+    (path "/ad7eb8de-5a92-4b6d-bc81-1ccfdfb12967"
+      (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a493cdec-12c9-4458-845a-45669fa02805"
+      (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.sub b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.sub
new file mode 100644
index 000000000..2dd965992
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175.sub
@@ -0,0 +1,86 @@
+* Subcircuit 74HC175
+.subckt 74HC175 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u21-pad2_ net-_u20-pad2_ gnd 
+.title kicad schematic
+* u19 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ d_dff
+* u16 net-_u15-pad6_ net-_u1-pad10_ d_inverter
+* u17 net-_u15-pad5_ net-_u1-pad11_ d_inverter
+* u18 net-_u1-pad13_ net-_u18-pad2_ d_inverter
+* u20 net-_u19-pad6_ net-_u20-pad2_ d_inverter
+* u21 net-_u19-pad5_ net-_u21-pad2_ d_inverter
+* u15 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_dff
+* u13 net-_u11-pad5_ net-_u1-pad6_ d_inverter
+* u12 net-_u11-pad6_ net-_u1-pad7_ d_inverter
+* u10 net-_u1-pad5_ net-_u10-pad2_ d_inverter
+* u14 net-_u1-pad12_ net-_u14-pad2_ d_inverter
+* u11 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_dff
+* u8 net-_u7-pad6_ net-_u1-pad2_ d_inverter
+* u9 net-_u7-pad5_ net-_u1-pad3_ d_inverter
+* u6 net-_u3-pad2_ net-_u11-pad4_ d_inverter
+* u5 net-_u2-pad2_ net-_u11-pad2_ d_inverter
+* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u4 net-_u1-pad4_ net-_u4-pad2_ d_inverter
+* u7 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ d_dff
+a1 net-_u18-pad2_ net-_u11-pad2_ unconnected-_u19-pad3_ net-_u11-pad4_ net-_u19-pad5_ net-_u19-pad6_ u19
+a2 net-_u15-pad6_ net-_u1-pad10_ u16
+a3 net-_u15-pad5_ net-_u1-pad11_ u17
+a4 net-_u1-pad13_ net-_u18-pad2_ u18
+a5 net-_u19-pad6_ net-_u20-pad2_ u20
+a6 net-_u19-pad5_ net-_u21-pad2_ u21
+a7 net-_u14-pad2_ net-_u11-pad2_ unconnected-_u15-pad3_ net-_u11-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15
+a8 net-_u11-pad5_ net-_u1-pad6_ u13
+a9 net-_u11-pad6_ net-_u1-pad7_ u12
+a10 net-_u1-pad5_ net-_u10-pad2_ u10
+a11 net-_u1-pad12_ net-_u14-pad2_ u14
+a12 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11
+a13 net-_u7-pad6_ net-_u1-pad2_ u8
+a14 net-_u7-pad5_ net-_u1-pad3_ u9
+a15 net-_u3-pad2_ net-_u11-pad4_ u6
+a16 net-_u2-pad2_ net-_u11-pad2_ u5
+a17 net-_u1-pad1_ net-_u3-pad2_ u3
+a18 net-_u1-pad9_ net-_u2-pad2_ u2
+a19 net-_u1-pad4_ net-_u4-pad2_ u4
+a20 net-_u4-pad2_ net-_u11-pad2_ unconnected-_u7-pad3_ net-_u11-pad4_ net-_u7-pad5_ net-_u7-pad6_ u7
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u19 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_dff, Ngspice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC175
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_Previous_Values.xml
new file mode 100644
index 000000000..fa06fcd98
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u19 name="type">d_dff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for Data Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u19><u16 name="type">d_inverter<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_inverter<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_inverter<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u21><u15 name="type">d_dff<field26 name="Enter Clk Delay (default=1.0e-9)" /><field27 name="Enter Set Delay (default=1.0e-9)" /><field28 name="Enter Reset Delay (default=1.0)" /><field29 name="Enter IC (default=0)" /><field30 name="Enter value for Data Load (default=1.0e-12)" /><field31 name="Enter value for Clk Load (default=1.0e-12)" /><field32 name="Enter value for Set Load (default=1.0e-12)" /><field33 name="Enter value for Reset Load (default=1.0e-12)" /><field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /></u15><u13 name="type">d_inverter<field36 name="Enter Rise Delay (default=1.0e-9)" /><field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /></u13><u12 name="type">d_inverter<field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /></u12><u10 name="type">d_inverter<field42 name="Enter Rise Delay (default=1.0e-9)" /><field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_inverter<field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_dff<field48 name="Enter Clk Delay (default=1.0e-9)" /><field49 name="Enter Set Delay (default=1.0e-9)" /><field50 name="Enter Reset Delay (default=1.0)" /><field51 name="Enter IC (default=0)" /><field52 name="Enter value for Data Load (default=1.0e-12)" /><field53 name="Enter value for Clk Load (default=1.0e-12)" /><field54 name="Enter value for Set Load (default=1.0e-12)" /><field55 name="Enter value for Reset Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /></u11><u8 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u9><u6 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u6><u5 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u5><u3 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u4><u7 name="type">d_dff<field79 name="Enter Clk Delay (default=1.0e-9)" /><field80 name="Enter Set Delay (default=1.0e-9)" /><field81 name="Enter Reset Delay (default=1.0)" /><field82 name="Enter IC (default=0)" /><field83 name="Enter value for Data Load (default=1.0e-12)" /><field84 name="Enter value for Clk Load (default=1.0e-12)" /><field85 name="Enter value for Set Load (default=1.0e-12)" /><field86 name="Enter value for Reset Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.cir b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.cir
new file mode 100644
index 000000000..330dc254b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.cir
@@ -0,0 +1,24 @@
+.title KiCad schematic
+X1 Net-_U6-Pad8_ Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U6-Pad7_ Net-_U6-Pad6_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U13-Pad2_ Net-_U12-Pad2_ Net-_U7-Pad4_ Net-_U7-Pad3_ Net-_U6-Pad10_ Net-_U6-Pad9_ Net-_U7-Pad2_ Net-_U7-Pad1_ Net-_v2-Pad1_ 74HC175
+U13 GND Net-_U13-Pad2_ adc_bridge_1
+V_D2 Net-_V_D2-Pad1_ GND DC
+V_D3 Net-_V_D3-Pad1_ GND DC
+V_D0 Net-_V_D0-Pad1_ GND DC
+V_D1 Net-_V_D1-Pad1_ GND DC
+V_MR_n1 Net-_V_MR_n1-Pad1_ GND DC
+U6 Net-_V_D1-Pad1_ Net-_V_D0-Pad1_ Net-_V_MR_n1-Pad1_ Net-_V_D3-Pad1_ Net-_V_D2-Pad1_ Net-_U6-Pad6_ Net-_U6-Pad7_ Net-_U6-Pad8_ Net-_U6-Pad9_ Net-_U6-Pad10_ adc_bridge_5
+v2 Net-_v2-Pad1_ GND 5
+U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ V_Q0 V_Q0_n V_Q1_n V_Q1 dac_bridge_4
+U4 V_Q0 plot_v1
+U9 V_Q3_n plot_v1
+U10 V_Q2_n plot_v1
+U11 V_Q2 plot_v1
+U8 V_Q3 plot_v1
+V_CP1 V_CP GND pulse
+U1 V_Q1 plot_v1
+U2 V_Q1_n plot_v1
+U3 V_Q0_n plot_v1
+U12 V_CP Net-_U12-Pad2_ adc_bridge_1
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U7-Pad4_ V_Q3 V_Q3_n V_Q2_n V_Q2 dac_bridge_4
+U14 V_CP plot_v1
+.end
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.cir.out b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.cir.out
new file mode 100644
index 000000000..1ec097869
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.cir.out
@@ -0,0 +1,58 @@
+.title kicad schematic
+
+.include 74HC175.sub
+x1 net-_u6-pad8_ net-_u5-pad1_ net-_u5-pad2_ net-_u6-pad7_ net-_u6-pad6_ net-_u5-pad3_ net-_u5-pad4_ net-_u13-pad2_ net-_u12-pad2_ net-_u7-pad4_ net-_u7-pad3_ net-_u6-pad10_ net-_u6-pad9_ net-_u7-pad2_ net-_u7-pad1_ net-_v2-pad1_ 74HC175
+* u13 gnd net-_u13-pad2_ adc_bridge_1
+v_d2 net-_v_d2-pad1_ gnd  dc 0
+v_d3 net-_v_d3-pad1_ gnd  dc 5
+v_d0 net-_v_d0-pad1_ gnd  dc 0
+v_d1 net-_v_d1-pad1_ gnd  dc 0
+v_mr_n1 net-_v_mr_n1-pad1_ gnd  dc 5
+* u6 net-_v_d1-pad1_ net-_v_d0-pad1_ net-_v_mr_n1-pad1_ net-_v_d3-pad1_ net-_v_d2-pad1_ net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ net-_u6-pad9_ net-_u6-pad10_ adc_bridge_5
+v2 net-_v2-pad1_ gnd 5
+* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ v_q0 v_q0_n v_q1_n v_q1 dac_bridge_4
+* u4 v_q0 plot_v1
+* u9 v_q3_n plot_v1
+* u10 v_q2_n plot_v1
+* u11 v_q2 plot_v1
+* u8 v_q3 plot_v1
+v_cp1 v_cp gnd pulse(0 5 0 1n 1n 5 10)
+* u1 v_q1 plot_v1
+* u2 v_q1_n plot_v1
+* u3 v_q0_n plot_v1
+* u12 v_cp net-_u12-pad2_ adc_bridge_1
+* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u7-pad3_ net-_u7-pad4_ v_q3 v_q3_n v_q2_n v_q2 dac_bridge_4
+* u14 v_cp plot_v1
+a1 [gnd ] [net-_u13-pad2_ ] u13
+a2 [net-_v_d1-pad1_ net-_v_d0-pad1_ net-_v_mr_n1-pad1_ net-_v_d3-pad1_ net-_v_d2-pad1_ ] [net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ net-_u6-pad9_ net-_u6-pad10_ ] u6
+a3 [net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ ] [v_q0 v_q0_n v_q1_n v_q1 ] u5
+a4 [v_cp ] [net-_u12-pad2_ ] u12
+a5 [net-_u7-pad1_ net-_u7-pad2_ net-_u7-pad3_ net-_u7-pad4_ ] [v_q3 v_q3_n v_q2_n v_q2 ] u7
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_5, Ngspice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 1e-00 20e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_q0)
+plot v(v_q3_n)
+plot v(v_q2_n)
+plot v(v_q2)
+plot v(v_q3)
+plot v(v_q1)
+plot v(v_q1_n)
+plot v(v_q0_n)
+plot v(v_cp)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.kicad_sch b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.kicad_sch
new file mode 100644
index 000000000..e6fec46f1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.kicad_sch
@@ -0,0 +1,1490 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid f8810317-ed50-4d19-bd90-770ef60b4732)
+
+  (paper "A3")
+
+  (lib_symbols
+    (symbol "eSim_Hybrid:adc_bridge_1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_1" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_1_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "adc_bridge_1_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 1.27 180) (length 5.08)
+          (name "OUT1" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:adc_bridge_5" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_5" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_5_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -10.16)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "adc_bridge_5_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -8.89 180) (length 5.08)
+          (name "OUT5" (effects (font (size 1.27 1.27))))
+          (number "10" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -1.27 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -3.81 0) (length 5.08)
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+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -6.35 0) (length 5.08)
+          (name "IN4" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -15.24 -8.89 0) (length 5.08)
+          (name "IN5" (effects (font (size 1.27 1.27))))
+          (number "5" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 1.27 180) (length 5.08)
+          (name "OUT1" (effects (font (size 1.27 1.27))))
+          (number "6" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -1.27 180) (length 5.08)
+          (name "OUT2" (effects (font (size 1.27 1.27))))
+          (number "7" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -3.81 180) (length 5.08)
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+          (number "8" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -6.35 180) (length 5.08)
+          (name "OUT4" (effects (font (size 1.27 1.27))))
+          (number "9" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:dac_bridge_4" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "dac_bridge_4" (id 1) (at 0 7.62 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "dac_bridge_4_0_1"
+        (rectangle (start -8.89 8.89) (end 8.89 -5.08)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "dac_bridge_4_1_1"
+        (pin input line (at -13.97 5.08 0) (length 5.08)
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+          (number "8" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
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+      (property "Reference" "U" (id 0) (at 0 12.7 0)
+        (effects (font (size 1.524 1.524)))
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+        (circle (center 0 12.7) (radius 2.54)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
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+      (symbol "plot_v1_1_1"
+        (pin input line (at 0 5.08 90) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "~" (effects (font (size 1.27 1.27))))
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+      )
+    )
+    (symbol "eSim_Power:eSim_GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "#PWR" (id 0) (at 0 -6.35 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Value" "eSim_GND" (id 1) (at 0 -3.81 0)
+        (effects (font (size 1.27 1.27)))
+      )
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+        (effects (font (size 1.27 1.27)) hide)
+      )
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+        (effects (font (size 1.27 1.27)) hide)
+      )
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+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "eSim_GND_1_1"
+        (pin power_in line (at 0 0 270) (length 0) hide
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+      )
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+    )
+    (path "/69045a69-6c02-469e-aa0a-1e2c20236836"
+      (reference "U4") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/756b7d71-7fc5-4b28-ac5c-a99ffde7fead"
+      (reference "U5") (unit 1) (value "dac_bridge_4") (footprint "")
+    )
+    (path "/815ec2a2-864d-41ff-ad50-447ade732cfc"
+      (reference "U6") (unit 1) (value "adc_bridge_5") (footprint "")
+    )
+    (path "/499edc05-6a24-4900-ba9a-532d5fa68e1d"
+      (reference "U7") (unit 1) (value "dac_bridge_4") (footprint "")
+    )
+    (path "/f063d719-ef4b-4c1d-9f08-5c9dc0443f81"
+      (reference "U8") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/bc2a2bdb-8d72-4dbd-b3a2-e69e52b203ef"
+      (reference "U9") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/10ff7a18-ee89-4fae-b14f-0f4a9173afea"
+      (reference "U10") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/5bff5534-87e1-4da6-8015-e26865f8e45a"
+      (reference "U11") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/1ad1bf0c-4752-44b5-bc82-f856af78b7ae"
+      (reference "U12") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
+    (path "/861b1002-4435-470a-a4de-fb1283fa11d1"
+      (reference "U13") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
+    (path "/8e5675a1-ffb7-46f3-87a9-dd5739f33202"
+      (reference "U14") (unit 1) (value "plot_v1") (footprint "")
+    )
+    (path "/42b4d900-413e-4505-89f4-6680d8f7f916"
+      (reference "V_CP1") (unit 1) (value "pulse") (footprint "R1")
+    )
+    (path "/5761f076-93bb-4b0c-8d53-e506484551bc"
+      (reference "V_D0") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/f496afec-0290-46f2-9f64-9994166d3104"
+      (reference "V_D1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/d85d257b-eae1-4b16-afbd-c304da79565d"
+      (reference "V_D2") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/bf028714-4120-4bb0-b579-5d89868bf1eb"
+      (reference "V_D3") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/0f806c57-89e6-40b4-9acc-9d8d834a5da1"
+      (reference "V_MR_n1") (unit 1) (value "DC") (footprint "R1")
+    )
+    (path "/4d6bb370-c1de-4c82-9b26-2344f86e7086"
+      (reference "X1") (unit 1) (value "74HC175") (footprint "")
+    )
+    (path "/c8b9face-b347-4b39-a5df-3a2a1e6cb607"
+      (reference "v2") (unit 1) (value "5") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.proj b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.proj
new file mode 100644
index 000000000..29cf4d7e1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.proj
@@ -0,0 +1 @@
+schematicFile 74HC175_TEST.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.raw b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.raw
new file mode 100644
index 000000000..a038b19da
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST.raw
@@ -0,0 +1,6376 @@
+Title: kicad schematic
+Date: Sat Jan 03 20:00:56  2026
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 32
+No. Points: 198     
+Variables:
+	0	time	time
+	1	v(net-_v_d2-pad1_)	voltage
+	2	v(net-_v_d3-pad1_)	voltage
+	3	v(net-_v_d0-pad1_)	voltage
+	4	v(net-_v_d1-pad1_)	voltage
+	5	v(net-_v_mr_n1-pad1_)	voltage
+	6	v(net-_v2-pad1_)	voltage
+	7	v(v_cp)	voltage
+	8	v(gnd)	voltage
+	9	v(v_q0)	voltage
+	10	v(v_q0_n)	voltage
+	11	v(v_q1_n)	voltage
+	12	v(v_q1)	voltage
+	13	v(v_q3)	voltage
+	14	v(v_q3_n)	voltage
+	15	v(v_q2_n)	voltage
+	16	v(v_q2)	voltage
+	17	i(v_cp1)	current
+	18	i(v2)	current
+	19	i(v_mr_n1)	current
+	20	i(v_d1)	current
+	21	i(v_d0)	current
+	22	i(v_d3)	current
+	23	i(v_d2)	current
+	24	i(a5)	current
+	25	i(a5)	current
+	26	i(a5)	current
+	27	i(a5)	current
+	28	i(a3)	current
+	29	i(a3)	current
+	30	i(a3)	current
+	31	i(a3)	current
+Values:
+0		0.000000000000000e+00
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diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST_Previous_Values.xml
new file mode 100644
index 000000000..6d6a0360e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/74HC175_TEST_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v_d2 name="Source type">dc<field1 name="Value">0</field1></v_d2><v_d3 name="Source type">dc<field1 name="Value">5</field1></v_d3><v_d0 name="Source type">dc<field1 name="Value">0</field1></v_d0><v_d1 name="Source type">dc<field1 name="Value">0</field1></v_d1><v_mr_n1 name="Source type">dc<field1 name="Value">5</field1></v_mr_n1><v2 name="Source type">5</v2><v1 name="Source type">0</v1><v1 name="Source type">5</v1><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">5</field5><field5 name="Period">10</field5></v1><v_cp1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">5</field5><field5 name="Period">10</field5></v_cp1></source><model><u5 name="type">dac_bridge<field1 name="Enter value for out_low (default=0.0)" /><field2 name="Enter value for out_high (default=5.0)" /><field3 name="Enter value for out_undef (default=0.5)" /><field4 name="Enter value for input load (default=1.0e-12)" /><field5 name="Enter the Rise Time (default=1.0e-9)" /><field6 name="Enter the Fall Time (default=1.0e-9)" /></u5><u6 name="type">adc_bridge<field7 name="Enter value for in_low (default=1.0)" /><field8 name="Enter value for in_high (default=2.0)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u6><u7 name="type">dac_bridge<field11 name="Enter value for out_low (default=0.0)" /><field12 name="Enter value for out_high (default=5.0)" /><field13 name="Enter value for out_undef (default=0.5)" /><field14 name="Enter value for input load (default=1.0e-12)" /><field15 name="Enter the Rise Time (default=1.0e-9)" /><field16 name="Enter the Fall Time (default=1.0e-9)" /></u7><u12 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC175</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">20</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/_autosave-74HC175.sch b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/_autosave-74HC175.sch
new file mode 100644
index 000000000..5d3dcea08
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/_autosave-74HC175.sch
@@ -0,0 +1,563 @@
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+F 2 "" H 1275 6575 50  0001 C CNN
+F 3 "" H 1275 6575 50  0001 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+F 1 "eSim_GND" H 1300 5950 50  0000 C CNN
+F 2 "" H 1300 6150 50  0001 C CNN
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+	1    1300 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 8 1 00000000
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+F 1 "PORT" H 850 6175 30  0000 C CNN
+F 2 "" H 825 6100 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 9 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
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+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 16 1 00000000
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+	1    0    0    -1  
+$EndComp
+$Comp
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+$EndComp
+$Comp
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+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
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+	0    -1   -1   0   
+$EndComp
+$Comp
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+	5    4225 1025
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 7 1 00000000
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+F 1 "PORT" V 5475 6275 30  0000 R CNN
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+F 3 "" H 5525 6350 60  0000 C CNN
+	7    5525 6350
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+$EndComp
+$Comp
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+U 6 1 00000000
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+F 2 "" H 6100 6350 60  0000 C CNN
+F 3 "" H 6100 6350 60  0000 C CNN
+	6    6100 6350
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+$EndComp
+$Comp
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+U 12 1 00000000
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+$EndComp
+$Comp
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+	10   7550 6350
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 11 1 00000000
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+F 2 "" H 8275 6350 60  0000 C CNN
+F 3 "" H 8275 6350 60  0000 C CNN
+	11   8275 6350
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
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+	13   8500 1000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
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+$EndComp
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+F 2 "" H 1700 4525 60  0000 C CNN
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+$EndComp
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+F 2 "" H 2500 4525 60  0000 C CNN
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+$EndComp
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+	1    9200 2750
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+$EndComp
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diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/analysis b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/analysis
new file mode 100644
index 000000000..69aaab65a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/74HC175_Test_Circuit/74HC175_TEST/analysis
@@ -0,0 +1 @@
+.tran 1e-00 20e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/_autosave-74HC175.sch b/library/SubcircuitLibrary/IC74HC175/74HC175/_autosave-74HC175.sch
new file mode 100644
index 000000000..5d3dcea08
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/_autosave-74HC175.sch
@@ -0,0 +1,563 @@
+EESchema Schematic File Version 5
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+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
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+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 2850 4000
+Connection ~ 2975 4575
+Connection ~ 4425 4000
+Connection ~ 4975 4575
+Connection ~ 6450 4000
+Connection ~ 7000 4575
+Wire Wire Line
+	1100 4000 1325 4000
+Wire Wire Line
+	1100 4575 1350 4575
+Wire Wire Line
+	1275 6550 1100 6550
+Wire Wire Line
+	1275 6575 1275 6550
+Wire Wire Line
+	1300 6100 1075 6100
+Wire Wire Line
+	1300 6150 1300 6100
+Wire Wire Line
+	1925 4000 2150 4000
+Wire Wire Line
+	1950 4575 2150 4575
+Wire Wire Line
+	2000 1350 2000 1600
+Wire Wire Line
+	2000 2200 2000 2400
+Wire Wire Line
+	2425 2400 2000 2400
+Wire Wire Line
+	2425 3050 2425 3450
+Wire Wire Line
+	2425 3450 2850 3450
+Wire Wire Line
+	2750 4000 2850 4000
+Wire Wire Line
+	2850 3450 2850 4000
+Wire Wire Line
+	2850 4000 4425 4000
+Wire Wire Line
+	2975 3350 2975 4575
+Wire Wire Line
+	2975 4575 2750 4575
+Wire Wire Line
+	2975 4575 4975 4575
+Wire Wire Line
+	3525 2400 4025 2400
+Wire Wire Line
+	3525 3050 3525 5250
+Wire Wire Line
+	3525 5850 3525 6125
+Wire Wire Line
+	4025 2400 4025 5200
+Wire Wire Line
+	4050 5800 4025 5800
+Wire Wire Line
+	4050 6100 4050 5800
+Wire Wire Line
+	4225 1275 4225 1500
+Wire Wire Line
+	4225 2400 4225 2100
+Wire Wire Line
+	4425 2400 4225 2400
+Wire Wire Line
+	4425 3050 4425 4000
+Wire Wire Line
+	4425 4000 6450 4000
+Wire Wire Line
+	4975 3350 4975 4575
+Wire Wire Line
+	4975 4575 7000 4575
+Wire Wire Line
+	5525 2400 6100 2400
+Wire Wire Line
+	5525 3050 5525 5250
+Wire Wire Line
+	5525 5850 5525 6100
+Wire Wire Line
+	6100 2400 6100 5250
+Wire Wire Line
+	6100 5850 6100 6100
+Wire Wire Line
+	6250 1250 6250 1500
+Wire Wire Line
+	6250 2400 6250 2100
+Wire Wire Line
+	6450 2400 6250 2400
+Wire Wire Line
+	6450 3050 6450 4000
+Wire Wire Line
+	6450 4000 8650 4000
+Wire Wire Line
+	7000 3350 7000 4575
+Wire Wire Line
+	7000 4575 9200 4575
+Wire Wire Line
+	7550 2400 8275 2400
+Wire Wire Line
+	7550 3050 7550 5275
+Wire Wire Line
+	7550 5875 7550 6100
+Wire Wire Line
+	8275 2400 8275 5275
+Wire Wire Line
+	8275 5875 8275 6100
+Wire Wire Line
+	8500 1250 8500 1500
+Wire Wire Line
+	8500 2400 8500 2100
+Wire Wire Line
+	8650 2400 8500 2400
+Wire Wire Line
+	8650 4000 8650 3050
+Wire Wire Line
+	9200 3350 9200 4575
+Wire Wire Line
+	9750 2400 10500 2400
+Wire Wire Line
+	9750 3050 9750 5375
+Wire Wire Line
+	9750 5975 9750 6150
+Wire Wire Line
+	10500 2400 10500 5350
+Wire Wire Line
+	10500 5950 10500 6150
+$Comp
+L eSim_Power:eSim_GND #PWR01
+U 1 1 00000000
+P 1275 6575
+F 0 "#PWR01" H 1275 6325 50  0001 C CNN
+F 1 "eSim_GND" H 1275 6400 50  0000 C CNN
+F 2 "" H 1275 6575 50  0001 C CNN
+F 3 "" H 1275 6575 50  0001 C CNN
+	1    1275 6575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Power:eSim_GND #PWR02
+U 1 1 00000000
+P 1300 6150
+F 0 "#PWR02" H 1300 5900 50  0001 C CNN
+F 1 "eSim_GND" H 1300 5950 50  0000 C CNN
+F 2 "" H 1300 6150 50  0001 C CNN
+F 3 "" H 1300 6150 50  0001 C CNN
+	1    1300 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 8 1 00000000
+P 825 6100
+F 0 "U1" H 850 6275 30  0000 C CNN
+F 1 "PORT" H 850 6175 30  0000 C CNN
+F 2 "" H 825 6100 60  0000 C CNN
+F 3 "" H 825 6100 60  0000 C CNN
+	8    825  6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 9 1 00000000
+P 850 4000
+F 0 "U1" H 875 4175 30  0000 C CNN
+F 1 "PORT" H 875 4075 30  0000 C CNN
+F 2 "" H 850 4000 60  0000 C CNN
+F 3 "" H 850 4000 60  0000 C CNN
+	9    850  4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 1 1 00000000
+P 850 4575
+F 0 "U1" H 875 4775 30  0000 C CNN
+F 1 "PORT" H 875 4675 30  0000 C CNN
+F 2 "" H 850 4575 60  0000 C CNN
+F 3 "" H 850 4575 60  0000 C CNN
+	1    850  4575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 16 1 00000000
+P 850 6550
+F 0 "U1" H 875 6750 30  0000 C CNN
+F 1 "PORT" H 875 6650 30  0000 C CNN
+F 2 "" H 850 6550 60  0000 C CNN
+F 3 "" H 850 6550 60  0000 C CNN
+	16   850  6550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 4 1 00000000
+P 2000 1100
+F 0 "U1" V 2000 1000 30  0000 R CNN
+F 1 "PORT" V 2100 1000 30  0000 R CNN
+F 2 "" H 2000 1100 60  0000 C CNN
+F 3 "" H 2000 1100 60  0000 C CNN
+	4    2000 1100
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 2 1 00000000
+P 3525 6375
+F 0 "U1" V 3575 6300 30  0000 R CNN
+F 1 "PORT" V 3475 6300 30  0000 R CNN
+F 2 "" H 3525 6375 60  0000 C CNN
+F 3 "" H 3525 6375 60  0000 C CNN
+	2    3525 6375
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 3 1 00000000
+P 4050 6350
+F 0 "U1" V 4100 6250 30  0000 R CNN
+F 1 "PORT" V 4000 6250 30  0000 R CNN
+F 2 "" H 4050 6350 60  0000 C CNN
+F 3 "" H 4050 6350 60  0000 C CNN
+	3    4050 6350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 5 1 00000000
+P 4225 1025
+F 0 "U1" V 4225 950 30  0000 R CNN
+F 1 "PORT" V 4325 950 30  0000 R CNN
+F 2 "" H 4225 1025 60  0000 C CNN
+F 3 "" H 4225 1025 60  0000 C CNN
+	5    4225 1025
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 7 1 00000000
+P 5525 6350
+F 0 "U1" V 5575 6275 30  0000 R CNN
+F 1 "PORT" V 5475 6275 30  0000 R CNN
+F 2 "" H 5525 6350 60  0000 C CNN
+F 3 "" H 5525 6350 60  0000 C CNN
+	7    5525 6350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 6 1 00000000
+P 6100 6350
+F 0 "U1" V 6150 6275 30  0000 R CNN
+F 1 "PORT" V 6050 6275 30  0000 R CNN
+F 2 "" H 6100 6350 60  0000 C CNN
+F 3 "" H 6100 6350 60  0000 C CNN
+	6    6100 6350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 12 1 00000000
+P 6250 1000
+F 0 "U1" V 6250 900 30  0000 R CNN
+F 1 "PORT" V 6350 900 30  0000 R CNN
+F 2 "" H 6250 1000 60  0000 C CNN
+F 3 "" H 6250 1000 60  0000 C CNN
+	12   6250 1000
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 10 1 00000000
+P 7550 6350
+F 0 "U1" V 7600 6250 30  0000 R CNN
+F 1 "PORT" V 7500 6250 30  0000 R CNN
+F 2 "" H 7550 6350 60  0000 C CNN
+F 3 "" H 7550 6350 60  0000 C CNN
+	10   7550 6350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 11 1 00000000
+P 8275 6350
+F 0 "U1" V 8325 6275 30  0000 R CNN
+F 1 "PORT" V 8225 6275 30  0000 R CNN
+F 2 "" H 8275 6350 60  0000 C CNN
+F 3 "" H 8275 6350 60  0000 C CNN
+	11   8275 6350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 13 1 00000000
+P 8500 1000
+F 0 "U1" V 8500 900 30  0000 R CNN
+F 1 "PORT" V 8600 900 30  0000 R CNN
+F 2 "" H 8500 1000 60  0000 C CNN
+F 3 "" H 8500 1000 60  0000 C CNN
+	13   8500 1000
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 15 1 00000000
+P 9750 6400
+F 0 "U1" V 9800 6300 30  0000 R CNN
+F 1 "PORT" V 9700 6300 30  0000 R CNN
+F 2 "" H 9750 6400 60  0000 C CNN
+F 3 "" H 9750 6400 60  0000 C CNN
+	15   9750 6400
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 14 1 00000000
+P 10500 6400
+F 0 "U1" V 10550 6300 30  0000 R CNN
+F 1 "PORT" V 10450 6300 30  0000 R CNN
+F 2 "" H 10500 6400 60  0000 C CNN
+F 3 "" H 10500 6400 60  0000 C CNN
+	14   10500 6400
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U2
+U 1 1 00000000
+P 1625 4000
+F 0 "U2" H 1625 4250 60  0000 C CNN
+F 1 "d_inverter" H 1625 4100 60  0000 C CNN
+F 2 "" H 1675 3950 60  0000 C CNN
+F 3 "" H 1675 3950 60  0000 C CNN
+	1    1625 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U3
+U 1 1 00000000
+P 1650 4575
+F 0 "U3" H 1650 4850 60  0000 C CNN
+F 1 "d_inverter" H 1650 4700 60  0000 C CNN
+F 2 "" H 1700 4525 60  0000 C CNN
+F 3 "" H 1700 4525 60  0000 C CNN
+	1    1650 4575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U4
+U 1 1 00000000
+P 2000 1900
+F 0 "U4" V 1950 1800 60  0000 R CNN
+F 1 "d_inverter" V 2100 1800 60  0000 R CNN
+F 2 "" H 2050 1850 60  0000 C CNN
+F 3 "" H 2050 1850 60  0000 C CNN
+	1    2000 1900
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U5
+U 1 1 00000000
+P 2450 4000
+F 0 "U5" H 2450 4250 60  0000 C CNN
+F 1 "d_inverter" H 2450 4100 60  0000 C CNN
+F 2 "" H 2500 3950 60  0000 C CNN
+F 3 "" H 2500 3950 60  0000 C CNN
+	1    2450 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U6
+U 1 1 00000000
+P 2450 4575
+F 0 "U6" H 2450 4850 60  0000 C CNN
+F 1 "d_inverter" H 2450 4700 60  0000 C CNN
+F 2 "" H 2500 4525 60  0000 C CNN
+F 3 "" H 2500 4525 60  0000 C CNN
+	1    2450 4575
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U8
+U 1 1 00000000
+P 3525 5550
+F 0 "U8" V 3475 5475 60  0000 R CNN
+F 1 "d_inverter" V 3650 6050 60  0000 R CNN
+F 2 "" H 3575 5500 60  0000 C CNN
+F 3 "" H 3575 5500 60  0000 C CNN
+	1    3525 5550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U9
+U 1 1 00000000
+P 4025 5500
+F 0 "U9" V 3975 5425 60  0000 R CNN
+F 1 "d_inverter" V 4125 5425 60  0000 R CNN
+F 2 "" H 4075 5450 60  0000 C CNN
+F 3 "" H 4075 5450 60  0000 C CNN
+	1    4025 5500
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U10
+U 1 1 00000000
+P 4225 1800
+F 0 "U10" V 4175 1725 60  0000 R CNN
+F 1 "d_inverter" V 4325 1725 60  0000 R CNN
+F 2 "" H 4275 1750 60  0000 C CNN
+F 3 "" H 4275 1750 60  0000 C CNN
+	1    4225 1800
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U12
+U 1 1 00000000
+P 5525 5550
+F 0 "U12" V 5475 5475 60  0000 R CNN
+F 1 "d_inverter" V 5625 5475 60  0000 R CNN
+F 2 "" H 5575 5500 60  0000 C CNN
+F 3 "" H 5575 5500 60  0000 C CNN
+	1    5525 5550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U13
+U 1 1 00000000
+P 6100 5550
+F 0 "U13" V 6050 5450 60  0000 R CNN
+F 1 "d_inverter" V 6200 5450 60  0000 R CNN
+F 2 "" H 6150 5500 60  0000 C CNN
+F 3 "" H 6150 5500 60  0000 C CNN
+	1    6100 5550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 6250 1800
+F 0 "U14" V 6200 1700 60  0000 R CNN
+F 1 "d_inverter" V 6350 1700 60  0000 R CNN
+F 2 "" H 6300 1750 60  0000 C CNN
+F 3 "" H 6300 1750 60  0000 C CNN
+	1    6250 1800
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U16
+U 1 1 00000000
+P 7550 5575
+F 0 "U16" V 7500 5475 60  0000 R CNN
+F 1 "d_inverter" V 7650 5475 60  0000 R CNN
+F 2 "" H 7600 5525 60  0000 C CNN
+F 3 "" H 7600 5525 60  0000 C CNN
+	1    7550 5575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U17
+U 1 1 00000000
+P 8275 5575
+F 0 "U17" V 8225 5500 60  0000 R CNN
+F 1 "d_inverter" V 8375 5500 60  0000 R CNN
+F 2 "" H 8325 5525 60  0000 C CNN
+F 3 "" H 8325 5525 60  0000 C CNN
+	1    8275 5575
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U18
+U 1 1 00000000
+P 8500 1800
+F 0 "U18" V 8450 1700 60  0000 R CNN
+F 1 "d_inverter" V 8600 1700 60  0000 R CNN
+F 2 "" H 8550 1750 60  0000 C CNN
+F 3 "" H 8550 1750 60  0000 C CNN
+	1    8500 1800
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U20
+U 1 1 00000000
+P 9750 5675
+F 0 "U20" V 9700 5575 60  0000 R CNN
+F 1 "d_inverter" V 9850 5575 60  0000 R CNN
+F 2 "" H 9800 5625 60  0000 C CNN
+F 3 "" H 9800 5625 60  0000 C CNN
+	1    9750 5675
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U21
+U 1 1 00000000
+P 10500 5650
+F 0 "U21" V 10450 5550 60  0000 R CNN
+F 1 "d_inverter" V 10600 5550 60  0000 R CNN
+F 2 "" H 10550 5600 60  0000 C CNN
+F 3 "" H 10550 5600 60  0000 C CNN
+	1    10500 5650
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_dff U7
+U 1 1 00000000
+P 2975 2750
+F 0 "U7" H 3055 3400 60  0000 L CNN
+F 1 "d_dff" H 3055 3250 60  0000 L CNN
+F 2 "" H 2975 2750 60  0000 C CNN
+F 3 "" H 2975 2750 60  0000 C CNN
+	1    2975 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_dff U11
+U 1 1 00000000
+P 4975 2750
+F 0 "U11" H 5055 3400 60  0000 L CNN
+F 1 "d_dff" H 5055 3250 60  0000 L CNN
+F 2 "" H 4975 2750 60  0000 C CNN
+F 3 "" H 4975 2750 60  0000 C CNN
+	1    4975 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_dff U15
+U 1 1 00000000
+P 7000 2750
+F 0 "U15" H 7080 3400 60  0000 L CNN
+F 1 "d_dff" H 7080 3250 60  0000 L CNN
+F 2 "" H 7000 2750 60  0000 C CNN
+F 3 "" H 7000 2750 60  0000 C CNN
+	1    7000 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_dff U19
+U 1 1 00000000
+P 9200 2750
+F 0 "U19" H 9280 3400 60  0000 L CNN
+F 1 "d_dff" H 9280 3250 60  0000 L CNN
+F 2 "" H 9200 2750 60  0000 C CNN
+F 3 "" H 9200 2750 60  0000 C CNN
+	1    9200 2750
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC175/74HC175/analysis b/library/SubcircuitLibrary/IC74HC175/74HC175/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC175/74HC175/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.cir b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.cir
new file mode 100644
index 000000000..ef0921335
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.cir
@@ -0,0 +1,22 @@
+.title KiCad schematic
+X11 Net-_U1-Pad16_ Net-_U67-Pad3_ Net-_U1-Pad4_ buffer_tri
+X14 Net-_U1-Pad18_ Net-_U67-Pad3_ Net-_U1-Pad2_ buffer_tri
+X13 Net-_U1-Pad17_ Net-_U67-Pad3_ Net-_U1-Pad3_ buffer_tri
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ GND Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ GND PORT
+X15 Net-_U1-Pad15_ Net-_U67-Pad3_ Net-_U1-Pad5_ buffer_tri
+X9 Net-_U1-Pad12_ Net-_U67-Pad3_ Net-_U1-Pad8_ buffer_tri
+X16 Net-_U1-Pad11_ Net-_U67-Pad3_ Net-_U1-Pad9_ buffer_tri
+X10 Net-_U1-Pad14_ Net-_U67-Pad3_ Net-_U1-Pad6_ buffer_tri
+X12 Net-_U1-Pad13_ Net-_U67-Pad3_ Net-_U1-Pad7_ buffer_tri
+X4 Net-_U1-Pad4_ Net-_U11-Pad3_ Net-_U1-Pad16_ buffer_tri
+X5 Net-_U1-Pad5_ Net-_U11-Pad3_ Net-_U1-Pad15_ buffer_tri
+X2 Net-_U1-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad17_ buffer_tri
+X1 Net-_U1-Pad2_ Net-_U11-Pad3_ Net-_U1-Pad18_ buffer_tri
+U67 Net-_U1-Pad1_ Net-_U1-Pad19_ Net-_U67-Pad3_ d_nand
+U11 Net-_U1-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+U2 Net-_U1-Pad19_ Net-_U11-Pad2_ d_inverter
+X8 Net-_U1-Pad7_ Net-_U11-Pad3_ Net-_U1-Pad13_ buffer_tri
+X6 Net-_U1-Pad6_ Net-_U11-Pad3_ Net-_U1-Pad14_ buffer_tri
+X3 Net-_U1-Pad8_ Net-_U11-Pad3_ Net-_U1-Pad12_ buffer_tri
+X7 Net-_U1-Pad9_ Net-_U11-Pad3_ Net-_U1-Pad11_ buffer_tri
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.cir.out b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.cir.out
new file mode 100644
index 000000000..b6cc764d1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.cir.out
@@ -0,0 +1,41 @@
+.title kicad schematic
+
+.include buffer_tri.sub
+x11 net-_u1-pad16_ net-_u67-pad3_ net-_u1-pad4_ buffer_tri
+x14 net-_u1-pad18_ net-_u67-pad3_ net-_u1-pad2_ buffer_tri
+x13 net-_u1-pad17_ net-_u67-pad3_ net-_u1-pad3_ buffer_tri
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ gnd net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ gnd port
+x15 net-_u1-pad15_ net-_u67-pad3_ net-_u1-pad5_ buffer_tri
+x9 net-_u1-pad12_ net-_u67-pad3_ net-_u1-pad8_ buffer_tri
+x16 net-_u1-pad11_ net-_u67-pad3_ net-_u1-pad9_ buffer_tri
+x10 net-_u1-pad14_ net-_u67-pad3_ net-_u1-pad6_ buffer_tri
+x12 net-_u1-pad13_ net-_u67-pad3_ net-_u1-pad7_ buffer_tri
+x4 net-_u1-pad4_ net-_u11-pad3_ net-_u1-pad16_ buffer_tri
+x5 net-_u1-pad5_ net-_u11-pad3_ net-_u1-pad15_ buffer_tri
+x2 net-_u1-pad3_ net-_u11-pad3_ net-_u1-pad17_ buffer_tri
+x1 net-_u1-pad2_ net-_u11-pad3_ net-_u1-pad18_ buffer_tri
+* u67 net-_u1-pad1_ net-_u1-pad19_ net-_u67-pad3_ d_nand
+* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u2 net-_u1-pad19_ net-_u11-pad2_ d_inverter
+x8 net-_u1-pad7_ net-_u11-pad3_ net-_u1-pad13_ buffer_tri
+x6 net-_u1-pad6_ net-_u11-pad3_ net-_u1-pad14_ buffer_tri
+x3 net-_u1-pad8_ net-_u11-pad3_ net-_u1-pad12_ buffer_tri
+x7 net-_u1-pad9_ net-_u11-pad3_ net-_u1-pad11_ buffer_tri
+a1 [net-_u1-pad1_ net-_u1-pad19_ ] net-_u67-pad3_ u67
+a2 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 net-_u1-pad19_ net-_u11-pad2_ u2
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.kicad_sch b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.kicad_sch
new file mode 100644
index 000000000..7b47b1197
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.kicad_sch
@@ -0,0 +1,2574 @@
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+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/e961d055-bf8e-41cc-83c5-00d33dc1920e"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/b2e89e92-34bd-4696-9e2b-9fd860711958"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/d29f9465-88f4-494d-a343-b871397aa090"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/4ee456cb-544f-497d-8380-d186d040b50d"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/42f36c6f-f41a-40c6-8202-430f7daf2900"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/10b8ad69-ba9c-4122-b8d8-807979bd2582"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/aa790697-e52d-4be0-8ff7-92d1247fe8a8"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/c1c35df4-fea0-4c3b-995f-fb892295ce27"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/35e2badb-89f3-4321-ab7e-9b23e918ee8a"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/ace23070-9786-4b70-a982-a7ea1d870e36"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/8adc1c78-2300-4f70-982e-b1a384827cfb"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/5daa985d-d5b8-4900-aac8-c6b6fba44ff2"
+      (reference "U1") (unit 17) (value "PORT") (footprint "")
+    )
+    (path "/2ce3db2d-611e-4518-9b0b-3f83cbc5e9a8"
+      (reference "U1") (unit 18) (value "PORT") (footprint "")
+    )
+    (path "/ac194cca-01a1-4e46-8574-42c723cd07aa"
+      (reference "U1") (unit 19) (value "PORT") (footprint "")
+    )
+    (path "/ff02da11-c3cc-4cf2-a404-22801bf98934"
+      (reference "U1") (unit 20) (value "PORT") (footprint "")
+    )
+    (path "/cf4c5cdd-f549-419f-ad10-e5116d0595af"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1f4f1ff2-be6a-4512-a7d4-dd71399fa034"
+      (reference "U11") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/3d0805e7-cb0e-4820-9c64-803b65d99809"
+      (reference "U67") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/161db0d7-5c97-4324-ad10-b5bdf2914a74"
+      (reference "X1") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/ec87d94d-3d82-44a8-87c6-9a0cec735cc0"
+      (reference "X2") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/b4ab8bdf-c210-489d-b22c-872e01cc2a12"
+      (reference "X3") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/d51c19f4-4f72-4309-8bd8-cd5a5c0c141f"
+      (reference "X4") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/9c367059-27a9-48f7-a0d6-9a6533351238"
+      (reference "X5") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/a5f4e357-49c8-45a1-9336-3535c25d4029"
+      (reference "X6") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/29afc680-29f7-4b5f-bb6c-0637bfc0cdaf"
+      (reference "X7") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/e13eb700-a476-460e-96cf-7f666fe25607"
+      (reference "X8") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/c8b96860-807c-43c5-8197-0538600888d5"
+      (reference "X9") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/84c3e5a2-1373-4ec6-89d0-4cabb13b2605"
+      (reference "X10") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/4eb67b79-e8c5-4e6a-ada4-45b44d5287ea"
+      (reference "X11") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/92b3944e-c7b9-4f8d-86e3-9067a446d689"
+      (reference "X12") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/b82770fe-e9bd-4576-a3ec-8d5fa666f0d0"
+      (reference "X13") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/8c6e8ab0-af31-4275-8a3f-0e2c84b01ed9"
+      (reference "X14") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/578603a4-9e17-4a40-aefc-7bfefe22cf4f"
+      (reference "X15") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/4d56904a-170c-4d39-889b-3b11cf95cbc2"
+      (reference "X16") (unit 1) (value "buffer_tri") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.sub b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.sub
new file mode 100644
index 000000000..aa9bdf7f0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245.sub
@@ -0,0 +1,35 @@
+* Subcircuit 74HC245
+.subckt 74HC245 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ gnd net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ gnd 
+.title kicad schematic
+.include buffer_tri.sub
+x11 net-_u1-pad16_ net-_u67-pad3_ net-_u1-pad4_ buffer_tri
+x14 net-_u1-pad18_ net-_u67-pad3_ net-_u1-pad2_ buffer_tri
+x13 net-_u1-pad17_ net-_u67-pad3_ net-_u1-pad3_ buffer_tri
+x15 net-_u1-pad15_ net-_u67-pad3_ net-_u1-pad5_ buffer_tri
+x9 net-_u1-pad12_ net-_u67-pad3_ net-_u1-pad8_ buffer_tri
+x16 net-_u1-pad11_ net-_u67-pad3_ net-_u1-pad9_ buffer_tri
+x10 net-_u1-pad14_ net-_u67-pad3_ net-_u1-pad6_ buffer_tri
+x12 net-_u1-pad13_ net-_u67-pad3_ net-_u1-pad7_ buffer_tri
+x4 net-_u1-pad4_ net-_u11-pad3_ net-_u1-pad16_ buffer_tri
+x5 net-_u1-pad5_ net-_u11-pad3_ net-_u1-pad15_ buffer_tri
+x2 net-_u1-pad3_ net-_u11-pad3_ net-_u1-pad17_ buffer_tri
+x1 net-_u1-pad2_ net-_u11-pad3_ net-_u1-pad18_ buffer_tri
+* u67 net-_u1-pad1_ net-_u1-pad19_ net-_u67-pad3_ d_nand
+* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u2 net-_u1-pad19_ net-_u11-pad2_ d_inverter
+x8 net-_u1-pad7_ net-_u11-pad3_ net-_u1-pad13_ buffer_tri
+x6 net-_u1-pad6_ net-_u11-pad3_ net-_u1-pad14_ buffer_tri
+x3 net-_u1-pad8_ net-_u11-pad3_ net-_u1-pad12_ buffer_tri
+x7 net-_u1-pad9_ net-_u11-pad3_ net-_u1-pad11_ buffer_tri
+a1 [net-_u1-pad1_ net-_u1-pad19_ ] net-_u67-pad3_ u67
+a2 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 net-_u1-pad19_ net-_u11-pad2_ u2
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC245
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Previous_Values.xml
new file mode 100644
index 000000000..af60663d3
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">12</v1></source><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u4><u10 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u27 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u27><u24 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u24><u26 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u26><u11 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u11><u22 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u22><u8 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8><u23 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u23><u7 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u34 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u34><u46 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u46><u20 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u21><u9 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u9><u25 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u25><u47 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u47><u50 name="type">d_nand<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u50><u49 name="type">d_nand<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u49><u45 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u45><u33 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u33><u35 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u35><u48 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u48><u51 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u51><u61 name="type">d_nand<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u61><u57 name="type">d_nand<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u57><u86 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u86><u97 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u97><u89 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u89><u99 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u99><u90 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u90><u87 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u87><u98 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u98><u88 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u88><u66 name="type">d_nand<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u66><u75 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u75><u72 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u72><u92 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u92><u91 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u91><u100 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u100><u96 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u96><u83 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u83><u84 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u84><u82 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u82><u95 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u95><u81 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u81><u85 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u85><u74 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u74><u64 name="type">d_nand<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u64><u60 name="type">d_nand<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u60><u70 name="type">d_inverter<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u70><u77 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u77><u78 name="type">d_inverter<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u78><u69 name="type">d_inverter<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u69><u79 name="type">d_inverter<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u79><u94 name="type">d_inverter<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u94><u93 name="type">d_inverter<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u93><u80 name="type">d_inverter<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u80><u53 name="type">d_nand<field175 name="Enter Rise Delay (default=1.0e-9)" /><field176 name="Enter Fall Delay (default=1.0e-9)" /><field177 name="Enter Input Load (default=1.0e-12)" /></u53><u54 name="type">d_nand<field178 name="Enter Rise Delay (default=1.0e-9)" /><field179 name="Enter Fall Delay (default=1.0e-9)" /><field180 name="Enter Input Load (default=1.0e-12)" /></u54><u55 name="type">d_nand<field181 name="Enter Rise Delay (default=1.0e-9)" /><field182 name="Enter Fall Delay (default=1.0e-9)" /><field183 name="Enter Input Load (default=1.0e-12)" /></u55><u67 name="type">d_nand<field184 name="Enter Rise Delay (default=1.0e-9)" /><field185 name="Enter Fall Delay (default=1.0e-9)" /><field186 name="Enter Input Load (default=1.0e-12)" /></u67><u52 name="type">d_nand<field187 name="Enter Rise Delay (default=1.0e-9)" /><field188 name="Enter Fall Delay (default=1.0e-9)" /><field189 name="Enter Input Load (default=1.0e-12)" /></u52><u32 name="type">d_inverter<field190 name="Enter Rise Delay (default=1.0e-9)" /><field191 name="Enter Fall Delay (default=1.0e-9)" /><field192 name="Enter Input Load (default=1.0e-12)" /></u32><u31 name="type">d_inverter<field193 name="Enter Rise Delay (default=1.0e-9)" /><field194 name="Enter Fall Delay (default=1.0e-9)" /><field195 name="Enter Input Load (default=1.0e-12)" /></u31><u43 name="type">d_nand<field196 name="Enter Rise Delay (default=1.0e-9)" /><field197 name="Enter Fall Delay (default=1.0e-9)" /><field198 name="Enter Input Load (default=1.0e-12)" /></u43><u42 name="type">d_nand<field199 name="Enter Rise Delay (default=1.0e-9)" /><field200 name="Enter Fall Delay (default=1.0e-9)" /><field201 name="Enter Input Load (default=1.0e-12)" /></u42><u44 name="type">d_nand<field202 name="Enter Rise Delay (default=1.0e-9)" /><field203 name="Enter Fall Delay (default=1.0e-9)" /><field204 name="Enter Input Load (default=1.0e-12)" /></u44><u62 name="type">d_nand<field205 name="Enter Rise Delay (default=1.0e-9)" /><field206 name="Enter Fall Delay (default=1.0e-9)" /><field207 name="Enter Input Load (default=1.0e-12)" /></u62><u59 name="type">d_nand<field208 name="Enter Rise Delay (default=1.0e-9)" /><field209 name="Enter Fall Delay (default=1.0e-9)" /><field210 name="Enter Input Load (default=1.0e-12)" /></u59><u65 name="type">d_nand<field211 name="Enter Rise Delay (default=1.0e-9)" /><field212 name="Enter Fall Delay (default=1.0e-9)" /><field213 name="Enter Input Load (default=1.0e-12)" /></u65><u68 name="type">d_nand<field214 name="Enter Rise Delay (default=1.0e-9)" /><field215 name="Enter Fall Delay (default=1.0e-9)" /><field216 name="Enter Input Load (default=1.0e-12)" /></u68><u76 name="type">d_inverter<field217 name="Enter Rise Delay (default=1.0e-9)" /><field218 name="Enter Fall Delay (default=1.0e-9)" /><field219 name="Enter Input Load (default=1.0e-12)" /></u76><u71 name="type">d_inverter<field220 name="Enter Rise Delay (default=1.0e-9)" /><field221 name="Enter Fall Delay (default=1.0e-9)" /><field222 name="Enter Input Load (default=1.0e-12)" /></u71><u56 name="type">d_nand<field223 name="Enter Rise Delay (default=1.0e-9)" /><field224 name="Enter Fall Delay (default=1.0e-9)" /><field225 name="Enter Input Load (default=1.0e-12)" /></u56><u58 name="type">d_nand<field226 name="Enter Rise Delay (default=1.0e-9)" /><field227 name="Enter Fall Delay (default=1.0e-9)" /><field228 name="Enter Input Load (default=1.0e-12)" /></u58><u73 name="type">d_inverter<field229 name="Enter Rise Delay (default=1.0e-9)" /><field230 name="Enter Fall Delay (default=1.0e-9)" /><field231 name="Enter Input Load (default=1.0e-12)" /></u73><u63 name="type">d_nand<field232 name="Enter Rise Delay (default=1.0e-9)" /><field233 name="Enter Fall Delay (default=1.0e-9)" /><field234 name="Enter Input Load (default=1.0e-12)" /></u63><u40 name="type">d_nand<field235 name="Enter Rise Delay (default=1.0e-9)" /><field236 name="Enter Fall Delay (default=1.0e-9)" /><field237 name="Enter Input Load (default=1.0e-12)" /></u40><u41 name="type">d_nand<field238 name="Enter Rise Delay (default=1.0e-9)" /><field239 name="Enter Fall Delay (default=1.0e-9)" /><field240 name="Enter Input Load (default=1.0e-12)" /></u41><u30 name="type">d_inverter<field241 name="Enter Rise Delay (default=1.0e-9)" /><field242 name="Enter Fall Delay (default=1.0e-9)" /><field243 name="Enter Input Load (default=1.0e-12)" /></u30><u39 name="type">d_nand<field244 name="Enter Rise Delay (default=1.0e-9)" /><field245 name="Enter Fall Delay (default=1.0e-9)" /><field246 name="Enter Input Load (default=1.0e-12)" /></u39><u37 name="type">d_nand<field247 name="Enter Rise Delay (default=1.0e-9)" /><field248 name="Enter Fall Delay (default=1.0e-9)" /><field249 name="Enter Input Load (default=1.0e-12)" /></u37><u29 name="type">d_inverter<field250 name="Enter Rise Delay (default=1.0e-9)" /><field251 name="Enter Fall Delay (default=1.0e-9)" /><field252 name="Enter Input Load (default=1.0e-12)" /></u29><u17 name="type">d_inverter<field253 name="Enter Rise Delay (default=1.0e-9)" /><field254 name="Enter Fall Delay (default=1.0e-9)" /><field255 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_inverter<field256 name="Enter Rise Delay (default=1.0e-9)" /><field257 name="Enter Fall Delay (default=1.0e-9)" /><field258 name="Enter Input Load (default=1.0e-12)" /></u19><u16 name="type">d_inverter<field262 name="Enter Rise Delay (default=1.0e-9)" /><field263 name="Enter Fall Delay (default=1.0e-9)" /><field264 name="Enter Input Load (default=1.0e-12)" /></u16><u4 name="type">d_inverter<field265 name="Enter Rise Delay (default=1.0e-9)" /><field266 name="Enter Fall Delay (default=1.0e-9)" /><field267 name="Enter Input Load (default=1.0e-12)" /></u4><u15 name="type">d_inverter<field271 name="Enter Rise Delay (default=1.0e-9)" /><field272 name="Enter Fall Delay (default=1.0e-9)" /><field273 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_inverter<field274 name="Enter Rise Delay (default=1.0e-9)" /><field275 name="Enter Fall Delay (default=1.0e-9)" /><field276 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_inverter<field277 name="Enter Rise Delay (default=1.0e-9)" /><field278 name="Enter Fall Delay (default=1.0e-9)" /><field279 name="Enter Input Load (default=1.0e-12)" /></u18><u38 name="type">d_nand<field280 name="Enter Rise Delay (default=1.0e-9)" /><field281 name="Enter Fall Delay (default=1.0e-9)" /><field282 name="Enter Input Load (default=1.0e-12)" /></u38><u3 name="type">d_inverter<field283 name="Enter Rise Delay (default=1.0e-9)" /><field284 name="Enter Fall Delay (default=1.0e-9)" /><field285 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_inverter<field286 name="Enter Rise Delay (default=1.0e-9)" /><field287 name="Enter Fall Delay (default=1.0e-9)" /><field288 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field289 name="Enter Rise Delay (default=1.0e-9)" /><field290 name="Enter Fall Delay (default=1.0e-9)" /><field291 name="Enter Input Load (default=1.0e-12)" /></u13><u36 name="type">d_nand<field292 name="Enter Rise Delay (default=1.0e-9)" /><field293 name="Enter Fall Delay (default=1.0e-9)" /><field294 name="Enter Input Load (default=1.0e-12)" /></u36><u28 name="type">d_inverter<field295 name="Enter Rise Delay (default=1.0e-9)" /><field296 name="Enter Fall Delay (default=1.0e-9)" /><field297 name="Enter Input Load (default=1.0e-12)" /></u28></model><devicemodel /><subcircuit><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x11><x14><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x14><x13><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x13><x15><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x15><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x9><x16><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x16><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x10><x12><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x12><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x5><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x2><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x1><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x8><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x6><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x3><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x7></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.cir b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.cir
new file mode 100644
index 000000000..ef0921335
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.cir
@@ -0,0 +1,22 @@
+.title KiCad schematic
+X11 Net-_U1-Pad16_ Net-_U67-Pad3_ Net-_U1-Pad4_ buffer_tri
+X14 Net-_U1-Pad18_ Net-_U67-Pad3_ Net-_U1-Pad2_ buffer_tri
+X13 Net-_U1-Pad17_ Net-_U67-Pad3_ Net-_U1-Pad3_ buffer_tri
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ GND Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ GND PORT
+X15 Net-_U1-Pad15_ Net-_U67-Pad3_ Net-_U1-Pad5_ buffer_tri
+X9 Net-_U1-Pad12_ Net-_U67-Pad3_ Net-_U1-Pad8_ buffer_tri
+X16 Net-_U1-Pad11_ Net-_U67-Pad3_ Net-_U1-Pad9_ buffer_tri
+X10 Net-_U1-Pad14_ Net-_U67-Pad3_ Net-_U1-Pad6_ buffer_tri
+X12 Net-_U1-Pad13_ Net-_U67-Pad3_ Net-_U1-Pad7_ buffer_tri
+X4 Net-_U1-Pad4_ Net-_U11-Pad3_ Net-_U1-Pad16_ buffer_tri
+X5 Net-_U1-Pad5_ Net-_U11-Pad3_ Net-_U1-Pad15_ buffer_tri
+X2 Net-_U1-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad17_ buffer_tri
+X1 Net-_U1-Pad2_ Net-_U11-Pad3_ Net-_U1-Pad18_ buffer_tri
+U67 Net-_U1-Pad1_ Net-_U1-Pad19_ Net-_U67-Pad3_ d_nand
+U11 Net-_U1-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+U2 Net-_U1-Pad19_ Net-_U11-Pad2_ d_inverter
+X8 Net-_U1-Pad7_ Net-_U11-Pad3_ Net-_U1-Pad13_ buffer_tri
+X6 Net-_U1-Pad6_ Net-_U11-Pad3_ Net-_U1-Pad14_ buffer_tri
+X3 Net-_U1-Pad8_ Net-_U11-Pad3_ Net-_U1-Pad12_ buffer_tri
+X7 Net-_U1-Pad9_ Net-_U11-Pad3_ Net-_U1-Pad11_ buffer_tri
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.cir.out b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.cir.out
new file mode 100644
index 000000000..b6cc764d1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.cir.out
@@ -0,0 +1,41 @@
+.title kicad schematic
+
+.include buffer_tri.sub
+x11 net-_u1-pad16_ net-_u67-pad3_ net-_u1-pad4_ buffer_tri
+x14 net-_u1-pad18_ net-_u67-pad3_ net-_u1-pad2_ buffer_tri
+x13 net-_u1-pad17_ net-_u67-pad3_ net-_u1-pad3_ buffer_tri
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ gnd net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ gnd port
+x15 net-_u1-pad15_ net-_u67-pad3_ net-_u1-pad5_ buffer_tri
+x9 net-_u1-pad12_ net-_u67-pad3_ net-_u1-pad8_ buffer_tri
+x16 net-_u1-pad11_ net-_u67-pad3_ net-_u1-pad9_ buffer_tri
+x10 net-_u1-pad14_ net-_u67-pad3_ net-_u1-pad6_ buffer_tri
+x12 net-_u1-pad13_ net-_u67-pad3_ net-_u1-pad7_ buffer_tri
+x4 net-_u1-pad4_ net-_u11-pad3_ net-_u1-pad16_ buffer_tri
+x5 net-_u1-pad5_ net-_u11-pad3_ net-_u1-pad15_ buffer_tri
+x2 net-_u1-pad3_ net-_u11-pad3_ net-_u1-pad17_ buffer_tri
+x1 net-_u1-pad2_ net-_u11-pad3_ net-_u1-pad18_ buffer_tri
+* u67 net-_u1-pad1_ net-_u1-pad19_ net-_u67-pad3_ d_nand
+* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u2 net-_u1-pad19_ net-_u11-pad2_ d_inverter
+x8 net-_u1-pad7_ net-_u11-pad3_ net-_u1-pad13_ buffer_tri
+x6 net-_u1-pad6_ net-_u11-pad3_ net-_u1-pad14_ buffer_tri
+x3 net-_u1-pad8_ net-_u11-pad3_ net-_u1-pad12_ buffer_tri
+x7 net-_u1-pad9_ net-_u11-pad3_ net-_u1-pad11_ buffer_tri
+a1 [net-_u1-pad1_ net-_u1-pad19_ ] net-_u67-pad3_ u67
+a2 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 net-_u1-pad19_ net-_u11-pad2_ u2
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.kicad_sch b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.kicad_sch
new file mode 100644
index 000000000..7b47b1197
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.kicad_sch
@@ -0,0 +1,2574 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid f2407303-efd4-4c4b-803f-19a4d11e3ea3)
+
+  (paper "A1")
+
+  (lib_symbols
+    (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_and" (id 1) (at 1.27 2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_and_0_1"
+        (polyline
+          (pts
+            (xy 3.81 -1.27)
+            (xy -6.35 -1.27)
+            (xy -6.35 3.81)
+            (xy 3.81 3.81)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_and_1_1"
+        (pin input line (at -11.43 2.54 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -11.43 0 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 11.43 1.27 180) (length 5.08)
+          (name "OUT" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 -2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_inverter" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_inverter_0_1"
+        (polyline
+          (pts
+            (xy -2.54 1.27)
+            (xy -2.54 -1.27)
+            (xy 2.54 0)
+            (xy -2.54 1.27)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_inverter_1_1"
+        (pin input line (at -7.62 0 0) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output inverted (at 7.62 0 180) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
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+      (reference "X11") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/92b3944e-c7b9-4f8d-86e3-9067a446d689"
+      (reference "X12") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/b82770fe-e9bd-4576-a3ec-8d5fa666f0d0"
+      (reference "X13") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/8c6e8ab0-af31-4275-8a3f-0e2c84b01ed9"
+      (reference "X14") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/578603a4-9e17-4a40-aefc-7bfefe22cf4f"
+      (reference "X15") (unit 1) (value "buffer_tri") (footprint "")
+    )
+    (path "/4d56904a-170c-4d39-889b-3b11cf95cbc2"
+      (reference "X16") (unit 1) (value "buffer_tri") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.sub b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.sub
new file mode 100644
index 000000000..aa9bdf7f0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245.sub
@@ -0,0 +1,35 @@
+* Subcircuit 74HC245
+.subckt 74HC245 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ gnd net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ gnd 
+.title kicad schematic
+.include buffer_tri.sub
+x11 net-_u1-pad16_ net-_u67-pad3_ net-_u1-pad4_ buffer_tri
+x14 net-_u1-pad18_ net-_u67-pad3_ net-_u1-pad2_ buffer_tri
+x13 net-_u1-pad17_ net-_u67-pad3_ net-_u1-pad3_ buffer_tri
+x15 net-_u1-pad15_ net-_u67-pad3_ net-_u1-pad5_ buffer_tri
+x9 net-_u1-pad12_ net-_u67-pad3_ net-_u1-pad8_ buffer_tri
+x16 net-_u1-pad11_ net-_u67-pad3_ net-_u1-pad9_ buffer_tri
+x10 net-_u1-pad14_ net-_u67-pad3_ net-_u1-pad6_ buffer_tri
+x12 net-_u1-pad13_ net-_u67-pad3_ net-_u1-pad7_ buffer_tri
+x4 net-_u1-pad4_ net-_u11-pad3_ net-_u1-pad16_ buffer_tri
+x5 net-_u1-pad5_ net-_u11-pad3_ net-_u1-pad15_ buffer_tri
+x2 net-_u1-pad3_ net-_u11-pad3_ net-_u1-pad17_ buffer_tri
+x1 net-_u1-pad2_ net-_u11-pad3_ net-_u1-pad18_ buffer_tri
+* u67 net-_u1-pad1_ net-_u1-pad19_ net-_u67-pad3_ d_nand
+* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u2 net-_u1-pad19_ net-_u11-pad2_ d_inverter
+x8 net-_u1-pad7_ net-_u11-pad3_ net-_u1-pad13_ buffer_tri
+x6 net-_u1-pad6_ net-_u11-pad3_ net-_u1-pad14_ buffer_tri
+x3 net-_u1-pad8_ net-_u11-pad3_ net-_u1-pad12_ buffer_tri
+x7 net-_u1-pad9_ net-_u11-pad3_ net-_u1-pad11_ buffer_tri
+a1 [net-_u1-pad1_ net-_u1-pad19_ ] net-_u67-pad3_ u67
+a2 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 net-_u1-pad19_ net-_u11-pad2_ u2
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC245
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_Previous_Values.xml
new file mode 100644
index 000000000..af60663d3
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">12</v1></source><model><u2 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u5 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u4><u10 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u27 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u27><u24 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u24><u26 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u26><u11 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u11><u22 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u22><u8 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u8><u23 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u23><u7 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u34 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u34><u46 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u46><u20 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u21><u9 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u9><u25 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u25><u47 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u47><u50 name="type">d_nand<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u50><u49 name="type">d_nand<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u49><u45 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u45><u33 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u33><u35 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u35><u48 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u48><u51 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u51><u61 name="type">d_nand<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u61><u57 name="type">d_nand<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u57><u86 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u86><u97 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u97><u89 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u89><u99 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u99><u90 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u90><u87 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u87><u98 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u98><u88 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u88><u66 name="type">d_nand<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u66><u75 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u75><u72 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u72><u92 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u92><u91 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u91><u100 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u100><u96 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u96><u83 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u83><u84 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u84><u82 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u82><u95 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u95><u81 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u81><u85 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u85><u74 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u74><u64 name="type">d_nand<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u64><u60 name="type">d_nand<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u60><u70 name="type">d_inverter<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u70><u77 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u77><u78 name="type">d_inverter<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u78><u69 name="type">d_inverter<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u69><u79 name="type">d_inverter<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u79><u94 name="type">d_inverter<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u94><u93 name="type">d_inverter<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u93><u80 name="type">d_inverter<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u80><u53 name="type">d_nand<field175 name="Enter Rise Delay (default=1.0e-9)" /><field176 name="Enter Fall Delay (default=1.0e-9)" /><field177 name="Enter Input Load (default=1.0e-12)" /></u53><u54 name="type">d_nand<field178 name="Enter Rise Delay (default=1.0e-9)" /><field179 name="Enter Fall Delay (default=1.0e-9)" /><field180 name="Enter Input Load (default=1.0e-12)" /></u54><u55 name="type">d_nand<field181 name="Enter Rise Delay (default=1.0e-9)" /><field182 name="Enter Fall Delay (default=1.0e-9)" /><field183 name="Enter Input Load (default=1.0e-12)" /></u55><u67 name="type">d_nand<field184 name="Enter Rise Delay (default=1.0e-9)" /><field185 name="Enter Fall Delay (default=1.0e-9)" /><field186 name="Enter Input Load (default=1.0e-12)" /></u67><u52 name="type">d_nand<field187 name="Enter Rise Delay (default=1.0e-9)" /><field188 name="Enter Fall Delay (default=1.0e-9)" /><field189 name="Enter Input Load (default=1.0e-12)" /></u52><u32 name="type">d_inverter<field190 name="Enter Rise Delay (default=1.0e-9)" /><field191 name="Enter Fall Delay (default=1.0e-9)" /><field192 name="Enter Input Load (default=1.0e-12)" /></u32><u31 name="type">d_inverter<field193 name="Enter Rise Delay (default=1.0e-9)" /><field194 name="Enter Fall Delay (default=1.0e-9)" /><field195 name="Enter Input Load (default=1.0e-12)" /></u31><u43 name="type">d_nand<field196 name="Enter Rise Delay (default=1.0e-9)" /><field197 name="Enter Fall Delay (default=1.0e-9)" /><field198 name="Enter Input Load (default=1.0e-12)" /></u43><u42 name="type">d_nand<field199 name="Enter Rise Delay (default=1.0e-9)" /><field200 name="Enter Fall Delay (default=1.0e-9)" /><field201 name="Enter Input Load (default=1.0e-12)" /></u42><u44 name="type">d_nand<field202 name="Enter Rise Delay (default=1.0e-9)" /><field203 name="Enter Fall Delay (default=1.0e-9)" /><field204 name="Enter Input Load (default=1.0e-12)" /></u44><u62 name="type">d_nand<field205 name="Enter Rise Delay (default=1.0e-9)" /><field206 name="Enter Fall Delay (default=1.0e-9)" /><field207 name="Enter Input Load (default=1.0e-12)" /></u62><u59 name="type">d_nand<field208 name="Enter Rise Delay (default=1.0e-9)" /><field209 name="Enter Fall Delay (default=1.0e-9)" /><field210 name="Enter Input Load (default=1.0e-12)" /></u59><u65 name="type">d_nand<field211 name="Enter Rise Delay (default=1.0e-9)" /><field212 name="Enter Fall Delay (default=1.0e-9)" /><field213 name="Enter Input Load (default=1.0e-12)" /></u65><u68 name="type">d_nand<field214 name="Enter Rise Delay (default=1.0e-9)" /><field215 name="Enter Fall Delay (default=1.0e-9)" /><field216 name="Enter Input Load (default=1.0e-12)" /></u68><u76 name="type">d_inverter<field217 name="Enter Rise Delay (default=1.0e-9)" /><field218 name="Enter Fall Delay (default=1.0e-9)" /><field219 name="Enter Input Load (default=1.0e-12)" /></u76><u71 name="type">d_inverter<field220 name="Enter Rise Delay (default=1.0e-9)" /><field221 name="Enter Fall Delay (default=1.0e-9)" /><field222 name="Enter Input Load (default=1.0e-12)" /></u71><u56 name="type">d_nand<field223 name="Enter Rise Delay (default=1.0e-9)" /><field224 name="Enter Fall Delay (default=1.0e-9)" /><field225 name="Enter Input Load (default=1.0e-12)" /></u56><u58 name="type">d_nand<field226 name="Enter Rise Delay (default=1.0e-9)" /><field227 name="Enter Fall Delay (default=1.0e-9)" /><field228 name="Enter Input Load (default=1.0e-12)" /></u58><u73 name="type">d_inverter<field229 name="Enter Rise Delay (default=1.0e-9)" /><field230 name="Enter Fall Delay (default=1.0e-9)" /><field231 name="Enter Input Load (default=1.0e-12)" /></u73><u63 name="type">d_nand<field232 name="Enter Rise Delay (default=1.0e-9)" /><field233 name="Enter Fall Delay (default=1.0e-9)" /><field234 name="Enter Input Load (default=1.0e-12)" /></u63><u40 name="type">d_nand<field235 name="Enter Rise Delay (default=1.0e-9)" /><field236 name="Enter Fall Delay (default=1.0e-9)" /><field237 name="Enter Input Load (default=1.0e-12)" /></u40><u41 name="type">d_nand<field238 name="Enter Rise Delay (default=1.0e-9)" /><field239 name="Enter Fall Delay (default=1.0e-9)" /><field240 name="Enter Input Load (default=1.0e-12)" /></u41><u30 name="type">d_inverter<field241 name="Enter Rise Delay (default=1.0e-9)" /><field242 name="Enter Fall Delay (default=1.0e-9)" /><field243 name="Enter Input Load (default=1.0e-12)" /></u30><u39 name="type">d_nand<field244 name="Enter Rise Delay (default=1.0e-9)" /><field245 name="Enter Fall Delay (default=1.0e-9)" /><field246 name="Enter Input Load (default=1.0e-12)" /></u39><u37 name="type">d_nand<field247 name="Enter Rise Delay (default=1.0e-9)" /><field248 name="Enter Fall Delay (default=1.0e-9)" /><field249 name="Enter Input Load (default=1.0e-12)" /></u37><u29 name="type">d_inverter<field250 name="Enter Rise Delay (default=1.0e-9)" /><field251 name="Enter Fall Delay (default=1.0e-9)" /><field252 name="Enter Input Load (default=1.0e-12)" /></u29><u17 name="type">d_inverter<field253 name="Enter Rise Delay (default=1.0e-9)" /><field254 name="Enter Fall Delay (default=1.0e-9)" /><field255 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_inverter<field256 name="Enter Rise Delay (default=1.0e-9)" /><field257 name="Enter Fall Delay (default=1.0e-9)" /><field258 name="Enter Input Load (default=1.0e-12)" /></u19><u16 name="type">d_inverter<field262 name="Enter Rise Delay (default=1.0e-9)" /><field263 name="Enter Fall Delay (default=1.0e-9)" /><field264 name="Enter Input Load (default=1.0e-12)" /></u16><u4 name="type">d_inverter<field265 name="Enter Rise Delay (default=1.0e-9)" /><field266 name="Enter Fall Delay (default=1.0e-9)" /><field267 name="Enter Input Load (default=1.0e-12)" /></u4><u15 name="type">d_inverter<field271 name="Enter Rise Delay (default=1.0e-9)" /><field272 name="Enter Fall Delay (default=1.0e-9)" /><field273 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_inverter<field274 name="Enter Rise Delay (default=1.0e-9)" /><field275 name="Enter Fall Delay (default=1.0e-9)" /><field276 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_inverter<field277 name="Enter Rise Delay (default=1.0e-9)" /><field278 name="Enter Fall Delay (default=1.0e-9)" /><field279 name="Enter Input Load (default=1.0e-12)" /></u18><u38 name="type">d_nand<field280 name="Enter Rise Delay (default=1.0e-9)" /><field281 name="Enter Fall Delay (default=1.0e-9)" /><field282 name="Enter Input Load (default=1.0e-12)" /></u38><u3 name="type">d_inverter<field283 name="Enter Rise Delay (default=1.0e-9)" /><field284 name="Enter Fall Delay (default=1.0e-9)" /><field285 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_inverter<field286 name="Enter Rise Delay (default=1.0e-9)" /><field287 name="Enter Fall Delay (default=1.0e-9)" /><field288 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field289 name="Enter Rise Delay (default=1.0e-9)" /><field290 name="Enter Fall Delay (default=1.0e-9)" /><field291 name="Enter Input Load (default=1.0e-12)" /></u13><u36 name="type">d_nand<field292 name="Enter Rise Delay (default=1.0e-9)" /><field293 name="Enter Fall Delay (default=1.0e-9)" /><field294 name="Enter Input Load (default=1.0e-12)" /></u36><u28 name="type">d_inverter<field295 name="Enter Rise Delay (default=1.0e-9)" /><field296 name="Enter Fall Delay (default=1.0e-9)" /><field297 name="Enter Input Load (default=1.0e-12)" /></u28></model><devicemodel /><subcircuit><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x11><x14><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x14><x13><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x13><x15><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x15><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x9><x16><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x16><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x10><x12><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x12><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x5><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x2><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x1><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x8><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x6><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x3><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\buffer_tri</field></x7></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.cir b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.cir
new file mode 100644
index 000000000..b4f35a452
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.cir
@@ -0,0 +1,27 @@
+.title KiCad schematic
+U6 Net-_V_OEn1-Pad1_ Net-_V_A0-Pad1_ Net-_V_A1-Pad1_ Net-_V_A2-Pad1_ Net-_V_A3-Pad1_ Net-_U6-Pad6_ Net-_U6-Pad7_ Net-_U6-Pad8_ Net-_U6-Pad9_ Net-_U6-Pad10_ adc_bridge_5
+V_OEn1 Net-_V_OEn1-Pad1_ GND DC
+V_A3 Net-_V_A3-Pad1_ GND DC
+U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ V_A4 V_A5 V_A6 V_A7 dac_bridge_4
+U1 V_A4 plot_v1
+U3 V_A6 plot_v1
+U4 V_A7 plot_v1
+U2 V_A5 plot_v1
+v1 Net-_v1-Pad1_ GND 5
+U7 Net-_V_DIR1-Pad1_ Net-_U7-Pad2_ adc_bridge_1
+U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U8-Pad4_ V_B0 V_B1 V_B2 V_B3 dac_bridge_4
+U9 Net-_V_B4-Pad1_ Net-_V_5-Pad1_ Net-_V_B6-Pad1_ Net-_V_B7-Pad1_ Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ adc_bridge_4
+X1 Net-_U6-Pad6_ Net-_U6-Pad7_ Net-_U6-Pad8_ Net-_U6-Pad9_ Net-_U6-Pad10_ Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ GND Net-_U9-Pad8_ Net-_U9-Pad7_ Net-_U9-Pad6_ Net-_U9-Pad5_ Net-_U8-Pad4_ Net-_U8-Pad3_ Net-_U8-Pad2_ Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_v1-Pad1_ 74HC245
+V_B7 Net-_V_B7-Pad1_ GND DC
+V_B6 Net-_V_B6-Pad1_ GND DC
+V_DIR1 Net-_V_DIR1-Pad1_ GND DC
+U11 V_B1 plot_v1
+U12 V_B2 plot_v1
+U13 V_B3 plot_v1
+U10 V_B0 plot_v1
+V_5 Net-_V_5-Pad1_ GND DC
+V_B4 Net-_V_B4-Pad1_ GND DC
+V_A0 Net-_V_A0-Pad1_ GND DC
+V_A2 Net-_V_A2-Pad1_ GND DC
+V_A1 Net-_V_A1-Pad1_ GND DC
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.cir.out b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.cir.out
new file mode 100644
index 000000000..5301f6d4b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.cir.out
@@ -0,0 +1,60 @@
+.title kicad schematic
+
+.include 74HC245.sub
+* u6 net-_v_oen1-pad1_ net-_v_a0-pad1_ net-_v_a1-pad1_ net-_v_a2-pad1_ net-_v_a3-pad1_ net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ net-_u6-pad9_ net-_u6-pad10_ adc_bridge_5
+v_oen1 net-_v_oen1-pad1_ gnd  dc 0
+v_a3 net-_v_a3-pad1_ gnd  dc 5
+* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ v_a4 v_a5 v_a6 v_a7 dac_bridge_4
+* u1 v_a4 plot_v1
+* u3 v_a6 plot_v1
+* u4 v_a7 plot_v1
+* u2 v_a5 plot_v1
+v1 net-_v1-pad1_ gnd 5
+* u7 net-_v_dir1-pad1_ net-_u7-pad2_ adc_bridge_1
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ v_b0 v_b1 v_b2 v_b3 dac_bridge_4
+* u9 net-_v_b4-pad1_ net-_v_5-pad1_ net-_v_b6-pad1_ net-_v_b7-pad1_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ adc_bridge_4
+x1 net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ net-_u6-pad9_ net-_u6-pad10_ net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ gnd net-_u9-pad8_ net-_u9-pad7_ net-_u9-pad6_ net-_u9-pad5_ net-_u8-pad4_ net-_u8-pad3_ net-_u8-pad2_ net-_u8-pad1_ net-_u7-pad2_ net-_v1-pad1_ 74HC245
+v_b7 net-_v_b7-pad1_ gnd  dc 0
+v_b6 net-_v_b6-pad1_ gnd  dc 0
+v_dir1 net-_v_dir1-pad1_ gnd  dc 5
+* u11 v_b1 plot_v1
+* u12 v_b2 plot_v1
+* u13 v_b3 plot_v1
+* u10 v_b0 plot_v1
+v_5 net-_v_5-pad1_ gnd  dc 5
+v_b4 net-_v_b4-pad1_ gnd  dc 5
+v_a0 net-_v_a0-pad1_ gnd  dc 5
+v_a2 net-_v_a2-pad1_ gnd  dc 5
+v_a1 net-_v_a1-pad1_ gnd  dc 0
+a1 [net-_v_oen1-pad1_ net-_v_a0-pad1_ net-_v_a1-pad1_ net-_v_a2-pad1_ net-_v_a3-pad1_ ] [net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ net-_u6-pad9_ net-_u6-pad10_ ] u6
+a2 [net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ ] [v_a4 v_a5 v_a6 v_a7 ] u5
+a3 [net-_v_dir1-pad1_ ] [net-_u7-pad2_ ] u7
+a4 [net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ ] [v_b0 v_b1 v_b2 v_b3 ] u8
+a5 [net-_v_b4-pad1_ net-_v_5-pad1_ net-_v_b6-pad1_ net-_v_b7-pad1_ ] [net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] u9
+* Schematic Name:                             adc_bridge_5, Ngspice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-00 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_a4)
+plot v(v_a6)
+plot v(v_a7)
+plot v(v_a5)
+plot v(v_b1)
+plot v(v_b2)
+plot v(v_b3)
+plot v(v_b0)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.kicad_sch b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.kicad_sch
new file mode 100644
index 000000000..5c8b871fd
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.kicad_sch
@@ -0,0 +1,1630 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 273357b9-18f7-4954-b97e-3aa53d16162c)
+
+  (paper "A1")
+
+  (lib_symbols
+    (symbol "eSim_Hybrid:adc_bridge_1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_1" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_1_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "adc_bridge_1_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 1.27 180) (length 5.08)
+          (name "OUT1" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:adc_bridge_4" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_4" (id 1) (at 0 7.62 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_4_0_1"
+        (rectangle (start -8.89 8.89) (end 8.89 -5.08)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "adc_bridge_4_1_1"
+        (pin input line (at -13.97 5.08 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -13.97 2.54 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -13.97 0 0) (length 5.08)
+          (name "IN3" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -13.97 -2.54 0) (length 5.08)
+          (name "IN4" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 5.08 180) (length 5.08)
+          (name "OUT1" (effects (font (size 1.27 1.27))))
+          (number "5" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 2.54 180) (length 5.08)
+          (name "OUT2" (effects (font (size 1.27 1.27))))
+          (number "6" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 0 180) (length 5.08)
+          (name "OUT3" (effects (font (size 1.27 1.27))))
+          (number "7" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 13.97 -2.54 180) (length 5.08)
+          (name "OUT4" (effects (font (size 1.27 1.27))))
+          (number "8" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Hybrid:adc_bridge_5" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_5" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_5_0_1"
+        (rectangle (start -10.16 5.08) (end 8.89 -10.16)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "adc_bridge_5_1_1"
+        (pin input line (at -15.24 1.27 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
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+        (pin output line (at 13.97 -8.89 180) (length 5.08)
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+          (number "10" (effects (font (size 1.27 1.27))))
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+        (pin input line (at -15.24 -1.27 0) (length 5.08)
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+          (number "2" (effects (font (size 1.27 1.27))))
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+        (pin input line (at -15.24 -3.81 0) (length 5.08)
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+          (number "3" (effects (font (size 1.27 1.27))))
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+        (pin input line (at -15.24 -6.35 0) (length 5.08)
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+          (number "4" (effects (font (size 1.27 1.27))))
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diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.proj b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.proj
new file mode 100644
index 000000000..3ba7565bd
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.proj
@@ -0,0 +1 @@
+schematicFile 74HC245_TEST.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.raw b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.raw
new file mode 100644
index 000000000..2413d8d86
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST.raw
@@ -0,0 +1,9068 @@
+Title: kicad schematic
+Date: Sat Dec 06 20:15:48  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 151
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(net-_v_oen1-pad1_)	voltage
+	2	v(net-_v_a3-pad1_)	voltage
+	3	v(net-_v1-pad1_)	voltage
+	4	v(x1.x11.net-_m2-pad1_)	voltage
+	5	v(x1.x11.net-_m2-pad2_)	voltage
+	6	v(x1.x11.net-_m1-pad1_)	voltage
+	7	v(x1.x11.net-_m1-pad2_)	voltage
+	8	v(x1.x14.net-_m2-pad1_)	voltage
+	9	v(x1.x14.net-_m2-pad2_)	voltage
+	10	v(x1.x14.net-_m1-pad1_)	voltage
+	11	v(x1.x14.net-_m1-pad2_)	voltage
+	12	v(x1.x13.net-_m2-pad1_)	voltage
+	13	v(x1.x13.net-_m2-pad2_)	voltage
+	14	v(x1.x13.net-_m1-pad1_)	voltage
+	15	v(x1.x13.net-_m1-pad2_)	voltage
+	16	v(x1.x15.net-_m2-pad1_)	voltage
+	17	v(x1.x15.net-_m2-pad2_)	voltage
+	18	v(x1.x15.net-_m1-pad1_)	voltage
+	19	v(x1.x15.net-_m1-pad2_)	voltage
+	20	v(x1.x9.net-_m2-pad1_)	voltage
+	21	v(x1.x9.net-_m2-pad2_)	voltage
+	22	v(x1.x9.net-_m1-pad1_)	voltage
+	23	v(x1.x9.net-_m1-pad2_)	voltage
+	24	v(x1.x16.net-_m2-pad1_)	voltage
+	25	v(x1.x16.net-_m2-pad2_)	voltage
+	26	v(x1.x16.net-_m1-pad1_)	voltage
+	27	v(x1.x16.net-_m1-pad2_)	voltage
+	28	v(x1.x10.net-_m2-pad1_)	voltage
+	29	v(x1.x10.net-_m2-pad2_)	voltage
+	30	v(x1.x10.net-_m1-pad1_)	voltage
+	31	v(x1.x10.net-_m1-pad2_)	voltage
+	32	v(x1.x12.net-_m2-pad1_)	voltage
+	33	v(x1.x12.net-_m2-pad2_)	voltage
+	34	v(x1.x12.net-_m1-pad1_)	voltage
+	35	v(x1.x12.net-_m1-pad2_)	voltage
+	36	v(x1.x4.net-_m2-pad1_)	voltage
+	37	v(x1.x4.net-_m2-pad2_)	voltage
+	38	v(x1.x4.net-_m1-pad1_)	voltage
+	39	v(x1.x4.net-_m1-pad2_)	voltage
+	40	v(x1.x5.net-_m2-pad1_)	voltage
+	41	v(x1.x5.net-_m2-pad2_)	voltage
+	42	v(x1.x5.net-_m1-pad1_)	voltage
+	43	v(x1.x5.net-_m1-pad2_)	voltage
+	44	v(x1.x2.net-_m2-pad1_)	voltage
+	45	v(x1.x2.net-_m2-pad2_)	voltage
+	46	v(x1.x2.net-_m1-pad1_)	voltage
+	47	v(x1.x2.net-_m1-pad2_)	voltage
+	48	v(x1.x1.net-_m2-pad1_)	voltage
+	49	v(x1.x1.net-_m2-pad2_)	voltage
+	50	v(x1.x1.net-_m1-pad1_)	voltage
+	51	v(x1.x1.net-_m1-pad2_)	voltage
+	52	v(x1.x8.net-_m2-pad1_)	voltage
+	53	v(x1.x8.net-_m2-pad2_)	voltage
+	54	v(x1.x8.net-_m1-pad1_)	voltage
+	55	v(x1.x8.net-_m1-pad2_)	voltage
+	56	v(x1.x6.net-_m2-pad1_)	voltage
+	57	v(x1.x6.net-_m2-pad2_)	voltage
+	58	v(x1.x6.net-_m1-pad1_)	voltage
+	59	v(x1.x6.net-_m1-pad2_)	voltage
+	60	v(x1.x3.net-_m2-pad1_)	voltage
+	61	v(x1.x3.net-_m2-pad2_)	voltage
+	62	v(x1.x3.net-_m1-pad1_)	voltage
+	63	v(x1.x3.net-_m1-pad2_)	voltage
+	64	v(x1.x7.net-_m2-pad1_)	voltage
+	65	v(x1.x7.net-_m2-pad2_)	voltage
+	66	v(x1.x7.net-_m1-pad1_)	voltage
+	67	v(x1.x7.net-_m1-pad2_)	voltage
+	68	v(net-_v_b7-pad1_)	voltage
+	69	v(net-_v_b6-pad1_)	voltage
+	70	v(net-_v_dir1-pad1_)	voltage
+	71	v(net-_v_5-pad1_)	voltage
+	72	v(net-_v_b4-pad1_)	voltage
+	73	v(net-_v_a0-pad1_)	voltage
+	74	v(net-_v_a2-pad1_)	voltage
+	75	v(net-_v_a1-pad1_)	voltage
+	76	v(v_a4)	voltage
+	77	v(v_a5)	voltage
+	78	v(v_a6)	voltage
+	79	v(v_a7)	voltage
+	80	v(v_b0)	voltage
+	81	v(v_b1)	voltage
+	82	v(v_b2)	voltage
+	83	v(v_b3)	voltage
+	84	i(v_a1)	current
+	85	i(v_a2)	current
+	86	i(v_a0)	current
+	87	i(v_b4)	current
+	88	i(v_5)	current
+	89	i(v_dir1)	current
+	90	i(v_b6)	current
+	91	i(v_b7)	current
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+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747242955414366e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747242955414366e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e-01
+	4.989341535357048e+00
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+	5.000000000000000e-01
+	4.989341535357048e+00
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+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353424910258e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e-01
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+	5.000000000000000e-01
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353424910258e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353424910258e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353424910258e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
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+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
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+	5.000000000000000e+00
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+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-8.102851699427505e-12
+	-8.102851699427505e-12
+	-8.102851699427505e-12
+	-8.102851699427505e-12
+	-1.518339928122947e-06
+	-8.102851699427505e-12
+	-1.518339928122947e-06
+	-1.518339928122947e-06
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	-8.065268270954827e-12
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-3.316936525555260e-23
+	-2.819889315229043e-23
+	-3.316936551439758e-23
+	-2.819889315268164e-23
+	-3.316936551439758e-23
+	-2.819889315268164e-23
+	-3.316936551439758e-23
+	-2.819889315268164e-23
+	-9.014047244518899e-23
+	-5.488963749748753e-20
+	-3.316936551439758e-23
+	-2.819889315268164e-23
+	-9.014047244518899e-23
+	-5.488963749748753e-20
+	-9.014047244518899e-23
+	-5.488963749748753e-20
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+	6.967574215173956e-21
+	6.226765516127921e-21
+58		1.000000000000000e+01
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	3.747243252548525e-02
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e-01
+	4.989341535357314e+00
+	5.000000000000000e-01
+	5.000000000000000e+00
+	5.000000000000000e-01
+	4.989341535357314e+00
+	5.000000000000000e-01
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353425259672e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e-01
+	4.989341535357314e+00
+	5.000000000000000e-01
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353425259672e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353425259672e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353425259672e-08
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	2.343353425259773e-08
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	-8.102962721729968e-12
+	-8.102962721729968e-12
+	-8.102962721729968e-12
+	-8.102962721729968e-12
+	-1.518339927909547e-06
+	-8.102962721729968e-12
+	-1.518339927909547e-06
+	-1.518339927909547e-06
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	-8.065268267964080e-12
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	3.251562736103671e-23
+	2.895998708609868e-23
+	3.251562677709475e-23
+	2.895998708521697e-23
+	3.251562677709475e-23
+	2.895998708521697e-23
+	3.251562677709475e-23
+	2.895998708521697e-23
+	9.037432868281995e-23
+	5.504225232050357e-20
+	3.251562677709475e-23
+	2.895998708521697e-23
+	9.037432868281995e-23
+	5.504225232050357e-20
+	9.037432868281995e-23
+	5.504225232050357e-20
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
+	-4.041071316558134e-21
+	-3.618943092973766e-21
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST_Previous_Values.xml
new file mode 100644
index 000000000..d4206b5c3
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/74HC245_TEST_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v_dir1 name="Source type">dc<field1 name="Value">0</field1></v_dir1><v_a3 name="Source type">dc<field1 name="Value">0</field1></v_a3><v_a1 name="Source type">dc<field1 name="Value">5</field1></v_a1><v_a0 name="Source type">dc<field1 name="Value">5</field1></v_a0><v_a2 name="Source type">dc<field1 name="Value">5</field1></v_a2><v1 name="Source type">5</v1><v_b7 name="Source type">dc<field1 name="Value">5</field1></v_b7><v_b6 name="Source type">dc<field1 name="Value">0</field1></v_b6><v_5 name="Source type">dc<field1 name="Value">5</field1></v_5><v_oe_n1 name="Source type">dc<field1 name="Value">0</field1></v_oe_n1><v_b4 name="Source type">dc<field1 name="Value">5</field1></v_b4><v1 name="Source type">12</v1><v_oen1 name="Source type">dc<field1 name="Value">0</field1></v_oen1></source><model><u5 name="type">dac_bridge<field1 name="Enter value for out_low (default=0.0)" /><field2 name="Enter value for out_high (default=5.0)" /><field3 name="Enter value for out_undef (default=0.5)" /><field4 name="Enter value for input load (default=1.0e-12)" /><field5 name="Enter the Rise Time (default=1.0e-9)" /><field6 name="Enter the Fall Time (default=1.0e-9)" /></u5><u6 name="type">adc_bridge<field7 name="Enter value for in_low (default=1.0)" /><field8 name="Enter value for in_high (default=2.0)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u6><u7 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u7><u8 name="type">dac_bridge<field15 name="Enter value for out_low (default=0.0)" /><field16 name="Enter value for out_high (default=5.0)" /><field17 name="Enter value for out_undef (default=0.5)" /><field18 name="Enter value for input load (default=1.0e-12)" /><field19 name="Enter the Rise Time (default=1.0e-9)" /><field20 name="Enter the Fall Time (default=1.0e-9)" /></u8><u9 name="type">adc_bridge<field21 name="Enter value for in_low (default=1.0)" /><field22 name="Enter value for in_high (default=2.0)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u9></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC245</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/NMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/PMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/_autosave-74HC245.sch b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/_autosave-74HC245.sch
new file mode 100644
index 000000000..27453edb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/_autosave-74HC245.sch
@@ -0,0 +1,610 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 6150 4675
+Connection ~ 6175 6350
+Connection ~ 6200 13350
+Connection ~ 6225 8075
+Connection ~ 6225 10000
+Connection ~ 6225 11675
+Connection ~ 6250 15250
+Connection ~ 6250 17250
+Connection ~ 7225 6350
+Connection ~ 7250 4675
+Connection ~ 7325 17250
+Connection ~ 7525 8075
+Connection ~ 7525 13350
+Connection ~ 7525 15250
+Connection ~ 7625 11675
+Connection ~ 7675 10000
+Connection ~ 8800 4400
+Connection ~ 8800 5875
+Connection ~ 8800 7550
+Connection ~ 8800 9450
+Connection ~ 8800 11175
+Connection ~ 8800 12875
+Connection ~ 8800 14675
+Connection ~ 9125 2800
+Connection ~ 9350 4900
+Connection ~ 9350 6650
+Connection ~ 9350 8375
+Connection ~ 9350 10350
+Connection ~ 9350 12025
+Connection ~ 9350 13675
+Connection ~ 9350 15625
+Connection ~ 10850 5150
+Connection ~ 10950 6975
+Connection ~ 11075 8750
+Connection ~ 11075 10625
+Connection ~ 11200 13975
+Connection ~ 11275 12300
+Connection ~ 11275 16050
+Connection ~ 11325 18050
+Connection ~ 11875 5150
+Connection ~ 11875 6975
+Connection ~ 11900 8750
+Connection ~ 12000 12300
+Connection ~ 12025 10625
+Connection ~ 12050 13975
+Connection ~ 12100 4125
+Connection ~ 12150 16050
+Connection ~ 12275 18050
+Wire Wire Line
+	5000 17250 6250 17250
+Wire Wire Line
+	5025 15250 6250 15250
+Wire Wire Line
+	5200 4675 6150 4675
+Wire Wire Line
+	5225 8075 6225 8075
+Wire Wire Line
+	5250 6350 6175 6350
+Wire Wire Line
+	5250 10000 6225 10000
+Wire Wire Line
+	5250 13350 6200 13350
+Wire Wire Line
+	5275 11675 6225 11675
+Wire Wire Line
+	5450 3675 5450 4125
+Wire Wire Line
+	5450 4125 12100 4125
+Wire Wire Line
+	5725 3675 5450 3675
+Wire Wire Line
+	6150 4675 6150 5150
+Wire Wire Line
+	6150 4675 7250 4675
+Wire Wire Line
+	6150 5150 10850 5150
+Wire Wire Line
+	6175 6350 6175 6975
+Wire Wire Line
+	6175 6350 7225 6350
+Wire Wire Line
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+	12000 11675 12000 12300
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+	12000 12300 13350 12300
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+	12025 10000 12025 10625
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+	12275 17250 12275 18050
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+	12275 18050 14175 18050
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+L eSim_Miscellaneous:PORT U?
+U 1 1 00000000
+P 17325 5150
+F 0 "U?" H 17350 5350 30  0000 C CNN
+F 1 "PORT" H 17350 5250 30  0000 C CNN
+F 2 "" H 17325 5150 60  0000 C CNN
+F 3 "" H 17325 5150 60  0000 C CNN
+	1    17325 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 2 1 00000000
+P 17325 5775
+F 0 "U?" H 17350 5950 30  0000 C CNN
+F 1 "PORT" H 17350 5850 30  0000 C CNN
+F 2 "" H 17325 5775 60  0000 C CNN
+F 3 "" H 17325 5775 60  0000 C CNN
+	2    17325 5775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 3 1 00000000
+P 17325 6550
+F 0 "U?" H 17350 6750 30  0000 C CNN
+F 1 "PORT" H 17350 6650 30  0000 C CNN
+F 2 "" H 17325 6550 60  0000 C CNN
+F 3 "" H 17325 6550 60  0000 C CNN
+	3    17325 6550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 4 1 00000000
+P 17350 7300
+F 0 "U?" H 17375 7500 30  0000 C CNN
+F 1 "PORT" H 17375 7400 30  0000 C CNN
+F 2 "" H 17350 7300 60  0000 C CNN
+F 3 "" H 17350 7300 60  0000 C CNN
+	4    17350 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 5 1 00000000
+P 17350 8200
+F 0 "U?" H 17375 8400 30  0000 C CNN
+F 1 "PORT" H 17375 8300 30  0000 C CNN
+F 2 "" H 17350 8200 60  0000 C CNN
+F 3 "" H 17350 8200 60  0000 C CNN
+	5    17350 8200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 6 1 00000000
+P 17450 9125
+F 0 "U?" H 17475 9300 30  0000 C CNN
+F 1 "PORT" H 17475 9200 30  0000 C CNN
+F 2 "" H 17450 9125 60  0000 C CNN
+F 3 "" H 17450 9125 60  0000 C CNN
+	6    17450 9125
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 7 1 00000000
+P 17450 9900
+F 0 "U?" H 17475 10100 30  0000 C CNN
+F 1 "PORT" H 17475 10000 30  0000 C CNN
+F 2 "" H 17450 9900 60  0000 C CNN
+F 3 "" H 17450 9900 60  0000 C CNN
+	7    17450 9900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 8 1 00000000
+P 17475 10750
+F 0 "U?" H 17500 10950 30  0000 C CNN
+F 1 "PORT" H 17500 10850 30  0000 C CNN
+F 2 "" H 17475 10750 60  0000 C CNN
+F 3 "" H 17475 10750 60  0000 C CNN
+	8    17475 10750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 9 1 00000000
+P 17525 11500
+F 0 "U?" H 17550 11700 30  0000 C CNN
+F 1 "PORT" H 17550 11600 30  0000 C CNN
+F 2 "" H 17525 11500 60  0000 C CNN
+F 3 "" H 17525 11500 60  0000 C CNN
+	9    17525 11500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 10 1 00000000
+P 17675 12300
+F 0 "U?" H 17700 12500 30  0000 C CNN
+F 1 "PORT" H 17700 12400 30  0000 C CNN
+F 2 "" H 17675 12300 60  0000 C CNN
+F 3 "" H 17675 12300 60  0000 C CNN
+	10   17675 12300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 20 1 00000000
+P 18400 5150
+F 0 "U?" H 18425 5350 30  0000 C CNN
+F 1 "PORT" H 18425 5250 30  0000 C CNN
+F 2 "" H 18400 5150 60  0000 C CNN
+F 3 "" H 18400 5150 60  0000 C CNN
+	20   18400 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 19 1 00000000
+P 18450 5900
+F 0 "U?" H 18475 6100 30  0000 C CNN
+F 1 "PORT" H 18475 6000 30  0000 C CNN
+F 2 "" H 18450 5900 60  0000 C CNN
+F 3 "" H 18450 5900 60  0000 C CNN
+	19   18450 5900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 18 1 00000000
+P 18550 6625
+F 0 "U?" H 18575 6800 30  0000 C CNN
+F 1 "PORT" H 18575 6700 30  0000 C CNN
+F 2 "" H 18550 6625 60  0000 C CNN
+F 3 "" H 18550 6625 60  0000 C CNN
+	18   18550 6625
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 17 1 00000000
+P 18625 7375
+F 0 "U?" H 18650 7550 30  0000 C CNN
+F 1 "PORT" H 18650 7450 30  0000 C CNN
+F 2 "" H 18625 7375 60  0000 C CNN
+F 3 "" H 18625 7375 60  0000 C CNN
+	17   18625 7375
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 16 1 00000000
+P 18625 8250
+F 0 "U?" H 18650 8450 30  0000 C CNN
+F 1 "PORT" H 18650 8350 30  0000 C CNN
+F 2 "" H 18625 8250 60  0000 C CNN
+F 3 "" H 18625 8250 60  0000 C CNN
+	16   18625 8250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 15 1 00000000
+P 18750 9100
+F 0 "U?" H 18775 9300 30  0000 C CNN
+F 1 "PORT" H 18775 9200 30  0000 C CNN
+F 2 "" H 18750 9100 60  0000 C CNN
+F 3 "" H 18750 9100 60  0000 C CNN
+	15   18750 9100
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 14 1 00000000
+P 18775 9900
+F 0 "U?" H 18800 10100 30  0000 C CNN
+F 1 "PORT" H 18800 10000 30  0000 C CNN
+F 2 "" H 18775 9900 60  0000 C CNN
+F 3 "" H 18775 9900 60  0000 C CNN
+	14   18775 9900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 13 1 00000000
+P 18775 10650
+F 0 "U?" H 18800 10850 30  0000 C CNN
+F 1 "PORT" H 18800 10750 30  0000 C CNN
+F 2 "" H 18775 10650 60  0000 C CNN
+F 3 "" H 18775 10650 60  0000 C CNN
+	13   18775 10650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 12 1 00000000
+P 18875 11425
+F 0 "U?" H 18900 11600 30  0000 C CNN
+F 1 "PORT" H 18900 11500 30  0000 C CNN
+F 2 "" H 18875 11425 60  0000 C CNN
+F 3 "" H 18875 11425 60  0000 C CNN
+	12   18875 11425
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 11 1 00000000
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+F 0 "U?" H 18925 12500 30  0000 C CNN
+F 1 "PORT" H 18925 12400 30  0000 C CNN
+F 2 "" H 18900 12300 60  0000 C CNN
+F 3 "" H 18900 12300 60  0000 C CNN
+	11   18900 12300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 6025 3675
+F 0 "U?" H 6025 3950 60  0000 C CNN
+F 1 "d_inverter" H 6025 3800 60  0000 C CNN
+F 2 "" H 6075 3625 60  0000 C CNN
+F 3 "" H 6075 3625 60  0000 C CNN
+	1    6025 3675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 11800 3250
+F 0 "U?" H 11800 3500 60  0000 C CNN
+F 1 "d_inverter" H 11800 3350 60  0000 C CNN
+F 2 "" H 11850 3200 60  0000 C CNN
+F 3 "" H 11850 3200 60  0000 C CNN
+	1    11800 3250
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
+P 11800 3775
+F 0 "U?" H 11800 4050 60  0000 C CNN
+F 1 "d_inverter" H 11800 3900 60  0000 C CNN
+F 2 "" H 11850 3725 60  0000 C CNN
+F 3 "" H 11850 3725 60  0000 C CNN
+	1    11800 3775
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 7400 3675
+F 0 "U?" H 7400 4050 60  0000 C CNN
+F 1 "d_nand" H 7400 3900 60  0000 C CNN
+F 2 "" H 7400 3675 60  0000 C CNN
+F 3 "" H 7400 3675 60  0000 C CNN
+	1    7400 3675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
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+F 0 "U?" H 10300 3300 60  0000 C CNN
+F 1 "d_nand" H 10300 3450 60  0000 C CNN
+F 2 "" H 10300 3550 60  0000 C CNN
+F 3 "" H 10300 3550 60  0000 C CNN
+	1    10300 3550
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/analysis b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/analysis
new file mode 100644
index 000000000..14a32166e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/analysis
@@ -0,0 +1 @@
+.tran 1e-00 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.cir b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.cir
new file mode 100644
index 000000000..ef9d3ba11
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.cir
@@ -0,0 +1,17 @@
+.title KiCad schematic
+v1 Net-_M2-Pad1_ GND 5
+U10 Net-_M1-Pad1_ Net-_U1-Pad3_ adc_bridge_1
+U1 Net-_U1-Pad1_ Net-_U3-Pad1_ Net-_U1-Pad3_ PORT
+U9 Net-_U7-Pad3_ Net-_M2-Pad2_ dac_bridge_1
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N
+U12 Net-_U11-Pad3_ Net-_M1-Pad2_ dac_bridge_1
+U6 Net-_U4-Pad2_ Net-_U11-Pad1_ d_inverter
+U7 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U7-Pad3_ d_nand
+U8 Net-_U5-Pad2_ Net-_U11-Pad2_ d_inverter
+U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter
+U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.cir.out b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.cir.out
new file mode 100644
index 000000000..e6a210648
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.cir.out
@@ -0,0 +1,61 @@
+.title kicad schematic
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+v1 net-_m2-pad1_ gnd 5
+* u10 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+* u1 net-_u1-pad1_ net-_u3-pad1_ net-_u1-pad3_ port
+* u9 net-_u7-pad3_ net-_m2-pad2_ dac_bridge_1
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u12 net-_u11-pad3_ net-_m1-pad2_ dac_bridge_1
+* u6 net-_u4-pad2_ net-_u11-pad1_ d_inverter
+* u7 net-_u3-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_nand
+* u8 net-_u5-pad2_ net-_u11-pad2_ d_inverter
+* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u10
+a2 [net-_u7-pad3_ ] [net-_m2-pad2_ ] u9
+a3 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u11-pad3_ ] [net-_m1-pad2_ ] u12
+a5 net-_u4-pad2_ net-_u11-pad1_ u6
+a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7
+a7 net-_u5-pad2_ net-_u11-pad2_ u8
+a8 net-_u3-pad2_ net-_u5-pad2_ u5
+a9 net-_u2-pad2_ net-_u4-pad2_ u4
+a10 net-_u3-pad1_ net-_u3-pad2_ u3
+a11 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.kicad_sch b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.kicad_sch
new file mode 100644
index 000000000..6019a937e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.kicad_sch
@@ -0,0 +1,1395 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/560319ac-da1e-455d-b891-682c876e8b6b"
+      (reference "U7") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/4e7aee47-2e76-4251-b0c7-6407d4e1d214"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c1ae03d7-1841-4223-8020-c58d3678fce7"
+      (reference "U9") (unit 1) (value "dac_bridge_1") (footprint "")
+    )
+    (path "/78335dca-8e23-412f-bc38-5e0c391b4572"
+      (reference "U10") (unit 1) (value "adc_bridge_1") (footprint "")
+    )
+    (path "/e3b4407c-30c2-4ac1-abd6-ec5f1661b334"
+      (reference "U11") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/7436f534-d3fc-412c-86fb-eb34a5145528"
+      (reference "U12") (unit 1) (value "dac_bridge_1") (footprint "")
+    )
+    (path "/84616311-f8ff-4499-9bcb-57137b940961"
+      (reference "v1") (unit 1) (value "5") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.sub b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.sub
new file mode 100644
index 000000000..896e91db6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri.sub
@@ -0,0 +1,55 @@
+* Subcircuit buffer_tri
+.subckt buffer_tri net-_u1-pad1_ net-_u3-pad1_ net-_u1-pad3_ 
+.title kicad schematic
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+v1 net-_m2-pad1_ gnd 5
+* u10 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+* u9 net-_u7-pad3_ net-_m2-pad2_ dac_bridge_1
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u12 net-_u11-pad3_ net-_m1-pad2_ dac_bridge_1
+* u6 net-_u4-pad2_ net-_u11-pad1_ d_inverter
+* u7 net-_u3-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_nand
+* u8 net-_u5-pad2_ net-_u11-pad2_ d_inverter
+* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u10
+a2 [net-_u7-pad3_ ] [net-_m2-pad2_ ] u9
+a3 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u11-pad3_ ] [net-_m1-pad2_ ] u12
+a5 net-_u4-pad2_ net-_u11-pad1_ u6
+a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7
+a7 net-_u5-pad2_ net-_u11-pad2_ u8
+a8 net-_u3-pad2_ net-_u5-pad2_ u5
+a9 net-_u2-pad2_ net-_u4-pad2_ u4
+a10 net-_u3-pad1_ net-_u3-pad2_ u3
+a11 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends buffer_tri
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri_Previous_Values.xml
new file mode 100644
index 000000000..f98d4d44d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/74HC245_Test_Circuit/74HC245_TEST/buffer_tri_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v1 name="Source type">5</v1></source><model><u10 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u10><u9 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u9><u8 name="type">dac_bridge<field11 name="Enter value for out_low (default=0.0)" /><field12 name="Enter value for out_high (default=5.0)" /><field13 name="Enter value for out_undef (default=0.5)" /><field14 name="Enter value for input load (default=1.0e-12)" /><field15 name="Enter the Rise Time (default=1.0e-9)" /><field16 name="Enter the Fall Time (default=1.0e-9)" /></u8><u6 name="type">d_nand<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u7><u5 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_inverter<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">d_inverter<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /><field34 name="Enter Input Load (default=1.0e-12)" /></u2><u11 name="type">d_and<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">dac_bridge<field14 name="Enter value for out_low (default=0.0)" /><field15 name="Enter value for out_high (default=5.0)" /><field16 name="Enter value for out_undef (default=0.5)" /><field17 name="Enter value for input load (default=1.0e-12)" /><field18 name="Enter the Rise Time (default=1.0e-9)" /><field19 name="Enter the Fall Time (default=1.0e-9)" /></u12><u6 name="type">d_inverter<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_inverter<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1></devicemodel><subcircuit /><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/NMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC245/74HC245/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/PMOS-180nm.lib b/library/SubcircuitLibrary/IC74HC245/74HC245/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/_autosave-74HC245.sch b/library/SubcircuitLibrary/IC74HC245/74HC245/_autosave-74HC245.sch
new file mode 100644
index 000000000..27453edb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/_autosave-74HC245.sch
@@ -0,0 +1,610 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 6150 4675
+Connection ~ 6175 6350
+Connection ~ 6200 13350
+Connection ~ 6225 8075
+Connection ~ 6225 10000
+Connection ~ 6225 11675
+Connection ~ 6250 15250
+Connection ~ 6250 17250
+Connection ~ 7225 6350
+Connection ~ 7250 4675
+Connection ~ 7325 17250
+Connection ~ 7525 8075
+Connection ~ 7525 13350
+Connection ~ 7525 15250
+Connection ~ 7625 11675
+Connection ~ 7675 10000
+Connection ~ 8800 4400
+Connection ~ 8800 5875
+Connection ~ 8800 7550
+Connection ~ 8800 9450
+Connection ~ 8800 11175
+Connection ~ 8800 12875
+Connection ~ 8800 14675
+Connection ~ 9125 2800
+Connection ~ 9350 4900
+Connection ~ 9350 6650
+Connection ~ 9350 8375
+Connection ~ 9350 10350
+Connection ~ 9350 12025
+Connection ~ 9350 13675
+Connection ~ 9350 15625
+Connection ~ 10850 5150
+Connection ~ 10950 6975
+Connection ~ 11075 8750
+Connection ~ 11075 10625
+Connection ~ 11200 13975
+Connection ~ 11275 12300
+Connection ~ 11275 16050
+Connection ~ 11325 18050
+Connection ~ 11875 5150
+Connection ~ 11875 6975
+Connection ~ 11900 8750
+Connection ~ 12000 12300
+Connection ~ 12025 10625
+Connection ~ 12050 13975
+Connection ~ 12100 4125
+Connection ~ 12150 16050
+Connection ~ 12275 18050
+Wire Wire Line
+	5000 17250 6250 17250
+Wire Wire Line
+	5025 15250 6250 15250
+Wire Wire Line
+	5200 4675 6150 4675
+Wire Wire Line
+	5225 8075 6225 8075
+Wire Wire Line
+	5250 6350 6175 6350
+Wire Wire Line
+	5250 10000 6225 10000
+Wire Wire Line
+	5250 13350 6200 13350
+Wire Wire Line
+	5275 11675 6225 11675
+Wire Wire Line
+	5450 3675 5450 4125
+Wire Wire Line
+	5450 4125 12100 4125
+Wire Wire Line
+	5725 3675 5450 3675
+Wire Wire Line
+	6150 4675 6150 5150
+Wire Wire Line
+	6150 4675 7250 4675
+Wire Wire Line
+	6150 5150 10850 5150
+Wire Wire Line
+	6175 6350 6175 6975
+Wire Wire Line
+	6175 6350 7225 6350
+Wire Wire Line
+	6175 6975 10950 6975
+Wire Wire Line
+	6200 13350 6200 13975
+Wire Wire Line
+	6200 13350 7525 13350
+Wire Wire Line
+	6200 13975 11200 13975
+Wire Wire Line
+	6225 8075 6225 8750
+Wire Wire Line
+	6225 8075 7525 8075
+Wire Wire Line
+	6225 8750 11075 8750
+Wire Wire Line
+	6225 10000 6225 10625
+Wire Wire Line
+	6225 10000 7675 10000
+Wire Wire Line
+	6225 10625 11075 10625
+Wire Wire Line
+	6225 11675 6225 12300
+Wire Wire Line
+	6225 11675 7625 11675
+Wire Wire Line
+	6225 12300 11275 12300
+Wire Wire Line
+	6250 15250 6250 16050
+Wire Wire Line
+	6250 15250 7525 15250
+Wire Wire Line
+	6250 16050 11275 16050
+Wire Wire Line
+	6250 17250 6250 18050
+Wire Wire Line
+	6250 17250 7325 17250
+Wire Wire Line
+	6250 18050 11325 18050
+Wire Wire Line
+	6325 3675 6950 3675
+Wire Wire Line
+	6450 2800 6450 3575
+Wire Wire Line
+	6450 2800 9125 2800
+Wire Wire Line
+	6950 3575 6450 3575
+Wire Wire Line
+	7225 5875 8800 5875
+Wire Wire Line
+	7225 6350 7225 5875
+Wire Wire Line
+	7225 6350 11875 6350
+Wire Wire Line
+	7250 4400 8800 4400
+Wire Wire Line
+	7250 4675 7250 4400
+Wire Wire Line
+	7250 4675 11875 4675
+Wire Wire Line
+	7325 16725 8800 16725
+Wire Wire Line
+	7325 17250 7325 16725
+Wire Wire Line
+	7325 17250 12275 17250
+Wire Wire Line
+	7525 7550 8800 7550
+Wire Wire Line
+	7525 8075 7525 7550
+Wire Wire Line
+	7525 8075 11900 8075
+Wire Wire Line
+	7525 12875 8800 12875
+Wire Wire Line
+	7525 13350 7525 12875
+Wire Wire Line
+	7525 13350 12050 13350
+Wire Wire Line
+	7525 14675 8800 14675
+Wire Wire Line
+	7525 15250 7525 14675
+Wire Wire Line
+	7525 15250 12150 15250
+Wire Wire Line
+	7625 11175 8800 11175
+Wire Wire Line
+	7625 11675 7625 11175
+Wire Wire Line
+	7625 11675 12000 11675
+Wire Wire Line
+	7675 9450 8800 9450
+Wire Wire Line
+	7675 10000 7675 9450
+Wire Wire Line
+	7675 10000 12025 10000
+Wire Wire Line
+	7850 3625 8800 3625
+Wire Wire Line
+	8800 3625 8800 4400
+Wire Wire Line
+	8800 4400 8800 5875
+Wire Wire Line
+	8800 5875 8800 7550
+Wire Wire Line
+	8800 7550 8800 9450
+Wire Wire Line
+	8800 9450 8800 11175
+Wire Wire Line
+	8800 11175 8800 12875
+Wire Wire Line
+	8800 12875 8800 14675
+Wire Wire Line
+	8800 14675 8800 16725
+Wire Wire Line
+	9125 2550 9125 2800
+Wire Wire Line
+	9125 2800 12100 2800
+Wire Wire Line
+	9350 3600 9350 4900
+Wire Wire Line
+	9350 4900 9350 6650
+Wire Wire Line
+	9350 6650 9350 8375
+Wire Wire Line
+	9350 8375 9350 10350
+Wire Wire Line
+	9350 10350 9350 12025
+Wire Wire Line
+	9350 12025 9350 13675
+Wire Wire Line
+	9350 13675 9350 15625
+Wire Wire Line
+	9350 15625 9350 17650
+Wire Wire Line
+	9850 3600 9350 3600
+Wire Wire Line
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+F 2 "" H 17325 5150 60  0000 C CNN
+F 3 "" H 17325 5150 60  0000 C CNN
+	1    17325 5150
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+$EndComp
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+F 0 "U?" H 17350 5950 30  0000 C CNN
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+	2    17325 5775
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 3 1 00000000
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+F 0 "U?" H 17350 6750 30  0000 C CNN
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+	3    17325 6550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+P 17350 7300
+F 0 "U?" H 17375 7500 30  0000 C CNN
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+	4    17350 7300
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+	1    0    0    -1  
+$EndComp
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+	7    17450 9900
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+F 0 "U?" H 17500 10950 30  0000 C CNN
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+	9    17525 11500
+	1    0    0    -1  
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+	10   17675 12300
+	1    0    0    -1  
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+	20   18400 5150
+	1    0    0    -1  
+$EndComp
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+	19   18450 5900
+	1    0    0    -1  
+$EndComp
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+	18   18550 6625
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+	1    11800 3250
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+F 2 "" H 7400 3675 60  0000 C CNN
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diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/analysis b/library/SubcircuitLibrary/IC74HC245/74HC245/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.cir b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.cir
new file mode 100644
index 000000000..ef9d3ba11
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.cir
@@ -0,0 +1,17 @@
+.title KiCad schematic
+v1 Net-_M2-Pad1_ GND 5
+U10 Net-_M1-Pad1_ Net-_U1-Pad3_ adc_bridge_1
+U1 Net-_U1-Pad1_ Net-_U3-Pad1_ Net-_U1-Pad3_ PORT
+U9 Net-_U7-Pad3_ Net-_M2-Pad2_ dac_bridge_1
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N
+U12 Net-_U11-Pad3_ Net-_M1-Pad2_ dac_bridge_1
+U6 Net-_U4-Pad2_ Net-_U11-Pad1_ d_inverter
+U7 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U7-Pad3_ d_nand
+U8 Net-_U5-Pad2_ Net-_U11-Pad2_ d_inverter
+U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter
+U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.cir.out b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.cir.out
new file mode 100644
index 000000000..e6a210648
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.cir.out
@@ -0,0 +1,61 @@
+.title kicad schematic
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+v1 net-_m2-pad1_ gnd 5
+* u10 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+* u1 net-_u1-pad1_ net-_u3-pad1_ net-_u1-pad3_ port
+* u9 net-_u7-pad3_ net-_m2-pad2_ dac_bridge_1
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u12 net-_u11-pad3_ net-_m1-pad2_ dac_bridge_1
+* u6 net-_u4-pad2_ net-_u11-pad1_ d_inverter
+* u7 net-_u3-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_nand
+* u8 net-_u5-pad2_ net-_u11-pad2_ d_inverter
+* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u10
+a2 [net-_u7-pad3_ ] [net-_m2-pad2_ ] u9
+a3 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u11-pad3_ ] [net-_m1-pad2_ ] u12
+a5 net-_u4-pad2_ net-_u11-pad1_ u6
+a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7
+a7 net-_u5-pad2_ net-_u11-pad2_ u8
+a8 net-_u3-pad2_ net-_u5-pad2_ u5
+a9 net-_u2-pad2_ net-_u4-pad2_ u4
+a10 net-_u3-pad1_ net-_u3-pad2_ u3
+a11 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.kicad_sch b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.kicad_sch
new file mode 100644
index 000000000..6019a937e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.kicad_sch
@@ -0,0 +1,1395 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid dadf0df6-2196-4257-bb26-4dd5b342f8c3)
+
+  (paper "A4")
+
+  (lib_symbols
+    (symbol "eSim_Devices:eSim_MOS_N" (pin_names (offset 0) hide) (in_bom yes) (on_board yes)
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+        (effects (font (size 1.27 1.27)) (justify right))
+      )
+      (property "Value" "eSim_MOS_N" (id 1) (at 2.54 -1.27 0)
+        (effects (font (size 1.27 1.27)) (justify right))
+      )
+      (property "Footprint" "" (id 2) (at 7.62 -7.62 0)
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+      )
+      (property "Datasheet" "" (id 3) (at 2.54 -5.08 0)
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+      )
+      (symbol "eSim_MOS_N_0_1"
+        (polyline
+          (pts
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+        )
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+          (pts
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+          (pts
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+        (circle (center 3.81 -5.08) (radius 2.8194)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
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diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.sub b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.sub
new file mode 100644
index 000000000..896e91db6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri.sub
@@ -0,0 +1,55 @@
+* Subcircuit buffer_tri
+.subckt buffer_tri net-_u1-pad1_ net-_u3-pad1_ net-_u1-pad3_ 
+.title kicad schematic
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+v1 net-_m2-pad1_ gnd 5
+* u10 net-_m1-pad1_ net-_u1-pad3_ adc_bridge_1
+* u9 net-_u7-pad3_ net-_m2-pad2_ dac_bridge_1
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+* u12 net-_u11-pad3_ net-_m1-pad2_ dac_bridge_1
+* u6 net-_u4-pad2_ net-_u11-pad1_ d_inverter
+* u7 net-_u3-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_nand
+* u8 net-_u5-pad2_ net-_u11-pad2_ d_inverter
+* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+a1 [net-_m1-pad1_ ] [net-_u1-pad3_ ] u10
+a2 [net-_u7-pad3_ ] [net-_m2-pad2_ ] u9
+a3 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u11-pad3_ ] [net-_m1-pad2_ ] u12
+a5 net-_u4-pad2_ net-_u11-pad1_ u6
+a6 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7
+a7 net-_u5-pad2_ net-_u11-pad2_ u8
+a8 net-_u3-pad2_ net-_u5-pad2_ u5
+a9 net-_u2-pad2_ net-_u4-pad2_ u4
+a10 net-_u3-pad1_ net-_u3-pad2_ u3
+a11 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name:                             adc_bridge_1, Ngspice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, Ngspice Name: dac_bridge
+.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends buffer_tri
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri_Previous_Values.xml
new file mode 100644
index 000000000..f98d4d44d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC245/74HC245/buffer_tri_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v1 name="Source type">5</v1></source><model><u10 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u10><u9 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u9><u8 name="type">dac_bridge<field11 name="Enter value for out_low (default=0.0)" /><field12 name="Enter value for out_high (default=5.0)" /><field13 name="Enter value for out_undef (default=0.5)" /><field14 name="Enter value for input load (default=1.0e-12)" /><field15 name="Enter the Rise Time (default=1.0e-9)" /><field16 name="Enter the Fall Time (default=1.0e-9)" /></u8><u6 name="type">d_nand<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_nand<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u7><u5 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_inverter<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u4><u3 name="type">d_inverter<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /><field34 name="Enter Input Load (default=1.0e-12)" /></u2><u11 name="type">d_and<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">dac_bridge<field14 name="Enter value for out_low (default=0.0)" /><field15 name="Enter value for out_high (default=5.0)" /><field16 name="Enter value for out_undef (default=0.5)" /><field17 name="Enter value for input load (default=1.0e-12)" /><field18 name="Enter the Rise Time (default=1.0e-9)" /><field19 name="Enter the Fall Time (default=1.0e-9)" /></u12><u6 name="type">d_inverter<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_inverter<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1></devicemodel><subcircuit /><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.cir b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.cir
new file mode 100644
index 000000000..4508ed35c
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.cir
@@ -0,0 +1,83 @@
+.title KiCad schematic
+U27 Net-_U23-Pad3_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nand
+U19 Net-_U1-Pad4_ Net-_U19-Pad2_ d_inverter
+U23 Net-_U14-Pad3_ Net-_U18-Pad2_ Net-_U23-Pad3_ d_nand
+U15 Net-_U10-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or
+U22 Net-_U19-Pad2_ Net-_U15-Pad3_ Net-_U22-Pad3_ d_nand
+U26 Net-_U26-Pad1_ Net-_U22-Pad3_ Net-_U26-Pad3_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or
+U18 Net-_U1-Pad1_ Net-_U18-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U9 Net-_U27-Pad2_ Net-_U15-Pad2_ d_inverter
+U37 Net-_U29-Pad3_ Net-_U37-Pad2_ d_inverter
+U29 Net-_U25-Pad3_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_nand
+U20 Net-_U1-Pad13_ Net-_U20-Pad2_ d_inverter
+U25 Net-_U16-Pad3_ Net-_U20-Pad2_ Net-_U25-Pad3_ d_nand
+U21 Net-_U1-Pad10_ Net-_U21-Pad2_ d_inverter
+U24 Net-_U21-Pad2_ Net-_U17-Pad3_ Net-_U24-Pad3_ d_nand
+U28 Net-_U28-Pad1_ Net-_U24-Pad3_ Net-_U28-Pad3_ d_nand
+U42 Net-_U1-Pad13_ Net-_U42-Pad2_ d_inverter
+U35 Net-_U1-Pad13_ Net-_U35-Pad2_ d_inverter
+U34 Net-_U28-Pad3_ Net-_U34-Pad2_ d_inverter
+U43 Net-_U34-Pad2_ Net-_U35-Pad2_ Net-_U43-Pad3_ d_or
+U51 Net-_U42-Pad2_ Net-_U51-Pad2_ d_inverter
+U40 Net-_U30-Pad2_ Net-_U31-Pad2_ Net-_U40-Pad3_ d_or
+U31 Net-_U1-Pad1_ Net-_U31-Pad2_ d_inverter
+U39 Net-_U1-Pad1_ Net-_U39-Pad2_ d_inverter
+U41 Net-_U1-Pad10_ Net-_U41-Pad2_ d_inverter
+U36 Net-_U1-Pad10_ Net-_U36-Pad2_ d_inverter
+U32 Net-_U1-Pad4_ Net-_U32-Pad2_ d_inverter
+U49 Net-_U38-Pad2_ Net-_U49-Pad2_ d_inverter
+U38 Net-_U1-Pad4_ Net-_U38-Pad2_ d_inverter
+U30 Net-_U26-Pad3_ Net-_U30-Pad2_ d_inverter
+U33 Net-_U27-Pad3_ Net-_U33-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U11-Pad1_ Net-_U16-Pad3_ d_or
+U7 Net-_U3-Pad2_ Net-_U11-Pad1_ d_inverter
+U17 Net-_U13-Pad2_ Net-_U12-Pad2_ Net-_U17-Pad3_ d_or
+U13 Net-_U11-Pad2_ Net-_U13-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U12 Net-_U29-Pad2_ Net-_U12-Pad2_ d_inverter
+U3 Net-_U1-Pad12_ Net-_U3-Pad2_ d_inverter
+U6 Net-_U28-Pad1_ Net-_U16-Pad1_ d_inverter
+U4 Net-_U26-Pad1_ Net-_U14-Pad1_ d_inverter
+U5 Net-_U2-Pad2_ Net-_U14-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+U8 Net-_U14-Pad2_ Net-_U10-Pad1_ d_inverter
+U46 Net-_U1-Pad3_ Net-_U40-Pad3_ Net-_U27-Pad2_ d_nand
+U44 Net-_U32-Pad2_ Net-_U33-Pad2_ Net-_U44-Pad3_ d_or
+U48 Net-_U39-Pad2_ Net-_U48-Pad2_ d_inverter
+U60 Net-_U49-Pad2_ Net-_U60-Pad2_ d_inverter
+U50 Net-_U44-Pad3_ Net-_U1-Pad3_ Net-_U26-Pad1_ d_nand
+U56 Net-_U48-Pad2_ Net-_U56-Pad2_ d_inverter
+U55 Net-_U27-Pad2_ Net-_U55-Pad2_ d_inverter
+U54 Net-_U54-Pad1_ Net-_U54-Pad2_ d_inverter
+U67 Net-_U60-Pad2_ Net-_U61-Pad2_ Net-_U67-Pad3_ d_or
+U62 Net-_U62-Pad1_ Net-_U62-Pad2_ d_inverter
+U66 Net-_U54-Pad2_ Net-_U55-Pad2_ Net-_U66-Pad3_ d_or
+U71 Net-_U67-Pad3_ Net-_U62-Pad2_ Net-_U54-Pad1_ d_or
+U61 Net-_U26-Pad1_ Net-_U61-Pad2_ d_inverter
+U80 Net-_U76-Pad2_ Net-_U1-Pad8_ d_inverter
+U81 Net-_U77-Pad2_ Net-_U1-Pad9_ d_inverter
+U59 Net-_U51-Pad2_ Net-_U59-Pad2_ d_inverter
+U77 Net-_U57-Pad1_ Net-_U77-Pad2_ d_inverter
+U73 Net-_U69-Pad3_ Net-_U65-Pad2_ Net-_U57-Pad1_ d_or
+U72 Net-_U68-Pad3_ Net-_U59-Pad2_ Net-_U65-Pad1_ d_or
+U76 Net-_U65-Pad1_ Net-_U76-Pad2_ d_inverter
+U69 Net-_U63-Pad2_ Net-_U64-Pad2_ Net-_U69-Pad3_ d_or
+U58 Net-_U29-Pad2_ Net-_U58-Pad2_ d_inverter
+U57 Net-_U57-Pad1_ Net-_U57-Pad2_ d_inverter
+U45 Net-_U36-Pad2_ Net-_U37-Pad2_ Net-_U45-Pad3_ d_or
+U65 Net-_U65-Pad1_ Net-_U65-Pad2_ d_inverter
+U64 Net-_U28-Pad1_ Net-_U64-Pad2_ d_inverter
+U53 Net-_U45-Pad3_ Net-_U1-Pad11_ Net-_U28-Pad1_ d_nand
+U63 Net-_U52-Pad2_ Net-_U63-Pad2_ d_inverter
+U52 Net-_U41-Pad2_ Net-_U52-Pad2_ d_inverter
+U68 Net-_U57-Pad2_ Net-_U58-Pad2_ Net-_U68-Pad3_ d_or
+U47 Net-_U1-Pad11_ Net-_U43-Pad3_ Net-_U29-Pad2_ d_nand
+U79 Net-_U75-Pad2_ Net-_U1-Pad5_ d_inverter
+U75 Net-_U54-Pad1_ Net-_U75-Pad2_ d_inverter
+U74 Net-_U62-Pad1_ Net-_U74-Pad2_ d_inverter
+U78 Net-_U74-Pad2_ Net-_U1-Pad6_ d_inverter
+U70 Net-_U66-Pad3_ Net-_U56-Pad2_ Net-_U62-Pad1_ d_or
+.end
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.cir.out b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.cir.out
new file mode 100644
index 000000000..d4e216cb4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.cir.out
@@ -0,0 +1,332 @@
+.title kicad schematic
+
+* u27 net-_u23-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nand
+* u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter
+* u23 net-_u14-pad3_ net-_u18-pad2_ net-_u23-pad3_ d_nand
+* u15 net-_u10-pad2_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u22 net-_u19-pad2_ net-_u15-pad3_ net-_u22-pad3_ d_nand
+* u26 net-_u26-pad1_ net-_u22-pad3_ net-_u26-pad3_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u9 net-_u27-pad2_ net-_u15-pad2_ d_inverter
+* u37 net-_u29-pad3_ net-_u37-pad2_ d_inverter
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_nand
+* u20 net-_u1-pad13_ net-_u20-pad2_ d_inverter
+* u25 net-_u16-pad3_ net-_u20-pad2_ net-_u25-pad3_ d_nand
+* u21 net-_u1-pad10_ net-_u21-pad2_ d_inverter
+* u24 net-_u21-pad2_ net-_u17-pad3_ net-_u24-pad3_ d_nand
+* u28 net-_u28-pad1_ net-_u24-pad3_ net-_u28-pad3_ d_nand
+* u42 net-_u1-pad13_ net-_u42-pad2_ d_inverter
+* u35 net-_u1-pad13_ net-_u35-pad2_ d_inverter
+* u34 net-_u28-pad3_ net-_u34-pad2_ d_inverter
+* u43 net-_u34-pad2_ net-_u35-pad2_ net-_u43-pad3_ d_or
+* u51 net-_u42-pad2_ net-_u51-pad2_ d_inverter
+* u40 net-_u30-pad2_ net-_u31-pad2_ net-_u40-pad3_ d_or
+* u31 net-_u1-pad1_ net-_u31-pad2_ d_inverter
+* u39 net-_u1-pad1_ net-_u39-pad2_ d_inverter
+* u41 net-_u1-pad10_ net-_u41-pad2_ d_inverter
+* u36 net-_u1-pad10_ net-_u36-pad2_ d_inverter
+* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter
+* u49 net-_u38-pad2_ net-_u49-pad2_ d_inverter
+* u38 net-_u1-pad4_ net-_u38-pad2_ d_inverter
+* u30 net-_u26-pad3_ net-_u30-pad2_ d_inverter
+* u33 net-_u27-pad3_ net-_u33-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u11-pad1_ net-_u16-pad3_ d_or
+* u7 net-_u3-pad2_ net-_u11-pad1_ d_inverter
+* u17 net-_u13-pad2_ net-_u12-pad2_ net-_u17-pad3_ d_or
+* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u29-pad2_ net-_u12-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u3-pad2_ d_inverter
+* u6 net-_u28-pad1_ net-_u16-pad1_ d_inverter
+* u4 net-_u26-pad1_ net-_u14-pad1_ d_inverter
+* u5 net-_u2-pad2_ net-_u14-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u8 net-_u14-pad2_ net-_u10-pad1_ d_inverter
+* u46 net-_u1-pad3_ net-_u40-pad3_ net-_u27-pad2_ d_nand
+* u44 net-_u32-pad2_ net-_u33-pad2_ net-_u44-pad3_ d_or
+* u48 net-_u39-pad2_ net-_u48-pad2_ d_inverter
+* u60 net-_u49-pad2_ net-_u60-pad2_ d_inverter
+* u50 net-_u44-pad3_ net-_u1-pad3_ net-_u26-pad1_ d_nand
+* u56 net-_u48-pad2_ net-_u56-pad2_ d_inverter
+* u55 net-_u27-pad2_ net-_u55-pad2_ d_inverter
+* u54 net-_u54-pad1_ net-_u54-pad2_ d_inverter
+* u67 net-_u60-pad2_ net-_u61-pad2_ net-_u67-pad3_ d_or
+* u62 net-_u62-pad1_ net-_u62-pad2_ d_inverter
+* u66 net-_u54-pad2_ net-_u55-pad2_ net-_u66-pad3_ d_or
+* u71 net-_u67-pad3_ net-_u62-pad2_ net-_u54-pad1_ d_or
+* u61 net-_u26-pad1_ net-_u61-pad2_ d_inverter
+* u80 net-_u76-pad2_ net-_u1-pad8_ d_inverter
+* u81 net-_u77-pad2_ net-_u1-pad9_ d_inverter
+* u59 net-_u51-pad2_ net-_u59-pad2_ d_inverter
+* u77 net-_u57-pad1_ net-_u77-pad2_ d_inverter
+* u73 net-_u69-pad3_ net-_u65-pad2_ net-_u57-pad1_ d_or
+* u72 net-_u68-pad3_ net-_u59-pad2_ net-_u65-pad1_ d_or
+* u76 net-_u65-pad1_ net-_u76-pad2_ d_inverter
+* u69 net-_u63-pad2_ net-_u64-pad2_ net-_u69-pad3_ d_or
+* u58 net-_u29-pad2_ net-_u58-pad2_ d_inverter
+* u57 net-_u57-pad1_ net-_u57-pad2_ d_inverter
+* u45 net-_u36-pad2_ net-_u37-pad2_ net-_u45-pad3_ d_or
+* u65 net-_u65-pad1_ net-_u65-pad2_ d_inverter
+* u64 net-_u28-pad1_ net-_u64-pad2_ d_inverter
+* u53 net-_u45-pad3_ net-_u1-pad11_ net-_u28-pad1_ d_nand
+* u63 net-_u52-pad2_ net-_u63-pad2_ d_inverter
+* u52 net-_u41-pad2_ net-_u52-pad2_ d_inverter
+* u68 net-_u57-pad2_ net-_u58-pad2_ net-_u68-pad3_ d_or
+* u47 net-_u1-pad11_ net-_u43-pad3_ net-_u29-pad2_ d_nand
+* u79 net-_u75-pad2_ net-_u1-pad5_ d_inverter
+* u75 net-_u54-pad1_ net-_u75-pad2_ d_inverter
+* u74 net-_u62-pad1_ net-_u74-pad2_ d_inverter
+* u78 net-_u74-pad2_ net-_u1-pad6_ d_inverter
+* u70 net-_u66-pad3_ net-_u56-pad2_ net-_u62-pad1_ d_or
+a1 [net-_u23-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a2 net-_u1-pad4_ net-_u19-pad2_ u19
+a3 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u23-pad3_ u23
+a4 [net-_u10-pad2_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a5 [net-_u19-pad2_ net-_u15-pad3_ ] net-_u22-pad3_ u22
+a6 [net-_u26-pad1_ net-_u22-pad3_ ] net-_u26-pad3_ u26
+a7 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a8 net-_u1-pad1_ net-_u18-pad2_ u18
+a9 net-_u10-pad1_ net-_u10-pad2_ u10
+a10 net-_u27-pad2_ net-_u15-pad2_ u9
+a11 net-_u29-pad3_ net-_u37-pad2_ u37
+a12 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
+a13 net-_u1-pad13_ net-_u20-pad2_ u20
+a14 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u25-pad3_ u25
+a15 net-_u1-pad10_ net-_u21-pad2_ u21
+a16 [net-_u21-pad2_ net-_u17-pad3_ ] net-_u24-pad3_ u24
+a17 [net-_u28-pad1_ net-_u24-pad3_ ] net-_u28-pad3_ u28
+a18 net-_u1-pad13_ net-_u42-pad2_ u42
+a19 net-_u1-pad13_ net-_u35-pad2_ u35
+a20 net-_u28-pad3_ net-_u34-pad2_ u34
+a21 [net-_u34-pad2_ net-_u35-pad2_ ] net-_u43-pad3_ u43
+a22 net-_u42-pad2_ net-_u51-pad2_ u51
+a23 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u40-pad3_ u40
+a24 net-_u1-pad1_ net-_u31-pad2_ u31
+a25 net-_u1-pad1_ net-_u39-pad2_ u39
+a26 net-_u1-pad10_ net-_u41-pad2_ u41
+a27 net-_u1-pad10_ net-_u36-pad2_ u36
+a28 net-_u1-pad4_ net-_u32-pad2_ u32
+a29 net-_u38-pad2_ net-_u49-pad2_ u49
+a30 net-_u1-pad4_ net-_u38-pad2_ u38
+a31 net-_u26-pad3_ net-_u30-pad2_ u30
+a32 net-_u27-pad3_ net-_u33-pad2_ u33
+a33 [net-_u16-pad1_ net-_u11-pad1_ ] net-_u16-pad3_ u16
+a34 net-_u3-pad2_ net-_u11-pad1_ u7
+a35 [net-_u13-pad2_ net-_u12-pad2_ ] net-_u17-pad3_ u17
+a36 net-_u11-pad2_ net-_u13-pad2_ u13
+a37 net-_u11-pad1_ net-_u11-pad2_ u11
+a38 net-_u29-pad2_ net-_u12-pad2_ u12
+a39 net-_u1-pad12_ net-_u3-pad2_ u3
+a40 net-_u28-pad1_ net-_u16-pad1_ u6
+a41 net-_u26-pad1_ net-_u14-pad1_ u4
+a42 net-_u2-pad2_ net-_u14-pad2_ u5
+a43 net-_u1-pad2_ net-_u2-pad2_ u2
+a44 net-_u14-pad2_ net-_u10-pad1_ u8
+a45 [net-_u1-pad3_ net-_u40-pad3_ ] net-_u27-pad2_ u46
+a46 [net-_u32-pad2_ net-_u33-pad2_ ] net-_u44-pad3_ u44
+a47 net-_u39-pad2_ net-_u48-pad2_ u48
+a48 net-_u49-pad2_ net-_u60-pad2_ u60
+a49 [net-_u44-pad3_ net-_u1-pad3_ ] net-_u26-pad1_ u50
+a50 net-_u48-pad2_ net-_u56-pad2_ u56
+a51 net-_u27-pad2_ net-_u55-pad2_ u55
+a52 net-_u54-pad1_ net-_u54-pad2_ u54
+a53 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u67-pad3_ u67
+a54 net-_u62-pad1_ net-_u62-pad2_ u62
+a55 [net-_u54-pad2_ net-_u55-pad2_ ] net-_u66-pad3_ u66
+a56 [net-_u67-pad3_ net-_u62-pad2_ ] net-_u54-pad1_ u71
+a57 net-_u26-pad1_ net-_u61-pad2_ u61
+a58 net-_u76-pad2_ net-_u1-pad8_ u80
+a59 net-_u77-pad2_ net-_u1-pad9_ u81
+a60 net-_u51-pad2_ net-_u59-pad2_ u59
+a61 net-_u57-pad1_ net-_u77-pad2_ u77
+a62 [net-_u69-pad3_ net-_u65-pad2_ ] net-_u57-pad1_ u73
+a63 [net-_u68-pad3_ net-_u59-pad2_ ] net-_u65-pad1_ u72
+a64 net-_u65-pad1_ net-_u76-pad2_ u76
+a65 [net-_u63-pad2_ net-_u64-pad2_ ] net-_u69-pad3_ u69
+a66 net-_u29-pad2_ net-_u58-pad2_ u58
+a67 net-_u57-pad1_ net-_u57-pad2_ u57
+a68 [net-_u36-pad2_ net-_u37-pad2_ ] net-_u45-pad3_ u45
+a69 net-_u65-pad1_ net-_u65-pad2_ u65
+a70 net-_u28-pad1_ net-_u64-pad2_ u64
+a71 [net-_u45-pad3_ net-_u1-pad11_ ] net-_u28-pad1_ u53
+a72 net-_u52-pad2_ net-_u63-pad2_ u63
+a73 net-_u41-pad2_ net-_u52-pad2_ u52
+a74 [net-_u57-pad2_ net-_u58-pad2_ ] net-_u68-pad3_ u68
+a75 [net-_u1-pad11_ net-_u43-pad3_ ] net-_u29-pad2_ u47
+a76 net-_u75-pad2_ net-_u1-pad5_ u79
+a77 net-_u54-pad1_ net-_u75-pad2_ u75
+a78 net-_u62-pad1_ net-_u74-pad2_ u74
+a79 net-_u74-pad2_ net-_u1-pad6_ u78
+a80 [net-_u66-pad3_ net-_u56-pad2_ ] net-_u62-pad1_ u70
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u67 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u66 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u71 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u80 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u81 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u77 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u73 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u72 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u69 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u68 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u79 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u75 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u74 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u78 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u70 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.kicad_sch b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.kicad_sch
new file mode 100644
index 000000000..87981d8cc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.kicad_sch
@@ -0,0 +1,3785 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 3bb8b7af-047a-4360-8663-6561c342947d)
+
+  (paper "A2")
+
+  (lib_symbols
+    (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 -2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_inverter" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_inverter_0_1"
+        (polyline
+          (pts
+            (xy -2.54 1.27)
+            (xy -2.54 -1.27)
+            (xy 2.54 0)
+            (xy -2.54 1.27)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_inverter_1_1"
+        (pin input line (at -7.62 0 0) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output inverted (at 7.62 0 180) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_nand" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
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+    (path "/6e045a3a-3989-4963-9d91-b5f34b7ca335"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/67630c70-d17f-432a-82e4-b371fa9ab116"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/dddcfe91-5b9a-40e8-835d-105249d10983"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/3f173381-7da1-441e-8495-e35f0e0f9731"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/69312017-e726-428a-93b5-54d4daa00046"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/4dd1edb5-fccb-4690-8e35-1df9bf17bd97"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/520639fe-1dfb-477b-bf14-0accbc4e8398"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/1f532f10-bcc5-406d-a40d-a212ae5b3c08"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/4305b016-3480-4f80-9f52-8fce7cf764cc"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/d09020b7-f64b-4894-b353-474a624e7c23"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/f2bdb91e-d7eb-49d5-8a6b-aa9a1ad02808"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6651e19d-aaba-4fd2-8771-49ca20356038"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/ba92ddfb-c91e-4928-a244-3570080387be"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/91d94e06-3a48-4e06-960c-03a7c30fb7d8"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/27f98212-4c76-4a1e-a024-ed514063113d"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9a1e7bd0-3a82-421c-87d4-1892b208ea9b"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/0422fdcc-70a0-49d5-96a4-4a4f23e95608"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/382314cb-f0cc-430b-bea5-73b47ccc1749"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/bf995a5a-1ad6-4bbd-9480-12acb0dd0d61"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6f563e98-40b6-46a3-b0c7-2a98961cca02"
+      (reference "U11") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/d099cd74-4023-4bb7-9b8a-21625717ecd4"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/8677808c-7f9f-4db2-89a2-5abc942b718f"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3ef8d9f6-0d8c-4b1f-936f-f8eb10954529"
+      (reference "U14") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/73a55029-a6ca-479a-a95d-cdb7aa678740"
+      (reference "U15") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/106e0604-3448-433b-b686-c998f878bf2b"
+      (reference "U16") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/e7210409-6806-4d14-bd55-bcfa597a0bb8"
+      (reference "U17") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/ab04b719-0656-458e-9bfd-c2d80f1b1f3f"
+      (reference "U18") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/182eaca5-1cb8-4ebd-9092-647aca0841c3"
+      (reference "U19") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/d868cb38-4b74-453c-98fb-d11c896423da"
+      (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9c508346-d310-4419-a2e0-0a4aa898e938"
+      (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/2f9c1255-7965-4429-a2d5-d359708b07ab"
+      (reference "U22") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/b64c53ab-143f-480d-83ba-0f4f068b4fd9"
+      (reference "U23") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/13ac743d-e135-4323-aac7-221715e6c34b"
+      (reference "U24") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/00c70862-0fab-4f8f-9592-b9ebb55047ed"
+      (reference "U25") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/15e239b9-b20d-4891-9be3-e0c01da5563c"
+      (reference "U26") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/9d2deadc-1359-4735-8cf9-f5eeba3490b3"
+      (reference "U27") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/93fc15ca-8e12-47a3-81c9-052fb4d01798"
+      (reference "U28") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/58e576ba-0ee5-47a1-87eb-4601e3c6ff03"
+      (reference "U29") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/1d7b92bb-2f98-4bc2-9c77-c452d580d1d9"
+      (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/43f6a2bf-2af6-4b12-8e89-0a7573f02914"
+      (reference "U31") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/fc6b8d08-7170-4f6f-962c-4464549da175"
+      (reference "U32") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/fdb81c9d-8048-472f-8968-b9a889e21f72"
+      (reference "U33") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/854c1811-4a4d-4805-81c7-dd34ef0d03a7"
+      (reference "U34") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/7b14e90a-bb58-4cba-bd8c-b8e42cef4edf"
+      (reference "U35") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5734b0b0-9720-401a-8ea9-3ca408db70d8"
+      (reference "U36") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/2d85cf7b-7754-463a-9af6-48ce0552b513"
+      (reference "U37") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1167232c-2bfe-4dbc-8d77-868e5ec4abd2"
+      (reference "U38") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/243f882b-43af-4eb0-8994-9bb55679550a"
+      (reference "U39") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/2b5ae47b-0e34-4621-a447-ccb3ff833c97"
+      (reference "U40") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/ec78a4b9-ee2f-414b-8b78-70af18b42420"
+      (reference "U41") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3fab27e7-119f-4022-9338-60dc4dfe026e"
+      (reference "U42") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5163275f-d265-499b-8e35-b1c6c321f35d"
+      (reference "U43") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/495461c9-631c-4827-9af1-de3785f32b8d"
+      (reference "U44") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/a6dd8a46-7403-49f8-8b8e-4e7d15f50cb3"
+      (reference "U45") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/820910c6-75e5-4dc5-97ed-b04cc119f83d"
+      (reference "U46") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/041f4a83-9238-4b80-a87f-10961926fbf3"
+      (reference "U47") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/8090cfa0-e604-4b10-b529-c68dc11714b8"
+      (reference "U48") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/46a2bf07-81d8-448d-99ee-4f66756d0667"
+      (reference "U49") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/5886fdfc-f543-4630-b926-d0243a6971d0"
+      (reference "U50") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/e99762d8-fca9-41fb-96de-f8229a4095c9"
+      (reference "U51") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/2767ef63-74a4-499e-9312-c2e58f10ae4f"
+      (reference "U52") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/9429f5c2-0629-4d16-84cf-2f319291b082"
+      (reference "U53") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/9b223fa1-1149-4f84-b5c5-3f003313ea95"
+      (reference "U54") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a54ceaf7-9ace-40c7-bdbb-97a32be9a238"
+      (reference "U55") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f75303b5-502c-449f-b86a-0c3ff5fc4856"
+      (reference "U56") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/21792801-2718-4945-ac9c-69fbf94922a2"
+      (reference "U57") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/623696cb-0b3e-4219-9b7f-340ea7df2ccc"
+      (reference "U58") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c44aeffb-25da-4cb3-bdf1-1be3ca68ca93"
+      (reference "U59") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3c5bbf44-4ee9-4566-95de-6ae5ca33fd62"
+      (reference "U60") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/55f3b059-c9aa-4727-8da5-3d2c6ff7f533"
+      (reference "U61") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/ec22aafd-8fa6-41f4-98c1-850843d4fba4"
+      (reference "U62") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/7d661702-40fa-40a7-ab92-c0dbeebe1874"
+      (reference "U63") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1bb08a56-6638-4d6f-a187-b9d474bb101a"
+      (reference "U64") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/74c7ddc7-d5d3-47b9-8db6-482dc497fbce"
+      (reference "U65") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/bbc7dbe2-243e-4d00-8936-54b00d05228a"
+      (reference "U66") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/2a1c4086-8c80-4ae0-b26d-418bd6d6755d"
+      (reference "U67") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/0b7d60c7-7537-4549-80eb-2b88bf8c8418"
+      (reference "U68") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/b7aebff5-65bf-4829-8602-dce79c14c56d"
+      (reference "U69") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/bd61fc6a-eecf-4c3b-a2bd-1a04327edb22"
+      (reference "U70") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/48c80a70-c2fd-4ba0-a017-fee8bdd11ba5"
+      (reference "U71") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/9e9f7d38-4e52-4ba8-bdd9-739771816a2d"
+      (reference "U72") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/a2235f9b-23cd-432c-8f11-5d899ac9a605"
+      (reference "U73") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/8db53618-43ed-45e5-9ba5-cb7a89f8a643"
+      (reference "U74") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6ebf2afc-2141-47ca-aa36-30cedeccd050"
+      (reference "U75") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/51106126-5af2-43ab-a7ec-eb3f4b313763"
+      (reference "U76") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/dc069dae-eb63-4ef3-b8e2-de6cc1ddc442"
+      (reference "U77") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/81064fd3-2081-4aa3-8a38-0c989665ef43"
+      (reference "U78") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3f31db3a-0a3e-4485-8aa3-01948eadb705"
+      (reference "U79") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/dedf7ec9-753c-476d-8c97-3bff6d336494"
+      (reference "U80") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/73ba7ed3-8af1-4cda-a835-84d4bb258a92"
+      (reference "U81") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.sub b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.sub
new file mode 100644
index 000000000..51f80151e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A.sub
@@ -0,0 +1,326 @@
+* Subcircuit 74HC74A
+.subckt 74HC74A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u27 net-_u23-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nand
+* u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter
+* u23 net-_u14-pad3_ net-_u18-pad2_ net-_u23-pad3_ d_nand
+* u15 net-_u10-pad2_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u22 net-_u19-pad2_ net-_u15-pad3_ net-_u22-pad3_ d_nand
+* u26 net-_u26-pad1_ net-_u22-pad3_ net-_u26-pad3_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u9 net-_u27-pad2_ net-_u15-pad2_ d_inverter
+* u37 net-_u29-pad3_ net-_u37-pad2_ d_inverter
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_nand
+* u20 net-_u1-pad13_ net-_u20-pad2_ d_inverter
+* u25 net-_u16-pad3_ net-_u20-pad2_ net-_u25-pad3_ d_nand
+* u21 net-_u1-pad10_ net-_u21-pad2_ d_inverter
+* u24 net-_u21-pad2_ net-_u17-pad3_ net-_u24-pad3_ d_nand
+* u28 net-_u28-pad1_ net-_u24-pad3_ net-_u28-pad3_ d_nand
+* u42 net-_u1-pad13_ net-_u42-pad2_ d_inverter
+* u35 net-_u1-pad13_ net-_u35-pad2_ d_inverter
+* u34 net-_u28-pad3_ net-_u34-pad2_ d_inverter
+* u43 net-_u34-pad2_ net-_u35-pad2_ net-_u43-pad3_ d_or
+* u51 net-_u42-pad2_ net-_u51-pad2_ d_inverter
+* u40 net-_u30-pad2_ net-_u31-pad2_ net-_u40-pad3_ d_or
+* u31 net-_u1-pad1_ net-_u31-pad2_ d_inverter
+* u39 net-_u1-pad1_ net-_u39-pad2_ d_inverter
+* u41 net-_u1-pad10_ net-_u41-pad2_ d_inverter
+* u36 net-_u1-pad10_ net-_u36-pad2_ d_inverter
+* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter
+* u49 net-_u38-pad2_ net-_u49-pad2_ d_inverter
+* u38 net-_u1-pad4_ net-_u38-pad2_ d_inverter
+* u30 net-_u26-pad3_ net-_u30-pad2_ d_inverter
+* u33 net-_u27-pad3_ net-_u33-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u11-pad1_ net-_u16-pad3_ d_or
+* u7 net-_u3-pad2_ net-_u11-pad1_ d_inverter
+* u17 net-_u13-pad2_ net-_u12-pad2_ net-_u17-pad3_ d_or
+* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u29-pad2_ net-_u12-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u3-pad2_ d_inverter
+* u6 net-_u28-pad1_ net-_u16-pad1_ d_inverter
+* u4 net-_u26-pad1_ net-_u14-pad1_ d_inverter
+* u5 net-_u2-pad2_ net-_u14-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u8 net-_u14-pad2_ net-_u10-pad1_ d_inverter
+* u46 net-_u1-pad3_ net-_u40-pad3_ net-_u27-pad2_ d_nand
+* u44 net-_u32-pad2_ net-_u33-pad2_ net-_u44-pad3_ d_or
+* u48 net-_u39-pad2_ net-_u48-pad2_ d_inverter
+* u60 net-_u49-pad2_ net-_u60-pad2_ d_inverter
+* u50 net-_u44-pad3_ net-_u1-pad3_ net-_u26-pad1_ d_nand
+* u56 net-_u48-pad2_ net-_u56-pad2_ d_inverter
+* u55 net-_u27-pad2_ net-_u55-pad2_ d_inverter
+* u54 net-_u54-pad1_ net-_u54-pad2_ d_inverter
+* u67 net-_u60-pad2_ net-_u61-pad2_ net-_u67-pad3_ d_or
+* u62 net-_u62-pad1_ net-_u62-pad2_ d_inverter
+* u66 net-_u54-pad2_ net-_u55-pad2_ net-_u66-pad3_ d_or
+* u71 net-_u67-pad3_ net-_u62-pad2_ net-_u54-pad1_ d_or
+* u61 net-_u26-pad1_ net-_u61-pad2_ d_inverter
+* u80 net-_u76-pad2_ net-_u1-pad8_ d_inverter
+* u81 net-_u77-pad2_ net-_u1-pad9_ d_inverter
+* u59 net-_u51-pad2_ net-_u59-pad2_ d_inverter
+* u77 net-_u57-pad1_ net-_u77-pad2_ d_inverter
+* u73 net-_u69-pad3_ net-_u65-pad2_ net-_u57-pad1_ d_or
+* u72 net-_u68-pad3_ net-_u59-pad2_ net-_u65-pad1_ d_or
+* u76 net-_u65-pad1_ net-_u76-pad2_ d_inverter
+* u69 net-_u63-pad2_ net-_u64-pad2_ net-_u69-pad3_ d_or
+* u58 net-_u29-pad2_ net-_u58-pad2_ d_inverter
+* u57 net-_u57-pad1_ net-_u57-pad2_ d_inverter
+* u45 net-_u36-pad2_ net-_u37-pad2_ net-_u45-pad3_ d_or
+* u65 net-_u65-pad1_ net-_u65-pad2_ d_inverter
+* u64 net-_u28-pad1_ net-_u64-pad2_ d_inverter
+* u53 net-_u45-pad3_ net-_u1-pad11_ net-_u28-pad1_ d_nand
+* u63 net-_u52-pad2_ net-_u63-pad2_ d_inverter
+* u52 net-_u41-pad2_ net-_u52-pad2_ d_inverter
+* u68 net-_u57-pad2_ net-_u58-pad2_ net-_u68-pad3_ d_or
+* u47 net-_u1-pad11_ net-_u43-pad3_ net-_u29-pad2_ d_nand
+* u79 net-_u75-pad2_ net-_u1-pad5_ d_inverter
+* u75 net-_u54-pad1_ net-_u75-pad2_ d_inverter
+* u74 net-_u62-pad1_ net-_u74-pad2_ d_inverter
+* u78 net-_u74-pad2_ net-_u1-pad6_ d_inverter
+* u70 net-_u66-pad3_ net-_u56-pad2_ net-_u62-pad1_ d_or
+a1 [net-_u23-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a2 net-_u1-pad4_ net-_u19-pad2_ u19
+a3 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u23-pad3_ u23
+a4 [net-_u10-pad2_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a5 [net-_u19-pad2_ net-_u15-pad3_ ] net-_u22-pad3_ u22
+a6 [net-_u26-pad1_ net-_u22-pad3_ ] net-_u26-pad3_ u26
+a7 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a8 net-_u1-pad1_ net-_u18-pad2_ u18
+a9 net-_u10-pad1_ net-_u10-pad2_ u10
+a10 net-_u27-pad2_ net-_u15-pad2_ u9
+a11 net-_u29-pad3_ net-_u37-pad2_ u37
+a12 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
+a13 net-_u1-pad13_ net-_u20-pad2_ u20
+a14 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u25-pad3_ u25
+a15 net-_u1-pad10_ net-_u21-pad2_ u21
+a16 [net-_u21-pad2_ net-_u17-pad3_ ] net-_u24-pad3_ u24
+a17 [net-_u28-pad1_ net-_u24-pad3_ ] net-_u28-pad3_ u28
+a18 net-_u1-pad13_ net-_u42-pad2_ u42
+a19 net-_u1-pad13_ net-_u35-pad2_ u35
+a20 net-_u28-pad3_ net-_u34-pad2_ u34
+a21 [net-_u34-pad2_ net-_u35-pad2_ ] net-_u43-pad3_ u43
+a22 net-_u42-pad2_ net-_u51-pad2_ u51
+a23 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u40-pad3_ u40
+a24 net-_u1-pad1_ net-_u31-pad2_ u31
+a25 net-_u1-pad1_ net-_u39-pad2_ u39
+a26 net-_u1-pad10_ net-_u41-pad2_ u41
+a27 net-_u1-pad10_ net-_u36-pad2_ u36
+a28 net-_u1-pad4_ net-_u32-pad2_ u32
+a29 net-_u38-pad2_ net-_u49-pad2_ u49
+a30 net-_u1-pad4_ net-_u38-pad2_ u38
+a31 net-_u26-pad3_ net-_u30-pad2_ u30
+a32 net-_u27-pad3_ net-_u33-pad2_ u33
+a33 [net-_u16-pad1_ net-_u11-pad1_ ] net-_u16-pad3_ u16
+a34 net-_u3-pad2_ net-_u11-pad1_ u7
+a35 [net-_u13-pad2_ net-_u12-pad2_ ] net-_u17-pad3_ u17
+a36 net-_u11-pad2_ net-_u13-pad2_ u13
+a37 net-_u11-pad1_ net-_u11-pad2_ u11
+a38 net-_u29-pad2_ net-_u12-pad2_ u12
+a39 net-_u1-pad12_ net-_u3-pad2_ u3
+a40 net-_u28-pad1_ net-_u16-pad1_ u6
+a41 net-_u26-pad1_ net-_u14-pad1_ u4
+a42 net-_u2-pad2_ net-_u14-pad2_ u5
+a43 net-_u1-pad2_ net-_u2-pad2_ u2
+a44 net-_u14-pad2_ net-_u10-pad1_ u8
+a45 [net-_u1-pad3_ net-_u40-pad3_ ] net-_u27-pad2_ u46
+a46 [net-_u32-pad2_ net-_u33-pad2_ ] net-_u44-pad3_ u44
+a47 net-_u39-pad2_ net-_u48-pad2_ u48
+a48 net-_u49-pad2_ net-_u60-pad2_ u60
+a49 [net-_u44-pad3_ net-_u1-pad3_ ] net-_u26-pad1_ u50
+a50 net-_u48-pad2_ net-_u56-pad2_ u56
+a51 net-_u27-pad2_ net-_u55-pad2_ u55
+a52 net-_u54-pad1_ net-_u54-pad2_ u54
+a53 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u67-pad3_ u67
+a54 net-_u62-pad1_ net-_u62-pad2_ u62
+a55 [net-_u54-pad2_ net-_u55-pad2_ ] net-_u66-pad3_ u66
+a56 [net-_u67-pad3_ net-_u62-pad2_ ] net-_u54-pad1_ u71
+a57 net-_u26-pad1_ net-_u61-pad2_ u61
+a58 net-_u76-pad2_ net-_u1-pad8_ u80
+a59 net-_u77-pad2_ net-_u1-pad9_ u81
+a60 net-_u51-pad2_ net-_u59-pad2_ u59
+a61 net-_u57-pad1_ net-_u77-pad2_ u77
+a62 [net-_u69-pad3_ net-_u65-pad2_ ] net-_u57-pad1_ u73
+a63 [net-_u68-pad3_ net-_u59-pad2_ ] net-_u65-pad1_ u72
+a64 net-_u65-pad1_ net-_u76-pad2_ u76
+a65 [net-_u63-pad2_ net-_u64-pad2_ ] net-_u69-pad3_ u69
+a66 net-_u29-pad2_ net-_u58-pad2_ u58
+a67 net-_u57-pad1_ net-_u57-pad2_ u57
+a68 [net-_u36-pad2_ net-_u37-pad2_ ] net-_u45-pad3_ u45
+a69 net-_u65-pad1_ net-_u65-pad2_ u65
+a70 net-_u28-pad1_ net-_u64-pad2_ u64
+a71 [net-_u45-pad3_ net-_u1-pad11_ ] net-_u28-pad1_ u53
+a72 net-_u52-pad2_ net-_u63-pad2_ u63
+a73 net-_u41-pad2_ net-_u52-pad2_ u52
+a74 [net-_u57-pad2_ net-_u58-pad2_ ] net-_u68-pad3_ u68
+a75 [net-_u1-pad11_ net-_u43-pad3_ ] net-_u29-pad2_ u47
+a76 net-_u75-pad2_ net-_u1-pad5_ u79
+a77 net-_u54-pad1_ net-_u75-pad2_ u75
+a78 net-_u62-pad1_ net-_u74-pad2_ u74
+a79 net-_u74-pad2_ net-_u1-pad6_ u78
+a80 [net-_u66-pad3_ net-_u56-pad2_ ] net-_u62-pad1_ u70
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u67 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u66 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u71 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u80 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u81 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u77 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u73 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u72 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u69 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u68 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u79 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u75 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u74 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u78 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u70 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC74A
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Previous_Values.xml
new file mode 100644
index 000000000..40bce30b6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u27 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u27><u19 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u23><u15 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u15><u22 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u26><u14 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u10 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u9><u37 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u37><u29 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u29><u20 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u20><u25 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u25><u21 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u24><u28 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u28><u42 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u42><u35 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u35><u34 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u34><u43 name="type">d_or<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u43><u51 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u51><u40 name="type">d_or<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u40><u31 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u31><u39 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u39><u41 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u41><u36 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u36><u32 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u32><u49 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u49><u38 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u38><u30 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u30><u33 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u33><u16 name="type">d_or<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u16><u7 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u7><u17 name="type">d_or<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u12><u3 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u2><u8 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u8><u46 name="type">d_nand<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u46><u44 name="type">d_or<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u44><u48 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u48><u60 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u60><u50 name="type">d_nand<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u50><u56 name="type">d_inverter<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u56><u55 name="type">d_inverter<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u55><u54 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u54><u67 name="type">d_or<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u67><u62 name="type">d_inverter<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u62><u66 name="type">d_or<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u66><u71 name="type">d_or<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u71><u61 name="type">d_inverter<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u61><u80 name="type">d_inverter<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u80><u81 name="type">d_inverter<field175 name="Enter Rise Delay (default=1.0e-9)" /><field176 name="Enter Fall Delay (default=1.0e-9)" /><field177 name="Enter Input Load (default=1.0e-12)" /></u81><u59 name="type">d_inverter<field178 name="Enter Rise Delay (default=1.0e-9)" /><field179 name="Enter Fall Delay (default=1.0e-9)" /><field180 name="Enter Input Load (default=1.0e-12)" /></u59><u77 name="type">d_inverter<field181 name="Enter Rise Delay (default=1.0e-9)" /><field182 name="Enter Fall Delay (default=1.0e-9)" /><field183 name="Enter Input Load (default=1.0e-12)" /></u77><u73 name="type">d_or<field184 name="Enter Rise Delay (default=1.0e-9)" /><field185 name="Enter Fall Delay (default=1.0e-9)" /><field186 name="Enter Input Load (default=1.0e-12)" /></u73><u72 name="type">d_or<field187 name="Enter Rise Delay (default=1.0e-9)" /><field188 name="Enter Fall Delay (default=1.0e-9)" /><field189 name="Enter Input Load (default=1.0e-12)" /></u72><u76 name="type">d_inverter<field190 name="Enter Rise Delay (default=1.0e-9)" /><field191 name="Enter Fall Delay (default=1.0e-9)" /><field192 name="Enter Input Load (default=1.0e-12)" /></u76><u69 name="type">d_or<field193 name="Enter Rise Delay (default=1.0e-9)" /><field194 name="Enter Fall Delay (default=1.0e-9)" /><field195 name="Enter Input Load (default=1.0e-12)" /></u69><u58 name="type">d_inverter<field196 name="Enter Rise Delay (default=1.0e-9)" /><field197 name="Enter Fall Delay (default=1.0e-9)" /><field198 name="Enter Input Load (default=1.0e-12)" /></u58><u57 name="type">d_inverter<field199 name="Enter Rise Delay (default=1.0e-9)" /><field200 name="Enter Fall Delay (default=1.0e-9)" /><field201 name="Enter Input Load (default=1.0e-12)" /></u57><u45 name="type">d_or<field202 name="Enter Rise Delay (default=1.0e-9)" /><field203 name="Enter Fall Delay (default=1.0e-9)" /><field204 name="Enter Input Load (default=1.0e-12)" /></u45><u65 name="type">d_inverter<field205 name="Enter Rise Delay (default=1.0e-9)" /><field206 name="Enter Fall Delay (default=1.0e-9)" /><field207 name="Enter Input Load (default=1.0e-12)" /></u65><u64 name="type">d_inverter<field208 name="Enter Rise Delay (default=1.0e-9)" /><field209 name="Enter Fall Delay (default=1.0e-9)" /><field210 name="Enter Input Load (default=1.0e-12)" /></u64><u53 name="type">d_nand<field211 name="Enter Rise Delay (default=1.0e-9)" /><field212 name="Enter Fall Delay (default=1.0e-9)" /><field213 name="Enter Input Load (default=1.0e-12)" /></u53><u63 name="type">d_inverter<field214 name="Enter Rise Delay (default=1.0e-9)" /><field215 name="Enter Fall Delay (default=1.0e-9)" /><field216 name="Enter Input Load (default=1.0e-12)" /></u63><u52 name="type">d_inverter<field217 name="Enter Rise Delay (default=1.0e-9)" /><field218 name="Enter Fall Delay (default=1.0e-9)" /><field219 name="Enter Input Load (default=1.0e-12)" /></u52><u68 name="type">d_or<field220 name="Enter Rise Delay (default=1.0e-9)" /><field221 name="Enter Fall Delay (default=1.0e-9)" /><field222 name="Enter Input Load (default=1.0e-12)" /></u68><u47 name="type">d_nand<field223 name="Enter Rise Delay (default=1.0e-9)" /><field224 name="Enter Fall Delay (default=1.0e-9)" /><field225 name="Enter Input Load (default=1.0e-12)" /></u47><u79 name="type">d_inverter<field226 name="Enter Rise Delay (default=1.0e-9)" /><field227 name="Enter Fall Delay (default=1.0e-9)" /><field228 name="Enter Input Load (default=1.0e-12)" /></u79><u75 name="type">d_inverter<field229 name="Enter Rise Delay (default=1.0e-9)" /><field230 name="Enter Fall Delay (default=1.0e-9)" /><field231 name="Enter Input Load (default=1.0e-12)" /></u75><u74 name="type">d_inverter<field232 name="Enter Rise Delay (default=1.0e-9)" /><field233 name="Enter Fall Delay (default=1.0e-9)" /><field234 name="Enter Input Load (default=1.0e-12)" /></u74><u78 name="type">d_inverter<field235 name="Enter Rise Delay (default=1.0e-9)" /><field236 name="Enter Fall Delay (default=1.0e-9)" /><field237 name="Enter Input Load (default=1.0e-12)" /></u78><u70 name="type">d_or<field238 name="Enter Rise Delay (default=1.0e-9)" /><field239 name="Enter Fall Delay (default=1.0e-9)" /><field240 name="Enter Input Load (default=1.0e-12)" /></u70></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.cir b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.cir
new file mode 100644
index 000000000..4508ed35c
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.cir
@@ -0,0 +1,83 @@
+.title KiCad schematic
+U27 Net-_U23-Pad3_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nand
+U19 Net-_U1-Pad4_ Net-_U19-Pad2_ d_inverter
+U23 Net-_U14-Pad3_ Net-_U18-Pad2_ Net-_U23-Pad3_ d_nand
+U15 Net-_U10-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or
+U22 Net-_U19-Pad2_ Net-_U15-Pad3_ Net-_U22-Pad3_ d_nand
+U26 Net-_U26-Pad1_ Net-_U22-Pad3_ Net-_U26-Pad3_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or
+U18 Net-_U1-Pad1_ Net-_U18-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U9 Net-_U27-Pad2_ Net-_U15-Pad2_ d_inverter
+U37 Net-_U29-Pad3_ Net-_U37-Pad2_ d_inverter
+U29 Net-_U25-Pad3_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_nand
+U20 Net-_U1-Pad13_ Net-_U20-Pad2_ d_inverter
+U25 Net-_U16-Pad3_ Net-_U20-Pad2_ Net-_U25-Pad3_ d_nand
+U21 Net-_U1-Pad10_ Net-_U21-Pad2_ d_inverter
+U24 Net-_U21-Pad2_ Net-_U17-Pad3_ Net-_U24-Pad3_ d_nand
+U28 Net-_U28-Pad1_ Net-_U24-Pad3_ Net-_U28-Pad3_ d_nand
+U42 Net-_U1-Pad13_ Net-_U42-Pad2_ d_inverter
+U35 Net-_U1-Pad13_ Net-_U35-Pad2_ d_inverter
+U34 Net-_U28-Pad3_ Net-_U34-Pad2_ d_inverter
+U43 Net-_U34-Pad2_ Net-_U35-Pad2_ Net-_U43-Pad3_ d_or
+U51 Net-_U42-Pad2_ Net-_U51-Pad2_ d_inverter
+U40 Net-_U30-Pad2_ Net-_U31-Pad2_ Net-_U40-Pad3_ d_or
+U31 Net-_U1-Pad1_ Net-_U31-Pad2_ d_inverter
+U39 Net-_U1-Pad1_ Net-_U39-Pad2_ d_inverter
+U41 Net-_U1-Pad10_ Net-_U41-Pad2_ d_inverter
+U36 Net-_U1-Pad10_ Net-_U36-Pad2_ d_inverter
+U32 Net-_U1-Pad4_ Net-_U32-Pad2_ d_inverter
+U49 Net-_U38-Pad2_ Net-_U49-Pad2_ d_inverter
+U38 Net-_U1-Pad4_ Net-_U38-Pad2_ d_inverter
+U30 Net-_U26-Pad3_ Net-_U30-Pad2_ d_inverter
+U33 Net-_U27-Pad3_ Net-_U33-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U11-Pad1_ Net-_U16-Pad3_ d_or
+U7 Net-_U3-Pad2_ Net-_U11-Pad1_ d_inverter
+U17 Net-_U13-Pad2_ Net-_U12-Pad2_ Net-_U17-Pad3_ d_or
+U13 Net-_U11-Pad2_ Net-_U13-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U12 Net-_U29-Pad2_ Net-_U12-Pad2_ d_inverter
+U3 Net-_U1-Pad12_ Net-_U3-Pad2_ d_inverter
+U6 Net-_U28-Pad1_ Net-_U16-Pad1_ d_inverter
+U4 Net-_U26-Pad1_ Net-_U14-Pad1_ d_inverter
+U5 Net-_U2-Pad2_ Net-_U14-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+U8 Net-_U14-Pad2_ Net-_U10-Pad1_ d_inverter
+U46 Net-_U1-Pad3_ Net-_U40-Pad3_ Net-_U27-Pad2_ d_nand
+U44 Net-_U32-Pad2_ Net-_U33-Pad2_ Net-_U44-Pad3_ d_or
+U48 Net-_U39-Pad2_ Net-_U48-Pad2_ d_inverter
+U60 Net-_U49-Pad2_ Net-_U60-Pad2_ d_inverter
+U50 Net-_U44-Pad3_ Net-_U1-Pad3_ Net-_U26-Pad1_ d_nand
+U56 Net-_U48-Pad2_ Net-_U56-Pad2_ d_inverter
+U55 Net-_U27-Pad2_ Net-_U55-Pad2_ d_inverter
+U54 Net-_U54-Pad1_ Net-_U54-Pad2_ d_inverter
+U67 Net-_U60-Pad2_ Net-_U61-Pad2_ Net-_U67-Pad3_ d_or
+U62 Net-_U62-Pad1_ Net-_U62-Pad2_ d_inverter
+U66 Net-_U54-Pad2_ Net-_U55-Pad2_ Net-_U66-Pad3_ d_or
+U71 Net-_U67-Pad3_ Net-_U62-Pad2_ Net-_U54-Pad1_ d_or
+U61 Net-_U26-Pad1_ Net-_U61-Pad2_ d_inverter
+U80 Net-_U76-Pad2_ Net-_U1-Pad8_ d_inverter
+U81 Net-_U77-Pad2_ Net-_U1-Pad9_ d_inverter
+U59 Net-_U51-Pad2_ Net-_U59-Pad2_ d_inverter
+U77 Net-_U57-Pad1_ Net-_U77-Pad2_ d_inverter
+U73 Net-_U69-Pad3_ Net-_U65-Pad2_ Net-_U57-Pad1_ d_or
+U72 Net-_U68-Pad3_ Net-_U59-Pad2_ Net-_U65-Pad1_ d_or
+U76 Net-_U65-Pad1_ Net-_U76-Pad2_ d_inverter
+U69 Net-_U63-Pad2_ Net-_U64-Pad2_ Net-_U69-Pad3_ d_or
+U58 Net-_U29-Pad2_ Net-_U58-Pad2_ d_inverter
+U57 Net-_U57-Pad1_ Net-_U57-Pad2_ d_inverter
+U45 Net-_U36-Pad2_ Net-_U37-Pad2_ Net-_U45-Pad3_ d_or
+U65 Net-_U65-Pad1_ Net-_U65-Pad2_ d_inverter
+U64 Net-_U28-Pad1_ Net-_U64-Pad2_ d_inverter
+U53 Net-_U45-Pad3_ Net-_U1-Pad11_ Net-_U28-Pad1_ d_nand
+U63 Net-_U52-Pad2_ Net-_U63-Pad2_ d_inverter
+U52 Net-_U41-Pad2_ Net-_U52-Pad2_ d_inverter
+U68 Net-_U57-Pad2_ Net-_U58-Pad2_ Net-_U68-Pad3_ d_or
+U47 Net-_U1-Pad11_ Net-_U43-Pad3_ Net-_U29-Pad2_ d_nand
+U79 Net-_U75-Pad2_ Net-_U1-Pad5_ d_inverter
+U75 Net-_U54-Pad1_ Net-_U75-Pad2_ d_inverter
+U74 Net-_U62-Pad1_ Net-_U74-Pad2_ d_inverter
+U78 Net-_U74-Pad2_ Net-_U1-Pad6_ d_inverter
+U70 Net-_U66-Pad3_ Net-_U56-Pad2_ Net-_U62-Pad1_ d_or
+.end
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.cir.out b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.cir.out
new file mode 100644
index 000000000..d4e216cb4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.cir.out
@@ -0,0 +1,332 @@
+.title kicad schematic
+
+* u27 net-_u23-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nand
+* u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter
+* u23 net-_u14-pad3_ net-_u18-pad2_ net-_u23-pad3_ d_nand
+* u15 net-_u10-pad2_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u22 net-_u19-pad2_ net-_u15-pad3_ net-_u22-pad3_ d_nand
+* u26 net-_u26-pad1_ net-_u22-pad3_ net-_u26-pad3_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u9 net-_u27-pad2_ net-_u15-pad2_ d_inverter
+* u37 net-_u29-pad3_ net-_u37-pad2_ d_inverter
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_nand
+* u20 net-_u1-pad13_ net-_u20-pad2_ d_inverter
+* u25 net-_u16-pad3_ net-_u20-pad2_ net-_u25-pad3_ d_nand
+* u21 net-_u1-pad10_ net-_u21-pad2_ d_inverter
+* u24 net-_u21-pad2_ net-_u17-pad3_ net-_u24-pad3_ d_nand
+* u28 net-_u28-pad1_ net-_u24-pad3_ net-_u28-pad3_ d_nand
+* u42 net-_u1-pad13_ net-_u42-pad2_ d_inverter
+* u35 net-_u1-pad13_ net-_u35-pad2_ d_inverter
+* u34 net-_u28-pad3_ net-_u34-pad2_ d_inverter
+* u43 net-_u34-pad2_ net-_u35-pad2_ net-_u43-pad3_ d_or
+* u51 net-_u42-pad2_ net-_u51-pad2_ d_inverter
+* u40 net-_u30-pad2_ net-_u31-pad2_ net-_u40-pad3_ d_or
+* u31 net-_u1-pad1_ net-_u31-pad2_ d_inverter
+* u39 net-_u1-pad1_ net-_u39-pad2_ d_inverter
+* u41 net-_u1-pad10_ net-_u41-pad2_ d_inverter
+* u36 net-_u1-pad10_ net-_u36-pad2_ d_inverter
+* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter
+* u49 net-_u38-pad2_ net-_u49-pad2_ d_inverter
+* u38 net-_u1-pad4_ net-_u38-pad2_ d_inverter
+* u30 net-_u26-pad3_ net-_u30-pad2_ d_inverter
+* u33 net-_u27-pad3_ net-_u33-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u11-pad1_ net-_u16-pad3_ d_or
+* u7 net-_u3-pad2_ net-_u11-pad1_ d_inverter
+* u17 net-_u13-pad2_ net-_u12-pad2_ net-_u17-pad3_ d_or
+* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u29-pad2_ net-_u12-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u3-pad2_ d_inverter
+* u6 net-_u28-pad1_ net-_u16-pad1_ d_inverter
+* u4 net-_u26-pad1_ net-_u14-pad1_ d_inverter
+* u5 net-_u2-pad2_ net-_u14-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u8 net-_u14-pad2_ net-_u10-pad1_ d_inverter
+* u46 net-_u1-pad3_ net-_u40-pad3_ net-_u27-pad2_ d_nand
+* u44 net-_u32-pad2_ net-_u33-pad2_ net-_u44-pad3_ d_or
+* u48 net-_u39-pad2_ net-_u48-pad2_ d_inverter
+* u60 net-_u49-pad2_ net-_u60-pad2_ d_inverter
+* u50 net-_u44-pad3_ net-_u1-pad3_ net-_u26-pad1_ d_nand
+* u56 net-_u48-pad2_ net-_u56-pad2_ d_inverter
+* u55 net-_u27-pad2_ net-_u55-pad2_ d_inverter
+* u54 net-_u54-pad1_ net-_u54-pad2_ d_inverter
+* u67 net-_u60-pad2_ net-_u61-pad2_ net-_u67-pad3_ d_or
+* u62 net-_u62-pad1_ net-_u62-pad2_ d_inverter
+* u66 net-_u54-pad2_ net-_u55-pad2_ net-_u66-pad3_ d_or
+* u71 net-_u67-pad3_ net-_u62-pad2_ net-_u54-pad1_ d_or
+* u61 net-_u26-pad1_ net-_u61-pad2_ d_inverter
+* u80 net-_u76-pad2_ net-_u1-pad8_ d_inverter
+* u81 net-_u77-pad2_ net-_u1-pad9_ d_inverter
+* u59 net-_u51-pad2_ net-_u59-pad2_ d_inverter
+* u77 net-_u57-pad1_ net-_u77-pad2_ d_inverter
+* u73 net-_u69-pad3_ net-_u65-pad2_ net-_u57-pad1_ d_or
+* u72 net-_u68-pad3_ net-_u59-pad2_ net-_u65-pad1_ d_or
+* u76 net-_u65-pad1_ net-_u76-pad2_ d_inverter
+* u69 net-_u63-pad2_ net-_u64-pad2_ net-_u69-pad3_ d_or
+* u58 net-_u29-pad2_ net-_u58-pad2_ d_inverter
+* u57 net-_u57-pad1_ net-_u57-pad2_ d_inverter
+* u45 net-_u36-pad2_ net-_u37-pad2_ net-_u45-pad3_ d_or
+* u65 net-_u65-pad1_ net-_u65-pad2_ d_inverter
+* u64 net-_u28-pad1_ net-_u64-pad2_ d_inverter
+* u53 net-_u45-pad3_ net-_u1-pad11_ net-_u28-pad1_ d_nand
+* u63 net-_u52-pad2_ net-_u63-pad2_ d_inverter
+* u52 net-_u41-pad2_ net-_u52-pad2_ d_inverter
+* u68 net-_u57-pad2_ net-_u58-pad2_ net-_u68-pad3_ d_or
+* u47 net-_u1-pad11_ net-_u43-pad3_ net-_u29-pad2_ d_nand
+* u79 net-_u75-pad2_ net-_u1-pad5_ d_inverter
+* u75 net-_u54-pad1_ net-_u75-pad2_ d_inverter
+* u74 net-_u62-pad1_ net-_u74-pad2_ d_inverter
+* u78 net-_u74-pad2_ net-_u1-pad6_ d_inverter
+* u70 net-_u66-pad3_ net-_u56-pad2_ net-_u62-pad1_ d_or
+a1 [net-_u23-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a2 net-_u1-pad4_ net-_u19-pad2_ u19
+a3 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u23-pad3_ u23
+a4 [net-_u10-pad2_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a5 [net-_u19-pad2_ net-_u15-pad3_ ] net-_u22-pad3_ u22
+a6 [net-_u26-pad1_ net-_u22-pad3_ ] net-_u26-pad3_ u26
+a7 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a8 net-_u1-pad1_ net-_u18-pad2_ u18
+a9 net-_u10-pad1_ net-_u10-pad2_ u10
+a10 net-_u27-pad2_ net-_u15-pad2_ u9
+a11 net-_u29-pad3_ net-_u37-pad2_ u37
+a12 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
+a13 net-_u1-pad13_ net-_u20-pad2_ u20
+a14 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u25-pad3_ u25
+a15 net-_u1-pad10_ net-_u21-pad2_ u21
+a16 [net-_u21-pad2_ net-_u17-pad3_ ] net-_u24-pad3_ u24
+a17 [net-_u28-pad1_ net-_u24-pad3_ ] net-_u28-pad3_ u28
+a18 net-_u1-pad13_ net-_u42-pad2_ u42
+a19 net-_u1-pad13_ net-_u35-pad2_ u35
+a20 net-_u28-pad3_ net-_u34-pad2_ u34
+a21 [net-_u34-pad2_ net-_u35-pad2_ ] net-_u43-pad3_ u43
+a22 net-_u42-pad2_ net-_u51-pad2_ u51
+a23 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u40-pad3_ u40
+a24 net-_u1-pad1_ net-_u31-pad2_ u31
+a25 net-_u1-pad1_ net-_u39-pad2_ u39
+a26 net-_u1-pad10_ net-_u41-pad2_ u41
+a27 net-_u1-pad10_ net-_u36-pad2_ u36
+a28 net-_u1-pad4_ net-_u32-pad2_ u32
+a29 net-_u38-pad2_ net-_u49-pad2_ u49
+a30 net-_u1-pad4_ net-_u38-pad2_ u38
+a31 net-_u26-pad3_ net-_u30-pad2_ u30
+a32 net-_u27-pad3_ net-_u33-pad2_ u33
+a33 [net-_u16-pad1_ net-_u11-pad1_ ] net-_u16-pad3_ u16
+a34 net-_u3-pad2_ net-_u11-pad1_ u7
+a35 [net-_u13-pad2_ net-_u12-pad2_ ] net-_u17-pad3_ u17
+a36 net-_u11-pad2_ net-_u13-pad2_ u13
+a37 net-_u11-pad1_ net-_u11-pad2_ u11
+a38 net-_u29-pad2_ net-_u12-pad2_ u12
+a39 net-_u1-pad12_ net-_u3-pad2_ u3
+a40 net-_u28-pad1_ net-_u16-pad1_ u6
+a41 net-_u26-pad1_ net-_u14-pad1_ u4
+a42 net-_u2-pad2_ net-_u14-pad2_ u5
+a43 net-_u1-pad2_ net-_u2-pad2_ u2
+a44 net-_u14-pad2_ net-_u10-pad1_ u8
+a45 [net-_u1-pad3_ net-_u40-pad3_ ] net-_u27-pad2_ u46
+a46 [net-_u32-pad2_ net-_u33-pad2_ ] net-_u44-pad3_ u44
+a47 net-_u39-pad2_ net-_u48-pad2_ u48
+a48 net-_u49-pad2_ net-_u60-pad2_ u60
+a49 [net-_u44-pad3_ net-_u1-pad3_ ] net-_u26-pad1_ u50
+a50 net-_u48-pad2_ net-_u56-pad2_ u56
+a51 net-_u27-pad2_ net-_u55-pad2_ u55
+a52 net-_u54-pad1_ net-_u54-pad2_ u54
+a53 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u67-pad3_ u67
+a54 net-_u62-pad1_ net-_u62-pad2_ u62
+a55 [net-_u54-pad2_ net-_u55-pad2_ ] net-_u66-pad3_ u66
+a56 [net-_u67-pad3_ net-_u62-pad2_ ] net-_u54-pad1_ u71
+a57 net-_u26-pad1_ net-_u61-pad2_ u61
+a58 net-_u76-pad2_ net-_u1-pad8_ u80
+a59 net-_u77-pad2_ net-_u1-pad9_ u81
+a60 net-_u51-pad2_ net-_u59-pad2_ u59
+a61 net-_u57-pad1_ net-_u77-pad2_ u77
+a62 [net-_u69-pad3_ net-_u65-pad2_ ] net-_u57-pad1_ u73
+a63 [net-_u68-pad3_ net-_u59-pad2_ ] net-_u65-pad1_ u72
+a64 net-_u65-pad1_ net-_u76-pad2_ u76
+a65 [net-_u63-pad2_ net-_u64-pad2_ ] net-_u69-pad3_ u69
+a66 net-_u29-pad2_ net-_u58-pad2_ u58
+a67 net-_u57-pad1_ net-_u57-pad2_ u57
+a68 [net-_u36-pad2_ net-_u37-pad2_ ] net-_u45-pad3_ u45
+a69 net-_u65-pad1_ net-_u65-pad2_ u65
+a70 net-_u28-pad1_ net-_u64-pad2_ u64
+a71 [net-_u45-pad3_ net-_u1-pad11_ ] net-_u28-pad1_ u53
+a72 net-_u52-pad2_ net-_u63-pad2_ u63
+a73 net-_u41-pad2_ net-_u52-pad2_ u52
+a74 [net-_u57-pad2_ net-_u58-pad2_ ] net-_u68-pad3_ u68
+a75 [net-_u1-pad11_ net-_u43-pad3_ ] net-_u29-pad2_ u47
+a76 net-_u75-pad2_ net-_u1-pad5_ u79
+a77 net-_u54-pad1_ net-_u75-pad2_ u75
+a78 net-_u62-pad1_ net-_u74-pad2_ u74
+a79 net-_u74-pad2_ net-_u1-pad6_ u78
+a80 [net-_u66-pad3_ net-_u56-pad2_ ] net-_u62-pad1_ u70
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u67 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u66 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u71 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u80 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u81 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u77 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u73 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u72 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u69 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u68 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u79 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u75 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u74 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u78 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u70 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.kicad_sch b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.kicad_sch
new file mode 100644
index 000000000..87981d8cc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.kicad_sch
@@ -0,0 +1,3785 @@
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+    )
+    (path "/7d661702-40fa-40a7-ab92-c0dbeebe1874"
+      (reference "U63") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/1bb08a56-6638-4d6f-a187-b9d474bb101a"
+      (reference "U64") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/74c7ddc7-d5d3-47b9-8db6-482dc497fbce"
+      (reference "U65") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/bbc7dbe2-243e-4d00-8936-54b00d05228a"
+      (reference "U66") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/2a1c4086-8c80-4ae0-b26d-418bd6d6755d"
+      (reference "U67") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/0b7d60c7-7537-4549-80eb-2b88bf8c8418"
+      (reference "U68") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/b7aebff5-65bf-4829-8602-dce79c14c56d"
+      (reference "U69") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/bd61fc6a-eecf-4c3b-a2bd-1a04327edb22"
+      (reference "U70") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/48c80a70-c2fd-4ba0-a017-fee8bdd11ba5"
+      (reference "U71") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/9e9f7d38-4e52-4ba8-bdd9-739771816a2d"
+      (reference "U72") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/a2235f9b-23cd-432c-8f11-5d899ac9a605"
+      (reference "U73") (unit 1) (value "d_or") (footprint "")
+    )
+    (path "/8db53618-43ed-45e5-9ba5-cb7a89f8a643"
+      (reference "U74") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6ebf2afc-2141-47ca-aa36-30cedeccd050"
+      (reference "U75") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/51106126-5af2-43ab-a7ec-eb3f4b313763"
+      (reference "U76") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/dc069dae-eb63-4ef3-b8e2-de6cc1ddc442"
+      (reference "U77") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/81064fd3-2081-4aa3-8a38-0c989665ef43"
+      (reference "U78") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/3f31db3a-0a3e-4485-8aa3-01948eadb705"
+      (reference "U79") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/dedf7ec9-753c-476d-8c97-3bff6d336494"
+      (reference "U80") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/73ba7ed3-8af1-4cda-a835-84d4bb258a92"
+      (reference "U81") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.sub b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.sub
new file mode 100644
index 000000000..51f80151e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A.sub
@@ -0,0 +1,326 @@
+* Subcircuit 74HC74A
+.subckt 74HC74A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u27 net-_u23-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nand
+* u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter
+* u23 net-_u14-pad3_ net-_u18-pad2_ net-_u23-pad3_ d_nand
+* u15 net-_u10-pad2_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u22 net-_u19-pad2_ net-_u15-pad3_ net-_u22-pad3_ d_nand
+* u26 net-_u26-pad1_ net-_u22-pad3_ net-_u26-pad3_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u9 net-_u27-pad2_ net-_u15-pad2_ d_inverter
+* u37 net-_u29-pad3_ net-_u37-pad2_ d_inverter
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_nand
+* u20 net-_u1-pad13_ net-_u20-pad2_ d_inverter
+* u25 net-_u16-pad3_ net-_u20-pad2_ net-_u25-pad3_ d_nand
+* u21 net-_u1-pad10_ net-_u21-pad2_ d_inverter
+* u24 net-_u21-pad2_ net-_u17-pad3_ net-_u24-pad3_ d_nand
+* u28 net-_u28-pad1_ net-_u24-pad3_ net-_u28-pad3_ d_nand
+* u42 net-_u1-pad13_ net-_u42-pad2_ d_inverter
+* u35 net-_u1-pad13_ net-_u35-pad2_ d_inverter
+* u34 net-_u28-pad3_ net-_u34-pad2_ d_inverter
+* u43 net-_u34-pad2_ net-_u35-pad2_ net-_u43-pad3_ d_or
+* u51 net-_u42-pad2_ net-_u51-pad2_ d_inverter
+* u40 net-_u30-pad2_ net-_u31-pad2_ net-_u40-pad3_ d_or
+* u31 net-_u1-pad1_ net-_u31-pad2_ d_inverter
+* u39 net-_u1-pad1_ net-_u39-pad2_ d_inverter
+* u41 net-_u1-pad10_ net-_u41-pad2_ d_inverter
+* u36 net-_u1-pad10_ net-_u36-pad2_ d_inverter
+* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter
+* u49 net-_u38-pad2_ net-_u49-pad2_ d_inverter
+* u38 net-_u1-pad4_ net-_u38-pad2_ d_inverter
+* u30 net-_u26-pad3_ net-_u30-pad2_ d_inverter
+* u33 net-_u27-pad3_ net-_u33-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u11-pad1_ net-_u16-pad3_ d_or
+* u7 net-_u3-pad2_ net-_u11-pad1_ d_inverter
+* u17 net-_u13-pad2_ net-_u12-pad2_ net-_u17-pad3_ d_or
+* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u29-pad2_ net-_u12-pad2_ d_inverter
+* u3 net-_u1-pad12_ net-_u3-pad2_ d_inverter
+* u6 net-_u28-pad1_ net-_u16-pad1_ d_inverter
+* u4 net-_u26-pad1_ net-_u14-pad1_ d_inverter
+* u5 net-_u2-pad2_ net-_u14-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u8 net-_u14-pad2_ net-_u10-pad1_ d_inverter
+* u46 net-_u1-pad3_ net-_u40-pad3_ net-_u27-pad2_ d_nand
+* u44 net-_u32-pad2_ net-_u33-pad2_ net-_u44-pad3_ d_or
+* u48 net-_u39-pad2_ net-_u48-pad2_ d_inverter
+* u60 net-_u49-pad2_ net-_u60-pad2_ d_inverter
+* u50 net-_u44-pad3_ net-_u1-pad3_ net-_u26-pad1_ d_nand
+* u56 net-_u48-pad2_ net-_u56-pad2_ d_inverter
+* u55 net-_u27-pad2_ net-_u55-pad2_ d_inverter
+* u54 net-_u54-pad1_ net-_u54-pad2_ d_inverter
+* u67 net-_u60-pad2_ net-_u61-pad2_ net-_u67-pad3_ d_or
+* u62 net-_u62-pad1_ net-_u62-pad2_ d_inverter
+* u66 net-_u54-pad2_ net-_u55-pad2_ net-_u66-pad3_ d_or
+* u71 net-_u67-pad3_ net-_u62-pad2_ net-_u54-pad1_ d_or
+* u61 net-_u26-pad1_ net-_u61-pad2_ d_inverter
+* u80 net-_u76-pad2_ net-_u1-pad8_ d_inverter
+* u81 net-_u77-pad2_ net-_u1-pad9_ d_inverter
+* u59 net-_u51-pad2_ net-_u59-pad2_ d_inverter
+* u77 net-_u57-pad1_ net-_u77-pad2_ d_inverter
+* u73 net-_u69-pad3_ net-_u65-pad2_ net-_u57-pad1_ d_or
+* u72 net-_u68-pad3_ net-_u59-pad2_ net-_u65-pad1_ d_or
+* u76 net-_u65-pad1_ net-_u76-pad2_ d_inverter
+* u69 net-_u63-pad2_ net-_u64-pad2_ net-_u69-pad3_ d_or
+* u58 net-_u29-pad2_ net-_u58-pad2_ d_inverter
+* u57 net-_u57-pad1_ net-_u57-pad2_ d_inverter
+* u45 net-_u36-pad2_ net-_u37-pad2_ net-_u45-pad3_ d_or
+* u65 net-_u65-pad1_ net-_u65-pad2_ d_inverter
+* u64 net-_u28-pad1_ net-_u64-pad2_ d_inverter
+* u53 net-_u45-pad3_ net-_u1-pad11_ net-_u28-pad1_ d_nand
+* u63 net-_u52-pad2_ net-_u63-pad2_ d_inverter
+* u52 net-_u41-pad2_ net-_u52-pad2_ d_inverter
+* u68 net-_u57-pad2_ net-_u58-pad2_ net-_u68-pad3_ d_or
+* u47 net-_u1-pad11_ net-_u43-pad3_ net-_u29-pad2_ d_nand
+* u79 net-_u75-pad2_ net-_u1-pad5_ d_inverter
+* u75 net-_u54-pad1_ net-_u75-pad2_ d_inverter
+* u74 net-_u62-pad1_ net-_u74-pad2_ d_inverter
+* u78 net-_u74-pad2_ net-_u1-pad6_ d_inverter
+* u70 net-_u66-pad3_ net-_u56-pad2_ net-_u62-pad1_ d_or
+a1 [net-_u23-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a2 net-_u1-pad4_ net-_u19-pad2_ u19
+a3 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u23-pad3_ u23
+a4 [net-_u10-pad2_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a5 [net-_u19-pad2_ net-_u15-pad3_ ] net-_u22-pad3_ u22
+a6 [net-_u26-pad1_ net-_u22-pad3_ ] net-_u26-pad3_ u26
+a7 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a8 net-_u1-pad1_ net-_u18-pad2_ u18
+a9 net-_u10-pad1_ net-_u10-pad2_ u10
+a10 net-_u27-pad2_ net-_u15-pad2_ u9
+a11 net-_u29-pad3_ net-_u37-pad2_ u37
+a12 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
+a13 net-_u1-pad13_ net-_u20-pad2_ u20
+a14 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u25-pad3_ u25
+a15 net-_u1-pad10_ net-_u21-pad2_ u21
+a16 [net-_u21-pad2_ net-_u17-pad3_ ] net-_u24-pad3_ u24
+a17 [net-_u28-pad1_ net-_u24-pad3_ ] net-_u28-pad3_ u28
+a18 net-_u1-pad13_ net-_u42-pad2_ u42
+a19 net-_u1-pad13_ net-_u35-pad2_ u35
+a20 net-_u28-pad3_ net-_u34-pad2_ u34
+a21 [net-_u34-pad2_ net-_u35-pad2_ ] net-_u43-pad3_ u43
+a22 net-_u42-pad2_ net-_u51-pad2_ u51
+a23 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u40-pad3_ u40
+a24 net-_u1-pad1_ net-_u31-pad2_ u31
+a25 net-_u1-pad1_ net-_u39-pad2_ u39
+a26 net-_u1-pad10_ net-_u41-pad2_ u41
+a27 net-_u1-pad10_ net-_u36-pad2_ u36
+a28 net-_u1-pad4_ net-_u32-pad2_ u32
+a29 net-_u38-pad2_ net-_u49-pad2_ u49
+a30 net-_u1-pad4_ net-_u38-pad2_ u38
+a31 net-_u26-pad3_ net-_u30-pad2_ u30
+a32 net-_u27-pad3_ net-_u33-pad2_ u33
+a33 [net-_u16-pad1_ net-_u11-pad1_ ] net-_u16-pad3_ u16
+a34 net-_u3-pad2_ net-_u11-pad1_ u7
+a35 [net-_u13-pad2_ net-_u12-pad2_ ] net-_u17-pad3_ u17
+a36 net-_u11-pad2_ net-_u13-pad2_ u13
+a37 net-_u11-pad1_ net-_u11-pad2_ u11
+a38 net-_u29-pad2_ net-_u12-pad2_ u12
+a39 net-_u1-pad12_ net-_u3-pad2_ u3
+a40 net-_u28-pad1_ net-_u16-pad1_ u6
+a41 net-_u26-pad1_ net-_u14-pad1_ u4
+a42 net-_u2-pad2_ net-_u14-pad2_ u5
+a43 net-_u1-pad2_ net-_u2-pad2_ u2
+a44 net-_u14-pad2_ net-_u10-pad1_ u8
+a45 [net-_u1-pad3_ net-_u40-pad3_ ] net-_u27-pad2_ u46
+a46 [net-_u32-pad2_ net-_u33-pad2_ ] net-_u44-pad3_ u44
+a47 net-_u39-pad2_ net-_u48-pad2_ u48
+a48 net-_u49-pad2_ net-_u60-pad2_ u60
+a49 [net-_u44-pad3_ net-_u1-pad3_ ] net-_u26-pad1_ u50
+a50 net-_u48-pad2_ net-_u56-pad2_ u56
+a51 net-_u27-pad2_ net-_u55-pad2_ u55
+a52 net-_u54-pad1_ net-_u54-pad2_ u54
+a53 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u67-pad3_ u67
+a54 net-_u62-pad1_ net-_u62-pad2_ u62
+a55 [net-_u54-pad2_ net-_u55-pad2_ ] net-_u66-pad3_ u66
+a56 [net-_u67-pad3_ net-_u62-pad2_ ] net-_u54-pad1_ u71
+a57 net-_u26-pad1_ net-_u61-pad2_ u61
+a58 net-_u76-pad2_ net-_u1-pad8_ u80
+a59 net-_u77-pad2_ net-_u1-pad9_ u81
+a60 net-_u51-pad2_ net-_u59-pad2_ u59
+a61 net-_u57-pad1_ net-_u77-pad2_ u77
+a62 [net-_u69-pad3_ net-_u65-pad2_ ] net-_u57-pad1_ u73
+a63 [net-_u68-pad3_ net-_u59-pad2_ ] net-_u65-pad1_ u72
+a64 net-_u65-pad1_ net-_u76-pad2_ u76
+a65 [net-_u63-pad2_ net-_u64-pad2_ ] net-_u69-pad3_ u69
+a66 net-_u29-pad2_ net-_u58-pad2_ u58
+a67 net-_u57-pad1_ net-_u57-pad2_ u57
+a68 [net-_u36-pad2_ net-_u37-pad2_ ] net-_u45-pad3_ u45
+a69 net-_u65-pad1_ net-_u65-pad2_ u65
+a70 net-_u28-pad1_ net-_u64-pad2_ u64
+a71 [net-_u45-pad3_ net-_u1-pad11_ ] net-_u28-pad1_ u53
+a72 net-_u52-pad2_ net-_u63-pad2_ u63
+a73 net-_u41-pad2_ net-_u52-pad2_ u52
+a74 [net-_u57-pad2_ net-_u58-pad2_ ] net-_u68-pad3_ u68
+a75 [net-_u1-pad11_ net-_u43-pad3_ ] net-_u29-pad2_ u47
+a76 net-_u75-pad2_ net-_u1-pad5_ u79
+a77 net-_u54-pad1_ net-_u75-pad2_ u75
+a78 net-_u62-pad1_ net-_u74-pad2_ u74
+a79 net-_u74-pad2_ net-_u1-pad6_ u78
+a80 [net-_u66-pad3_ net-_u56-pad2_ ] net-_u62-pad1_ u70
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u67 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u66 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u71 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u80 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u81 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u77 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u73 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u72 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u76 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u69 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u68 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u79 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u75 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u74 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u78 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u70 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC74A
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_Previous_Values.xml
new file mode 100644
index 000000000..40bce30b6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u27 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u27><u19 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u23><u15 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u15><u22 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u26><u14 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u10 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u9><u37 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u37><u29 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u29><u20 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u20><u25 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u25><u21 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u21><u24 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u24><u28 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u28><u42 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u42><u35 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u35><u34 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u34><u43 name="type">d_or<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u43><u51 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u51><u40 name="type">d_or<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u40><u31 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u31><u39 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u39><u41 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u41><u36 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u36><u32 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u32><u49 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u49><u38 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u38><u30 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u30><u33 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u33><u16 name="type">d_or<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u16><u7 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u7><u17 name="type">d_or<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u12><u3 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u3><u6 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u2><u8 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u8><u46 name="type">d_nand<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u46><u44 name="type">d_or<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u44><u48 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u48><u60 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u60><u50 name="type">d_nand<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u50><u56 name="type">d_inverter<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u56><u55 name="type">d_inverter<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u55><u54 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u54><u67 name="type">d_or<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u67><u62 name="type">d_inverter<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u62><u66 name="type">d_or<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u66><u71 name="type">d_or<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u71><u61 name="type">d_inverter<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u61><u80 name="type">d_inverter<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u80><u81 name="type">d_inverter<field175 name="Enter Rise Delay (default=1.0e-9)" /><field176 name="Enter Fall Delay (default=1.0e-9)" /><field177 name="Enter Input Load (default=1.0e-12)" /></u81><u59 name="type">d_inverter<field178 name="Enter Rise Delay (default=1.0e-9)" /><field179 name="Enter Fall Delay (default=1.0e-9)" /><field180 name="Enter Input Load (default=1.0e-12)" /></u59><u77 name="type">d_inverter<field181 name="Enter Rise Delay (default=1.0e-9)" /><field182 name="Enter Fall Delay (default=1.0e-9)" /><field183 name="Enter Input Load (default=1.0e-12)" /></u77><u73 name="type">d_or<field184 name="Enter Rise Delay (default=1.0e-9)" /><field185 name="Enter Fall Delay (default=1.0e-9)" /><field186 name="Enter Input Load (default=1.0e-12)" /></u73><u72 name="type">d_or<field187 name="Enter Rise Delay (default=1.0e-9)" /><field188 name="Enter Fall Delay (default=1.0e-9)" /><field189 name="Enter Input Load (default=1.0e-12)" /></u72><u76 name="type">d_inverter<field190 name="Enter Rise Delay (default=1.0e-9)" /><field191 name="Enter Fall Delay (default=1.0e-9)" /><field192 name="Enter Input Load (default=1.0e-12)" /></u76><u69 name="type">d_or<field193 name="Enter Rise Delay (default=1.0e-9)" /><field194 name="Enter Fall Delay (default=1.0e-9)" /><field195 name="Enter Input Load (default=1.0e-12)" /></u69><u58 name="type">d_inverter<field196 name="Enter Rise Delay (default=1.0e-9)" /><field197 name="Enter Fall Delay (default=1.0e-9)" /><field198 name="Enter Input Load (default=1.0e-12)" /></u58><u57 name="type">d_inverter<field199 name="Enter Rise Delay (default=1.0e-9)" /><field200 name="Enter Fall Delay (default=1.0e-9)" /><field201 name="Enter Input Load (default=1.0e-12)" /></u57><u45 name="type">d_or<field202 name="Enter Rise Delay (default=1.0e-9)" /><field203 name="Enter Fall Delay (default=1.0e-9)" /><field204 name="Enter Input Load (default=1.0e-12)" /></u45><u65 name="type">d_inverter<field205 name="Enter Rise Delay (default=1.0e-9)" /><field206 name="Enter Fall Delay (default=1.0e-9)" /><field207 name="Enter Input Load (default=1.0e-12)" /></u65><u64 name="type">d_inverter<field208 name="Enter Rise Delay (default=1.0e-9)" /><field209 name="Enter Fall Delay (default=1.0e-9)" /><field210 name="Enter Input Load (default=1.0e-12)" /></u64><u53 name="type">d_nand<field211 name="Enter Rise Delay (default=1.0e-9)" /><field212 name="Enter Fall Delay (default=1.0e-9)" /><field213 name="Enter Input Load (default=1.0e-12)" /></u53><u63 name="type">d_inverter<field214 name="Enter Rise Delay (default=1.0e-9)" /><field215 name="Enter Fall Delay (default=1.0e-9)" /><field216 name="Enter Input Load (default=1.0e-12)" /></u63><u52 name="type">d_inverter<field217 name="Enter Rise Delay (default=1.0e-9)" /><field218 name="Enter Fall Delay (default=1.0e-9)" /><field219 name="Enter Input Load (default=1.0e-12)" /></u52><u68 name="type">d_or<field220 name="Enter Rise Delay (default=1.0e-9)" /><field221 name="Enter Fall Delay (default=1.0e-9)" /><field222 name="Enter Input Load (default=1.0e-12)" /></u68><u47 name="type">d_nand<field223 name="Enter Rise Delay (default=1.0e-9)" /><field224 name="Enter Fall Delay (default=1.0e-9)" /><field225 name="Enter Input Load (default=1.0e-12)" /></u47><u79 name="type">d_inverter<field226 name="Enter Rise Delay (default=1.0e-9)" /><field227 name="Enter Fall Delay (default=1.0e-9)" /><field228 name="Enter Input Load (default=1.0e-12)" /></u79><u75 name="type">d_inverter<field229 name="Enter Rise Delay (default=1.0e-9)" /><field230 name="Enter Fall Delay (default=1.0e-9)" /><field231 name="Enter Input Load (default=1.0e-12)" /></u75><u74 name="type">d_inverter<field232 name="Enter Rise Delay (default=1.0e-9)" /><field233 name="Enter Fall Delay (default=1.0e-9)" /><field234 name="Enter Input Load (default=1.0e-12)" /></u74><u78 name="type">d_inverter<field235 name="Enter Rise Delay (default=1.0e-9)" /><field236 name="Enter Fall Delay (default=1.0e-9)" /><field237 name="Enter Input Load (default=1.0e-12)" /></u78><u70 name="type">d_or<field238 name="Enter Rise Delay (default=1.0e-9)" /><field239 name="Enter Fall Delay (default=1.0e-9)" /><field240 name="Enter Input Load (default=1.0e-12)" /></u70></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.cir b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.cir
new file mode 100644
index 000000000..6c9340f7e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.cir
@@ -0,0 +1,22 @@
+.title KiCad schematic
+U6 Net-_V_RESET2-Pad1_ Net-_V_DATA2-Pad1_ V_CLK2 Net-_V_SET2-Pad1_ Net-_U6-Pad5_ Net-_U6-Pad6_ Net-_U6-Pad7_ Net-_U6-Pad8_ adc_bridge_4
+U5 Net-_U5-Pad1_ Net-_U5-Pad2_ V_Q2 V_Q2n dac_bridge_2
+U8 V_Q2 plot_v1
+U7 V_Q2n plot_v1
+U10 V_CLK2 plot_v1
+U1 V_Q1 plot_v1
+U3 Net-_V_RESET1-Pad1_ Net-_V_DATA1-Pad1_ V_CLK1 Net-_V_SET1-Pad1_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ V_Q1 V_Q1n dac_bridge_2
+V_RESET1 Net-_V_RESET1-Pad1_ GND DC
+U2 V_Q1n plot_v1
+X1 Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U4-Pad1_ Net-_U4-Pad2_ GND Net-_U5-Pad2_ Net-_U5-Pad1_ Net-_U6-Pad8_ Net-_U6-Pad7_ Net-_U6-Pad6_ Net-_U6-Pad5_ Net-_X1-Pad14_ 74HC74A
+v1 Net-_X1-Pad14_ GND 5
+V_RESET2 Net-_V_RESET2-Pad1_ GND DC
+V_DATA2 Net-_V_DATA2-Pad1_ GND DC
+V_SET2 Net-_V_SET2-Pad1_ GND DC
+V_CLK2 V_CLK2 GND pulse
+V_SET1 Net-_V_SET1-Pad1_ GND DC
+V_DATA1 Net-_V_DATA1-Pad1_ GND DC
+U9 V_CLK1 plot_v1
+V_CLK1 V_CLK1 GND pulse
+.end
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.cir.out b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.cir.out
new file mode 100644
index 000000000..32171e13d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.cir.out
@@ -0,0 +1,50 @@
+.title kicad schematic
+
+.include 74HC74A.sub
+* u6 net-_v_reset2-pad1_ net-_v_data2-pad1_ v_clk2 net-_v_set2-pad1_ net-_u6-pad5_ net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ adc_bridge_4
+* u5 net-_u5-pad1_ net-_u5-pad2_ v_q2 v_q2n dac_bridge_2
+* u8 v_q2 plot_v1
+* u7 v_q2n plot_v1
+* u10 v_clk2 plot_v1
+* u1 v_q1 plot_v1
+* u3 net-_v_reset1-pad1_ net-_v_data1-pad1_ v_clk1 net-_v_set1-pad1_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
+* u4 net-_u4-pad1_ net-_u4-pad2_ v_q1 v_q1n dac_bridge_2
+v_reset1 net-_v_reset1-pad1_ gnd  dc 5
+* u2 v_q1n plot_v1
+x1 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u4-pad1_ net-_u4-pad2_ gnd net-_u5-pad2_ net-_u5-pad1_ net-_u6-pad8_ net-_u6-pad7_ net-_u6-pad6_ net-_u6-pad5_ net-_x1-pad14_ 74HC74A
+v1 net-_x1-pad14_ gnd 5
+v_reset2 net-_v_reset2-pad1_ gnd  dc 5
+v_data2 net-_v_data2-pad1_ gnd  dc 5
+v_set2 net-_v_set2-pad1_ gnd  dc 5
+v_clk2 v_clk2 gnd pulse(0 5 0 1n 1n 5 10)
+v_set1 net-_v_set1-pad1_ gnd  dc 5
+v_data1 net-_v_data1-pad1_ gnd  dc 5
+* u9 v_clk1 plot_v1
+v_clk1 v_clk1 gnd pulse(0 5 0 1n 1n 5 10)
+a1 [net-_v_reset2-pad1_ net-_v_data2-pad1_ v_clk2 net-_v_set2-pad1_ ] [net-_u6-pad5_ net-_u6-pad6_ net-_u6-pad7_ net-_u6-pad8_ ] u6
+a2 [net-_u5-pad1_ net-_u5-pad2_ ] [v_q2 v_q2n ] u5
+a3 [net-_v_reset1-pad1_ net-_v_data1-pad1_ v_clk1 net-_v_set1-pad1_ ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
+a4 [net-_u4-pad1_ net-_u4-pad2_ ] [v_q1 v_q1n ] u4
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_2, Ngspice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_2, Ngspice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 1e-00 50e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_q2)
+plot v(v_q2n)
+plot v(v_clk2)
+plot v(v_q1)
+plot v(v_q1n)
+plot v(v_clk1)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.kicad_sch b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.kicad_sch
new file mode 100644
index 000000000..10f85cee7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.kicad_sch
@@ -0,0 +1,1218 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.proj b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.proj
new file mode 100644
index 000000000..07de6d6f1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.proj
@@ -0,0 +1 @@
+schematicFile 74HC74A_TEST_CIRCUIT.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.raw b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.raw
new file mode 100644
index 000000000..46e207868
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT.raw
@@ -0,0 +1,7 @@
+Title: kicad schematic
+Date: Fri Dec 19 14:57:28  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 27
+No. Points: 0       
+Variables:
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT_Previous_Values.xml
new file mode 100644
index 000000000..3f3fb3dd4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/74HC74A_TEST_CIRCUIT_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v_reset1 name="Source type">dc<field1 name="Value">5</field1></v_reset1><v1 name="Source type">5</v1><v_reset2 name="Source type">dc<field1 name="Value">5</field1></v_reset2><v_data2 name="Source type">dc<field1 name="Value">5</field1></v_data2><v_set2 name="Source type">dc<field1 name="Value">5</field1></v_set2><v_clk2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">5</field5><field5 name="Period">10</field5></v_clk2><v_set1 name="Source type">dc<field1 name="Value">5</field1></v_set1><v_data1 name="Source type">dc<field1 name="Value">5</field1></v_data1><v_clk1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">5</field5><field5 name="Period">10</field5></v_clk1></source><model><u6 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u6><u5 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u5><u3 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">dac_bridge<field15 name="Enter value for out_low (default=0.0)" /><field16 name="Enter value for out_high (default=5.0)" /><field17 name="Enter value for out_undef (default=0.5)" /><field18 name="Enter value for input load (default=1.0e-12)" /><field19 name="Enter the Rise Time (default=1.0e-9)" /><field20 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC74A</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">50</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/_autosave-74HC74A.sch b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/_autosave-74HC74A.sch
new file mode 100644
index 000000000..3ee4012e1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/_autosave-74HC74A.sch
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+L eSim_Power:eSim_GND #PWR?
+U 1 1 00000000
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+F 0 "#PWR?" H 21300 7950 50  0001 C CNN
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+F 2 "" H 21300 8200 50  0001 C CNN
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+	1    21300 8200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Power:eSim_GND #PWR?
+U 1 1 00000000
+P 21350 7525
+F 0 "#PWR?" H 21350 7275 50  0001 C CNN
+F 1 "eSim_GND" H 21350 7350 50  0000 C CNN
+F 2 "" H 21350 7525 50  0001 C CNN
+F 3 "" H 21350 7525 50  0001 C CNN
+	1    21350 7525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 4 1 00000000
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+F 2 "" H 2975 2125 60  0000 C CNN
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+	4    2975 2125
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 2 1 00000000
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+F 2 "" H 3075 4125 60  0000 C CNN
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 1 1 00000000
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+	1    3100 7100
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 10 1 00000000
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+$EndComp
+$Comp
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+U 12 1 00000000
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+$EndComp
+$Comp
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+U 13 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 3 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 11 1 00000000
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+F 2 "" H 12425 11600 60  0000 C CNN
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 7 1 00000000
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+$EndComp
+$Comp
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+U 14 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 5 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 6 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 9 1 00000000
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 8 1 00000000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+	1    5700 11000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 5850 4625 60  0000 C CNN
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+	1    5800 4675
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 6125 6125 60  0000 C CNN
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+F 2 "" H 6175 5825 60  0000 C CNN
+F 3 "" H 6175 5825 60  0000 C CNN
+	1    6125 5875
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 6200 5325 60  0000 C CNN
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+	1    6150 5375
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" V 6150 11475 60  0000 R CNN
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+F 2 "" H 6250 11500 60  0000 C CNN
+F 3 "" H 6250 11500 60  0000 C CNN
+	1    6200 11550
+	0    -1   1    0   
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 6575 12700 60  0000 C CNN
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+	1    6525 12750
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 6550 12500 60  0000 C CNN
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+F 2 "" H 6600 12200 60  0000 C CNN
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+	1    6550 12250
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 7850 4100 60  0000 C CNN
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+	1    7800 4150
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 7875 5075 60  0000 C CNN
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+	1    7825 5125
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 8250 10975 60  0000 C CNN
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+	1    8200 11025
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 8275 11950 60  0000 C CNN
+F 3 "" H 8275 11950 60  0000 C CNN
+	1    8225 12000
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 10875 5450 60  0000 C CNN
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+	1    10825 5500
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 10825 6325 60  0000 C CNN
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+F 2 "" H 10875 6000 60  0000 C CNN
+F 3 "" H 10875 6000 60  0000 C CNN
+	1    10825 6050
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 11200 3125 60  0000 C CNN
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+F 2 "" H 11250 2825 60  0000 C CNN
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 2 "" H 11250 3525 60  0000 C CNN
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+	1    11200 3575
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 11225 12650 60  0000 C CNN
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+F 2 "" H 11275 12325 60  0000 C CNN
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+	1    11225 12375
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 11225 13200 60  0000 C CNN
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+F 2 "" H 11275 12875 60  0000 C CNN
+F 3 "" H 11275 12875 60  0000 C CNN
+	1    11225 12925
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 11600 10000 60  0000 C CNN
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+F 2 "" H 11650 9700 60  0000 C CNN
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+	1    11600 9750
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 11600 10700 60  0000 C CNN
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+F 2 "" H 11650 10400 60  0000 C CNN
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+	1    11600 10450
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+$EndComp
+$Comp
+L eSim_Digital:d_inverter U?
+U 1 1 00000000
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+F 0 "U?" H 11675 2400 60  0000 C CNN
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+F 2 "" H 11725 2075 60  0000 C CNN
+F 3 "" H 11725 2075 60  0000 C CNN
+	1    11675 2125
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+$EndComp
+$Comp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+F 2 "" H 14150 13925 60  0000 C CNN
+F 3 "" H 14150 13925 60  0000 C CNN
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+$EndComp
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+F 1 "d_inverter" H 14125 9125 60  0000 C CNN
+F 2 "" H 14175 8950 60  0000 C CNN
+F 3 "" H 14175 8950 60  0000 C CNN
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+$EndComp
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+F 1 "d_inverter" H 14550 5275 60  0000 C CNN
+F 2 "" H 14600 5100 60  0000 C CNN
+F 3 "" H 14600 5100 60  0000 C CNN
+	1    14550 5150
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+$EndComp
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+F 0 "U?" H 14550 5950 60  0000 C CNN
+F 1 "d_inverter" H 14550 5800 60  0000 C CNN
+F 2 "" H 14600 5650 60  0000 C CNN
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+	1    14550 5700
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+F 2 "" H 14625 6200 60  0000 C CNN
+F 3 "" H 14625 6200 60  0000 C CNN
+	1    14575 6250
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+$EndComp
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+F 1 "d_inverter" H 14950 12150 60  0000 C CNN
+F 2 "" H 15000 11975 60  0000 C CNN
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+$EndComp
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+F 2 "" H 15000 12525 60  0000 C CNN
+F 3 "" H 15000 12525 60  0000 C CNN
+	1    14950 12575
+	1    0    0    -1  
+$EndComp
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+F 0 "U?" H 14975 13400 60  0000 C CNN
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+F 2 "" H 15025 13075 60  0000 C CNN
+F 3 "" H 15025 13075 60  0000 C CNN
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+F 2 "" H 15275 2625 60  0000 C CNN
+F 3 "" H 15275 2625 60  0000 C CNN
+	1    15225 2675
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+$EndComp
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+F 2 "" H 15275 3200 60  0000 C CNN
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+	1    15225 3250
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+F 2 "" H 15300 3800 60  0000 C CNN
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+$EndComp
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+F 0 "U?" H 15625 9800 60  0000 C CNN
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+F 2 "" H 15675 9500 60  0000 C CNN
+F 3 "" H 15675 9500 60  0000 C CNN
+	1    15625 9550
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+$EndComp
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+F 0 "U?" H 15625 10400 60  0000 C CNN
+F 1 "d_inverter" H 15625 10250 60  0000 C CNN
+F 2 "" H 15675 10075 60  0000 C CNN
+F 3 "" H 15675 10075 60  0000 C CNN
+	1    15625 10125
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 15650 11000 60  0000 C CNN
+F 1 "d_inverter" H 15650 10850 60  0000 C CNN
+F 2 "" H 15700 10675 60  0000 C CNN
+F 3 "" H 15700 10675 60  0000 C CNN
+	1    15650 10725
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 18550 6100 60  0000 C CNN
+F 1 "d_inverter" H 18550 5950 60  0000 C CNN
+F 2 "" H 18600 5800 60  0000 C CNN
+F 3 "" H 18600 5800 60  0000 C CNN
+	1    18550 5850
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 18850 3725 60  0000 C CNN
+F 1 "d_inverter" H 18850 3575 60  0000 C CNN
+F 2 "" H 18900 3425 60  0000 C CNN
+F 3 "" H 18900 3425 60  0000 C CNN
+	1    18850 3475
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 18950 12975 60  0000 C CNN
+F 1 "d_inverter" H 18950 12825 60  0000 C CNN
+F 2 "" H 19000 12675 60  0000 C CNN
+F 3 "" H 19000 12675 60  0000 C CNN
+	1    18950 12725
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 19250 10600 60  0000 C CNN
+F 1 "d_inverter" H 19250 10450 60  0000 C CNN
+F 2 "" H 19300 10300 60  0000 C CNN
+F 3 "" H 19300 10300 60  0000 C CNN
+	1    19250 10350
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 19650 6100 60  0000 C CNN
+F 1 "d_inverter" H 19650 5950 60  0000 C CNN
+F 2 "" H 19700 5800 60  0000 C CNN
+F 3 "" H 19700 5800 60  0000 C CNN
+	1    19650 5850
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 19900 3725 60  0000 C CNN
+F 1 "d_inverter" H 19900 3575 60  0000 C CNN
+F 2 "" H 19950 3425 60  0000 C CNN
+F 3 "" H 19950 3425 60  0000 C CNN
+	1    19900 3475
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 20050 12975 60  0000 C CNN
+F 1 "d_inverter" H 20050 12825 60  0000 C CNN
+F 2 "" H 20100 12675 60  0000 C CNN
+F 3 "" H 20100 12675 60  0000 C CNN
+	1    20050 12725
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 20300 10600 60  0000 C CNN
+F 1 "d_inverter" H 20300 10450 60  0000 C CNN
+F 2 "" H 20350 10300 60  0000 C CNN
+F 3 "" H 20350 10300 60  0000 C CNN
+	1    20300 10350
+	1    0    0    -1  
+$EndComp
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+F 0 "U?" H 6775 4125 60  0000 C CNN
+F 1 "d_or" H 6775 3975 60  0000 C CNN
+F 2 "" H 6775 3750 60  0000 C CNN
+F 3 "" H 6775 3750 60  0000 C CNN
+	1    6775 3750
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 1 "d_or" H 7150 5875 60  0000 C CNN
+F 2 "" H 7150 5650 60  0000 C CNN
+F 3 "" H 7150 5650 60  0000 C CNN
+	1    7150 5650
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+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 7175 11000 60  0000 C CNN
+F 1 "d_or" H 7175 10850 60  0000 C CNN
+F 2 "" H 7175 10625 60  0000 C CNN
+F 3 "" H 7175 10625 60  0000 C CNN
+	1    7175 10625
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 00000000
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+F 0 "U?" H 7550 12900 60  0000 C CNN
+F 1 "d_or" H 7550 12750 60  0000 C CNN
+F 2 "" H 7550 12525 60  0000 C CNN
+F 3 "" H 7550 12525 60  0000 C CNN
+	1    7550 12525
+	1    0    0    -1  
+$EndComp
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+U 1 1 00000000
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+F 0 "U?" H 8450 5975 60  0000 C CNN
+F 1 "d_nand" H 8450 5825 60  0000 C CNN
+F 2 "" H 8450 5600 60  0000 C CNN
+F 3 "" H 8450 5600 60  0000 C CNN
+	1    8450 5600
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 00000000
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+F 0 "U?" H 8500 4175 60  0000 C CNN
+F 1 "d_nand" H 8500 4025 60  0000 C CNN
+F 2 "" H 8500 3800 60  0000 C CNN
+F 3 "" H 8500 3800 60  0000 C CNN
+	1    8500 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
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+F 0 "U?" H 8850 12850 60  0000 C CNN
+F 1 "d_nand" H 8850 12700 60  0000 C CNN
+F 2 "" H 8850 12475 60  0000 C CNN
+F 3 "" H 8850 12475 60  0000 C CNN
+	1    8850 12475
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
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+F 0 "U?" H 8900 11050 60  0000 C CNN
+F 1 "d_nand" H 8900 10900 60  0000 C CNN
+F 2 "" H 8900 10675 60  0000 C CNN
+F 3 "" H 8900 10675 60  0000 C CNN
+	1    8900 10675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
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+F 0 "U?" H 9725 5925 60  0000 C CNN
+F 1 "d_nand" H 9725 5775 60  0000 C CNN
+F 2 "" H 9725 5550 60  0000 C CNN
+F 3 "" H 9725 5550 60  0000 C CNN
+	1    9725 5550
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+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
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+F 0 "U?" H 10125 4200 60  0000 C CNN
+F 1 "d_nand" H 10125 4050 60  0000 C CNN
+F 2 "" H 10125 3850 60  0000 C CNN
+F 3 "" H 10125 3850 60  0000 C CNN
+	1    10125 3850
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 00000000
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+F 0 "U?" H 10125 12800 60  0000 C CNN
+F 1 "d_nand" H 10125 12650 60  0000 C CNN
+F 2 "" H 10125 12425 60  0000 C CNN
+F 3 "" H 10125 12425 60  0000 C CNN
+	1    10125 12425
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+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
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+F 0 "U?" H 10525 11075 60  0000 C CNN
+F 1 "d_nand" H 10525 10925 60  0000 C CNN
+F 2 "" H 10525 10725 60  0000 C CNN
+F 3 "" H 10525 10725 60  0000 C CNN
+	1    10525 10725
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+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
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+F 0 "U?" H 11925 6175 60  0000 C CNN
+F 1 "d_or" H 11925 6025 60  0000 C CNN
+F 2 "" H 11925 5800 60  0000 C CNN
+F 3 "" H 11925 5800 60  0000 C CNN
+	1    11925 5800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
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+F 0 "U?" H 12325 13050 60  0000 C CNN
+F 1 "d_or" H 12325 12900 60  0000 C CNN
+F 2 "" H 12325 12675 60  0000 C CNN
+F 3 "" H 12325 12675 60  0000 C CNN
+	1    12325 12675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
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+F 0 "U?" H 12375 3625 60  0000 C CNN
+F 1 "d_or" H 12375 3475 60  0000 C CNN
+F 2 "" H 12375 3250 60  0000 C CNN
+F 3 "" H 12375 3250 60  0000 C CNN
+	1    12375 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 12775 10125
+F 0 "U?" H 12775 10500 60  0000 C CNN
+F 1 "d_or" H 12775 10350 60  0000 C CNN
+F 2 "" H 12775 10125 60  0000 C CNN
+F 3 "" H 12775 10125 60  0000 C CNN
+	1    12775 10125
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 13275 5750
+F 0 "U?" H 13275 6100 60  0000 C CNN
+F 1 "d_nand" H 13275 5950 60  0000 C CNN
+F 2 "" H 13275 5750 60  0000 C CNN
+F 3 "" H 13275 5750 60  0000 C CNN
+	1    13275 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nand U?
+U 1 1 00000000
+P 13675 12625
+F 0 "U?" H 13675 12975 60  0000 C CNN
+F 1 "d_nand" H 13675 12825 60  0000 C CNN
+F 2 "" H 13675 12625 60  0000 C CNN
+F 3 "" H 13675 12625 60  0000 C CNN
+	1    13675 12625
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 00000000
+P 13925 3300
+F 0 "U?" H 13925 3675 60  0000 C CNN
+F 1 "d_nand" H 13925 3525 60  0000 C CNN
+F 2 "" H 13925 3300 60  0000 C CNN
+F 3 "" H 13925 3300 60  0000 C CNN
+	1    13925 3300
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 00000000
+P 14325 10175
+F 0 "U?" H 14325 10550 60  0000 C CNN
+F 1 "d_nand" H 14325 10400 60  0000 C CNN
+F 2 "" H 14325 10175 60  0000 C CNN
+F 3 "" H 14325 10175 60  0000 C CNN
+	1    14325 10175
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 15950 5400
+F 0 "U?" H 15950 5775 60  0000 C CNN
+F 1 "d_or" H 15950 5625 60  0000 C CNN
+F 2 "" H 15950 5400 60  0000 C CNN
+F 3 "" H 15950 5400 60  0000 C CNN
+	1    15950 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 16350 2925
+F 0 "U?" H 16350 3275 60  0000 C CNN
+F 1 "d_or" H 16350 3125 60  0000 C CNN
+F 2 "" H 16350 2925 60  0000 C CNN
+F 3 "" H 16350 2925 60  0000 C CNN
+	1    16350 2925
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 16350 12275
+F 0 "U?" H 16350 12650 60  0000 C CNN
+F 1 "d_or" H 16350 12500 60  0000 C CNN
+F 2 "" H 16350 12275 60  0000 C CNN
+F 3 "" H 16350 12275 60  0000 C CNN
+	1    16350 12275
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 16750 9800
+F 0 "U?" H 16750 10150 60  0000 C CNN
+F 1 "d_or" H 16750 10000 60  0000 C CNN
+F 2 "" H 16750 9800 60  0000 C CNN
+F 3 "" H 16750 9800 60  0000 C CNN
+	1    16750 9800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 17250 5900
+F 0 "U?" H 17250 6275 60  0000 C CNN
+F 1 "d_or" H 17250 6125 60  0000 C CNN
+F 2 "" H 17250 5900 60  0000 C CNN
+F 3 "" H 17250 5900 60  0000 C CNN
+	1    17250 5900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 17525 3525
+F 0 "U?" H 17525 3875 60  0000 C CNN
+F 1 "d_or" H 17525 3725 60  0000 C CNN
+F 2 "" H 17525 3525 60  0000 C CNN
+F 3 "" H 17525 3525 60  0000 C CNN
+	1    17525 3525
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 17650 12775
+F 0 "U?" H 17650 13150 60  0000 C CNN
+F 1 "d_or" H 17650 13000 60  0000 C CNN
+F 2 "" H 17650 12775 60  0000 C CNN
+F 3 "" H 17650 12775 60  0000 C CNN
+	1    17650 12775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_or U?
+U 1 1 00000000
+P 17925 10400
+F 0 "U?" H 17925 10750 60  0000 C CNN
+F 1 "d_or" H 17925 10600 60  0000 C CNN
+F 2 "" H 17925 10400 60  0000 C CNN
+F 3 "" H 17925 10400 60  0000 C CNN
+	1    17925 10400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/analysis b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/analysis
new file mode 100644
index 000000000..2525db397
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/74HC74A_Test_Circuit/74HC74A_TEST_CIRCUIT/analysis
@@ -0,0 +1 @@
+.tran 1e-00 50e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/_autosave-74HC74A.sch b/library/SubcircuitLibrary/IC74HC74A/74HC74A/_autosave-74HC74A.sch
new file mode 100644
index 000000000..3ee4012e1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/_autosave-74HC74A.sch
@@ -0,0 +1,1535 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 5800 4125
+Connection ~ 6200 11000
+Connection ~ 10525 6050
+Connection ~ 10525 7100
+Connection ~ 10900 2125
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+Connection ~ 10925 13975
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+Connection ~ 14200 12575
+Connection ~ 14600 3250
+Connection ~ 15000 10125
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+Connection ~ 18300 3475
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+$EndComp
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+$EndComp
+$Comp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
+$Comp
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+$EndComp
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+$EndComp
+$Comp
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+$EndComp
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+U 9 1 00000000
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+$EndComp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+L eSim_Digital:d_inverter U?
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+F 2 "" H 17925 10400 60  0000 C CNN
+F 3 "" H 17925 10400 60  0000 C CNN
+	1    17925 10400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC74A/74HC74A/analysis b/library/SubcircuitLibrary/IC74HC74A/74HC74A/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC74A/74HC74A/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.cir b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.cir
new file mode 100644
index 000000000..8bf91ccc1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.cir
@@ -0,0 +1,35 @@
+.title KiCad schematic
+U31 Net-_U27-Pad3_ Net-_U1-Pad6_ d_inverter
+U27 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U27-Pad3_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U26 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U26-Pad3_ d_nor
+U30 Net-_U26-Pad3_ Net-_U1-Pad3_ d_inverter
+U19 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_and
+U18 Net-_U10-Pad2_ Net-_U11-Pad1_ Net-_U18-Pad3_ d_and
+U20 Net-_U12-Pad2_ Net-_U13-Pad1_ Net-_U20-Pad3_ d_and
+U21 Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U21-Pad3_ d_and
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+U7 Net-_U1-Pad9_ Net-_U14-Pad1_ d_inverter
+U6 Net-_U1-Pad10_ Net-_U15-Pad1_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U8 Net-_U1-Pad13_ Net-_U17-Pad1_ d_inverter
+U9 Net-_U1-Pad12_ Net-_U16-Pad1_ d_inverter
+U22 Net-_U14-Pad2_ Net-_U15-Pad1_ Net-_U22-Pad3_ d_and
+U23 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U23-Pad3_ d_and
+U3 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U4 Net-_U1-Pad5_ Net-_U13-Pad1_ d_inverter
+U5 Net-_U1-Pad4_ Net-_U12-Pad1_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U28 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U28-Pad3_ d_nor
+U29 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U29-Pad3_ d_nor
+U33 Net-_U29-Pad3_ Net-_U1-Pad11_ d_inverter
+U32 Net-_U28-Pad3_ Net-_U1-Pad8_ d_inverter
+U25 Net-_U16-Pad1_ Net-_U17-Pad2_ Net-_U25-Pad3_ d_and
+U24 Net-_U16-Pad2_ Net-_U17-Pad1_ Net-_U24-Pad3_ d_and
+.end
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.cir.out b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.cir.out
new file mode 100644
index 000000000..a065a7c0a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.cir.out
@@ -0,0 +1,140 @@
+.title kicad schematic
+
+* u31 net-_u27-pad3_ net-_u1-pad6_ d_inverter
+* u27 net-_u20-pad3_ net-_u21-pad3_ net-_u27-pad3_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u26 net-_u18-pad3_ net-_u19-pad3_ net-_u26-pad3_ d_nor
+* u30 net-_u26-pad3_ net-_u1-pad3_ d_inverter
+* u19 net-_u10-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u10-pad2_ net-_u11-pad1_ net-_u18-pad3_ d_and
+* u20 net-_u12-pad2_ net-_u13-pad1_ net-_u20-pad3_ d_and
+* u21 net-_u12-pad1_ net-_u13-pad2_ net-_u21-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u7 net-_u1-pad9_ net-_u14-pad1_ d_inverter
+* u6 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u17-pad1_ d_inverter
+* u9 net-_u1-pad12_ net-_u16-pad1_ d_inverter
+* u22 net-_u14-pad2_ net-_u15-pad1_ net-_u22-pad3_ d_and
+* u23 net-_u14-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_and
+* u3 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad5_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad4_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u28 net-_u22-pad3_ net-_u23-pad3_ net-_u28-pad3_ d_nor
+* u29 net-_u24-pad3_ net-_u25-pad3_ net-_u29-pad3_ d_nor
+* u33 net-_u29-pad3_ net-_u1-pad11_ d_inverter
+* u32 net-_u28-pad3_ net-_u1-pad8_ d_inverter
+* u25 net-_u16-pad1_ net-_u17-pad2_ net-_u25-pad3_ d_and
+* u24 net-_u16-pad2_ net-_u17-pad1_ net-_u24-pad3_ d_and
+a1 net-_u27-pad3_ net-_u1-pad6_ u31
+a2 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u27-pad3_ u27
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u26-pad3_ u26
+a4 net-_u26-pad3_ net-_u1-pad3_ u30
+a5 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u10-pad2_ net-_u11-pad1_ ] net-_u18-pad3_ u18
+a7 [net-_u12-pad2_ net-_u13-pad1_ ] net-_u20-pad3_ u20
+a8 [net-_u12-pad1_ net-_u13-pad2_ ] net-_u21-pad3_ u21
+a9 net-_u17-pad1_ net-_u17-pad2_ u17
+a10 net-_u16-pad1_ net-_u16-pad2_ u16
+a11 net-_u1-pad9_ net-_u14-pad1_ u7
+a12 net-_u1-pad10_ net-_u15-pad1_ u6
+a13 net-_u15-pad1_ net-_u15-pad2_ u15
+a14 net-_u14-pad1_ net-_u14-pad2_ u14
+a15 net-_u1-pad13_ net-_u17-pad1_ u8
+a16 net-_u1-pad12_ net-_u16-pad1_ u9
+a17 [net-_u14-pad2_ net-_u15-pad1_ ] net-_u22-pad3_ u22
+a18 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23
+a19 net-_u1-pad1_ net-_u10-pad1_ u3
+a20 net-_u1-pad2_ net-_u11-pad1_ u2
+a21 net-_u10-pad1_ net-_u10-pad2_ u10
+a22 net-_u11-pad1_ net-_u11-pad2_ u11
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u1-pad5_ net-_u13-pad1_ u4
+a25 net-_u1-pad4_ net-_u12-pad1_ u5
+a26 net-_u12-pad1_ net-_u12-pad2_ u12
+a27 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u28-pad3_ u28
+a28 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u29-pad3_ u29
+a29 net-_u29-pad3_ net-_u1-pad11_ u33
+a30 net-_u28-pad3_ net-_u1-pad8_ u32
+a31 [net-_u16-pad1_ net-_u17-pad2_ ] net-_u25-pad3_ u25
+a32 [net-_u16-pad2_ net-_u17-pad1_ ] net-_u24-pad3_ u24
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.kicad_sch b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.kicad_sch
new file mode 100644
index 000000000..36c6947b5
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.kicad_sch
@@ -0,0 +1,2161 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid f319222f-1e93-4954-a09e-1aa427019a0e)
+
+  (paper "A3")
+
+  (lib_symbols
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+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Value" "d_and" (id 1) (at 171.45 98.425 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Footprint" "" (id 2) (at 171.45 103.505 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 171.45 103.505 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid b46e2d91-40e5-4d88-a327-75cd05b4d5fb))
+    (pin "2" (uuid bd0ef44f-fe5c-4fbc-a424-c69d7e601c88))
+    (pin "3" (uuid df0040a6-3698-4edb-86dd-fad58f0be404))
+  )
+
+  (symbol (lib_id "eSim_Digital:d_inverter") (at 128.905 34.29 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f307faf9-03f3-49d1-abbc-6fac09e1a3d2)
+    (property "Reference" "U10" (id 0) (at 128.905 27.94 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Value" "d_inverter" (id 1) (at 128.905 31.75 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Footprint" "" (id 2) (at 130.175 35.56 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 130.175 35.56 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 4cb2b664-e906-49b6-a41e-f27a041b52af))
+    (pin "2" (uuid 0b2cc1ac-0be7-4fbb-8e0e-5d9704911828))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/c07692fb-6def-4305-9e60-ece5a2a055ce"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/9cd30ed9-049e-4d66-976a-9b33edec4e63"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/3d79850d-34df-4574-a949-1cb2fa5d9b93"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/b9e4015f-6073-47fa-9041-475089066acd"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/308c9690-f11d-4d9a-a26c-f61fa9598706"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/21f76b9f-d897-46ad-85a1-a62ef605249c"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/33de3cbb-2c8a-4c2b-936c-09eb11ad7bcf"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/0dce1f8b-b837-4ec2-9b72-906215c5aa01"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/ad15f7fa-5dd1-411a-af56-104f6bb8ebf9"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/21d3a524-a812-4e6a-8bc9-73bf4eb63af7"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/03714e14-c7cb-4395-839d-dd47c253e4e5"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/cbaa2708-7f62-4504-9bbe-7eb4a4771fe7"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/c64adba6-f304-4a6f-8f7b-4ca58cd84b16"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/4689c642-ba05-4789-b69f-0d88454bf6f7"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/d946d1e2-8884-4562-a223-367a257b3fa0"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/a357f4b4-a77a-4087-ae28-78d5c7a598b2"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/106b7d5b-f762-4f0f-8d25-611dd3f129e9"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/0bdb5e09-d492-48b5-b955-e52aacd32676"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a2f62aa5-7978-46d6-8acd-d50c3b42a9e0"
+      (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a0e50fed-1e8b-4d07-89ee-ec6605ef24ac"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/434ffef4-ed78-4fbe-b928-9b73626eb0ab"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/820ab384-1507-47ec-a527-1120ed025c68"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/29637e45-635b-441e-a473-f9b7c41b8be6"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6ace02d2-226a-441d-85f7-105fcb764ba2"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f307faf9-03f3-49d1-abbc-6fac09e1a3d2"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/92be3097-b83e-45b7-97f7-0c683f28f1fa"
+      (reference "U11") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/e4feb14f-8a40-4720-9ade-76af07c0a3ef"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6549c843-e006-4093-84b0-92b42cf7d552"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6525c2b6-d32f-4fa0-b39a-80d5a01b0acf"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/277e09d6-4e56-462f-bbc0-574a2f9ea4e6"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/56d9c074-1f87-4341-afc4-6cf3df18afbc"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/d5c4d798-43a2-4e3d-a9c2-ab5fe2b42050"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/278ff6bc-d702-402c-8396-674c65f92d55"
+      (reference "U18") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/c3172621-529e-4614-b6f4-43561721f96c"
+      (reference "U19") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/e87baf08-a56c-40f5-b9ff-18362bbfe239"
+      (reference "U20") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/a48ff191-6ea7-4e56-9de7-93f442849be9"
+      (reference "U21") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/84e9e6f1-6ba5-436a-8108-d2f761fff21d"
+      (reference "U22") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/a274ede9-4ee4-496e-9eae-c1cc80b28ccd"
+      (reference "U23") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/d532dd37-36cf-4688-8f3e-04472d3331f0"
+      (reference "U24") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/2be99f1b-5aa0-4ead-be2f-5756925fd31b"
+      (reference "U25") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/311317f1-4d8b-41c9-a379-7a32a640298d"
+      (reference "U26") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/d077bbe1-bd8e-419e-86f6-c51bc842c34e"
+      (reference "U27") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/4a0cda82-2123-44d7-85d5-2cb253304a8d"
+      (reference "U28") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/6a0907ea-79d1-40ef-8a64-93cb16f45986"
+      (reference "U29") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/3d42e2f4-fbdd-4e0d-84bc-3a114f6951cf"
+      (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6ebe93cd-f0d5-48ef-8368-305f5fde279a"
+      (reference "U31") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/77f04a2d-18ff-42e7-93be-e5f414aecdb8"
+      (reference "U32") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/41efc874-bb2e-4cd8-931f-22da9a456ec4"
+      (reference "U33") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.sub b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.sub
new file mode 100644
index 000000000..f22b88c5b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86.sub
@@ -0,0 +1,134 @@
+* Subcircuit 74HC86
+.subckt 74HC86 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u31 net-_u27-pad3_ net-_u1-pad6_ d_inverter
+* u27 net-_u20-pad3_ net-_u21-pad3_ net-_u27-pad3_ d_nor
+* u26 net-_u18-pad3_ net-_u19-pad3_ net-_u26-pad3_ d_nor
+* u30 net-_u26-pad3_ net-_u1-pad3_ d_inverter
+* u19 net-_u10-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u10-pad2_ net-_u11-pad1_ net-_u18-pad3_ d_and
+* u20 net-_u12-pad2_ net-_u13-pad1_ net-_u20-pad3_ d_and
+* u21 net-_u12-pad1_ net-_u13-pad2_ net-_u21-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u7 net-_u1-pad9_ net-_u14-pad1_ d_inverter
+* u6 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u17-pad1_ d_inverter
+* u9 net-_u1-pad12_ net-_u16-pad1_ d_inverter
+* u22 net-_u14-pad2_ net-_u15-pad1_ net-_u22-pad3_ d_and
+* u23 net-_u14-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_and
+* u3 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad5_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad4_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u28 net-_u22-pad3_ net-_u23-pad3_ net-_u28-pad3_ d_nor
+* u29 net-_u24-pad3_ net-_u25-pad3_ net-_u29-pad3_ d_nor
+* u33 net-_u29-pad3_ net-_u1-pad11_ d_inverter
+* u32 net-_u28-pad3_ net-_u1-pad8_ d_inverter
+* u25 net-_u16-pad1_ net-_u17-pad2_ net-_u25-pad3_ d_and
+* u24 net-_u16-pad2_ net-_u17-pad1_ net-_u24-pad3_ d_and
+a1 net-_u27-pad3_ net-_u1-pad6_ u31
+a2 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u27-pad3_ u27
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u26-pad3_ u26
+a4 net-_u26-pad3_ net-_u1-pad3_ u30
+a5 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u10-pad2_ net-_u11-pad1_ ] net-_u18-pad3_ u18
+a7 [net-_u12-pad2_ net-_u13-pad1_ ] net-_u20-pad3_ u20
+a8 [net-_u12-pad1_ net-_u13-pad2_ ] net-_u21-pad3_ u21
+a9 net-_u17-pad1_ net-_u17-pad2_ u17
+a10 net-_u16-pad1_ net-_u16-pad2_ u16
+a11 net-_u1-pad9_ net-_u14-pad1_ u7
+a12 net-_u1-pad10_ net-_u15-pad1_ u6
+a13 net-_u15-pad1_ net-_u15-pad2_ u15
+a14 net-_u14-pad1_ net-_u14-pad2_ u14
+a15 net-_u1-pad13_ net-_u17-pad1_ u8
+a16 net-_u1-pad12_ net-_u16-pad1_ u9
+a17 [net-_u14-pad2_ net-_u15-pad1_ ] net-_u22-pad3_ u22
+a18 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23
+a19 net-_u1-pad1_ net-_u10-pad1_ u3
+a20 net-_u1-pad2_ net-_u11-pad1_ u2
+a21 net-_u10-pad1_ net-_u10-pad2_ u10
+a22 net-_u11-pad1_ net-_u11-pad2_ u11
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u1-pad5_ net-_u13-pad1_ u4
+a25 net-_u1-pad4_ net-_u12-pad1_ u5
+a26 net-_u12-pad1_ net-_u12-pad2_ u12
+a27 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u28-pad3_ u28
+a28 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u29-pad3_ u29
+a29 net-_u29-pad3_ net-_u1-pad11_ u33
+a30 net-_u28-pad3_ net-_u1-pad8_ u32
+a31 [net-_u16-pad1_ net-_u17-pad2_ ] net-_u25-pad3_ u25
+a32 [net-_u16-pad2_ net-_u17-pad1_ ] net-_u24-pad3_ u24
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC86
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Previous_Values.xml
new file mode 100644
index 000000000..064c41d72
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u31 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u31><u27 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u26><u30 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u30><u19 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u19><u18 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u17><u16 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u16><u7 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u6><u15 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u9><u22 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u23><u3 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u2><u10 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u13><u4 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u5><u12 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u12><u28 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u29><u33 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u33><u32 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u32><u25 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u25><u24 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u24></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.cir b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.cir
new file mode 100644
index 000000000..8bf91ccc1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.cir
@@ -0,0 +1,35 @@
+.title KiCad schematic
+U31 Net-_U27-Pad3_ Net-_U1-Pad6_ d_inverter
+U27 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U27-Pad3_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ GND Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ GND PORT
+U26 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U26-Pad3_ d_nor
+U30 Net-_U26-Pad3_ Net-_U1-Pad3_ d_inverter
+U19 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_and
+U18 Net-_U10-Pad2_ Net-_U11-Pad1_ Net-_U18-Pad3_ d_and
+U20 Net-_U12-Pad2_ Net-_U13-Pad1_ Net-_U20-Pad3_ d_and
+U21 Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U21-Pad3_ d_and
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+U7 Net-_U1-Pad9_ Net-_U14-Pad1_ d_inverter
+U6 Net-_U1-Pad10_ Net-_U15-Pad1_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U8 Net-_U1-Pad13_ Net-_U17-Pad1_ d_inverter
+U9 Net-_U1-Pad12_ Net-_U16-Pad1_ d_inverter
+U22 Net-_U14-Pad2_ Net-_U15-Pad1_ Net-_U22-Pad3_ d_and
+U23 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U23-Pad3_ d_and
+U3 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U4 Net-_U1-Pad5_ Net-_U13-Pad1_ d_inverter
+U5 Net-_U1-Pad4_ Net-_U12-Pad1_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U28 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U28-Pad3_ d_nor
+U29 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U29-Pad3_ d_nor
+U33 Net-_U29-Pad3_ Net-_U1-Pad11_ d_inverter
+U32 Net-_U28-Pad3_ Net-_U1-Pad8_ d_inverter
+U25 Net-_U16-Pad1_ Net-_U17-Pad2_ Net-_U25-Pad3_ d_and
+U24 Net-_U16-Pad2_ Net-_U17-Pad1_ Net-_U24-Pad3_ d_and
+.end
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.cir.out b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.cir.out
new file mode 100644
index 000000000..a065a7c0a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.cir.out
@@ -0,0 +1,140 @@
+.title kicad schematic
+
+* u31 net-_u27-pad3_ net-_u1-pad6_ d_inverter
+* u27 net-_u20-pad3_ net-_u21-pad3_ net-_u27-pad3_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd port
+* u26 net-_u18-pad3_ net-_u19-pad3_ net-_u26-pad3_ d_nor
+* u30 net-_u26-pad3_ net-_u1-pad3_ d_inverter
+* u19 net-_u10-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u10-pad2_ net-_u11-pad1_ net-_u18-pad3_ d_and
+* u20 net-_u12-pad2_ net-_u13-pad1_ net-_u20-pad3_ d_and
+* u21 net-_u12-pad1_ net-_u13-pad2_ net-_u21-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u7 net-_u1-pad9_ net-_u14-pad1_ d_inverter
+* u6 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u17-pad1_ d_inverter
+* u9 net-_u1-pad12_ net-_u16-pad1_ d_inverter
+* u22 net-_u14-pad2_ net-_u15-pad1_ net-_u22-pad3_ d_and
+* u23 net-_u14-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_and
+* u3 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad5_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad4_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u28 net-_u22-pad3_ net-_u23-pad3_ net-_u28-pad3_ d_nor
+* u29 net-_u24-pad3_ net-_u25-pad3_ net-_u29-pad3_ d_nor
+* u33 net-_u29-pad3_ net-_u1-pad11_ d_inverter
+* u32 net-_u28-pad3_ net-_u1-pad8_ d_inverter
+* u25 net-_u16-pad1_ net-_u17-pad2_ net-_u25-pad3_ d_and
+* u24 net-_u16-pad2_ net-_u17-pad1_ net-_u24-pad3_ d_and
+a1 net-_u27-pad3_ net-_u1-pad6_ u31
+a2 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u27-pad3_ u27
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u26-pad3_ u26
+a4 net-_u26-pad3_ net-_u1-pad3_ u30
+a5 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u10-pad2_ net-_u11-pad1_ ] net-_u18-pad3_ u18
+a7 [net-_u12-pad2_ net-_u13-pad1_ ] net-_u20-pad3_ u20
+a8 [net-_u12-pad1_ net-_u13-pad2_ ] net-_u21-pad3_ u21
+a9 net-_u17-pad1_ net-_u17-pad2_ u17
+a10 net-_u16-pad1_ net-_u16-pad2_ u16
+a11 net-_u1-pad9_ net-_u14-pad1_ u7
+a12 net-_u1-pad10_ net-_u15-pad1_ u6
+a13 net-_u15-pad1_ net-_u15-pad2_ u15
+a14 net-_u14-pad1_ net-_u14-pad2_ u14
+a15 net-_u1-pad13_ net-_u17-pad1_ u8
+a16 net-_u1-pad12_ net-_u16-pad1_ u9
+a17 [net-_u14-pad2_ net-_u15-pad1_ ] net-_u22-pad3_ u22
+a18 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23
+a19 net-_u1-pad1_ net-_u10-pad1_ u3
+a20 net-_u1-pad2_ net-_u11-pad1_ u2
+a21 net-_u10-pad1_ net-_u10-pad2_ u10
+a22 net-_u11-pad1_ net-_u11-pad2_ u11
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u1-pad5_ net-_u13-pad1_ u4
+a25 net-_u1-pad4_ net-_u12-pad1_ u5
+a26 net-_u12-pad1_ net-_u12-pad2_ u12
+a27 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u28-pad3_ u28
+a28 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u29-pad3_ u29
+a29 net-_u29-pad3_ net-_u1-pad11_ u33
+a30 net-_u28-pad3_ net-_u1-pad8_ u32
+a31 [net-_u16-pad1_ net-_u17-pad2_ ] net-_u25-pad3_ u25
+a32 [net-_u16-pad2_ net-_u17-pad1_ ] net-_u24-pad3_ u24
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.kicad_sch b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.kicad_sch
new file mode 100644
index 000000000..36c6947b5
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.kicad_sch
@@ -0,0 +1,2161 @@
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+    )
+    (path "/c64adba6-f304-4a6f-8f7b-4ca58cd84b16"
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+    )
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+    (path "/d946d1e2-8884-4562-a223-367a257b3fa0"
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+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/0bdb5e09-d492-48b5-b955-e52aacd32676"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/a2f62aa5-7978-46d6-8acd-d50c3b42a9e0"
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+    )
+    (path "/a0e50fed-1e8b-4d07-89ee-ec6605ef24ac"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/434ffef4-ed78-4fbe-b928-9b73626eb0ab"
+      (reference "U6") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/820ab384-1507-47ec-a527-1120ed025c68"
+      (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/29637e45-635b-441e-a473-f9b7c41b8be6"
+      (reference "U8") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6ace02d2-226a-441d-85f7-105fcb764ba2"
+      (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/f307faf9-03f3-49d1-abbc-6fac09e1a3d2"
+      (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/92be3097-b83e-45b7-97f7-0c683f28f1fa"
+      (reference "U11") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/e4feb14f-8a40-4720-9ade-76af07c0a3ef"
+      (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6549c843-e006-4093-84b0-92b42cf7d552"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6525c2b6-d32f-4fa0-b39a-80d5a01b0acf"
+      (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/277e09d6-4e56-462f-bbc0-574a2f9ea4e6"
+      (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/56d9c074-1f87-4341-afc4-6cf3df18afbc"
+      (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/d5c4d798-43a2-4e3d-a9c2-ab5fe2b42050"
+      (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/278ff6bc-d702-402c-8396-674c65f92d55"
+      (reference "U18") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/c3172621-529e-4614-b6f4-43561721f96c"
+      (reference "U19") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/e87baf08-a56c-40f5-b9ff-18362bbfe239"
+      (reference "U20") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/a48ff191-6ea7-4e56-9de7-93f442849be9"
+      (reference "U21") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/84e9e6f1-6ba5-436a-8108-d2f761fff21d"
+      (reference "U22") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/a274ede9-4ee4-496e-9eae-c1cc80b28ccd"
+      (reference "U23") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/d532dd37-36cf-4688-8f3e-04472d3331f0"
+      (reference "U24") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/2be99f1b-5aa0-4ead-be2f-5756925fd31b"
+      (reference "U25") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/311317f1-4d8b-41c9-a379-7a32a640298d"
+      (reference "U26") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/d077bbe1-bd8e-419e-86f6-c51bc842c34e"
+      (reference "U27") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/4a0cda82-2123-44d7-85d5-2cb253304a8d"
+      (reference "U28") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/6a0907ea-79d1-40ef-8a64-93cb16f45986"
+      (reference "U29") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/3d42e2f4-fbdd-4e0d-84bc-3a114f6951cf"
+      (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6ebe93cd-f0d5-48ef-8368-305f5fde279a"
+      (reference "U31") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/77f04a2d-18ff-42e7-93be-e5f414aecdb8"
+      (reference "U32") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/41efc874-bb2e-4cd8-931f-22da9a456ec4"
+      (reference "U33") (unit 1) (value "d_inverter") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.sub b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.sub
new file mode 100644
index 000000000..f22b88c5b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86.sub
@@ -0,0 +1,134 @@
+* Subcircuit 74HC86
+.subckt 74HC86 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ gnd 
+.title kicad schematic
+* u31 net-_u27-pad3_ net-_u1-pad6_ d_inverter
+* u27 net-_u20-pad3_ net-_u21-pad3_ net-_u27-pad3_ d_nor
+* u26 net-_u18-pad3_ net-_u19-pad3_ net-_u26-pad3_ d_nor
+* u30 net-_u26-pad3_ net-_u1-pad3_ d_inverter
+* u19 net-_u10-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u10-pad2_ net-_u11-pad1_ net-_u18-pad3_ d_and
+* u20 net-_u12-pad2_ net-_u13-pad1_ net-_u20-pad3_ d_and
+* u21 net-_u12-pad1_ net-_u13-pad2_ net-_u21-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u7 net-_u1-pad9_ net-_u14-pad1_ d_inverter
+* u6 net-_u1-pad10_ net-_u15-pad1_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u8 net-_u1-pad13_ net-_u17-pad1_ d_inverter
+* u9 net-_u1-pad12_ net-_u16-pad1_ d_inverter
+* u22 net-_u14-pad2_ net-_u15-pad1_ net-_u22-pad3_ d_and
+* u23 net-_u14-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_and
+* u3 net-_u1-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad2_ net-_u11-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u4 net-_u1-pad5_ net-_u13-pad1_ d_inverter
+* u5 net-_u1-pad4_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u28 net-_u22-pad3_ net-_u23-pad3_ net-_u28-pad3_ d_nor
+* u29 net-_u24-pad3_ net-_u25-pad3_ net-_u29-pad3_ d_nor
+* u33 net-_u29-pad3_ net-_u1-pad11_ d_inverter
+* u32 net-_u28-pad3_ net-_u1-pad8_ d_inverter
+* u25 net-_u16-pad1_ net-_u17-pad2_ net-_u25-pad3_ d_and
+* u24 net-_u16-pad2_ net-_u17-pad1_ net-_u24-pad3_ d_and
+a1 net-_u27-pad3_ net-_u1-pad6_ u31
+a2 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u27-pad3_ u27
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u26-pad3_ u26
+a4 net-_u26-pad3_ net-_u1-pad3_ u30
+a5 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u10-pad2_ net-_u11-pad1_ ] net-_u18-pad3_ u18
+a7 [net-_u12-pad2_ net-_u13-pad1_ ] net-_u20-pad3_ u20
+a8 [net-_u12-pad1_ net-_u13-pad2_ ] net-_u21-pad3_ u21
+a9 net-_u17-pad1_ net-_u17-pad2_ u17
+a10 net-_u16-pad1_ net-_u16-pad2_ u16
+a11 net-_u1-pad9_ net-_u14-pad1_ u7
+a12 net-_u1-pad10_ net-_u15-pad1_ u6
+a13 net-_u15-pad1_ net-_u15-pad2_ u15
+a14 net-_u14-pad1_ net-_u14-pad2_ u14
+a15 net-_u1-pad13_ net-_u17-pad1_ u8
+a16 net-_u1-pad12_ net-_u16-pad1_ u9
+a17 [net-_u14-pad2_ net-_u15-pad1_ ] net-_u22-pad3_ u22
+a18 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23
+a19 net-_u1-pad1_ net-_u10-pad1_ u3
+a20 net-_u1-pad2_ net-_u11-pad1_ u2
+a21 net-_u10-pad1_ net-_u10-pad2_ u10
+a22 net-_u11-pad1_ net-_u11-pad2_ u11
+a23 net-_u13-pad1_ net-_u13-pad2_ u13
+a24 net-_u1-pad5_ net-_u13-pad1_ u4
+a25 net-_u1-pad4_ net-_u12-pad1_ u5
+a26 net-_u12-pad1_ net-_u12-pad2_ u12
+a27 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u28-pad3_ u28
+a28 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u29-pad3_ u29
+a29 net-_u29-pad3_ net-_u1-pad11_ u33
+a30 net-_u28-pad3_ net-_u1-pad8_ u32
+a31 [net-_u16-pad1_ net-_u17-pad2_ ] net-_u25-pad3_ u25
+a32 [net-_u16-pad2_ net-_u17-pad1_ ] net-_u24-pad3_ u24
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC86
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_Previous_Values.xml
new file mode 100644
index 000000000..064c41d72
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u31 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u31><u27 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u26><u30 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u30><u19 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u19><u18 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u17><u16 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u16><u7 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u6><u15 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u15><u14 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u9><u22 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u23><u3 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u3><u2 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u2><u10 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u11><u13 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u13><u4 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u5><u12 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u12><u28 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u29><u33 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u33><u32 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u32><u25 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u25><u24 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u24></model><devicemodel /><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.cir b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.cir
new file mode 100644
index 000000000..b6a4ef9e9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.cir
@@ -0,0 +1,19 @@
+.title KiCad schematic
+V_4B1 Net-_V_4B1-Pad1_ GND DC
+U6 V_4Y plot_v1
+U5 V_3Y plot_v1
+U7 Net-_V_4B1-Pad1_ Net-_V_4A1-Pad1_ Net-_V_3B1-Pad1_ Net-_V_3A1-Pad1_ Net-_U7-Pad5_ Net-_U7-Pad6_ Net-_U7-Pad7_ Net-_U7-Pad8_ adc_bridge_4
+v1 Net-_X1-Pad14_ GND 5
+V_3A1 Net-_V_3A1-Pad1_ GND DC
+V_3B1 Net-_V_3B1-Pad1_ GND DC
+V_4A1 Net-_V_4A1-Pad1_ GND DC
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ Net-_U4-Pad4_ V_4Y V_3Y V_2Y V_1Y dac_bridge_4
+U3 V_2Y plot_v1
+V_2A1 Net-_V_2A1-Pad1_ GND DC
+V_1B1 Net-_V_1B1-Pad1_ GND DC
+V_1A1 Net-_V_1A1-Pad1_ GND DC
+V_2B1 Net-_V_2B1-Pad1_ GND DC
+X1 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad4_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U4-Pad3_ GND Net-_U4-Pad2_ Net-_U7-Pad8_ Net-_U7-Pad7_ Net-_U4-Pad1_ Net-_U7-Pad6_ Net-_U7-Pad5_ Net-_X1-Pad14_ 74HC86
+U2 V_1Y plot_v1
+U1 Net-_V_1A1-Pad1_ Net-_V_1B1-Pad1_ Net-_V_2A1-Pad1_ Net-_V_2B1-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4
+.end
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.cir.out b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.cir.out
new file mode 100644
index 000000000..a2e325ea1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.cir.out
@@ -0,0 +1,42 @@
+.title kicad schematic
+
+.include 74HC86.sub
+v_4b1 net-_v_4b1-pad1_ gnd  dc 5
+* u6 v_4y plot_v1
+* u5 v_3y plot_v1
+* u7 net-_v_4b1-pad1_ net-_v_4a1-pad1_ net-_v_3b1-pad1_ net-_v_3a1-pad1_ net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ adc_bridge_4
+v1 net-_x1-pad14_ gnd 5
+v_3a1 net-_v_3a1-pad1_ gnd  dc 5
+v_3b1 net-_v_3b1-pad1_ gnd  dc 0
+v_4a1 net-_v_4a1-pad1_ gnd  dc 5
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ v_4y v_3y v_2y v_1y dac_bridge_4
+* u3 v_2y plot_v1
+v_2a1 net-_v_2a1-pad1_ gnd  dc 0
+v_1b1 net-_v_1b1-pad1_ gnd  dc 0
+v_1a1 net-_v_1a1-pad1_ gnd  dc 0
+v_2b1 net-_v_2b1-pad1_ gnd  dc 5
+x1 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad4_ net-_u1-pad7_ net-_u1-pad8_ net-_u4-pad3_ gnd net-_u4-pad2_ net-_u7-pad8_ net-_u7-pad7_ net-_u4-pad1_ net-_u7-pad6_ net-_u7-pad5_ net-_x1-pad14_ 74HC86
+* u2 v_1y plot_v1
+* u1 net-_v_1a1-pad1_ net-_v_1b1-pad1_ net-_v_2a1-pad1_ net-_v_2b1-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
+a1 [net-_v_4b1-pad1_ net-_v_4a1-pad1_ net-_v_3b1-pad1_ net-_v_3a1-pad1_ ] [net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ ] u7
+a2 [net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ ] [v_4y v_3y v_2y v_1y ] u4
+a3 [net-_v_1a1-pad1_ net-_v_1b1-pad1_ net-_v_2a1-pad1_ net-_v_2b1-pad1_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, Ngspice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-00 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(v_4y)
+plot v(v_3y)
+plot v(v_2y)
+plot v(v_1y)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.kicad_sch b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.kicad_sch
new file mode 100644
index 000000000..ca7dc803a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.kicad_sch
@@ -0,0 +1,1113 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 60960b6c-bfab-43d3-b20c-75a24e867391)
+
+  (paper "A3")
+
+  (lib_symbols
+    (symbol "eSim_Hybrid:adc_bridge_4" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "adc_bridge_4" (id 1) (at 0 7.62 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "adc_bridge_4_0_1"
+        (rectangle (start -8.89 8.89) (end 8.89 -5.08)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
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diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.proj b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.proj
new file mode 100644
index 000000000..7edab0ae7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.proj
@@ -0,0 +1 @@
+schematicFile 74HC86.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.raw b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.raw
new file mode 100644
index 000000000..d4ca7542e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST.raw
@@ -0,0 +1,1628 @@
+Title: kicad schematic
+Date: Mon Jan 26 19:42:33  2026
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 27
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(net-_v_4b1-pad1_)	voltage
+	2	v(net-_x1-pad14_)	voltage
+	3	v(net-_v_3a1-pad1_)	voltage
+	4	v(net-_v_3b1-pad1_)	voltage
+	5	v(net-_v_4a1-pad1_)	voltage
+	6	v(net-_v_2a1-pad1_)	voltage
+	7	v(net-_v_1b1-pad1_)	voltage
+	8	v(net-_v_1a1-pad1_)	voltage
+	9	v(net-_v_2b1-pad1_)	voltage
+	10	v(v_4y)	voltage
+	11	v(v_3y)	voltage
+	12	v(v_2y)	voltage
+	13	v(v_1y)	voltage
+	14	i(v_2b1)	current
+	15	i(v_1a1)	current
+	16	i(v_1b1)	current
+	17	i(v_2a1)	current
+	18	i(v_4a1)	current
+	19	i(v_3b1)	current
+	20	i(v_3a1)	current
+	21	i(v1)	current
+	22	i(v_4b1)	current
+	23	i(a2)	current
+	24	i(a2)	current
+	25	i(a2)	current
+	26	i(a2)	current
+Values:
+0		0.000000000000000e+00
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+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
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+	5.000000000000000e+00
+	0.000000000000000e+00
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+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+3		4.000000000000000e-03
+	5.000000000000000e+00
+	5.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
+	0.000000000000000e+00
+	5.000000000000000e+00
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+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
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+	0.000000000000000e+00
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diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST_Previous_Values.xml b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST_Previous_Values.xml
new file mode 100644
index 000000000..6ba6effff
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/74HC86_TEST_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source><v_4b1 name="Source type">dc<field1 name="Value">5</field1></v_4b1><v1 name="Source type">5</v1><v_3a1 name="Source type">dc<field1 name="Value">5</field1></v_3a1><v_3b1 name="Source type">dc<field1 name="Value">0</field1></v_3b1><v_4a1 name="Source type">dc<field1 name="Value">5</field1></v_4a1><v_2a1 name="Source type">dc<field1 name="Value">0</field1></v_2a1><v_1b1 name="Source type">dc<field1 name="Value">0</field1></v_1b1><v_1a1 name="Source type">dc<field1 name="Value">0</field1></v_1a1><v_2b1 name="Source type">dc<field1 name="Value">5</field1></v_2b1></source><model><u7 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u7><u4 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u4><u1 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u1></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC86</field></x1></subcircuit><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/_autosave-74HC86.sch b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/_autosave-74HC86.sch
new file mode 100644
index 000000000..c889934bc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/_autosave-74HC86.sch
@@ -0,0 +1,737 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
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+$EndComp
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+F 2 "" H 10075 7225 60  0000 C CNN
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+F 2 "" H 10350 9725 60  0000 C CNN
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+	1    0    0    -1  
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+L eSim_Digital:d_and U18
+U 1 1 00000000
+P 6675 1450
+F 0 "U18" H 6675 1800 60  0000 C CNN
+F 1 "d_and" H 6675 1650 60  0000 C CNN
+F 2 "" H 6675 1450 60  0000 C CNN
+F 3 "" H 6675 1450 60  0000 C CNN
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+	1    0    0    -1  
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+L eSim_Digital:d_and U19
+U 1 1 00000000
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+F 0 "U19" H 6675 2750 60  0000 C CNN
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+F 2 "" H 6675 2400 60  0000 C CNN
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+F 0 "U20" H 6750 4425 60  0000 C CNN
+F 1 "d_and" H 6750 4275 60  0000 C CNN
+F 2 "" H 6750 4075 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U21
+U 1 1 00000000
+P 6750 5025
+F 0 "U21" H 6750 5375 60  0000 C CNN
+F 1 "d_and" H 6750 5225 60  0000 C CNN
+F 2 "" H 6750 5025 60  0000 C CNN
+F 3 "" H 6750 5025 60  0000 C CNN
+	1    6750 5025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U22
+U 1 1 00000000
+P 6925 6750
+F 0 "U22" H 6925 7100 60  0000 C CNN
+F 1 "d_and" H 6925 6950 60  0000 C CNN
+F 2 "" H 6925 6750 60  0000 C CNN
+F 3 "" H 6925 6750 60  0000 C CNN
+	1    6925 6750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U23
+U 1 1 00000000
+P 6925 7700
+F 0 "U23" H 6925 8050 60  0000 C CNN
+F 1 "d_and" H 6925 7900 60  0000 C CNN
+F 2 "" H 6925 7700 60  0000 C CNN
+F 3 "" H 6925 7700 60  0000 C CNN
+	1    6925 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U24
+U 1 1 00000000
+P 7200 9250
+F 0 "U24" H 7200 9600 60  0000 C CNN
+F 1 "d_and" H 7200 9450 60  0000 C CNN
+F 2 "" H 7200 9250 60  0000 C CNN
+F 3 "" H 7200 9250 60  0000 C CNN
+	1    7200 9250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U25
+U 1 1 00000000
+P 7200 10200
+F 0 "U25" H 7200 10550 60  0000 C CNN
+F 1 "d_and" H 7200 10400 60  0000 C CNN
+F 2 "" H 7200 10200 60  0000 C CNN
+F 3 "" H 7200 10200 60  0000 C CNN
+	1    7200 10200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U26
+U 1 1 00000000
+P 8500 2025
+F 0 "U26" H 8500 2400 60  0000 C CNN
+F 1 "d_nor" H 8500 2250 60  0000 C CNN
+F 2 "" H 8500 2025 60  0000 C CNN
+F 3 "" H 8500 2025 60  0000 C CNN
+	1    8500 2025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U27
+U 1 1 00000000
+P 8575 4650
+F 0 "U27" H 8575 5025 60  0000 C CNN
+F 1 "d_nor" H 8575 4875 60  0000 C CNN
+F 2 "" H 8575 4650 60  0000 C CNN
+F 3 "" H 8575 4650 60  0000 C CNN
+	1    8575 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U28
+U 1 1 00000000
+P 8750 7325
+F 0 "U28" H 8750 7700 60  0000 C CNN
+F 1 "d_nor" H 8750 7550 60  0000 C CNN
+F 2 "" H 8750 7325 60  0000 C CNN
+F 3 "" H 8750 7325 60  0000 C CNN
+	1    8750 7325
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U29
+U 1 1 00000000
+P 9025 9825
+F 0 "U29" H 9025 10200 60  0000 C CNN
+F 1 "d_nor" H 9025 10050 60  0000 C CNN
+F 2 "" H 9025 9825 60  0000 C CNN
+F 3 "" H 9025 9825 60  0000 C CNN
+	1    9025 9825
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/analysis b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/analysis
new file mode 100644
index 000000000..14a32166e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/74HC86_Test_Circuit/74HC86_TEST/analysis
@@ -0,0 +1 @@
+.tran 1e-00 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/_autosave-74HC86.sch b/library/SubcircuitLibrary/IC74HC86/74HC86/_autosave-74HC86.sch
new file mode 100644
index 000000000..c889934bc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/_autosave-74HC86.sch
@@ -0,0 +1,737 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 4375 1350
+Connection ~ 4400 2400
+Connection ~ 4450 3975
+Connection ~ 4475 5025
+Connection ~ 4625 6650
+Connection ~ 4650 7700
+Connection ~ 4900 9150
+Connection ~ 4925 10200
+Wire Wire Line
+	2800 1350 3300 1350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	2900 5025 3350 5025
+Wire Wire Line
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+Wire Wire Line
+	3075 7700 3525 7700
+Wire Wire Line
+	3325 9150 3825 9150
+Wire Wire Line
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+Wire Wire Line
+	3875 2400 4400 2400
+Wire Wire Line
+	3900 1350 4375 1350
+Wire Wire Line
+	3950 5025 4475 5025
+Wire Wire Line
+	3975 3975 4450 3975
+Wire Wire Line
+	4125 7700 4650 7700
+Wire Wire Line
+	4150 6650 4625 6650
+Wire Wire Line
+	4375 1350 4375 1725
+Wire Wire Line
+	4375 1350 4775 1350
+Wire Wire Line
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+Wire Wire Line
+	4400 2000 4400 2400
+Wire Wire Line
+	4400 2000 5750 2000
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4450 3975 4850 3975
+Wire Wire Line
+	4450 4350 6050 4350
+Wire Wire Line
+	4475 4625 4475 5025
+Wire Wire Line
+	4475 4625 5825 4625
+Wire Wire Line
+	4475 5025 4850 5025
+Wire Wire Line
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+Wire Wire Line
+	4625 6650 5025 6650
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4650 7300 6000 7300
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4925 9800 4925 10200
+Wire Wire Line
+	4925 9800 6275 9800
+Wire Wire Line
+	4925 10200 5300 10200
+Wire Wire Line
+	5375 1350 6225 1350
+Wire Wire Line
+	5375 2400 6225 2400
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+L eSim_Power:eSim_GND #PWR01
+U 1 1 00000000
+P 13850 6675
+F 0 "#PWR01" H 13850 6425 50  0001 C CNN
+F 1 "eSim_GND" H 13850 6500 50  0000 C CNN
+F 2 "" H 13850 6675 50  0001 C CNN
+F 3 "" H 13850 6675 50  0001 C CNN
+	1    13850 6675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Power:eSim_GND #PWR02
+U 1 1 00000000
+P 13875 6050
+F 0 "#PWR02" H 13875 5800 50  0001 C CNN
+F 1 "eSim_GND" H 13875 5850 50  0000 C CNN
+F 2 "" H 13875 6050 50  0001 C CNN
+F 3 "" H 13875 6050 50  0001 C CNN
+	1    13875 6050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 1 1 00000000
+P 2550 1350
+F 0 "U1" H 2575 1525 30  0000 C CNN
+F 1 "PORT" H 2575 1425 30  0000 C CNN
+F 2 "" H 2550 1350 60  0000 C CNN
+F 3 "" H 2550 1350 60  0000 C CNN
+	1    2550 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 2 1 00000000
+P 2575 2400
+F 0 "U1" H 2600 2600 30  0000 C CNN
+F 1 "PORT" H 2600 2500 30  0000 C CNN
+F 2 "" H 2575 2400 60  0000 C CNN
+F 3 "" H 2575 2400 60  0000 C CNN
+	2    2575 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 4 1 00000000
+P 2625 3975
+F 0 "U1" H 2650 4175 30  0000 C CNN
+F 1 "PORT" H 2650 4075 30  0000 C CNN
+F 2 "" H 2625 3975 60  0000 C CNN
+F 3 "" H 2625 3975 60  0000 C CNN
+	4    2625 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 5 1 00000000
+P 2650 5025
+F 0 "U1" H 2675 5200 30  0000 C CNN
+F 1 "PORT" H 2675 5100 30  0000 C CNN
+F 2 "" H 2650 5025 60  0000 C CNN
+F 3 "" H 2650 5025 60  0000 C CNN
+	5    2650 5025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 9 1 00000000
+P 2800 6650
+F 0 "U1" H 2825 6825 30  0000 C CNN
+F 1 "PORT" H 2825 6725 30  0000 C CNN
+F 2 "" H 2800 6650 60  0000 C CNN
+F 3 "" H 2800 6650 60  0000 C CNN
+	9    2800 6650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 10 1 00000000
+P 2825 7700
+F 0 "U1" H 2850 7900 30  0000 C CNN
+F 1 "PORT" H 2850 7800 30  0000 C CNN
+F 2 "" H 2825 7700 60  0000 C CNN
+F 3 "" H 2825 7700 60  0000 C CNN
+	10   2825 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 12 1 00000000
+P 3075 9150
+F 0 "U1" H 3100 9325 30  0000 C CNN
+F 1 "PORT" H 3100 9225 30  0000 C CNN
+F 2 "" H 3075 9150 60  0000 C CNN
+F 3 "" H 3075 9150 60  0000 C CNN
+	12   3075 9150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 13 1 00000000
+P 3100 10200
+F 0 "U1" H 3125 10400 30  0000 C CNN
+F 1 "PORT" H 3125 10300 30  0000 C CNN
+F 2 "" H 3100 10200 60  0000 C CNN
+F 3 "" H 3100 10200 60  0000 C CNN
+	13   3100 10200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 3 1 00000000
+P 10675 1975
+F 0 "U1" H 10525 2000 30  0000 R CNN
+F 1 "PORT" H 10525 1900 30  0000 R CNN
+F 2 "" H 10675 1975 60  0000 C CNN
+F 3 "" H 10675 1975 60  0000 C CNN
+	3    10675 1975
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 6 1 00000000
+P 10750 4600
+F 0 "U1" H 10625 4625 30  0000 R CNN
+F 1 "PORT" H 10625 4525 30  0000 R CNN
+F 2 "" H 10750 4600 60  0000 C CNN
+F 3 "" H 10750 4600 60  0000 C CNN
+	6    10750 4600
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 8 1 00000000
+P 10925 7275
+F 0 "U1" H 10775 7300 30  0000 R CNN
+F 1 "PORT" H 10775 7200 30  0000 R CNN
+F 2 "" H 10925 7275 60  0000 C CNN
+F 3 "" H 10925 7275 60  0000 C CNN
+	8    10925 7275
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 11 1 00000000
+P 11200 9775
+F 0 "U1" H 11075 9800 30  0000 R CNN
+F 1 "PORT" H 11075 9700 30  0000 R CNN
+F 2 "" H 11200 9775 60  0000 C CNN
+F 3 "" H 11200 9775 60  0000 C CNN
+	11   11200 9775
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 7 1 00000000
+P 13275 6050
+F 0 "U1" H 13300 6225 30  0000 C CNN
+F 1 "PORT" H 13300 6125 30  0000 C CNN
+F 2 "" H 13275 6050 60  0000 C CNN
+F 3 "" H 13275 6050 60  0000 C CNN
+	7    13275 6050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 14 1 00000000
+P 13275 6675
+F 0 "U1" H 13300 6850 30  0000 C CNN
+F 1 "PORT" H 13300 6750 30  0000 C CNN
+F 2 "" H 13275 6675 60  0000 C CNN
+F 3 "" H 13275 6675 60  0000 C CNN
+	14   13275 6675
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U2
+U 1 1 00000000
+P 3575 2400
+F 0 "U2" H 3575 2650 60  0000 C CNN
+F 1 "d_inverter" H 3575 2500 60  0000 C CNN
+F 2 "" H 3625 2350 60  0000 C CNN
+F 3 "" H 3625 2350 60  0000 C CNN
+	1    3575 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U3
+U 1 1 00000000
+P 3600 1350
+F 0 "U3" H 3600 1600 60  0000 C CNN
+F 1 "d_inverter" H 3600 1450 60  0000 C CNN
+F 2 "" H 3650 1300 60  0000 C CNN
+F 3 "" H 3650 1300 60  0000 C CNN
+	1    3600 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U4
+U 1 1 00000000
+P 3650 5025
+F 0 "U4" H 3650 5275 60  0000 C CNN
+F 1 "d_inverter" H 3650 5125 60  0000 C CNN
+F 2 "" H 3700 4975 60  0000 C CNN
+F 3 "" H 3700 4975 60  0000 C CNN
+	1    3650 5025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U5
+U 1 1 00000000
+P 3675 3975
+F 0 "U5" H 3675 4225 60  0000 C CNN
+F 1 "d_inverter" H 3675 4075 60  0000 C CNN
+F 2 "" H 3725 3925 60  0000 C CNN
+F 3 "" H 3725 3925 60  0000 C CNN
+	1    3675 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U6
+U 1 1 00000000
+P 3825 7700
+F 0 "U6" H 3825 7950 60  0000 C CNN
+F 1 "d_inverter" H 3825 7800 60  0000 C CNN
+F 2 "" H 3875 7650 60  0000 C CNN
+F 3 "" H 3875 7650 60  0000 C CNN
+	1    3825 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U7
+U 1 1 00000000
+P 3850 6650
+F 0 "U7" H 3850 6900 60  0000 C CNN
+F 1 "d_inverter" H 3850 6750 60  0000 C CNN
+F 2 "" H 3900 6600 60  0000 C CNN
+F 3 "" H 3900 6600 60  0000 C CNN
+	1    3850 6650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U8
+U 1 1 00000000
+P 4100 10200
+F 0 "U8" H 4100 10450 60  0000 C CNN
+F 1 "d_inverter" H 4100 10300 60  0000 C CNN
+F 2 "" H 4150 10150 60  0000 C CNN
+F 3 "" H 4150 10150 60  0000 C CNN
+	1    4100 10200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U9
+U 1 1 00000000
+P 4125 9150
+F 0 "U9" H 4125 9400 60  0000 C CNN
+F 1 "d_inverter" H 4125 9250 60  0000 C CNN
+F 2 "" H 4175 9100 60  0000 C CNN
+F 3 "" H 4175 9100 60  0000 C CNN
+	1    4125 9150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U10
+U 1 1 00000000
+P 5075 1350
+F 0 "U10" H 5075 1600 60  0000 C CNN
+F 1 "d_inverter" H 5075 1450 60  0000 C CNN
+F 2 "" H 5125 1300 60  0000 C CNN
+F 3 "" H 5125 1300 60  0000 C CNN
+	1    5075 1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U11
+U 1 1 00000000
+P 5075 2400
+F 0 "U11" H 5075 2650 60  0000 C CNN
+F 1 "d_inverter" H 5075 2500 60  0000 C CNN
+F 2 "" H 5125 2350 60  0000 C CNN
+F 3 "" H 5125 2350 60  0000 C CNN
+	1    5075 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U12
+U 1 1 00000000
+P 5150 3975
+F 0 "U12" H 5150 4225 60  0000 C CNN
+F 1 "d_inverter" H 5150 4075 60  0000 C CNN
+F 2 "" H 5200 3925 60  0000 C CNN
+F 3 "" H 5200 3925 60  0000 C CNN
+	1    5150 3975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U13
+U 1 1 00000000
+P 5150 5025
+F 0 "U13" H 5150 5275 60  0000 C CNN
+F 1 "d_inverter" H 5150 5125 60  0000 C CNN
+F 2 "" H 5200 4975 60  0000 C CNN
+F 3 "" H 5200 4975 60  0000 C CNN
+	1    5150 5025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 5325 6650
+F 0 "U14" H 5325 6900 60  0000 C CNN
+F 1 "d_inverter" H 5325 6750 60  0000 C CNN
+F 2 "" H 5375 6600 60  0000 C CNN
+F 3 "" H 5375 6600 60  0000 C CNN
+	1    5325 6650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U15
+U 1 1 00000000
+P 5325 7700
+F 0 "U15" H 5325 7950 60  0000 C CNN
+F 1 "d_inverter" H 5325 7800 60  0000 C CNN
+F 2 "" H 5375 7650 60  0000 C CNN
+F 3 "" H 5375 7650 60  0000 C CNN
+	1    5325 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U16
+U 1 1 00000000
+P 5600 9150
+F 0 "U16" H 5600 9400 60  0000 C CNN
+F 1 "d_inverter" H 5600 9250 60  0000 C CNN
+F 2 "" H 5650 9100 60  0000 C CNN
+F 3 "" H 5650 9100 60  0000 C CNN
+	1    5600 9150
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U17
+U 1 1 00000000
+P 5600 10200
+F 0 "U17" H 5600 10450 60  0000 C CNN
+F 1 "d_inverter" H 5600 10300 60  0000 C CNN
+F 2 "" H 5650 10150 60  0000 C CNN
+F 3 "" H 5650 10150 60  0000 C CNN
+	1    5600 10200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U30
+U 1 1 00000000
+P 9775 1975
+F 0 "U30" H 9775 2250 60  0000 C CNN
+F 1 "d_inverter" H 9775 2100 60  0000 C CNN
+F 2 "" H 9825 1925 60  0000 C CNN
+F 3 "" H 9825 1925 60  0000 C CNN
+	1    9775 1975
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U31
+U 1 1 00000000
+P 9850 4600
+F 0 "U31" H 9850 4875 60  0000 C CNN
+F 1 "d_inverter" H 9850 4725 60  0000 C CNN
+F 2 "" H 9900 4550 60  0000 C CNN
+F 3 "" H 9900 4550 60  0000 C CNN
+	1    9850 4600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U32
+U 1 1 00000000
+P 10025 7275
+F 0 "U32" H 10025 7550 60  0000 C CNN
+F 1 "d_inverter" H 10025 7400 60  0000 C CNN
+F 2 "" H 10075 7225 60  0000 C CNN
+F 3 "" H 10075 7225 60  0000 C CNN
+	1    10025 7275
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U33
+U 1 1 00000000
+P 10300 9775
+F 0 "U33" H 10300 10050 60  0000 C CNN
+F 1 "d_inverter" H 10300 9900 60  0000 C CNN
+F 2 "" H 10350 9725 60  0000 C CNN
+F 3 "" H 10350 9725 60  0000 C CNN
+	1    10300 9775
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U18
+U 1 1 00000000
+P 6675 1450
+F 0 "U18" H 6675 1800 60  0000 C CNN
+F 1 "d_and" H 6675 1650 60  0000 C CNN
+F 2 "" H 6675 1450 60  0000 C CNN
+F 3 "" H 6675 1450 60  0000 C CNN
+	1    6675 1450
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U19
+U 1 1 00000000
+P 6675 2400
+F 0 "U19" H 6675 2750 60  0000 C CNN
+F 1 "d_and" H 6675 2600 60  0000 C CNN
+F 2 "" H 6675 2400 60  0000 C CNN
+F 3 "" H 6675 2400 60  0000 C CNN
+	1    6675 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U20
+U 1 1 00000000
+P 6750 4075
+F 0 "U20" H 6750 4425 60  0000 C CNN
+F 1 "d_and" H 6750 4275 60  0000 C CNN
+F 2 "" H 6750 4075 60  0000 C CNN
+F 3 "" H 6750 4075 60  0000 C CNN
+	1    6750 4075
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U21
+U 1 1 00000000
+P 6750 5025
+F 0 "U21" H 6750 5375 60  0000 C CNN
+F 1 "d_and" H 6750 5225 60  0000 C CNN
+F 2 "" H 6750 5025 60  0000 C CNN
+F 3 "" H 6750 5025 60  0000 C CNN
+	1    6750 5025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U22
+U 1 1 00000000
+P 6925 6750
+F 0 "U22" H 6925 7100 60  0000 C CNN
+F 1 "d_and" H 6925 6950 60  0000 C CNN
+F 2 "" H 6925 6750 60  0000 C CNN
+F 3 "" H 6925 6750 60  0000 C CNN
+	1    6925 6750
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U23
+U 1 1 00000000
+P 6925 7700
+F 0 "U23" H 6925 8050 60  0000 C CNN
+F 1 "d_and" H 6925 7900 60  0000 C CNN
+F 2 "" H 6925 7700 60  0000 C CNN
+F 3 "" H 6925 7700 60  0000 C CNN
+	1    6925 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U24
+U 1 1 00000000
+P 7200 9250
+F 0 "U24" H 7200 9600 60  0000 C CNN
+F 1 "d_and" H 7200 9450 60  0000 C CNN
+F 2 "" H 7200 9250 60  0000 C CNN
+F 3 "" H 7200 9250 60  0000 C CNN
+	1    7200 9250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_and U25
+U 1 1 00000000
+P 7200 10200
+F 0 "U25" H 7200 10550 60  0000 C CNN
+F 1 "d_and" H 7200 10400 60  0000 C CNN
+F 2 "" H 7200 10200 60  0000 C CNN
+F 3 "" H 7200 10200 60  0000 C CNN
+	1    7200 10200
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U26
+U 1 1 00000000
+P 8500 2025
+F 0 "U26" H 8500 2400 60  0000 C CNN
+F 1 "d_nor" H 8500 2250 60  0000 C CNN
+F 2 "" H 8500 2025 60  0000 C CNN
+F 3 "" H 8500 2025 60  0000 C CNN
+	1    8500 2025
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U27
+U 1 1 00000000
+P 8575 4650
+F 0 "U27" H 8575 5025 60  0000 C CNN
+F 1 "d_nor" H 8575 4875 60  0000 C CNN
+F 2 "" H 8575 4650 60  0000 C CNN
+F 3 "" H 8575 4650 60  0000 C CNN
+	1    8575 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U28
+U 1 1 00000000
+P 8750 7325
+F 0 "U28" H 8750 7700 60  0000 C CNN
+F 1 "d_nor" H 8750 7550 60  0000 C CNN
+F 2 "" H 8750 7325 60  0000 C CNN
+F 3 "" H 8750 7325 60  0000 C CNN
+	1    8750 7325
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Digital:d_nor U29
+U 1 1 00000000
+P 9025 9825
+F 0 "U29" H 9025 10200 60  0000 C CNN
+F 1 "d_nor" H 9025 10050 60  0000 C CNN
+F 2 "" H 9025 9825 60  0000 C CNN
+F 3 "" H 9025 9825 60  0000 C CNN
+	1    9025 9825
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74HC86/74HC86/analysis b/library/SubcircuitLibrary/IC74HC86/74HC86/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74HC86/74HC86/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and-cache.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.pro b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.sch b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and-cache.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and-rescue.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.pro b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.sch b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60  0000 C CNN
+F 1 "3_and" H 4650 4000 60  0000 C CNN
+F 2 "" H 3700 3500 60  0000 C CNN
+F 3 "" H 3700 3500 60  0000 C CNN
+	1    3700 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60  0000 C CNN
+F 1 "d_and" H 5500 3500 60  0000 C CNN
+F 2 "" H 5450 3400 60  0000 C CNN
+F 3 "" H 5450 3400 60  0000 C CNN
+	1    5450 3400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5000 3100 5000 3300
+Wire Wire Line
+	4150 3000 4150 2700
+Wire Wire Line
+	4150 2700 3200 2700
+Wire Wire Line
+	4150 3100 4000 3100
+Wire Wire Line
+	4000 3100 4000 3000
+Wire Wire Line
+	4000 3000 3200 3000
+Wire Wire Line
+	4150 3200 4150 3300
+Wire Wire Line
+	4150 3300 3250 3300
+Wire Wire Line
+	5000 3400 5000 3550
+Wire Wire Line
+	5000 3550 3250 3550
+Wire Wire Line
+	5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30  0000 C CNN
+F 1 "PORT" H 2950 2700 30  0000 C CNN
+F 2 "" H 2950 2700 60  0000 C CNN
+F 3 "" H 2950 2700 60  0000 C CNN
+	1    2950 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30  0000 C CNN
+F 1 "PORT" H 2950 3000 30  0000 C CNN
+F 2 "" H 2950 3000 60  0000 C CNN
+F 3 "" H 2950 3000 60  0000 C CNN
+	2    2950 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30  0000 C CNN
+F 1 "PORT" H 3000 3300 30  0000 C CNN
+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	3    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30  0000 C CNN
+F 1 "PORT" H 3000 3550 30  0000 C CNN
+F 2 "" H 3000 3550 60  0000 C CNN
+F 3 "" H 3000 3550 60  0000 C CNN
+	4    3000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30  0000 C CNN
+F 1 "PORT" H 6750 3350 30  0000 C CNN
+F 2 "" H 6750 3350 60  0000 C CNN
+F 3 "" H 6750 3350 60  0000 C CNN
+	5    6750 3350
+	-1   0    0    1   
+$EndComp
+Text Notes 3450 2650 0    60   ~ 12
+in1
+Text Notes 3450 2950 0    60   ~ 12
+in2
+Text Notes 3500 3300 0    60   ~ 12
+in3
+Text Notes 3500 3550 0    60   ~ 12
+in4
+Text Notes 6150 3350 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/4_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and-cache.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and-rescue.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.pro b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.sch b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/5_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir
new file mode 100644
index 000000000..723ae75ad
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir
@@ -0,0 +1,45 @@
+.title KiCad schematic
+U33 Net-_U33-Pad1_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_nor
+U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U34-Pad2_ d_nor
+U37 Net-_U34-Pad3_ Net-_U28-Pad3_ Net-_U1-Pad14_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ GND Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ GND Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+U34 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U34-Pad3_ d_nor
+U32 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U31-Pad2_ d_nand
+U28 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U28-Pad3_ d_nor
+U29 Net-_U25-Pad3_ Net-_U29-Pad2_ Net-_U1-Pad15_ d_xor
+U27 Net-_U26-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad2_ d_nor
+U36 Net-_U31-Pad2_ Net-_U20-Pad3_ Net-_U35-Pad2_ d_and
+X6 Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U11-Pad3_ Net-_U35-Pad1_ 3_and
+U31 Net-_U30-Pad2_ Net-_U31-Pad2_ Net-_U29-Pad2_ d_and
+U30 Net-_U28-Pad3_ Net-_U30-Pad2_ d_inverter
+X5 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U10-Pad2_ Net-_U33-Pad2_ 4_and
+X4 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U33-Pad1_ 5_and
+U20 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U20-Pad3_ d_nor
+U23 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U22-Pad1_ d_nand
+U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter
+U6 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ d_and
+U9 Net-_U6-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_and
+U14 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U12-Pad2_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ d_inverter
+U7 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U6-Pad2_ d_nand
+U11 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U11-Pad3_ d_nor
+U15 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U14-Pad2_ d_nand
+U2 Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter
+X2 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U24-Pad1_ 4_and
+U26 Net-_U22-Pad1_ Net-_U11-Pad3_ Net-_U26-Pad3_ d_and
+X3 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U10-Pad2_ Net-_U24-Pad2_ 3_and
+X1 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U16-Pad1_ 3_and
+U22 Net-_U22-Pad1_ Net-_U21-Pad2_ Net-_U19-Pad2_ d_and
+U21 Net-_U20-Pad3_ Net-_U21-Pad2_ d_inverter
+U17 Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U16-Pad2_ d_and
+U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_nor
+U25 Net-_U24-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_nor
+U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad9_ d_xor
+U18 Net-_U16-Pad3_ Net-_U11-Pad3_ Net-_U18-Pad3_ d_nor
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U19 Net-_U18-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad2_ d_xor
+U12 Net-_U10-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad6_ d_xor
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir.out
new file mode 100644
index 000000000..c55334e36
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir.out
@@ -0,0 +1,165 @@
+.title kicad schematic
+
+.include 3_and.sub
+.include 5_and.sub
+.include 4_and.sub
+* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u33-pad3_ d_nor
+* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u34-pad2_ d_nor
+* u37 net-_u34-pad3_ net-_u28-pad3_ net-_u1-pad14_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ gnd net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ gnd net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+* u34 net-_u33-pad3_ net-_u34-pad2_ net-_u34-pad3_ d_nor
+* u32 net-_u1-pad1_ net-_u1-pad16_ net-_u31-pad2_ d_nand
+* u28 net-_u1-pad1_ net-_u1-pad16_ net-_u28-pad3_ d_nor
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u1-pad15_ d_xor
+* u27 net-_u26-pad3_ net-_u20-pad3_ net-_u25-pad2_ d_nor
+* u36 net-_u31-pad2_ net-_u20-pad3_ net-_u35-pad2_ d_and
+x6 net-_u22-pad1_ net-_u31-pad2_ net-_u11-pad3_ net-_u35-pad1_ 3_and
+* u31 net-_u30-pad2_ net-_u31-pad2_ net-_u29-pad2_ d_and
+* u30 net-_u28-pad3_ net-_u30-pad2_ d_inverter
+x5 net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u10-pad2_ net-_u33-pad2_ 4_and
+x4 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u33-pad1_ 5_and
+* u20 net-_u1-pad3_ net-_u1-pad4_ net-_u20-pad3_ d_nor
+* u23 net-_u1-pad3_ net-_u1-pad4_ net-_u22-pad1_ d_nand
+* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ net-_u4-pad2_ d_and
+* u9 net-_u6-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and
+* u14 net-_u13-pad2_ net-_u14-pad2_ net-_u12-pad2_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ d_inverter
+* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u10-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad11_ net-_u6-pad2_ d_nand
+* u11 net-_u1-pad8_ net-_u1-pad7_ net-_u11-pad3_ d_nor
+* u15 net-_u1-pad8_ net-_u1-pad7_ net-_u14-pad2_ d_nand
+* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter
+x2 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u24-pad1_ 4_and
+* u26 net-_u22-pad1_ net-_u11-pad3_ net-_u26-pad3_ d_and
+x3 net-_u14-pad2_ net-_u22-pad1_ net-_u10-pad2_ net-_u24-pad2_ 3_and
+x1 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u16-pad1_ 3_and
+* u22 net-_u22-pad1_ net-_u21-pad2_ net-_u19-pad2_ d_and
+* u21 net-_u20-pad3_ net-_u21-pad2_ d_inverter
+* u17 net-_u14-pad2_ net-_u10-pad2_ net-_u16-pad2_ d_and
+* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor
+* u25 net-_u24-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_nor
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad9_ d_xor
+* u18 net-_u16-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u19 net-_u18-pad3_ net-_u19-pad2_ net-_u1-pad2_ d_xor
+* u12 net-_u10-pad3_ net-_u12-pad2_ net-_u1-pad6_ d_xor
+a1 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a2 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u34-pad2_ u35
+a3 [net-_u34-pad3_ net-_u28-pad3_ ] net-_u1-pad14_ u37
+a4 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u34-pad3_ u34
+a5 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u31-pad2_ u32
+a6 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u28-pad3_ u28
+a7 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u1-pad15_ u29
+a8 [net-_u26-pad3_ net-_u20-pad3_ ] net-_u25-pad2_ u27
+a9 [net-_u31-pad2_ net-_u20-pad3_ ] net-_u35-pad2_ u36
+a10 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u29-pad2_ u31
+a11 net-_u28-pad3_ net-_u30-pad2_ u30
+a12 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u20-pad3_ u20
+a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u22-pad1_ u23
+a14 net-_u2-pad2_ net-_u3-pad2_ u3
+a15 net-_u10-pad2_ net-_u5-pad2_ u5
+a16 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u4-pad2_ u6
+a17 [net-_u6-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u9
+a18 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u12-pad2_ u14
+a19 net-_u11-pad3_ net-_u13-pad2_ u13
+a20 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u10-pad2_ u7
+a21 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u6-pad2_ u8
+a22 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u11-pad3_ u11
+a23 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u14-pad2_ u15
+a24 net-_u1-pad13_ net-_u2-pad2_ u2
+a25 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u26-pad3_ u26
+a26 [net-_u22-pad1_ net-_u21-pad2_ ] net-_u19-pad2_ u22
+a27 net-_u20-pad3_ net-_u21-pad2_ u21
+a28 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u16-pad2_ u17
+a29 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a30 [net-_u24-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
+a31 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u1-pad9_ u4
+a32 [net-_u16-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18
+a33 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a34 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a35 [net-_u18-pad3_ net-_u19-pad2_ ] net-_u1-pad2_ u19
+a36 [net-_u10-pad3_ net-_u12-pad2_ ] net-_u1-pad6_ u12
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u19 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir.txt b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir.txt
new file mode 100644
index 000000000..44e09960a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.cir.txt
@@ -0,0 +1,46 @@
+.title KiCad schematic
+U33 Net-_U33-Pad1_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_nor
+U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U34-Pad2_ d_nor
+U37 Net-_U34-Pad3_ Net-_U28-Pad3_ Net-_U1-Pad14_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ GND Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ GND Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+U34 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U34-Pad3_ d_nor
+U32 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U31-Pad2_ d_nand
+U28 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U28-Pad3_ d_nor
+U29 Net-_U25-Pad3_ Net-_U29-Pad2_ Net-_U1-Pad15_ d_xor
+U27 Net-_U26-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad2_ d_nor
+U36 Net-_U31-Pad2_ Net-_U20-Pad3_ Net-_U35-Pad2_ d_and
+X6 Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U11-Pad3_ Net-_U35-Pad1_ 3_and
+U31 Net-_U30-Pad2_ Net-_U31-Pad2_ Net-_U29-Pad2_ d_and
+U30 Net-_U28-Pad3_ Net-_U30-Pad2_ d_inverter
+X5 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U10-Pad2_ Net-_U33-Pad2_ 4_and
+X4 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U33-Pad1_ 5_and
+U20 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U20-Pad3_ d_nor
+U23 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U22-Pad1_ d_nand
+U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter
+U6 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ d_and
+U9 Net-_U6-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_and
+U14 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U12-Pad2_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ d_inverter
+U7 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U6-Pad2_ d_nand
+U11 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U11-Pad3_ d_nor
+U15 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U14-Pad2_ d_nand
+U2 Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter
+X2 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U24-Pad1_ 4_and
+U26 Net-_U22-Pad1_ Net-_U11-Pad3_ Net-_U26-Pad3_ d_and
+X3 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U10-Pad2_ Net-_U24-Pad2_ 3_and
+X1 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U16-Pad1_ 3_and
+U22 Net-_U22-Pad1_ Net-_U21-Pad2_ Net-_U19-Pad2_ d_and
+U21 Net-_U20-Pad3_ Net-_U21-Pad2_ d_inverter
+U17 Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U16-Pad2_ d_and
+U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_nor
+U25 Net-_U24-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_nor
+U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad9_ d_xor
+U18 Net-_U16-Pad3_ Net-_U11-Pad3_ Net-_U18-Pad3_ d_nor
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U19 Net-_U18-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad2_ d_xor
+U12 Net-_U10-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad6_ d_xor
+.end
+
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_prl b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_prl
new file mode 100644
index 000000000..b4533b173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_prl
@@ -0,0 +1,75 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "",
+    "auto_track_width": true,
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
+      13,
+      14,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "74LS83.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_pro b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_pro
new file mode 100644
index 000000000..2a12c62ec
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_pro
@@ -0,0 +1,294 @@
+{
+  "board": {
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "74LS83.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Spice",
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "04eb507f-10b6-4ac6-bb2a-65616eb44f33",
+      ""
+    ]
+  ],
+  "text_variables": {}
+}
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_sch b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_sch
new file mode 100644
index 000000000..b940b23c0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.kicad_sch
@@ -0,0 +1,3412 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 04eb507f-10b6-4ac6-bb2a-65616eb44f33)
+
+  (paper "A2")
+
+  (lib_symbols
+    (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_and" (id 1) (at 1.27 2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_and_0_1"
+        (polyline
+          (pts
+            (xy 3.81 -1.27)
+            (xy -6.35 -1.27)
+            (xy -6.35 3.81)
+            (xy 3.81 3.81)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_and_1_1"
+        (pin input line (at -11.43 2.54 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -11.43 0 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 11.43 1.27 180) (length 5.08)
+          (name "OUT" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 -2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_inverter" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_inverter_0_1"
+        (polyline
+          (pts
+            (xy -2.54 1.27)
+            (xy -2.54 -1.27)
+            (xy 2.54 0)
+            (xy -2.54 1.27)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_inverter_1_1"
+        (pin input line (at -7.62 0 0) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output inverted (at 7.62 0 180) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_nand" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
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+    (pin "2" (uuid 2f5eee4f-fd54-4a24-9ba2-153585157a52))
+    (pin "3" (uuid 96bdbb03-5003-4bf4-8e2d-c70723d5bf4b))
+    (pin "4" (uuid e6840fde-b42a-47a4-92aa-53cf8487e06e))
+    (pin "5" (uuid af2e1e6b-be70-4ca0-8a9a-6608762fe11d))
+    (pin "6" (uuid c93df8cb-bcd3-4ec4-9d96-bae88e610a33))
+    (pin "7" (uuid ddc55bf5-afa3-4f18-b5c2-ee4182bb57c1))
+    (pin "8" (uuid 19b23044-622d-4351-b2a2-733378185f32))
+    (pin "9" (uuid 595eeb75-584a-47ff-96e5-aba1c5dd4fed))
+    (pin "10" (uuid 87c98a1c-8a9c-4283-b4e9-60018a93aaad))
+    (pin "11" (uuid d69732f1-d623-4eb5-b7f9-d31b9226e5c0))
+    (pin "12" (uuid 7ce16d17-11cc-4110-bdcd-c5b62240f18a))
+    (pin "13" (uuid 7461163a-2ca8-4434-ba27-6c8630127ed8))
+    (pin "14" (uuid 48badb1e-3af6-4375-b420-e25b25a810e0))
+    (pin "15" (uuid 85f80fba-beea-48b6-9468-57c83e773247))
+    (pin "16" (uuid e74a46b3-d6c5-4102-9f90-1f443d96f078))
+    (pin "17" (uuid eaecee58-aee1-477d-bef9-a34d2695fa75))
+    (pin "18" (uuid 4833a109-5d64-4725-9880-8bc98a9c7fa7))
+    (pin "19" (uuid 16aad1b1-6efc-4626-95fa-83bc077f52dc))
+    (pin "20" (uuid fe98b05e-6a52-4894-ac05-bdd4579361be))
+    (pin "21" (uuid 37cc23b9-2f43-4506-8ccc-c618f2b80032))
+    (pin "22" (uuid 9771921c-d516-4b4b-bb23-5d0ba1420c18))
+    (pin "23" (uuid dc9d92d6-f2e3-4830-9908-a201df004a1f))
+    (pin "24" (uuid d8f38b0e-8005-4270-aa3b-fd2485a6e7be))
+    (pin "25" (uuid b8b844bc-26df-4a03-8747-94c151699a11))
+    (pin "26" (uuid 9e48c09b-8227-4311-ad01-ea6df68cc13a))
+  )
+
+  (symbol (lib_id "eSim_Digital:d_xor") (at 170.18 323.215 90) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid ee4ea1c7-a11c-44d1-97e7-f14f190a6dfa)
+    (property "Reference" "U12" (id 0) (at 172.72 321.945 90)
+      (effects (font (size 1.524 1.524)) (justify right))
+    )
+    (property "Value" "d_xor" (id 1) (at 172.72 325.12 90)
+      (effects (font (size 1.1938 1.1938)) (justify right))
+    )
+    (property "Footprint" "" (id 2) (at 170.18 323.215 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 170.18 323.215 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 15e8c30c-731c-4d60-9927-97f5a1dd3937))
+    (pin "2" (uuid 1cf1c3f6-c946-4f08-a535-09e1fb5efe7d))
+    (pin "3" (uuid 2cc58c4c-b5da-4455-a823-10258c086065))
+  )
+
+  (symbol (lib_id "eSim_Miscellaneous:PORT") (at 105.41 51.435 90) (mirror x) (unit 10)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f8f0ae3b-691e-467a-a3ac-7ee5926adc70)
+    (property "Reference" "U1" (id 0) (at 100.33 52.07 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Value" "PORT" (id 1) (at 102.87 52.07 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Footprint" "" (id 2) (at 105.41 51.435 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 105.41 51.435 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 32650968-e987-4b78-ac9d-c8ec5ae580b0))
+    (pin "2" (uuid 5284aa48-cfe4-43e8-a392-f54d89cf1682))
+    (pin "3" (uuid 33c324b1-d268-4c51-9d14-882f890d9032))
+    (pin "4" (uuid c57c2172-af89-458f-a0b5-0e2a39f8027a))
+    (pin "5" (uuid dddab577-33a7-416f-a099-ba55376f90c1))
+    (pin "6" (uuid b78c2e03-d676-47c9-b803-0846df700e69))
+    (pin "7" (uuid 51adf4a0-e6ea-4fc2-b1e8-e0abff628f6e))
+    (pin "8" (uuid 06fa291b-dc3c-4ab1-84b2-9c7071a760b5))
+    (pin "9" (uuid 3f8cb50f-3d4a-491b-8418-cacda346f90d))
+    (pin "10" (uuid 6a421cf4-762f-4ea7-90a7-9d97a50c81f1))
+    (pin "11" (uuid 0259b869-0be5-4c53-9a11-4b2e9f4cfb70))
+    (pin "12" (uuid a7073c61-a27e-4ba8-9efe-9a7fd0573fa2))
+    (pin "13" (uuid 4749e5be-0f02-44a9-aa58-dec82c7f90f1))
+    (pin "14" (uuid 77d9656a-a024-4f08-b93e-f122a755398a))
+    (pin "15" (uuid 26dd4307-8383-47f9-9b2f-ca73628b7771))
+    (pin "16" (uuid d6de67ca-2a8f-42e1-9b7f-f1b2c04a93ef))
+    (pin "17" (uuid 0f9bea7a-4d0f-4ca6-b5bd-8db2a572206f))
+    (pin "18" (uuid 2e44977a-0735-46a4-be5f-fc4373aa022a))
+    (pin "19" (uuid 0eb7e9ed-5854-4a85-8580-8bbef03b2b00))
+    (pin "20" (uuid 1f1cb59c-a80e-4abf-abe4-02e53648338f))
+    (pin "21" (uuid 8a13047b-216a-4fc8-99a3-b5ea6fea9bca))
+    (pin "22" (uuid 2a19852d-8716-4909-9c5a-253fa1713d8c))
+    (pin "23" (uuid 7bbfec7d-6d8c-4b2f-97c8-20015c1f990a))
+    (pin "24" (uuid ca31cb7b-c790-4e28-abe2-c4dc302720e1))
+    (pin "25" (uuid e86e4376-c7e2-434a-b47e-8ed97fadfc08))
+    (pin "26" (uuid 3459991f-887c-4478-8ef7-6edf8c90ea86))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/d7f2f3c0-4623-4d11-912c-9cb83a9d10d0"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/6b646d19-3391-4d18-a2ab-cbf06135855f"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/ae442690-d7cc-4547-aaab-a987b9aa9079"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/e8661895-adf8-47c4-b5b8-03926bce2898"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/18be16c0-1c98-44c5-88ed-dd82f69f9ef6"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/5242ae5b-4fd7-4187-a463-c111c68b083a"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/3883f092-da1a-463c-8233-6051c7c0c37c"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/8ca72e6d-0cda-4f16-a26e-bd6354f9d0d9"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/ecf86bd5-b1c7-4ab5-876e-8d618506c771"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/54e6305f-d5eb-468f-bec4-99ec4395204b"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/0e313b7b-0e0b-4233-a9c3-f96e3c8e359c"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/f8f0ae3b-691e-467a-a3ac-7ee5926adc70"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/2267fe2a-e08a-41c8-b850-0bbaa38fd704"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/6271bebe-7945-4185-bd69-6e09d2ea8a67"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/0a2f39a2-ecfd-410e-9515-073f89951795"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/b104f17b-38dd-46c2-82a1-a1f005794857"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/49a82764-481c-46d4-80a6-b0dc04926da3"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/c2490a11-76b6-4eb9-9941-d20bfa5e71fd"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/727be04b-5134-43c1-b3e1-f6faf0709bee"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/06f308d7-5ec0-48bd-a96c-736e222ec49f"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6aeb3039-9600-49a4-931e-5cf6927144e1"
+      (reference "U4") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/e619ab85-199d-43f9-b90b-df7047f9f783"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c4e0ed43-12be-42f2-b04e-48ec6bd4279d"
+      (reference "U6") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/13208c70-96e7-49a3-8d14-bf761d010a23"
+      (reference "U7") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b507ef94-5957-42fe-8f96-f9d1403a7906"
+      (reference "U8") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/e6ac8b26-37ca-4e7b-bdb6-e3f57eabd794"
+      (reference "U9") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/763994ad-e490-419b-bd49-a61a3d9be9a9"
+      (reference "U10") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/1832402b-a42a-474e-9b9c-3fd567f9aa47"
+      (reference "U11") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/ee4ea1c7-a11c-44d1-97e7-f14f190a6dfa"
+      (reference "U12") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/b3e66f2e-6261-4f34-9914-6e272e580393"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c3f2223f-2112-42a7-bf3b-c169b52908a5"
+      (reference "U14") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/d50258f8-e589-4fd6-88e2-4dcfe090b241"
+      (reference "U15") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/d6c668ed-885a-4454-8070-4f77f14cad96"
+      (reference "U16") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/3434dcc5-138b-434e-bde3-6bce90fa4161"
+      (reference "U17") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/da639c8b-d7b1-482e-901f-9306b138820d"
+      (reference "U18") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0f3cc159-c4b3-4992-b7c3-f796a6ce5d51"
+      (reference "U19") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/2ba7bd73-7e5d-4aad-ba02-1dd2e36a680d"
+      (reference "U20") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/7ebe236c-6131-48bf-bbf2-67c5800b677e"
+      (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/97308ba3-7b58-4b51-81fc-6ad40e79e425"
+      (reference "U22") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/59ef5793-620b-49ce-b3f7-7ec72a529fa4"
+      (reference "U23") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/ab05a71b-bd7a-4c82-bd95-cef7d908735d"
+      (reference "U24") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/a8578ddc-3d82-47b2-93ea-305326df9663"
+      (reference "U25") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b8e56fd6-a24a-4696-a8dd-27b17a23e740"
+      (reference "U26") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/e26a87c6-311f-4471-95f8-74c959587f75"
+      (reference "U27") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b6528284-3aa5-4eec-b905-0d90a1563829"
+      (reference "U28") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/2ea9c543-bafe-4042-b3e1-2e64f1ace3e2"
+      (reference "U29") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/9e8b7537-5043-469c-8efe-094a07628f75"
+      (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c5f4eaaa-1ed2-4f99-8676-c5801b211126"
+      (reference "U31") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/b5345862-baea-4554-b114-cfb064403df6"
+      (reference "U32") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/91fcf55e-12be-4092-9f4b-c3f9f04366e5"
+      (reference "U33") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0606497b-b65d-4bb4-9ac0-589c9826325e"
+      (reference "U34") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/63bf30f8-904b-49ad-805c-dc0a480197cd"
+      (reference "U35") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/d64dca26-00e0-417b-92df-467c4826c54a"
+      (reference "U36") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/0f31771f-c0b1-42fe-aef3-ed753c5d5f49"
+      (reference "U37") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/c2b6327a-24c5-406f-b57a-1dc1ed0ec722"
+      (reference "X1") (unit 1) (value "3_and") (footprint "")
+    )
+    (path "/841c9ad9-e9a0-49e0-ab0a-3099f6d1fa5f"
+      (reference "X2") (unit 1) (value "4_and") (footprint "")
+    )
+    (path "/e12d2b3b-f2d6-4753-97c9-39227b96b7ee"
+      (reference "X3") (unit 1) (value "3_and") (footprint "")
+    )
+    (path "/406f8e83-48f8-4a57-8ebb-90aa656183f8"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/5dfe0b87-d843-4ebe-955d-61174908b9b6"
+      (reference "X5") (unit 1) (value "4_and") (footprint "")
+    )
+    (path "/c99ade31-1be4-4b27-8c9f-53d76bbf1ac2"
+      (reference "X6") (unit 1) (value "3_and") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.sub
new file mode 100644
index 000000000..b81f13f64
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83.sub
@@ -0,0 +1,159 @@
+* Subcircuit 74LS83
+.subckt 74LS83 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ gnd net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ gnd net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ 
+.title kicad schematic
+.include 3_and.sub
+.include 5_and.sub
+.include 4_and.sub
+* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u33-pad3_ d_nor
+* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u34-pad2_ d_nor
+* u37 net-_u34-pad3_ net-_u28-pad3_ net-_u1-pad14_ d_nor
+* u34 net-_u33-pad3_ net-_u34-pad2_ net-_u34-pad3_ d_nor
+* u32 net-_u1-pad1_ net-_u1-pad16_ net-_u31-pad2_ d_nand
+* u28 net-_u1-pad1_ net-_u1-pad16_ net-_u28-pad3_ d_nor
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u1-pad15_ d_xor
+* u27 net-_u26-pad3_ net-_u20-pad3_ net-_u25-pad2_ d_nor
+* u36 net-_u31-pad2_ net-_u20-pad3_ net-_u35-pad2_ d_and
+x6 net-_u22-pad1_ net-_u31-pad2_ net-_u11-pad3_ net-_u35-pad1_ 3_and
+* u31 net-_u30-pad2_ net-_u31-pad2_ net-_u29-pad2_ d_and
+* u30 net-_u28-pad3_ net-_u30-pad2_ d_inverter
+x5 net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u10-pad2_ net-_u33-pad2_ 4_and
+x4 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u33-pad1_ 5_and
+* u20 net-_u1-pad3_ net-_u1-pad4_ net-_u20-pad3_ d_nor
+* u23 net-_u1-pad3_ net-_u1-pad4_ net-_u22-pad1_ d_nand
+* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ net-_u4-pad2_ d_and
+* u9 net-_u6-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and
+* u14 net-_u13-pad2_ net-_u14-pad2_ net-_u12-pad2_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ d_inverter
+* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u10-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad11_ net-_u6-pad2_ d_nand
+* u11 net-_u1-pad8_ net-_u1-pad7_ net-_u11-pad3_ d_nor
+* u15 net-_u1-pad8_ net-_u1-pad7_ net-_u14-pad2_ d_nand
+* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter
+x2 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u24-pad1_ 4_and
+* u26 net-_u22-pad1_ net-_u11-pad3_ net-_u26-pad3_ d_and
+x3 net-_u14-pad2_ net-_u22-pad1_ net-_u10-pad2_ net-_u24-pad2_ 3_and
+x1 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u16-pad1_ 3_and
+* u22 net-_u22-pad1_ net-_u21-pad2_ net-_u19-pad2_ d_and
+* u21 net-_u20-pad3_ net-_u21-pad2_ d_inverter
+* u17 net-_u14-pad2_ net-_u10-pad2_ net-_u16-pad2_ d_and
+* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor
+* u25 net-_u24-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_nor
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad9_ d_xor
+* u18 net-_u16-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u19 net-_u18-pad3_ net-_u19-pad2_ net-_u1-pad2_ d_xor
+* u12 net-_u10-pad3_ net-_u12-pad2_ net-_u1-pad6_ d_xor
+a1 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a2 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u34-pad2_ u35
+a3 [net-_u34-pad3_ net-_u28-pad3_ ] net-_u1-pad14_ u37
+a4 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u34-pad3_ u34
+a5 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u31-pad2_ u32
+a6 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u28-pad3_ u28
+a7 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u1-pad15_ u29
+a8 [net-_u26-pad3_ net-_u20-pad3_ ] net-_u25-pad2_ u27
+a9 [net-_u31-pad2_ net-_u20-pad3_ ] net-_u35-pad2_ u36
+a10 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u29-pad2_ u31
+a11 net-_u28-pad3_ net-_u30-pad2_ u30
+a12 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u20-pad3_ u20
+a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u22-pad1_ u23
+a14 net-_u2-pad2_ net-_u3-pad2_ u3
+a15 net-_u10-pad2_ net-_u5-pad2_ u5
+a16 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u4-pad2_ u6
+a17 [net-_u6-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u9
+a18 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u12-pad2_ u14
+a19 net-_u11-pad3_ net-_u13-pad2_ u13
+a20 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u10-pad2_ u7
+a21 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u6-pad2_ u8
+a22 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u11-pad3_ u11
+a23 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u14-pad2_ u15
+a24 net-_u1-pad13_ net-_u2-pad2_ u2
+a25 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u26-pad3_ u26
+a26 [net-_u22-pad1_ net-_u21-pad2_ ] net-_u19-pad2_ u22
+a27 net-_u20-pad3_ net-_u21-pad2_ u21
+a28 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u16-pad2_ u17
+a29 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a30 [net-_u24-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
+a31 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u1-pad9_ u4
+a32 [net-_u16-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18
+a33 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a34 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a35 [net-_u18-pad3_ net-_u19-pad2_ ] net-_u1-pad2_ u19
+a36 [net-_u10-pad3_ net-_u12-pad2_ ] net-_u1-pad6_ u12
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u19 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74LS83
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Previous_Values.xml
new file mode 100644
index 000000000..1d915ac37
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model><u4 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u10 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u8 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u7><u11 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u11><u2 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u2><u9 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u9><u6 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u6><u16 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u5><u15 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u15><u12 name="type">d_xor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u12><u18 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_xor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19><u22 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u26><u21 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_nor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u20><u23 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u23><u32 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u32><u28 name="type">d_nor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u27 name="type">d_nor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u27><u24 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u25><u29 name="type">d_xor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u29><u36 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u36><u30 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u31><u34 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u34><u35 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u35><u33 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u33><u37 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u37></model><devicemodel /><subcircuit><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and-cache.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.pro b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.sch b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and-cache.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and-rescue.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.pro b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.sch b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60  0000 C CNN
+F 1 "3_and" H 4650 4000 60  0000 C CNN
+F 2 "" H 3700 3500 60  0000 C CNN
+F 3 "" H 3700 3500 60  0000 C CNN
+	1    3700 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60  0000 C CNN
+F 1 "d_and" H 5500 3500 60  0000 C CNN
+F 2 "" H 5450 3400 60  0000 C CNN
+F 3 "" H 5450 3400 60  0000 C CNN
+	1    5450 3400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5000 3100 5000 3300
+Wire Wire Line
+	4150 3000 4150 2700
+Wire Wire Line
+	4150 2700 3200 2700
+Wire Wire Line
+	4150 3100 4000 3100
+Wire Wire Line
+	4000 3100 4000 3000
+Wire Wire Line
+	4000 3000 3200 3000
+Wire Wire Line
+	4150 3200 4150 3300
+Wire Wire Line
+	4150 3300 3250 3300
+Wire Wire Line
+	5000 3400 5000 3550
+Wire Wire Line
+	5000 3550 3250 3550
+Wire Wire Line
+	5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30  0000 C CNN
+F 1 "PORT" H 2950 2700 30  0000 C CNN
+F 2 "" H 2950 2700 60  0000 C CNN
+F 3 "" H 2950 2700 60  0000 C CNN
+	1    2950 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30  0000 C CNN
+F 1 "PORT" H 2950 3000 30  0000 C CNN
+F 2 "" H 2950 3000 60  0000 C CNN
+F 3 "" H 2950 3000 60  0000 C CNN
+	2    2950 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30  0000 C CNN
+F 1 "PORT" H 3000 3300 30  0000 C CNN
+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	3    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30  0000 C CNN
+F 1 "PORT" H 3000 3550 30  0000 C CNN
+F 2 "" H 3000 3550 60  0000 C CNN
+F 3 "" H 3000 3550 60  0000 C CNN
+	4    3000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30  0000 C CNN
+F 1 "PORT" H 6750 3350 30  0000 C CNN
+F 2 "" H 6750 3350 60  0000 C CNN
+F 3 "" H 6750 3350 60  0000 C CNN
+	5    6750 3350
+	-1   0    0    1   
+$EndComp
+Text Notes 3450 2650 0    60   ~ 12
+in1
+Text Notes 3450 2950 0    60   ~ 12
+in2
+Text Notes 3500 3300 0    60   ~ 12
+in3
+Text Notes 3500 3550 0    60   ~ 12
+in4
+Text Notes 6150 3350 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and-cache.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and-rescue.lib b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.pro b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.sch b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir
new file mode 100644
index 000000000..723ae75ad
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir
@@ -0,0 +1,45 @@
+.title KiCad schematic
+U33 Net-_U33-Pad1_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_nor
+U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U34-Pad2_ d_nor
+U37 Net-_U34-Pad3_ Net-_U28-Pad3_ Net-_U1-Pad14_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ GND Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ GND Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+U34 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U34-Pad3_ d_nor
+U32 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U31-Pad2_ d_nand
+U28 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U28-Pad3_ d_nor
+U29 Net-_U25-Pad3_ Net-_U29-Pad2_ Net-_U1-Pad15_ d_xor
+U27 Net-_U26-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad2_ d_nor
+U36 Net-_U31-Pad2_ Net-_U20-Pad3_ Net-_U35-Pad2_ d_and
+X6 Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U11-Pad3_ Net-_U35-Pad1_ 3_and
+U31 Net-_U30-Pad2_ Net-_U31-Pad2_ Net-_U29-Pad2_ d_and
+U30 Net-_U28-Pad3_ Net-_U30-Pad2_ d_inverter
+X5 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U10-Pad2_ Net-_U33-Pad2_ 4_and
+X4 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U33-Pad1_ 5_and
+U20 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U20-Pad3_ d_nor
+U23 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U22-Pad1_ d_nand
+U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter
+U6 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ d_and
+U9 Net-_U6-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_and
+U14 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U12-Pad2_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ d_inverter
+U7 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U6-Pad2_ d_nand
+U11 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U11-Pad3_ d_nor
+U15 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U14-Pad2_ d_nand
+U2 Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter
+X2 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U24-Pad1_ 4_and
+U26 Net-_U22-Pad1_ Net-_U11-Pad3_ Net-_U26-Pad3_ d_and
+X3 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U10-Pad2_ Net-_U24-Pad2_ 3_and
+X1 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U16-Pad1_ 3_and
+U22 Net-_U22-Pad1_ Net-_U21-Pad2_ Net-_U19-Pad2_ d_and
+U21 Net-_U20-Pad3_ Net-_U21-Pad2_ d_inverter
+U17 Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U16-Pad2_ d_and
+U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_nor
+U25 Net-_U24-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_nor
+U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad9_ d_xor
+U18 Net-_U16-Pad3_ Net-_U11-Pad3_ Net-_U18-Pad3_ d_nor
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U19 Net-_U18-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad2_ d_xor
+U12 Net-_U10-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad6_ d_xor
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir.out
new file mode 100644
index 000000000..c55334e36
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir.out
@@ -0,0 +1,165 @@
+.title kicad schematic
+
+.include 3_and.sub
+.include 5_and.sub
+.include 4_and.sub
+* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u33-pad3_ d_nor
+* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u34-pad2_ d_nor
+* u37 net-_u34-pad3_ net-_u28-pad3_ net-_u1-pad14_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ gnd net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ gnd net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+* u34 net-_u33-pad3_ net-_u34-pad2_ net-_u34-pad3_ d_nor
+* u32 net-_u1-pad1_ net-_u1-pad16_ net-_u31-pad2_ d_nand
+* u28 net-_u1-pad1_ net-_u1-pad16_ net-_u28-pad3_ d_nor
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u1-pad15_ d_xor
+* u27 net-_u26-pad3_ net-_u20-pad3_ net-_u25-pad2_ d_nor
+* u36 net-_u31-pad2_ net-_u20-pad3_ net-_u35-pad2_ d_and
+x6 net-_u22-pad1_ net-_u31-pad2_ net-_u11-pad3_ net-_u35-pad1_ 3_and
+* u31 net-_u30-pad2_ net-_u31-pad2_ net-_u29-pad2_ d_and
+* u30 net-_u28-pad3_ net-_u30-pad2_ d_inverter
+x5 net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u10-pad2_ net-_u33-pad2_ 4_and
+x4 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u33-pad1_ 5_and
+* u20 net-_u1-pad3_ net-_u1-pad4_ net-_u20-pad3_ d_nor
+* u23 net-_u1-pad3_ net-_u1-pad4_ net-_u22-pad1_ d_nand
+* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ net-_u4-pad2_ d_and
+* u9 net-_u6-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and
+* u14 net-_u13-pad2_ net-_u14-pad2_ net-_u12-pad2_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ d_inverter
+* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u10-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad11_ net-_u6-pad2_ d_nand
+* u11 net-_u1-pad8_ net-_u1-pad7_ net-_u11-pad3_ d_nor
+* u15 net-_u1-pad8_ net-_u1-pad7_ net-_u14-pad2_ d_nand
+* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter
+x2 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u24-pad1_ 4_and
+* u26 net-_u22-pad1_ net-_u11-pad3_ net-_u26-pad3_ d_and
+x3 net-_u14-pad2_ net-_u22-pad1_ net-_u10-pad2_ net-_u24-pad2_ 3_and
+x1 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u16-pad1_ 3_and
+* u22 net-_u22-pad1_ net-_u21-pad2_ net-_u19-pad2_ d_and
+* u21 net-_u20-pad3_ net-_u21-pad2_ d_inverter
+* u17 net-_u14-pad2_ net-_u10-pad2_ net-_u16-pad2_ d_and
+* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor
+* u25 net-_u24-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_nor
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad9_ d_xor
+* u18 net-_u16-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u19 net-_u18-pad3_ net-_u19-pad2_ net-_u1-pad2_ d_xor
+* u12 net-_u10-pad3_ net-_u12-pad2_ net-_u1-pad6_ d_xor
+a1 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a2 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u34-pad2_ u35
+a3 [net-_u34-pad3_ net-_u28-pad3_ ] net-_u1-pad14_ u37
+a4 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u34-pad3_ u34
+a5 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u31-pad2_ u32
+a6 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u28-pad3_ u28
+a7 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u1-pad15_ u29
+a8 [net-_u26-pad3_ net-_u20-pad3_ ] net-_u25-pad2_ u27
+a9 [net-_u31-pad2_ net-_u20-pad3_ ] net-_u35-pad2_ u36
+a10 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u29-pad2_ u31
+a11 net-_u28-pad3_ net-_u30-pad2_ u30
+a12 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u20-pad3_ u20
+a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u22-pad1_ u23
+a14 net-_u2-pad2_ net-_u3-pad2_ u3
+a15 net-_u10-pad2_ net-_u5-pad2_ u5
+a16 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u4-pad2_ u6
+a17 [net-_u6-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u9
+a18 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u12-pad2_ u14
+a19 net-_u11-pad3_ net-_u13-pad2_ u13
+a20 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u10-pad2_ u7
+a21 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u6-pad2_ u8
+a22 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u11-pad3_ u11
+a23 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u14-pad2_ u15
+a24 net-_u1-pad13_ net-_u2-pad2_ u2
+a25 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u26-pad3_ u26
+a26 [net-_u22-pad1_ net-_u21-pad2_ ] net-_u19-pad2_ u22
+a27 net-_u20-pad3_ net-_u21-pad2_ u21
+a28 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u16-pad2_ u17
+a29 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a30 [net-_u24-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
+a31 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u1-pad9_ u4
+a32 [net-_u16-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18
+a33 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a34 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a35 [net-_u18-pad3_ net-_u19-pad2_ ] net-_u1-pad2_ u19
+a36 [net-_u10-pad3_ net-_u12-pad2_ ] net-_u1-pad6_ u12
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u19 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir.txt b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir.txt
new file mode 100644
index 000000000..44e09960a
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.cir.txt
@@ -0,0 +1,46 @@
+.title KiCad schematic
+U33 Net-_U33-Pad1_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_nor
+U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U34-Pad2_ d_nor
+U37 Net-_U34-Pad3_ Net-_U28-Pad3_ Net-_U1-Pad14_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ GND Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ GND Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+U34 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U34-Pad3_ d_nor
+U32 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U31-Pad2_ d_nand
+U28 Net-_U1-Pad1_ Net-_U1-Pad16_ Net-_U28-Pad3_ d_nor
+U29 Net-_U25-Pad3_ Net-_U29-Pad2_ Net-_U1-Pad15_ d_xor
+U27 Net-_U26-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad2_ d_nor
+U36 Net-_U31-Pad2_ Net-_U20-Pad3_ Net-_U35-Pad2_ d_and
+X6 Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U11-Pad3_ Net-_U35-Pad1_ 3_and
+U31 Net-_U30-Pad2_ Net-_U31-Pad2_ Net-_U29-Pad2_ d_and
+U30 Net-_U28-Pad3_ Net-_U30-Pad2_ d_inverter
+X5 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U10-Pad2_ Net-_U33-Pad2_ 4_and
+X4 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U33-Pad1_ 5_and
+U20 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U20-Pad3_ d_nor
+U23 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U22-Pad1_ d_nand
+U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter
+U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter
+U6 Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ d_and
+U9 Net-_U6-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_and
+U14 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U12-Pad2_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ d_inverter
+U7 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U6-Pad2_ d_nand
+U11 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U11-Pad3_ d_nor
+U15 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U14-Pad2_ d_nand
+U2 Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter
+X2 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U24-Pad1_ 4_and
+U26 Net-_U22-Pad1_ Net-_U11-Pad3_ Net-_U26-Pad3_ d_and
+X3 Net-_U14-Pad2_ Net-_U22-Pad1_ Net-_U10-Pad2_ Net-_U24-Pad2_ 3_and
+X1 Net-_U2-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ Net-_U16-Pad1_ 3_and
+U22 Net-_U22-Pad1_ Net-_U21-Pad2_ Net-_U19-Pad2_ d_and
+U21 Net-_U20-Pad3_ Net-_U21-Pad2_ d_inverter
+U17 Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U16-Pad2_ d_and
+U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_nor
+U25 Net-_U24-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_nor
+U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad9_ d_xor
+U18 Net-_U16-Pad3_ Net-_U11-Pad3_ Net-_U18-Pad3_ d_nor
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nor
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U19 Net-_U18-Pad3_ Net-_U19-Pad2_ Net-_U1-Pad2_ d_xor
+U12 Net-_U10-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad6_ d_xor
+.end
+
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_prl b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_prl
new file mode 100644
index 000000000..b4533b173
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_prl
@@ -0,0 +1,75 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "",
+    "auto_track_width": true,
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
+      13,
+      14,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "74LS83.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_pro b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_pro
new file mode 100644
index 000000000..2a12c62ec
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_pro
@@ -0,0 +1,294 @@
+{
+  "board": {
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "74LS83.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Spice",
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "04eb507f-10b6-4ac6-bb2a-65616eb44f33",
+      ""
+    ]
+  ],
+  "text_variables": {}
+}
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_sch b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_sch
new file mode 100644
index 000000000..b940b23c0
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.kicad_sch
@@ -0,0 +1,3412 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 04eb507f-10b6-4ac6-bb2a-65616eb44f33)
+
+  (paper "A2")
+
+  (lib_symbols
+    (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_and" (id 1) (at 1.27 2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_and_0_1"
+        (polyline
+          (pts
+            (xy 3.81 -1.27)
+            (xy -6.35 -1.27)
+            (xy -6.35 3.81)
+            (xy 3.81 3.81)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_and_1_1"
+        (pin input line (at -11.43 2.54 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -11.43 0 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin output line (at 11.43 1.27 180) (length 5.08)
+          (name "OUT" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 -2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_inverter" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 -1.27 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_inverter_0_1"
+        (polyline
+          (pts
+            (xy -2.54 1.27)
+            (xy -2.54 -1.27)
+            (xy 2.54 0)
+            (xy -2.54 1.27)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_inverter_1_1"
+        (pin input line (at -7.62 0 0) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin output inverted (at 7.62 0 180) (length 5.08)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_nand" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_nand" (id 1) (at 1.27 2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_nand_0_1"
+        (polyline
+          (pts
+            (xy 3.81 -1.27)
+            (xy -6.35 -1.27)
+            (xy -6.35 3.81)
+            (xy 3.81 3.81)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "d_nand_1_1"
+        (pin input line (at -11.43 2.54 0) (length 5.08)
+          (name "IN1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin input line (at -11.43 0 0) (length 5.08)
+          (name "IN2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin output inverted (at 11.43 1.27 180) (length 5.08)
+          (name "OUT" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Digital:d_nor" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Value" "d_nor" (id 1) (at 1.27 2.54 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "d_nor_0_1"
+        (arc (start -6.35 -1.27) (mid -5.7504 1.27) (end -6.35 3.81)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy -6.35 -1.27)
+            (xy 3.81 -1.27)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy -6.35 3.81)
+            (xy 3.81 3.81)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
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+    (pin "2" (uuid 1cf1c3f6-c946-4f08-a535-09e1fb5efe7d))
+    (pin "3" (uuid 2cc58c4c-b5da-4455-a823-10258c086065))
+  )
+
+  (symbol (lib_id "eSim_Miscellaneous:PORT") (at 105.41 51.435 90) (mirror x) (unit 10)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f8f0ae3b-691e-467a-a3ac-7ee5926adc70)
+    (property "Reference" "U1" (id 0) (at 100.33 52.07 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Value" "PORT" (id 1) (at 102.87 52.07 0)
+      (effects (font (size 0.762 0.762)))
+    )
+    (property "Footprint" "" (id 2) (at 105.41 51.435 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (property "Datasheet" "" (id 3) (at 105.41 51.435 0)
+      (effects (font (size 1.524 1.524)))
+    )
+    (pin "1" (uuid 32650968-e987-4b78-ac9d-c8ec5ae580b0))
+    (pin "2" (uuid 5284aa48-cfe4-43e8-a392-f54d89cf1682))
+    (pin "3" (uuid 33c324b1-d268-4c51-9d14-882f890d9032))
+    (pin "4" (uuid c57c2172-af89-458f-a0b5-0e2a39f8027a))
+    (pin "5" (uuid dddab577-33a7-416f-a099-ba55376f90c1))
+    (pin "6" (uuid b78c2e03-d676-47c9-b803-0846df700e69))
+    (pin "7" (uuid 51adf4a0-e6ea-4fc2-b1e8-e0abff628f6e))
+    (pin "8" (uuid 06fa291b-dc3c-4ab1-84b2-9c7071a760b5))
+    (pin "9" (uuid 3f8cb50f-3d4a-491b-8418-cacda346f90d))
+    (pin "10" (uuid 6a421cf4-762f-4ea7-90a7-9d97a50c81f1))
+    (pin "11" (uuid 0259b869-0be5-4c53-9a11-4b2e9f4cfb70))
+    (pin "12" (uuid a7073c61-a27e-4ba8-9efe-9a7fd0573fa2))
+    (pin "13" (uuid 4749e5be-0f02-44a9-aa58-dec82c7f90f1))
+    (pin "14" (uuid 77d9656a-a024-4f08-b93e-f122a755398a))
+    (pin "15" (uuid 26dd4307-8383-47f9-9b2f-ca73628b7771))
+    (pin "16" (uuid d6de67ca-2a8f-42e1-9b7f-f1b2c04a93ef))
+    (pin "17" (uuid 0f9bea7a-4d0f-4ca6-b5bd-8db2a572206f))
+    (pin "18" (uuid 2e44977a-0735-46a4-be5f-fc4373aa022a))
+    (pin "19" (uuid 0eb7e9ed-5854-4a85-8580-8bbef03b2b00))
+    (pin "20" (uuid 1f1cb59c-a80e-4abf-abe4-02e53648338f))
+    (pin "21" (uuid 8a13047b-216a-4fc8-99a3-b5ea6fea9bca))
+    (pin "22" (uuid 2a19852d-8716-4909-9c5a-253fa1713d8c))
+    (pin "23" (uuid 7bbfec7d-6d8c-4b2f-97c8-20015c1f990a))
+    (pin "24" (uuid ca31cb7b-c790-4e28-abe2-c4dc302720e1))
+    (pin "25" (uuid e86e4376-c7e2-434a-b47e-8ed97fadfc08))
+    (pin "26" (uuid 3459991f-887c-4478-8ef7-6edf8c90ea86))
+  )
+
+  (sheet_instances
+    (path "/" (page "1"))
+  )
+
+  (symbol_instances
+    (path "/d7f2f3c0-4623-4d11-912c-9cb83a9d10d0"
+      (reference "#PWR01") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/6b646d19-3391-4d18-a2ab-cbf06135855f"
+      (reference "#PWR02") (unit 1) (value "eSim_GND") (footprint "")
+    )
+    (path "/ae442690-d7cc-4547-aaab-a987b9aa9079"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/e8661895-adf8-47c4-b5b8-03926bce2898"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/18be16c0-1c98-44c5-88ed-dd82f69f9ef6"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/5242ae5b-4fd7-4187-a463-c111c68b083a"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/3883f092-da1a-463c-8233-6051c7c0c37c"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/8ca72e6d-0cda-4f16-a26e-bd6354f9d0d9"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/ecf86bd5-b1c7-4ab5-876e-8d618506c771"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/54e6305f-d5eb-468f-bec4-99ec4395204b"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+    (path "/0e313b7b-0e0b-4233-a9c3-f96e3c8e359c"
+      (reference "U1") (unit 9) (value "PORT") (footprint "")
+    )
+    (path "/f8f0ae3b-691e-467a-a3ac-7ee5926adc70"
+      (reference "U1") (unit 10) (value "PORT") (footprint "")
+    )
+    (path "/2267fe2a-e08a-41c8-b850-0bbaa38fd704"
+      (reference "U1") (unit 11) (value "PORT") (footprint "")
+    )
+    (path "/6271bebe-7945-4185-bd69-6e09d2ea8a67"
+      (reference "U1") (unit 12) (value "PORT") (footprint "")
+    )
+    (path "/0a2f39a2-ecfd-410e-9515-073f89951795"
+      (reference "U1") (unit 13) (value "PORT") (footprint "")
+    )
+    (path "/b104f17b-38dd-46c2-82a1-a1f005794857"
+      (reference "U1") (unit 14) (value "PORT") (footprint "")
+    )
+    (path "/49a82764-481c-46d4-80a6-b0dc04926da3"
+      (reference "U1") (unit 15) (value "PORT") (footprint "")
+    )
+    (path "/c2490a11-76b6-4eb9-9941-d20bfa5e71fd"
+      (reference "U1") (unit 16) (value "PORT") (footprint "")
+    )
+    (path "/727be04b-5134-43c1-b3e1-f6faf0709bee"
+      (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/06f308d7-5ec0-48bd-a96c-736e222ec49f"
+      (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/6aeb3039-9600-49a4-931e-5cf6927144e1"
+      (reference "U4") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/e619ab85-199d-43f9-b90b-df7047f9f783"
+      (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c4e0ed43-12be-42f2-b04e-48ec6bd4279d"
+      (reference "U6") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/13208c70-96e7-49a3-8d14-bf761d010a23"
+      (reference "U7") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b507ef94-5957-42fe-8f96-f9d1403a7906"
+      (reference "U8") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/e6ac8b26-37ca-4e7b-bdb6-e3f57eabd794"
+      (reference "U9") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/763994ad-e490-419b-bd49-a61a3d9be9a9"
+      (reference "U10") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/1832402b-a42a-474e-9b9c-3fd567f9aa47"
+      (reference "U11") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/ee4ea1c7-a11c-44d1-97e7-f14f190a6dfa"
+      (reference "U12") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/b3e66f2e-6261-4f34-9914-6e272e580393"
+      (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c3f2223f-2112-42a7-bf3b-c169b52908a5"
+      (reference "U14") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/d50258f8-e589-4fd6-88e2-4dcfe090b241"
+      (reference "U15") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/d6c668ed-885a-4454-8070-4f77f14cad96"
+      (reference "U16") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/3434dcc5-138b-434e-bde3-6bce90fa4161"
+      (reference "U17") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/da639c8b-d7b1-482e-901f-9306b138820d"
+      (reference "U18") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0f3cc159-c4b3-4992-b7c3-f796a6ce5d51"
+      (reference "U19") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/2ba7bd73-7e5d-4aad-ba02-1dd2e36a680d"
+      (reference "U20") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/7ebe236c-6131-48bf-bbf2-67c5800b677e"
+      (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/97308ba3-7b58-4b51-81fc-6ad40e79e425"
+      (reference "U22") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/59ef5793-620b-49ce-b3f7-7ec72a529fa4"
+      (reference "U23") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/ab05a71b-bd7a-4c82-bd95-cef7d908735d"
+      (reference "U24") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/a8578ddc-3d82-47b2-93ea-305326df9663"
+      (reference "U25") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b8e56fd6-a24a-4696-a8dd-27b17a23e740"
+      (reference "U26") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/e26a87c6-311f-4471-95f8-74c959587f75"
+      (reference "U27") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/b6528284-3aa5-4eec-b905-0d90a1563829"
+      (reference "U28") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/2ea9c543-bafe-4042-b3e1-2e64f1ace3e2"
+      (reference "U29") (unit 1) (value "d_xor") (footprint "")
+    )
+    (path "/9e8b7537-5043-469c-8efe-094a07628f75"
+      (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+    )
+    (path "/c5f4eaaa-1ed2-4f99-8676-c5801b211126"
+      (reference "U31") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/b5345862-baea-4554-b114-cfb064403df6"
+      (reference "U32") (unit 1) (value "d_nand") (footprint "")
+    )
+    (path "/91fcf55e-12be-4092-9f4b-c3f9f04366e5"
+      (reference "U33") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/0606497b-b65d-4bb4-9ac0-589c9826325e"
+      (reference "U34") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/63bf30f8-904b-49ad-805c-dc0a480197cd"
+      (reference "U35") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/d64dca26-00e0-417b-92df-467c4826c54a"
+      (reference "U36") (unit 1) (value "d_and") (footprint "")
+    )
+    (path "/0f31771f-c0b1-42fe-aef3-ed753c5d5f49"
+      (reference "U37") (unit 1) (value "d_nor") (footprint "")
+    )
+    (path "/c2b6327a-24c5-406f-b57a-1dc1ed0ec722"
+      (reference "X1") (unit 1) (value "3_and") (footprint "")
+    )
+    (path "/841c9ad9-e9a0-49e0-ab0a-3099f6d1fa5f"
+      (reference "X2") (unit 1) (value "4_and") (footprint "")
+    )
+    (path "/e12d2b3b-f2d6-4753-97c9-39227b96b7ee"
+      (reference "X3") (unit 1) (value "3_and") (footprint "")
+    )
+    (path "/406f8e83-48f8-4a57-8ebb-90aa656183f8"
+      (reference "X4") (unit 1) (value "5_and") (footprint "")
+    )
+    (path "/5dfe0b87-d843-4ebe-955d-61174908b9b6"
+      (reference "X5") (unit 1) (value "4_and") (footprint "")
+    )
+    (path "/c99ade31-1be4-4b27-8c9f-53d76bbf1ac2"
+      (reference "X6") (unit 1) (value "3_and") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.sub b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.sub
new file mode 100644
index 000000000..b81f13f64
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83.sub
@@ -0,0 +1,159 @@
+* Subcircuit 74LS83
+.subckt 74LS83 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ gnd net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ gnd net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ 
+.title kicad schematic
+.include 3_and.sub
+.include 5_and.sub
+.include 4_and.sub
+* u33 net-_u33-pad1_ net-_u33-pad2_ net-_u33-pad3_ d_nor
+* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u34-pad2_ d_nor
+* u37 net-_u34-pad3_ net-_u28-pad3_ net-_u1-pad14_ d_nor
+* u34 net-_u33-pad3_ net-_u34-pad2_ net-_u34-pad3_ d_nor
+* u32 net-_u1-pad1_ net-_u1-pad16_ net-_u31-pad2_ d_nand
+* u28 net-_u1-pad1_ net-_u1-pad16_ net-_u28-pad3_ d_nor
+* u29 net-_u25-pad3_ net-_u29-pad2_ net-_u1-pad15_ d_xor
+* u27 net-_u26-pad3_ net-_u20-pad3_ net-_u25-pad2_ d_nor
+* u36 net-_u31-pad2_ net-_u20-pad3_ net-_u35-pad2_ d_and
+x6 net-_u22-pad1_ net-_u31-pad2_ net-_u11-pad3_ net-_u35-pad1_ 3_and
+* u31 net-_u30-pad2_ net-_u31-pad2_ net-_u29-pad2_ d_and
+* u30 net-_u28-pad3_ net-_u30-pad2_ d_inverter
+x5 net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u10-pad2_ net-_u33-pad2_ 4_and
+x4 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u31-pad2_ net-_u33-pad1_ 5_and
+* u20 net-_u1-pad3_ net-_u1-pad4_ net-_u20-pad3_ d_nor
+* u23 net-_u1-pad3_ net-_u1-pad4_ net-_u22-pad1_ d_nand
+* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter
+* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ net-_u4-pad2_ d_and
+* u9 net-_u6-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and
+* u14 net-_u13-pad2_ net-_u14-pad2_ net-_u12-pad2_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ d_inverter
+* u7 net-_u1-pad10_ net-_u1-pad11_ net-_u10-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad11_ net-_u6-pad2_ d_nand
+* u11 net-_u1-pad8_ net-_u1-pad7_ net-_u11-pad3_ d_nor
+* u15 net-_u1-pad8_ net-_u1-pad7_ net-_u14-pad2_ d_nand
+* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter
+x2 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u22-pad1_ net-_u24-pad1_ 4_and
+* u26 net-_u22-pad1_ net-_u11-pad3_ net-_u26-pad3_ d_and
+x3 net-_u14-pad2_ net-_u22-pad1_ net-_u10-pad2_ net-_u24-pad2_ 3_and
+x1 net-_u2-pad2_ net-_u6-pad2_ net-_u14-pad2_ net-_u16-pad1_ 3_and
+* u22 net-_u22-pad1_ net-_u21-pad2_ net-_u19-pad2_ d_and
+* u21 net-_u20-pad3_ net-_u21-pad2_ d_inverter
+* u17 net-_u14-pad2_ net-_u10-pad2_ net-_u16-pad2_ d_and
+* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor
+* u25 net-_u24-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_nor
+* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad9_ d_xor
+* u18 net-_u16-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u19 net-_u18-pad3_ net-_u19-pad2_ net-_u1-pad2_ d_xor
+* u12 net-_u10-pad3_ net-_u12-pad2_ net-_u1-pad6_ d_xor
+a1 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u33-pad3_ u33
+a2 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u34-pad2_ u35
+a3 [net-_u34-pad3_ net-_u28-pad3_ ] net-_u1-pad14_ u37
+a4 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u34-pad3_ u34
+a5 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u31-pad2_ u32
+a6 [net-_u1-pad1_ net-_u1-pad16_ ] net-_u28-pad3_ u28
+a7 [net-_u25-pad3_ net-_u29-pad2_ ] net-_u1-pad15_ u29
+a8 [net-_u26-pad3_ net-_u20-pad3_ ] net-_u25-pad2_ u27
+a9 [net-_u31-pad2_ net-_u20-pad3_ ] net-_u35-pad2_ u36
+a10 [net-_u30-pad2_ net-_u31-pad2_ ] net-_u29-pad2_ u31
+a11 net-_u28-pad3_ net-_u30-pad2_ u30
+a12 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u20-pad3_ u20
+a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u22-pad1_ u23
+a14 net-_u2-pad2_ net-_u3-pad2_ u3
+a15 net-_u10-pad2_ net-_u5-pad2_ u5
+a16 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u4-pad2_ u6
+a17 [net-_u6-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u9
+a18 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u12-pad2_ u14
+a19 net-_u11-pad3_ net-_u13-pad2_ u13
+a20 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u10-pad2_ u7
+a21 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u6-pad2_ u8
+a22 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u11-pad3_ u11
+a23 [net-_u1-pad8_ net-_u1-pad7_ ] net-_u14-pad2_ u15
+a24 net-_u1-pad13_ net-_u2-pad2_ u2
+a25 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u26-pad3_ u26
+a26 [net-_u22-pad1_ net-_u21-pad2_ ] net-_u19-pad2_ u22
+a27 net-_u20-pad3_ net-_u21-pad2_ u21
+a28 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u16-pad2_ u17
+a29 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a30 [net-_u24-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
+a31 [net-_u3-pad2_ net-_u4-pad2_ ] net-_u1-pad9_ u4
+a32 [net-_u16-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18
+a33 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a34 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a35 [net-_u18-pad3_ net-_u19-pad2_ ] net-_u1-pad2_ u19
+a36 [net-_u10-pad3_ net-_u12-pad2_ ] net-_u1-pad6_ u12
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, Ngspice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, Ngspice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u19 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xor, Ngspice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74LS83
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Previous_Values.xml
new file mode 100644
index 000000000..1d915ac37
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model><u4 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u10 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u8 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u7><u11 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u11><u2 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u2><u9 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u9><u6 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u6><u16 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u14><u3 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u5><u15 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u15><u12 name="type">d_xor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u12><u18 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_xor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19><u22 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u26><u21 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_nor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u20><u23 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u23><u32 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u32><u28 name="type">d_nor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u27 name="type">d_nor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u27><u24 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u25><u29 name="type">d_xor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u29><u36 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u36><u30 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u31><u34 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u34><u35 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u35><u33 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u33><u37 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u37></model><devicemodel /><subcircuit><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.cir b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.cir
new file mode 100644
index 000000000..04adfaf4e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.cir
@@ -0,0 +1,28 @@
+.title KiCad schematic
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ adc_bridge_5
+U10 Net-_X1-Pad15_ Net-_U2-Pad3_ d_inverter
+U9 Net-_X1-Pad2_ Net-_U2-Pad1_ d_inverter
+X1 Net-_U1-Pad6_ Net-_X1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_v1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U2-Pad5_ Net-_U3-Pad8_ Net-_U3-Pad7_ GND Net-_U3-Pad6_ Net-_U2-Pad4_ Net-_X1-Pad15_ Net-_U3-Pad5_ 74LS83
+U4 S1 plot_v1
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ S3 S2 S4 C4 S1 dac_bridge_5
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4
+R2 GND C4 1k
+U6 S4 plot_v1
+U8 S3 plot_v1
+U7 S2 plot_v1
+U5 C4 plot_v1
+R5 GND S3 1k
+R4 GND S2 1k
+R3 GND S4 1k
+VA3 Net-_U1-Pad2_ GND DC
+VB3 Net-_U1-Pad3_ GND DC
+VA4 Net-_U1-Pad1_ GND DC
+v1 Net-_v1-Pad1_ GND 5
+VA2 Net-_U1-Pad5_ GND DC
+VB2 Net-_U1-Pad4_ GND DC
+R1 GND S1 1k
+VB4 Net-_U3-Pad1_ GND DC
+VC0 Net-_U3-Pad2_ GND DC
+VB1 Net-_U3-Pad3_ GND DC
+VA1 Net-_U3-Pad4_ GND DC
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.cir.out b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.cir.out
new file mode 100644
index 000000000..312bbabdd
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.cir.out
@@ -0,0 +1,58 @@
+.title kicad schematic
+
+.include 74LS83.sub
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ adc_bridge_5
+* u10 net-_x1-pad15_ net-_u2-pad3_ d_inverter
+* u9 net-_x1-pad2_ net-_u2-pad1_ d_inverter
+x1 net-_u1-pad6_ net-_x1-pad2_ net-_u1-pad7_ net-_u1-pad8_ net-_v1-pad1_ net-_u2-pad2_ net-_u1-pad9_ net-_u1-pad10_ net-_u2-pad5_ net-_u3-pad8_ net-_u3-pad7_ gnd net-_u3-pad6_ net-_u2-pad4_ net-_x1-pad15_ net-_u3-pad5_ 74LS83
+* u4 s1 plot_v1
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ s3 s2 s4 c4 s1 dac_bridge_5
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
+r2 gnd c4 1k
+* u6 s4 plot_v1
+* u8 s3 plot_v1
+* u7 s2 plot_v1
+* u5 c4 plot_v1
+r5 gnd s3 1k
+r4 gnd s2 1k
+r3 gnd s4 1k
+va3 net-_u1-pad2_ gnd  dc 0
+vb3 net-_u1-pad3_ gnd  dc 5
+va4 net-_u1-pad1_ gnd  dc 0
+v1 net-_v1-pad1_ gnd 5
+va2 net-_u1-pad5_ gnd  dc 0
+vb2 net-_u1-pad4_ gnd  dc 5
+r1 gnd s1 1k
+vb4 net-_u3-pad1_ gnd  dc 5
+vc0 net-_u3-pad2_ gnd  dc 5
+vb1 net-_u3-pad3_ gnd  dc 5
+va1 net-_u3-pad4_ gnd  dc 0
+a1 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] u1
+a2 net-_x1-pad15_ net-_u2-pad3_ u10
+a3 net-_x1-pad2_ net-_u2-pad1_ u9
+a4 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ ] [s3 s2 s4 c4 s1 ] u2
+a5 [net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
+* Schematic Name:                             adc_bridge_5, Ngspice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_5, Ngspice Name: dac_bridge
+.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, Ngspice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 5e-00 100e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(s1)
+plot v(s4)
+plot v(s3)
+plot v(s2)
+plot v(c4)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.kicad_sch b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.kicad_sch
new file mode 100644
index 000000000..bf08fdc3e
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.kicad_sch
@@ -0,0 +1,1626 @@
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diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.proj b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.proj
new file mode 100644
index 000000000..219749add
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.proj
@@ -0,0 +1 @@
+schematicFile 74LS83_Test_Circuit1.kicad_sch
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.raw b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.raw
new file mode 100644
index 000000000..6958fccf1
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1.raw
@@ -0,0 +1,1868 @@
+Title: kicad schematic
+Date: Sat Nov 29 22:14:28  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 31
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(c4)	voltage
+	2	v(s3)	voltage
+	3	v(s2)	voltage
+	4	v(s4)	voltage
+	5	v(net-_u1-pad2_)	voltage
+	6	v(net-_u1-pad3_)	voltage
+	7	v(net-_u1-pad1_)	voltage
+	8	v(net-_v1-pad1_)	voltage
+	9	v(net-_u1-pad5_)	voltage
+	10	v(net-_u1-pad4_)	voltage
+	11	v(s1)	voltage
+	12	v(net-_u3-pad1_)	voltage
+	13	v(net-_u3-pad2_)	voltage
+	14	v(net-_u3-pad3_)	voltage
+	15	v(net-_u3-pad4_)	voltage
+	16	i(va1)	current
+	17	i(vb1)	current
+	18	i(vc0)	current
+	19	i(vb4)	current
+	20	i(vb2)	current
+	21	i(va2)	current
+	22	i(v1)	current
+	23	i(va4)	current
+	24	i(vb3)	current
+	25	i(va3)	current
+	26	i(a4)	current
+	27	i(a4)	current
+	28	i(a4)	current
+	29	i(a4)	current
+	30	i(a4)	current
+Values:
+0		0.000000000000000e+00
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diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1_Previous_Values.xml b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1_Previous_Values.xml
new file mode 100644
index 000000000..d52970e6b
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/74LS83_Test_Circuit1_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><vb3 name="Source type">dc<field1 name="Value">5</field1></vb3><va3 name="Source type">dc<field1 name="Value">0</field1></va3><va4 name="Source type">dc<field1 name="Value">0</field1></va4><v1 name="Source type">5</v1><va2 name="Source type">dc<field1 name="Value">0</field1></va2><vb2 name="Source type">dc<field1 name="Value">5</field1></vb2><vb4 name="Source type">dc<field1 name="Value">5</field1></vb4><vb1 name="Source type">dc<field1 name="Value">5</field1></vb1><vc0 name="Source type">dc<field1 name="Value">5</field1></vc0><va1 name="Source type">dc<field1 name="Value">0</field1></va1></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u2><u3 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u3><u10 name="type">d_inverter<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_inverter<field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter Input Load (default=1.0e-12)" /></u9></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\74LS83</field></x1></subcircuit><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/analysis b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/analysis
new file mode 100644
index 000000000..ef45c15d2
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/74LS83_Test_Circuit/74LS83_Test_Circuit1/analysis
@@ -0,0 +1 @@
+.tran 5e-00 100e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/IC74LS83/74LS83/analysis b/library/SubcircuitLibrary/IC74LS83/74LS83/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/IC74LS83/74LS83/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/LM567.cir b/library/SubcircuitLibrary/ICLM567/LM567/LM567.cir
new file mode 100644
index 000000000..2ef275a70
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/LM567.cir
@@ -0,0 +1,112 @@
+.title KiCad schematic
+U1 Net-_Q54-Pad2_ Net-_Q30-Pad1_ Net-_Q32-Pad2_ V+ A Net-_Q9-Pad2_ GND Net-_Q61-Pad1_ PORT
+R3 Net-_Q6-Pad3_ V+ 47K
+Q1 V+ Net-_Q1-Pad2_ A eSim_NPN
+Q4 V+ Net-_Q4-Pad2_ A eSim_NPN
+R1 Net-_Q1-Pad2_ V+ 47K
+R2 Net-_Q4-Pad2_ Net-_Q2-Pad2_ 10K
+Q6 Net-_Q2-Pad2_ D Net-_Q6-Pad3_ eSim_PNP
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ GND eSim_NPN
+Q11 A A Net-_Q11-Pad3_ eSim_NPN
+R4 Net-_Q12-Pad1_ Net-_Q11-Pad3_ 47K
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ GND eSim_NPN
+R12 Net-_Q19-Pad3_ V+ 2.2K
+Q19 GND Net-_Q16-Pad1_ Net-_Q19-Pad3_ eSim_PNP
+R7 Net-_Q16-Pad1_ V+ 2.2K
+Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN
+Q20 Net-_Q16-Pad3_ B Net-_Q20-Pad3_ eSim_NPN
+R10 GND Net-_Q20-Pad3_ 10K
+Q22 Net-_Q22-Pad1_ Net-_Q22-Pad1_ Net-_Q16-Pad1_ eSim_NPN
+R11 GND Net-_Q25-Pad3_ 2.2K
+Q18 E Net-_Q10-Pad1_ Net-_Q18-Pad3_ eSim_NPN
+Q5 Net-_Q2-Pad2_ Net-_Q12-Pad1_ GND eSim_NPN
+Q3 Net-_Q1-Pad2_ Net-_Q2-Pad2_ GND eSim_NPN
+Q7 Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_Q10-Pad2_ eSim_NPN
+Q8 Net-_Q10-Pad2_ Net-_Q10-Pad2_ GND eSim_NPN
+Q2 A Net-_Q2-Pad2_ GND eSim_NPN
+R5 Net-_Q13-Pad1_ V+ 22K
+Q13 Net-_Q13-Pad1_ Net-_Q10-Pad1_ Net-_Q13-Pad3_ eSim_NPN
+Q14 Net-_Q13-Pad3_ B Net-_Q14-Pad3_ eSim_NPN
+Q9 V+ Net-_Q9-Pad2_ Net-_Q10-Pad1_ eSim_NPN
+R6 GND Net-_Q14-Pad3_ 10K
+R9 E Net-_R14-Pad1_ 10K
+Q15 Net-_Q12-Pad2_ Net-_Q13-Pad1_ Net-_Q15-Pad3_ eSim_PNP
+Q21 GND Net-_Q17-Pad3_ Net-_Q15-Pad3_ eSim_PNP
+R8 Net-_Q15-Pad3_ V+ 22K
+Q17 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q17-Pad3_ eSim_NPN
+Q23 Net-_Q17-Pad3_ Net-_Q23-Pad2_ Net-_Q13-Pad3_ eSim_NPN
+R13 Net-_Q17-Pad3_ V+ 22K
+Q46 D D Net-_Q46-Pad3_ eSim_PNP
+R36 Net-_Q42-Pad1_ Net-_Q34-Pad2_ 21K
+R41 GND Net-_Q47-Pad3_ 2.2K
+Q47 B B Net-_Q47-Pad3_ eSim_NPN
+Q56 Net-_Q52-Pad3_ B Net-_Q56-Pad3_ eSim_NPN
+R45 GND Net-_Q56-Pad3_ 10K
+R40 B D 2.2K
+Q58 Net-_Q57-Pad3_ Net-_Q32-Pad3_ Net-_Q52-Pad3_ eSim_NPN
+Q52 Net-_Q51-Pad3_ Net-_Q38-Pad3_ Net-_Q52-Pad3_ eSim_NPN
+R48 GND Net-_Q60-Pad3_ 4.7K
+Q60 Net-_Q60-Pad1_ Net-_Q50-Pad1_ Net-_Q60-Pad3_ eSim_NPN
+R47 Net-_Q60-Pad1_ V+ 4.7K
+Q61 Net-_Q61-Pad1_ Net-_Q60-Pad3_ GND eSim_NPN
+Q43 C C Net-_Q43-Pad3_ eSim_NPN
+R30 Net-_Q33-Pad1_ Net-_Q38-Pad3_ 33K
+Q42 Net-_Q42-Pad1_ Net-_Q42-Pad1_ C eSim_NPN
+Q44 Net-_Q43-Pad3_ Net-_Q43-Pad3_ GND eSim_NPN
+Q24 Net-_Q19-Pad3_ Net-_Q22-Pad1_ Net-_Q12-Pad1_ eSim_PNP
+Q27 Net-_Q22-Pad1_ Net-_Q27-Pad2_ Net-_Q16-Pad3_ eSim_NPN
+R20 GND Net-_Q27-Pad2_ 4.7K
+R19 Net-_Q27-Pad2_ Net-_Q26-Pad2_ 4.7K
+Q33 Net-_Q33-Pad1_ B Net-_Q33-Pad3_ eSim_NPN
+R25 GND Net-_Q33-Pad3_ 4.7K
+R23 A Net-_Q30-Pad2_ 4.7K
+R27 Net-_Q30-Pad2_ Net-_Q34-Pad2_ 4.7K
+Q32 Net-_Q30-Pad3_ Net-_Q32-Pad2_ Net-_Q32-Pad3_ eSim_NPN
+R24 Net-_Q33-Pad1_ Net-_Q32-Pad3_ 33K
+R16 Net-_Q22-Pad1_ V+ 2.2K
+Q25 Net-_Q18-Pad3_ B Net-_Q25-Pad3_ eSim_NPN
+Q26 F Net-_Q26-Pad2_ Net-_Q18-Pad3_ eSim_NPN
+R33 Net-_Q38-Pad2_ Net-_Q42-Pad1_ 21K
+R34 Net-_Q32-Pad2_ Net-_Q42-Pad1_ 21K
+Q38 Net-_Q37-Pad3_ Net-_Q38-Pad2_ Net-_Q38-Pad3_ eSim_NPN
+R31 Net-_Q35-Pad2_ V+ 47K
+R28 Net-_Q36-Pad1_ Net-_Q35-Pad3_ 10K
+R32 GND Net-_Q39-Pad3_ 10K
+Q39 Net-_Q35-Pad2_ B Net-_Q39-Pad3_ eSim_NPN
+Q31 V+ Net-_Q30-Pad1_ Net-_Q31-Pad3_ eSim_NPN
+Q35 Net-_Q28-Pad1_ Net-_Q35-Pad2_ Net-_Q35-Pad3_ eSim_NPN
+Q36 Net-_Q36-Pad1_ B Net-_Q36-Pad3_ eSim_NPN
+R29 GND Net-_Q36-Pad3_ 10K
+Q40 V+ Net-_Q30-Pad2_ Net-_Q37-Pad3_ eSim_NPN
+Q37 Net-_Q30-Pad1_ Net-_Q34-Pad2_ Net-_Q37-Pad3_ eSim_NPN
+R38 Net-_Q48-Pad3_ Net-_Q41-Pad3_ 21K
+Q41 Net-_Q41-Pad1_ Net-_Q35-Pad2_ Net-_Q41-Pad3_ eSim_NPN
+Q34 V+ Net-_Q34-Pad2_ Net-_Q30-Pad3_ eSim_NPN
+R35 Net-_Q34-Pad2_ V+ 21K
+R39 Net-_Q46-Pad3_ V+ 21K
+R22 Net-_Q30-Pad1_ V+ 10K
+R17 Net-_Q28-Pad1_ V+ 10K
+Q30 Net-_Q30-Pad1_ Net-_Q30-Pad2_ Net-_Q30-Pad3_ eSim_NPN
+R15 F Net-_R14-Pad1_ 10K
+Q29 Net-_Q28-Pad3_ Net-_Q29-Pad2_ Net-_Q23-Pad2_ eSim_NPN
+Q28 Net-_Q28-Pad1_ Net-_Q28-Pad1_ Net-_Q28-Pad3_ eSim_NPN
+R26 Net-_Q36-Pad1_ Net-_Q31-Pad3_ 10K
+R18 Net-_Q26-Pad2_ Net-_Q23-Pad2_ 10K
+R21 Net-_Q29-Pad2_ Net-_Q28-Pad3_ 100K
+R14 Net-_R14-Pad1_ V+ 10K
+Q54 Net-_Q50-Pad3_ Net-_Q54-Pad2_ Net-_Q53-Pad2_ eSim_NPN
+R46 Net-_Q54-Pad2_ V+ 4.7K
+Q48 Net-_Q41-Pad1_ Net-_Q41-Pad3_ Net-_Q48-Pad3_ eSim_NPN
+R44 Net-_Q48-Pad3_ Net-_Q53-Pad2_ 21K
+Q53 Net-_Q50-Pad3_ Net-_Q53-Pad2_ Net-_Q48-Pad3_ eSim_NPN
+R42 GND Net-_Q49-Pad3_ 10K
+Q49 Net-_Q48-Pad3_ C Net-_Q49-Pad3_ eSim_NPN
+Q57 V+ E Net-_Q57-Pad3_ eSim_NPN
+Q59 Net-_Q54-Pad2_ F Net-_Q57-Pad3_ eSim_NPN
+Q55 Net-_Q54-Pad2_ E Net-_Q51-Pad3_ eSim_NPN
+Q51 V+ F Net-_Q51-Pad3_ eSim_NPN
+Q45 Net-_Q41-Pad1_ Net-_Q41-Pad1_ Net-_Q45-Pad3_ eSim_PNP
+R37 Net-_Q45-Pad3_ V+ 47K
+R43 Net-_Q50-Pad3_ V+ 47K
+Q50 Net-_Q50-Pad1_ Net-_Q41-Pad1_ Net-_Q50-Pad3_ eSim_PNP
+.end
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/LM567.cir.out b/library/SubcircuitLibrary/ICLM567/LM567/LM567.cir.out
new file mode 100644
index 000000000..3d89817b5
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/LM567.cir.out
@@ -0,0 +1,123 @@
+.title kicad schematic
+
+.include NPN.lib
+.include PNP.lib
+* u1 net-_q54-pad2_ net-_q30-pad1_ net-_q32-pad2_ v+ a net-_q9-pad2_ gnd net-_q61-pad1_ port
+r3 net-_q6-pad3_ v+ 47k
+q1 v+ net-_q1-pad2_ a Q2N2222
+q4 v+ net-_q4-pad2_ a Q2N2222
+r1 net-_q1-pad2_ v+ 47k
+r2 net-_q4-pad2_ net-_q2-pad2_ 10k
+q6 net-_q2-pad2_ d net-_q6-pad3_ Q2N2907A
+q10 net-_q10-pad1_ net-_q10-pad2_ gnd Q2N2222
+q11 a a net-_q11-pad3_ Q2N2222
+r4 net-_q12-pad1_ net-_q11-pad3_ 47k
+q12 net-_q12-pad1_ net-_q12-pad2_ gnd Q2N2222
+r12 net-_q19-pad3_ v+ 2.2k
+q19 gnd net-_q16-pad1_ net-_q19-pad3_ Q2N2907A
+r7 net-_q16-pad1_ v+ 2.2k
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
+q20 net-_q16-pad3_ b net-_q20-pad3_ Q2N2222
+r10 gnd net-_q20-pad3_ 10k
+q22 net-_q22-pad1_ net-_q22-pad1_ net-_q16-pad1_ Q2N2222
+r11 gnd net-_q25-pad3_ 2.2k
+q18 e net-_q10-pad1_ net-_q18-pad3_ Q2N2222
+q5 net-_q2-pad2_ net-_q12-pad1_ gnd Q2N2222
+q3 net-_q1-pad2_ net-_q2-pad2_ gnd Q2N2222
+q7 net-_q2-pad2_ net-_q2-pad2_ net-_q10-pad2_ Q2N2222
+q8 net-_q10-pad2_ net-_q10-pad2_ gnd Q2N2222
+q2 a net-_q2-pad2_ gnd Q2N2222
+r5 net-_q13-pad1_ v+ 22k
+q13 net-_q13-pad1_ net-_q10-pad1_ net-_q13-pad3_ Q2N2222
+q14 net-_q13-pad3_ b net-_q14-pad3_ Q2N2222
+q9 v+ net-_q9-pad2_ net-_q10-pad1_ Q2N2222
+r6 gnd net-_q14-pad3_ 10k
+r9 e net-_r14-pad1_ 10k
+q15 net-_q12-pad2_ net-_q13-pad1_ net-_q15-pad3_ Q2N2907A
+q21 gnd net-_q17-pad3_ net-_q15-pad3_ Q2N2907A
+r8 net-_q15-pad3_ v+ 22k
+q17 net-_q13-pad1_ net-_q13-pad1_ net-_q17-pad3_ Q2N2222
+q23 net-_q17-pad3_ net-_q23-pad2_ net-_q13-pad3_ Q2N2222
+r13 net-_q17-pad3_ v+ 22k
+q46 d d net-_q46-pad3_ Q2N2907A
+r36 net-_q42-pad1_ net-_q34-pad2_ 21k
+r41 gnd net-_q47-pad3_ 2.2k
+q47 b b net-_q47-pad3_ Q2N2222
+q56 net-_q52-pad3_ b net-_q56-pad3_ Q2N2222
+r45 gnd net-_q56-pad3_ 10k
+r40 b d 2.2k
+q58 net-_q57-pad3_ net-_q32-pad3_ net-_q52-pad3_ Q2N2222
+q52 net-_q51-pad3_ net-_q38-pad3_ net-_q52-pad3_ Q2N2222
+r48 gnd net-_q60-pad3_ 4.7k
+q60 net-_q60-pad1_ net-_q50-pad1_ net-_q60-pad3_ Q2N2222
+r47 net-_q60-pad1_ v+ 4.7k
+q61 net-_q61-pad1_ net-_q60-pad3_ gnd Q2N2222
+q43 c c net-_q43-pad3_ Q2N2222
+r30 net-_q33-pad1_ net-_q38-pad3_ 33k
+q42 net-_q42-pad1_ net-_q42-pad1_ c Q2N2222
+q44 net-_q43-pad3_ net-_q43-pad3_ gnd Q2N2222
+q24 net-_q19-pad3_ net-_q22-pad1_ net-_q12-pad1_ Q2N2907A
+q27 net-_q22-pad1_ net-_q27-pad2_ net-_q16-pad3_ Q2N2222
+r20 gnd net-_q27-pad2_ 4.7k
+r19 net-_q27-pad2_ net-_q26-pad2_ 4.7k
+q33 net-_q33-pad1_ b net-_q33-pad3_ Q2N2222
+r25 gnd net-_q33-pad3_ 4.7k
+r23 a net-_q30-pad2_ 4.7k
+r27 net-_q30-pad2_ net-_q34-pad2_ 4.7k
+q32 net-_q30-pad3_ net-_q32-pad2_ net-_q32-pad3_ Q2N2222
+r24 net-_q33-pad1_ net-_q32-pad3_ 33k
+r16 net-_q22-pad1_ v+ 2.2k
+q25 net-_q18-pad3_ b net-_q25-pad3_ Q2N2222
+q26 f net-_q26-pad2_ net-_q18-pad3_ Q2N2222
+r33 net-_q38-pad2_ net-_q42-pad1_ 21k
+r34 net-_q32-pad2_ net-_q42-pad1_ 21k
+q38 net-_q37-pad3_ net-_q38-pad2_ net-_q38-pad3_ Q2N2222
+r31 net-_q35-pad2_ v+ 47k
+r28 net-_q36-pad1_ net-_q35-pad3_ 10k
+r32 gnd net-_q39-pad3_ 10k
+q39 net-_q35-pad2_ b net-_q39-pad3_ Q2N2222
+q31 v+ net-_q30-pad1_ net-_q31-pad3_ Q2N2222
+q35 net-_q28-pad1_ net-_q35-pad2_ net-_q35-pad3_ Q2N2222
+q36 net-_q36-pad1_ b net-_q36-pad3_ Q2N2222
+r29 gnd net-_q36-pad3_ 10k
+q40 v+ net-_q30-pad2_ net-_q37-pad3_ Q2N2222
+q37 net-_q30-pad1_ net-_q34-pad2_ net-_q37-pad3_ Q2N2222
+r38 net-_q48-pad3_ net-_q41-pad3_ 21k
+q41 net-_q41-pad1_ net-_q35-pad2_ net-_q41-pad3_ Q2N2222
+q34 v+ net-_q34-pad2_ net-_q30-pad3_ Q2N2222
+r35 net-_q34-pad2_ v+ 21k
+r39 net-_q46-pad3_ v+ 21k
+r22 net-_q30-pad1_ v+ 10k
+r17 net-_q28-pad1_ v+ 10k
+q30 net-_q30-pad1_ net-_q30-pad2_ net-_q30-pad3_ Q2N2222
+r15 f net-_r14-pad1_ 10k
+q29 net-_q28-pad3_ net-_q29-pad2_ net-_q23-pad2_ Q2N2222
+q28 net-_q28-pad1_ net-_q28-pad1_ net-_q28-pad3_ Q2N2222
+r26 net-_q36-pad1_ net-_q31-pad3_ 10k
+r18 net-_q26-pad2_ net-_q23-pad2_ 10k
+r21 net-_q29-pad2_ net-_q28-pad3_ 100k
+r14 net-_r14-pad1_ v+ 10k
+q54 net-_q50-pad3_ net-_q54-pad2_ net-_q53-pad2_ Q2N2222
+r46 net-_q54-pad2_ v+ 4.7k
+q48 net-_q41-pad1_ net-_q41-pad3_ net-_q48-pad3_ Q2N2222
+r44 net-_q48-pad3_ net-_q53-pad2_ 21k
+q53 net-_q50-pad3_ net-_q53-pad2_ net-_q48-pad3_ Q2N2222
+r42 gnd net-_q49-pad3_ 10k
+q49 net-_q48-pad3_ c net-_q49-pad3_ Q2N2222
+q57 v+ e net-_q57-pad3_ Q2N2222
+q59 net-_q54-pad2_ f net-_q57-pad3_ Q2N2222
+q55 net-_q54-pad2_ e net-_q51-pad3_ Q2N2222
+q51 v+ f net-_q51-pad3_ Q2N2222
+q45 net-_q41-pad1_ net-_q41-pad1_ net-_q45-pad3_ Q2N2907A
+r37 net-_q45-pad3_ v+ 47k
+r43 net-_q50-pad3_ v+ 47k
+q50 net-_q50-pad1_ net-_q41-pad1_ net-_q50-pad3_ Q2N2907A
+.tran 0.1e-03 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/LM567.kicad_sch b/library/SubcircuitLibrary/ICLM567/LM567/LM567.kicad_sch
new file mode 100644
index 000000000..d44dc5e7a
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/LM567.kicad_sch
@@ -0,0 +1,5600 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid d1457a9b-bd18-41e7-8084-7d0d6ff3934b)
+
+  (paper "A2")
+
+  (lib_symbols
+    (symbol "eSim_Devices:eSim_NPN" (pin_names (offset 0) hide) (in_bom yes) (on_board yes)
+      (property "Reference" "Q" (id 0) (at -2.54 1.27 0)
+        (effects (font (size 1.27 1.27)) (justify right))
+      )
+      (property "Value" "eSim_NPN" (id 1) (at -1.27 3.81 0)
+        (effects (font (size 1.27 1.27)) (justify right))
+      )
+      (property "Footprint" "" (id 2) (at 5.08 2.54 0)
+        (effects (font (size 0.7366 0.7366)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "eSim_NPN_0_1"
+        (polyline
+          (pts
+            (xy 0.635 0.635)
+            (xy 2.54 2.54)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy 0.635 -0.635)
+            (xy 2.54 -2.54)
+            (xy 2.54 -2.54)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy 0.635 1.905)
+            (xy 0.635 -1.905)
+            (xy 0.635 -1.905)
+          )
+          (stroke (width 0.508) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy 1.27 -1.778)
+            (xy 1.778 -1.27)
+            (xy 2.286 -2.286)
+            (xy 1.27 -1.778)
+            (xy 1.27 -1.778)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type outline))
+        )
+        (circle (center 1.27 0) (radius 2.8194)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "eSim_NPN_1_1"
+        (pin passive line (at 2.54 5.08 270) (length 2.54)
+          (name "C" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at -5.08 0 0) (length 5.715)
+          (name "B" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 2.54 -5.08 90) (length 2.54)
+          (name "E" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Devices:eSim_PNP" (pin_names (offset 0) hide) (in_bom yes) (on_board yes)
+      (property "Reference" "Q" (id 0) (at -2.54 1.27 0)
+        (effects (font (size 1.27 1.27)) (justify right))
+      )
+      (property "Value" "eSim_PNP" (id 1) (at -1.27 3.81 0)
+        (effects (font (size 1.27 1.27)) (justify right))
+      )
+      (property "Footprint" "" (id 2) (at 5.08 2.54 0)
+        (effects (font (size 0.7366 0.7366)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "eSim_PNP_0_1"
+        (polyline
+          (pts
+            (xy 0.635 0.635)
+            (xy 2.54 2.54)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy 0.635 -0.635)
+            (xy 2.54 -2.54)
+            (xy 2.54 -2.54)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy 0.635 1.905)
+            (xy 0.635 -1.905)
+            (xy 0.635 -1.905)
+          )
+          (stroke (width 0.508) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy 2.286 -1.778)
+            (xy 1.778 -2.286)
+            (xy 1.27 -1.27)
+            (xy 2.286 -1.778)
+            (xy 2.286 -1.778)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type outline))
+        )
+        (circle (center 1.27 0) (radius 2.8194)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "eSim_PNP_1_1"
+        (pin passive line (at 2.54 5.08 270) (length 2.54)
+          (name "C" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at -5.08 0 0) (length 5.715)
+          (name "B" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 2.54 -5.08 90) (length 2.54)
+          (name "E" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "eSim_Devices:resistor" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "R" (id 0) (at 1.27 3.302 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "resistor" (id 1) (at 1.27 -1.27 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 1.27 -0.508 0)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "Datasheet" "" (id 3) (at 1.27 1.27 90)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "ki_fp_filters" "R_* Resistor_*" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "resistor_0_1"
+        (rectangle (start 3.81 0.254) (end -1.27 2.286)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "resistor_1_1"
+        (pin passive line (at -2.54 1.27 0) (length 1.27)
+          (name "~" (effects (font (size 1.524 1.524))))
+          (number "1" (effects (font (size 1.524 1.524))))
+        )
+        (pin passive line (at 5.08 1.27 180) (length 1.27)
+          (name "~" (effects (font (size 1.524 1.524))))
+          (number "2" (effects (font (size 1.524 1.524))))
+        )
+      )
+    )
+    (symbol "eSim_Miscellaneous:PORT" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 1.27 2.54 0)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "Value" "PORT" (id 1) (at 0 0 0)
+        (effects (font (size 0.762 0.762)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.524 1.524)))
+      )
+      (symbol "PORT_0_1"
+        (rectangle (start -2.54 1.27) (end 2.54 -1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 2.54 1.27) (mid 3.1355 0.5955) (end 3.81 0)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (arc (start 3.81 0) (mid 3.1447 -0.6046) (end 2.54 -1.27)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+      )
+      (symbol "PORT_1_1"
+        (pin bidirectional line (at 6.35 0 180) (length 2.54)
+          (name "~" (effects (font (size 0.762 0.762))))
+          (number "1" (effects (font (size 0.762 0.762))))
+        )
+      )
+      (symbol "PORT_2_1"
+        (pin bidirectional line (at 6.35 0 180) (length 2.54)
+          (name "~" (effects (font (size 0.762 0.762))))
+          (number "2" (effects (font (size 0.762 0.762))))
+        )
+      )
+      (symbol "PORT_3_1"
+        (pin bidirectional line (at 6.35 0 180) (length 2.54)
+          (name "~" (effects (font (size 0.762 0.762))))
+          (number "3" (effects (font (size 0.762 0.762))))
+        )
+      )
+      (symbol "PORT_4_1"
+        (pin bidirectional line (at 6.35 0 180) (length 2.54)
+          (name "~" (effects (font (size 0.762 0.762))))
+          (number "4" (effects (font (size 0.762 0.762))))
+        )
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+    )
+    (path "/f10bfdef-bf99-44eb-abc2-48b3709c9ead"
+      (reference "R1") (unit 1) (value "47K") (footprint "")
+    )
+    (path "/cffe4f8c-9eb8-4c22-a31b-5241f530f128"
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+    (path "/d5c0a532-d64d-452d-a0d7-4dd9eb7eac6c"
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+    )
+    (path "/b3562fd2-70fa-4a26-9580-5172eec75e75"
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+      (reference "R11") (unit 1) (value "2.2K") (footprint "")
+    )
+    (path "/8b33da34-3547-4d6f-ae37-25518fa05527"
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+    )
+    (path "/e92b1fb6-994b-42f6-8a21-39e6d16cf0e2"
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+    )
+    (path "/9d710db5-ffe6-45ff-b26a-13140500ddb4"
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+    (path "/f872fbd0-c61d-4c61-933b-2225699f130f"
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+    )
+    (path "/d215eba3-bf58-453e-97af-a70b382813ef"
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+    )
+    (path "/8a6b7eb6-3181-4e1a-8ab5-958d877ddde3"
+      (reference "R17") (unit 1) (value "10K") (footprint "")
+    )
+    (path "/eaddc60f-0cf2-42ca-a392-c64ae0c9c61d"
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+    )
+    (path "/5a946dbd-8e12-47bd-9207-2630cd298d40"
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+    )
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+    )
+    (path "/912dd7d8-cd4c-474a-940f-52c0341002ce"
+      (reference "R21") (unit 1) (value "100K") (footprint "")
+    )
+    (path "/95140b52-7a48-4eef-9c70-633d8f3f1069"
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+    )
+    (path "/dae98b63-23c7-49f8-ae04-d31fac645a95"
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+    )
+    (path "/3232da08-bbf2-45f6-be05-02f4bd6d0915"
+      (reference "R24") (unit 1) (value "33K") (footprint "")
+    )
+    (path "/e24176e6-cfe2-4d36-93a5-de369158b09b"
+      (reference "R25") (unit 1) (value "4.7K") (footprint "")
+    )
+    (path "/d9bda1e2-9fd8-40e2-bd20-0a464983bc3f"
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+    )
+    (path "/fbce6552-a8a8-4810-af12-87315cdfbc30"
+      (reference "R27") (unit 1) (value "4.7K") (footprint "")
+    )
+    (path "/a805956f-4a86-4fd1-a933-73c52145c836"
+      (reference "R28") (unit 1) (value "10K") (footprint "")
+    )
+    (path "/a6d4e9c9-a12f-4b51-8954-ea3b133ac747"
+      (reference "R29") (unit 1) (value "10K") (footprint "")
+    )
+    (path "/add13638-d746-4f03-b992-48f8ad47eb4e"
+      (reference "R30") (unit 1) (value "33K") (footprint "")
+    )
+    (path "/8e58cc46-99cf-4589-9245-18382226a69c"
+      (reference "R31") (unit 1) (value "47K") (footprint "")
+    )
+    (path "/cea98c26-da30-4985-867a-3ae7d64ad7da"
+      (reference "R32") (unit 1) (value "10K") (footprint "")
+    )
+    (path "/9e6333f0-8b81-4596-b8fc-d001921ebd9f"
+      (reference "R33") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/5a563fcc-e809-4a2f-827c-cc08b462998d"
+      (reference "R34") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/d7357417-0e32-4014-b863-eb312ead1944"
+      (reference "R35") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/a6e6c229-6454-4091-810b-5defce23e0d8"
+      (reference "R36") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/92956b2c-e1d4-4057-8572-b8ed1dff6b91"
+      (reference "R37") (unit 1) (value "47K") (footprint "")
+    )
+    (path "/cb0675cc-5d6b-45e6-a4dc-64016d010df8"
+      (reference "R38") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/3f312faa-65f3-4bda-b4b1-c64d8454ea5f"
+      (reference "R39") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/fe55a0c9-a4e4-4091-b26e-c83e1489cc37"
+      (reference "R40") (unit 1) (value "2.2K") (footprint "")
+    )
+    (path "/ffa624b5-5313-472a-adb2-03534f45038b"
+      (reference "R41") (unit 1) (value "2.2K") (footprint "")
+    )
+    (path "/83dd30d8-573e-42b7-b96d-8550d056d753"
+      (reference "R42") (unit 1) (value "10K") (footprint "")
+    )
+    (path "/564b306c-6e9a-4e34-b419-e972aa17edb0"
+      (reference "R43") (unit 1) (value "47K") (footprint "")
+    )
+    (path "/36f16730-bf38-4e4e-9003-9b6457076dcc"
+      (reference "R44") (unit 1) (value "21K") (footprint "")
+    )
+    (path "/05ee826b-e440-4dec-baf9-991d4e204e29"
+      (reference "R45") (unit 1) (value "10K") (footprint "")
+    )
+    (path "/250f9265-0036-42b1-8ccb-37295bc90a2d"
+      (reference "R46") (unit 1) (value "4.7K") (footprint "")
+    )
+    (path "/e7acafb7-03d8-4206-bdb3-6a44e6220236"
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+    )
+    (path "/6465c99b-5c4d-43c4-9900-bcd59d10e27f"
+      (reference "R48") (unit 1) (value "4.7K") (footprint "")
+    )
+    (path "/cc6e8cad-3cae-49c9-9ace-3f7b4e6c9e87"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/765f5c53-d6d3-4350-b7c9-9660e43be77c"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/85da4275-0c83-4c39-93f5-8c52a98cb865"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/8ff969e1-ef17-4c29-b8df-298e35dc59f3"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/fd254f12-844e-4089-9944-cc6f86e89491"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+    (path "/2459b484-c29c-4c49-8a0c-a870052fa73d"
+      (reference "U1") (unit 6) (value "PORT") (footprint "")
+    )
+    (path "/7f7ad6af-f0df-48f0-b7d8-245f1f2ed115"
+      (reference "U1") (unit 7) (value "PORT") (footprint "")
+    )
+    (path "/a7ed59f7-df6b-4aab-9617-780482fa9a5b"
+      (reference "U1") (unit 8) (value "PORT") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/LM567.sub b/library/SubcircuitLibrary/ICLM567/LM567/LM567.sub
new file mode 100644
index 000000000..0bcd1b143
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/LM567.sub
@@ -0,0 +1,117 @@
+* Subcircuit LM567
+.subckt LM567 net-_q54-pad2_ net-_q30-pad1_ net-_q32-pad2_ v+ a net-_q9-pad2_ gnd net-_q61-pad1_ 
+.title kicad schematic
+.include NPN.lib
+.include PNP.lib
+r3 net-_q6-pad3_ v+ 47k
+q1 v+ net-_q1-pad2_ a Q2N2222
+q4 v+ net-_q4-pad2_ a Q2N2222
+r1 net-_q1-pad2_ v+ 47k
+r2 net-_q4-pad2_ net-_q2-pad2_ 10k
+q6 net-_q2-pad2_ d net-_q6-pad3_ Q2N2907A
+q10 net-_q10-pad1_ net-_q10-pad2_ gnd Q2N2222
+q11 a a net-_q11-pad3_ Q2N2222
+r4 net-_q12-pad1_ net-_q11-pad3_ 47k
+q12 net-_q12-pad1_ net-_q12-pad2_ gnd Q2N2222
+r12 net-_q19-pad3_ v+ 2.2k
+q19 gnd net-_q16-pad1_ net-_q19-pad3_ Q2N2907A
+r7 net-_q16-pad1_ v+ 2.2k
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
+q20 net-_q16-pad3_ b net-_q20-pad3_ Q2N2222
+r10 gnd net-_q20-pad3_ 10k
+q22 net-_q22-pad1_ net-_q22-pad1_ net-_q16-pad1_ Q2N2222
+r11 gnd net-_q25-pad3_ 2.2k
+q18 e net-_q10-pad1_ net-_q18-pad3_ Q2N2222
+q5 net-_q2-pad2_ net-_q12-pad1_ gnd Q2N2222
+q3 net-_q1-pad2_ net-_q2-pad2_ gnd Q2N2222
+q7 net-_q2-pad2_ net-_q2-pad2_ net-_q10-pad2_ Q2N2222
+q8 net-_q10-pad2_ net-_q10-pad2_ gnd Q2N2222
+q2 a net-_q2-pad2_ gnd Q2N2222
+r5 net-_q13-pad1_ v+ 22k
+q13 net-_q13-pad1_ net-_q10-pad1_ net-_q13-pad3_ Q2N2222
+q14 net-_q13-pad3_ b net-_q14-pad3_ Q2N2222
+q9 v+ net-_q9-pad2_ net-_q10-pad1_ Q2N2222
+r6 gnd net-_q14-pad3_ 10k
+r9 e net-_r14-pad1_ 10k
+q15 net-_q12-pad2_ net-_q13-pad1_ net-_q15-pad3_ Q2N2907A
+q21 gnd net-_q17-pad3_ net-_q15-pad3_ Q2N2907A
+r8 net-_q15-pad3_ v+ 22k
+q17 net-_q13-pad1_ net-_q13-pad1_ net-_q17-pad3_ Q2N2222
+q23 net-_q17-pad3_ net-_q23-pad2_ net-_q13-pad3_ Q2N2222
+r13 net-_q17-pad3_ v+ 22k
+q46 d d net-_q46-pad3_ Q2N2907A
+r36 net-_q42-pad1_ net-_q34-pad2_ 21k
+r41 gnd net-_q47-pad3_ 2.2k
+q47 b b net-_q47-pad3_ Q2N2222
+q56 net-_q52-pad3_ b net-_q56-pad3_ Q2N2222
+r45 gnd net-_q56-pad3_ 10k
+r40 b d 2.2k
+q58 net-_q57-pad3_ net-_q32-pad3_ net-_q52-pad3_ Q2N2222
+q52 net-_q51-pad3_ net-_q38-pad3_ net-_q52-pad3_ Q2N2222
+r48 gnd net-_q60-pad3_ 4.7k
+q60 net-_q60-pad1_ net-_q50-pad1_ net-_q60-pad3_ Q2N2222
+r47 net-_q60-pad1_ v+ 4.7k
+q61 net-_q61-pad1_ net-_q60-pad3_ gnd Q2N2222
+q43 c c net-_q43-pad3_ Q2N2222
+r30 net-_q33-pad1_ net-_q38-pad3_ 33k
+q42 net-_q42-pad1_ net-_q42-pad1_ c Q2N2222
+q44 net-_q43-pad3_ net-_q43-pad3_ gnd Q2N2222
+q24 net-_q19-pad3_ net-_q22-pad1_ net-_q12-pad1_ Q2N2907A
+q27 net-_q22-pad1_ net-_q27-pad2_ net-_q16-pad3_ Q2N2222
+r20 gnd net-_q27-pad2_ 4.7k
+r19 net-_q27-pad2_ net-_q26-pad2_ 4.7k
+q33 net-_q33-pad1_ b net-_q33-pad3_ Q2N2222
+r25 gnd net-_q33-pad3_ 4.7k
+r23 a net-_q30-pad2_ 4.7k
+r27 net-_q30-pad2_ net-_q34-pad2_ 4.7k
+q32 net-_q30-pad3_ net-_q32-pad2_ net-_q32-pad3_ Q2N2222
+r24 net-_q33-pad1_ net-_q32-pad3_ 33k
+r16 net-_q22-pad1_ v+ 2.2k
+q25 net-_q18-pad3_ b net-_q25-pad3_ Q2N2222
+q26 f net-_q26-pad2_ net-_q18-pad3_ Q2N2222
+r33 net-_q38-pad2_ net-_q42-pad1_ 21k
+r34 net-_q32-pad2_ net-_q42-pad1_ 21k
+q38 net-_q37-pad3_ net-_q38-pad2_ net-_q38-pad3_ Q2N2222
+r31 net-_q35-pad2_ v+ 47k
+r28 net-_q36-pad1_ net-_q35-pad3_ 10k
+r32 gnd net-_q39-pad3_ 10k
+q39 net-_q35-pad2_ b net-_q39-pad3_ Q2N2222
+q31 v+ net-_q30-pad1_ net-_q31-pad3_ Q2N2222
+q35 net-_q28-pad1_ net-_q35-pad2_ net-_q35-pad3_ Q2N2222
+q36 net-_q36-pad1_ b net-_q36-pad3_ Q2N2222
+r29 gnd net-_q36-pad3_ 10k
+q40 v+ net-_q30-pad2_ net-_q37-pad3_ Q2N2222
+q37 net-_q30-pad1_ net-_q34-pad2_ net-_q37-pad3_ Q2N2222
+r38 net-_q48-pad3_ net-_q41-pad3_ 21k
+q41 net-_q41-pad1_ net-_q35-pad2_ net-_q41-pad3_ Q2N2222
+q34 v+ net-_q34-pad2_ net-_q30-pad3_ Q2N2222
+r35 net-_q34-pad2_ v+ 21k
+r39 net-_q46-pad3_ v+ 21k
+r22 net-_q30-pad1_ v+ 10k
+r17 net-_q28-pad1_ v+ 10k
+q30 net-_q30-pad1_ net-_q30-pad2_ net-_q30-pad3_ Q2N2222
+r15 f net-_r14-pad1_ 10k
+q29 net-_q28-pad3_ net-_q29-pad2_ net-_q23-pad2_ Q2N2222
+q28 net-_q28-pad1_ net-_q28-pad1_ net-_q28-pad3_ Q2N2222
+r26 net-_q36-pad1_ net-_q31-pad3_ 10k
+r18 net-_q26-pad2_ net-_q23-pad2_ 10k
+r21 net-_q29-pad2_ net-_q28-pad3_ 100k
+r14 net-_r14-pad1_ v+ 10k
+q54 net-_q50-pad3_ net-_q54-pad2_ net-_q53-pad2_ Q2N2222
+r46 net-_q54-pad2_ v+ 4.7k
+q48 net-_q41-pad1_ net-_q41-pad3_ net-_q48-pad3_ Q2N2222
+r44 net-_q48-pad3_ net-_q53-pad2_ 21k
+q53 net-_q50-pad3_ net-_q53-pad2_ net-_q48-pad3_ Q2N2222
+r42 gnd net-_q49-pad3_ 10k
+q49 net-_q48-pad3_ c net-_q49-pad3_ Q2N2222
+q57 v+ e net-_q57-pad3_ Q2N2222
+q59 net-_q54-pad2_ f net-_q57-pad3_ Q2N2222
+q55 net-_q54-pad2_ e net-_q51-pad3_ Q2N2222
+q51 v+ f net-_q51-pad3_ Q2N2222
+q45 net-_q41-pad1_ net-_q41-pad1_ net-_q45-pad3_ Q2N2907A
+r37 net-_q45-pad3_ v+ 47k
+r43 net-_q50-pad3_ v+ 47k
+q50 net-_q50-pad1_ net-_q41-pad1_ net-_q50-pad3_ Q2N2907A
+* Control Statements
+
+.ends LM567
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/LM567_Previous_Values.xml b/library/SubcircuitLibrary/ICLM567/LM567/LM567_Previous_Values.xml
new file mode 100644
index 000000000..7f9431c57
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/LM567_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q46><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q46><q47><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q47><q56><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q56><q58><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q58><q52><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q52><q60><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q60><q61><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q61><q43><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q43><q42><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q42><q44><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q44><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q24><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q33><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q32><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q26><q38><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q38><q39><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q39><q31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q31><q35><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q35><q36><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q36><q40><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q40><q37><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q37><q41><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q41><q34><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q34><q30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q29><q28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q28><q54><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q54><q48><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><q53><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q53><q49><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q49><q57><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q57><q59><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q59><q55><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q55><q51><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q51><q45><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q45><q50><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q50></devicemodel><subcircuit /><microcontroller /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/NPN.lib b/library/SubcircuitLibrary/ICLM567/LM567/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/PNP.lib b/library/SubcircuitLibrary/ICLM567/LM567/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/_autosave-LM567.sch b/library/SubcircuitLibrary/ICLM567/LM567/_autosave-LM567.sch
new file mode 100644
index 000000000..0c010ac4f
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/_autosave-LM567.sch
@@ -0,0 +1,2100 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 2300 750 
+Connection ~ 2300 2800
+Connection ~ 2300 3250
+Connection ~ 2300 6050
+Connection ~ 2300 9000
+Connection ~ 2700 750 
+Connection ~ 2700 1950
+Connection ~ 2700 9000
+Connection ~ 3100 6700
+Connection ~ 3200 750 
+Connection ~ 3550 6700
+Connection ~ 3550 9000
+Connection ~ 4200 750 
+Connection ~ 4200 1900
+Connection ~ 4200 2450
+Connection ~ 4200 2600
+Connection ~ 4200 3150
+Connection ~ 4200 3250
+Connection ~ 4600 750 
+Connection ~ 4600 4900
+Connection ~ 4600 6050
+Connection ~ 4600 7250
+Connection ~ 4750 7250
+Connection ~ 4750 9000
+Connection ~ 5550 4650
+Connection ~ 5550 4900
+Connection ~ 6250 750 
+Connection ~ 6250 1600
+Connection ~ 6250 2500
+Connection ~ 6250 3250
+Connection ~ 6950 2500
+Connection ~ 7050 6850
+Connection ~ 7050 7800
+Connection ~ 7100 750 
+Connection ~ 7100 1300
+Connection ~ 7450 4650
+Connection ~ 7450 8500
+Connection ~ 7450 9350
+Connection ~ 7800 6100
+Connection ~ 7800 6550
+Connection ~ 8150 750 
+Connection ~ 8150 1550
+Connection ~ 8150 2500
+Connection ~ 8400 7800
+Connection ~ 8500 750 
+Connection ~ 8500 3450
+Connection ~ 8500 4050
+Connection ~ 8500 4600
+Connection ~ 8500 5250
+Connection ~ 8850 6100
+Connection ~ 8850 6850
+Connection ~ 8850 7800
+Connection ~ 8950 750 
+Connection ~ 8950 1150
+Connection ~ 8950 1700
+Connection ~ 8950 2850
+Connection ~ 9250 1150
+Connection ~ 9450 4900
+Connection ~ 9450 8150
+Connection ~ 9450 9350
+Connection ~ 10050 750 
+Connection ~ 10050 1950
+Connection ~ 10050 3000
+Connection ~ 10050 4600
+Connection ~ 10050 5500
+Connection ~ 10050 5650
+Connection ~ 10400 5400
+Connection ~ 10400 7100
+Connection ~ 10400 7800
+Connection ~ 10400 9350
+Connection ~ 10550 750 
+Connection ~ 10900 6750
+Connection ~ 11250 5000
+Connection ~ 11250 5650
+Connection ~ 11350 2650
+Connection ~ 11500 6900
+Connection ~ 11800 3050
+Connection ~ 11850 5300
+Connection ~ 11950 750 
+Connection ~ 11950 1950
+Connection ~ 12200 1950
+Connection ~ 12500 4500
+Connection ~ 13150 4500
+Connection ~ 13150 5650
+Connection ~ 13150 5950
+Connection ~ 13150 6750
+Connection ~ 13150 7200
+Connection ~ 13150 7750
+Connection ~ 13150 7900
+Connection ~ 13150 8550
+Connection ~ 13150 9350
+Connection ~ 13350 750 
+Connection ~ 13350 1850
+Connection ~ 13350 2050
+Connection ~ 13350 2650
+Connection ~ 13750 1550
+Connection ~ 13850 4500
+Connection ~ 13850 6250
+Connection ~ 13850 8200
+Connection ~ 13850 9350
+Connection ~ 14150 8500
+Connection ~ 14250 3000
+Connection ~ 14250 3100
+Connection ~ 14250 5850
+Connection ~ 14450 750 
+Connection ~ 14450 1300
+Connection ~ 14550 4500
+Connection ~ 14900 5300
+Connection ~ 15300 1800
+Connection ~ 15300 2650
+Connection ~ 15900 5000
+Connection ~ 15900 5450
+Connection ~ 16000 1250
+Connection ~ 16000 2200
+Connection ~ 16400 4500
+Wire Wire Line
+	1800 700  1800 750 
+Wire Wire Line
+	1850 3250 2300 3250
+Wire Wire Line
+	1850 9000 2300 9000
+Wire Wire Line
+	1950 4600 4300 4600
+Wire Wire Line
+	2300 750  1800 750 
+Wire Wire Line
+	2300 750  2700 750 
+Wire Wire Line
+	2300 1750 2300 750 
+Wire Wire Line
+	2300 2150 2300 2800
+Wire Wire Line
+	2300 2800 2300 3250
+Wire Wire Line
+	2300 2800 3200 2800
+Wire Wire Line
+	2300 3250 2300 6050
+Wire Wire Line
+	2300 6050 2300 7200
+Wire Wire Line
+	2300 6050 4600 6050
+Wire Wire Line
+	2300 7600 2300 9000
+Wire Wire Line
+	2300 9000 2700 9000
+Wire Wire Line
+	2600 1950 2700 1950
+Wire Wire Line
+	2600 7400 3100 7400
+Wire Wire Line
+	2700 750  2700 1100
+Wire Wire Line
+	2700 750  3200 750 
+Wire Wire Line
+	2700 1950 2700 1400
+Wire Wire Line
+	2700 1950 2700 6500
+Wire Wire Line
+	2700 6900 2700 9000
+Wire Wire Line
+	2700 9000 3550 9000
+Wire Wire Line
+	3000 6700 3100 6700
+Wire Wire Line
+	3100 6700 3550 6700
+Wire Wire Line
+	3100 7400 3100 6700
+Wire Wire Line
+	3200 750  3200 2250
+Wire Wire Line
+	3200 750  4200 750 
+Wire Wire Line
+	3200 2800 3200 2650
+Wire Wire Line
+	3500 2450 3650 2450
+Wire Wire Line
+	3550 1900 3550 6700
+Wire Wire Line
+	3550 6700 3550 7050
+Wire Wire Line
+	3550 7450 3550 9000
+Wire Wire Line
+	3550 9000 4750 9000
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+	3850 7250 4600 7250
+Wire Wire Line
+	3900 3150 3900 5250
+Wire Wire Line
+	3900 5250 4300 5250
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+	3950 2450 4200 2450
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+	4200 750  4600 750 
+Wire Wire Line
+	4200 900  4200 750 
+Wire Wire Line
+	4200 1200 4200 1400
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+	4200 1900 3550 1900
+Wire Wire Line
+	4200 1900 4200 1800
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+	4200 2450 4200 1900
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+	4200 2600 4200 2700
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+	4200 3100 4200 3150
+Wire Wire Line
+	4200 3150 3900 3150
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+	4200 3150 4200 3250
+Wire Wire Line
+	4200 3250 4200 3350
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+	4600 6050 4900 6050
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+	4750 7250 4750 7550
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+	4750 7950 4750 9000
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+	4750 9000 5350 9000
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+	5350 9350 5350 9000
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+	5550 2900 5550 4650
+Wire Wire Line
+	5550 4650 5550 4900
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+	5550 8300 6750 8300
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+	5850 4650 5550 4650
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+	5850 4900 5850 4650
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+	5950 2900 5550 2900
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+	6250 750  6250 900 
+Wire Wire Line
+	6250 750  7100 750 
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+	6250 1200 6250 1600
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+	6250 1600 6250 2500
+Wire Wire Line
+	6250 1600 6500 1600
+Wire Wire Line
+	6250 2500 6250 2700
+Wire Wire Line
+	6250 2500 6950 2500
+Wire Wire Line
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+$EndComp
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+U 1 1 00000000
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+$EndComp
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+$EndComp
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+	1    10450 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 10500 6750
+F 0 "Q?" H 10700 6800 50  0000 L CNN
+F 1 "eSim_NPN" H 10700 6700 50  0000 L CNN
+F 2 "" H 10700 6850 29  0000 C CNN
+F 3 "" H 10500 6750 60  0000 C CNN
+	1    10500 6750
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 10500 8450
+F 0 "Q?" H 10700 8500 50  0000 L CNN
+F 1 "eSim_NPN" H 10700 8400 50  0000 L CNN
+F 2 "" H 10700 8550 29  0000 C CNN
+F 3 "" H 10500 8450 60  0000 C CNN
+	1    10500 8450
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 10800 5000
+F 0 "Q?" H 11000 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 11000 4950 50  0000 L CNN
+F 2 "" H 11000 5100 29  0000 C CNN
+F 3 "" H 10800 5000 60  0000 C CNN
+	1    10800 5000
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 11450 1950
+F 0 "Q?" H 11650 2000 50  0000 L CNN
+F 1 "eSim_NPN" H 11650 1900 50  0000 L CNN
+F 2 "" H 11650 2050 29  0000 C CNN
+F 3 "" H 11450 1950 60  0000 C CNN
+	1    11450 1950
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 11450 3050
+F 0 "Q?" H 11650 3100 50  0000 L CNN
+F 1 "eSim_NPN" H 11650 3000 50  0000 L CNN
+F 2 "" H 11650 3150 29  0000 C CNN
+F 3 "" H 11450 3050 60  0000 C CNN
+	1    11450 3050
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 11750 5000
+F 0 "Q?" H 11950 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 11950 4950 50  0000 L CNN
+F 2 "" H 11950 5100 29  0000 C CNN
+F 3 "" H 11750 5000 60  0000 C CNN
+	1    11750 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 11950 5950
+F 0 "Q?" H 12150 6000 50  0000 L CNN
+F 1 "eSim_NPN" H 12150 5900 50  0000 L CNN
+F 2 "" H 12150 6050 29  0000 C CNN
+F 3 "" H 11950 5950 60  0000 C CNN
+	1    11950 5950
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 12100 3050
+F 0 "Q?" H 12300 3100 50  0000 L CNN
+F 1 "eSim_NPN" H 12300 3000 50  0000 L CNN
+F 2 "" H 12300 3150 29  0000 C CNN
+F 3 "" H 12100 3050 60  0000 C CNN
+	1    12100 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 12600 5000
+F 0 "Q?" H 12800 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 12800 4950 50  0000 L CNN
+F 2 "" H 12800 5100 29  0000 C CNN
+F 3 "" H 12600 5000 60  0000 C CNN
+	1    12600 5000
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 13250 2350
+F 0 "Q?" H 13450 2400 50  0000 L CNN
+F 1 "eSim_NPN" H 13450 2300 50  0000 L CNN
+F 2 "" H 13450 2450 29  0000 C CNN
+F 3 "" H 13250 2350 60  0000 C CNN
+	1    13250 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 13250 7450
+F 0 "Q?" H 13450 7500 50  0000 L CNN
+F 1 "eSim_NPN" H 13450 7400 50  0000 L CNN
+F 2 "" H 13450 7550 29  0000 C CNN
+F 3 "" H 13250 7450 60  0000 C CNN
+	1    13250 7450
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 13250 8200
+F 0 "Q?" H 13450 8250 50  0000 L CNN
+F 1 "eSim_NPN" H 13450 8150 50  0000 L CNN
+F 2 "" H 13450 8300 29  0000 C CNN
+F 3 "" H 13250 8200 60  0000 C CNN
+	1    13250 8200
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 13250 8900
+F 0 "Q?" H 13450 8950 50  0000 L CNN
+F 1 "eSim_NPN" H 13450 8850 50  0000 L CNN
+F 2 "" H 13450 9000 29  0000 C CNN
+F 3 "" H 13250 8900 60  0000 C CNN
+	1    13250 8900
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_PNP Q?
+U 1 1 00000000
+P 13450 1550
+F 0 "Q?" H 13650 1500 50  0000 L CNN
+F 1 "eSim_PNP" H 13650 1600 50  0000 L CNN
+F 2 "" H 13650 1650 29  0000 C CNN
+F 3 "" H 13450 1550 60  0000 C CNN
+	1    13450 1550
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_PNP Q?
+U 1 1 00000000
+P 13950 5850
+F 0 "Q?" H 14150 5800 50  0000 L CNN
+F 1 "eSim_PNP" H 14150 5900 50  0000 L CNN
+F 2 "" H 14150 5950 29  0000 C CNN
+F 3 "" H 13950 5850 60  0000 C CNN
+	1    13950 5850
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 13950 8500
+F 0 "Q?" H 14150 8550 50  0000 L CNN
+F 1 "eSim_NPN" H 14150 8450 50  0000 L CNN
+F 2 "" H 14150 8600 29  0000 C CNN
+F 3 "" H 13950 8500 60  0000 C CNN
+	1    13950 8500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 14000 2650
+F 0 "Q?" H 14200 2700 50  0000 L CNN
+F 1 "eSim_NPN" H 14200 2600 50  0000 L CNN
+F 2 "" H 14200 2750 29  0000 C CNN
+F 3 "" H 14000 2650 60  0000 C CNN
+	1    14000 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_PNP Q?
+U 1 1 00000000
+P 14350 1550
+F 0 "Q?" H 14550 1500 50  0000 L CNN
+F 1 "eSim_PNP" H 14550 1600 50  0000 L CNN
+F 2 "" H 14550 1650 29  0000 C CNN
+F 3 "" H 14350 1550 60  0000 C CNN
+	1    14350 1550
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 14350 3300
+F 0 "Q?" H 14550 3350 50  0000 L CNN
+F 1 "eSim_NPN" H 14550 3250 50  0000 L CNN
+F 2 "" H 14550 3400 29  0000 C CNN
+F 3 "" H 14350 3300 60  0000 C CNN
+	1    14350 3300
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 14450 5000
+F 0 "Q?" H 14650 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 14650 4950 50  0000 L CNN
+F 2 "" H 14650 5100 29  0000 C CNN
+F 3 "" H 14450 5000 60  0000 C CNN
+	1    14450 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 14850 2650
+F 0 "Q?" H 15050 2700 50  0000 L CNN
+F 1 "eSim_NPN" H 15050 2600 50  0000 L CNN
+F 2 "" H 15050 2750 29  0000 C CNN
+F 3 "" H 14850 2650 60  0000 C CNN
+	1    14850 2650
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 15400 2200
+F 0 "Q?" H 15600 2250 50  0000 L CNN
+F 1 "eSim_NPN" H 15600 2150 50  0000 L CNN
+F 2 "" H 15600 2300 29  0000 C CNN
+F 3 "" H 15400 2200 60  0000 C CNN
+	1    15400 2200
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 15400 5000
+F 0 "Q?" H 15600 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 15600 4950 50  0000 L CNN
+F 2 "" H 15600 5100 29  0000 C CNN
+F 3 "" H 15400 5000 60  0000 C CNN
+	1    15400 5000
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 16300 5000
+F 0 "Q?" H 16500 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 16500 4950 50  0000 L CNN
+F 2 "" H 16500 5100 29  0000 C CNN
+F 3 "" H 16300 5000 60  0000 C CNN
+	1    16300 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Devices:eSim_NPN Q?
+U 1 1 00000000
+P 17300 5000
+F 0 "Q?" H 17500 5050 50  0000 L CNN
+F 1 "eSim_NPN" H 17500 4950 50  0000 L CNN
+F 2 "" H 17500 5100 29  0000 C CNN
+F 3 "" H 17300 5000 60  0000 C CNN
+	1    17300 5000
+	-1   0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/ICLM567/LM567/analysis b/library/SubcircuitLibrary/ICLM567/LM567/analysis
new file mode 100644
index 000000000..6982bcf72
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLM567/LM567/analysis
@@ -0,0 +1 @@
+.tran 0.1e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/NMOS-180nm.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/NPN.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/PMOS-180nm.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/PNP.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/analysis b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/analysis
new file mode 100644
index 000000000..14a32166e
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/analysis
@@ -0,0 +1 @@
+.tran 1e-00 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.cir b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.cir
new file mode 100644
index 000000000..203241592
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.cir
@@ -0,0 +1,35 @@
+.title KiCad schematic
+R9 GND Net-_Q10-Pad3_ 5k
+R8 GND Net-_Q2-Pad1_ 2k
+Q10 Net-_I4-Pad2_ Net-_I4-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+I5 Net-_I5-Pad1_ GND 500u
+Q9 Net-_Q12-Pad2_ Net-_I4-Pad2_ Net-_Q2-Pad1_ eSim_NPN
+Q4 Net-_Q4-Pad1_ vref Net-_I1-Pad1_ eSim_NPN
+R3 vin Net-_I2-Pad1_ 1k
+Q3 Net-_Q3-Pad1_ vref Net-_I2-Pad2_ eSim_PNP
+Q2 Net-_Q2-Pad1_ vin Net-_I2-Pad2_ eSim_PNP
+I2 Net-_I2-Pad1_ Net-_I2-Pad2_ 200u
+R10 Net-_M1-Pad2_ Net-_I2-Pad1_ 10k
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_I2-Pad1_ Net-_I2-Pad1_ eSim_MOS_P
+Q12 Net-_M4-Pad2_ Net-_Q12-Pad2_ Net-_I5-Pad1_ eSim_NPN
+R11 Net-_M4-Pad2_ Net-_I2-Pad1_ 10k
+Q11 Net-_M1-Pad2_ Net-_Q11-Pad2_ Net-_I5-Pad1_ eSim_NPN
+M4 out Net-_M4-Pad2_ Net-_I2-Pad1_ Net-_I2-Pad1_ eSim_MOS_P
+Q6 Net-_Q4-Pad1_ Net-_I3-Pad1_ Net-_Q11-Pad2_ eSim_PNP
+R6 GND Net-_Q3-Pad1_ 2k
+R5 Net-_Q4-Pad1_ Net-_I2-Pad1_ 50k
+R4 Net-_Q5-Pad3_ Net-_I2-Pad1_ 50k
+Q7 Net-_Q11-Pad2_ Net-_I4-Pad2_ Net-_Q3-Pad1_ eSim_NPN
+Q5 Net-_I3-Pad1_ Net-_I3-Pad1_ Net-_Q5-Pad3_ eSim_PNP
+I3 Net-_I3-Pad1_ GND 300u
+M2 Net-_M1-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N
+v1 Net-_I2-Pad1_ GND 5
+M3 out Net-_M1-Pad1_ GND GND eSim_MOS_N
+R7 Net-_Q1-Pad1_ Net-_I2-Pad1_ 20k
+I4 Net-_I2-Pad1_ Net-_I4-Pad2_ 1m
+Q8 Net-_Q1-Pad1_ Net-_I3-Pad1_ Net-_Q12-Pad2_ eSim_PNP
+I1 Net-_I1-Pad1_ GND 400u
+Q1 Net-_Q1-Pad1_ vin Net-_I1-Pad1_ eSim_NPN
+R2 GND vref 1k
+R1 vref Net-_I2-Pad1_ 3k
+.end
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.cir.out b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.cir.out
new file mode 100644
index 000000000..a9188da09
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.cir.out
@@ -0,0 +1,48 @@
+.title kicad schematic
+
+.include PNP.lib
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+.include NPN.lib
+r9 gnd net-_q10-pad3_ 5k
+r8 gnd net-_q2-pad1_ 2k
+q10 net-_i4-pad2_ net-_i4-pad2_ net-_q10-pad3_ Q2N2222
+i5 net-_i5-pad1_ gnd 500u
+q9 net-_q12-pad2_ net-_i4-pad2_ net-_q2-pad1_ Q2N2222
+q4 net-_q4-pad1_ vref net-_i1-pad1_ Q2N2222
+r3 vin net-_i2-pad1_ 1k
+q3 net-_q3-pad1_ vref net-_i2-pad2_ Q2N2907A
+q2 net-_q2-pad1_ vin net-_i2-pad2_ Q2N2907A
+i2 net-_i2-pad1_ net-_i2-pad2_ 200u
+r10 net-_m1-pad2_ net-_i2-pad1_ 10k
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_i2-pad1_ net-_i2-pad1_ CMOSP W=100u L=100u M=1
+q12 net-_m4-pad2_ net-_q12-pad2_ net-_i5-pad1_ Q2N2222
+r11 net-_m4-pad2_ net-_i2-pad1_ 10k
+q11 net-_m1-pad2_ net-_q11-pad2_ net-_i5-pad1_ Q2N2222
+m4 out net-_m4-pad2_ net-_i2-pad1_ net-_i2-pad1_ CMOSP W=100u L=100u M=1
+q6 net-_q4-pad1_ net-_i3-pad1_ net-_q11-pad2_ Q2N2907A
+r6 gnd net-_q3-pad1_ 2k
+r5 net-_q4-pad1_ net-_i2-pad1_ 50k
+r4 net-_q5-pad3_ net-_i2-pad1_ 50k
+q7 net-_q11-pad2_ net-_i4-pad2_ net-_q3-pad1_ Q2N2222
+q5 net-_i3-pad1_ net-_i3-pad1_ net-_q5-pad3_ Q2N2907A
+i3 net-_i3-pad1_ gnd 300u
+m2 net-_m1-pad1_ net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+v1 net-_i2-pad1_ gnd 5
+m3 out net-_m1-pad1_ gnd gnd CMOSN W=100u L=100u M=1
+r7 net-_q1-pad1_ net-_i2-pad1_ 20k
+i4 net-_i2-pad1_ net-_i4-pad2_ 1m
+q8 net-_q1-pad1_ net-_i3-pad1_ net-_q12-pad2_ Q2N2907A
+i1 net-_i1-pad1_ gnd 400u
+q1 net-_q1-pad1_ vin net-_i1-pad1_ Q2N2222
+r2 gnd vref 1k
+r1 vref net-_i2-pad1_ 3k
+.tran 1e-00 10e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.kicad_sch b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.kicad_sch
new file mode 100644
index 000000000..fba220cd7
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.kicad_sch
@@ -0,0 +1,2055 @@
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+      (reference "R6") (unit 1) (value "2k") (footprint "")
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+    (path "/d5ab7408-7815-4adc-a8d1-6d10f2c6dbc3"
+      (reference "R7") (unit 1) (value "20k") (footprint "")
+    )
+    (path "/1d4ff0eb-4b3d-445e-b3d1-7157926b5499"
+      (reference "R8") (unit 1) (value "2k") (footprint "")
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+      (reference "R9") (unit 1) (value "5k") (footprint "")
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+    (path "/4bb39a13-8a92-4d03-b604-b0956a27ed62"
+      (reference "R10") (unit 1) (value "10k") (footprint "")
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+    (path "/3d77cff8-8423-4fd1-9c45-bf06f9605cee"
+      (reference "R11") (unit 1) (value "10k") (footprint "")
+    )
+    (path "/e4b49ed7-363d-4cd4-abf2-32bc0150de2b"
+      (reference "v1") (unit 1) (value "5") (footprint "R1")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.proj b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.proj
new file mode 100644
index 000000000..a96cb28bc
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.proj
@@ -0,0 +1 @@
+schematicFile lmv7239_test3.kicad_sch
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.raw b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.raw
new file mode 100644
index 000000000..87777786c
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3.raw
@@ -0,0 +1,2048 @@
+Title: kicad schematic
+Date: Sat Nov 08 09:28:33  2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 34
+No. Points: 59      
+Variables:
+	0	time	time
+	1	v(net-_q10-pad3_)	voltage
+	2	v(net-_q2-pad1_)	voltage
+	3	v(net-_i4-pad2_)	voltage
+	4	v(net-_i5-pad1_)	voltage
+	5	v(net-_q12-pad2_)	voltage
+	6	v(net-_q4-pad1_)	voltage
+	7	v(vref)	voltage
+	8	v(net-_i1-pad1_)	voltage
+	9	v(vin)	voltage
+	10	v(net-_i2-pad1_)	voltage
+	11	v(net-_q3-pad1_)	voltage
+	12	v(net-_i2-pad2_)	voltage
+	13	v(net-_m1-pad2_)	voltage
+	14	v(net-_m1-pad1_)	voltage
+	15	v(net-_m4-pad2_)	voltage
+	16	v(net-_q11-pad2_)	voltage
+	17	v(out)	voltage
+	18	v(net-_i3-pad1_)	voltage
+	19	v(net-_q5-pad3_)	voltage
+	20	v(net-_q1-pad1_)	voltage
+	21	v(q8#collCX)	voltage
+	22	v(q5#collCX)	voltage
+	23	v(q6#collCX)	voltage
+	24	v(q2#collCX)	voltage
+	25	v(q3#collCX)	voltage
+	26	v(q1#collCX)	voltage
+	27	v(q7#collCX)	voltage
+	28	v(q11#collCX)	voltage
+	29	v(q12#collCX)	voltage
+	30	v(q4#collCX)	voltage
+	31	v(q9#collCX)	voltage
+	32	v(q10#collCX)	voltage
+	33	i(v1)	current
+Values:
+0		0.000000000000000e+00
+	1.742954993467938e+00
+	1.712196356684234e+00
+	2.361385894532613e+00
+	1.109876588143495e+00
+	1.750905264197997e+00
+	2.786338031478976e+00
+	1.250726871091846e+00
+	2.872857422863913e+00
+	3.588865877850780e+00
+	5.000000000000000e+00
+	1.672495306156165e+00
+	1.934875899586565e+00
+	4.508806281311858e+00
+	4.173300444479624e-01
+	1.131255244028580e+00
+	1.676764269496609e+00
+	4.997451909182606e+00
+	2.147333839889747e+00
+	2.792291154845850e+00
+	2.872987318874099e+00
+	2.872188317281767e+00
+	2.147365241926457e+00
+	2.786306376115919e+00
+	1.712196356685576e+00
+	1.672637613208321e+00
+	2.873998452984563e+00
+	1.676730134167132e+00
+	4.508757161939990e+00
+	1.130868369552983e+00
+	2.786338031474651e+00
+	1.750097493535625e+00
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diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3_Previous_Values.xml b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3_Previous_Values.xml
new file mode 100644
index 000000000..0e272ca26
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/LMV7239_Test_Circuit/lmv7239_test3/lmv7239_test3_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><i1 name="Source type">400u</i1><i2 name="Source type">200u</i2><i4 name="Source type">1m</i4><i5 name="Source type">500u</i5><i3 name="Source type">300u</i3><v1 name="Source type">5</v1></source><model /><devicemodel><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m1><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1></devicemodel><subcircuit /><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/NMOS-0.5um.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/NMOS-0.5um.lib
new file mode 100644
index 000000000..2e6f4635c
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/NMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/NPN.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/PMOS-0.5um.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/PMOS-0.5um.lib
new file mode 100644
index 000000000..848e8b051
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/PMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
++ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/PNP.lib b/library/SubcircuitLibrary/ICLMV7239/lmv7239/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/analysis b/library/SubcircuitLibrary/ICLMV7239/lmv7239/analysis
new file mode 100644
index 000000000..dce0ea0fa
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/analysis
@@ -0,0 +1 @@
+.tran 10e-03 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.cir b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.cir
new file mode 100644
index 000000000..ae6b3099a
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.cir
@@ -0,0 +1,32 @@
+.title KiCad schematic
+R3 Net-_I1-Pad2_ Net-_Q3-Pad1_ 2k
+Q6 Net-_Q4-Pad1_ Net-_I3-Pad1_ Net-_Q11-Pad2_ eSim_PNP
+R2 Net-_Q4-Pad1_ Net-_I4-Pad1_ 50k
+Q7 Net-_Q11-Pad2_ Net-_I4-Pad2_ Net-_Q3-Pad1_ eSim_NPN
+R8 Net-_M4-Pad2_ Net-_I4-Pad1_ 10k
+R7 Net-_M1-Pad2_ Net-_I4-Pad1_ 10k
+R4 Net-_Q1-Pad1_ Net-_I4-Pad1_ 20k
+Q8 Net-_Q1-Pad1_ Net-_I3-Pad1_ Net-_Q12-Pad2_ eSim_PNP
+Q11 Net-_M1-Pad2_ Net-_Q11-Pad2_ Net-_I5-Pad1_ eSim_NPN
+I4 Net-_I4-Pad1_ Net-_I4-Pad2_ 1m
+I5 Net-_I5-Pad1_ Net-_I1-Pad2_ 500u
+M2 Net-_M1-Pad1_ Net-_M1-Pad1_ Net-_I1-Pad2_ Net-_I1-Pad2_ eSim_MOS_N
+M3 Net-_M3-Pad1_ Net-_M1-Pad1_ Net-_I1-Pad2_ Net-_I1-Pad2_ eSim_MOS_N
+Q12 Net-_M4-Pad2_ Net-_Q12-Pad2_ Net-_I5-Pad1_ eSim_NPN
+Q5 Net-_I3-Pad1_ Net-_I3-Pad1_ Net-_Q5-Pad3_ eSim_PNP
+R1 Net-_Q5-Pad3_ Net-_I4-Pad1_ 50k
+I1 Net-_Q1-Pad3_ Net-_I1-Pad2_ 400u
+Q4 Net-_Q4-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+I3 Net-_I3-Pad1_ Net-_I1-Pad2_ 300u
+I2 Net-_I4-Pad1_ Net-_Q2-Pad3_ 200u
+U1 Net-_M3-Pad1_ Net-_I1-Pad2_ Net-_Q3-Pad2_ Net-_Q1-Pad2_ Net-_I4-Pad1_ PORT
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q2-Pad3_ eSim_PNP
+Q2 Net-_Q2-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_PNP
+R5 Net-_I1-Pad2_ Net-_Q2-Pad1_ 2k
+Q9 Net-_Q12-Pad2_ Net-_I4-Pad2_ Net-_Q2-Pad1_ eSim_NPN
+R6 Net-_I1-Pad2_ Net-_Q10-Pad3_ 5k
+Q10 Net-_I4-Pad2_ Net-_I4-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_I4-Pad1_ Net-_I4-Pad1_ eSim_MOS_P
+M4 Net-_M3-Pad1_ Net-_M4-Pad2_ Net-_I4-Pad1_ Net-_I4-Pad1_ eSim_MOS_P
+.end
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.cir.out b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.cir.out
new file mode 100644
index 000000000..95ea494c7
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.cir.out
@@ -0,0 +1,45 @@
+.title kicad schematic
+
+.include PNP.lib
+.include PMOS-0.5um.lib
+.include NMOS-0.5um.lib
+.include NPN.lib
+r3 net-_i1-pad2_ net-_q3-pad1_ 2k
+q6 net-_q4-pad1_ net-_i3-pad1_ net-_q11-pad2_ Q2N2907A
+r2 net-_q4-pad1_ net-_i4-pad1_ 50k
+q7 net-_q11-pad2_ net-_i4-pad2_ net-_q3-pad1_ Q2N2222
+r8 net-_m4-pad2_ net-_i4-pad1_ 10k
+r7 net-_m1-pad2_ net-_i4-pad1_ 10k
+r4 net-_q1-pad1_ net-_i4-pad1_ 20k
+q8 net-_q1-pad1_ net-_i3-pad1_ net-_q12-pad2_ Q2N2907A
+q11 net-_m1-pad2_ net-_q11-pad2_ net-_i5-pad1_ Q2N2222
+i4 net-_i4-pad1_ net-_i4-pad2_ 1m
+i5 net-_i5-pad1_ net-_i1-pad2_ 500u
+m2 net-_m1-pad1_ net-_m1-pad1_ net-_i1-pad2_ net-_i1-pad2_ mos_n W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad1_ net-_i1-pad2_ net-_i1-pad2_ mos_n W=100u L=100u M=1
+q12 net-_m4-pad2_ net-_q12-pad2_ net-_i5-pad1_ Q2N2222
+q5 net-_i3-pad1_ net-_i3-pad1_ net-_q5-pad3_ Q2N2907A
+r1 net-_q5-pad3_ net-_i4-pad1_ 50k
+i1 net-_q1-pad3_ net-_i1-pad2_ 400u
+q4 net-_q4-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
+i3 net-_i3-pad1_ net-_i1-pad2_ 300u
+i2 net-_i4-pad1_ net-_q2-pad3_ 200u
+* u1 net-_m3-pad1_ net-_i1-pad2_ net-_q3-pad2_ net-_q1-pad2_ net-_i4-pad1_ port
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q2-pad3_ Q2N2907A
+q2 net-_q2-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2907A
+r5 net-_i1-pad2_ net-_q2-pad1_ 2k
+q9 net-_q12-pad2_ net-_i4-pad2_ net-_q2-pad1_ Q2N2222
+r6 net-_i1-pad2_ net-_q10-pad3_ 5k
+q10 net-_i4-pad2_ net-_i4-pad2_ net-_q10-pad3_ Q2N2222
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_i4-pad1_ net-_i4-pad1_ mos_p W=100u L=100u M=1
+m4 net-_m3-pad1_ net-_m4-pad2_ net-_i4-pad1_ net-_i4-pad1_ mos_p W=100u L=100u M=1
+.tran 10e-03 10e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.kicad_sch b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.kicad_sch
new file mode 100644
index 000000000..ff13a1799
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.kicad_sch
@@ -0,0 +1,2209 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid ec4d0017-e767-42b2-91ec-9f848889c9a9)
+
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+
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+    (path "/319addbb-6068-4673-a68d-84666362d55a"
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+    )
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+    )
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+    )
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+    )
+    (path "/8872f144-c9ea-4179-aac5-8a0d91ba3557"
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+    )
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+    )
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+    )
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+      (reference "Q5") (unit 1) (value "eSim_PNP") (footprint "")
+    )
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+      (reference "Q6") (unit 1) (value "eSim_PNP") (footprint "")
+    )
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+    )
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+    )
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+    )
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+      (reference "Q12") (unit 1) (value "eSim_NPN") (footprint "")
+    )
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+      (reference "R1") (unit 1) (value "50k") (footprint "")
+    )
+    (path "/ba4f1b37-551a-46cc-9ffc-257aaccaaa40"
+      (reference "R2") (unit 1) (value "50k") (footprint "")
+    )
+    (path "/c3474365-4965-450b-8e1c-966ce3ed0a72"
+      (reference "R3") (unit 1) (value "2k") (footprint "")
+    )
+    (path "/e269437b-ecc6-46e4-b7f3-b8bfb7af3aa6"
+      (reference "R4") (unit 1) (value "20k") (footprint "")
+    )
+    (path "/a6b5e1f3-5bc5-43a0-8f43-2fd2ad787a80"
+      (reference "R5") (unit 1) (value "2k") (footprint "")
+    )
+    (path "/93878323-9c02-4c02-a2fd-df06981d1d4f"
+      (reference "R6") (unit 1) (value "5k") (footprint "")
+    )
+    (path "/f90cabe4-41f6-485a-ad89-d8c81f8b74af"
+      (reference "R7") (unit 1) (value "10k") (footprint "")
+    )
+    (path "/77856676-4c46-4242-a891-e4d095df7f43"
+      (reference "R8") (unit 1) (value "10k") (footprint "")
+    )
+    (path "/38e3d04c-bc09-4b9d-a26e-de8f6d4a7591"
+      (reference "U1") (unit 1) (value "PORT") (footprint "")
+    )
+    (path "/fb23a371-2bc6-44f2-af5a-cc7bd06e0a58"
+      (reference "U1") (unit 2) (value "PORT") (footprint "")
+    )
+    (path "/8f947063-20fb-4c89-b620-10b3ce575b60"
+      (reference "U1") (unit 3) (value "PORT") (footprint "")
+    )
+    (path "/7af4f8dd-3bff-43ec-8078-f86a10ed0f49"
+      (reference "U1") (unit 4) (value "PORT") (footprint "")
+    )
+    (path "/9dac605c-c4fd-4320-984f-830f3fddc608"
+      (reference "U1") (unit 5) (value "PORT") (footprint "")
+    )
+  )
+)
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.sub b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.sub
new file mode 100644
index 000000000..be4e6b746
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239.sub
@@ -0,0 +1,39 @@
+* Subcircuit lmv7239
+.subckt lmv7239 net-_m3-pad1_ net-_i1-pad2_ net-_q3-pad2_ net-_q1-pad2_ net-_i4-pad1_ 
+.title kicad schematic
+.include PNP.lib
+.include PMOS-0.5um.lib
+.include NMOS-0.5um.lib
+.include NPN.lib
+r3 net-_i1-pad2_ net-_q3-pad1_ 2k
+q6 net-_q4-pad1_ net-_i3-pad1_ net-_q11-pad2_ Q2N2907A
+r2 net-_q4-pad1_ net-_i4-pad1_ 50k
+q7 net-_q11-pad2_ net-_i4-pad2_ net-_q3-pad1_ Q2N2222
+r8 net-_m4-pad2_ net-_i4-pad1_ 10k
+r7 net-_m1-pad2_ net-_i4-pad1_ 10k
+r4 net-_q1-pad1_ net-_i4-pad1_ 20k
+q8 net-_q1-pad1_ net-_i3-pad1_ net-_q12-pad2_ Q2N2907A
+q11 net-_m1-pad2_ net-_q11-pad2_ net-_i5-pad1_ Q2N2222
+i4 net-_i4-pad1_ net-_i4-pad2_ 1m
+i5 net-_i5-pad1_ net-_i1-pad2_ 500u
+m2 net-_m1-pad1_ net-_m1-pad1_ net-_i1-pad2_ net-_i1-pad2_ mos_n W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad1_ net-_i1-pad2_ net-_i1-pad2_ mos_n W=100u L=100u M=1
+q12 net-_m4-pad2_ net-_q12-pad2_ net-_i5-pad1_ Q2N2222
+q5 net-_i3-pad1_ net-_i3-pad1_ net-_q5-pad3_ Q2N2907A
+r1 net-_q5-pad3_ net-_i4-pad1_ 50k
+i1 net-_q1-pad3_ net-_i1-pad2_ 400u
+q4 net-_q4-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
+i3 net-_i3-pad1_ net-_i1-pad2_ 300u
+i2 net-_i4-pad1_ net-_q2-pad3_ 200u
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q2-pad3_ Q2N2907A
+q2 net-_q2-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2907A
+r5 net-_i1-pad2_ net-_q2-pad1_ 2k
+q9 net-_q12-pad2_ net-_i4-pad2_ net-_q2-pad1_ Q2N2222
+r6 net-_i1-pad2_ net-_q10-pad3_ 5k
+q10 net-_i4-pad2_ net-_i4-pad2_ net-_q10-pad3_ Q2N2222
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_i4-pad1_ net-_i4-pad1_ mos_p W=100u L=100u M=1
+m4 net-_m3-pad1_ net-_m4-pad2_ net-_i4-pad1_ net-_i4-pad1_ mos_p W=100u L=100u M=1
+* Control Statements
+
+.ends lmv7239
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239_Previous_Values.xml b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239_Previous_Values.xml
new file mode 100644
index 000000000..17231b95b
--- /dev/null
+++ b/library/SubcircuitLibrary/ICLMV7239/lmv7239/lmv7239_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><i3 name="Source type">300u</i3><i5 name="Source type">500u</i5><i2 name="Source type">200u</i2><i1 name="Source type">400u</i1><i4 name="Source type">1m</i4><v1 name="Source type">5</v1><v1 name="Source type">9</v1></source><model /><devicemodel><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m3><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m1><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m4></devicemodel><subcircuit /><microcontroller /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file