diff --git a/designs/mega_board/Core9558.sch b/designs/mega_board/Core9558.sch index 3630586..e1b7c2b 100644 --- a/designs/mega_board/Core9558.sch +++ b/designs/mega_board/Core9558.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A3 16535 11693 @@ -226,14 +225,6 @@ Wire Wire Line 5000 2350 7250 2350 Wire Wire Line 7250 2350 7250 3100 -Text HLabel 5000 4000 0 50 Input ~ 0 -SPI_CS_L -Text HLabel 5000 4100 0 50 Input ~ 0 -SPI_CLK -Text HLabel 5000 4200 0 50 Input ~ 0 -SPI_MOSI -Text HLabel 5000 4300 0 50 Input ~ 0 -SPI_MISO Wire Wire Line 5000 4500 5500 4500 Wire Wire Line @@ -462,14 +453,6 @@ NoConn ~ 12050 4000 NoConn ~ 12050 4100 NoConn ~ 12050 4200 NoConn ~ 12050 4300 -NoConn ~ 12050 5200 -NoConn ~ 12050 5100 -NoConn ~ 12050 5000 -NoConn ~ 12050 4900 -NoConn ~ 12050 4800 -NoConn ~ 12050 4700 -NoConn ~ 12050 4600 -NoConn ~ 12050 4500 Text HLabel 2200 1250 0 50 Input ~ 0 5V0_2GPA NoConn ~ 5000 2350 @@ -719,8 +702,8 @@ $Comp L Core9558:Core9558 U1 U 1 1 5D47B6E1 P 8600 4950 -F 0 "U1" H 11591 4996 50 0000 L CNN -F 1 "CORE9558_V2" H 11591 4905 50 0000 L CNN +F 0 "U1" H 8550 5100 50 0000 L CNN +F 1 "CORE9558_V2" H 8350 4800 50 0000 L CNN F 2 "LibreRouter_MegaBoard:DRAGINO_CORE9558" H 8600 4600 50 0001 C CNN F 3 "DOCUMENTATION" H 8600 4700 50 0001 C CNN F 4 "DNP" H 8600 4950 50 0001 C CNN "DNP" @@ -732,4 +715,24 @@ Wire Wire Line Connection ~ 7650 3000 Wire Wire Line 7650 3000 7750 3000 +NoConn ~ 5000 4000 +NoConn ~ 5000 4100 +NoConn ~ 5000 4200 +NoConn ~ 5000 4300 +Text HLabel 12050 5200 2 50 Input ~ 0 +S17_P0_TRX0+ +Text HLabel 12050 5100 2 50 Input ~ 0 +S17_P0_TRX0- +Text HLabel 12050 5000 2 50 Input ~ 0 +S17_P0_TRX1+ +Text HLabel 12050 4900 2 50 Input ~ 0 +S17_P0_TRX1- +Text HLabel 12050 4800 2 50 Input ~ 0 +S17_P0_TRX2+ +Text HLabel 12050 4700 2 50 Input ~ 0 +S17_P0_TRX2- +Text HLabel 12050 4600 2 50 Input ~ 0 +S17_P0_TRX3+ +Text HLabel 12050 4500 2 50 Input ~ 0 +S17_P0_TRX3- $EndSCHEMATC diff --git a/designs/mega_board/LibreRouter_MegaBoard-cache.lib b/designs/mega_board/LibreRouter_MegaBoard-cache.lib index 2d8d524..b883a63 100644 --- a/designs/mega_board/LibreRouter_MegaBoard-cache.lib +++ b/designs/mega_board/LibreRouter_MegaBoard-cache.lib @@ -177,6 +177,84 @@ X Pin_6 6 300 -100 150 L 50 50 1 1 P ENDDRAW ENDDEF # +# Connector_Generic_Conn_02x05_Odd_Even +# +DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N +F0 "J" 50 300 50 H V C CNN +F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_2x??_* +$ENDFPLIST +DRAW +S -50 -195 0 -205 1 1 6 N +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 105 0 95 1 1 6 N +S -50 205 0 195 1 1 6 N +S -50 250 150 -250 1 1 10 f +S 150 -195 100 -205 1 1 6 N +S 150 -95 100 -105 1 1 6 N +S 150 5 100 -5 1 1 6 N +S 150 105 100 95 1 1 6 N +S 150 205 100 195 1 1 6 N +X Pin_1 1 -200 200 150 R 50 50 1 1 P +X Pin_10 10 300 -200 150 L 50 50 1 1 P +X Pin_2 2 300 200 150 L 50 50 1 1 P +X Pin_3 3 -200 100 150 R 50 50 1 1 P +X Pin_4 4 300 100 150 L 50 50 1 1 P +X Pin_5 5 -200 0 150 R 50 50 1 1 P +X Pin_6 6 300 0 150 L 50 50 1 1 P +X Pin_7 7 -200 -100 150 R 50 50 1 1 P +X Pin_8 8 300 -100 150 L 50 50 1 1 P +X Pin_9 9 -200 -200 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Connector_Generic_Conn_02x07_Odd_Even +# +DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N +F0 "J" 50 400 50 H V C CNN +F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_2x??_* +$ENDFPLIST +DRAW +S -50 -295 0 -305 1 1 6 N +S -50 -195 0 -205 1 1 6 N +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 105 0 95 1 1 6 N +S -50 205 0 195 1 1 6 N +S -50 305 0 295 1 1 6 N +S -50 350 150 -350 1 1 10 f +S 150 -295 100 -305 1 1 6 N +S 150 -195 100 -205 1 1 6 N +S 150 -95 100 -105 1 1 6 N +S 150 5 100 -5 1 1 6 N +S 150 105 100 95 1 1 6 N +S 150 205 100 195 1 1 6 N +S 150 305 100 295 1 1 6 N +X Pin_1 1 -200 300 150 R 50 50 1 1 P +X Pin_10 10 300 -100 150 L 50 50 1 1 P +X Pin_11 11 -200 -200 150 R 50 50 1 1 P +X Pin_12 12 300 -200 150 L 50 50 1 1 P +X Pin_13 13 -200 -300 150 R 50 50 1 1 P +X Pin_14 14 300 -300 150 L 50 50 1 1 P +X Pin_2 2 300 300 150 L 50 50 1 1 P +X Pin_3 3 -200 200 150 R 50 50 1 1 P +X Pin_4 4 300 200 150 L 50 50 1 1 P +X Pin_5 5 -200 100 150 R 50 50 1 1 P +X Pin_6 6 300 100 150 L 50 50 1 1 P +X Pin_7 7 -200 0 150 R 50 50 1 1 P +X Pin_8 8 300 0 150 L 50 50 1 1 P +X Pin_9 9 -200 -100 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# # Connector_Generic_Conn_02x13_Odd_Even # DEF Connector_Generic_Conn_02x13_Odd_Even J 0 40 Y N 1 F N @@ -583,6 +661,29 @@ X ~ 2 0 -150 50 U 50 50 1 1 P ENDDRAW ENDDEF # +# LibreRouter_MegaBoard-rescue_ATtiny13-20SSU-MCU_Microchip_ATtiny +# +DEF LibreRouter_MegaBoard-rescue_ATtiny13-20SSU-MCU_Microchip_ATtiny U 0 20 Y Y 1 F N +F0 "U" -500 550 50 H V L BNN +F1 "LibreRouter_MegaBoard-rescue_ATtiny13-20SSU-MCU_Microchip_ATtiny" 100 -550 50 H V L TNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -500 -500 500 500 0 1 10 f +X ~RESET~/PB5 1 600 -200 100 L 50 50 1 1 T +X PB3 2 600 0 100 L 50 50 1 1 T +X PB4 3 600 -100 100 L 50 50 1 1 T +X GND 4 0 -600 100 U 50 50 1 1 W +X PB0 5 600 300 100 L 50 50 1 1 T +X PB1 6 600 200 100 L 50 50 1 1 T +X PB2 7 600 100 100 L 50 50 1 1 T +X VCC 8 0 600 100 D 50 50 1 1 W +ENDDRAW +ENDDEF +# # LibreRouter_MegaBoard-rescue_Crystal_GND24_Small-Device # DEF LibreRouter_MegaBoard-rescue_Crystal_GND24_Small-Device Y 0 40 Y N 1 F N @@ -606,27 +707,18 @@ X 4 4 0 125 50 D 50 50 1 1 P ENDDRAW ENDDEF # -# MCU_Microchip_ATtiny_ATtiny13-20SSU +# Mechanical_MountingHole # -DEF MCU_Microchip_ATtiny_ATtiny13-20SSU U 0 20 Y Y 1 F N -F0 "U" -500 550 50 H V L BNN -F1 "MCU_Microchip_ATtiny_ATtiny13-20SSU" 100 -550 50 H V L TNN -F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +DEF Mechanical_MountingHole H 0 40 Y Y 1 F N +F0 "H" 0 200 50 H V C CNN +F1 "Mechanical_MountingHole" 0 125 50 H V C CNN +F2 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN -ALIAS ATtiny13-20SSU ATtiny13A-SSU $FPLIST - SOIC*3.9x4.9mm*P1.27mm* + MountingHole* $ENDFPLIST DRAW -S -500 -500 500 500 0 1 10 f -X ~RESET~/PB5 1 600 -200 100 L 50 50 1 1 T -X PB3 2 600 0 100 L 50 50 1 1 T -X PB4 3 600 -100 100 L 50 50 1 1 T -X GND 4 0 -600 100 U 50 50 1 1 W -X PB0 5 600 300 100 L 50 50 1 1 T -X PB1 6 600 200 100 L 50 50 1 1 T -X PB2 7 600 100 100 L 50 50 1 1 T -X VCC 8 0 600 100 D 50 50 1 1 W +C 0 0 50 0 1 50 N ENDDRAW ENDDEF # @@ -1039,6 +1131,24 @@ X EPAD 9 -500 -250 100 R 50 50 1 1 I ENDDRAW ENDDEF # +# Switch_SW_SPDT +# +DEF Switch_SW_SPDT SW 0 0 Y N 1 F N +F0 "SW" 0 170 50 H V C CNN +F1 "Switch_SW_SPDT" 0 -200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C -80 0 20 0 0 0 N +C 80 -100 20 0 0 0 N +C 80 100 20 0 1 0 N +P 2 0 1 0 -60 10 65 90 N +X A 1 200 100 100 L 50 50 1 1 P +X B 2 -200 0 100 R 50 50 1 1 P +X C 3 200 -100 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# # USB_HUB_FE1_1s_FE1.1s # DEF USB_HUB_FE1_1s_FE1.1s U 0 40 Y Y 1 F N diff --git a/designs/mega_board/LibreRouter_MegaBoard-rescue.lib b/designs/mega_board/LibreRouter_MegaBoard-rescue.lib index af500e6..fb68dd2 100644 --- a/designs/mega_board/LibreRouter_MegaBoard-rescue.lib +++ b/designs/mega_board/LibreRouter_MegaBoard-rescue.lib @@ -1,6 +1,29 @@ EESchema-LIBRARY Version 2.4 #encoding utf-8 # +# ATtiny13-20SSU-MCU_Microchip_ATtiny +# +DEF ATtiny13-20SSU-MCU_Microchip_ATtiny U 0 20 Y Y 1 F N +F0 "U" -500 550 50 H V L BNN +F1 "ATtiny13-20SSU-MCU_Microchip_ATtiny" 100 -550 50 H V L TNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -500 -500 500 500 0 1 10 f +X ~RESET~/PB5 1 600 -200 100 L 50 50 1 1 T +X PB3 2 600 0 100 L 50 50 1 1 T +X PB4 3 600 -100 100 L 50 50 1 1 T +X GND 4 0 -600 100 U 50 50 1 1 W +X PB0 5 600 300 100 L 50 50 1 1 T +X PB1 6 600 200 100 L 50 50 1 1 T +X PB2 7 600 100 100 L 50 50 1 1 T +X VCC 8 0 600 100 D 50 50 1 1 W +ENDDRAW +ENDDEF +# # Crystal_GND24_Small-Device # DEF Crystal_GND24_Small-Device Y 0 40 Y N 1 F N diff --git a/designs/mega_board/LibreRouter_MegaBoard.kicad_pcb b/designs/mega_board/LibreRouter_MegaBoard.kicad_pcb index 7d9df52..112e802 100644 --- a/designs/mega_board/LibreRouter_MegaBoard.kicad_pcb +++ b/designs/mega_board/LibreRouter_MegaBoard.kicad_pcb @@ -1,12 +1,12 @@ -(kicad_pcb (version 20171130) (host pcbnew 5.1.4+dfsg1-1) +(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2) (general (thickness 1.6) - (drawings 4924) - (tracks 4875) + (drawings 4920) + (tracks 3186) (zones 0) - (modules 237) - (nets 277) + (modules 259) + (nets 299) ) (page A3) @@ -18,7 +18,7 @@ (34 B.Paste user) (35 F.Paste user) (36 B.SilkS user) - (37 F.SilkS user hide) + (37 F.SilkS user) (38 B.Mask user) (39 F.Mask user) (40 Dwgs.User user) @@ -29,12 +29,12 @@ (45 Margin user) (46 B.CrtYd user) (47 F.CrtYd user) - (48 B.Fab user) - (49 F.Fab user) + (48 B.Fab user hide) + (49 F.Fab user hide) ) (setup - (last_trace_width 0.25) + (last_trace_width 2.1844) (user_trace_width 0.2032) (user_trace_width 0.254) (user_trace_width 0.3048) @@ -42,10 +42,12 @@ (user_trace_width 0.6) (user_trace_width 0.6096) (user_trace_width 0.8128) + (user_trace_width 1.016) (user_trace_width 1.6764) + (user_trace_width 2.1844) (user_trace_width 2.54) (trace_clearance 0.1524) - (zone_clearance 0.000001) + (zone_clearance 0.1524) (zone_45_only yes) (trace_min 0.127) (via_size 0.8) @@ -64,11 +66,11 @@ (mod_edge_width 0.15) (mod_text_size 1 1) (mod_text_width 0.15) - (pad_size 1.524 1.524) - (pad_drill 0.762) + (pad_size 2.999999 2.999999) + (pad_drill 2.999999) (pad_to_mask_clearance 0.051) (solder_mask_min_width 0.25) - (aux_axis_origin 0 0) + (aux_axis_origin 166.06 134.61) (visible_elements FFFFFF7F) (pcbplotparams (layerselection 0x010fc_ffffffff) @@ -81,7 +83,7 @@ (plotframeref false) (viasonmask false) (mode 1) - (useauxorigin false) + (useauxorigin true) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) @@ -94,7 +96,7 @@ (subtractmaskfromsilk false) (outputformat 1) (mirror false) - (drillshape 1) + (drillshape 0) (scaleselection 1) (outputdirectory "")) ) @@ -169,213 +171,235 @@ (net 67 "Net-(PCIE1-Pad3)") (net 68 "Net-(Q11-Pad3)") (net 69 "Net-(Q9-PadP$4)") - (net 70 "Net-(Q11-Pad1)") - (net 71 "Net-(WDT1-Pad2)") - (net 72 /pcie0/SIM_VCC) - (net 73 /pcie0/SIM_DATA) - (net 74 /pcie0/SIM_CLK) - (net 75 /pcie0/SIM_RST) - (net 76 "Net-(C5-Pad1)") - (net 77 /+3V3_PCIE) - (net 78 "Net-(C10-Pad1)") - (net 79 "Net-(C11-Pad1)") - (net 80 /+3V3) - (net 81 /+12V) - (net 82 /5V_PCIE) - (net 83 /5V_1) - (net 84 "Net-(C33-Pad1)") - (net 85 "Net-(C34-Pad1)") - (net 86 "Net-(C35-Pad1)") - (net 87 "Net-(C37-Pad1)") - (net 88 "Net-(C40-Pad1)") - (net 89 "Net-(C41-Pad1)") - (net 90 "Net-(C49-Pad1)") - (net 91 /USB_hub/USB_3.3V) - (net 92 /USB_hub/USB_1.8V) - (net 93 "Net-(C61-Pad1)") - (net 94 "Net-(C63-Pad1)") - (net 95 /5V0_2GPA) - (net 96 /POWER_EN_3.3V) - (net 97 /POWER_EN_5V) - (net 98 /GPIO17) - (net 99 /RST_B) - (net 100 /watchdog/~WR_RST) - (net 101 "Net-(C137-Pad1)") - (net 102 /EARTH) - (net 103 /GPIO16) - (net 104 /GPIO19) - (net 105 /GPIO15) - (net 106 /GPIO20) - (net 107 /GPIO14) - (net 108 /GPIO21) - (net 109 /GPIO13) - (net 110 /GPIO12) - (net 111 /UART_SOUT) - (net 112 /GPIO18) - (net 113 /UART_SIN) - (net 114 /GPIO4) - (net 115 /GPIO3) - (net 116 /WD_PCIe0_WAKE) - (net 117 /GPIO1) - (net 118 /GPIO0) - (net 119 /ethernet_frontend/AM_TRX3_N) - (net 120 /ethernet_frontend/AM_TRX3_P) - (net 121 /ethernet_frontend/AM_TRX1_N) - (net 122 /ethernet_frontend/AM_TRX2_P) - (net 123 /ethernet_frontend/AM_TRX2_N) - (net 124 /ethernet_frontend/AM_TRX1_P) - (net 125 /ethernet_frontend/AM_TRX0_P) - (net 126 /ethernet_frontend/AM_TRX0_N) - (net 127 /ethernet_frontend/BM_TRX3_N) - (net 128 /ethernet_frontend/BM_TRX3_P) - (net 129 /ethernet_frontend/BM_TRX1_N) - (net 130 /ethernet_frontend/BM_TRX2_P) - (net 131 /ethernet_frontend/BM_TRX2_N) - (net 132 /ethernet_frontend/BM_TRX1_P) - (net 133 /ethernet_frontend/BM_TRX0_P) - (net 134 /ethernet_frontend/BM_TRX0_N) - (net 135 /power_supply/12V_IN) - (net 136 /USB_hub/USB_3_P) - (net 137 /USB_hub/USB_3_N) - (net 138 /USB_hub/USB_4_P) - (net 139 /USB_hub/USB_4_N) - (net 140 /watchdog/RST_J-) - (net 141 /pcie0/LED_WLAN) - (net 142 /USB2_P) - (net 143 /USB2_N) - (net 144 "Net-(PCIE0-Pad20)") - (net 145 /pcie0/SIM_VPP) - (net 146 /PCIe_0_CLK_P) - (net 147 /PCIe_0_CLK_N) - (net 148 /CLKREQ_L_0) - (net 149 "Net-(PCIE0-Pad1)") - (net 150 "Net-(PCIE1-Pad1)") - (net 151 /CLKREQ_L_1) - (net 152 /sheet5D1650DF/SIM_VCC) - (net 153 /sheet5D1650DF/SIM_DATA) - (net 154 /PCIe_1_CLK_N) - (net 155 /sheet5D1650DF/SIM_CLK) - (net 156 /PCIe_1_CLK_P) - (net 157 /sheet5D1650DF/SIM_RST) - (net 158 /sheet5D1650DF/SIM_VPP) - (net 159 "Net-(PCIE1-Pad20)") - (net 160 "Net-(PCIE1-Pad22)") - (net 161 "Net-(PCIE1-Pad28)") - (net 162 /sheet5D1650DF/USB_N) - (net 163 "Net-(PCIE1-Pad37)") - (net 164 /sheet5D1650DF/USB_P) - (net 165 /5G_WLAN_LED_1) - (net 166 /ethernet_frontend/POE_OUT) - (net 167 /ethernet_frontend/MCT1-5) - (net 168 /ethernet_frontend/MCT2) - (net 169 /ethernet_frontend/MCT6) - (net 170 /ethernet_frontend/MCT3) - (net 171 "Net-(2G_WLAN1-Pad1)") - (net 172 /GPIO22) - (net 173 "Net-(R11-Pad1)") - (net 174 "Net-(R10-Pad2)") - (net 175 "Net-(R14-Pad2)") - (net 176 /LEDN_3) - (net 177 "Net-(P3_100-Pad1)") - (net 178 "Net-(R23-Pad1)") - (net 179 "Net-(PWR1-Pad1)") - (net 180 /12V_POE) - (net 181 "Net-(R26-Pad1)") - (net 182 "Net-(5G_WLAN1-Pad1)") - (net 183 /5G_WLAN_LED_0) - (net 184 "Net-(5G_WLAN0-Pad1)") - (net 185 /ethernet_frontend/MCT4) - (net 186 /ethernet_frontend/MCT7) - (net 187 /ethernet_frontend/MCT8) - (net 188 "Net-(R34-Pad2)") - (net 189 "Net-(R45-Pad2)") - (net 190 /WL_MISO) - (net 191 "Net-(R64-Pad2)") - (net 192 /LEDN_4) - (net 193 "Net-(P4_100-Pad1)") - (net 194 /PCIe_1_RX_N) - (net 195 /PCIe_0_RX_N) - (net 196 /PCIe_0_RX_P) - (net 197 /PCIe_0_TX_N) - (net 198 /PCIe_0_TX_P) - (net 199 /PCIe_0_RST) - (net 200 /PCIe_1_RX_P) - (net 201 /PCIe_1_TX_N) - (net 202 /PCIe_1_TX_P) - (net 203 /PCIe_1_RST) - (net 204 /LEDN1000_3) - (net 205 "Net-(P3_1000-Pad1)") - (net 206 /LEDN1000_4) - (net 207 "Net-(P4_1000-Pad1)") - (net 208 "Net-(S2-Pad4)") - (net 209 /COM_B_2G) - (net 210 /COM_A_2G) - (net 211 /S17_P3_TRX_0_P) - (net 212 /S17_P3_TRX_0_N) - (net 213 /S17_P3_TRX_1_P) - (net 214 /S17_P3_TRX_1_N) - (net 215 /S17_P3_TRX_2_P) - (net 216 /S17_P3_TRX_2_N) - (net 217 /S17_P3_TRX_3_P) - (net 218 /S17_P3_TRX_3_N) - (net 219 /S17_P4_TRX_0_P) - (net 220 /S17_P4_TRX_0_N) - (net 221 /S17_P4_TRX_1_P) - (net 222 /S17_P4_TRX_1_N) - (net 223 /S17_P4_TRX_2_P) - (net 224 /S17_P4_TRX_2_N) - (net 225 /S17_P4_TRX_3_P) - (net 226 /S17_P4_TRX_3_N) - (net 227 /WL_MOSI) - (net 228 /WL_SLK) - (net 229 /Core9558/SPI_CS_L) - (net 230 "Net-(U1-Pad104)") - (net 231 "Net-(U1-Pad103)") - (net 232 "Net-(U1-Pad102)") - (net 233 "Net-(U1-Pad101)") - (net 234 "Net-(U1-Pad100)") - (net 235 "Net-(U1-Pad99)") - (net 236 "Net-(U1-Pad74)") - (net 237 "Net-(U1-Pad73)") - (net 238 "Net-(U1-Pad72)") - (net 239 "Net-(U1-Pad71)") - (net 240 "Net-(U1-Pad70)") - (net 241 "Net-(U1-Pad69)") - (net 242 "Net-(U1-Pad68)") - (net 243 "Net-(U1-Pad67)") - (net 244 "Net-(U1-Pad66)") - (net 245 "Net-(U1-Pad65)") - (net 246 "Net-(U1-Pad64)") - (net 247 "Net-(U1-Pad63)") - (net 248 "Net-(U1-Pad62)") - (net 249 "Net-(U1-Pad61)") - (net 250 "Net-(U1-Pad60)") - (net 251 "Net-(U1-Pad59)") - (net 252 "Net-(U1-Pad57)") - (net 253 "Net-(U1-Pad56)") - (net 254 "Net-(U1-Pad55)") - (net 255 "Net-(U1-Pad54)") - (net 256 "Net-(U1-Pad53)") - (net 257 "Net-(U1-Pad52)") - (net 258 "Net-(U1-Pad51)") - (net 259 "Net-(U1-Pad50)") - (net 260 /Core9558/USB1_DM) - (net 261 /Core9558/USB1_DP) - (net 262 /GPIO23) - (net 263 /USB_hub/USB_1_P) - (net 264 /USB_hub/USB_1_N) - (net 265 /USB_hub/USB_2_P) - (net 266 /USB_hub/USB_2_N) - (net 267 "Net-(D13-Pad1)") - (net 268 "Net-(SIM_CARD_CON_6MICRO0-Pad6)") - (net 269 /pcie0/PCIe_TX_bis_P) - (net 270 /pcie0/PCIe_TX_bis_N) - (net 271 /pcie0/PCIe_RX_bis_P) - (net 272 /pcie0/PCIe_RX_bis_N) - (net 273 /sheet5D1650DF/PCIe_RX_bis_N) - (net 274 /sheet5D1650DF/PCIe_RX_bis_P) - (net 275 /sheet5D1650DF/PCIe_TX_bis_N) - (net 276 /sheet5D1650DF/PCIe_TX_bis_P) + (net 70 "Net-(WDT1-Pad2)") + (net 71 /pcie0/SIM_VCC) + (net 72 /pcie0/SIM_DATA) + (net 73 /pcie0/SIM_CLK) + (net 74 /pcie0/SIM_RST) + (net 75 "Net-(C5-Pad1)") + (net 76 /+3V3_PCIE) + (net 77 "Net-(C10-Pad1)") + (net 78 "Net-(C11-Pad1)") + (net 79 /+3V3) + (net 80 /5V_PCIE) + (net 81 /5V_1) + (net 82 "Net-(C33-Pad1)") + (net 83 "Net-(C34-Pad1)") + (net 84 "Net-(C35-Pad1)") + (net 85 "Net-(C37-Pad1)") + (net 86 "Net-(C40-Pad1)") + (net 87 "Net-(C41-Pad1)") + (net 88 "Net-(C49-Pad1)") + (net 89 /USB_hub/USB_3.3V) + (net 90 /USB_hub/USB_1.8V) + (net 91 "Net-(C61-Pad1)") + (net 92 "Net-(C63-Pad1)") + (net 93 /5V0_2GPA) + (net 94 /POWER_EN_3.3V) + (net 95 /POWER_EN_5V) + (net 96 /GPIO17) + (net 97 /RST_B) + (net 98 /watchdog/~WR_RST) + (net 99 "Net-(C137-Pad1)") + (net 100 /EARTH) + (net 101 /GPIO19) + (net 102 /GPIO20) + (net 103 /GPIO21) + (net 104 /UART_SOUT) + (net 105 /GPIO18) + (net 106 /UART_SIN) + (net 107 /GPIO4) + (net 108 /ethernet_frontend/AM_TRX3_N) + (net 109 /ethernet_frontend/AM_TRX3_P) + (net 110 /ethernet_frontend/AM_TRX1_N) + (net 111 /ethernet_frontend/AM_TRX2_P) + (net 112 /ethernet_frontend/AM_TRX2_N) + (net 113 /ethernet_frontend/AM_TRX1_P) + (net 114 /ethernet_frontend/AM_TRX0_P) + (net 115 /ethernet_frontend/AM_TRX0_N) + (net 116 /ethernet_frontend/BM_TRX3_N) + (net 117 /ethernet_frontend/BM_TRX3_P) + (net 118 /ethernet_frontend/BM_TRX1_N) + (net 119 /ethernet_frontend/BM_TRX2_P) + (net 120 /ethernet_frontend/BM_TRX2_N) + (net 121 /ethernet_frontend/BM_TRX1_P) + (net 122 /ethernet_frontend/BM_TRX0_P) + (net 123 /ethernet_frontend/BM_TRX0_N) + (net 124 /USB_hub/USB_3_P) + (net 125 /USB_hub/USB_3_N) + (net 126 /USB_hub/USB_4_P) + (net 127 /USB_hub/USB_4_N) + (net 128 /watchdog/RST_J-) + (net 129 /pcie0/LED_WLAN) + (net 130 /USB2_P) + (net 131 /USB2_N) + (net 132 "Net-(PCIE0-Pad20)") + (net 133 /pcie0/SIM_VPP) + (net 134 /PCIe_0_CLK_P) + (net 135 /PCIe_0_CLK_N) + (net 136 /CLKREQ_L_0) + (net 137 "Net-(PCIE0-Pad1)") + (net 138 "Net-(PCIE1-Pad1)") + (net 139 /CLKREQ_L_1) + (net 140 /sheet5D1650DF/SIM_VCC) + (net 141 /sheet5D1650DF/SIM_DATA) + (net 142 /PCIe_1_CLK_N) + (net 143 /sheet5D1650DF/SIM_CLK) + (net 144 /PCIe_1_CLK_P) + (net 145 /sheet5D1650DF/SIM_RST) + (net 146 /sheet5D1650DF/SIM_VPP) + (net 147 "Net-(PCIE1-Pad20)") + (net 148 "Net-(PCIE1-Pad22)") + (net 149 "Net-(PCIE1-Pad28)") + (net 150 /sheet5D1650DF/USB_N) + (net 151 "Net-(PCIE1-Pad37)") + (net 152 /sheet5D1650DF/USB_P) + (net 153 /5G_WLAN_LED_1) + (net 154 /ethernet_frontend/MCT1-5) + (net 155 /ethernet_frontend/MCT2) + (net 156 /ethernet_frontend/MCT6) + (net 157 /ethernet_frontend/MCT3) + (net 158 "Net-(2G_WLAN1-Pad1)") + (net 159 /GPIO22) + (net 160 "Net-(R11-Pad1)") + (net 161 "Net-(R10-Pad2)") + (net 162 "Net-(R14-Pad2)") + (net 163 /LEDN_3) + (net 164 "Net-(P3_100-Pad1)") + (net 165 "Net-(R23-Pad1)") + (net 166 "Net-(PWR1-Pad1)") + (net 167 "Net-(R26-Pad1)") + (net 168 "Net-(5G_WLAN1-Pad1)") + (net 169 /5G_WLAN_LED_0) + (net 170 "Net-(5G_WLAN0-Pad1)") + (net 171 /ethernet_frontend/MCT4) + (net 172 /ethernet_frontend/MCT7) + (net 173 /ethernet_frontend/MCT8) + (net 174 "Net-(R34-Pad2)") + (net 175 "Net-(R45-Pad2)") + (net 176 /WL_MISO) + (net 177 "Net-(R64-Pad2)") + (net 178 /LEDN_4) + (net 179 "Net-(P4_100-Pad1)") + (net 180 /PCIe_1_RX_N) + (net 181 /PCIe_0_RX_N) + (net 182 /PCIe_0_RX_P) + (net 183 /PCIe_0_TX_N) + (net 184 /PCIe_0_TX_P) + (net 185 /PCIe_0_RST) + (net 186 /PCIe_1_RX_P) + (net 187 /PCIe_1_TX_N) + (net 188 /PCIe_1_TX_P) + (net 189 /PCIe_1_RST) + (net 190 /LEDN1000_3) + (net 191 "Net-(P3_1000-Pad1)") + (net 192 /LEDN1000_4) + (net 193 "Net-(P4_1000-Pad1)") + (net 194 /COM_B_2G) + (net 195 /COM_A_2G) + (net 196 /S17_P3_TRX_0_P) + (net 197 /S17_P3_TRX_0_N) + (net 198 /S17_P3_TRX_1_P) + (net 199 /S17_P3_TRX_1_N) + (net 200 /S17_P3_TRX_2_P) + (net 201 /S17_P3_TRX_2_N) + (net 202 /S17_P3_TRX_3_P) + (net 203 /S17_P3_TRX_3_N) + (net 204 /S17_P4_TRX_0_P) + (net 205 /S17_P4_TRX_0_N) + (net 206 /S17_P4_TRX_1_P) + (net 207 /S17_P4_TRX_1_N) + (net 208 /S17_P4_TRX_2_P) + (net 209 /S17_P4_TRX_2_N) + (net 210 /S17_P4_TRX_3_P) + (net 211 /S17_P4_TRX_3_N) + (net 212 /WL_MOSI) + (net 213 /WL_SLK) + (net 214 "Net-(U1-Pad104)") + (net 215 "Net-(U1-Pad103)") + (net 216 "Net-(U1-Pad102)") + (net 217 "Net-(U1-Pad101)") + (net 218 "Net-(U1-Pad100)") + (net 219 "Net-(U1-Pad99)") + (net 220 "Net-(U1-Pad74)") + (net 221 "Net-(U1-Pad73)") + (net 222 "Net-(U1-Pad72)") + (net 223 "Net-(U1-Pad71)") + (net 224 "Net-(U1-Pad70)") + (net 225 "Net-(U1-Pad69)") + (net 226 "Net-(U1-Pad68)") + (net 227 "Net-(U1-Pad67)") + (net 228 "Net-(U1-Pad66)") + (net 229 "Net-(U1-Pad65)") + (net 230 "Net-(U1-Pad64)") + (net 231 "Net-(U1-Pad63)") + (net 232 "Net-(U1-Pad62)") + (net 233 "Net-(U1-Pad61)") + (net 234 "Net-(U1-Pad60)") + (net 235 "Net-(U1-Pad59)") + (net 236 /Core9558/USB1_DM) + (net 237 /Core9558/USB1_DP) + (net 238 /GPIO23) + (net 239 /USB_hub/USB_1_P) + (net 240 /USB_hub/USB_1_N) + (net 241 /USB_hub/USB_2_P) + (net 242 /USB_hub/USB_2_N) + (net 243 "Net-(D13-Pad1)") + (net 244 "Net-(SIM_CARD_CON_6MICRO0-Pad6)") + (net 245 /pcie0/PCIe_TX_bis_P) + (net 246 /pcie0/PCIe_TX_bis_N) + (net 247 /pcie0/PCIe_RX_bis_P) + (net 248 /pcie0/PCIe_RX_bis_N) + (net 249 /sheet5D1650DF/PCIe_RX_bis_N) + (net 250 /sheet5D1650DF/PCIe_RX_bis_P) + (net 251 /sheet5D1650DF/PCIe_TX_bis_N) + (net 252 /sheet5D1650DF/PCIe_TX_bis_P) + (net 253 "Net-(U1-Pad112)") + (net 254 "Net-(U1-Pad111)") + (net 255 "Net-(U1-Pad110)") + (net 256 "Net-(U1-Pad109)") + (net 257 /POE_A) + (net 258 /POE_B) + (net 259 "Net-(D27-Pad1)") + (net 260 "Net-(D28-Pad1)") + (net 261 /ethernet_frontend/POE_INJECT_CTRL) + (net 262 "Net-(Q12-PadP$4)") + (net 263 /ethernet_frontend/POE_INJECT_HARD_EN) + (net 264 /S17_P0_TRX_1_N) + (net 265 "Net-(C138-Pad1)") + (net 266 /S17_P0_TRX_1_P) + (net 267 "Net-(C139-Pad1)") + (net 268 /S17_P0_TRX_0_N) + (net 269 "Net-(C140-Pad1)") + (net 270 /S17_P0_TRX_0_P) + (net 271 "Net-(C141-Pad1)") + (net 272 /S17_P0_TRX_2_P) + (net 273 "Net-(C142-Pad1)") + (net 274 /S17_P0_TRX_2_N) + (net 275 "Net-(C143-Pad1)") + (net 276 /S17_P0_TRX_3_P) + (net 277 "Net-(C144-Pad1)") + (net 278 /S17_P0_TRX_3_N) + (net 279 "Net-(C145-Pad1)") + (net 280 "Net-(J9-Pad13)") + (net 281 "Net-(J9-Pad12)") + (net 282 "Net-(J9-Pad1)") + (net 283 "Net-(GPIO1-Pad8)") + (net 284 "Net-(GPIO1-Pad6)") + (net 285 "Net-(GPIO1-Pad4)") + (net 286 "Net-(GPIO1-Pad2)") + (net 287 "Net-(GPIO1-Pad5)") + (net 288 /GPIO16-GPS_UART_TX) + (net 289 /GPIO15-GPS_UART_RX) + (net 290 /GPIO14-PCIe1_nDISABLE) + (net 291 /GPIO13-GPS_PPS) + (net 292 /GPIO12-PCIe0_nDISABLE) + (net 293 /GPIO0-EJTAG_TCK) + (net 294 /GPIO3-EJTAG_TMS) + (net 295 /GPIO2-EJTAG_TDO) + (net 296 /GPIO1-EJTAG_TDI) + (net 297 /VCC) + (net 298 /power_supply/VCC_IN) (net_class Default "This is the default net class." (clearance 0.1524) @@ -384,10 +408,8 @@ (via_drill 0.4) (uvia_dia 0.3) (uvia_drill 0.1) - (add_net /+12V) (add_net /+3V3) (add_net /+3V3_PCIE) - (add_net /12V_POE) (add_net /5G_WLAN_LED_0) (add_net /5G_WLAN_LED_1) (add_net /5V0_2GPA) @@ -397,25 +419,25 @@ (add_net /CLKREQ_L_1) (add_net /COM_A_2G) (add_net /COM_B_2G) - (add_net /Core9558/SPI_CS_L) (add_net /Core9558/USB1_DM) (add_net /Core9558/USB1_DP) (add_net /EARTH) - (add_net /GPIO0) - (add_net /GPIO1) - (add_net /GPIO12) - (add_net /GPIO13) - (add_net /GPIO14) - (add_net /GPIO15) - (add_net /GPIO16) + (add_net /GPIO0-EJTAG_TCK) + (add_net /GPIO1-EJTAG_TDI) + (add_net /GPIO12-PCIe0_nDISABLE) + (add_net /GPIO13-GPS_PPS) + (add_net /GPIO14-PCIe1_nDISABLE) + (add_net /GPIO15-GPS_UART_RX) + (add_net /GPIO16-GPS_UART_TX) (add_net /GPIO17) (add_net /GPIO18) (add_net /GPIO19) + (add_net /GPIO2-EJTAG_TDO) (add_net /GPIO20) (add_net /GPIO21) (add_net /GPIO22) (add_net /GPIO23) - (add_net /GPIO3) + (add_net /GPIO3-EJTAG_TMS) (add_net /GPIO4) (add_net /LEDN1000_3) (add_net /LEDN1000_4) @@ -435,9 +457,19 @@ (add_net /PCIe_1_RX_P) (add_net /PCIe_1_TX_N) (add_net /PCIe_1_TX_P) + (add_net /POE_A) + (add_net /POE_B) (add_net /POWER_EN_3.3V) (add_net /POWER_EN_5V) (add_net /RST_B) + (add_net /S17_P0_TRX_0_N) + (add_net /S17_P0_TRX_0_P) + (add_net /S17_P0_TRX_1_N) + (add_net /S17_P0_TRX_1_P) + (add_net /S17_P0_TRX_2_N) + (add_net /S17_P0_TRX_2_P) + (add_net /S17_P0_TRX_3_N) + (add_net /S17_P0_TRX_3_P) (add_net /S17_P3_TRX_0_N) (add_net /S17_P3_TRX_0_P) (add_net /S17_P3_TRX_1_N) @@ -468,7 +500,7 @@ (add_net /USB_hub/USB_3_P) (add_net /USB_hub/USB_4_N) (add_net /USB_hub/USB_4_P) - (add_net /WD_PCIe0_WAKE) + (add_net /VCC) (add_net /WL_MISO) (add_net /WL_MOSI) (add_net /WL_SLK) @@ -495,7 +527,8 @@ (add_net /ethernet_frontend/MCT6) (add_net /ethernet_frontend/MCT7) (add_net /ethernet_frontend/MCT8) - (add_net /ethernet_frontend/POE_OUT) + (add_net /ethernet_frontend/POE_INJECT_CTRL) + (add_net /ethernet_frontend/POE_INJECT_HARD_EN) (add_net /pcie0/LED_WLAN) (add_net /pcie0/PCIe_RX_bis_N) (add_net /pcie0/PCIe_RX_bis_P) @@ -506,7 +539,7 @@ (add_net /pcie0/SIM_RST) (add_net /pcie0/SIM_VCC) (add_net /pcie0/SIM_VPP) - (add_net /power_supply/12V_IN) + (add_net /power_supply/VCC_IN) (add_net /sheet5D1650DF/PCIe_RX_bis_N) (add_net /sheet5D1650DF/PCIe_RX_bis_P) (add_net /sheet5D1650DF/PCIe_TX_bis_N) @@ -531,6 +564,14 @@ (add_net "Net-(C13-Pad1)") (add_net "Net-(C13-Pad2)") (add_net "Net-(C137-Pad1)") + (add_net "Net-(C138-Pad1)") + (add_net "Net-(C139-Pad1)") + (add_net "Net-(C140-Pad1)") + (add_net "Net-(C141-Pad1)") + (add_net "Net-(C142-Pad1)") + (add_net "Net-(C143-Pad1)") + (add_net "Net-(C144-Pad1)") + (add_net "Net-(C145-Pad1)") (add_net "Net-(C16-Pad1)") (add_net "Net-(C16-Pad2)") (add_net "Net-(C21-Pad1)") @@ -558,10 +599,20 @@ (add_net "Net-(C66-Pad1)") (add_net "Net-(C66-Pad2)") (add_net "Net-(D13-Pad1)") + (add_net "Net-(D27-Pad1)") + (add_net "Net-(D28-Pad1)") + (add_net "Net-(GPIO1-Pad2)") + (add_net "Net-(GPIO1-Pad4)") + (add_net "Net-(GPIO1-Pad5)") + (add_net "Net-(GPIO1-Pad6)") + (add_net "Net-(GPIO1-Pad8)") (add_net "Net-(J5-Pad10)") (add_net "Net-(J5-Pad11)") (add_net "Net-(J5-Pad12)") (add_net "Net-(J5-Pad9)") + (add_net "Net-(J9-Pad1)") + (add_net "Net-(J9-Pad12)") + (add_net "Net-(J9-Pad13)") (add_net "Net-(P3_100-Pad1)") (add_net "Net-(P3_1000-Pad1)") (add_net "Net-(P4_100-Pad1)") @@ -601,8 +652,8 @@ (add_net "Net-(PCIE1-Pad5)") (add_net "Net-(PCIE1-Pad6)") (add_net "Net-(PWR1-Pad1)") - (add_net "Net-(Q11-Pad1)") (add_net "Net-(Q11-Pad3)") + (add_net "Net-(Q12-PadP$4)") (add_net "Net-(Q9-PadP$4)") (add_net "Net-(R10-Pad2)") (add_net "Net-(R11-Pad1)") @@ -622,21 +673,16 @@ (add_net "Net-(R83-Pad1)") (add_net "Net-(R84-Pad2)") (add_net "Net-(R86-Pad1)") - (add_net "Net-(S2-Pad4)") (add_net "Net-(SIM_CARD_CON_6MICRO0-Pad6)") (add_net "Net-(U1-Pad100)") (add_net "Net-(U1-Pad101)") (add_net "Net-(U1-Pad102)") (add_net "Net-(U1-Pad103)") (add_net "Net-(U1-Pad104)") - (add_net "Net-(U1-Pad50)") - (add_net "Net-(U1-Pad51)") - (add_net "Net-(U1-Pad52)") - (add_net "Net-(U1-Pad53)") - (add_net "Net-(U1-Pad54)") - (add_net "Net-(U1-Pad55)") - (add_net "Net-(U1-Pad56)") - (add_net "Net-(U1-Pad57)") + (add_net "Net-(U1-Pad109)") + (add_net "Net-(U1-Pad110)") + (add_net "Net-(U1-Pad111)") + (add_net "Net-(U1-Pad112)") (add_net "Net-(U1-Pad59)") (add_net "Net-(U1-Pad60)") (add_net "Net-(U1-Pad61)") @@ -662,1069 +708,1057 @@ (add_net "Net-(WDT1-Pad2)") ) - (module LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON (layer Top) (tedit 5DF0F220) (tstamp 5D66DB48) - (at 101.6127 78.9813) - (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 7.7 mm

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(fp_line (start -0.542 -5.0677) (end -0.542 -4.0108) (layer F.SilkS) (width 0.1016)) - (fp_line (start -2.439 -5.0677) (end -0.542 -5.0677) (layer F.SilkS) (width 0.1016)) - (fp_line (start -2.439 4.9051) (end -2.439 -5.0677) (layer F.Fab) (width 0.1016)) - (pad 54 thru_hole circle (at 24.5 -47.7 270) (size 6.2 6.2) (drill 4.09) (layers *.Cu *.Mask) - (solder_mask_margin 0.0508)) - (pad 53 thru_hole circle (at 0.2 -47.7 270) (size 6.2 6.2) (drill 4.09) (layers *.Cu *.Mask) - (solder_mask_margin 0.0508)) - (pad "" np_thru_hole circle (at 25 0 270) (size 1.1 1.1) (drill 1.1) (layers *.Cu *.Mask)) - (pad "" np_thru_hole circle (at 0 0 270) (size 1.55 1.55) (drill 1.55) (layers *.Cu *.Mask)) - (pad M2 smd rect (at -2.2 3.5 270) (size 2.3 3.2) (layers Top F.Paste F.Mask) - (solder_mask_margin 0.0508)) - (pad 52 smd rect (at 24.3 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 51 smd rect (at 23.9 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) - (pad 50 smd rect (at 23.5 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 49 smd rect (at 23.1 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) - (pad 48 smd rect (at 22.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 41 "Net-(PCIE0-Pad48)") (solder_mask_margin 0.0508)) - (pad 47 smd rect (at 22.3 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 42 "Net-(PCIE0-Pad47)") (solder_mask_margin 0.0508)) - (pad 46 smd rect (at 21.9 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 43 "Net-(PCIE0-Pad46)") (solder_mask_margin 0.0508)) - (pad 45 smd rect (at 21.5 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 44 "Net-(PCIE0-Pad45)") (solder_mask_margin 0.0508)) - (pad 44 smd rect (at 21.1 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 141 /pcie0/LED_WLAN) (solder_mask_margin 0.0508)) - (pad 43 smd rect (at 20.7 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 42 smd rect (at 20.3 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 45 "Net-(PCIE0-Pad42)") (solder_mask_margin 0.0508)) - (pad 41 smd rect (at 19.9 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 40 smd rect (at 19.5 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 39 smd rect (at 19.1 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 38 smd rect (at 18.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 142 /USB2_P) (solder_mask_margin 0.0508)) - (pad 37 smd rect (at 18.3 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 46 "Net-(PCIE0-Pad37)") (solder_mask_margin 0.0508)) - (pad 36 smd rect (at 17.9 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 143 /USB2_N) (solder_mask_margin 0.0508)) - (pad 35 smd rect (at 17.5 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 34 smd rect (at 17.1 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 33 smd rect (at 16.7 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 269 /pcie0/PCIe_TX_bis_P) (solder_mask_margin 0.0508)) - (pad 32 smd rect (at 16.3 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 47 "Net-(PCIE0-Pad32)") (solder_mask_margin 0.0508)) - (pad 31 smd rect (at 15.9 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 270 /pcie0/PCIe_TX_bis_N) (solder_mask_margin 0.0508)) - (pad 30 smd rect (at 15.5 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 48 "Net-(PCIE0-Pad30)") (solder_mask_margin 0.0508)) - (pad 29 smd rect (at 15.1 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 28 smd rect (at 14.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 49 "Net-(PCIE0-Pad28)") (solder_mask_margin 0.0508)) - (pad 27 smd rect (at 14.3 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 26 smd rect (at 13.9 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 25 smd rect (at 13.5 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 271 /pcie0/PCIe_RX_bis_P) (solder_mask_margin 0.0508)) - (pad 24 smd rect (at 13.1 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 23 smd rect (at 12.7 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 272 /pcie0/PCIe_RX_bis_N) (solder_mask_margin 0.0508)) - (pad 22 smd rect (at 12.3 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 50 "Net-(PCIE0-Pad22)") (solder_mask_margin 0.0508)) - (pad 21 smd rect (at 11.9 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 20 smd rect (at 11.5 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 144 "Net-(PCIE0-Pad20)") (solder_mask_margin 0.0508)) - (pad 19 smd rect (at 11.1 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 51 "Net-(PCIE0-Pad19)") (solder_mask_margin 0.0508)) - (pad 18 smd rect (at 10.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 17 smd rect (at 10.3 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 52 "Net-(PCIE0-Pad17)") (solder_mask_margin 0.0508)) - (pad 16 smd rect (at 6.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 145 /pcie0/SIM_VPP) (solder_mask_margin 0.0508)) - (pad 15 smd rect (at 6.2 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 14 smd rect (at 5.9 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 75 /pcie0/SIM_RST) (solder_mask_margin 0.0508)) - (pad 13 smd rect (at 5.4 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 146 /PCIe_0_CLK_P) (solder_mask_margin 0.0508)) - (pad 12 smd rect (at 5.1 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 74 /pcie0/SIM_CLK) (solder_mask_margin 0.0508)) - (pad 11 smd rect (at 4.6 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 147 /PCIe_0_CLK_N) (solder_mask_margin 0.0508)) - (pad 10 smd rect (at 4.3 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 73 /pcie0/SIM_DATA) (solder_mask_margin 0.0508)) - (pad 9 smd rect (at 3.8 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 8 smd rect (at 3.5 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 72 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) - (pad 7 smd rect (at 3 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 148 /CLKREQ_L_0) (solder_mask_margin 0.0508)) - (pad 6 smd rect (at 2.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 53 "Net-(PCIE0-Pad6)") (solder_mask_margin 0.0508)) - (pad 5 smd rect (at 2.2 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 54 "Net-(PCIE0-Pad5)") (solder_mask_margin 0.0508)) - (pad 4 smd rect (at 1.9 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 1.4 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 55 "Net-(PCIE0-Pad3)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 1.1 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 0.6 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) - (net 149 "Net-(PCIE0-Pad1)") (solder_mask_margin 0.0508)) - (pad M1 smd rect (at 27.15 3.5 270) (size 2.3 3.2) (layers Top F.Paste F.Mask) - (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696B1) - (at 221.9237 170.0924) - (path /5D032DC8/5D47E794) - (fp_text reference D11 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C1206 (layer Top) (tedit 5E693595) (tstamp 5E694AD9) + (at 124.27204 55.16626 270) + (descr "CAPACITOR

\nchip") + (path /5D46D273) + (fp_text reference C20 (at -2.77876 -0.37846 270) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) + (fp_text value "47uF, 6.3V" (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 220 /S17_P4_TRX_0_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 219 /S17_P4_TRX_0_P) (solder_mask_margin 0.0508)) + (fp_line (start 2 -1) (end 1.75 -1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.5 1) (end 1.75 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.5 -1) (end 2.5 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2 -1) (end 2.5 -1) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 1) (end -1.75 1) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -1) (end -2.5 1) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.75 -1) (end -2.5 -1) (layer F.SilkS) (width 0.12)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.473 -0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 -0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1.4 0 270) (size 1.6 1.8) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1.4 0 270) (size 1.6 1.8) (layers Top F.Paste F.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696A8) - (at 224.9463 170.0924) - (path /5D032DC8/5D47E751) - (fp_text reference D10 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C1206 (layer Bottom) (tedit 5E693595) (tstamp 5DE3D907) + (at 244.48126 96.41208 180) + (descr "CAPACITOR

\nchip") + (path /5D46CAA5) + (fp_text reference C39 (at -5.0585 -0.28572) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) + (fp_text value "47uF, 6.3V" (at 0 0 180) (layer B.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom mirror)) ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 222 /S17_P4_TRX_1_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 221 /S17_P4_TRX_1_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D66970F) - (at 231.0931 170.0924) - (path /5D032DC8/5D47A51B) - (fp_text reference D9 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) - ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 226 /S17_P4_TRX_3_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 225 /S17_P4_TRX_3_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D669706) - (at 228.0451 170.0924) - (path /5D032DC8/5D47CF73) - (fp_text reference D8 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) - ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 224 /S17_P4_TRX_2_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 223 /S17_P4_TRX_2_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696FD) - (at 209.6047 170.0924) - (path /5D032DC8/5D482062) - (fp_text reference D7 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) - ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 212 /S17_P3_TRX_0_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 211 /S17_P3_TRX_0_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696F4) - (at 212.7035 170.0924) - (path /5D032DC8/5D48201F) - (fp_text reference D6 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) - ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 214 /S17_P3_TRX_1_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 213 /S17_P3_TRX_1_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696EB) - (at 218.8503 170.0924) - (path /5D032DC8/5D481F99) - (fp_text reference D4 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) - ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 218 /S17_P3_TRX_3_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 217 /S17_P3_TRX_3_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696E2) - (at 215.8023 170.0924) - (path /5D032DC8/5D481FDC) - (fp_text reference D3 (at -1.27 -1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide - (effects (font (size 0.77216 0.77216) (thickness 0.06096))) - ) - (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 216 /S17_P3_TRX_2_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) - (net 215 /S17_P3_TRX_2_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:POWER_JACK_SLOT (layer Top) (tedit 5DF101DF) (tstamp 5D669718) - (at 114.0753 223.788) - (path /5D1DA32E) - (fp_text reference J1 (at -6.35 7.62 90) (layer F.SilkS) - (effects (font (size 1.6891 1.6891) (thickness 0.135128)) (justify left bottom)) - ) - (fp_text value 12V_JACK (at 7.62 7.62 90) (layer F.Fab) - (effects (font (size 1.6891 1.6891) (thickness 0.135128)) (justify left bottom)) - ) - (fp_line (start -4.5 4.52) (end 4.5 4.52) (layer F.SilkS) (width 0.2032)) - (fp_line (start 4.5 4.52) (end 4.5 -6.2) (layer F.SilkS) (width 0.2032)) - (fp_line (start -4.5 -6.2) (end -4.5 4.52) (layer F.SilkS) (width 0.2032)) - (fp_line (start 4.5 7.5) (end -4.5 7.5) (layer F.Fab) (width 0.2032)) - (fp_line (start 4.5 7.5) (end 4.5 4.52) (layer F.Fab) (width 0.2032)) - (fp_line (start -4.5 4.52) (end -4.5 7.5) (layer F.Fab) (width 0.2032)) - (fp_line (start 4.5 -6.2) (end -4.5 -6.2) (layer F.SilkS) (width 0.2032)) - (pad 3 thru_hole oval (at 4.7 -3.5 90) (size 5.08 2.54) (drill 1) (layers *.Cu *.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 2 thru_hole oval (at 0 0) (size 5.08 2.54) (drill 1) (layers *.Cu *.Mask) + (fp_line (start 2 1) (end 1.75 1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2.5 -1) (end 1.75 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2.5 1) (end 2.5 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2 1) (end 2.5 1) (layer B.SilkS) (width 0.12)) + (fp_line (start -2.5 -1) (end -1.75 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start -2.5 1) (end -2.5 -1) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.75 1) (end -2.5 1) (layer B.SilkS) (width 0.12)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy 0.9517 -0.8491) (xy 1.7018 -0.8491) (xy 1.7018 0.8509) (xy 0.9517 0.8509)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy -1.7018 -0.8509) (xy -0.9517 -0.8509) (xy -0.9517 0.8491) (xy -1.7018 0.8491)) (layer B.Fab) (width 0)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer B.Fab) (width 0.1016)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer B.Fab) (width 0.1016)) + (fp_line (start 2.473 0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 -0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 -0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1.4 0 180) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 thru_hole oval (at 0.04 -6.2) (size 5.08 2.54) (drill 1) (layers *.Cu *.Mask) - (net 135 /power_supply/12V_IN) (solder_mask_margin 0.0508) (zone_connect 2)) + (pad 1 smd rect (at -1.4 0 180) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SIM-MICRO-PUSH (layer Bottom) (tedit 5DF0FEB4) (tstamp 5DF23F5B) - (at 131.62744 49.67008) - (path /5D0C3185) - (fp_text reference SIM_CARD_CON_6MICRO0 (at -1.16 6.34) (layer B.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left top mirror)) + (module LibreRouter_MegaBoard:C1206 (layer Bottom) (tedit 5E693595) (tstamp 5D66A118) + (at 236.68228 195.30568) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D4FF644) + (fp_text reference C49 (at -2.69748 -0.24638 180) (layer B.SilkS) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left top mirror)) ) - (fp_text value SIM_Card (at 0 0) (layer B.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror)) + (fp_text value "10nF, 2KV" (at -2.15138 -0.41148 180) (layer B.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left top mirror)) ) - (fp_line (start 0.25 -4.5) (end 0.25 -2.1) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.75 -5.1) (end 0.25 -4.5) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.25 -2) (end 0.25 -1.6) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.75 -2.62) (end 0.25 -2) (layer B.SilkS) (width 0.127)) - (fp_line (start 15.3 -2.8) (end 15.3 -0.4) (layer B.SilkS) (width 0.127)) - (fp_line (start 13.1 -5) (end 15.3 -2.8) (layer B.SilkS) (width 0.127)) - (fp_line (start 15.3 -0.3) (end 15.3 0.3) (layer B.SilkS) (width 0.127)) - (fp_line (start 13 -2.6) (end 15.3 -0.3) (layer B.SilkS) (width 0.127)) - (fp_line (start 15.3 0.3) (end 15.3 2.1) (layer B.SilkS) (width 0.127)) - (fp_line (start 13.1 -1.9) (end 15.3 0.3) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.5 -1.92) (end 0.25 -1.62) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.7 -1.92) (end 0.5 -1.92) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.75 -5.12) (end 13.01 -5.12) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.75 -2.62) (end 13.01 -2.62) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.75 -1.92) (end 13.01 -1.92) (layer B.SilkS) (width 0.127)) - (fp_line (start 15.55 15.78) (end 15.55 -1.62) (layer B.SilkS) (width 0.127)) - (fp_line (start 11.43 15.78) (end 15.55 15.78) (layer B.SilkS) (width 0.127)) - (fp_line (start 11.43 13.98) (end 11.43 15.78) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.25 13.98) (end 11.43 13.98) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.25 -1.6) (end 0.25 -1.62) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.25 13.98) (end 0.25 -1.6) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.25 -1.62) (end 15.55 -1.62) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy 2.1 8.62) (xy 3.8 8.62) (xy 3.8 11.62) (xy 2.1 11.62)) (layer Dwgs.User) (width 0)) - (fp_poly (pts (xy 4.64 8.62) (xy 6.34 8.62) (xy 6.34 11.62) (xy 4.64 11.62)) (layer Dwgs.User) (width 0)) - (fp_poly (pts (xy 7.18 8.62) (xy 8.88 8.62) (xy 8.88 11.62) (xy 7.18 11.62)) (layer Dwgs.User) (width 0)) - (fp_poly (pts (xy 7.18 0.7) (xy 8.88 0.7) (xy 8.88 3.7) (xy 7.18 3.7)) (layer Dwgs.User) (width 0)) - (fp_poly (pts (xy 4.64 0.7) (xy 6.34 0.7) (xy 6.34 3.7) (xy 4.64 3.7)) (layer Dwgs.User) (width 0)) - (fp_poly (pts (xy 2.1 0.7) (xy 3.8 0.7) (xy 3.8 3.7) (xy 2.1 3.7)) (layer Dwgs.User) (width 0)) - (pad 4 smd rect (at 0.25 12.58) (size 1.2 2.999999) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at 15.55 12.58) (size 1.2 2.999999) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at 15.8 0) (size 1.55 2.6) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at 0 0) (size 1.55 2.6) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 7.91 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) - (net 74 /pcie0/SIM_CLK) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 5.37 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) - (net 75 /pcie0/SIM_RST) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 2.83 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) - (net 72 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) - (pad 5 smd rect (at 1.56 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (fp_line (start 2 1) (end 1.75 1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2.5 -1) (end 1.75 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2.5 1) (end 2.5 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2 1) (end 2.5 1) (layer B.SilkS) (width 0.12)) + (fp_line (start -2.5 -1) (end -1.75 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start -2.5 1) (end -2.5 -1) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.75 1) (end -2.5 1) (layer B.SilkS) (width 0.12)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy 0.9517 -0.8491) (xy 1.7018 -0.8491) (xy 1.7018 0.8509) (xy 0.9517 0.8509)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy -1.7018 -0.8509) (xy -0.9517 -0.8509) (xy -0.9517 0.8491) (xy -1.7018 0.8491)) (layer B.Fab) (width 0)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer B.Fab) (width 0.1016)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer B.Fab) (width 0.1016)) + (fp_line (start 2.473 0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 -0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 -0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1.4 0) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 6 smd rect (at 4.1 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) - (net 268 "Net-(SIM_CARD_CON_6MICRO0-Pad6)") (solder_mask_margin 0.0508)) - (pad 7 smd rect (at 6.64 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) - (net 73 /pcie0/SIM_DATA) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:TEST_POINT_0.8MM (layer Bottom) (tedit 5DF0F968) (tstamp 5DE3D95B) - (at 224.29724 80.264 180) - (path /5D158FCC) - (fp_text reference TP2 (at 0 0) (layer B.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror)) - ) - (fp_text value TEST-POINT0.8MM (at 0 0) (layer B.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror)) - ) - (pad 1 smd roundrect (at 0 0 180) (size 0.8 0.8) (layers Bottom B.Mask) (roundrect_rratio 0.5) - (net 151 /CLKREQ_L_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1.4 0) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) + (net 88 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:TEST_POINT_0.8MM (layer Top) (tedit 5DF0F968) (tstamp 5D66A025) - (at 108.5127 58.0784 90) - (path /5D13FB87) - (fp_text reference TP1 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) + (module LibreRouter_MegaBoard:C1206 (layer Bottom) (tedit 5E693595) (tstamp 5D66DB81) + (at 239.94872 182.1053 180) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D6301C9) + (fp_text reference C40 (at 1.00584 1.2319) (layer B.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom mirror)) ) - (fp_text value TEST-POINT0.8MM (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) + (fp_text value "10nF, 2KV" (at -1.27 -2.413) (layer B.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom mirror)) ) - (pad 1 smd roundrect (at 0 0 90) (size 0.8 0.8) (layers Top F.Mask) (roundrect_rratio 0.5) - (net 148 /CLKREQ_L_0) (solder_mask_margin 0.0508)) + (fp_line (start 2 1) (end 1.75 1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2.5 -1) (end 1.75 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2.5 1) (end 2.5 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start 2 1) (end 2.5 1) (layer B.SilkS) (width 0.12)) + (fp_line (start -2.5 -1) (end -1.75 -1) (layer B.SilkS) (width 0.12)) + (fp_line (start -2.5 1) (end -2.5 -1) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.75 1) (end -2.5 1) (layer B.SilkS) (width 0.12)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy 0.9517 -0.8491) (xy 1.7018 -0.8491) (xy 1.7018 0.8509) (xy 0.9517 0.8509)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy -1.7018 -0.8509) (xy -0.9517 -0.8509) (xy -0.9517 0.8491) (xy -1.7018 0.8491)) (layer B.Fab) (width 0)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer B.Fab) (width 0.1016)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer B.Fab) (width 0.1016)) + (fp_line (start 2.473 0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 -0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 -0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1.4 0 180) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1.4 0 180) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) + (net 86 "Net-(C40-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:TEST_POINT_0.8MM (layer Top) (tedit 5DF0F968) (tstamp 5D66A19E) - (at 118.7743 116.3206) - (path /5D801B21) - (fp_text reference TP3 (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) + (module LibreRouter_MegaBoard:C1206 (layer Top) (tedit 5E693595) (tstamp 5E171412) + (at 239.28324 202.24496 180) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D63CAC9) + (fp_text reference C41 (at -1.94056 -2.60604) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) ) - (fp_text value TEST-POINT0.8MM (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) + (fp_text value "10nF, 2KV" (at -1.27 2.413) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) ) - (pad 1 smd roundrect (at 0 0) (size 0.8 0.8) (layers Top F.Mask) (roundrect_rratio 0.5) - (net 116 /WD_PCIe0_WAKE) (solder_mask_margin 0.0508)) + (fp_line (start 2 -1) (end 1.75 -1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.5 1) (end 1.75 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.5 -1) (end 2.5 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2 -1) (end 2.5 -1) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 1) (end -1.75 1) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -1) (end -2.5 1) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.75 -1) (end -2.5 -1) (layer F.SilkS) (width 0.12)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) + (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.473 -0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 2.473 0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -2.473 -0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1.4 0 180) (size 1.6 1.8) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1.4 0 180) (size 1.6 1.8) (layers Top F.Paste F.Mask) + (net 87 "Net-(C41-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5348A) - (at 192.498162 53.49624 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D44A5FE) - (fp_text reference P4_1000 (at -3.22698 3.53444) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module LibreRouter_MegaBoard:MINI-PCI-E-FULL (layer Bottom) (tedit 5D71604F) (tstamp 5DE3DABE) + (at 221.89316 87.11574) + (path /5D1650F5/5D19C7E9) + (fp_text reference PCIE1 (at -2.94008 5.96002) (layer B.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top mirror)) ) - (fp_text value 3mm/GREEN (at -6.4223 3.316) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (fp_text value f5521gw (at -2.8334 8.79466) (layer B.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top mirror)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 207 "Net-(P4_1000-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE536B7) - (at 182.69086 53.49624 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D44B725) - (fp_text reference 5G_WLAN0 (at -3.87214 3.53444) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (fp_line (start -2.54 50.8) (end -2.54 45.72) (layer B.SilkS) (width 0.127)) + (fp_line (start 27.3 50.8) (end 27.3 45.72) (layer B.SilkS) (width 0.127)) + (fp_line (start -2.54 50.8) (end 27.3 50.8) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy 24.14 3.9295) (xy 24.4652 3.9295) (xy 24.4652 4.7695) (xy 24.14 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 23.34 3.9295) (xy 23.6652 3.9295) (xy 23.6652 4.7695) (xy 23.34 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 22.54 3.9295) (xy 22.8652 3.9295) (xy 22.8652 4.7695) (xy 22.54 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 21.74 3.9295) (xy 22.0652 3.9295) (xy 22.0652 4.7695) (xy 21.74 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 20.94 3.9295) (xy 21.2652 3.9295) (xy 21.2652 4.7695) (xy 20.94 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 20.14 3.9295) (xy 20.4652 3.9295) (xy 20.4652 4.7695) (xy 20.14 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 19.34 3.9295) (xy 19.6652 3.9295) (xy 19.6652 4.7695) (xy 19.34 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 18.54 3.9295) (xy 18.8652 3.9295) (xy 18.8652 4.7695) (xy 18.54 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 17.74 3.9295) (xy 18.0652 3.9295) (xy 18.0652 4.7695) (xy 17.74 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 16.94 3.9295) (xy 17.2652 3.9295) (xy 17.2652 4.7695) (xy 16.94 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 16.14 3.9295) (xy 16.4652 3.9295) (xy 16.4652 4.7695) (xy 16.14 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 15.34 3.9295) (xy 15.6652 3.9295) (xy 15.6652 4.7695) (xy 15.34 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 14.54 3.9295) (xy 14.8652 3.9295) (xy 14.8652 4.7695) (xy 14.54 4.7695)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 13.74 3.9295) (xy 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5.0677) (layer B.SilkS) (width 0.1016)) + (fp_line (start -2.439 -4.9051) (end -2.439 5.0677) (layer B.Fab) (width 0.1016)) + (pad 54 thru_hole circle (at 24.5 47.7) (size 6.2 6.2) (drill 4.09) (layers *.Cu *.Mask) + (solder_mask_margin 0.0508)) + (pad 53 thru_hole circle (at 0.2 47.7) (size 6.2 6.2) (drill 4.09) (layers *.Cu *.Mask) + (solder_mask_margin 0.0508)) + (pad "" np_thru_hole circle (at 25 0) (size 1.1 1.1) (drill 1.1) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 0 0) (size 1.55 1.55) (drill 1.55) (layers *.Cu *.Mask)) + (pad M2 smd rect (at -2.2 -3.5) (size 2.3 3.2) (layers Bottom B.Paste B.Mask) + (solder_mask_margin 0.0508)) + (pad 52 smd rect (at 24.3 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 51 smd rect (at 23.9 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) + (pad 50 smd rect (at 23.5 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 49 smd rect (at 23.1 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) + (pad 48 smd rect (at 22.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 56 "Net-(PCIE1-Pad48)") (solder_mask_margin 0.0508)) + (pad 47 smd rect (at 22.3 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 57 "Net-(PCIE1-Pad47)") (solder_mask_margin 0.0508)) + (pad 46 smd rect (at 21.9 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 58 "Net-(PCIE1-Pad46)") (solder_mask_margin 0.0508)) + (pad 45 smd rect (at 21.5 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 59 "Net-(PCIE1-Pad45)") (solder_mask_margin 0.0508)) + (pad 44 smd rect (at 21.1 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 153 /5G_WLAN_LED_1) (solder_mask_margin 0.0508)) + (pad 43 smd rect (at 20.7 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 42 smd rect (at 20.3 4.1) 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"Net-(PCIE1-Pad20)") (solder_mask_margin 0.0508)) + (pad 19 smd rect (at 11.1 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 63 "Net-(PCIE1-Pad19)") (solder_mask_margin 0.0508)) + (pad 18 smd rect (at 10.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 17 smd rect (at 10.3 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 64 "Net-(PCIE1-Pad17)") (solder_mask_margin 0.0508)) + (pad 16 smd rect (at 6.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 146 /sheet5D1650DF/SIM_VPP) (solder_mask_margin 0.0508)) + (pad 15 smd rect (at 6.2 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 14 smd rect (at 5.9 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 145 /sheet5D1650DF/SIM_RST) (solder_mask_margin 0.0508)) + (pad 13 smd rect (at 5.4 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 144 /PCIe_1_CLK_P) (solder_mask_margin 0.0508)) + (pad 12 smd rect (at 5.1 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 143 /sheet5D1650DF/SIM_CLK) (solder_mask_margin 0.0508)) + (pad 11 smd rect (at 4.6 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 142 /PCIe_1_CLK_N) (solder_mask_margin 0.0508)) + (pad 10 smd rect (at 4.3 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 141 /sheet5D1650DF/SIM_DATA) (solder_mask_margin 0.0508)) + (pad 9 smd rect (at 3.8 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 8 smd rect (at 3.5 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 140 /sheet5D1650DF/SIM_VCC) (solder_mask_margin 0.0508)) + (pad 7 smd rect (at 3 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 139 /CLKREQ_L_1) (solder_mask_margin 0.0508)) + (pad 6 smd rect (at 2.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 65 "Net-(PCIE1-Pad6)") (solder_mask_margin 0.0508)) + (pad 5 smd rect (at 2.2 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 66 "Net-(PCIE1-Pad5)") (solder_mask_margin 0.0508)) + (pad 4 smd rect (at 1.9 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 1.4 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 67 "Net-(PCIE1-Pad3)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 1.1 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0.6 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (net 138 "Net-(PCIE1-Pad1)") (solder_mask_margin 0.0508)) + (pad M1 smd rect (at 27.15 -3.5) (size 2.3 3.2) (layers Bottom B.Paste B.Mask) + (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:CUI_PJ-002A_noedge (layer Top) (tedit 5E68FE4F) (tstamp 5E6A80B8) + (at 114.1222 217.5764 270) + (path /5D1DA32E) + (fp_text reference J1 (at -2.0193 -4.3434 180) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09))) + ) + (fp_text value DC_IN_JACK (at 2.48793 5.78184 90) (layer F.SilkS) + (effects (font (size 1.00118 1.00118) (thickness 0.05))) + ) + (fp_line (start -1.55 2.35) (end -1 2.35) (layer Eco1.User) (width 0.05)) + (fp_line (start -1.55 -2.25) (end -1.55 2.35) (layer Eco1.User) (width 0.05)) + (fp_line (start -1 -2.25) (end -1.55 -2.25) (layer Eco1.User) (width 0.05)) + (fp_line (start -1 -2.25) (end -1 -4.75) (layer Eco1.User) (width 0.05)) + (fp_circle (center -2 0) (end -1.8 0) (layer F.SilkS) (width 0.4)) + (fp_line (start -1 4.75) (end -1 2.35) (layer Eco1.User) (width 0.05)) + (fp_line (start 14 4.75) (end -1 4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 14 -4.75) (end 14 4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 5.55 -4.75) (end 14 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 5.55 -6.1) (end 5.55 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 0.45 -6.1) (end 5.55 -6.1) (layer Eco1.User) (width 0.05)) + (fp_line (start 0.45 -4.75) (end 0.45 -6.1) (layer Eco1.User) (width 0.05)) + (fp_line (start -1 -4.75) (end 0.45 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start -0.7 -2.55) (end -0.7 -4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 5.55 -4.5) (end 13.7 -4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7 4.5) (end -0.7 2.65) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7 -4.5) (end 0.45 -4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 13.7 4.5) (end -0.7 4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 13.7 -4.5) (end 13.7 4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7 4.5) (end -0.7 -4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start 13.7 4.5) (end -0.7 4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start 13.7 -4.5) (end 13.7 4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start -0.7 -4.5) (end 13.7 -4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start 0.5 -1.75) (end 0.5 1.75) (layer F.Mask) (width 0.0001)) + (pad 3 thru_hole oval (at 3 -4.7 90) (size 4.5 2.25) (drill oval 3.5 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 2 thru_hole oval (at 6 0) (size 4.5 2.25) (drill oval 3.5 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 1 thru_hole oval (at 0 0) (size 5 2.5) (drill oval 3.7 1) (layers *.Cu *.Mask) + (net 298 /power_supply/VCC_IN)) + ) + + (module Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Vertical (layer Top) (tedit 59FED5CC) (tstamp 5E170C66) + (at 147.72386 196.68236) + (descr "Through hole straight pin header, 2x05, 2.54mm pitch, double rows") + (tags "Through hole pin header THT 2x05 2.54mm double row") + (path /5E373917) + (fp_text reference J6 (at 1.27 -2.33) (layer F.SilkS) + (effects (font (size 1.2 1.2) (thickness 0.15))) + ) + (fp_text value "Hack ETH" (at 1.27 12.49) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 1.27 5.08 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 4.35 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.35 11.95) (end 4.35 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 11.95) (end 4.35 11.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 -1.8) (end -1.8 11.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.27 -1.33) (end 3.87 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.27 1.27) (end 1.27 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.87 -1.33) (end 3.87 11.49) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 11.49) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 11.49) (end 3.87 11.49) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 11.43) (end -1.27 0) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 11.43) (end -1.27 11.43) (layer F.Fab) (width 0.1)) + (fp_line (start 3.81 -1.27) (end 3.81 11.43) (layer F.Fab) (width 0.1)) + (fp_line (start 0 -1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1)) + (pad 10 thru_hole oval (at 2.54 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 9 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 279 "Net-(C145-Pad1)")) + (pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 271 "Net-(C141-Pad1)")) + (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 277 "Net-(C144-Pad1)")) + (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 269 "Net-(C140-Pad1)")) + (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 275 "Net-(C143-Pad1)")) + (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 267 "Net-(C139-Pad1)")) + (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 273 "Net-(C142-Pad1)")) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 265 "Net-(C138-Pad1)")) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x05_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_text value 3mm/BLUE (at -5.2793 3.316) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + ) + + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E172568) + (at 154.29992 204.29728) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5EA54CF5) + (attr smd) + (fp_text reference C145 (at 0.20066 -1.17348) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 278 /S17_P0_TRX_3_N)) + (pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 279 "Net-(C145-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 184 "Net-(5G_WLAN0-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE534D2) - (at 212.112766 53.49624 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D4489EC) - (fp_text reference PWR1 (at -2.31766 3.53444) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E16B65A) + (at 154.29992 201.75728) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5EA54CFB) + (attr smd) + (fp_text reference C144 (at 0.22352 -1.16078) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 276 /S17_P0_TRX_3_P)) + (pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 277 "Net-(C144-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_text value 3mm/RED (at -4.3903 3.57) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + ) + + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E16B649) + (at 154.29992 199.22998) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5EA54D01) + (attr smd) + (fp_text reference C143 (at 0.20574 -1.1811) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 274 /S17_P0_TRX_2_N)) + (pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 275 "Net-(C143-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 179 "Net-(PWR1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C461) - (at 207.209115 61.17212 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D44A60F) - (fp_text reference 2G_WLAN1 (at -5.286074 3.44808) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E16B638) + (at 154.29992 196.69252) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5EA54D07) + (attr smd) + (fp_text reference C142 (at 0.16256 -1.17856) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 272 /S17_P0_TRX_2_P)) + (pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 273 "Net-(C142-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_text value 3mm/GREEN (at 1.905 1.651) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) - ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 171 "Net-(2G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C2C9) - (at 197.401813 61.10608 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D449D05) - (fp_text reference P3_100 (at -2.285487 3.38204) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E17234B) + (at 143.67002 204.30236 180) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5E8BC398) + (attr smd) + (fp_text reference C141 (at -0.22352 1.17094) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 270 /S17_P0_TRX_0_P)) + (pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 271 "Net-(C141-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_text value 3mm/RED (at -4.6443 3.57) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) - ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 177 "Net-(P3_100-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE53442) - (at 202.305464 53.49624 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D449F09) - (fp_text reference P3_1000 (at -3.4505 3.53444) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) - ) - (fp_text value 3mm/BLUE (at -5.4063 3.316) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E16B616) + (at 143.67002 201.76236 180) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5E8BC037) + (attr smd) + (fp_text reference C140 (at -0.19304 1.16078) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 268 /S17_P0_TRX_0_N)) + (pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 269 "Net-(C140-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 205 "Net-(P3_1000-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C371) - (at 217.01642 61.17212 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D44A631) - (fp_text reference 5G_WLAN1 (at -5.5333 3.44808) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E16B605) + (at 143.67002 199.22236 180) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5E8BBD4D) + (attr smd) + (fp_text reference C139 (at 0.03302 1.17856) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 266 /S17_P0_TRX_1_P)) + (pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 267 "Net-(C139-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_text value 3mm/GREEN (at 1.905 1.651) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + ) + + (module Capacitor_SMD:C_0603_1608Metric (layer Top) (tedit 5B301BBE) (tstamp 5E16B5F4) + (at 144.46758 195.88988 90) + (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5E888C1B) + (attr smd) + (fp_text reference C138 (at 0.08128 -1.18618 270) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) + ) + (fp_text value 33nF (at 0 1.43 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.06))) + ) + (fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.7875 0 90) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 264 /S17_P0_TRX_1_N)) + (pad 1 smd roundrect (at -0.7875 0 90) (size 0.875 0.95) (layers Top F.Paste F.Mask) (roundrect_rratio 0.25) + (net 265 "Net-(C138-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 182 "Net-(5G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C3B9) - (at 187.594511 61.10608 180) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D449EF8) - (fp_text reference P4_100 (at -2.34814 3.38204) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D5D) + (at 129.20218 195.13804 180) + (descr "RESISTOR

\nchip") + (path /5D032896/5D4B35F0) + (fp_text reference R81 (at -1.07442 1.38684) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 3mm/RED (at -4.6443 3.316) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (fp_text value "2.7k 1%" (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 193 "Net-(P4_100-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 36 "Net-(R81-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5D66A358) - (at 84.1287 171.591 90) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D44BE4E) - (fp_text reference STATUS1 (at 1.905 -0.381) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module LibreRouter_MegaBoard:EG1213 (layer Top) (tedit 5E162B36) (tstamp 5E16C0C5) + (at 241.51082 226.20478) + (path /5E2D65CF) + (fp_text reference SW1 (at -4.03352 -3.61188) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SW_SPDT (at 0 -2.794) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.5 6.9) (end 2.5 1.9) (layer F.Fab) (width 0.15)) + (fp_line (start -2.5 6.9) (end 2.5 6.9) (layer F.Fab) (width 0.15)) + (fp_line (start -2.5 1.9) (end -2.5 6.9) (layer F.Fab) (width 0.15)) + (fp_line (start -5 1.9) (end -5 -1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 1.9) (end -5 1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 -1.9) (end 5 1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start -5 -1.9) (end 5 -1.9) (layer F.SilkS) (width 0.15)) + (pad S thru_hole circle (at 4.85 0) (size 1.4 1.4) (drill 1.4) (layers *.Cu *.Mask)) + (pad S thru_hole circle (at -4.85 0) (size 1.4 1.4) (drill 1.4) (layers *.Cu *.Mask)) + (pad 3 thru_hole circle (at 2 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) + (net 79 /+3V3)) + (pad 2 thru_hole circle (at 0 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) + (net 263 /ethernet_frontend/POE_INJECT_HARD_EN)) + (pad 1 thru_hole circle (at -2 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) + (net 1 GND)) + ) + + (module LibreRouter_MegaBoard:R0603 (layer Top) (tedit 0) (tstamp 5E16F44E) + (at 240.6142 198.5772) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5E611D93) + (fp_text reference R127 (at 4.9149 0.6096 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 3mm/GREEN (at 1.905 1.651 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + (fp_text value "0 1/10W" (at -1.651 1.778 180) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 178 "Net-(R23-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 262 /GPIO23) (solder_mask_margin 0.0508)) + (fp_line (start 1.651 0.762) (end 0.889 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.889 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.762) (end -0.889 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.889 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.8382 0.4318) (xy -0.4318 0.4318) (xy -0.4318 -0.4318) (xy -0.8382 -0.4318)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4318 0.4318) (xy 0.8382 0.4318) (xy 0.8382 -0.4318) (xy 0.4318 -0.4318)) (layer F.Fab) (width 0)) + (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 0.432 -0.356) (end -0.432 -0.356) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.432 0.356) (end 0.432 0.356) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.85 0) (size 1 1.1) (layers Top F.Paste F.Mask) + (net 258 /POE_B) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.85 0) (size 1 1.1) (layers Top F.Paste F.Mask) + (net 156 /ethernet_frontend/MCT6) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5D66A380) - (at 92.1297 171.591 90) - (descr "LED

\n3 mm, round") - (path /5D032C56/5D44A620) - (fp_text reference USB_LED1 (at 1.905 -0.381) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E16F489) + (at 239.43564 187.6806) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5E611D9D) + (fp_text reference R126 (at 1.17856 0.6604) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 3mm/BLUE (at 1.905 1.651 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + (fp_text value 68k (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) - (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) - (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) - (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) - (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) - (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) - (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) - (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) - (pad 1 thru_hole circle (at 1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 181 "Net-(R26-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 262 "Net-(Q12-PadP$4)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 261 /ethernet_frontend/POE_INJECT_CTRL) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:UD-6,3X5,8_NICHICON (layer Top) (tedit 5DF0F2BC) (tstamp 5D669565) - (at 112.1195 203.3918 90) - (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 5.8 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") - (path /5D032896/5D48969C) - (fp_text reference C55 (at -3.175 -3.81) (layer F.SilkS) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E16F411) + (at 241.9096 187.67806) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5E611DA7) + (fp_text reference R125 (at 4.1275 -0.39116) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "100uF, 16V" (at -3.175 4.445 90) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) + (fp_text value 100k (at -1.41732 1.48082) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_poly (pts (xy -2.2 -2.15) (xy -2.200001 -2.149999) (xy -2.439523 -1.873329) (xy -2.644527 -1.570195) - (xy -2.812117 -1.24488) (xy -2.939926 -0.901978) (xy -3.026149 -0.546334) (xy -3.069567 -0.182973) - (xy -3.069567 0.182974) (xy -3.026149 0.546336) (xy -2.939926 0.901979) (xy -2.812116 1.244881) - (xy -2.644526 1.570196) (xy -2.439522 1.87333) (xy -2.2 2.15)) (layer F.Fab) (width 0)) - (fp_circle (center 0 0) (end 3.1001 0) (layer F.Fab) (width 0.1016)) - (fp_arc (start 0.002365 0.0051) (end 3 0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 3.25) (end -3.25 0.7) (layer F.SilkS) (width 0.1016)) - (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.SilkS) (width 0.1016)) - (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.SilkS) (width 0.1016)) - (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 -0.8) (end -3.25 -3.25) (layer F.SilkS) (width 0.1016)) - (fp_arc (start -0.002365 -0.0051) (end -3 -0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 3.25) (end -3.25 -3.25) (layer F.Fab) (width 0.1016)) - (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.Fab) (width 0.1016)) - (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.Fab) (width 0.1016)) - (fp_line (start 3.25 -2.45) (end 3.25 2.45) (layer F.Fab) (width 0.1016)) - (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.Fab) (width 0.1016)) - (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.Fab) (width 0.1016)) - (pad 1 smd rect (at 2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON (layer Bottom) (tedit 5DF0F220) (tstamp 5DE4A0A2) - (at 245.7958 73.2282 270) - (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 7.7 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") - (path /5D1650F5/5D1D8CB3) - (fp_text reference C43 (at 2.31022 -6.27256) (layer B.SilkS) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left top mirror)) - ) - (fp_text value 470uF (at 5.91702 -4.0272 270) (layer B.Fab) hide - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify right top mirror)) - ) - (fp_poly (pts (xy -2.2 2.15) (xy -2.200001 2.149999) (xy -2.439523 1.873329) (xy -2.644527 1.570195) - (xy -2.812117 1.24488) (xy -2.939926 0.901978) (xy -3.026149 0.546334) (xy -3.069567 0.182973) - (xy -3.069567 -0.182974) (xy -3.026149 -0.546336) (xy -2.939926 -0.901979) (xy -2.812116 -1.244881) - (xy -2.644526 -1.570196) (xy -2.439522 -1.87333) (xy -2.2 -2.15)) (layer B.Fab) (width 0)) - (fp_circle (center 0 0) (end 3.1001 0) (layer B.Fab) (width 0.1016)) - (fp_arc (start 0.002365 -0.0051) (end 3 -0.775) (angle -149.753145) (layer B.SilkS) (width 0.1016)) - (fp_line (start -3.25 -3.25) (end -3.25 -0.7) (layer B.SilkS) (width 0.1016)) - (fp_line (start 2.45 -3.25) (end -3.25 -3.25) (layer B.SilkS) (width 0.1016)) - (fp_line (start 3.25 -2.45) (end 2.45 -3.25) (layer B.SilkS) (width 0.1016)) - (fp_line (start 2.45 3.25) (end 3.25 2.45) (layer B.SilkS) (width 0.1016)) - (fp_line (start -3.25 3.25) (end 2.45 3.25) (layer B.SilkS) (width 0.1016)) - (fp_line (start -3.25 0.8) (end -3.25 3.25) (layer B.SilkS) (width 0.1016)) - (fp_arc (start -0.002365 0.0051) (end -3 0.775) (angle -149.753145) (layer B.SilkS) (width 0.1016)) - (fp_line (start -3.25 -3.25) (end -3.25 3.25) (layer B.Fab) (width 0.1016)) - (fp_line (start 2.45 -3.25) (end -3.25 -3.25) (layer B.Fab) (width 0.1016)) - (fp_line (start 3.25 -2.45) (end 2.45 -3.25) (layer B.Fab) (width 0.1016)) - (fp_line (start 3.25 2.45) (end 3.25 -2.45) (layer B.Fab) (width 0.1016)) - (fp_line (start 2.45 3.25) (end 3.25 2.45) (layer B.Fab) (width 0.1016)) - (fp_line (start -3.25 3.25) (end 2.45 3.25) (layer B.Fab) (width 0.1016)) - (pad 1 smd rect (at 2.35 0 270) (size 2.799999 1) (layers Bottom B.Paste B.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -2.35 0 270) (size 2.799999 1) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON (layer Top) (tedit 5DF0F220) (tstamp 5DF93AC9) - (at 101.90734 56.75376 90) - (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 7.7 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") - (path /5D2A0A2B) - (fp_text reference C18 (at -3.175 -3.81 270) (layer F.SilkS) - (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left top)) - ) - (fp_text value 470uF (at -7.9121 -1.98374 270) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left top)) - ) - (fp_poly (pts (xy -2.2 -2.15) (xy -2.200001 -2.149999) (xy -2.439523 -1.873329) (xy -2.644527 -1.570195) - (xy -2.812117 -1.24488) (xy -2.939926 -0.901978) (xy -3.026149 -0.546334) (xy -3.069567 -0.182973) - (xy -3.069567 0.182974) (xy -3.026149 0.546336) (xy -2.939926 0.901979) (xy -2.812116 1.244881) - (xy -2.644526 1.570196) (xy -2.439522 1.87333) (xy -2.2 2.15)) (layer F.Fab) (width 0)) - (fp_circle (center 0 0) (end 3.1001 0) (layer F.Fab) (width 0.1016)) - (fp_arc (start 0.002365 0.0051) (end 3 0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 3.25) (end -3.25 0.7) (layer F.SilkS) (width 0.1016)) - (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.SilkS) (width 0.1016)) - (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.SilkS) (width 0.1016)) - (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 -0.8) (end -3.25 -3.25) (layer F.SilkS) (width 0.1016)) - (fp_arc (start -0.002365 -0.0051) (end -3 -0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) - (fp_line (start -3.25 3.25) (end -3.25 -3.25) (layer F.Fab) (width 0.1016)) - (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.Fab) (width 0.1016)) - (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.Fab) (width 0.1016)) - (fp_line (start 3.25 -2.45) (end 3.25 2.45) (layer F.Fab) (width 0.1016)) - (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.Fab) (width 0.1016)) - (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.Fab) (width 0.1016)) - (pad 1 smd rect (at 2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:DO214AC (layer Top) (tedit 5DF0F09D) (tstamp 5D6696D8) - (at 90.8597 203.2394) - (descr "DO-214AA GULL-WING

\nSource: www.rsonline.de .. SMBJ12/C/15/C/24/C/30/C/5.0/C/7.5/C Voltage Suppressor. Data Sheet") - (path /5D0328DE/5D503196) - (fp_text reference D2 (at -1.905 -2.54) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value SS14 (at -1.905 3.81) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) - ) - (fp_poly (pts (xy -1.37 1.4) (xy -0.36 1.4) (xy -0.36 -1.4) (xy -1.37 -1.4)) (layer F.Fab) (width 0)) - (fp_line (start -2.24 -1.4) (end 2.24 -1.4) (layer F.SilkS) (width 0.1016)) - (fp_line (start -2.24 1.4) (end -2.24 -1.4) (layer F.SilkS) (width 0.1016)) - (fp_line (start 2.24 1.4) (end -2.24 1.4) (layer F.SilkS) (width 0.1016)) - (fp_line (start 2.24 -1.4) (end 2.24 1.4) (layer F.SilkS) (width 0.1016)) - (pad 2 smd rect (at 2.13 0 180) (size 1.45 1.8) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -2.13 0) (size 1.45 1.8) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 259 "Net-(D27-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 262 "Net-(Q12-PadP$4)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:E3,5-10 (layer Top) (tedit 5DF0F07C) (tstamp 5D669668) - (at 81.8935 206.9224 180) - (descr "ELECTROLYTIC CAPACITOR

\ngrid 3.5 mm, diameter 10 mm") - (path /5D0328DE/5D503338) - (fp_text reference C76 (at 4.064 -3.429 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.077216)) (justify right top)) + (module LibreRouter_MegaBoard:SI4435 (layer Top) (tedit 0) (tstamp 5E16F3DF) + (at 243.3701 193.3067 270) + (path /5D032DC8/5E611DC0) + (fp_text reference Q12 (at -3.0099 -3.0099) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value "1000uF, 35V" (at -3.302 3.048) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) + (fp_text value Si4435DDY-T1 (at -2.6 4.3 270) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) ) - (fp_poly (pts (xy 0.254 1.27) (xy 0.762 1.27) (xy 0.762 -1.27) (xy 0.254 -1.27)) (layer F.Fab) (width 0)) - (fp_circle (center 0 0) (end 5.08 0) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0.635 0) (end 1.651 0) (layer F.Fab) (width 0.1524)) - (fp_line (start -0.762 -1.27) (end -0.762 0) (layer F.Fab) (width 0.1524)) - (fp_line (start -0.254 -1.27) (end -0.762 -1.27) (layer F.Fab) (width 0.1524)) - (fp_line (start -0.254 1.27) (end -0.254 -1.27) (layer F.Fab) (width 0.1524)) - (fp_line (start -0.762 1.27) (end -0.254 1.27) (layer F.Fab) (width 0.1524)) - (fp_line (start -0.762 0) (end -0.762 1.27) (layer F.Fab) (width 0.1524)) - (fp_line (start -1.651 0) (end -0.762 0) (layer F.Fab) (width 0.1524)) - (fp_line (start -3.048 -0.762) (end -3.048 -1.524) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.429 -1.143) (end -2.667 -1.143) (layer F.SilkS) (width 0.1524)) - (pad 1 thru_hole circle (at -1.778 0 180) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at 1.778 0 180) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_circle (center -3.9878 -1.9558) (end -3.6576 -1.9558) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -1.2 2.5) (xy 3.65 2.5) (xy 3.65 -2.5) (xy -1.2 -2.5)) (layer Dwgs.User) (width 0)) + (fp_line (start -3.4 2.7) (end -3.4 -2.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.6 2.7) (end -3.4 2.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.6 -2.7) (end 3.6 2.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.4 -2.7) (end 3.6 -2.7) (layer F.SilkS) (width 0.127)) + (pad P$8 smd rect (at 2.52725 -1.9305 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 258 /POE_B) (solder_mask_margin 0.0508)) + (pad P$7 smd rect (at 2.52725 -0.635 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 258 /POE_B) (solder_mask_margin 0.0508)) + (pad P$6 smd rect (at 2.52725 0.635 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 258 /POE_B) (solder_mask_margin 0.0508)) + (pad P$5 smd rect (at 2.52725 1.905 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 258 /POE_B) (solder_mask_margin 0.0508)) + (pad P$4 smd rect (at -2.66 1.905 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) + (net 262 "Net-(Q12-PadP$4)") (solder_mask_margin 0.0508)) + (pad P$3 smd rect (at -2.66 0.635 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) + (net 259 "Net-(D27-Pad1)") (solder_mask_margin 0.0508)) + (pad P$2 smd rect (at -2.66 -0.635 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) + (net 259 "Net-(D27-Pad1)") (solder_mask_margin 0.0508)) + (pad P$1 smd rect (at -2.66 -1.905 270) (size 1.98 0.568) (layers Top F.Paste F.Mask) + (net 259 "Net-(D27-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:GR72-135 (layer Top) (tedit 5DF0F038) (tstamp 5D6697ED) - (at 83.6461 219.851 90) - (path /5D0328DE/5D503666) - (fp_text reference L1 (at -6.64 -1.78 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5E16F1B9) + (at 241.0714 169.4942 180) + (descr DIODE) + (path /5D032DC8/5E485211) + (fp_text reference D28 (at -7.1247 -0.5334 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value "4A, GR30-400" (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) + (fp_text value MBRS540T3 (at -3.459 4.629) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) ) - (fp_line (start 4.8 -1.5) (end 4.8 1.4) (layer F.Fab) (width 0.127)) - (fp_line (start -5 -1.5) (end -5 1.4) (layer F.Fab) (width 0.127)) - (fp_line (start -5 -1.5) (end -6.9 -1.5) (layer F.Fab) (width 0.127)) - (fp_line (start 4.8 -1.5) (end -5 -1.5) (layer F.Fab) (width 0.127)) - (fp_line (start 6.9 -1.5) (end 4.8 -1.5) (layer F.Fab) (width 0.127)) - (fp_line (start 6.9 1.5) (end 6.9 -1.5) (layer F.Fab) (width 0.127)) - (fp_line (start -6.9 1.5) (end 6.9 1.5) (layer F.Fab) (width 0.127)) - (fp_line (start -6.9 -1.5) (end -6.9 1.5) (layer F.Fab) (width 0.127)) - (pad 1 thru_hole circle (at 2.5 0 90) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -2.5 0 90) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) - (net 267 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) + (fp_poly (pts (xy -2.1 3.1) (xy -0.85 3.1) (xy -0.85 -3.1) (xy -2.1 -3.1)) (layer F.SilkS) (width 0)) + (fp_poly (pts (xy 3.5606 1.0922) (xy 4.094 1.0922) (xy 4.094 -1.0922) (xy 3.5606 -1.0922)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.094 1.0922) (xy -3.5606 1.0922) (xy -3.5606 -1.0922) (xy -4.094 -1.0922)) (layer F.Fab) (width 0)) + (fp_line (start 0.543 1) (end 0.543 -1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.83 0) (end 0.543 1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.543 -1) (end -0.83 0) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.5606 3.105) (end 3.5606 -3.105) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.5606 3.105) (end -3.5606 -3.105) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.5606 3.105) (end 3.5606 3.105) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.5606 -3.105) (end 3.5606 -3.105) (layer F.SilkS) (width 0.1016)) + (pad 2 smd rect (at 3.7 0 180) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.7 0 180) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 260 "Net-(D28-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5D6696BA) - (at 92.4853 216.041) + (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5E16AE0E) + (at 241.0714 162.56 180) (descr DIODE) - (path /5D0328DE/5D502FE5) - (fp_text reference D13 (at -3.459 -3.359) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D032DC8/5E611DCD) + (fp_text reference D27 (at -7.1755 -0.6985 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value MBRS540T3 (at -3.459 4.629) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) ) (fp_poly (pts (xy -2.1 3.1) (xy -0.85 3.1) (xy -0.85 -3.1) (xy -2.1 -3.1)) (layer F.SilkS) (width 0)) (fp_poly (pts (xy 3.5606 1.0922) (xy 4.094 1.0922) (xy 4.094 -1.0922) (xy 3.5606 -1.0922)) (layer F.Fab) (width 0)) @@ -1736,18 +1770,18 @@ (fp_line (start -3.5606 3.105) (end -3.5606 -3.105) (layer F.Fab) (width 0.1016)) (fp_line (start -3.5606 3.105) (end 3.5606 3.105) (layer F.SilkS) (width 0.1016)) (fp_line (start -3.5606 -3.105) (end 3.5606 -3.105) (layer F.SilkS) (width 0.1016)) - (pad 2 smd rect (at 3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) - (net 180 /12V_POE) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) - (net 267 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 3.7 0 180) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.7 0 180) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 259 "Net-(D27-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5D6696C9) - (at 92.5107 222.5688) + (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5E16ADFE) + (at 92.20708 215.68094) (descr DIODE) - (path /5D0328DE/5D5033BC) - (fp_text reference D14 (at -3.459 -3.359 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D0328DE/5E6FC475) + (fp_text reference D26 (at -5.51688 1.00646 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_text value MBRS540T3 (at -3.459 4.629) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) @@ -1763,4053 +1797,4379 @@ (fp_line (start -3.5606 3.105) (end 3.5606 3.105) (layer F.SilkS) (width 0.1016)) (fp_line (start -3.5606 -3.105) (end 3.5606 -3.105) (layer F.SilkS) (width 0.1016)) (pad 2 smd rect (at 3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) - (net 135 /power_supply/12V_IN) (solder_mask_margin 0.0508)) + (net 258 /POE_B) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) - (net 267 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:DO-214AA (layer Top) (tedit 5DF0EF3B) (tstamp 5D66DB9D) - (at 91.2407 206.643) - (path /5D0328DE/5D5030DB) - (fp_text reference D25 (at -3.4 -1.8) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) - ) - (fp_text value SMBJ40CA (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -0.8 -1.2) (end -0.8 1.2) (layer F.SilkS) (width 0.4064)) - (fp_line (start 2.2 -1.4) (end -2.2 -1.4) (layer F.SilkS) (width 0.127)) - (fp_line (start 2.2 1.4) (end 2.2 -1.4) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.2 1.4) (end 2.2 1.4) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.2 -1.4) (end -2.2 1.4) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 2.11 0 90) (size 2.18 1.62) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -2.11 0 90) (size 2.18 1.62) (layers Top F.Paste F.Mask) - (net 267 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:BC301N-D (layer Top) (tedit 5DF0EDF6) (tstamp 5D669EB2) - (at 91.0375 209.9958) - (path /5D0328DE/5D504AD9) - (fp_text reference V1 (at -2.286 -2.032) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) - ) - (fp_text value BC301N-D (at 0 0 180) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify left top)) - ) - (fp_line (start 2.25 -1.6) (end -2.25 -1.6) (layer F.SilkS) (width 0.127)) - (fp_line (start 2.25 1.6) (end 2.25 -1.6) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.25 1.6) (end 2.25 1.6) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.25 -1.6) (end -2.25 1.6) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 2.25 0 90) (size 3.500001 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -2.25 0 90) (size 3.500001 1.4) (layers Top F.Paste F.Mask) - (net 267 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A28F) - (at 135.6907 220.486 270) - (path /5D57E8BF) - (fp_text reference D5 (at -1.27 1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify right bottom)) - ) - (fp_text value ESD7951ST5G (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 136 /USB_hub/USB_3_P) (solder_mask_margin 0.0508)) + (net 243 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A298) - (at 135.6907 218.835 90) - (path /5D57E8C6) - (fp_text reference D17 (at -1.27 1.27 270) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left top)) + (module LibreRouter_MegaBoard:QT48103 (layer Top) (tedit 0) (tstamp 5D669E0D) + (at 220.9463 180.3286 270) + (path /5D032DC8/5D45306C) + (fp_text reference T1 (at -6.1 -14.1 270) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) ) - (fp_text value ESD7951ST5G (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify left top)) + (fp_text value QT48A03 (at -6.2 15.3 270) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) ) - (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 137 /USB_hub/USB_3_N) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A2A1) - (at 142.2947 210.58 180) - (path /5D5E3160) - (fp_text reference D18 (at -1.27 1.27) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) - ) - (fp_text value ESD7951ST5G (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0.45 0 180) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.45 0 180) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A2AA) - (at 135.6907 217.057 270) - (path /5D4BB44C) - (fp_text reference D12 (at -1.27 1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) - ) - (fp_text value ESD7951ST5G (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 138 /USB_hub/USB_4_P) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A2B3) - (at 135.6907 215.533 90) - (path /5D4BB8A3) - (fp_text reference D15 (at -1.27 1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) - ) - (fp_text value ESD7951ST5G (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify left top)) - ) - (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) - (net 139 /USB_hub/USB_4_N) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D6697FA) - (at 96.3715 180.0238 90) - (path /5D0328DE/5D4FE12B/5D42D3B9) - (fp_text reference L3 (at -3.27 2 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 13 "Net-(C30-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D669803) - (at 91.1391 139.841 90) - (path /5D0328DE/5D4FEB2F/5D42D3B9) - (fp_text reference L4 (at -3.27 2) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 18 "Net-(C62-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D66980C) - (at 90.6565 100.6996 90) - (path /5D0328DE/5D42E225/5D42D3B9) - (fp_text reference L8 (at -3.27 2) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 3 "Net-(C12-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D66A085) - (at 89.6683 59.2468 90) - (path /5D0328DE/5D42CD47/5D42D3B9) - (fp_text reference L2 (at -3.27 2) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 8 "Net-(C13-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D66DAC5) - (at 96.7017 89.676) - (path /5D0328DE/5D4FC17D/5D42D3B9) - (fp_text reference L5 (at -3.27 2) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) - ) - (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) - (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 0 2.25) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at 0 -2.25) (size 5.7 1.7) (layers Top F.Paste F.Mask) - (net 23 "Net-(C21-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D66994F) - (at 224.4949 207.4558 270) - (path /5D032DC8/5D47AAF5) - (fp_text reference P1 (at -5 -3 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) - ) - (fp_text value 3R420L (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) - ) - (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 120 /ethernet_frontend/AM_TRX3_P) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0 0 270) (size 2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 119 /ethernet_frontend/AM_TRX3_N) (solder_mask_margin 0.0508)) + (fp_circle (center -5.3 -11.6) (end -5 -11.6) (layer F.SilkS) (width 0.4064)) + (fp_line (start -6.1 13.85) (end -6.1 -13.85) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.1 13.85) (end -6.1 13.85) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.1 -13.85) (end 6.1 13.85) (layer F.SilkS) (width 0.127)) + (fp_line (start -6.1 -13.85) (end 6.1 -13.85) (layer F.SilkS) (width 0.127)) + (pad 48 smd rect (at 7.27 -11.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 154 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) + (pad 47 smd rect (at 7.27 -10.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 108 /ethernet_frontend/AM_TRX3_N) (solder_mask_margin 0.0508)) + (pad 46 smd rect (at 7.27 -9.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 109 /ethernet_frontend/AM_TRX3_P) (solder_mask_margin 0.0508)) + (pad 45 smd rect (at 7.27 -8.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 155 /ethernet_frontend/MCT2) (solder_mask_margin 0.0508)) + (pad 44 smd rect (at 7.27 -7.57 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 112 /ethernet_frontend/AM_TRX2_N) (solder_mask_margin 0.0508)) + (pad 43 smd rect (at 7.27 -6.55 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 111 /ethernet_frontend/AM_TRX2_P) (solder_mask_margin 0.0508)) + (pad 42 smd rect (at 7.27 -5.53 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 157 /ethernet_frontend/MCT3) (solder_mask_margin 0.0508)) + (pad 41 smd rect (at 7.27 -4.51 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 110 /ethernet_frontend/AM_TRX1_N) (solder_mask_margin 0.0508)) + (pad 40 smd rect (at 7.27 -3.49 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 113 /ethernet_frontend/AM_TRX1_P) (solder_mask_margin 0.0508)) + (pad 39 smd rect (at 7.27 -2.47 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 171 /ethernet_frontend/MCT4) (solder_mask_margin 0.0508)) + (pad 38 smd rect (at 7.27 -1.45 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 115 /ethernet_frontend/AM_TRX0_N) (solder_mask_margin 0.0508)) + (pad 37 smd rect (at 7.27 -0.43 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 114 /ethernet_frontend/AM_TRX0_P) (solder_mask_margin 0.0508)) + (pad 36 smd rect (at 7.27 0.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 154 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) + (pad 35 smd rect (at 7.27 1.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 116 /ethernet_frontend/BM_TRX3_N) (solder_mask_margin 0.0508)) + (pad 34 smd rect (at 7.27 2.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 117 /ethernet_frontend/BM_TRX3_P) (solder_mask_margin 0.0508)) + (pad 33 smd rect (at 7.27 3.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 156 /ethernet_frontend/MCT6) (solder_mask_margin 0.0508)) + (pad 32 smd rect (at 7.27 4.67 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 120 /ethernet_frontend/BM_TRX2_N) (solder_mask_margin 0.0508)) + (pad 31 smd rect (at 7.27 5.69 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 119 /ethernet_frontend/BM_TRX2_P) (solder_mask_margin 0.0508)) + (pad 30 smd rect (at 7.27 6.71 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 172 /ethernet_frontend/MCT7) (solder_mask_margin 0.0508)) + (pad 29 smd rect (at 7.27 7.73 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 118 /ethernet_frontend/BM_TRX1_N) (solder_mask_margin 0.0508)) + (pad 28 smd rect (at 7.27 8.75 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 121 /ethernet_frontend/BM_TRX1_P) (solder_mask_margin 0.0508)) + (pad 27 smd rect (at 7.27 9.77 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 173 /ethernet_frontend/MCT8) (solder_mask_margin 0.0508)) + (pad 26 smd rect (at 7.27 10.77 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 123 /ethernet_frontend/BM_TRX0_N) (solder_mask_margin 0.0508)) + (pad 25 smd rect (at 7.27 11.81 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 122 /ethernet_frontend/BM_TRX0_P) (solder_mask_margin 0.0508)) + (pad 24 smd rect (at -7.27 11.81 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 196 /S17_P3_TRX_0_P) (solder_mask_margin 0.0508)) + (pad 23 smd rect (at -7.27 10.79 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 197 /S17_P3_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 22 smd rect (at -7.27 9.77 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 99 "Net-(C137-Pad1)") (solder_mask_margin 0.0508)) + (pad 21 smd rect (at -7.27 8.75 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 198 /S17_P3_TRX_1_P) (solder_mask_margin 0.0508)) + (pad 20 smd rect (at -7.27 7.73 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 199 /S17_P3_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 19 smd rect (at -7.27 6.71 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 85 "Net-(C37-Pad1)") (solder_mask_margin 0.0508)) + (pad 18 smd rect (at -7.27 5.69 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 200 /S17_P3_TRX_2_P) (solder_mask_margin 0.0508)) + (pad 17 smd rect (at -7.27 4.67 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 201 /S17_P3_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 16 smd rect (at -7.27 3.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 84 "Net-(C35-Pad1)") (solder_mask_margin 0.0508)) + (pad 15 smd rect (at -7.27 2.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 202 /S17_P3_TRX_3_P) (solder_mask_margin 0.0508)) + (pad 14 smd rect (at -7.27 1.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 203 /S17_P3_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 13 smd rect (at -7.27 0.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 83 "Net-(C34-Pad1)") (solder_mask_margin 0.0508)) + (pad 12 smd rect (at -7.27 -0.43 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 204 /S17_P4_TRX_0_P) (solder_mask_margin 0.0508)) + (pad 11 smd rect (at -7.27 -1.45 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 205 /S17_P4_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 10 smd rect (at -7.27 -2.47 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 82 "Net-(C33-Pad1)") (solder_mask_margin 0.0508)) + (pad 9 smd rect (at -7.27 -3.49 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 206 /S17_P4_TRX_1_P) (solder_mask_margin 0.0508)) + (pad 8 smd rect (at -7.27 -4.51 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 207 /S17_P4_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 7 smd rect (at -7.27 -5.53 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 78 "Net-(C11-Pad1)") (solder_mask_margin 0.0508)) + (pad 6 smd rect (at -7.27 -6.55 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 208 /S17_P4_TRX_2_P) (solder_mask_margin 0.0508)) + (pad 5 smd rect (at -7.27 -7.57 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 209 /S17_P4_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at -7.27 -8.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 77 "Net-(C10-Pad1)") (solder_mask_margin 0.0508)) + (pad 3 smd rect (at -7.27 -9.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 210 /S17_P4_TRX_3_P) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -7.27 -10.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 211 /S17_P4_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -7.27 -11.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) + (net 75 "Net-(C5-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669959) - (at 216.2547 207.4558 270) - (path /5D032DC8/5D47CF84) - (fp_text reference P2 (at -5 -3 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E15EAA8) + (at 96.47936 172.88256) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D44A619) + (fp_text reference R26 (at -1.17094 0.64262) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value 3R420L (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text value 330 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 122 /ethernet_frontend/AM_TRX2_P) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0 0 270) (size 2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 123 /ethernet_frontend/AM_TRX2_N) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 102 /GPIO20) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 167 "Net-(R26-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669963) - (at 208.2547 207.4558 270) - (path /5D032DC8/5D47E762) - (fp_text reference P3 (at -5 -3 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5E15CFFE) + (at 92.1297 174.1564 90) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D44A620) + (fp_text reference USB_LED1 (at 3.60048 5.42408) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value 3R420L (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text value 3mm/BLUE (at 1.905 1.651 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) ) - (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 124 /ethernet_frontend/AM_TRX1_P) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0 0 270) (size 2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 121 /ethernet_frontend/AM_TRX1_N) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 167 "Net-(R26-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D66996D) - (at 200.2547 207.4558 270) - (path /5D032DC8/5D47E7A5) - (fp_text reference P4 (at -5 -3 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (module LibreRouter_MegaBoard:DRAGINO_CORE9558 (layer Top) (tedit 0) (tstamp 5E151241) + (at 157.3315 133.8466 270) + (path /5D032850/5D47B6E1) + (fp_text reference U1 (at -35.648 36.584 270) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) ) - (fp_text value 3R420L (at 0 0 270) (layer F.SilkS) hide + (fp_text value CORE9558_V2 (at 0 0 270) (layer F.SilkS) hide (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line 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F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text user 1 (at -36.9964 36.1481) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.09)) (justify left bottom)) ) - (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 133 /ethernet_frontend/BM_TRX0_P) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0 0 270) (size 2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 134 /ethernet_frontend/BM_TRX0_N) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669981) - (at 192.2547 207.4558 270) - (path /5D032DC8/5D481FAA) - (fp_text reference P6 (at -5 -3 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (fp_text user 105 (at -42.5209 -34.7179) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) ) - (fp_text value 3R420L (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text user 104 (at -37.86 -40.9155) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) ) - (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 128 /ethernet_frontend/BM_TRX3_P) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0 0 270) (size 2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 127 /ethernet_frontend/BM_TRX3_N) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D66998B) - (at 184.2547 207.4558 270) - (path /5D032DC8/5D481FED) - (fp_text reference P7 (at -5 -3 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text user 67 (at 51.6623 -42.122 270) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) ) - (fp_text value 3R420L (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text user 66 (at 56.5645 -35.0481) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) ) - (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) - (pad 2 smd rect (at 3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 130 /ethernet_frontend/BM_TRX2_P) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0 0 270) (size 2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 131 /ethernet_frontend/BM_TRX2_N) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669995) - (at 176.2547 207.4304 270) - (path /5D032DC8/5D482030) - (fp_text reference P8 (at -5 -3 90) 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2 5.5) (layers Top F.Paste F.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -3.48 0 270) (size 1 5.5) (layers Top F.Paste F.Mask) - (net 129 /ethernet_frontend/BM_TRX1_N) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:MINI-PCI-E-FULL (layer Bottom) (tedit 5D71604F) (tstamp 5DE3DABE) - (at 221.89316 87.11574) - (path /5D1650F5/5D19C7E9) - (fp_text reference PCIE1 (at -2.87912 6.98618) (layer B.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top mirror)) - ) - (fp_text value f5521gw (at -2.8334 8.79466) (layer B.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top mirror)) - ) - (fp_line (start -2.439 -4.9051) (end -2.439 5.0677) (layer B.Fab) (width 0.1016)) - (fp_line (start -2.439 5.0677) (end -0.542 5.0677) (layer B.SilkS) (width 0.1016)) - (fp_line (start -0.542 5.0677) (end -0.542 4.0108) (layer B.SilkS) (width 0.1016)) - (fp_line (start -2.3848 3.9295) (end 27.371 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"Net-(U1-Pad101)") (solder_mask_margin 0.0508)) + (pad 100 smd rect (at -26.7965 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 218 "Net-(U1-Pad100)") (solder_mask_margin 0.0508)) + (pad 99 smd rect (at -24.5105 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 219 "Net-(U1-Pad99)") (solder_mask_margin 0.0508)) + (pad 98 smd rect (at -22.2245 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 97 smd rect (at -19.9385 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 96 smd rect (at -17.6525 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 95 smd rect (at -15.365 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 28 smd rect (at 14.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 161 "Net-(PCIE1-Pad28)") (solder_mask_margin 0.0508)) - (pad 29 smd rect (at 15.1 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (pad 94 smd rect (at -13.0805 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 30 smd rect (at 15.5 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 62 "Net-(PCIE1-Pad30)") (solder_mask_margin 0.0508)) - (pad 31 smd rect (at 15.9 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 275 /sheet5D1650DF/PCIe_TX_bis_N) (solder_mask_margin 0.0508)) - (pad 32 smd rect (at 16.3 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 61 "Net-(PCIE1-Pad32)") (solder_mask_margin 0.0508)) - (pad 33 smd rect (at 16.7 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 276 /sheet5D1650DF/PCIe_TX_bis_P) (solder_mask_margin 0.0508)) - (pad 34 smd rect (at 17.1 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (pad 93 smd rect (at -10.7945 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 35 smd rect (at 17.5 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (pad 92 smd rect (at -8.5085 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 211 /S17_P4_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 91 smd rect (at -6.2225 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 210 /S17_P4_TRX_3_P) (solder_mask_margin 0.0508)) + (pad 90 smd rect (at -3.9365 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 209 /S17_P4_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 89 smd rect (at -1.6505 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 208 /S17_P4_TRX_2_P) (solder_mask_margin 0.0508)) + (pad 88 smd rect (at 0.6355 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 207 /S17_P4_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 87 smd rect (at 2.9215 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 206 /S17_P4_TRX_1_P) (solder_mask_margin 0.0508)) + (pad 86 smd rect (at 5.2075 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 205 /S17_P4_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 85 smd rect (at 7.4935 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 204 /S17_P4_TRX_0_P) (solder_mask_margin 0.0508)) + (pad 84 smd rect (at 9.7795 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 36 smd rect (at 17.9 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 162 /sheet5D1650DF/USB_N) (solder_mask_margin 0.0508)) - (pad 37 smd rect (at 18.3 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 163 "Net-(PCIE1-Pad37)") (solder_mask_margin 0.0508)) - (pad 38 smd rect (at 18.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 164 /sheet5D1650DF/USB_P) (solder_mask_margin 0.0508)) - (pad 39 smd rect (at 19.1 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 40 smd rect (at 19.5 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (pad 83 smd rect (at 12.0655 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 203 /S17_P3_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 82 smd rect (at 14.3515 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 202 /S17_P3_TRX_3_P) (solder_mask_margin 0.0508)) + (pad 81 smd rect (at 16.6375 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 201 /S17_P3_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 80 smd rect (at 18.9235 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 200 /S17_P3_TRX_2_P) (solder_mask_margin 0.0508)) + (pad 79 smd rect (at 21.2095 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 199 /S17_P3_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 78 smd rect (at 23.4955 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 198 /S17_P3_TRX_1_P) (solder_mask_margin 0.0508)) + (pad 77 smd rect (at 25.7815 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 197 /S17_P3_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 76 smd rect (at 28.0675 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 196 /S17_P3_TRX_0_P) (solder_mask_margin 0.0508)) + (pad 75 smd rect (at 30.3535 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 41 smd rect (at 19.9 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 42 smd rect (at 20.3 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 60 "Net-(PCIE1-Pad42)") (solder_mask_margin 0.0508)) - (pad 43 smd rect (at 20.7 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (pad 74 smd rect (at 32.6395 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 220 "Net-(U1-Pad74)") (solder_mask_margin 0.0508)) + (pad 73 smd rect (at 34.9255 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 221 "Net-(U1-Pad73)") (solder_mask_margin 0.0508)) + (pad 72 smd rect (at 37.2115 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 222 "Net-(U1-Pad72)") (solder_mask_margin 0.0508)) + (pad 71 smd rect (at 39.4975 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 223 "Net-(U1-Pad71)") (solder_mask_margin 0.0508)) + (pad 70 smd rect (at 41.7835 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 224 "Net-(U1-Pad70)") (solder_mask_margin 0.0508)) + (pad 69 smd rect (at 44.0695 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 225 "Net-(U1-Pad69)") (solder_mask_margin 0.0508)) + (pad 68 smd rect (at 46.3555 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 226 "Net-(U1-Pad68)") (solder_mask_margin 0.0508)) + (pad 67 smd rect (at 48.6415 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 227 "Net-(U1-Pad67)") (solder_mask_margin 0.0508)) + (pad 66 smd rect (at 54.61 -33.4354 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 228 "Net-(U1-Pad66)") (solder_mask_margin 0.0508)) + (pad 65 smd rect (at 54.61 -31.1494 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 229 "Net-(U1-Pad65)") (solder_mask_margin 0.0508)) + (pad 64 smd rect (at 54.61 -28.8634 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 230 "Net-(U1-Pad64)") (solder_mask_margin 0.0508)) + (pad 63 smd rect (at 54.61 -26.5774 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 231 "Net-(U1-Pad63)") (solder_mask_margin 0.0508)) + (pad 62 smd rect (at 54.61 -24.2914 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 232 "Net-(U1-Pad62)") (solder_mask_margin 0.0508)) + (pad 61 smd rect (at 54.61 -22.006 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 233 "Net-(U1-Pad61)") (solder_mask_margin 0.0508)) + (pad 60 smd rect (at 54.61 -19.72 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 234 "Net-(U1-Pad60)") (solder_mask_margin 0.0508)) + (pad 59 smd rect (at 54.61 -17.434 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 235 "Net-(U1-Pad59)") (solder_mask_margin 0.0508)) + (pad 58 smd rect (at 54.61 -15.148 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 44 smd rect (at 21.1 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 165 /5G_WLAN_LED_1) (solder_mask_margin 0.0508)) - (pad 45 smd rect (at 21.5 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 59 "Net-(PCIE1-Pad45)") (solder_mask_margin 0.0508)) - (pad 46 smd rect (at 21.9 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 58 "Net-(PCIE1-Pad46)") (solder_mask_margin 0.0508)) - (pad 47 smd rect (at 22.3 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 57 "Net-(PCIE1-Pad47)") (solder_mask_margin 0.0508)) - (pad 48 smd rect (at 22.7 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 56 "Net-(PCIE1-Pad48)") (solder_mask_margin 0.0508)) - (pad 49 smd rect (at 23.1 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) - (pad 50 smd rect (at 23.5 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) + (pad 57 smd rect (at 54.61 -12.862 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 278 /S17_P0_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 56 smd rect (at 54.61 -10.576 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 276 /S17_P0_TRX_3_P) (solder_mask_margin 0.0508)) + (pad 55 smd rect (at 54.61 -8.29 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 274 /S17_P0_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 54 smd rect (at 54.61 -6.004 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 272 /S17_P0_TRX_2_P) (solder_mask_margin 0.0508)) + (pad 53 smd rect (at 54.61 -3.718 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 264 /S17_P0_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 52 smd rect (at 54.61 -1.432 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 266 /S17_P0_TRX_1_P) (solder_mask_margin 0.0508)) + (pad 51 smd rect (at 54.61 0.854 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 268 /S17_P0_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 50 smd rect (at 54.61 3.14 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 270 /S17_P0_TRX_0_P) (solder_mask_margin 0.0508)) + (pad 49 smd rect (at 54.61 5.426 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 48 smd rect (at 54.61 7.712 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 47 smd rect (at 54.61 9.998 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 46 smd rect (at 54.61 12.284 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 45 smd rect (at 54.61 14.57 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 44 smd rect (at 54.61 16.856 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 43 smd rect (at 54.61 19.142 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 42 smd rect (at 54.61 21.428 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 41 smd rect (at 54.61 23.714 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 40 smd rect (at 54.61 26 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 39 smd rect (at 54.61 28.286 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 38 smd rect (at 48.6415 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 37 smd rect (at 46.3555 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 236 /Core9558/USB1_DM) (solder_mask_margin 0.0508)) + (pad 36 smd rect (at 44.0695 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 237 /Core9558/USB1_DP) (solder_mask_margin 0.0508)) + (pad 35 smd rect (at 41.7835 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 34 smd rect (at 39.4975 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 131 /USB2_N) (solder_mask_margin 0.0508)) + (pad 33 smd rect (at 37.2115 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 130 /USB2_P) (solder_mask_margin 0.0508)) + (pad 32 smd rect (at 34.9255 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 31 smd rect (at 32.6395 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 238 /GPIO23) (solder_mask_margin 0.0508)) + (pad 30 smd rect (at 30.3535 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 159 /GPIO22) (solder_mask_margin 0.0508)) + (pad 29 smd rect (at 28.0675 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 103 /GPIO21) (solder_mask_margin 0.0508)) + (pad 28 smd rect (at 25.7815 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 102 /GPIO20) (solder_mask_margin 0.0508)) + (pad 27 smd rect (at 23.4955 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 101 /GPIO19) (solder_mask_margin 0.0508)) + (pad 26 smd rect (at 21.2095 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 105 /GPIO18) (solder_mask_margin 0.0508)) + (pad 25 smd rect (at 18.9235 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 96 /GPIO17) (solder_mask_margin 0.0508)) + (pad 24 smd rect (at 16.6375 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 288 /GPIO16-GPS_UART_TX) (solder_mask_margin 0.0508)) + (pad 23 smd rect (at 14.3515 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 289 /GPIO15-GPS_UART_RX) (solder_mask_margin 0.0508)) + (pad 22 smd rect (at 12.0655 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 290 /GPIO14-PCIe1_nDISABLE) (solder_mask_margin 0.0508)) + (pad 21 smd rect (at 9.7795 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 291 /GPIO13-GPS_PPS) (solder_mask_margin 0.0508)) + (pad 20 smd rect (at 7.4935 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 292 /GPIO12-PCIe0_nDISABLE) (solder_mask_margin 0.0508)) + (pad 19 smd rect (at 5.2075 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 104 /UART_SOUT) (solder_mask_margin 0.0508)) + (pad 18 smd rect (at 2.9215 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 106 /UART_SIN) (solder_mask_margin 0.0508)) + (pad 17 smd rect (at 0.6355 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 107 /GPIO4) (solder_mask_margin 0.0508)) + (pad 16 smd rect (at -1.6505 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 15 smd rect (at -3.9365 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 14 smd rect (at -6.2225 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 13 smd rect (at -8.5085 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 12 smd rect (at -10.7945 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 11 smd rect (at -13.0805 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 10 smd rect (at -15.365 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 294 /GPIO3-EJTAG_TMS) (solder_mask_margin 0.0508)) + (pad 9 smd rect (at -17.6525 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 295 /GPIO2-EJTAG_TDO) (solder_mask_margin 0.0508)) + (pad 8 smd rect (at -19.9385 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 296 /GPIO1-EJTAG_TDI) (solder_mask_margin 0.0508)) + (pad 7 smd rect (at -22.2245 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 293 /GPIO0-EJTAG_TCK) (solder_mask_margin 0.0508)) + (pad 6 smd rect (at -24.5105 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 97 /RST_B) (solder_mask_margin 0.0508)) + (pad 5 smd rect (at -26.7965 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at -29.0825 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at -31.3685 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 194 /COM_B_2G) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -33.6545 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (net 195 /COM_A_2G) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -35.9405 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 51 smd rect (at 23.9 -4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) - (pad 52 smd rect (at 24.3 4.1) (size 0.6 2) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad M2 smd rect (at -2.2 -3.5) (size 2.3 3.2) (layers Bottom B.Paste B.Mask) - (solder_mask_margin 0.0508)) - (pad "" np_thru_hole circle (at 0 0) (size 1.55 1.55) (drill 1.55) (layers *.Cu *.Mask)) - (pad "" np_thru_hole circle (at 25 0) (size 1.1 1.1) (drill 1.1) (layers *.Cu *.Mask)) - (pad 53 thru_hole circle (at 0.2 47.7) (size 6.2 6.2) (drill 4.09) (layers *.Cu *.Mask) - (solder_mask_margin 0.0508)) - (pad 54 thru_hole circle (at 24.5 47.7) (size 6.2 6.2) (drill 4.09) (layers *.Cu *.Mask) - (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE54003) - (at 177.34788 53.95468 270) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D44B71E) - (fp_text reference R28 (at -1.40716 -1.40716 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module MountingHole:MountingHole_3mm (layer Top) (tedit 56D1B4CB) (tstamp 5E14F5EE) + (at 104.3813 107.27182) + (descr "Mounting Hole 3mm, no annular") + (tags "mounting hole 3mm no annular") + (path /5E1D080E) + (attr virtual) + (fp_text reference H4 (at 0 -4) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value 330 (at -3.46964 -0.24384 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 183 /5G_WLAN_LED_0) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 184 "Net-(5G_WLAN0-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF7C046) - (at 207.89138 53.95468 270) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D4487F6) - (fp_text reference R24 (at -1.23444 -0.69088 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value MountingHole (at 0 4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value 330 (at -3.44932 0.39624 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_circle (center 0 0) (end 3.25 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.0508 -3.98272) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 179 "Net-(PWR1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 np_thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF1920D) - (at 226.22764 62.61608) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D44A608) - (fp_text reference R7 (at 1.2319 0.40894) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module MountingHole:MountingHole_3mm (layer Top) (tedit 56D1B4CB) (tstamp 5E14F5E6) + (at 244.63502 152.47366) + (descr "Mounting Hole 3mm, no annular") + (tags "mounting hole 3mm no annular") + (path /5E179365) + (attr virtual) + (fp_text reference H3 (at 0 -4) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value 330 (at -3.41884 0.508) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) - ) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 171 "Net-(2G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 172 /GPIO22) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DEFE4E0) - (at 234.53728 95.2031 180) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1A0459) - (fp_text reference R118 (at -4.09324 0.39742) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value MountingHole (at 0 4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value 0 (at 1.15948 0.39742) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_circle (center 0 0) (end 3.25 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at -0.02652 -3.9624) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 203 /PCIe_1_RST) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 160 "Net-(PCIE1-Pad22)") (solder_mask_margin 0.0508)) + (pad 1 np_thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE3D9D3) - (at 222.49892 79.71028 90) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1A5891) - (fp_text reference R20 (at -1.0961 0.70996 270) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) - ) - (fp_text value TBD (at -1.905 -1.397 270) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module MountingHole:MountingHole_3mm (layer Top) (tedit 56D1B4CB) (tstamp 5E69C677) + (at 235.95584 207.59674) + (descr "Mounting Hole 3mm, no annular") + (tags "mounting hole 3mm no annular") + (path /5E1A5736) + (attr virtual) + (fp_text reference H2 (at 0 -4) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 150 "Net-(PCIE1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 115 /GPIO3) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE49E9A) - (at 226.88296 80.05064) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1AF5AD) - (fp_text reference R49 (at 1.20396 0.36068) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text value MountingHole (at 0 4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value TBD (at -1.905 -1.397) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_circle (center 0 0) (end 3.25 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.01016 -3.98384) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 154 /PCIe_1_CLK_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 156 /PCIe_1_CLK_P) (solder_mask_margin 0.0508)) + (pad 1 np_thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE3D973) - (at 234.51696 79.4551 90) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1F3D95) - (fp_text reference R80 (at -4.8553 -0.2146 270) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module MountingHole:MountingHole_3mm (layer Top) (tedit 56D1B4CB) (tstamp 5E690617) + (at 101.55682 204.50556) + (descr "Mounting Hole 3mm, no annular") + (tags "mounting hole 3mm no annular") + (path /5E1FBC61) + (attr virtual) + (fp_text reference H1 (at 0 -4) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text value MountingHole (at 0 4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 273 /sheet5D1650DF/PCIe_RX_bis_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 194 /PCIe_1_RX_N) (solder_mask_margin 0.0508)) + (fp_circle (center 0 0) (end 3.25 0) (layer F.CrtYd) (width 0.05)) + (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.15)) + (fp_text user %R (at 0.0508 -4.28752) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 np_thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)) ) - (module LibreRouter_MegaBoard:C1206 (layer Top) (tedit 0) (tstamp 5DEFD0D3) - (at 124.27204 55.16626 270) - (descr "CAPACITOR

\nchip") - (path /5D46D273) - (fp_text reference C20 (at 3.1203 -0.40008 270) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON (layer Top) (tedit 5DF0F220) (tstamp 5D66DB48) + (at 101.6127 78.9813) + (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 7.7 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") + (path /5D032C97/5D1D8CB3) + (fp_text reference C27 (at 0.2413 -3.6068) (layer F.SilkS) + (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left bottom)) ) - (fp_text value "47uF, 6.3V" (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) + (fp_text value 470uF (at -3.175 4.445) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left bottom)) ) - (fp_line (start 1.651 1.143) (end 2.794 1.143) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.651 -1.143) (end 2.794 -1.143) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.794 1.143) (end -1.778 1.143) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.794 -1.143) (end -1.651 -1.143) (layer F.SilkS) (width 0.127)) - (fp_line (start -2.794 1.143) (end -2.794 -1.143) (layer F.SilkS) (width 0.127)) - (fp_line (start 2.794 -1.143) (end 2.794 1.143) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) - (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer F.Fab) (width 0.1016)) - (pad 2 smd rect (at 1.71 0 270) (size 1.52 1.8) (layers Top F.Paste F.Mask) + (fp_poly (pts (xy -2.2 -2.15) (xy -2.200001 -2.149999) (xy -2.439523 -1.873329) (xy -2.644527 -1.570195) + (xy -2.812117 -1.24488) (xy -2.939926 -0.901978) (xy -3.026149 -0.546334) (xy -3.069567 -0.182973) + (xy -3.069567 0.182974) (xy -3.026149 0.546336) (xy -2.939926 0.901979) (xy -2.812116 1.244881) + (xy -2.644526 1.570196) (xy -2.439522 1.87333) (xy -2.2 2.15)) (layer F.Fab) (width 0)) + (fp_circle (center 0 0) (end 3.1001 0) (layer F.Fab) (width 0.1016)) + (fp_arc (start 0.002365 0.0051) (end 3 0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end -3.25 0.7) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 -0.8) (end -3.25 -3.25) (layer F.SilkS) (width 0.1016)) + (fp_arc (start -0.002365 -0.0051) (end -3 -0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end -3.25 -3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 3.25 -2.45) (end 3.25 2.45) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.Fab) (width 0.1016)) + (pad 1 smd rect (at 2.35 0) (size 2.799999 1) (layers Top F.Paste F.Mask) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -2.35 0) (size 2.799999 1) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1.71 0 270) (size 1.52 1.8) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C1206 (layer Bottom) (tedit 0) (tstamp 5DE3D907) - (at 244.48126 96.41208 180) - (descr "CAPACITOR

\nchip") - (path /5D46CAA5) - (fp_text reference C39 (at 3.26254 0.38484) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module LibreRouter_MegaBoard:MINI-PCI-E-FULL (layer Top) (tedit 5D71604F) (tstamp 5E693750) + (at 115.6755 55.0812 270) + (path /5D032C97/5D19C7E9) + (fp_text reference PCIE0 (at -3.7732 -4.3649 180) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_text value "47uF, 6.3V" (at 0 0 180) (layer B.SilkS) hide - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom mirror)) + (fp_text value f5521gw (at 10.16 -6.35 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer B.Fab) (width 0.1016)) - (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer B.Fab) (width 0.1016)) - (fp_poly (pts (xy -1.7018 -0.8509) (xy -0.9517 -0.8509) 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B.Paste B.Mask) + (fp_line (start -2.54 -50.8) (end -2.54 -45.72) (layer F.SilkS) (width 0.127)) + (fp_line (start 27.3 -50.8) (end 27.3 -45.72) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.54 -50.8) (end 27.3 -50.8) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy 24.14 -3.9295) (xy 24.4652 -3.9295) (xy 24.4652 -4.7695) (xy 24.14 -4.7695)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 23.34 -3.9295) (xy 23.6652 -3.9295) (xy 23.6652 -4.7695) (xy 23.34 -4.7695)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 22.54 -3.9295) (xy 22.8652 -3.9295) (xy 22.8652 -4.7695) (xy 22.54 -4.7695)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 21.74 -3.9295) (xy 22.0652 -3.9295) (xy 22.0652 -4.7695) (xy 21.74 -4.7695)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 20.94 -3.9295) (xy 21.2652 -3.9295) (xy 21.2652 -4.7695) (xy 20.94 -4.7695)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 20.14 -3.9295) (xy 20.4652 -3.9295) (xy 20.4652 -4.7695) (xy 20.14 -4.7695)) (layer F.Fab) (width 0)) + (fp_poly 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(net 135 /PCIe_0_CLK_N) (solder_mask_margin 0.0508)) + (pad 10 smd rect (at 4.3 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 72 /pcie0/SIM_DATA) (solder_mask_margin 0.0508)) + (pad 9 smd rect (at 3.8 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 8 smd rect (at 3.5 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 71 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) + (pad 7 smd rect (at 3 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 136 /CLKREQ_L_0) (solder_mask_margin 0.0508)) + (pad 6 smd rect (at 2.7 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 53 "Net-(PCIE0-Pad6)") (solder_mask_margin 0.0508)) + (pad 5 smd rect (at 2.2 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 54 "Net-(PCIE0-Pad5)") (solder_mask_margin 0.0508)) + (pad 4 smd rect (at 1.9 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 1.4 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 55 "Net-(PCIE0-Pad3)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 1.1 -4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0.6 4.1 270) (size 0.6 2) (layers Top F.Paste F.Mask) + (net 137 "Net-(PCIE0-Pad1)") (solder_mask_margin 0.0508)) + (pad M1 smd rect (at 27.15 3.5 270) (size 2.3 3.2) (layers Top F.Paste F.Mask) + (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5DE3D8D7) - (at 242.24556 79.72434) - (descr "CAPACITOR

\nchip") - (path /5D1650F5/5D1C5785) - (fp_text reference C75 (at 1.04518 0.38472) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696B1) + (at 221.8944 168.12514) + (path /5D032DC8/5D47E794) + (fp_text reference D11 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 205 /S17_P4_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 204 /S17_P4_TRX_0_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE43712) - (at 235.50756 79.4551 90) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1F3F5D) - (fp_text reference R110 (at -5.5665 -0.38732 270) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696A8) + (at 224.95002 168.12514) + (path /5D032DC8/5D47E751) + (fp_text reference D10 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 274 /sheet5D1650DF/PCIe_RX_bis_P) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 200 /PCIe_1_RX_P) (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 207 /S17_P4_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 206 /S17_P4_TRX_1_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE43786) - (at 237.71482 79.46272 90) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1F7584) - (fp_text reference R111 (at -5.58936 -0.23238 270) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D66970F) + (at 231.07396 168.12006) + (path /5D032DC8/5D47A51B) + (fp_text reference D9 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 275 /sheet5D1650DF/PCIe_TX_bis_N) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 201 /PCIe_1_TX_N) (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 211 /S17_P4_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 210 /S17_P4_TRX_3_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE43843) - (at 238.68002 79.46272 90) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1F758C) - (fp_text reference R112 (at -5.63 -0.4559 270) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D669706) + (at 228.01326 168.12006) + (path /5D032DC8/5D47CF73) + (fp_text reference D8 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 276 /sheet5D1650DF/PCIe_TX_bis_P) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 202 /PCIe_1_TX_P) (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 209 /S17_P4_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 208 /S17_P4_TRX_2_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DEFE510) - (at 234.53728 94.0601 180) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1A051B) - (fp_text reference R116 (at 4.03736 -0.26534) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5E15E995) + (at 209.64398 168.1226) + (path /5D032DC8/5D482062) + (fp_text reference D7 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 1.5k (at -3.81124 0.37982) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 160 "Net-(PCIE1-Pad22)") (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 197 /S17_P3_TRX_0_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 196 /S17_P3_TRX_0_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DF00846) - (at 232.03916 95.82404 90) - (descr "RESISTOR

\nchip") - (path /5D1650F5/5D1A04F3) - (fp_text reference R117 (at 1.34874 0.65042) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696F4) + (at 212.70722 168.1226) + (path /5D032DC8/5D48201F) + (fp_text reference D6 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 0 (at 0.08636 -0.53068) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 107 /GPIO14) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 159 "Net-(PCIE1-Pad20)") (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 199 /S17_P3_TRX_1_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 198 /S17_P3_TRX_1_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5DE438CA) - (at 242.24556 80.79114) - (descr "CAPACITOR

\nchip") - (path /5D1650F5/5D1C583F) - (fp_text reference C116 (at 1.04264 0.34662) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696EB) + (at 218.8337 168.12514) + (path /5D032DC8/5D481F99) + (fp_text reference D4 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397) (layer B.Fab) hide - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 203 /S17_P3_TRX_3_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 202 /S17_P3_TRX_3_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5340A) - (at 226.22764 56.41848) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D449F02) - (fp_text reference R123 (at 1.3208 0.35814) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:SOD-323 (layer Top) (tedit 5DF0F8C3) (tstamp 5D6696E2) + (at 215.76792 168.1226) + (path /5D032DC8/5D481FDC) + (fp_text reference D3 (at -1.27 -1.27) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 330 (at -3.5052 0.44704) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value BS05C (at -0.0254 1.68656) (layer F.SilkS) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889))) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 204 /LEDN1000_3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 205 "Net-(P3_1000-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start -0.9 0.675) (end -0.9 -0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 0.675) (end -0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.9 -0.675) (end 0.9 0.675) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.9 -0.675) (end 0.9 -0.675) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at 1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 201 /S17_P3_TRX_2_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -1.05 0) (size 0.6 0.7) (layers Top F.Paste F.Mask) + (net 200 /S17_P3_TRX_2_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5C339) - (at 223.85528 54.86908) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D449CFE) - (fp_text reference R17 (at 1.20904 0.40132) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:SIM-MICRO-PUSH (layer Bottom) (tedit 5DF0FEB4) (tstamp 5E69457D) + (at 131.62744 49.67008) + (path /5D0C3185) + (fp_text reference SIM_CARD_CON_6MICRO0 (at -1.16 6.34) (layer B.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left top mirror)) ) - (fp_text value 330 (at -3.35788 0.57912) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value SIM_Card (at 20.07406 2.20942) (layer B.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 176 /LEDN_3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 177 "Net-(P3_100-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 0.25 -4.5) (end 0.25 -2.1) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.75 -5.1) (end 0.25 -4.5) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.25 -2) (end 0.25 -1.6) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.75 -2.62) (end 0.25 -2) (layer B.SilkS) (width 0.127)) + (fp_line (start 15.3 -2.8) (end 15.3 -0.4) (layer B.SilkS) (width 0.127)) + (fp_line (start 13.1 -5) (end 15.3 -2.8) (layer B.SilkS) (width 0.127)) + (fp_line (start 15.3 -0.3) (end 15.3 0.3) (layer B.SilkS) (width 0.127)) + (fp_line (start 13 -2.6) (end 15.3 -0.3) (layer B.SilkS) (width 0.127)) + (fp_line (start 15.3 0.3) (end 15.3 2.1) (layer B.SilkS) (width 0.127)) + (fp_line (start 13.1 -1.9) (end 15.3 0.3) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.5 -1.92) (end 0.25 -1.62) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.7 -1.92) (end 0.5 -1.92) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.75 -5.12) (end 13.01 -5.12) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.75 -2.62) (end 13.01 -2.62) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.75 -1.92) (end 13.01 -1.92) (layer B.SilkS) (width 0.127)) + (fp_line (start 15.55 15.78) (end 15.55 -1.62) (layer B.SilkS) (width 0.127)) + (fp_line (start 11.43 15.78) (end 15.55 15.78) (layer B.SilkS) (width 0.127)) + (fp_line (start 11.43 13.98) (end 11.43 15.78) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.25 13.98) (end 11.43 13.98) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.25 -1.6) (end 0.25 -1.62) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.25 13.98) (end 0.25 -1.6) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.25 -1.62) (end 15.55 -1.62) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy 2.1 8.62) (xy 3.8 8.62) (xy 3.8 11.62) (xy 2.1 11.62)) (layer Dwgs.User) (width 0)) + (fp_poly (pts (xy 4.64 8.62) (xy 6.34 8.62) (xy 6.34 11.62) (xy 4.64 11.62)) (layer Dwgs.User) (width 0)) + (fp_poly (pts (xy 7.18 8.62) (xy 8.88 8.62) (xy 8.88 11.62) (xy 7.18 11.62)) (layer Dwgs.User) (width 0)) + (fp_poly (pts (xy 7.18 0.7) (xy 8.88 0.7) (xy 8.88 3.7) (xy 7.18 3.7)) (layer Dwgs.User) (width 0)) + (fp_poly (pts (xy 4.64 0.7) (xy 6.34 0.7) (xy 6.34 3.7) (xy 4.64 3.7)) (layer Dwgs.User) (width 0)) + (fp_poly (pts (xy 2.1 0.7) (xy 3.8 0.7) (xy 3.8 3.7) (xy 2.1 3.7)) (layer Dwgs.User) (width 0)) + (pad 4 smd rect (at 0.25 12.58) (size 1.2 2.999999) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at 15.55 12.58) (size 1.2 2.999999) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at 15.8 0) (size 1.55 2.6) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at 0 0) (size 1.55 2.6) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 7.91 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (net 73 /pcie0/SIM_CLK) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 5.37 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (net 74 /pcie0/SIM_RST) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 2.83 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (net 71 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) + (pad 5 smd rect (at 1.56 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 6 smd rect (at 4.1 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (net 244 "Net-(SIM_CARD_CON_6MICRO0-Pad6)") (solder_mask_margin 0.0508)) + (pad 7 smd rect (at 6.64 15.105 270) (size 1.35 0.65) (layers Bottom B.Paste B.Mask) + (net 72 /pcie0/SIM_DATA) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5C309) - (at 223.8502 61.0743) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D44A62A) - (fp_text reference R27 (at -1.1684 -1.41732) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:TEST_POINT_0.8MM (layer Bottom) (tedit 5DF0F968) (tstamp 5DE3D95B) + (at 224.29724 80.264 180) + (path /5D158FCC) + (fp_text reference TP2 (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror)) ) - (fp_text value 330 (at -3.38836 -0.25908) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value TEST-POINT0.8MM (at 0 0) (layer B.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify mirror)) ) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 182 "Net-(5G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 165 /5G_WLAN_LED_1) (solder_mask_margin 0.0508)) + (pad 1 smd roundrect (at 0 0 180) (size 0.8 0.8) (layers Bottom B.Mask) (roundrect_rratio 0.5) + (net 139 /CLKREQ_L_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669328) - (at 229.5437 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D47CF61) - (fp_text reference C10 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) - ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (module LibreRouter_MegaBoard:TEST_POINT_0.8MM (layer Top) (tedit 5DF0F968) (tstamp 5D66A025) + (at 108.5127 58.0784 90) + (path /5D13FB87) + (fp_text reference TP1 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 78 "Net-(C10-Pad1)") (solder_mask_margin 0.0508)) + (fp_text value TEST-POINT0.8MM (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (pad 1 smd roundrect (at 0 0 90) (size 0.8 0.8) (layers Top F.Mask) (roundrect_rratio 0.5) + (net 136 /CLKREQ_L_0) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669338) - (at 90.1993 182.894 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE35A) - (fp_text reference C100 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:TEST_POINT_0.8MM (layer Top) (tedit 5DF0F968) (tstamp 5D66A19E) + (at 118.7743 116.19484) + (path /5D801B21) + (fp_text reference TP3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_text value "0.1uF, 50V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value JTAG_TDO (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 97 /POWER_EN_5V) (solder_mask_margin 0.0508)) + (pad 1 smd roundrect (at 0 0) (size 0.8 0.8) (layers Top F.Mask) (roundrect_rratio 0.5) + (net 295 /GPIO2-EJTAG_TDO) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669348) - (at 102.2897 186.4754 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42DC2B) - (fp_text reference C102 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5348A) + (at 192.498162 53.49624 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D44A5FE) + (fp_text reference P4_1000 (at -3.22698 3.53444) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 3mm/GREEN (at -6.4223 3.316) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 193 "Net-(P4_1000-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669358) - (at 96.2699 139.1552 180) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42DC2B) - (fp_text reference C103 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE536B7) + (at 182.69086 53.49624 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D44B725) + (fp_text reference 5G_WLAN0 (at -3.87214 3.53444) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 3mm/BLUE (at -5.2793 3.316) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 170 "Net-(5G_WLAN0-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669368) - (at 226.4885 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D47E73F) - (fp_text reference C11 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE534D2) + (at 212.112766 53.49624 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D4489EC) + (fp_text reference PWR1 (at -2.31766 3.53444) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value 3mm/RED (at -4.3903 3.57) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 79 "Net-(C11-Pad1)") (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 166 "Net-(PWR1-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669378) - (at 107.62872 75.43156 270) - (descr "CAPACITOR

\nchip") - (path /5D032C97/5D1C5785) - (fp_text reference C110 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C461) + (at 207.209115 61.17212 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D44A60F) + (fp_text reference 2G_WLAN1 (at -5.286074 3.44808) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 3mm/GREEN (at 1.905 1.651) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 158 "Net-(2G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669388) - (at 108.64472 75.43156 270) - (descr "CAPACITOR

\nchip") - (path /5D032C97/5D1C583F) - (fp_text reference C111 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C2C9) + (at 197.401813 61.10608 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D449D05) + (fp_text reference P3_100 (at -2.285487 3.38204) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 3mm/RED (at -4.6443 3.57) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 164 "Net-(P3_100-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693A8) - (at 86.5417 102.122 270) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42D488) - (fp_text reference C12 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE53442) + (at 202.305464 53.49624 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D449F09) + (fp_text reference P3_1000 (at -3.4505 3.53444) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value 3mm/BLUE (at -5.4063 3.316) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 2 "Net-(C12-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 3 "Net-(C12-Pad1)") (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 191 "Net-(P3_1000-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693B8) - (at 130.3059 220.0796 180) - (descr "CAPACITOR

\nchip") - (path /5E2BEE88) - (fp_text reference C121 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C371) + (at 217.01642 61.17212 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D44A631) + (fp_text reference 5G_WLAN1 (at -5.5333 3.44808) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 3mm/GREEN (at 1.905 1.651) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 98 /GPIO17) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 168 "Net-(5G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693C8) - (at 93.1965 130.2398 180) - (descr "CAPACITOR

\nchip") - (path /5D032C38/5D1B5630) - (fp_text reference C124 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5DE5C3B9) + (at 187.594511 61.10608 180) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D449EF8) + (fp_text reference P4_100 (at -2.34814 3.38204) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value 3mm/RED (at -4.6443 3.316) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 179 "Net-(P4_100-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 180) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693D8) - (at 98.2257 122.696 180) - (descr "CAPACITOR

\nchip") - (path /5D032C38/5D15063F) - (fp_text reference C125 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:LED3MM (layer Top) (tedit 5DF0F943) (tstamp 5E15D046) + (at 84.1287 174.1564 90) + (descr "LED

\n3 mm, round") + (path /5D032C56/5D44BE4E) + (fp_text reference STATUS1 (at 3.60048 3.2727) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_text value 0.01uF (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value 3mm/GREEN (at 1.905 1.651 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_arc (start 0 0.000083) (end -2.032 0) (angle -31.60822) (layer F.Fab) (width 0.254)) + (fp_arc (start 0 0.000002) (end -2.032 0) (angle 28.301701) (layer F.Fab) (width 0.254)) + (fp_arc (start -0.000056 0) (end -1.7643 1.0082) (angle -60.255215) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000037 0) (end 0 2.032) (angle -49.763022) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.00006 0) (end -1.7929 -0.9562) (angle 61.926949) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0.000012 0) (end 0 -2.032) (angle 50.193108) (layer F.SilkS) (width 0.254)) + (fp_arc (start 0 0) (end 0 1.016) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end 0 0.635) (angle -90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -1.016 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0) (end -0.635 0) (angle 90) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0.000008 0) (end -1.203 0.9356) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000008 0) (end 0 1.524) (angle -52.126876) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 0) (end -1.2192 -0.9144) (angle 53.130102) (layer F.SilkS) (width 0.1524)) + (fp_arc (start -0.000034 0) (end 0 -1.524) (angle 54.461337) (layer F.SilkS) (width 0.1524)) + (fp_arc (start 0 -0.000004) (end 1.1708 0.9756) (angle -39.80361) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000014) (end 1.1571 -0.9918) (angle 40.601165) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000063) (end -1.524 0) (angle -41.633208) (layer F.Fab) (width 0.1524)) + (fp_arc (start 0 0.000004) (end -1.524 0) (angle 39.80361) (layer F.Fab) (width 0.1524)) + (fp_line (start 1.5748 1.27) (end 1.5748 -1.27) (layer F.Fab) (width 0.254)) + (pad 1 thru_hole circle (at 1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 165 "Net-(R23-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -1.27 0 90) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask) + (net 238 /GPIO23) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:UD-6,3X5,8_NICHICON (layer Top) (tedit 5DF0F2BC) (tstamp 5D669565) + (at 112.1195 203.3918 90) + (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 5.8 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") + (path /5D032896/5D48969C) + (fp_text reference C55 (at -3.4404 1.1518) (layer F.SilkS) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify right top)) + ) + (fp_text value "100uF, 16V" (at -3.175 4.445 90) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) + ) + (fp_poly (pts (xy -2.2 -2.15) (xy -2.200001 -2.149999) (xy -2.439523 -1.873329) (xy -2.644527 -1.570195) + (xy -2.812117 -1.24488) (xy -2.939926 -0.901978) (xy -3.026149 -0.546334) (xy -3.069567 -0.182973) + (xy -3.069567 0.182974) (xy -3.026149 0.546336) (xy -2.939926 0.901979) (xy -2.812116 1.244881) + (xy -2.644526 1.570196) (xy -2.439522 1.87333) (xy -2.2 2.15)) (layer F.Fab) (width 0)) + (fp_circle (center 0 0) (end 3.1001 0) (layer F.Fab) (width 0.1016)) + (fp_arc (start 0.002365 0.0051) (end 3 0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end -3.25 0.7) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 -0.8) (end -3.25 -3.25) (layer F.SilkS) (width 0.1016)) + (fp_arc (start -0.002365 -0.0051) (end -3 -0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end -3.25 -3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 3.25 -2.45) (end 3.25 2.45) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.Fab) (width 0.1016)) + (pad 1 smd rect (at 2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 99 /RST_B) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693E8) - (at 94.4157 121.6546) - (descr "CAPACITOR

\nchip") - (path /5D032C38/5D1501FA) - (fp_text reference C126 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON (layer Bottom) (tedit 5DF0F220) (tstamp 5DE4A0A2) + (at 245.7958 73.2282 270) + (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 7.7 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") + (path /5D1650F5/5D1D8CB3) + (fp_text reference C43 (at 2.31022 -6.27256) (layer B.SilkS) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left top mirror)) ) - (fp_text value 0.01uF (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value 470uF (at 5.91702 -4.0272 270) (layer B.Fab) hide + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify right top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_poly (pts (xy -2.2 2.15) (xy -2.200001 2.149999) (xy -2.439523 1.873329) (xy -2.644527 1.570195) + (xy -2.812117 1.24488) (xy -2.939926 0.901978) (xy -3.026149 0.546334) (xy -3.069567 0.182973) + (xy -3.069567 -0.182974) (xy -3.026149 -0.546336) (xy -2.939926 -0.901979) (xy -2.812116 -1.244881) + (xy -2.644526 -1.570196) (xy -2.439522 -1.87333) (xy -2.2 -2.15)) (layer B.Fab) (width 0)) + (fp_circle (center 0 0) (end 3.1001 0) (layer B.Fab) (width 0.1016)) + (fp_arc (start 0.002365 -0.0051) (end 3 -0.775) (angle -149.753145) (layer B.SilkS) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end -3.25 -0.7) (layer B.SilkS) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end -3.25 -3.25) (layer B.SilkS) (width 0.1016)) + (fp_line (start 3.25 -2.45) (end 2.45 -3.25) (layer B.SilkS) (width 0.1016)) + (fp_line (start 2.45 3.25) (end 3.25 2.45) (layer B.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end 2.45 3.25) (layer B.SilkS) (width 0.1016)) + (fp_line (start -3.25 0.8) (end -3.25 3.25) (layer B.SilkS) (width 0.1016)) + (fp_arc (start -0.002365 0.0051) (end -3 0.775) (angle -149.753145) (layer B.SilkS) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end -3.25 3.25) (layer B.Fab) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end -3.25 -3.25) (layer B.Fab) (width 0.1016)) + (fp_line (start 3.25 -2.45) (end 2.45 -3.25) (layer B.Fab) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 3.25 -2.45) (layer B.Fab) (width 0.1016)) + (fp_line (start 2.45 3.25) (end 3.25 2.45) (layer B.Fab) (width 0.1016)) + (fp_line (start -3.25 3.25) (end 2.45 3.25) (layer B.Fab) (width 0.1016)) + (pad 1 smd rect (at 2.35 0 270) (size 2.799999 1) (layers Bottom B.Paste B.Mask) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -2.35 0 270) (size 2.799999 1) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 100 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D6693F8) - (at 142.2947 212.104 180) - (descr "CAPACITOR

\nchip") - (path /5D08F1AF) - (fp_text reference C130 (at -0.889 -1.016) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON (layer Top) (tedit 5DF0F220) (tstamp 5DF93AC9) + (at 101.90734 56.75376 90) + (descr "ALUMINUM ELECTROLYTIC CAPACITORS UD Series 6.3 x 7.7 mm

\nSource: http://products.nichicon.co.jp/en/pdf/XJA043/e-ud.pdf") + (path /5D2A0A2B) + (fp_text reference C18 (at -3.50774 -4.43484 270) (layer F.SilkS) + (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left top)) ) - (fp_text value "10uF, 10V" (at -0.889 2.286) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) + (fp_text value 470uF (at -7.9121 -1.98374 270) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left top)) ) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.85 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) + (fp_poly (pts (xy -2.2 -2.15) (xy -2.200001 -2.149999) (xy -2.439523 -1.873329) (xy -2.644527 -1.570195) + (xy -2.812117 -1.24488) (xy -2.939926 -0.901978) (xy -3.026149 -0.546334) (xy -3.069567 -0.182973) + (xy -3.069567 0.182974) (xy -3.026149 0.546336) (xy -2.939926 0.901979) (xy -2.812116 1.244881) + (xy -2.644526 1.570196) (xy -2.439522 1.87333) (xy -2.2 2.15)) (layer F.Fab) (width 0)) + (fp_circle (center 0 0) (end 3.1001 0) (layer F.Fab) (width 0.1016)) + (fp_arc (start 0.002365 0.0051) (end 3 0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end -3.25 0.7) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 -0.8) (end -3.25 -3.25) (layer F.SilkS) (width 0.1016)) + (fp_arc (start -0.002365 -0.0051) (end -3 -0.775) (angle 149.753145) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.25 3.25) (end -3.25 -3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.45 3.25) (end -3.25 3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 3.25 2.45) (end 2.45 3.25) (layer F.Fab) (width 0.1016)) + (fp_line (start 3.25 -2.45) (end 3.25 2.45) (layer F.Fab) (width 0.1016)) + (fp_line (start 2.45 -3.25) (end 3.25 -2.45) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.25 -3.25) (end 2.45 -3.25) (layer F.Fab) (width 0.1016)) + (pad 1 smd rect (at 2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -2.35 0 90) (size 2.799999 1) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.85 0 180) (size 1.3 1.5) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669406) - (at 211.1885 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D482050) - (fp_text reference C137 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:DO214AC (layer Top) (tedit 5DF0F09D) (tstamp 5D6696D8) + (at 82.71764 192.4177 180) + (descr "DO-214AA GULL-WING

\nSource: www.rsonline.de .. SMBJ12/C/15/C/24/C/30/C/5.0/C/7.5/C Voltage Suppressor. Data Sheet") + (path /5D0328DE/5D503196) + (fp_text reference D2 (at -2.43586 1.5748) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0762)) (justify right bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value SS14 (at -1.905 3.81) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (fp_poly (pts (xy -1.37 1.4) (xy -0.36 1.4) (xy -0.36 -1.4) (xy -1.37 -1.4)) (layer F.Fab) (width 0)) + (fp_line (start -2.24 -1.4) (end 2.24 -1.4) (layer F.SilkS) (width 0.1016)) + (fp_line (start -2.24 1.4) (end -2.24 -1.4) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.24 1.4) (end -2.24 1.4) (layer F.SilkS) (width 0.1016)) + (fp_line (start 2.24 -1.4) (end 2.24 1.4) (layer F.SilkS) (width 0.1016)) + (pad 2 smd rect (at 2.13 0) (size 1.45 1.8) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 101 "Net-(C137-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -2.13 0 180) (size 1.45 1.8) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669416) - (at 94.1363 105.9828 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42DBCD) - (fp_text reference C14 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:E3,5-10 (layer Top) (tedit 5DF0F07C) (tstamp 5E69B32A) + (at 83.03514 201.17816 180) + (descr "ELECTROLYTIC CAPACITOR

\ngrid 3.5 mm, diameter 10 mm") + (path /5D0328DE/5D503338) + (fp_text reference C76 (at 3.50774 -4.42214 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + (fp_text value "1000uF, 35V" (at -3.302 3.048) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right top)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (fp_poly (pts (xy 0.254 1.27) (xy 0.762 1.27) (xy 0.762 -1.27) (xy 0.254 -1.27)) (layer F.Fab) (width 0)) + (fp_circle (center 0 0) (end 5.08 0) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 0) (end 1.651 0) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.762 -1.27) (end -0.762 0) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.254 -1.27) (end -0.762 -1.27) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.254 1.27) (end -0.254 -1.27) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.762 1.27) (end -0.254 1.27) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.762 0) (end -0.762 1.27) (layer F.Fab) (width 0.1524)) + (fp_line (start -1.651 0) (end -0.762 0) (layer F.Fab) (width 0.1524)) + (fp_line (start -3.048 -0.762) (end -3.048 -1.524) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.429 -1.143) (end -2.667 -1.143) (layer F.SilkS) (width 0.1524)) + (pad 1 thru_hole circle (at -1.778 0 180) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at 1.778 0 180) (size 1.6002 1.6002) (drill 0.8128) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66942A) - (at 90.8597 109.9452 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42D229) - (fp_text reference C15 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:GR72-135 (layer Top) (tedit 5DF0F038) (tstamp 5D6697ED) + (at 83.6461 219.851 90) + (path /5D0328DE/5D503666) + (fp_text reference L1 (at -6.64 -1.78 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + (fp_text value "4A, GR30-400" (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 4.8 -1.5) (end 4.8 1.4) (layer F.Fab) (width 0.127)) + (fp_line (start -5 -1.5) (end -5 1.4) (layer F.Fab) (width 0.127)) + (fp_line (start -5 -1.5) (end -6.9 -1.5) (layer F.Fab) (width 0.127)) + (fp_line (start 4.8 -1.5) (end -5 -1.5) (layer F.Fab) (width 0.127)) + (fp_line (start 6.9 -1.5) (end 4.8 -1.5) (layer F.Fab) (width 0.127)) + (fp_line (start 6.9 1.5) (end 6.9 -1.5) (layer F.Fab) (width 0.127)) + (fp_line (start -6.9 1.5) (end 6.9 1.5) (layer F.Fab) (width 0.127)) + (fp_line (start -6.9 -1.5) (end -6.9 1.5) (layer F.Fab) (width 0.127)) + (pad 1 thru_hole circle (at 2.5 0 90) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -2.5 0 90) (size 1.508 1.508) (drill 1) (layers *.Cu *.Mask) + (net 243 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66943E) - (at 85.7289 114.06 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42D659) - (fp_text reference C16 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5E172197) + (at 92.20708 208.79308) + (descr DIODE) + (path /5D0328DE/5D502FE5) + (fp_text reference D13 (at -5.47878 1.08712 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value MBRS540T3 (at -3.459 4.629) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 4 "Net-(C16-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 5 "Net-(C16-Pad1)") (solder_mask_margin 0.0508)) + (fp_poly (pts (xy -2.1 3.1) (xy -0.85 3.1) (xy -0.85 -3.1) (xy -2.1 -3.1)) (layer F.SilkS) (width 0)) + (fp_poly (pts (xy 3.5606 1.0922) (xy 4.094 1.0922) (xy 4.094 -1.0922) (xy 3.5606 -1.0922)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.094 1.0922) (xy -3.5606 1.0922) (xy -3.5606 -1.0922) (xy -4.094 -1.0922)) (layer F.Fab) (width 0)) + (fp_line (start 0.543 1) (end 0.543 -1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.83 0) (end 0.543 1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.543 -1) (end -0.83 0) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.5606 3.105) (end 3.5606 -3.105) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.5606 3.105) (end -3.5606 -3.105) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.5606 3.105) (end 3.5606 3.105) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.5606 -3.105) (end 3.5606 -3.105) (layer F.SilkS) (width 0.1016)) + (pad 2 smd rect (at 3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 257 /POE_A) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 243 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66944E) - (at 92.0027 105.9828 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42DAC0) - (fp_text reference C17 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:SMC (layer Top) (tedit 5DF0EFAD) (tstamp 5D6696C9) + (at 92.20708 222.5688) + (descr DIODE) + (path /5D0328DE/5D5033BC) + (fp_text reference D14 (at -5.50418 0.4432 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + (fp_text value MBRS540T3 (at -3.459 4.629) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669462) - (at 92.9679 109.9452 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D43058C) - (fp_text reference C19 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) hide - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) - ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_poly (pts (xy -2.1 3.1) (xy -0.85 3.1) (xy -0.85 -3.1) (xy -2.1 -3.1)) (layer F.SilkS) (width 0)) + (fp_poly (pts (xy 3.5606 1.0922) (xy 4.094 1.0922) (xy 4.094 -1.0922) (xy 3.5606 -1.0922)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.094 1.0922) (xy -3.5606 1.0922) (xy -3.5606 -1.0922) (xy -4.094 -1.0922)) (layer F.Fab) (width 0)) + (fp_line (start 0.543 1) (end 0.543 -1) (layer F.SilkS) (width 0.2032)) + (fp_line (start -0.83 0) (end 0.543 1) (layer F.SilkS) (width 0.2032)) + (fp_line (start 0.543 -1) (end -0.83 0) (layer F.SilkS) (width 0.2032)) + (fp_line (start 3.5606 3.105) (end 3.5606 -3.105) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.5606 3.105) (end -3.5606 -3.105) (layer F.Fab) (width 0.1016)) + (fp_line (start -3.5606 3.105) (end 3.5606 3.105) (layer F.SilkS) (width 0.1016)) + (fp_line (start -3.5606 -3.105) (end 3.5606 -3.105) (layer F.SilkS) (width 0.1016)) + (pad 2 smd rect (at 3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 298 /power_supply/VCC_IN) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.7 0) (size 2.799999 3.8) (layers Top F.Paste F.Mask) + (net 243 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669486) - (at 92.4345 182.894 270) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D488) - (fp_text reference C30 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:DO-214AA (layer Top) (tedit 5DF0EF3B) (tstamp 5D66DB9D) + (at 91.7194 199.81164) + (path /5D0328DE/5D5030DB) + (fp_text reference D25 (at 2.413 -0.54864) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value SMBJ40CA (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 12 "Net-(C30-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 13 "Net-(C30-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start -0.8 -1.2) (end -0.8 1.2) (layer F.SilkS) (width 0.4064)) + (fp_line (start 2.2 -1.4) (end -2.2 -1.4) (layer F.SilkS) (width 0.127)) + (fp_line (start 2.2 1.4) (end 2.2 -1.4) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.2 1.4) (end 2.2 1.4) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.2 -1.4) (end -2.2 1.4) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 2.11 0 90) (size 2.18 1.62) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -2.11 0 90) (size 2.18 1.62) (layers Top F.Paste F.Mask) + (net 243 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669496) - (at 99.6989 185.434 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42DBCD) - (fp_text reference C31 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:BC301N-D (layer Top) (tedit 5DF0EDF6) (tstamp 5D669EB2) + (at 91.87942 203.50988) + (path /5D0328DE/5D504AD9) + (fp_text reference V1 (at 2.48158 -1.49098 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + (fp_text value BC301N-D (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify left top)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (fp_line (start 2.25 -1.6) (end -2.25 -1.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 2.25 1.6) (end 2.25 -1.6) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.25 1.6) (end 2.25 1.6) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.25 -1.6) (end -2.25 1.6) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 2.25 0 90) (size 3.500001 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -2.25 0 90) (size 3.500001 1.4) (layers Top F.Paste F.Mask) + (net 243 "Net-(D13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694AA) - (at 223.4223 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D47E782) - (fp_text reference C33 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A28F) + (at 135.6907 220.486 270) + (path /5D57E8BF) + (fp_text reference D5 (at -0.5728 0.6135 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify right bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value ESD7951ST5G (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 84 "Net-(C33-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) + (net 124 /USB_hub/USB_3_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694BA) - (at 220.3743 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D481F87) - (fp_text reference C34 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A298) + (at 135.6907 218.835 90) + (path /5D57E8C6) + (fp_text reference D17 (at -1.1163 0.9232 270) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value ESD7951ST5G (at 0 0 270) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify left top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 85 "Net-(C34-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) + (net 125 /USB_hub/USB_3_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694CA) - (at 217.3009 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D481FCA) - (fp_text reference C35 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A2A1) + (at 143.74114 209.3976) + (path /5D5E3160) + (fp_text reference D18 (at -3.13436 0.48006) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value ESD7951ST5G (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0.45 0) (size 0.3 0.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 86 "Net-(C35-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.45 0) (size 0.3 0.4) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694DA) - (at 214.2529 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D48200D) - (fp_text reference C37 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A2AA) + (at 135.6907 217.057 270) + (path /5D4BB44C) + (fp_text reference D12 (at -0.9919 1.2104 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value ESD7951ST5G (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 87 "Net-(C37-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.45 0 270) (size 0.3 0.4) (layers Top F.Paste F.Mask) + (net 126 /USB_hub/USB_4_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D6694FA) - (at 95.9397 190.7426 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D43058C) - (fp_text reference C44 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:SOD−923 (layer Top) (tedit 5DF0EA87) (tstamp 5D66A2B3) + (at 135.6907 215.533 90) + (path /5D4BB8A3) + (fp_text reference D15 (at 1.4237 1.4312 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) + (fp_text value ESD7951ST5G (at 0 0 270) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify left top)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (fp_line (start -0.7366 0.3302) (end -0.7366 -0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 0.3302) (end -0.7366 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.7112 -0.3302) (end 0.7112 0.3302) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7366 -0.3302) (end 0.7112 -0.3302) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.45 0 90) (size 0.3 0.4) (layers Top F.Paste F.Mask) + (net 127 /USB_hub/USB_4_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66950E) - (at 91.1899 193.943 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D659) - (fp_text reference C45 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D6697FA) + (at 96.3715 180.0238 90) + (path /5D0328DE/5D4FE12B/5D42D3B9) + (fp_text reference L3 (at 4.0018 2.8282 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 14 "Net-(C45-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 15 "Net-(C45-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 13 "Net-(C30-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66951E) - (at 97.5907 185.434 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42DAC0) - (fp_text reference C46 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D669803) + (at 91.1391 139.841 90) + (path /5D0328DE/5D4FEB2F/5D42D3B9) + (fp_text reference L4 (at -3.27 2) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 18 "Net-(C62-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669532) - (at 232.6171 169.4828 90) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D45320B) - (fp_text reference C5 (at -1.016 0.762 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D66980C) + (at 90.6565 100.6996 90) + (path /5D0328DE/5D42E225/5D42D3B9) + (fp_text reference L8 (at -3.27 2) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 76 "Net-(C5-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 3 "Net-(C12-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669542) - (at 98.0479 190.7426 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D229) - (fp_text reference C53 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D66A085) + (at 89.6683 59.2468 90) + (path /5D0328DE/5D42CD47/5D42D3B9) + (fp_text reference L2 (at 1.0808 -3.1813 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) + (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0 2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0 -2.25 90) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 8 "Net-(C13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0603 (layer Top) (tedit 0) (tstamp 5D669556) - (at 118.1647 200.0898 180) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D47774A) - (fp_text reference C54 (at -1.778 -0.889 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:SWPA6028S (layer Top) (tedit 5DF0E9C9) (tstamp 5D66DAC5) + (at 96.7017 89.676) + (path /5D0328DE/5D4FC17D/5D42D3B9) + (fp_text reference L5 (at -3.27 2) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "10uF, 10V" (at -1.778 1.778) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "6.8uH, SWPA6045S6R8MT" (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) ) - (fp_line (start 1.651 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.762 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 0.762) (end -0.762 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.762 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) + (fp_line (start -3 3) (end -3 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 3) (end -3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start 3 -3) (end 3 3) (layer F.SilkS) (width 0.127)) + (fp_line (start -3 -3) (end 3 -3) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 0 2.25) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at 0 -2.25) (size 5.7 1.7) (layers Top F.Paste F.Mask) + (net 23 "Net-(C21-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0603 (layer Top) (tedit 0) (tstamp 5D66957A) - (at 118.1647 201.7154 180) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D46FDA8) - (fp_text reference C56 (at -1.778 -0.889 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5E160420) + (at 200.387856 210.61934 180) + (path /5D032DC8/5D47AAF5) + (fp_text reference P1 (at 0.997856 -4.62026) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_text value "10uF, 10V" (at -1.778 1.778) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line (start 1.651 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.762 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 0.762) (end -0.762 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.762 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 109 /ethernet_frontend/AM_TRX3_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 108 /ethernet_frontend/AM_TRX3_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669589) - (at 129.6709 196.9402 90) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D492EC4) - (fp_text reference C57 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5E160402) + (at 209.09425 210.61934 180) + (path /5D032DC8/5D47CF84) + (fp_text reference P2 (at 0.83965 -4.50596) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 111 /ethernet_frontend/AM_TRX2_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 112 /ethernet_frontend/AM_TRX2_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669599) - (at 117.0217 197.88 90) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D4763C3) - (fp_text reference C58 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5E1603E4) + (at 217.800644 210.61934 180) + (path /5D032DC8/5D47E762) + (fp_text reference P3 (at 1.075144 -4.68376) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 113 /ethernet_frontend/AM_TRX1_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 110 /ethernet_frontend/AM_TRX1_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695A9) - (at 119.5109 205.3692 180) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D492F4C) - (fp_text reference C59 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5E1603C6) + (at 226.50704 210.61934 180) + (path /5D032DC8/5D47E7A5) + (fp_text reference P4 (at 1.03124 -4.64566) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 92 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:C0603 (layer Top) (tedit 0) (tstamp 5D6695B9) - (at 131.0933 197.6006 90) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D470A72) - (fp_text reference C60 (at -1.778 -0.889 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 114 /ethernet_frontend/AM_TRX0_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 115 /ethernet_frontend/AM_TRX0_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669977) + (at 191.681462 210.61934 180) + (path /5D032DC8/5D482073) + (fp_text reference P5 (at 1.117962 -4.62026) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_text value "10uF, 10V" (at -1.778 1.778 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line (start 1.651 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.762 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 0.762) (end -0.762 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.762 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) - (net 92 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 122 /ethernet_frontend/BM_TRX0_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 123 /ethernet_frontend/BM_TRX0_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695C8) - (at 132.9983 205.5254 90) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D497BD9) - (fp_text reference C61 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669981) + (at 165.56228 210.61934 180) + (path /5D032DC8/5D481FAA) + (fp_text reference P6 (at 0.74168 -4.84886) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_text value 18pF (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + ) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 117 /ethernet_frontend/BM_TRX3_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 116 /ethernet_frontend/BM_TRX3_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D66998B) + (at 174.268674 210.61934 180) + (path /5D032DC8/5D481FED) + (fp_text reference P7 (at -0.838926 -3.70586) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + ) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 119 /ethernet_frontend/BM_TRX2_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 120 /ethernet_frontend/BM_TRX2_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:GDT-LT-B3D090L (layer Top) (tedit 5DF0D801) (tstamp 5D669995) + (at 182.975068 210.61934 180) + (path /5D032DC8/5D482030) + (fp_text reference P8 (at -1.111432 -3.54076) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_text value 3R420L (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + ) + (fp_line (start 3.8 -2.75) (end -3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.8 2.75) (end 3.8 -2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 2.75) (end 3.8 2.75) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -2.75) (end -3.8 2.75) (layer F.SilkS) (width 0.127)) + (pad 2 smd rect (at 3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 121 /ethernet_frontend/BM_TRX1_P) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0 0 180) (size 2 5.5) (layers Top F.Paste F.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -3.48 0 180) (size 1 5.5) (layers Top F.Paste F.Mask) + (net 118 /ethernet_frontend/BM_TRX1_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE54003) + (at 177.34788 53.95468 270) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D44B71E) + (fp_text reference R28 (at 1.25222 0.27178 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value 330 (at -3.46964 -0.24384 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 93 "Net-(C61-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 170 "Net-(5G_WLAN0-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 169 /5G_WLAN_LED_0) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695D8) - (at 87.0751 142.0254 270) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D488) - (fp_text reference C62 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF7C046) + (at 207.89138 53.95468 270) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D4487F6) + (fp_text reference R24 (at -1.08458 -1.55702 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value 330 (at -3.44932 0.39624 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 17 "Net-(C62-Pad2)") (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 18 "Net-(C62-Pad1)") (solder_mask_margin 0.0508)) + (net 166 "Net-(PWR1-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695E8) - (at 130.2297 202.2742) - (descr "CAPACITOR

\nchip") - (path /5D032896/5D497D13) - (fp_text reference C63 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF1920D) + (at 226.22764 62.61608) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D44A608) + (fp_text reference R7 (at -2.73304 0.42672) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 18pF (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value 330 (at -3.41884 0.508) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (net 159 /GPIO22) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 94 "Net-(C63-Pad1)") (solder_mask_margin 0.0508)) + (net 158 "Net-(2G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D6695F8) - (at 94.5427 145.1242 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42DBCD) - (fp_text reference C64 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DEFE4E0) + (at 234.53728 95.2031 180) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1A0459) + (fp_text reference R118 (at -4.2024 0.31378) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + (fp_text value 0 (at 1.15948 0.39742) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 148 "Net-(PCIE1-Pad22)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 189 /PCIe_1_RST) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66960C) - (at 90.8597 149.1628 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D43058C) - (fp_text reference C65 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE3D9D3) + (at 222.504 78.613 90) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1A5891) + (fp_text reference R20 (at 4.7625 0.254 270) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) + (fp_text value TBD (at -1.905 -1.397 270) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 294 /GPIO3-EJTAG_TMS) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 138 "Net-(PCIE1-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669620) - (at 86.0337 153.176 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D659) - (fp_text reference C66 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE49E9A) + (at 226.88296 80.05064) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1AF5AD) + (fp_text reference R49 (at -1.07696 -1.56464) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value TBD (at -1.905 -1.397) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 19 "Net-(C66-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 20 "Net-(C66-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669630) - (at 92.3837 145.1242 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42DAC0) - (fp_text reference C67 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 144 /PCIe_1_CLK_P) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 142 /PCIe_1_CLK_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE3D973) + (at 234.51696 79.4551 90) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1F3D95) + (fp_text reference R80 (at 6.2396 0.24254 270) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 180 /PCIe_1_RX_N) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 249 /sheet5D1650DF/PCIe_RX_bis_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669644) - (at 93.0187 149.1628 90) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5DE3D8D7) + (at 242.24556 79.72434) (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D229) - (fp_text reference C68 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D1650F5/5D1C5785) + (fp_text reference C75 (at -1.00906 -1.49234) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669678) - (at 84.2049 102.0966 90) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42F1FB) - (fp_text reference C90 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE43712) + (at 235.50756 79.4551 90) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1F3F5D) + (fp_text reference R110 (at 6.2396 0.39494 270) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value "0.1uF, 50V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 96 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 186 /PCIe_1_RX_P) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 250 /sheet5D1650DF/PCIe_RX_bis_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669688) - (at 96.0667 99.4296 180) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42DC2B) - (fp_text reference C91 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE43786) + (at 237.71482 79.46272 90) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1F7584) + (fp_text reference R111 (at 6.24722 0.28318 270) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 187 /PCIe_1_TX_N) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 251 /sheet5D1650DF/PCIe_TX_bis_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669698) - (at 96.0667 100.4202 180) - (descr "CAPACITOR

\nchip") - (path /5D0328DE/5D42E225/5D42DCB2) - (fp_text reference C92 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DE43843) + (at 238.68002 79.46272 90) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1F758C) + (fp_text reference R112 (at 6.31072 0.58798 270) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 0 (at -1.905 -1.397 270) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 188 /PCIe_1_TX_P) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 252 /sheet5D1650DF/PCIe_TX_bis_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:ETHERNET-1X2 (layer Top) (tedit 0) (tstamp 5D669738) - (at 197.8953 226.3534 180) - (path /5D9F8A35) - (fp_text reference J2 (at 0 0 180) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DEFE510) + (at 234.53728 94.0601 180) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1A051B) + (fp_text reference R116 (at 1.25352 1.39074) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_text value ETHERNET_2PORT (at 0 0 180) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text value 1.5k (at -3.81124 0.37982) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 3.5 -3) (end 3.5 -5.5) (layer F.SilkS) (width 0.127)) - (fp_line (start 5.5 -3) (end 3.5 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 5.5 -1.5) (end 5.5 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 10 -1.5) (end 5.5 -1.5) (layer F.SilkS) (width 0.127)) - (fp_line (start 10 -3) (end 10 -1.5) (layer F.SilkS) (width 0.127)) - (fp_line (start 12 -3) (end 10 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start 12 -5.5) (end 12 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start -4 -3) (end -4 -5.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -6 -3) (end -4 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start -6 -1.5) (end -6 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start -10.5 -1.5) (end -6 -1.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -10.5 -3) (end -10.5 -1.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -12.5 -3) (end -10.5 -3) (layer F.SilkS) (width 0.127)) - (fp_line (start -12.5 -5.5) (end -12.5 -3) (layer F.SilkS) (width 0.127)) - (fp_text user Front (at -2.5 -1.84 180) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 148 "Net-(PCIE1-Pad22)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DF00846) + (at 232.03916 95.82404 90) + (descr "RESISTOR

\nchip") + (path /5D1650F5/5D1A04F3) + (fp_text reference R117 (at 1.40208 -0.8382 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start 16.25 -5.46) (end 16.25 10.29) (layer F.SilkS) (width 0.127)) - (fp_line (start -16.25 -5.46) (end -16.25 10.29) (layer F.SilkS) (width 0.127)) - (fp_line (start -16.25 -5.46) (end 16.25 -5.46) (layer F.SilkS) (width 0.127)) - (fp_line (start -16.25 10.29) (end 16.25 10.29) (layer F.SilkS) (width 0.127)) - (pad "" np_thru_hole circle (at 14.225 0 180) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask)) - (pad "" np_thru_hole circle (at -14.225 0 180) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask)) - (pad S2 thru_hole circle (at -16 3.43 180) (size 2.55 2.55) (drill 1.7) (layers *.Cu *.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad S1 thru_hole circle (at 16 3.43 180) (size 2.55 2.55) (drill 1.7) (layers *.Cu *.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 2-8 thru_hole circle (at -4.305 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 119 /ethernet_frontend/AM_TRX3_N) (solder_mask_margin 0.0508)) - (pad 2-7 thru_hole circle (at -5.325 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 120 /ethernet_frontend/AM_TRX3_P) (solder_mask_margin 0.0508)) - (pad 2-6 thru_hole circle (at -6.345 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 121 /ethernet_frontend/AM_TRX1_N) (solder_mask_margin 0.0508)) - (pad 2-5 thru_hole circle (at -7.365 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 122 /ethernet_frontend/AM_TRX2_P) (solder_mask_margin 0.0508)) - (pad 2-4 thru_hole circle (at -8.385 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 123 /ethernet_frontend/AM_TRX2_N) (solder_mask_margin 0.0508)) - (pad 2-3 thru_hole circle (at -9.405 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 124 /ethernet_frontend/AM_TRX1_P) (solder_mask_margin 0.0508)) - (pad 2-2 thru_hole circle (at -10.425 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 125 /ethernet_frontend/AM_TRX0_P) (solder_mask_margin 0.0508)) - (pad 2-1 thru_hole rect (at -11.445 2.54 180) (size 1.27 1.27) (drill 0.9398) (layers *.Cu *.Mask) - (net 126 /ethernet_frontend/AM_TRX0_N) (solder_mask_margin 0.0508)) - (pad 1-8 thru_hole circle (at 11.445 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 127 /ethernet_frontend/BM_TRX3_N) (solder_mask_margin 0.0508)) - (pad 1-7 thru_hole circle (at 10.425 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 128 /ethernet_frontend/BM_TRX3_P) (solder_mask_margin 0.0508)) - (pad 1-6 thru_hole circle (at 9.405 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 129 /ethernet_frontend/BM_TRX1_N) (solder_mask_margin 0.0508)) - (pad 1-5 thru_hole circle (at 8.385 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 130 /ethernet_frontend/BM_TRX2_P) (solder_mask_margin 0.0508)) - (pad 1-4 thru_hole circle (at 7.365 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 131 /ethernet_frontend/BM_TRX2_N) (solder_mask_margin 0.0508)) - (pad 1-3 thru_hole circle (at 6.345 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 132 /ethernet_frontend/BM_TRX1_P) (solder_mask_margin 0.0508)) - (pad 1-2 thru_hole circle (at 5.325 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) - (net 133 /ethernet_frontend/BM_TRX0_P) (solder_mask_margin 0.0508)) - (pad 1-1 thru_hole rect (at 4.305 2.54 180) (size 1.27 1.27) (drill 0.9398) (layers *.Cu *.Mask) - (net 134 /ethernet_frontend/BM_TRX0_N) (solder_mask_margin 0.0508)) + (fp_text value 0 (at 0.08636 -0.53068) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 147 "Net-(PCIE1-Pad20)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 290 /GPIO14-PCIe1_nDISABLE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:KF350-2P (layer Top) (tedit 0) (tstamp 5D669762) - (at 102.7977 217.5904 180) - (path /5D605BA6) - (fp_text reference J3 (at -3.81 -3.81) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5DE438CA) + (at 242.24556 80.79114) + (descr "CAPACITOR

\nchip") + (path /5D1650F5/5D1C583F) + (fp_text reference C116 (at 1.97544 -0.27314) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_text value Conn_01x02 (at -3.81 5.08) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397) (layer B.Fab) hide + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_line (start 3.5 -3.5) (end -3.5 -3.5) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.5 3.5) (end 3.5 -3.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.5 3.5) (end 3.5 3.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.5 -3.5) (end -3.5 3.5) (layer F.SilkS) (width 0.127)) - (pad 2 thru_hole circle (at 1.75 0 180) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 thru_hole circle (at -1.75 0 180) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask) - (net 135 /power_supply/12V_IN) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:M4 (layer Top) (tedit 0) (tstamp 5D66976B) - (at 165.8151 223.6102 180) - (path /5D49E0A2) - (fp_text reference EARTH1 (at -5.08 -5.08 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5340A) + (at 226.22764 56.41848) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D449F02) + (fp_text reference R123 (at -4.20624 0.35052) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value M4 (at -5.08 6.35) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 330 (at -3.5052 0.44704) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start -5.5 4.25) (end -5.5 -4.25) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.5 4.25) (end -5.5 4.25) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.5 -4.25) (end 6.5 4.25) (layer F.SilkS) (width 0.127)) - (fp_line (start -5.5 -4.25) (end 6.5 -4.25) (layer F.SilkS) (width 0.127)) - (pad 4 thru_hole circle (at 3.75 2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 3 thru_hole circle (at -3.75 2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at 3.75 -2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) - (pad 1 thru_hole circle (at -3.75 -2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) - (net 102 /EARTH) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 190 /LEDN1000_3) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 191 "Net-(P3_1000-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:USB-DUAL-JS-AF10-002 (layer Top) (tedit 0) (tstamp 5D669776) - (at 146.8159 216.676 90) - (path /5D75DBE4) - (fp_text reference J5 (at 0 -10.16 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) - ) - (fp_text value USB-CON-A-DUALC39472 (at 0 0 90) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15))) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5C339) + (at 223.85528 54.86908) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D449CFE) + (fp_text reference R17 (at 1.20904 0.40132) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text user FRONT (at -12.7 2.54 180) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + (fp_text value 330 (at -3.35788 0.57912) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 2.4 -6.55) (end 2.4 6.55) (layer F.SilkS) (width 0.127)) - (fp_line (start -15.1 -6.55) (end -15.1 6.55) (layer F.SilkS) (width 0.127)) - (fp_line (start -15.1 6.55) (end 2.4 6.55) (layer F.SilkS) (width 0.127)) - (fp_line (start -15.1 -6.55) (end 2.4 -6.55) (layer F.SilkS) (width 0.127)) - (pad 12 thru_hole circle (at -5.33 6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) - (net 37 "Net-(J5-Pad12)") (solder_mask_margin 0.0508)) - (pad 11 thru_hole circle (at -5.33 -6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) - (net 38 "Net-(J5-Pad11)") (solder_mask_margin 0.0508)) - (pad 10 thru_hole circle (at 0.35 6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) - (net 39 "Net-(J5-Pad10)") (solder_mask_margin 0.0508)) - (pad 9 thru_hole circle (at 0.35 -6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) - (net 40 "Net-(J5-Pad9)") (solder_mask_margin 0.0508)) - (pad 8 thru_hole circle (at -2.62 3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 7 thru_hole circle (at -2.62 1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 136 /USB_hub/USB_3_P) (solder_mask_margin 0.0508)) - (pad 6 thru_hole circle (at -2.62 -1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 137 /USB_hub/USB_3_N) (solder_mask_margin 0.0508)) - (pad 5 thru_hole circle (at -2.62 -3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 4 thru_hole circle (at 0 3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 thru_hole circle (at 0 1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 138 /USB_hub/USB_4_P) (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at 0 -1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 139 /USB_hub/USB_4_N) (solder_mask_margin 0.0508)) - (pad 1 thru_hole circle (at 0 -3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 163 /LEDN_3) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 164 "Net-(P3_100-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:1X04 (layer Top) (tedit 0) (tstamp 5D66978A) - (at 88.4975 164.2758 180) - (descr "PIN HEADER") - (path /5DB76F0E) - (fp_text reference UART1 (at -5.1562 -1.8288 90) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5C309) + (at 223.8502 61.0743) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D44A62A) + (fp_text reference R27 (at 1.2954 -0.3302) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value Conn_01x04 (at -5.08 3.175) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 330 (at -3.38836 -0.25908) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_poly (pts (xy 3.556 0.254) (xy 4.064 0.254) (xy 4.064 -0.254) (xy 3.556 -0.254)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -4.064 0.254) (xy -3.556 0.254) (xy -3.556 -0.254) (xy -4.064 -0.254)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) - (fp_line (start 4.445 1.27) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 2.54 0.635) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 3.175 -1.27) (end 2.54 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 5.08 0.635) (end 4.445 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 5.08 -0.635) (end 5.08 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 4.445 -1.27) (end 5.08 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 3.175 -1.27) (end 4.445 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.175 1.27) (end -4.445 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -5.08 0.635) (end -4.445 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -4.445 -1.27) (end -5.08 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -5.08 -0.635) (end -5.08 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 1.27) (end -2.54 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -0.635 1.27) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0 0.635) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0 -0.635) (end 0 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -0.635 -1.27) (end 0 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 -1.27) (end -0.635 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -2.54 -0.635) (end -1.905 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -2.54 0.635) (end -3.175 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -2.54 -0.635) (end -2.54 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.175 -1.27) (end -2.54 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -4.445 -1.27) (end -3.175 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0.635 1.27) (end 0 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.905 1.27) (end 0.635 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 2.54 0.635) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 2.54 -0.635) (end 2.54 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.905 -1.27) (end 2.54 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0.635 -1.27) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0 -0.635) (end 0.635 -1.27) (layer F.SilkS) (width 0.1524)) - (pad 4 thru_hole oval (at 3.81 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 thru_hole oval (at 1.27 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 111 /UART_SOUT) (solder_mask_margin 0.0508)) - (pad 2 thru_hole oval (at -1.27 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 191 "Net-(R64-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 thru_hole oval (at -3.81 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 153 /5G_WLAN_LED_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 168 "Net-(5G_WLAN1-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:1X02 (layer Top) (tedit 0) (tstamp 5D6697B2) - (at 98.2511 126.2774 270) - (descr "PIN HEADER") - (path /5DE0918B) - (fp_text reference JP8 (at -2.6162 -1.8288 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.077216)) (justify right top)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669328) + (at 229.5437 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D47CF61) + (fp_text reference C10 (at 1.4618 -0.7405 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value Conn_01x02 (at -2.54 3.175 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) - (fp_line (start 0.635 1.27) (end 0 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.905 1.27) (end 0.635 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 2.54 0.635) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 2.54 -0.635) (end 2.54 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.905 -1.27) (end 2.54 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0.635 -1.27) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0 -0.635) (end 0.635 -1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -0.635 1.27) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -2.54 0.635) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 -1.27) (end -2.54 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -2.54 -0.635) (end -2.54 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0 0.635) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0 -0.635) (end 0 0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -0.635 -1.27) (end 0 -0.635) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 -1.27) (end -0.635 -1.27) (layer F.SilkS) (width 0.1524)) - (pad 2 thru_hole oval (at 1.27 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 140 /watchdog/RST_J-) (solder_mask_margin 0.0508)) - (pad 1 thru_hole oval (at -1.27 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 99 /RST_B) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 77 "Net-(C10-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:2X03 (layer Top) (tedit 0) (tstamp 5D6697C8) - (at 84.2811 126.3536 90) - (descr "PIN HEADER") - (path /5DD24EF7) - (fp_text reference WDT_CON1 (at -3.81 -3.175) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.077216)) (justify right top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669338) + (at 89.45626 182.894 270) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE35A) + (fp_text reference C100 (at 1.1824 -0.423 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value Conn_02x03 (at -3.81 4.445 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (fp_text value "0.1uF, 50V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_poly (pts (xy 2.286 1.524) (xy 2.794 1.524) (xy 2.794 1.016) (xy 2.286 1.016)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy 2.286 -1.016) (xy 2.794 -1.016) (xy 2.794 -1.524) (xy 2.286 -1.524)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -0.254 1.524) (xy 0.254 1.524) (xy 0.254 1.016) (xy -0.254 1.016)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -0.254 -1.016) (xy 0.254 -1.016) (xy 0.254 -1.524) (xy -0.254 -1.524)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -2.794 -1.016) (xy -2.286 -1.016) (xy -2.286 -1.524) (xy -2.794 -1.524)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -2.794 1.524) (xy -2.286 1.524) (xy -2.286 1.016) (xy -2.794 1.016)) (layer F.Fab) (width 0)) - (fp_line (start 1.905 2.54) (end 3.175 2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start 3.81 -1.905) (end 3.81 1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start 3.175 -2.54) (end 3.81 -1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.905 -2.54) (end 3.175 -2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.27 -1.905) (end 1.905 -2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start 3.175 2.54) (end 3.81 1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.27 1.905) (end 1.905 2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.175 2.54) (end -1.905 2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -0.635 2.54) (end 0.635 2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.27 -1.905) (end 1.27 1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.27 -1.905) (end -1.27 1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0.635 -2.54) (end 1.27 -1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start -0.635 -2.54) (end 0.635 -2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.27 -1.905) (end -0.635 -2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 -2.54) (end -1.27 -1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.175 -2.54) (end -1.905 -2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.81 -1.905) (end -3.175 -2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.81 1.905) (end -3.81 -1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start 0.635 2.54) (end 1.27 1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.27 1.905) (end -0.635 2.54) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.905 2.54) (end -1.27 1.905) (layer F.SilkS) (width 0.1524)) - (fp_line (start -3.81 1.905) (end -3.175 2.54) (layer F.SilkS) (width 0.1524)) - (pad 6 thru_hole circle (at 2.54 -1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 5 thru_hole circle (at 2.54 1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 100 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) - (pad 4 thru_hole circle (at 0 -1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 227 /WL_MOSI) (solder_mask_margin 0.0508)) - (pad 3 thru_hole circle (at 0 1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 228 /WL_SLK) (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at -2.54 -1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 1 thru_hole circle (at -2.54 1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 190 /WL_MISO) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 95 /POWER_EN_5V) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SOT-23 (layer Top) (tedit 0) (tstamp 5D66999F) - (at 241.6087 179.1602) - (descr "Small Outline Transistor") - (path /5D032DC8/5DD00C18) - (fp_text reference Q11 (at -1.397 -3.302 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.077216)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669348) + (at 101.65842 185.07964 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42DC2B) + (fp_text reference C102 (at -1.34366 1.52908 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value BSS138-7-F (at -1.397 -1.778) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_poly (pts (xy -0.1778 0.9398) (xy 0.2032 0.9398) (xy 0.2032 0.4318) (xy -0.1778 0.4318)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.143 -0.4318) (xy -0.762 -0.4318) (xy -0.762 -0.9398) (xy -1.143 -0.9398)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy 0.7874 -0.4318) (xy 1.1684 -0.4318) (xy 1.1684 -0.9398) (xy 0.7874 -0.9398)) (layer F.Fab) (width 0)) - (fp_line (start -1.4224 0.381) (end -1.4224 -0.381) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.4732 0.381) (end -1.4224 0.381) (layer F.SilkS) (width 0.1524)) - (fp_line (start 1.4732 -0.381) (end 1.4732 0.381) (layer F.SilkS) (width 0.1524)) - (fp_line (start -1.4224 -0.381) (end 1.4732 -0.381) (layer F.SilkS) (width 0.1524)) - (pad 1 smd rect (at 0 1.016) (size 0.7874 0.889) (layers Top F.Paste F.Mask) - (net 70 "Net-(Q11-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -0.95 -1.016) (size 0.7874 0.889) (layers Top F.Paste F.Mask) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 0.95 -1.016) (size 0.7874 0.889) (layers Top F.Paste F.Mask) - (net 68 "Net-(Q11-Pad3)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SI4435 (layer Top) (tedit 0) (tstamp 5D6699AC) - (at 244.3265 185.9928 270) - (path /5D032DC8/5DD0095A) - (fp_text reference Q9 (at -2.7 -2.9 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669358) + (at 96.2699 139.1552 180) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42DC2B) + (fp_text reference C103 (at -1.016 -0.762) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value Si4435DDY-T1 (at -2.6 4.3 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_circle (center -3.9878 -1.9558) (end -3.6576 -1.9558) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -1.2 2.5) (xy 3.65 2.5) (xy 3.65 -2.5) (xy -1.2 -2.5)) (layer Dwgs.User) (width 0)) - (fp_line (start -3.4 2.7) (end -3.4 -2.7) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.6 2.7) (end -3.4 2.7) (layer F.SilkS) (width 0.127)) - (fp_line (start 3.6 -2.7) (end 3.6 2.7) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.4 -2.7) (end 3.6 -2.7) (layer F.SilkS) (width 0.127)) - (pad P$8 smd rect (at 2.52725 -1.9305 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) - (net 166 /ethernet_frontend/POE_OUT) (solder_mask_margin 0.0508)) - (pad P$7 smd rect (at 2.52725 -0.635 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) - (net 166 /ethernet_frontend/POE_OUT) (solder_mask_margin 0.0508)) - (pad P$6 smd rect (at 2.52725 0.635 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) - (net 166 /ethernet_frontend/POE_OUT) (solder_mask_margin 0.0508)) - (pad P$5 smd rect (at 2.52725 1.905 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) - (net 166 /ethernet_frontend/POE_OUT) (solder_mask_margin 0.0508)) - (pad P$4 smd rect (at -2.66 1.905 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) - (net 69 "Net-(Q9-PadP$4)") (solder_mask_margin 0.0508)) - (pad P$3 smd rect (at -2.66 0.635 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) - (pad P$2 smd rect (at -2.66 -0.635 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) - (pad P$1 smd rect (at -2.66 -1.905 270) (size 1.98 0.568) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D6699BD) - (at 232.6085 188.3042 270) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D4F4E73) - (fp_text reference R1 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669368) + (at 226.4885 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D47E73F) + (fp_text reference C11 (at 1.4872 -0.7079 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 167 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 78 "Net-(C11-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D6699CD) - (at 87.2021 191.022 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D571) - (fp_text reference R10 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669378) + (at 107.62872 75.43156 270) + (descr "CAPACITOR

\nchip") + (path /5D032C97/5D1C5785) + (fp_text reference C110 (at 1.27644 0.31372 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 174 "Net-(R10-Pad2)") (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF929C9) - (at 107.36834 68.707 180) - (descr "RESISTOR

\nchip") - (path /5D032C97/5D1F3F5D) - (fp_text reference R100 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5E694225) + (at 108.64472 75.43156 270) + (descr "CAPACITOR

\nchip") + (path /5D032C97/5D1C583F) + (fp_text reference C111 (at 1.27644 0.18672 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 0 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 196 /PCIe_0_RX_P) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 271 /pcie0/PCIe_RX_bis_P) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D6699ED) - (at 107.36834 70.87108 180) - (descr "RESISTOR

\nchip") - (path /5D032C97/5D1F7584) - (fp_text reference R101 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693A8) + (at 86.5417 102.122 270) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42D488) + (fp_text reference C12 (at -1.016 -0.762 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 0 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 197 /PCIe_0_TX_N) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 270 /pcie0/PCIe_TX_bis_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 2 "Net-(C12-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 3 "Net-(C12-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D6699FD) - (at 107.36698 71.9061 180) - (descr "RESISTOR

\nchip") - (path /5D032C97/5D1F758C) - (fp_text reference R102 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693B8) + (at 117.2249 175.40862 180) + (descr "CAPACITOR

\nchip") + (path /5E2BEE88) + (fp_text reference C121 (at 1.1342 0.30102) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 0 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 198 /PCIe_0_TX_P) (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 269 /pcie0/PCIe_TX_bis_P) (solder_mask_margin 0.0508)) + (net 96 /GPIO17) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A0D) - (at 124.45882 68.87848 90) - (descr "RESISTOR

\nchip") - (path /5D032C97/5D1A051B) - (fp_text reference R106 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693C8) + (at 93.1965 130.2398 180) + (descr "CAPACITOR

\nchip") + (path /5D032C38/5D1B5630) + (fp_text reference C124 (at -1.7995 -1.3957) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 1.5k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 50 "Net-(PCIE0-Pad22)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A1D) - (at 124.0282 66.58356 180) - (descr "RESISTOR

\nchip") - (path /5D032C97/5D1A04F3) - (fp_text reference R107 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5E16D166) + (at 98.71456 122.77598) + (descr "CAPACITOR

\nchip") + (path /5D032C38/5D15063F) + (fp_text reference C125 (at 1.17094 0.35052) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 0 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value 0.01uF (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 144 "Net-(PCIE0-Pad20)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 110 /GPIO12) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A2D) - (at 125.66904 68.8848 90) - (descr "RESISTOR

\nchip") - (path /5D032C97/5D1A0459) - (fp_text reference R108 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) - ) - (fp_text value 0 (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) - ) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 199 /PCIe_0_RST) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 50 "Net-(PCIE0-Pad22)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 97 /RST_B) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A3D) - (at 175.97882 53.95722 90) - (descr "RESISTOR

\nchip") - (path /5D3C88FD) - (fp_text reference R109 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6693E8) + (at 94.27972 119.4435) + (descr "CAPACITOR

\nchip") + (path /5D032C38/5D1501FA) + (fp_text reference C126 (at -4.10972 -0.381) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value 0 (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 0.01uF (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 141 /pcie0/LED_WLAN) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 183 /5G_WLAN_LED_0) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 98 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A4D) - (at 82.7317 111.2406 90) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D42E225/5D42D5CB) - (fp_text reference R11 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5E167CD9) + (at 144.13992 211.64804) + (descr "CAPACITOR

\nchip") + (path /5D08F1AF) + (fp_text reference C130 (at -5.03682 0.23876) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value "10uF, 10V" (at -0.889 2.286) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 173 "Net-(R11-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669ABD) - (at 87.2021 193.181 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D5CB) - (fp_text reference R12 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669406) + (at 211.1885 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D482050) + (fp_text reference C137 (at 1.4872 -1.2448 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 174 "Net-(R10-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 99 "Net-(C137-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669ADD) - (at 226.22764 59.51728) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D44A5F7) - (fp_text reference R124 (at 1.27 0.39116) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669416) + (at 94.1363 105.9828 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42DBCD) + (fp_text reference C14 (at -1.651 -1.143 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 330 (at -3.429 0.44704) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 206 /LEDN1000_4) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 207 "Net-(P4_1000-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669AED) - (at 92.2059 193.943 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D2DE) - (fp_text reference R13 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66942A) + (at 90.8597 109.9452 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42D229) + (fp_text reference C15 (at -1.651 -1.143) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 16 "Net-(R13-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669AFD) - (at 90.1485 193.943 90) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FE12B/5D42D605) - (fp_text reference R16 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66943E) + (at 85.7289 114.06 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42D659) + (fp_text reference C16 (at -1.016 -0.762 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (net 4 "Net-(C16-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 15 "Net-(C45-Pad1)") (solder_mask_margin 0.0508)) + (net 5 "Net-(C16-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669B1D) - (at 91.1899 182.894 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FE353) - (fp_text reference R18 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) - ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 97 /POWER_EN_5V) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66944E) + (at 92.0027 105.9828 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42DAC0) + (fp_text reference C17 (at -1.651 -1.143 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) + ) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669B2D) - (at 220.3743 188.3042 270) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D4DF89D) - (fp_text reference R2 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669462) + (at 92.9679 109.9452 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D43058C) + (fp_text reference C19 (at -1.651 -1.143) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 167 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669B4D) - (at 130.3059 219.1398) - (descr "RESISTOR

\nchip") - (path /5E2BEE06) - (fp_text reference R21 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669486) + (at 92.4345 182.894 270) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D488) + (fp_text reference C30 (at -1.1824 0.3595 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value 330 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 98 /GPIO17) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 12 "Net-(C30-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 13 "Net-(C30-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R1206 (layer Bottom) (tedit 0) (tstamp 5D669B5D) - (at 232.9727 193.7398 90) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D662C5E) - (fp_text reference R22 (at -1.397 1.143 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5E69AD75) + (at 99.822 185.43016 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42DBCD) + (fp_text reference C31 (at -4.24434 -0.1651 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value 0 (at -1.397 -2.413 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) ) - (fp_line (start -2.667 -1.016) (end -2.667 1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start 2.667 -1.016) (end -2.667 -1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start 2.667 1.016) (end 2.667 -1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start -2.667 1.016) (end 2.667 1.016) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.3 -0.7) (xy 0.3 -0.7) (xy 0.3 0.7) (xy -0.3 0.7)) (layer B.Adhes) (width 0)) - (fp_poly (pts (xy 0.9525 -0.8763) (xy 1.6891 -0.8763) (xy 1.6891 0.8763) (xy 0.9525 0.8763)) (layer B.Fab) (width 0)) - (fp_poly (pts (xy -1.6891 -0.8763) (xy -0.9525 -0.8763) (xy -0.9525 0.8763) (xy -1.6891 0.8763)) (layer B.Fab) (width 0)) - (fp_line (start 0.9525 0.8128) (end -0.9652 0.8128) (layer B.Fab) (width 0.1524)) - (fp_line (start 0.9525 -0.8128) (end -0.9652 -0.8128) (layer B.Fab) (width 0.1524)) - (pad 1 smd rect (at -1.71 0 90) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 1.71 0 90) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) - (net 167 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669B7B) - (at 223.4405 188.3042 270) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D4DFC33) - (fp_text reference R29 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694AA) + (at 223.4285 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D47E782) + (fp_text reference C33 (at 1.3983 -0.7975 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 185 /ethernet_frontend/MCT4) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 82 "Net-(C33-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669B8B) - (at 241.9897 175.975 180) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D88FC3A) - (fp_text reference R3 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694BA) + (at 220.3685 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D481F87) + (fp_text reference C34 (at 1.4618 -0.9633 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value 4.7k (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 117 /GPIO1) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 68 "Net-(Q11-Pad3)") (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 83 "Net-(C34-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669B9B) - (at 214.2365 188.3042 270) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D4DFC3A) - (fp_text reference R30 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694CA) + (at 217.3085 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D481FCA) + (fp_text reference C35 (at 1.4618 -0.7862 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 186 /ethernet_frontend/MCT7) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 84 "Net-(C35-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669BAB) - (at 211.2365 188.3042 270) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D4EA21B) - (fp_text reference R31 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D6694DA) + (at 214.2485 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D48200D) + (fp_text reference C37 (at 1.538 -0.8504 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 187 /ethernet_frontend/MCT8) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 85 "Net-(C37-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669BBB) - (at 241.4309 181.37) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D87479D) - (fp_text reference R32 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D6694FA) + (at 95.9397 190.7426 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D43058C) + (fp_text reference C44 (at -2.1577 0.9613) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 68k (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66950E) + (at 91.1899 193.943 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D659) + (fp_text reference C45 (at -3.34642 0.45584 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 69 "Net-(Q9-PadP$4)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 70 "Net-(Q11-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 14 "Net-(C45-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 15 "Net-(C45-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0603 (layer Top) (tedit 0) (tstamp 5D669BCB) - (at 238.9417 187.1612) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D8661A5) - (fp_text reference R33 (at -1.651 -0.889) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66951E) + (at 97.5907 185.434 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42DAC0) + (fp_text reference C46 (at -1.9672 -1.947 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value "0 1/10W" (at -1.651 1.778) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) ) - (fp_line (start 1.651 0.762) (end 0.889 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.889 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 0.762) (end -0.889 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.889 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy -0.8382 0.4318) (xy -0.4318 0.4318) (xy -0.4318 -0.4318) (xy -0.8382 -0.4318)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy 0.4318 0.4318) (xy 0.8382 0.4318) (xy 0.8382 -0.4318) (xy 0.4318 -0.4318)) (layer F.Fab) (width 0)) - (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 0.432 -0.356) (end -0.432 -0.356) (layer F.Fab) (width 0.1524)) - (fp_line (start -0.432 0.356) (end 0.432 0.356) (layer F.Fab) (width 0.1524)) - (pad 2 smd rect (at 0.85 0) (size 1 1.1) (layers Top F.Paste F.Mask) - (net 166 /ethernet_frontend/POE_OUT) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.85 0) (size 1 1.1) (layers Top F.Paste F.Mask) - (net 168 /ethernet_frontend/MCT2) (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669BDF) - (at 229.5389 190.9458 90) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D63CAC2) - (fp_text reference R4 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D669532) + (at 232.6037 169.4828 90) + (descr "CAPACITOR

\nchip") + (path /5D032DC8/5D45320B) + (fp_text reference C5 (at 1.3729 -0.6001 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 168 /ethernet_frontend/MCT2) (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 88 "Net-(C40-Pad1)") (solder_mask_margin 0.0508)) + (net 75 "Net-(C5-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669BEF) - (at 98.2257 121.68) - (descr "RESISTOR

\nchip") - (path /5D032C38/5D150638) - (fp_text reference R43 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669542) + (at 98.0479 190.7426 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D229) + (fp_text reference C53 (at -2.1577 1.2788) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 99 /RST_B) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669BFF) - (at 241.9897 176.986 180) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D88FD1C) - (fp_text reference R44 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:C0603 (layer Top) (tedit 0) (tstamp 5E16A836) + (at 118.1647 200.0898 180) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D47774A) + (fp_text reference C54 (at -1.8757 1.1824 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value 47k (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "10uF, 10V" (at -1.778 1.778) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.762 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.762) (end -0.762 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.762 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:C0603 (layer Top) (tedit 0) (tstamp 5E16A891) + (at 118.1647 201.7154 180) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D46FDA8) + (fp_text reference C56 (at 0.296 -0.9385) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value "10uF, 10V" (at -1.778 1.778) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.651 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.762 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.762) (end -0.762 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.762 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.85 0 180) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669589) + (at 129.6709 196.9402 90) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D492EC4) + (fp_text reference C57 (at -1.1925 1.5201 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 68 "Net-(Q11-Pad3)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C0F) - (at 83.4937 151.0678 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D571) - (fp_text reference R45 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669599) + (at 117.0217 197.88 90) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D4763C3) + (fp_text reference C58 (at 1.1316 -2.2772 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 189 "Net-(R45-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C1F) - (at 83.4937 153.2522 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D5CB) - (fp_text reference R47 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695A9) + (at 119.50192 205.49616 180) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D492F4C) + (fp_text reference C59 (at -1.13538 -0.77724) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 189 "Net-(R45-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 90 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669C3F) - (at 217.5295 194.0268 180) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D6301C2) - (fp_text reference R5 (at -1.905 0.635) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (module LibreRouter_MegaBoard:C0603 (layer Top) (tedit 0) (tstamp 5D6695B9) + (at 132.19938 196.54102 90) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D470A72) + (fp_text reference C60 (at -1.33604 1.7526 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 75 (at -1.905 -1.397) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (fp_text value "10uF, 10V" (at -1.778 1.778 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 169 /ethernet_frontend/MCT6) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 89 "Net-(C41-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.651 0.762) (end 0.762 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.762 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.762) (end -0.762 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.762 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.85 0 90) (size 1.1 1) (layers Top F.Paste F.Mask) + (net 90 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C4F) - (at 91.3169 130.951 270) - (descr "RESISTOR

\nchip") - (path /5D171F88) - (fp_text reference R50 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695C8) + (at 132.9983 205.5254 90) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D497BD9) + (fp_text reference C61 (at 1.2586 1.5455 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 0 (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value 18pF (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 116 /WD_PCIe0_WAKE) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 190 /WL_MISO) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 91 "Net-(C61-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C5F) - (at 86.9735 153.176 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D2DE) - (fp_text reference R52 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695D8) + (at 87.0751 142.0254 270) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D488) + (fp_text reference C62 (at -3.3668 -0.3771 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (net 17 "Net-(C62-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 21 "Net-(R52-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C6F) - (at 94.4157 120.664 180) - (descr "RESISTOR

\nchip") - (path /5D032C38/5D15016D) - (fp_text reference R53 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) - ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) - ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 100 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (net 18 "Net-(C62-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C7F) - (at 85.0177 153.176 90) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D4FEB2F/5D42D605) - (fp_text reference R54 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D6695E8) + (at 130.2297 202.2742) + (descr "CAPACITOR

\nchip") + (path /5D032896/5D497D13) + (fp_text reference C63 (at -1.21802 -1.3475) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 18pF (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 20 "Net-(C66-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 92 "Net-(C63-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C8F) - (at 243.6915 181.37) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D874841) - (fp_text reference R57 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D6695F8) + (at 94.5427 145.1242 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42DBCD) + (fp_text reference C64 (at 1.157 2.0027 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 100k (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 69 "Net-(Q9-PadP$4)") (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C9F) - (at 86.7957 114.06 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D42E225/5D42D2DE) - (fp_text reference R58 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5E6950BB) + (at 90.8597 149.1628 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D43058C) + (fp_text reference C65 (at -4.2786 0.4025 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 6 "Net-(R58-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CAF) - (at 84.7129 114.06 90) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D42E225/5D42D605) - (fp_text reference R59 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669620) + (at 86.0337 153.176 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D659) + (fp_text reference C66 (at -3.3388 0.4279 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (net 19 "Net-(C66-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 5 "Net-(C16-Pad1)") (solder_mask_margin 0.0508)) + (net 20 "Net-(C66-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669CBF) - (at 226.5719 188.3042 270) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D4DFAC1) - (fp_text reference R6 (at -1.905 0.635 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D669630) + (at 92.3837 145.1242 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42DAC0) + (fp_text reference C67 (at 1.2078 -1.1469 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 170 /ethernet_frontend/MCT3) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CCF) - (at 85.2209 102.0966 270) - (descr "RESISTOR

\nchip") - (path /5D0328DE/5D42F0F7) - (fp_text reference R60 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5E695134) + (at 93.0187 149.1628 90) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D229) + (fp_text reference C68 (at -4.2024 0.5041 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) + (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 96 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CDF) - (at 90.2247 160.4658 180) - (descr "RESISTOR

\nchip") - (path /5DBFA05D) - (fp_text reference R63 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5E70B428) + (at 83.58378 102.0826 270) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42F1FB) + (fp_text reference C90 (at -1.016 -0.762 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value "0.1uF, 50V" (at -1.143 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 113 /UART_SIN) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 94 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CEF) - (at 90.2247 161.5834 180) - (descr "RESISTOR

\nchip") - (path /5DBF9F7A) - (fp_text reference R64 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669688) + (at 96.0667 99.4296 180) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42DC2B) + (fp_text reference C91 (at -1.016 -0.762) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 191 "Net-(R64-Pad2)") (solder_mask_margin 0.0508)) + (net 79 /+3V3) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 113 /UART_SIN) (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CFF) - (at 118.8251 113.9076 180) - (descr "RESISTOR

\nchip") - (path /5D6C533C) - (fp_text reference R66 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D669698) + (at 96.0667 100.4202 180) + (descr "CAPACITOR

\nchip") + (path /5D0328DE/5D42E225/5D42DCB2) + (fp_text reference C92 (at -1.016 -0.762) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.5715 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (net 79 /+3V3) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 117 /GPIO1) (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D0F) - (at 118.8251 118.3526 180) - (descr "RESISTOR

\nchip") - (path /5D6C52AE) - (fp_text reference R67 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:ETHERNET-1X2 (layer Top) (tedit 0) (tstamp 5E69E903) + (at 197.8953 226.3534 180) + (path /5D9F8A35) + (fp_text reference J2 (at -18.7667 9.0945 180) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value ETHERNET_2PORT (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 115 /GPIO3) (solder_mask_margin 0.0508)) + (fp_line (start 3.5 -3) (end 3.5 -5.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 5.5 -3) (end 3.5 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 5.5 -1.5) (end 5.5 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 10 -1.5) (end 5.5 -1.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 10 -3) (end 10 -1.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 12 -3) (end 10 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start 12 -5.5) (end 12 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start -4 -3) (end -4 -5.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -6 -3) (end -4 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start -6 -1.5) (end -6 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start -10.5 -1.5) (end -6 -1.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -10.5 -3) (end -10.5 -1.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -12.5 -3) (end -10.5 -3) (layer F.SilkS) (width 0.127)) + (fp_line (start -12.5 -5.5) (end -12.5 -3) (layer F.SilkS) (width 0.127)) + (fp_text user Front (at -2.5 -1.84 180) (layer F.SilkS) hide + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_line (start 16.25 -5.46) (end 16.25 10.29) (layer F.SilkS) (width 0.127)) + (fp_line (start -16.25 -5.46) (end -16.25 10.29) (layer F.SilkS) (width 0.127)) + (fp_line (start -16.25 -5.46) (end 16.25 -5.46) (layer F.SilkS) (width 0.127)) + (fp_line (start -16.25 10.29) (end 16.25 10.29) (layer F.SilkS) (width 0.127)) + (pad "" np_thru_hole circle (at 14.225 0 180) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at -14.225 0 180) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask)) + (pad S2 thru_hole circle (at -16 3.43 180) (size 2.55 2.55) (drill 1.7) (layers *.Cu *.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad S1 thru_hole circle (at 16 3.43 180) (size 2.55 2.55) (drill 1.7) (layers *.Cu *.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 2-8 thru_hole circle (at -4.305 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 108 /ethernet_frontend/AM_TRX3_N) (solder_mask_margin 0.0508)) + (pad 2-7 thru_hole circle (at -5.325 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 109 /ethernet_frontend/AM_TRX3_P) (solder_mask_margin 0.0508)) + (pad 2-6 thru_hole circle (at -6.345 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 110 /ethernet_frontend/AM_TRX1_N) (solder_mask_margin 0.0508)) + (pad 2-5 thru_hole circle (at -7.365 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 111 /ethernet_frontend/AM_TRX2_P) (solder_mask_margin 0.0508)) + (pad 2-4 thru_hole circle (at -8.385 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 112 /ethernet_frontend/AM_TRX2_N) (solder_mask_margin 0.0508)) + (pad 2-3 thru_hole circle (at -9.405 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 113 /ethernet_frontend/AM_TRX1_P) (solder_mask_margin 0.0508)) + (pad 2-2 thru_hole circle (at -10.425 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 114 /ethernet_frontend/AM_TRX0_P) (solder_mask_margin 0.0508)) + (pad 2-1 thru_hole rect (at -11.445 2.54 180) (size 1.27 1.27) (drill 0.9398) (layers *.Cu *.Mask) + (net 115 /ethernet_frontend/AM_TRX0_N) (solder_mask_margin 0.0508)) + (pad 1-8 thru_hole circle (at 11.445 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 116 /ethernet_frontend/BM_TRX3_N) (solder_mask_margin 0.0508)) + (pad 1-7 thru_hole circle (at 10.425 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 117 /ethernet_frontend/BM_TRX3_P) (solder_mask_margin 0.0508)) + (pad 1-6 thru_hole circle (at 9.405 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 118 /ethernet_frontend/BM_TRX1_N) (solder_mask_margin 0.0508)) + (pad 1-5 thru_hole circle (at 8.385 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 119 /ethernet_frontend/BM_TRX2_P) (solder_mask_margin 0.0508)) + (pad 1-4 thru_hole circle (at 7.365 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 120 /ethernet_frontend/BM_TRX2_N) (solder_mask_margin 0.0508)) + (pad 1-3 thru_hole circle (at 6.345 2.54 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 121 /ethernet_frontend/BM_TRX1_P) (solder_mask_margin 0.0508)) + (pad 1-2 thru_hole circle (at 5.325 4.32 180) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) + (net 122 /ethernet_frontend/BM_TRX0_P) (solder_mask_margin 0.0508)) + (pad 1-1 thru_hole rect (at 4.305 2.54 180) (size 1.27 1.27) (drill 0.9398) (layers *.Cu *.Mask) + (net 123 /ethernet_frontend/BM_TRX0_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D1F) - (at 118.8251 111.6216 180) - (descr "RESISTOR

\nchip") - (path /5D6C5372) - (fp_text reference R68 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:KF350-2P (layer Top) (tedit 0) (tstamp 5D669762) + (at 102.7977 217.5904 180) + (path /5D605BA6) + (fp_text reference J3 (at -2.4472 -4.0246) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value Conn_01x02 (at -3.81 5.08) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (fp_line (start 3.5 -3.5) (end -3.5 -3.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.5 3.5) (end 3.5 -3.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.5 3.5) (end 3.5 3.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.5 -3.5) (end -3.5 3.5) (layer F.SilkS) (width 0.127)) + (pad 2 thru_hole circle (at 1.75 0 180) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 118 /GPIO0) (solder_mask_margin 0.0508)) + (pad 1 thru_hole circle (at -1.75 0 180) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask) + (net 298 /power_supply/VCC_IN) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5C3F9) - (at 223.85528 57.96788) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D449EF1) - (fp_text reference R77 (at 1.2954 0.3683) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:M4 (layer Top) (tedit 0) (tstamp 5E69EA6B) + (at 165.8151 223.6102 180) + (path /5D49E0A2) + (fp_text reference EARTH1 (at -6.2826 3.2906 90) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_text value 330 (at -3.41376 0.4826) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value M4 (at -5.08 6.35) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 192 /LEDN_4) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 193 "Net-(P4_100-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start -5.5 4.25) (end -5.5 -4.25) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.5 4.25) (end -5.5 4.25) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.5 -4.25) (end 6.5 4.25) (layer F.SilkS) (width 0.127)) + (fp_line (start -5.5 -4.25) (end 6.5 -4.25) (layer F.SilkS) (width 0.127)) + (pad 4 thru_hole circle (at 3.75 2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 3 thru_hole circle (at -3.75 2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at 3.75 -2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) + (pad 1 thru_hole circle (at -3.75 -2.5 180) (size 2.7 2.7) (drill 1.8) (layers *.Cu *.Mask) + (net 100 /EARTH) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R1206 (layer Bottom) (tedit 0) (tstamp 5D669D3F) - (at 221.9999 192.165 180) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D662C66) - (fp_text reference R8 (at -1.397 1.143) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) - ) - (fp_text value 0 (at -1.397 -2.413) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top mirror)) + (module LibreRouter_MegaBoard:USB-DUAL-JS-AF10-002 (layer Top) (tedit 0) (tstamp 5E69C272) + (at 146.8159 216.676 90) + (path /5D75DBE4) + (fp_text reference J5 (at 3.8494 -5.0458 180) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) - (fp_line (start -2.667 -1.016) (end -2.667 1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start 2.667 -1.016) (end -2.667 -1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start 2.667 1.016) (end 2.667 -1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start -2.667 1.016) (end 2.667 1.016) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.3 -0.7) (xy 0.3 -0.7) (xy 0.3 0.7) (xy -0.3 0.7)) (layer B.Adhes) (width 0)) - (fp_poly (pts (xy 0.9525 -0.8763) (xy 1.6891 -0.8763) (xy 1.6891 0.8763) (xy 0.9525 0.8763)) (layer B.Fab) (width 0)) - (fp_poly (pts (xy -1.6891 -0.8763) (xy -0.9525 -0.8763) (xy -0.9525 0.8763) (xy -1.6891 0.8763)) (layer B.Fab) (width 0)) - (fp_line (start 0.9525 0.8128) (end -0.9652 0.8128) (layer B.Fab) (width 0.1524)) - (fp_line (start 0.9525 -0.8128) (end -0.9652 -0.8128) (layer B.Fab) (width 0.1524)) - (pad 1 smd rect (at -1.71 0 180) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) + (fp_text value USB-CON-A-DUALC39472 (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_text user "USB FRONT" (at 3.0747 0.6438 180) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) + ) + (fp_line (start 2.4 -6.55) (end 2.4 6.55) (layer F.SilkS) (width 0.127)) + (fp_line (start -15.1 -6.55) (end -15.1 6.55) (layer F.SilkS) (width 0.127)) + (fp_line (start -15.1 6.55) (end 2.4 6.55) (layer F.SilkS) (width 0.127)) + (fp_line (start -15.1 -6.55) (end 2.4 -6.55) (layer F.SilkS) (width 0.127)) + (pad 12 thru_hole circle (at -5.33 6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) + (net 37 "Net-(J5-Pad12)") (solder_mask_margin 0.0508)) + (pad 11 thru_hole circle (at -5.33 -6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) + (net 38 "Net-(J5-Pad11)") (solder_mask_margin 0.0508)) + (pad 10 thru_hole circle (at 0.35 6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) + (net 39 "Net-(J5-Pad10)") (solder_mask_margin 0.0508)) + (pad 9 thru_hole circle (at 0.35 -6.57 90) (size 3.316 3.316) (drill 2.3) (layers *.Cu *.Mask) + (net 40 "Net-(J5-Pad9)") (solder_mask_margin 0.0508)) + (pad 8 thru_hole circle (at -2.62 3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 1.71 0 180) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) - (net 167 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) + (pad 7 thru_hole circle (at -2.62 1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 124 /USB_hub/USB_3_P) (solder_mask_margin 0.0508)) + (pad 6 thru_hole circle (at -2.62 -1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 125 /USB_hub/USB_3_N) (solder_mask_margin 0.0508)) + (pad 5 thru_hole circle (at -2.62 -3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 4 thru_hole circle (at 0 3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 3 thru_hole circle (at 0 1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 126 /USB_hub/USB_4_P) (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at 0 -1 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 127 /USB_hub/USB_4_N) (solder_mask_margin 0.0508)) + (pad 1 thru_hole circle (at 0 -3.5 90) (size 1.408 1.408) (drill 0.9) (layers *.Cu *.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D5D) - (at 127.5119 195.721 180) + (module LibreRouter_MegaBoard:1X04 (layer Top) (tedit 0) (tstamp 5E695470) + (at 88.15324 160.655 180) + (descr "PIN HEADER") + (path /5DB76F0E) + (fp_text reference UART1 (at 5.19684 1.9558) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + ) + (fp_text value Conn_01x04 (at -5.08 3.175) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_poly (pts (xy 3.556 0.254) (xy 4.064 0.254) (xy 4.064 -0.254) (xy 3.556 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -4.064 0.254) (xy -3.556 0.254) (xy -3.556 -0.254) (xy -4.064 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) + (fp_line (start 4.445 1.27) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 0.635) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -1.27) (end 2.54 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 0.635) (end 4.445 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 5.08 -0.635) (end 5.08 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 4.445 -1.27) (end 5.08 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -1.27) (end 4.445 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 1.27) (end -4.445 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.08 0.635) (end -4.445 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 -1.27) (end -5.08 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -5.08 -0.635) (end -5.08 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 1.27) (end -2.54 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 1.27) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 0.635) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 -0.635) (end 0 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -1.27) (end 0 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -1.27) (end -0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 -0.635) (end -1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 0.635) (end -3.175 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 -0.635) (end -2.54 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 -1.27) (end -2.54 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -4.445 -1.27) (end -3.175 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 1.27) (end 0 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 1.27) (end 0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 0.635) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 -0.635) (end 2.54 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -1.27) (end 2.54 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -1.27) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 -0.635) (end 0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (pad 4 thru_hole oval (at 3.81 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 3 thru_hole oval (at 1.27 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 104 /UART_SOUT) (solder_mask_margin 0.0508)) + (pad 2 thru_hole oval (at -1.27 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 177 "Net-(R64-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 thru_hole oval (at -3.81 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:1X02 (layer Top) (tedit 0) (tstamp 5E694DB6) + (at 98.2511 126.2774 270) + (descr "PIN HEADER") + (path /5DE0918B) + (fp_text reference JP8 (at -0.7252 -2.3075 90) (layer F.SilkS) + (effects (font (size 1.28016 1.28016) (thickness 0.128016)) (justify right top)) + ) + (fp_text value Conn_01x02 (at -2.54 3.175 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) + (fp_line (start 0.635 1.27) (end 0 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 1.27) (end 0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 0.635) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 2.54 -0.635) (end 2.54 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -1.27) (end 2.54 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -1.27) (end 1.905 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 -0.635) (end 0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 1.27) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 0.635) (end -1.905 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -1.27) (end -2.54 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.54 -0.635) (end -2.54 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 0.635) (end -0.635 1.27) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0 -0.635) (end 0 0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -1.27) (end 0 -0.635) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -1.27) (end -0.635 -1.27) (layer F.SilkS) (width 0.1524)) + (pad 2 thru_hole oval (at 1.27 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 128 /watchdog/RST_J-) (solder_mask_margin 0.0508)) + (pad 1 thru_hole oval (at -1.27 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 97 /RST_B) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:2X03 (layer Top) (tedit 0) (tstamp 5D6697C8) + (at 84.2811 126.3536 90) + (descr "PIN HEADER") + (path /5DD24EF7) + (fp_text reference WDT_CON1 (at 5.5512 4.0347) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.127)) (justify right top)) + ) + (fp_text value Conn_02x03 (at -3.81 4.445 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_poly (pts (xy 2.286 1.524) (xy 2.794 1.524) (xy 2.794 1.016) (xy 2.286 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 2.286 -1.016) (xy 2.794 -1.016) (xy 2.794 -1.524) (xy 2.286 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.254 1.524) (xy 0.254 1.524) (xy 0.254 1.016) (xy -0.254 1.016)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.254 -1.016) (xy 0.254 -1.016) (xy 0.254 -1.524) (xy -0.254 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 -1.016) (xy -2.286 -1.016) (xy -2.286 -1.524) (xy -2.794 -1.524)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -2.794 1.524) (xy -2.286 1.524) (xy -2.286 1.016) (xy -2.794 1.016)) (layer F.Fab) (width 0)) + (fp_line (start 1.905 2.54) (end 3.175 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.81 -1.905) (end 3.81 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 -2.54) (end 3.81 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.905 -2.54) (end 3.175 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -1.905) (end 1.905 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 3.175 2.54) (end 3.81 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 1.905) (end 1.905 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 2.54) (end -1.905 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 2.54) (end 0.635 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1.27 -1.905) (end 1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -1.905) (end -1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 -2.54) (end 1.27 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.635 -2.54) (end 0.635 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 -1.905) (end -0.635 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 -2.54) (end -1.27 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.175 -2.54) (end -1.905 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 -1.905) (end -3.175 -2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 1.905) (end -3.81 -1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start 0.635 2.54) (end 1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.27 1.905) (end -0.635 2.54) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.905 2.54) (end -1.27 1.905) (layer F.SilkS) (width 0.1524)) + (fp_line (start -3.81 1.905) (end -3.175 2.54) (layer F.SilkS) (width 0.1524)) + (pad 6 thru_hole circle (at 2.54 -1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 5 thru_hole circle (at 2.54 1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 98 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) + (pad 4 thru_hole circle (at 0 -1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 212 /WL_MOSI) (solder_mask_margin 0.0508)) + (pad 3 thru_hole circle (at 0 1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 213 /WL_SLK) (solder_mask_margin 0.0508)) + (pad 2 thru_hole circle (at -2.54 -1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 1 thru_hole circle (at -2.54 1.27 90) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 176 /WL_MISO) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:SOT-23 (layer Bottom) (tedit 0) (tstamp 5E1718B8) + (at 243.68252 203.9493 90) + (descr "Small Outline Transistor") + (path /5D032DC8/5DD00C18) + (fp_text reference Q11 (at -1.69418 -2.78892) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.077216)) (justify right bottom mirror)) + ) + (fp_text value BSS138-7-F (at -1.397 1.778 270) (layer B.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom mirror)) + ) + (fp_poly (pts (xy -0.1778 -0.9398) (xy 0.2032 -0.9398) (xy 0.2032 -0.4318) (xy -0.1778 -0.4318)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy -1.143 0.4318) (xy -0.762 0.4318) (xy -0.762 0.9398) (xy -1.143 0.9398)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy 0.7874 0.4318) (xy 1.1684 0.4318) (xy 1.1684 0.9398) (xy 0.7874 0.9398)) (layer B.Fab) (width 0)) + (fp_line (start -1.4224 -0.381) (end -1.4224 0.381) (layer B.SilkS) (width 0.1524)) + (fp_line (start 1.4732 -0.381) (end -1.4224 -0.381) (layer B.SilkS) (width 0.1524)) + (fp_line (start 1.4732 0.381) (end 1.4732 -0.381) (layer B.SilkS) (width 0.1524)) + (fp_line (start -1.4224 0.381) (end 1.4732 0.381) (layer B.SilkS) (width 0.1524)) + (pad 1 smd rect (at 0 -1.016 90) (size 0.7874 0.889) (layers Bottom B.Paste B.Mask) + (net 261 /ethernet_frontend/POE_INJECT_CTRL) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -0.95 1.016 90) (size 0.7874 0.889) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at 0.95 1.016 90) (size 0.7874 0.889) (layers Bottom B.Paste B.Mask) + (net 68 "Net-(Q11-Pad3)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:SI4435 (layer Top) (tedit 0) (tstamp 5D6699AC) + (at 243.3701 179.67198 270) + (path /5D032DC8/5DD0095A) + (fp_text reference Q9 (at -2.83718 -4.5085 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value Si4435DDY-T1 (at -2.6 4.3 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_circle (center -3.9878 -1.9558) (end -3.6576 -1.9558) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -1.2 2.5) (xy 3.65 2.5) (xy 3.65 -2.5) (xy -1.2 -2.5)) (layer Dwgs.User) (width 0)) + (fp_line (start -3.4 2.7) (end -3.4 -2.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.6 2.7) (end -3.4 2.7) (layer F.SilkS) (width 0.127)) + (fp_line (start 3.6 -2.7) (end 3.6 2.7) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.4 -2.7) (end 3.6 -2.7) (layer F.SilkS) (width 0.127)) + (pad P$8 smd rect (at 2.52725 -1.9305 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 257 /POE_A) (solder_mask_margin 0.0508)) + (pad P$7 smd rect (at 2.52725 -0.635 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 257 /POE_A) (solder_mask_margin 0.0508)) + (pad P$6 smd rect (at 2.52725 0.635 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 257 /POE_A) (solder_mask_margin 0.0508)) + (pad P$5 smd rect (at 2.52725 1.905 270) (size 1.1935 0.559) (layers Top F.Paste F.Mask) + (net 257 /POE_A) (solder_mask_margin 0.0508)) + (pad P$4 smd rect (at -2.66 1.905 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) + (net 69 "Net-(Q9-PadP$4)") (solder_mask_margin 0.0508)) + (pad P$3 smd rect (at -2.66 0.635 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) + (net 260 "Net-(D28-Pad1)") (solder_mask_margin 0.0508)) + (pad P$2 smd rect (at -2.66 -0.635 270) (size 1.98 0.69) (layers Top F.Paste F.Mask) + (net 260 "Net-(D28-Pad1)") (solder_mask_margin 0.0508)) + (pad P$1 smd rect (at -2.66 -1.905 270) (size 1.98 0.568) (layers Top F.Paste F.Mask) + (net 260 "Net-(D28-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D6699BD) + (at 232.5783 188.1251 90) (descr "RESISTOR

\nchip") - (path /5D032896/5D4B35F0) - (fp_text reference R81 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (path /5D032DC8/5D4F4E73) + (fp_text reference R1 (at -1.4732 0.2635 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value "2.7k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 154 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 88 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D6699CD) + (at 87.2021 191.022 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D571) + (fp_text reference R10 (at 0.9766 1.3374 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5822,21 +6182,21 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 36 "Net-(R81-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 161 "Net-(R10-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D6D) - (at 122.0763 194.6796 90) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF929C9) + (at 107.36834 68.707 180) (descr "RESISTOR

\nchip") - (path /5D032896/5D46F542) - (fp_text reference R82 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D032C97/5D1F3F5D) + (fp_text reference R100 (at 5.13334 -0.381) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 0 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5849,21 +6209,21 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 35 "Net-(R82-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 182 /PCIe_0_RX_P) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 247 /pcie0/PCIe_RX_bis_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D7D) - (at 123.1685 194.6796 90) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D6699ED) + (at 107.36834 70.87108 180) (descr "RESISTOR

\nchip") - (path /5D032896/5D46F4F0) - (fp_text reference R83 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D032C97/5D1F7584) + (fp_text reference R101 (at 5.13334 -0.31242) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 0 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5876,21 +6236,21 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 33 "Net-(R83-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 183 /PCIe_0_TX_N) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 246 /pcie0/PCIe_TX_bis_N) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D8D) - (at 119.0029 197.88 90) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D6699FD) + (at 107.36698 71.9061 180) (descr "RESISTOR

\nchip") - (path /5D032896/5D475208) - (fp_text reference R84 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (path /5D032C97/5D1F758C) + (fp_text reference R102 (at 5.13198 -0.3569) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 0 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5903,21 +6263,21 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 34 "Net-(R84-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 184 /PCIe_0_TX_P) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 245 /pcie0/PCIe_TX_bis_P) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D9D) - (at 117.9869 197.88 270) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A0D) + (at 124.45882 68.87848 90) (descr "RESISTOR

\nchip") - (path /5D032896/5D4752D0) - (fp_text reference R85 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (path /5D032C97/5D1A051B) + (fp_text reference R106 (at -1.47952 -0.88782 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 47k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 1.5k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5930,21 +6290,21 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 34 "Net-(R84-Pad2)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 50 "Net-(PCIE0-Pad22)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669DAD) - (at 119.3839 203.6204 90) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A1D) + (at 124.0282 66.58356 180) (descr "RESISTOR

\nchip") - (path /5D032896/5D46F475) - (fp_text reference R86 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D032C97/5D1A04F3) + (fp_text reference R107 (at -1.5748 0.73406) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text value 0 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5957,21 +6317,21 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 28 "Net-(R86-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 132 "Net-(PCIE0-Pad20)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 292 /GPIO12-PCIe0_nDISABLE) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669DBD) - (at 82.7317 113.4504 90) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A2D) + (at 125.66904 68.8848 90) (descr "RESISTOR

\nchip") - (path /5D0328DE/5D42E225/5D42D571) - (fp_text reference R9 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (path /5D032C97/5D1A0459) + (fp_text reference R108 (at -1.2827 0.50546 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text value 0 (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -5985,47 +6345,74 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 173 "Net-(R11-Pad1)") (solder_mask_margin 0.0508)) + (net 50 "Net-(PCIE0-Pad22)") (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (net 185 /PCIe_0_RST) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DF90A47) - (at 108.95838 51.98364 180) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A3D) + (at 175.97882 53.95722 90) (descr "RESISTOR

\nchip") - (path /5D032C97/5D1A5891) - (fp_text reference R96 (at -1.905 0.635 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (path /5D3C88FD) + (fp_text reference R109 (at -4.32308 0.46228 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value TBD (at 1.29794 0.3556 180) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom mirror)) + (fp_text value 0 (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 116 /WD_PCIe0_WAKE) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 149 "Net-(PCIE0-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 169 /5G_WLAN_LED_0) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 129 /pcie0/LED_WLAN) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF90ACB) - (at 108.37164 60.071 270) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669A4D) + (at 82.7317 111.2406 90) (descr "RESISTOR

\nchip") - (path /5D032C97/5D1AF5AD) - (fp_text reference R98 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (path /5D0328DE/5D42E225/5D42D5CB) + (fp_text reference R11 (at -1.905 -0.635 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) - (fp_text value TBD (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 160 "Net-(R11-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669ABD) + (at 87.2021 193.181 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D5CB) + (fp_text reference R12 (at 1.4338 1.3374 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -6039,20 +6426,20 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 146 /PCIe_0_CLK_P) (solder_mask_margin 0.0508)) + (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 147 /PCIe_0_CLK_N) (solder_mask_margin 0.0508)) + (net 161 "Net-(R10-Pad2)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF92999) - (at 107.36834 67.65922 180) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669ADD) + (at 226.22764 59.51728) (descr "RESISTOR

\nchip") - (path /5D032C97/5D1F3D95) - (fp_text reference R99 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (path /5D032C56/5D44A5F7) + (fp_text reference R124 (at -4.07924 0.37592) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value 0 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text value 330 (at -3.429 0.44704) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -6065,904 +6452,1446 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 195 /PCIe_0_RX_N) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 272 /pcie0/PCIe_RX_bis_N) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 192 /LEDN1000_4) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 193 "Net-(P4_1000-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SWITCH_6X6X5 (layer Top) (tedit 0) (tstamp 5D669DFD) - (at 131.0437 226.0232) - (descr "PUSH SWITCH

\nITT-Cannon-Cannon") - (path /5D2895FD) - (fp_text reference S2 (at -5.27 -4.27) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669AED) + (at 92.4599 193.943 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D2DE) + (fp_text reference R13 (at 3.35658 -0.45584 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value push_switch_SH (at -4.905 5.54) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 2 3.5) (end 2 2.55) (layer F.SilkS) (width 0.127)) - (fp_line (start -2 3.5) (end 2 3.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -2 2.55) (end -2 3.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -4.8999 -4.1001) (end -4.8999 2.55) (layer F.SilkS) (width 0.2032)) - (fp_line (start 4.8999 -4.1001) (end -4.8999 -4.1001) (layer F.SilkS) (width 0.2032)) - (fp_line (start 4.8999 2.55) (end 4.8999 -4.1001) (layer F.SilkS) (width 0.2032)) - (fp_line (start 2 2.55) (end 4.8999 2.55) (layer F.SilkS) (width 0.2032)) - (fp_line (start -2 2.55) (end 2 2.55) (layer F.SilkS) (width 0.2032)) - (fp_line (start -4.8999 2.55) (end -2 2.55) (layer F.SilkS) (width 0.2032)) - (pad 3 thru_hole circle (at 3.5 -2.5 90) (size 1.905 1.905) (drill 1.2954) (layers *.Cu *.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 2 thru_hole circle (at 2.25 0 90) (size 1.524 1.524) (drill 0.9906) (layers *.Cu *.Mask) - (net 98 /GPIO17) (solder_mask_margin 0.0508)) - (pad 1 thru_hole circle (at -2.25 0 90) (size 1.524 1.524) (drill 0.9906) (layers *.Cu *.Mask) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 thru_hole circle (at -3.5 -2.5 90) (size 1.905 1.905) (drill 1.2954) (layers *.Cu *.Mask) - (net 208 "Net-(S2-Pad4)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 16 "Net-(R13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:QT48103 (layer Top) (tedit 0) (tstamp 5D669E0D) - (at 220.9585 180.3286 270) - (path /5D032DC8/5D45306C) - (fp_text reference T1 (at -6.1 -14.1 270) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669AFD) + (at 90.1485 193.943 90) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FE12B/5D42D605) + (fp_text reference R16 (at -3.38706 0.34916 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text value QT48A03 (at -6.2 15.3 270) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) + (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_circle (center -5.3 -11.6) (end -5 -11.6) (layer F.SilkS) (width 0.4064)) - (fp_line (start -6.1 13.85) (end -6.1 -13.85) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.1 13.85) (end -6.1 13.85) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.1 -13.85) (end 6.1 13.85) (layer F.SilkS) (width 0.127)) - (fp_line (start -6.1 -13.85) (end 6.1 -13.85) (layer F.SilkS) (width 0.127)) - (pad 48 smd rect (at 7.27 -11.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 167 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) - (pad 47 smd rect (at 7.27 -10.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 119 /ethernet_frontend/AM_TRX3_N) (solder_mask_margin 0.0508)) - (pad 46 smd rect (at 7.27 -9.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 120 /ethernet_frontend/AM_TRX3_P) (solder_mask_margin 0.0508)) - (pad 45 smd rect (at 7.27 -8.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 168 /ethernet_frontend/MCT2) (solder_mask_margin 0.0508)) - (pad 44 smd rect (at 7.27 -7.57 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 123 /ethernet_frontend/AM_TRX2_N) (solder_mask_margin 0.0508)) - (pad 43 smd rect (at 7.27 -6.55 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 122 /ethernet_frontend/AM_TRX2_P) (solder_mask_margin 0.0508)) - (pad 42 smd rect (at 7.27 -5.53 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 170 /ethernet_frontend/MCT3) (solder_mask_margin 0.0508)) - (pad 41 smd rect (at 7.27 -4.51 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 121 /ethernet_frontend/AM_TRX1_N) (solder_mask_margin 0.0508)) - (pad 40 smd rect (at 7.27 -3.49 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 124 /ethernet_frontend/AM_TRX1_P) (solder_mask_margin 0.0508)) - (pad 39 smd rect (at 7.27 -2.47 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 185 /ethernet_frontend/MCT4) (solder_mask_margin 0.0508)) - (pad 38 smd rect (at 7.27 -1.45 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 126 /ethernet_frontend/AM_TRX0_N) (solder_mask_margin 0.0508)) - (pad 37 smd rect (at 7.27 -0.43 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 125 /ethernet_frontend/AM_TRX0_P) (solder_mask_margin 0.0508)) - (pad 36 smd rect (at 7.27 0.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 167 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) - (pad 35 smd rect (at 7.27 1.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 127 /ethernet_frontend/BM_TRX3_N) (solder_mask_margin 0.0508)) - (pad 34 smd rect (at 7.27 2.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 128 /ethernet_frontend/BM_TRX3_P) (solder_mask_margin 0.0508)) - (pad 33 smd rect (at 7.27 3.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 169 /ethernet_frontend/MCT6) (solder_mask_margin 0.0508)) - (pad 32 smd rect (at 7.27 4.67 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 131 /ethernet_frontend/BM_TRX2_N) (solder_mask_margin 0.0508)) - (pad 31 smd rect (at 7.27 5.69 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 130 /ethernet_frontend/BM_TRX2_P) (solder_mask_margin 0.0508)) - (pad 30 smd rect (at 7.27 6.71 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 186 /ethernet_frontend/MCT7) (solder_mask_margin 0.0508)) - (pad 29 smd rect (at 7.27 7.73 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 129 /ethernet_frontend/BM_TRX1_N) (solder_mask_margin 0.0508)) - (pad 28 smd rect (at 7.27 8.75 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 132 /ethernet_frontend/BM_TRX1_P) (solder_mask_margin 0.0508)) - (pad 27 smd rect (at 7.27 9.77 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 187 /ethernet_frontend/MCT8) (solder_mask_margin 0.0508)) - (pad 26 smd rect (at 7.27 10.77 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 134 /ethernet_frontend/BM_TRX0_N) (solder_mask_margin 0.0508)) - (pad 25 smd rect (at 7.27 11.81 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 133 /ethernet_frontend/BM_TRX0_P) (solder_mask_margin 0.0508)) - (pad 24 smd rect (at -7.27 11.81 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 211 /S17_P3_TRX_0_P) (solder_mask_margin 0.0508)) - (pad 23 smd rect (at -7.27 10.79 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 212 /S17_P3_TRX_0_N) (solder_mask_margin 0.0508)) - (pad 22 smd rect (at -7.27 9.77 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 101 "Net-(C137-Pad1)") (solder_mask_margin 0.0508)) - (pad 21 smd rect (at -7.27 8.75 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 213 /S17_P3_TRX_1_P) (solder_mask_margin 0.0508)) - (pad 20 smd rect (at -7.27 7.73 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 214 /S17_P3_TRX_1_N) (solder_mask_margin 0.0508)) - (pad 19 smd rect (at -7.27 6.71 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 87 "Net-(C37-Pad1)") (solder_mask_margin 0.0508)) - (pad 18 smd rect (at -7.27 5.69 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 215 /S17_P3_TRX_2_P) (solder_mask_margin 0.0508)) - (pad 17 smd rect (at -7.27 4.67 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 216 /S17_P3_TRX_2_N) (solder_mask_margin 0.0508)) - (pad 16 smd rect (at -7.27 3.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 86 "Net-(C35-Pad1)") (solder_mask_margin 0.0508)) - (pad 15 smd rect (at -7.27 2.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 217 /S17_P3_TRX_3_P) (solder_mask_margin 0.0508)) - (pad 14 smd rect (at -7.27 1.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 218 /S17_P3_TRX_3_N) (solder_mask_margin 0.0508)) - (pad 13 smd rect (at -7.27 0.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 85 "Net-(C34-Pad1)") (solder_mask_margin 0.0508)) - (pad 12 smd rect (at -7.27 -0.43 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 219 /S17_P4_TRX_0_P) (solder_mask_margin 0.0508)) - (pad 11 smd rect (at -7.27 -1.45 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 220 /S17_P4_TRX_0_N) (solder_mask_margin 0.0508)) - (pad 10 smd rect (at -7.27 -2.47 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 84 "Net-(C33-Pad1)") (solder_mask_margin 0.0508)) - (pad 9 smd rect (at -7.27 -3.49 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 221 /S17_P4_TRX_1_P) (solder_mask_margin 0.0508)) - (pad 8 smd rect (at -7.27 -4.51 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 222 /S17_P4_TRX_1_N) (solder_mask_margin 0.0508)) - (pad 7 smd rect (at -7.27 -5.53 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 79 "Net-(C11-Pad1)") (solder_mask_margin 0.0508)) - (pad 6 smd rect (at -7.27 -6.55 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 223 /S17_P4_TRX_2_P) (solder_mask_margin 0.0508)) - (pad 5 smd rect (at -7.27 -7.57 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 224 /S17_P4_TRX_2_N) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at -7.27 -8.59 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 78 "Net-(C10-Pad1)") (solder_mask_margin 0.0508)) - (pad 3 smd rect (at -7.27 -9.61 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 225 /S17_P4_TRX_3_P) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -7.27 -10.63 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 226 /S17_P4_TRX_3_N) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -7.27 -11.65 270) (size 2.34 0.64) (layers Top F.Paste F.Mask) - (net 76 "Net-(C5-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 15 "Net-(C45-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:USB_HUB_FE1.1S (layer Top) (tedit 0) (tstamp 5D669E45) - (at 124.4639 201.3344 90) - (path /5D032896/5D46F2DE) - (fp_text reference U12 (at -6 3.5) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669B1D) + (at 91.1899 182.894 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FE353) + (fp_text reference R18 (at -3.4811 0.3214 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text value USB_HUB_FE1.1S (at 7.5 3) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_arc (start -5 0) (end -5 -0.5) (angle 180) (layer F.SilkS) (width 0.127)) - (fp_circle (center -4.6 1.6) (end -4.4 1.6) (layer F.SilkS) (width 0.127)) - (fp_line (start 5 2) (end 5 -2) (layer F.SilkS) (width 0.127)) - (fp_line (start -5 2) (end 5 2) (layer F.SilkS) (width 0.127)) - (fp_line (start -5 0.5) (end -5 2) (layer F.SilkS) (width 0.127)) - (fp_line (start -5 -0.5) (end -5 0.5) (layer F.SilkS) (width 0.127)) - (fp_line (start -5 -2) (end -5 -0.5) (layer F.SilkS) (width 0.127)) - (fp_line (start 5 -2) (end -5 -2) (layer F.SilkS) (width 0.127)) - (pad 28 smd rect (at -4.16 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 92 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) - (pad 27 smd rect (at -3.52 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 27 "Net-(U12-Pad27)") (solder_mask_margin 0.0508)) - (pad 26 smd rect (at -2.88 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 28 "Net-(R86-Pad1)") (solder_mask_margin 0.0508)) - (pad 25 smd rect (at -2.24 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 29 "Net-(U12-Pad25)") (solder_mask_margin 0.0508)) - (pad 24 smd rect (at -1.6 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 30 "Net-(U12-Pad24)") (solder_mask_margin 0.0508)) - (pad 23 smd rect (at -0.96 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 31 "Net-(U12-Pad23)") (solder_mask_margin 0.0508)) - (pad 22 smd rect (at -0.32 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 32 "Net-(U12-Pad22)") (solder_mask_margin 0.0508)) - (pad 21 smd rect (at 0.32 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) - (pad 20 smd rect (at 0.96 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 19 smd rect (at 1.6 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 33 "Net-(R83-Pad1)") (solder_mask_margin 0.0508)) - (pad 18 smd rect (at 2.24 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 34 "Net-(R84-Pad2)") (solder_mask_margin 0.0508)) - (pad 17 smd rect (at 2.88 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 35 "Net-(R82-Pad1)") (solder_mask_margin 0.0508)) - (pad 16 smd rect (at 3.52 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 261 /Core9558/USB1_DP) (solder_mask_margin 0.0508)) - (pad 15 smd rect (at 4.16 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 260 /Core9558/USB1_DM) (solder_mask_margin 0.0508)) - (pad 14 smd rect (at 4.16 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 36 "Net-(R81-Pad2)") (solder_mask_margin 0.0508)) - (pad 13 smd rect (at 3.52 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 91 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) - (pad 12 smd rect (at 2.88 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 92 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) - (pad 11 smd rect (at 2.24 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 263 /USB_hub/USB_1_P) (solder_mask_margin 0.0508)) - (pad 10 smd rect (at 1.6 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 264 /USB_hub/USB_1_N) (solder_mask_margin 0.0508)) - (pad 9 smd rect (at 0.96 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 265 /USB_hub/USB_2_P) (solder_mask_margin 0.0508)) - (pad 8 smd rect (at 0.32 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 266 /USB_hub/USB_2_N) (solder_mask_margin 0.0508)) - (pad 7 smd rect (at -0.32 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 136 /USB_hub/USB_3_P) (solder_mask_margin 0.0508)) - (pad 6 smd rect (at -0.96 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 137 /USB_hub/USB_3_N) (solder_mask_margin 0.0508)) - (pad 5 smd rect (at -1.6 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 138 /USB_hub/USB_4_P) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at -2.24 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 139 /USB_hub/USB_4_N) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at -2.88 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 94 "Net-(C63-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -3.52 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 93 "Net-(C61-Pad1)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -4.16 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 95 /POWER_EN_5V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D669E6C) - (at 93.7299 186.9326 270) - (path /5D0328DE/5D4FE12B/5D42D1B4) - (fp_text reference U4 (at -1.27 -1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669B2D) + (at 220.3383 188.1251 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D4DF89D) + (fp_text reference R2 (at -1.3843 0.4004 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_arc (start 1.6256 -0.9144) (end 2.3368 -0.9398) (angle 180) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 -0.9144) (end 2.3876 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start -0.0762 -0.9144) (end 0.9144 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start -0.0762 4.5466) (end -0.0762 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 4.5466) (end -0.0762 4.5466) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 -0.9144) (end 3.4036 4.5466) (layer F.SilkS) (width 0.3048)) - (pad 9 smd rect (at 1.651 1.9558 270) (size 2.9972 3.5052) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 97 /POWER_EN_5V) (solder_mask_margin 0.0508)) - (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 12 "Net-(C30-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 13 "Net-(C30-Pad1)") (solder_mask_margin 0.0508)) - (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 174 "Net-(R10-Pad2)") (solder_mask_margin 0.0508)) - (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 14 "Net-(C45-Pad2)") (solder_mask_margin 0.0508)) - (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 16 "Net-(R13-Pad1)") (solder_mask_margin 0.0508)) - (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 154 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 88 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D669E7E) - (at 88.4975 145.7338 270) - (path /5D0328DE/5D4FEB2F/5D42D1B4) - (fp_text reference U5 (at -1.27 -1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669B4D) + (at 117.2249 174.46882) + (descr "RESISTOR

\nchip") + (path /5E2BEE06) + (fp_text reference R21 (at -3.3821 -0.45342) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 330 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) - (fp_arc (start 1.6256 -0.9144) (end 2.3368 -0.9398) (angle 180) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 -0.9144) (end 2.3876 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start -0.0762 -0.9144) (end 0.9144 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start -0.0762 4.5466) (end -0.0762 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 4.5466) (end -0.0762 4.5466) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 -0.9144) (end 3.4036 4.5466) (layer F.SilkS) (width 0.3048)) - (pad 9 smd rect (at 1.651 1.9558 270) (size 2.9972 3.5052) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 97 /POWER_EN_5V) (solder_mask_margin 0.0508)) - (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 17 "Net-(C62-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 18 "Net-(C62-Pad1)") (solder_mask_margin 0.0508)) - (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 189 "Net-(R45-Pad2)") (solder_mask_margin 0.0508)) - (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 19 "Net-(C66-Pad2)") (solder_mask_margin 0.0508)) - (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 21 "Net-(R52-Pad1)") (solder_mask_margin 0.0508)) - (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 96 /GPIO17) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D669E90) - (at 88.2689 106.5924 270) - (path /5D0328DE/5D42E225/5D42D1B4) - (fp_text reference U6 (at -1.27 -1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:R1206 (layer Bottom) (tedit 0) (tstamp 5D669B5D) + (at 236.78388 192.74028 180) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D662C5E) + (fp_text reference R22 (at 5.30352 0.52832) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 0 (at -1.397 -2.413) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_arc (start 1.6256 -0.9144) (end 2.3368 -0.9398) (angle 180) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 -0.9144) (end 2.3876 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start -0.0762 -0.9144) (end 0.9144 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start -0.0762 4.5466) (end -0.0762 -0.9144) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 4.5466) (end -0.0762 4.5466) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.4036 -0.9144) (end 3.4036 4.5466) (layer F.SilkS) (width 0.3048)) - (pad 9 smd rect (at 1.651 1.9558 270) (size 2.9972 3.5052) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (fp_line (start -2.667 -1.016) (end -2.667 1.016) (layer B.SilkS) (width 0.127)) + (fp_line (start 2.667 -1.016) (end -2.667 -1.016) (layer B.SilkS) (width 0.127)) + (fp_line (start 2.667 1.016) (end 2.667 -1.016) (layer B.SilkS) (width 0.127)) + (fp_line (start -2.667 1.016) (end 2.667 1.016) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.3 -0.7) (xy 0.3 -0.7) (xy 0.3 0.7) (xy -0.3 0.7)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy 0.9525 -0.8763) (xy 1.6891 -0.8763) (xy 1.6891 0.8763) (xy 0.9525 0.8763)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy -1.6891 -0.8763) (xy -0.9525 -0.8763) (xy -0.9525 0.8763) (xy -1.6891 0.8763)) (layer B.Fab) (width 0)) + (fp_line (start 0.9525 0.8128) (end -0.9652 0.8128) (layer B.Fab) (width 0.1524)) + (fp_line (start 0.9525 -0.8128) (end -0.9652 -0.8128) (layer B.Fab) (width 0.1524)) + (pad 1 smd rect (at -1.71 0 180) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 96 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) - (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 2 "Net-(C12-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 3 "Net-(C12-Pad1)") (solder_mask_margin 0.0508)) - (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 173 "Net-(R11-Pad1)") (solder_mask_margin 0.0508)) - (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 4 "Net-(C16-Pad2)") (solder_mask_margin 0.0508)) - (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 6 "Net-(R58-Pad1)") (solder_mask_margin 0.0508)) - (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 1.71 0 180) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) + (net 154 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:S8S1 (layer Top) (tedit 0) (tstamp 5D669EA2) - (at 88.3451 124.2708 270) - (path /5D032C38/5D14FFA1) - (fp_text reference WDT1 (at 0 -6.31 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669B7B) + (at 223.3983 188.1251 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D4DFC33) + (fp_text reference R29 (at -1.4859 0.4011 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value ATTINY13 (at -0.03 0.6 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_circle (center 0.63 -5.27) (end 0.936103 -5.27) (layer F.SilkS) (width 0.127)) - (fp_line (start 4 -1) (end -0.01 -1) (layer F.SilkS) (width 0.127)) - (fp_line (start 4 -5.98) (end 4 -1) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.01 -5.98) (end 4 -5.98) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.01 -1) (end -0.01 -5.98) (layer F.SilkS) (width 0.127)) - (pad 7 smd rect (at 4.46 -4.11 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 228 /WL_SLK) (solder_mask_margin 0.0508)) - (pad 8 smd rect (at 4.46 -5.47 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 5 smd rect (at 4.46 -1.48 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 227 /WL_MOSI) (solder_mask_margin 0.0508)) - (pad 6 smd rect (at 4.46 -2.84 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 190 /WL_MISO) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -0.54 -4.11 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 71 "Net-(WDT1-Pad2)") (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.54 -5.47 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 100 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at -0.54 -1.48 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at -0.54 -2.84 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) - (net 140 /watchdog/RST_J-) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 171 /ethernet_frontend/MCT4) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 88 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:SMARTPRJ_CRYSTAL-3.2-2.5 (layer Top) (tedit 0) (tstamp 5D669EBB) - (at 130.6869 204.8396 270) - (path /5D032896/5D497A3C) - (fp_text reference X2 (at -1.65 -1.6) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5E1718E2) + (at 246.80164 202.5396 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D88FC3A) + (fp_text reference R3 (at -0.635 0.762 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_text value "YSX321SL 12MHz" (at -1.6 2.25 90) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + (fp_text value 4.7k (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) - (fp_line (start -1.6 -1.25) (end 1.6 -1.25) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.6 1.25) (end -1.6 -1.25) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.6 1.25) (end -1.6 1.25) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.6 -1.25) (end 1.6 1.25) (layer F.SilkS) (width 0.127)) - (pad 4 smd rect (at -1.15 -0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at 1.15 -0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) - (net 93 "Net-(C61-Pad1)") (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 1.15 0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1.15 0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) - (net 94 "Net-(C63-Pad1)") (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 296 /GPIO1-EJTAG_TDI) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 68 "Net-(Q11-Pad3)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:DRAGINO_CORE9558 (layer Top) (tedit 0) (tstamp 5D669EC6) - (at 157.3315 133.8466 270) - (path /5D032850/5D47B6E1) - (fp_text reference U1 (at -35.648 36.584 270) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669B9B) + (at 214.2183 188.1251 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D4DFC3A) + (fp_text reference R30 (at -1.3462 0.3736 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_text value CORE9558_V2 (at 0 0 270) (layer F.SilkS) hide - (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) + (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_arc (start 29.4438 20.2728) (end 29.4438 20.2093) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 43.2306 20.2728) (end 43.2306 20.3363) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 29.4438 20.2728) (end 43.2306 20.2728) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 29.4438 14.6458) (end 29.5073 14.6458) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 29.4438 20.2728) (end 29.4438 20.3363) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 29.4438 20.2728) (end 29.3803 20.2728) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 29.4438 20.2093) (end 29.4438 20.2728) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 29.4438 14.6458) (end 29.4438 20.2093) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 16.4082 14.6556) (end 16.4082 14.5921) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 29.4438 14.6458) (end 29.5073 14.6458) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 29.4438 14.6458) (end 29.4438 14.7093) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 16.4082 14.6556) (end 29.4438 14.6458) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 11.3282 14.6556) (end 11.3282 14.5921) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 16.4082 14.6556) (end 16.4082 14.7191) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 11.3282 14.6556) (end 16.4082 14.6556) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 11.3282 21.0056) (end 11.2647 21.0056) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 11.3282 14.6556) (end 11.3282 14.5921) (angle -90) (layer Edge.Cuts) (width 0.001)) - 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(fp_line (start 5.3592 21.0691) (end 5.3592 21.0056) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 5.3592 25.8316) (end 5.3592 21.0691) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start -0.2288 25.8316) (end -0.2288 25.7681) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 5.3592 25.8316) (end 5.4227 25.8316) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start 5.3592 25.8316) (end 5.3592 25.8951) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_line (start 5.2957 25.8316) (end 5.3592 25.8316) (layer Edge.Cuts) (width 0.001)) - (fp_line (start -0.2288 25.8316) (end 5.2957 25.8316) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start -0.2288 17.3226) (end -0.1653 17.3226) (angle -180) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start -0.2288 25.8316) (end -0.2288 25.8951) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_arc (start -0.2288 25.8316) (end -0.2923 25.8316) (angle -90) (layer Edge.Cuts) (width 0.001)) - (fp_line (start -0.2288 25.7681) (end -0.2288 25.8316) (layer Edge.Cuts) (width 0.001)) - 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\nchip") + (path /5D032DC8/5D4EA21B) + (fp_text reference R31 (at -1.4097 0.3729 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) + ) + (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 173 /ethernet_frontend/MCT8) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 88 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669BBB) + (at 239.5474 174.7774 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D87479D) + (fp_text reference R32 (at -1.1176 -0.635 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 68k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 69 "Net-(Q9-PadP$4)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 261 /ethernet_frontend/POE_INJECT_CTRL) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0603 (layer Top) (tedit 0) (tstamp 5E1656BC) + (at 240.5888 185.0136) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D8661A5) + (fp_text reference R33 (at 1.6637 -0.3556) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value "0 1/10W" (at -1.651 1.778) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_line (start 1.651 0.762) (end 0.889 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.651 -0.762) (end 1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.889 -0.762) (end 1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 0.762) (end -0.889 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.651 -0.762) (end -1.651 0.762) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.889 -0.762) (end -1.651 -0.762) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_poly (pts (xy -0.8382 0.4318) (xy -0.4318 0.4318) (xy -0.4318 -0.4318) (xy -0.8382 -0.4318)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.4318 0.4318) (xy 0.8382 0.4318) (xy 0.8382 -0.4318) (xy 0.4318 -0.4318)) (layer F.Fab) (width 0)) + (fp_line (start -1.6 0.729) (end -1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 0.729) (end -1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.6 -0.729) (end 1.6 0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.6 -0.729) (end 1.6 -0.729) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 0.432 -0.356) (end -0.432 -0.356) (layer F.Fab) (width 0.1524)) + (fp_line (start -0.432 0.356) (end 0.432 0.356) (layer F.Fab) (width 0.1524)) + (pad 2 smd rect (at 0.85 0) (size 1 1.1) (layers Top F.Paste F.Mask) + (net 257 /POE_A) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.85 0) (size 1 1.1) (layers Top F.Paste F.Mask) + (net 155 /ethernet_frontend/MCT2) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5E16FCF4) + (at 240.87328 184.99836 180) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D63CAC2) + (fp_text reference R4 (at -1.49352 0.28448) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) + ) + (fp_text value 75 (at -1.905 -1.397) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 155 /ethernet_frontend/MCT2) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 86 "Net-(C40-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669BEF) + (at 97.81032 121.67616) + (descr "RESISTOR

\nchip") + (path /5D032C38/5D150638) + (fp_text reference R43 (at 3.47218 0.30734) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 97 /RST_B) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5E17188B) + (at 246.80164 206.68996 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D88FD1C) + (fp_text reference R44 (at 1.0922 0.80772 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) + ) + (fp_text value 47k (at -1.905 -1.397 270) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 68 "Net-(Q11-Pad3)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 263 /ethernet_frontend/POE_INJECT_HARD_EN) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C0F) + (at 83.4937 151.0678 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D571) + (fp_text reference R45 (at -1.1824 0.7151 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 175 "Net-(R45-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 93 /5V0_2GPA) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E694FD9) + (at 83.4937 153.2522 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D5CB) + (fp_text reference R47 (at -1.157 0.6897 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 175 "Net-(R45-Pad2)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C3F) + (at 240.22558 200.18502 180) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D6301C2) + (fp_text reference R5 (at -2.64922 -0.00508) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value 75 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 156 /ethernet_frontend/MCT6) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 87 "Net-(C41-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C4F) + (at 91.3169 130.951 270) + (descr "RESISTOR

\nchip") + (path /5D171F88) + (fp_text reference R50 (at 1.0655 1.4009 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value 0 (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 295 /GPIO2-EJTAG_TDO) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 176 /WL_MISO) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C5F) + (at 86.9735 153.176 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D2DE) + (fp_text reference R52 (at 3.3642 -0.4787 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 21 "Net-(R52-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C6F) + (at 94.26956 121.63806 180) + (descr "RESISTOR

\nchip") + (path /5D032C38/5D15016D) + (fp_text reference R53 (at 3.40106 0.41656) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 98 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C7F) + (at 85.0177 153.176 90) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D4FEB2F/5D42D605) + (fp_text reference R54 (at -3.3134 0.3771 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 20 "Net-(C66-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C8F) + (at 241.935 174.3202) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D874841) + (fp_text reference R57 (at 1.0668 -0.3556) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value 100k (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 260 "Net-(D28-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 69 "Net-(Q9-PadP$4)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669C9F) + (at 86.7957 114.06 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D42E225/5D42D2DE) + (fp_text reference R58 (at -1.905 -0.635 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 6 "Net-(R58-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CAF) + (at 84.7129 114.06 90) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D42E225/5D42D605) + (fp_text reference R59 (at -1.905 -0.635 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 5 "Net-(C16-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5D669CBF) + (at 226.4583 188.1251 90) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D4DFAC1) + (fp_text reference R6 (at -1.5113 0.3637 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) + ) + (fp_text value 75 (at -1.905 -1.397 90) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 157 /ethernet_frontend/MCT3) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 88 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CCF) + (at 85.2209 102.0966 270) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D42F0F7) + (fp_text reference R60 (at -1.905 -0.635 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 94 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CDF) + (at 97.11182 157.86354 90) + (descr "RESISTOR

\nchip") + (path /5DBFA05D) + (fp_text reference R63 (at 1.1684 0.70866 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 106 /UART_SIN) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669CEF) + (at 94.80296 158.32074 180) + (descr "RESISTOR

\nchip") + (path /5DBF9F7A) + (fp_text reference R64 (at 1.16078 1.36398) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 177 "Net-(R64-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 106 /UART_SIN) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E7201A7) + (at 118.8251 113.9076 180) + (descr "RESISTOR

\nchip") + (path /5D6C533C) + (fp_text reference R66 (at 1.2866 0.3061) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 296 /GPIO1-EJTAG_TDI) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D0F) + (at 119.25808 118.94566 270) + (descr "RESISTOR

\nchip") + (path /5D6C52AE) + (fp_text reference R67 (at 1.4771 0.3462 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 294 /GPIO3-EJTAG_TMS) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D1F) + (at 118.8251 111.6216 180) + (descr "RESISTOR

\nchip") + (path /5D6C5372) + (fp_text reference R68 (at 1.3374 0.3188) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 293 /GPIO0-EJTAG_TCK) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DE5C3F9) + (at 223.85528 57.96788) + (descr "RESISTOR

\nchip") + (path /5D032C56/5D449EF1) + (fp_text reference R77 (at 1.2954 0.3683) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 330 (at -3.41376 0.4826) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 178 /LEDN_4) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 179 "Net-(P4_100-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R1206 (layer Bottom) (tedit 0) (tstamp 5D669D3F) + (at 236.78388 190.42888 180) + (descr "RESISTOR

\nchip") + (path /5D032DC8/5D662C66) + (fp_text reference R8 (at -0.66802 2.07518) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) + ) + (fp_text value 0 (at -1.397 -2.413) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top mirror)) + ) + (fp_line (start -2.667 -1.016) (end -2.667 1.016) (layer B.SilkS) (width 0.127)) + (fp_line (start 2.667 -1.016) (end -2.667 -1.016) (layer B.SilkS) (width 0.127)) + (fp_line (start 2.667 1.016) (end 2.667 -1.016) (layer B.SilkS) (width 0.127)) + (fp_line (start -2.667 1.016) (end 2.667 1.016) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.3 -0.7) (xy 0.3 -0.7) (xy 0.3 0.7) (xy -0.3 0.7)) (layer B.Adhes) (width 0)) + (fp_poly (pts (xy 0.9525 -0.8763) (xy 1.6891 -0.8763) (xy 1.6891 0.8763) (xy 0.9525 0.8763)) (layer B.Fab) (width 0)) + (fp_poly (pts (xy -1.6891 -0.8763) (xy -0.9525 -0.8763) (xy -0.9525 0.8763) (xy -1.6891 0.8763)) (layer B.Fab) (width 0)) + (fp_line (start 0.9525 0.8128) (end -0.9652 0.8128) (layer B.Fab) (width 0.1524)) + (fp_line (start 0.9525 -0.8128) (end -0.9652 -0.8128) (layer B.Fab) (width 0.1524)) + (pad 1 smd rect (at -1.71 0 180) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 1.71 0 180) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) + (net 154 /ethernet_frontend/MCT1-5) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E69B685) + (at 122.9907 194.60086 90) + (descr "RESISTOR

\nchip") + (path /5D032896/5D46F542) + (fp_text reference R82 (at 1.47196 0.3009 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 35 "Net-(R82-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D7D) + (at 124.0829 194.60086 90) + (descr "RESISTOR

\nchip") + (path /5D032896/5D46F4F0) + (fp_text reference R83 (at 1.53546 0.4406 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text user 1 (at -37.084 35.306 270) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text user 105 (at -42.164 -34.036) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 33 "Net-(R83-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D8D) + (at 117.51818 196.1515) + (descr "RESISTOR

\nchip") + (path /5D032896/5D475208) + (fp_text reference R84 (at 1.07442 -1.5113) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text user 104 (at -38.354 -39.624 270) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_text value 100k (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text user 67 (at 49.276 -39.624 270) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 34 "Net-(R84-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669D9D) + (at 117.9869 197.88 270) + (descr "RESISTOR

\nchip") + (path /5D032896/5D4752D0) + (fp_text reference R85 (at -1.1697 -0.8089 270) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text user 66 (at 55.634 -34.044) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_text value 47k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_text user 39 (at 55.672 30.176) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 34 "Net-(R84-Pad2)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669DAD) + (at 119.01932 203.75626 90) + (descr "RESISTOR

\nchip") + (path /5D032896/5D46F475) + (fp_text reference R86 (at -1.13284 1.51638 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_text user 38 (at 49.53 35.314 270) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left bottom)) + (fp_text value 100k (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_poly (pts (xy -40.64 33.02) (xy -26.162 33.02) (xy -26.162 18.542) (xy -40.64 18.542)) (layer F.SilkS) (width 0)) - (fp_line (start -41.91 -39.37) (end -41.91 34.29) (layer F.SilkS) (width 0.001)) - (fp_line (start 54.61 -39.37) (end -41.91 -39.37) (layer F.SilkS) (width 0.001)) - (fp_line (start 54.61 34.29) (end 54.61 -39.37) (layer F.SilkS) (width 0.001)) - (fp_line (start -41.91 34.29) (end 54.61 34.29) (layer F.SilkS) (width 0.001)) - (fp_circle (center -41.656 35.306) (end -41.148 35.306) (layer F.SilkS) (width 0.127)) - (pad 132 smd rect (at -41.91 28.288 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 131 smd rect (at -41.91 26 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 198 /PCIe_0_TX_P) (solder_mask_margin 0.0508)) - (pad 130 smd rect (at -41.91 23.714 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 197 /PCIe_0_TX_N) (solder_mask_margin 0.0508)) - (pad 129 smd rect (at -41.91 21.428 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 128 smd rect (at -41.91 19.142 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 196 /PCIe_0_RX_P) (solder_mask_margin 0.0508)) - (pad 127 smd rect (at -41.91 16.856 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 195 /PCIe_0_RX_N) (solder_mask_margin 0.0508)) - (pad 126 smd rect (at -41.91 14.57 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 125 smd rect (at -41.91 12.284 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 146 /PCIe_0_CLK_P) (solder_mask_margin 0.0508)) - (pad 124 smd rect (at -41.91 9.998 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 147 /PCIe_0_CLK_N) (solder_mask_margin 0.0508)) - (pad 123 smd rect (at -41.91 7.712 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 199 /PCIe_0_RST) (solder_mask_margin 0.0508)) - (pad 122 smd rect (at -41.91 5.426 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 203 /PCIe_1_RST) (solder_mask_margin 0.0508)) - (pad 121 smd rect (at -41.91 3.14 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 154 /PCIe_1_CLK_N) (solder_mask_margin 0.0508)) - (pad 120 smd rect (at -41.91 0.854 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 156 /PCIe_1_CLK_P) (solder_mask_margin 0.0508)) - (pad 119 smd rect (at -41.91 -1.432 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 118 smd rect (at -41.91 -3.718 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 194 /PCIe_1_RX_N) (solder_mask_margin 0.0508)) - (pad 117 smd rect (at -41.91 -6.004 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 200 /PCIe_1_RX_P) (solder_mask_margin 0.0508)) - (pad 116 smd rect (at -41.91 -8.29 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 115 smd rect (at -41.91 -10.576 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 201 /PCIe_1_TX_N) (solder_mask_margin 0.0508)) - (pad 114 smd rect (at -41.91 -12.862 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 202 /PCIe_1_TX_P) (solder_mask_margin 0.0508)) - (pad 113 smd rect (at -41.91 -15.148 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 112 smd rect (at -41.91 -17.434 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 190 /WL_MISO) (solder_mask_margin 0.0508)) - (pad 111 smd rect (at -41.91 -19.72 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 227 /WL_MOSI) (solder_mask_margin 0.0508)) - (pad 110 smd rect (at -41.91 -22.006 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 228 /WL_SLK) (solder_mask_margin 0.0508)) - (pad 109 smd rect (at -41.91 -24.2914 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 229 /Core9558/SPI_CS_L) (solder_mask_margin 0.0508)) - (pad 108 smd rect (at -41.91 -26.5774 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 206 /LEDN1000_4) (solder_mask_margin 0.0508)) - (pad 107 smd rect (at -41.91 -28.8634 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 192 /LEDN_4) (solder_mask_margin 0.0508)) - (pad 106 smd rect (at -41.91 -31.1494 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 204 /LEDN1000_3) (solder_mask_margin 0.0508)) - (pad 105 smd rect (at -41.91 -33.4354 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 176 /LEDN_3) (solder_mask_margin 0.0508)) - (pad 104 smd rect (at -35.9405 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 230 "Net-(U1-Pad104)") (solder_mask_margin 0.0508)) - (pad 103 smd rect (at -33.6545 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 231 "Net-(U1-Pad103)") (solder_mask_margin 0.0508)) - (pad 102 smd rect (at -31.3685 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 232 "Net-(U1-Pad102)") (solder_mask_margin 0.0508)) - (pad 101 smd rect (at -29.0825 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 233 "Net-(U1-Pad101)") (solder_mask_margin 0.0508)) - (pad 100 smd rect (at -26.7965 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 234 "Net-(U1-Pad100)") (solder_mask_margin 0.0508)) - (pad 99 smd rect (at -24.5105 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 235 "Net-(U1-Pad99)") (solder_mask_margin 0.0508)) - (pad 98 smd rect (at -22.2245 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 97 smd rect (at -19.9385 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 96 smd rect (at -17.6525 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) - (pad 95 smd rect (at -15.365 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 94 smd rect (at -13.0805 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 93 smd rect (at -10.7945 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 92 smd rect (at -8.5085 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 226 /S17_P4_TRX_3_N) (solder_mask_margin 0.0508)) - (pad 91 smd rect (at -6.2225 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 225 /S17_P4_TRX_3_P) (solder_mask_margin 0.0508)) - (pad 90 smd rect (at -3.9365 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 224 /S17_P4_TRX_2_N) (solder_mask_margin 0.0508)) - (pad 89 smd rect (at -1.6505 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 223 /S17_P4_TRX_2_P) (solder_mask_margin 0.0508)) - (pad 88 smd rect (at 0.6355 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 222 /S17_P4_TRX_1_N) (solder_mask_margin 0.0508)) - (pad 87 smd rect (at 2.9215 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 221 /S17_P4_TRX_1_P) (solder_mask_margin 0.0508)) - (pad 86 smd rect (at 5.2075 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 220 /S17_P4_TRX_0_N) (solder_mask_margin 0.0508)) - (pad 85 smd rect (at 7.4935 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 219 /S17_P4_TRX_0_P) (solder_mask_margin 0.0508)) - (pad 84 smd rect (at 9.7795 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 83 smd rect (at 12.0655 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 218 /S17_P3_TRX_3_N) (solder_mask_margin 0.0508)) - (pad 82 smd rect (at 14.3515 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 217 /S17_P3_TRX_3_P) (solder_mask_margin 0.0508)) - (pad 81 smd rect (at 16.6375 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 216 /S17_P3_TRX_2_N) (solder_mask_margin 0.0508)) - (pad 80 smd rect (at 18.9235 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 215 /S17_P3_TRX_2_P) (solder_mask_margin 0.0508)) - (pad 79 smd rect (at 21.2095 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 214 /S17_P3_TRX_1_N) (solder_mask_margin 0.0508)) - (pad 78 smd rect (at 23.4955 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 213 /S17_P3_TRX_1_P) (solder_mask_margin 0.0508)) - (pad 77 smd rect (at 25.7815 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 212 /S17_P3_TRX_0_N) (solder_mask_margin 0.0508)) - (pad 76 smd rect (at 28.0675 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 211 /S17_P3_TRX_0_P) (solder_mask_margin 0.0508)) - (pad 75 smd rect (at 30.3535 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 74 smd rect (at 32.6395 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 236 "Net-(U1-Pad74)") (solder_mask_margin 0.0508)) - (pad 73 smd rect (at 34.9255 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 237 "Net-(U1-Pad73)") (solder_mask_margin 0.0508)) - (pad 72 smd rect (at 37.2115 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 238 "Net-(U1-Pad72)") (solder_mask_margin 0.0508)) - (pad 71 smd rect (at 39.4975 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 239 "Net-(U1-Pad71)") (solder_mask_margin 0.0508)) - (pad 70 smd rect (at 41.7835 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 240 "Net-(U1-Pad70)") (solder_mask_margin 0.0508)) - (pad 69 smd rect (at 44.0695 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 241 "Net-(U1-Pad69)") (solder_mask_margin 0.0508)) - (pad 68 smd rect (at 46.3555 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 242 "Net-(U1-Pad68)") (solder_mask_margin 0.0508)) - (pad 67 smd rect (at 48.6415 -39.4025) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 243 "Net-(U1-Pad67)") (solder_mask_margin 0.0508)) - (pad 66 smd rect (at 54.61 -33.4354 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 244 "Net-(U1-Pad66)") (solder_mask_margin 0.0508)) - (pad 65 smd rect (at 54.61 -31.1494 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 245 "Net-(U1-Pad65)") (solder_mask_margin 0.0508)) - (pad 64 smd rect (at 54.61 -28.8634 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 246 "Net-(U1-Pad64)") (solder_mask_margin 0.0508)) - (pad 63 smd rect (at 54.61 -26.5774 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 247 "Net-(U1-Pad63)") (solder_mask_margin 0.0508)) - (pad 62 smd rect (at 54.61 -24.2914 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 248 "Net-(U1-Pad62)") (solder_mask_margin 0.0508)) - (pad 61 smd rect (at 54.61 -22.006 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 249 "Net-(U1-Pad61)") (solder_mask_margin 0.0508)) - (pad 60 smd rect (at 54.61 -19.72 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 250 "Net-(U1-Pad60)") (solder_mask_margin 0.0508)) - (pad 59 smd rect (at 54.61 -17.434 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 251 "Net-(U1-Pad59)") (solder_mask_margin 0.0508)) - (pad 58 smd rect (at 54.61 -15.148 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 57 smd rect (at 54.61 -12.862 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 252 "Net-(U1-Pad57)") (solder_mask_margin 0.0508)) - (pad 56 smd rect (at 54.61 -10.576 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 253 "Net-(U1-Pad56)") (solder_mask_margin 0.0508)) - (pad 55 smd rect (at 54.61 -8.29 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 254 "Net-(U1-Pad55)") (solder_mask_margin 0.0508)) - (pad 54 smd rect (at 54.61 -6.004 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 255 "Net-(U1-Pad54)") (solder_mask_margin 0.0508)) - (pad 53 smd rect (at 54.61 -3.718 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 256 "Net-(U1-Pad53)") (solder_mask_margin 0.0508)) - (pad 52 smd rect (at 54.61 -1.432 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 257 "Net-(U1-Pad52)") (solder_mask_margin 0.0508)) - (pad 51 smd rect (at 54.61 0.854 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 258 "Net-(U1-Pad51)") (solder_mask_margin 0.0508)) - (pad 50 smd rect (at 54.61 3.14 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 259 "Net-(U1-Pad50)") (solder_mask_margin 0.0508)) - (pad 49 smd rect (at 54.61 5.426 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 28 "Net-(R86-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D669DBD) + (at 82.7317 113.4504 90) + (descr "RESISTOR

\nchip") + (path /5D0328DE/5D42E225/5D42D571) + (fp_text reference R9 (at -1.905 -0.635 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 160 "Net-(R11-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Bottom) (tedit 0) (tstamp 5DF90A47) + (at 108.95838 51.98364 180) + (descr "RESISTOR

\nchip") + (path /5D032C97/5D1A5891) + (fp_text reference R96 (at 1.07188 0.80264 180) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) + ) + (fp_text value TBD (at 1.29794 0.3556 180) (layer B.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom mirror)) + ) + (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 -0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.508 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 295 /GPIO2-EJTAG_TDO) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 137 "Net-(PCIE0-Pad1)") (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E6942B8) + (at 108.37164 60.071 270) + (descr "RESISTOR

\nchip") + (path /5D032C97/5D1AF5AD) + (fp_text reference R98 (at -1.143 -0.78486 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value TBD (at -1.905 1.397 90) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 134 /PCIe_0_CLK_P) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 135 /PCIe_0_CLK_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF92999) + (at 107.36834 67.65922 180) + (descr "RESISTOR

\nchip") + (path /5D032C97/5D1F3D95) + (fp_text reference R99 (at 4.43484 -0.34928) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value 0 (at -1.905 1.397) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 181 /PCIe_0_RX_N) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 248 /pcie0/PCIe_RX_bis_N) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:SWITCH_6X6X5 (layer Top) (tedit 0) (tstamp 5D669DFD) + (at 131.0437 226.0232) + (descr "PUSH SWITCH

\nITT-Cannon-Cannon") + (path /5D2895FD) + (fp_text reference S2 (at -7.0536 -4.5098) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_text value push_switch_SH (at -4.905 5.54) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) + ) + (fp_line (start 2 3.5) (end 2 2.55) (layer F.SilkS) (width 0.127)) + (fp_line (start -2 3.5) (end 2 3.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -2 2.55) (end -2 3.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -4.8999 -4.1001) (end -4.8999 2.55) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.8999 -4.1001) (end -4.8999 -4.1001) (layer F.SilkS) (width 0.2032)) + (fp_line (start 4.8999 2.55) (end 4.8999 -4.1001) (layer F.SilkS) (width 0.2032)) + (fp_line (start 2 2.55) (end 4.8999 2.55) (layer F.SilkS) (width 0.2032)) + (fp_line (start -2 2.55) (end 2 2.55) (layer F.SilkS) (width 0.2032)) + (fp_line (start -4.8999 2.55) (end -2 2.55) (layer F.SilkS) (width 0.2032)) + (pad 3 thru_hole circle (at 3.5 -2.5 90) (size 1.905 1.905) (drill 1.2954) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 48 smd rect (at 54.61 7.712 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 2 thru_hole circle (at 2.25 0 90) (size 1.524 1.524) (drill 0.9906) (layers *.Cu *.Mask) + (net 96 /GPIO17) (solder_mask_margin 0.0508)) + (pad 1 thru_hole circle (at -2.25 0 90) (size 1.524 1.524) (drill 0.9906) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 47 smd rect (at 54.61 9.998 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 4 thru_hole circle (at -3.5 -2.5 90) (size 1.905 1.905) (drill 1.2954) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 46 smd rect (at 54.61 12.284 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + ) + + (module LibreRouter_MegaBoard:USB_HUB_FE1.1S (layer Top) (tedit 0) (tstamp 5D669E45) + (at 124.4639 201.3344 90) + (path /5D032896/5D46F2DE) + (fp_text reference U12 (at -5.4216 1.9646) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_text value USB_HUB_FE1.1S (at 7.5 3) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_arc (start -5 0) (end -5 -0.5) (angle 180) (layer F.SilkS) (width 0.127)) + (fp_circle (center -4.6 1.6) (end -4.4 1.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 5 2) (end 5 -2) (layer F.SilkS) (width 0.127)) + (fp_line (start -5 2) (end 5 2) (layer F.SilkS) (width 0.127)) + (fp_line (start -5 0.5) (end -5 2) (layer F.SilkS) (width 0.127)) + (fp_line (start -5 -0.5) (end -5 0.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -5 -2) (end -5 -0.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 5 -2) (end -5 -2) (layer F.SilkS) (width 0.127)) + (pad 28 smd rect (at -4.16 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 90 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) + (pad 27 smd rect (at -3.52 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 27 "Net-(U12-Pad27)") (solder_mask_margin 0.0508)) + (pad 26 smd rect (at -2.88 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 28 "Net-(R86-Pad1)") (solder_mask_margin 0.0508)) + (pad 25 smd rect (at -2.24 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 29 "Net-(U12-Pad25)") (solder_mask_margin 0.0508)) + (pad 24 smd rect (at -1.6 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 30 "Net-(U12-Pad24)") (solder_mask_margin 0.0508)) + (pad 23 smd rect (at -0.96 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 31 "Net-(U12-Pad23)") (solder_mask_margin 0.0508)) + (pad 22 smd rect (at -0.32 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 32 "Net-(U12-Pad22)") (solder_mask_margin 0.0508)) + (pad 21 smd rect (at 0.32 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (pad 20 smd rect (at 0.96 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) + (pad 19 smd rect (at 1.6 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 33 "Net-(R83-Pad1)") (solder_mask_margin 0.0508)) + (pad 18 smd rect (at 2.24 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 34 "Net-(R84-Pad2)") (solder_mask_margin 0.0508)) + (pad 17 smd rect (at 2.88 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 35 "Net-(R82-Pad1)") (solder_mask_margin 0.0508)) + (pad 16 smd rect (at 3.52 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 237 /Core9558/USB1_DP) (solder_mask_margin 0.0508)) + (pad 15 smd rect (at 4.16 -2.62 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 236 /Core9558/USB1_DM) (solder_mask_margin 0.0508)) + (pad 14 smd rect (at 4.16 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 36 "Net-(R81-Pad2)") (solder_mask_margin 0.0508)) + (pad 13 smd rect (at 3.52 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 89 /USB_hub/USB_3.3V) (solder_mask_margin 0.0508)) + (pad 12 smd rect (at 2.88 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 90 /USB_hub/USB_1.8V) (solder_mask_margin 0.0508)) + (pad 11 smd rect (at 2.24 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 239 /USB_hub/USB_1_P) (solder_mask_margin 0.0508)) + (pad 10 smd rect (at 1.6 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 240 /USB_hub/USB_1_N) (solder_mask_margin 0.0508)) + (pad 9 smd rect (at 0.96 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 241 /USB_hub/USB_2_P) (solder_mask_margin 0.0508)) + (pad 8 smd rect (at 0.32 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 242 /USB_hub/USB_2_N) (solder_mask_margin 0.0508)) + (pad 7 smd rect (at -0.32 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 124 /USB_hub/USB_3_P) (solder_mask_margin 0.0508)) + (pad 6 smd rect (at -0.96 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 125 /USB_hub/USB_3_N) (solder_mask_margin 0.0508)) + (pad 5 smd rect (at -1.6 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 126 /USB_hub/USB_4_P) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at -2.24 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 127 /USB_hub/USB_4_N) (solder_mask_margin 0.0508)) + (pad 3 smd rect (at -2.88 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 92 "Net-(C63-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -3.52 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) + (net 91 "Net-(C61-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -4.16 2.6 180) (size 1.1 0.3) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 45 smd rect (at 54.61 14.57 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + ) + + (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D669E6C) + (at 93.7299 186.9326 270) + (path /5D0328DE/5D4FE12B/5D42D1B4) + (fp_text reference U4 (at -1.2713 -1.9138 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_arc (start 1.6256 -0.9144) (end 2.3368 -0.9398) (angle 180) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 -0.9144) (end 2.3876 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start -0.0762 -0.9144) (end 0.9144 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start -0.0762 4.5466) (end -0.0762 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 4.5466) (end -0.0762 4.5466) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 -0.9144) (end 3.4036 4.5466) (layer F.SilkS) (width 0.3048)) + (pad 9 smd rect (at 1.651 1.9558 270) (size 2.9972 3.5052) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 44 smd rect (at 54.61 16.856 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 43 smd rect (at 54.61 19.142 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 42 smd rect (at 54.61 21.428 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 41 smd rect (at 54.61 23.714 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 40 smd rect (at 54.61 26 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 39 smd rect (at 54.61 28.286 90) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 38 smd rect (at 48.6415 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 95 /POWER_EN_5V) (solder_mask_margin 0.0508)) + (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 12 "Net-(C30-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 13 "Net-(C30-Pad1)") (solder_mask_margin 0.0508)) + (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 161 "Net-(R10-Pad2)") (solder_mask_margin 0.0508)) + (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 14 "Net-(C45-Pad2)") (solder_mask_margin 0.0508)) + (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 16 "Net-(R13-Pad1)") (solder_mask_margin 0.0508)) + (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 297 /VCC) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D669E7E) + (at 88.4975 145.7338 270) + (path /5D0328DE/5D4FEB2F/5D42D1B4) + (fp_text reference U5 (at -1.3094 -1.1137 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_arc (start 1.6256 -0.9144) (end 2.3368 -0.9398) (angle 180) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 -0.9144) (end 2.3876 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start -0.0762 -0.9144) (end 0.9144 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start -0.0762 4.5466) (end -0.0762 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 4.5466) (end -0.0762 4.5466) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 -0.9144) (end 3.4036 4.5466) (layer F.SilkS) (width 0.3048)) + (pad 9 smd rect (at 1.651 1.9558 270) (size 2.9972 3.5052) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 37 smd rect (at 46.3555 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 260 /Core9558/USB1_DM) (solder_mask_margin 0.0508)) - (pad 36 smd rect (at 44.0695 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 261 /Core9558/USB1_DP) (solder_mask_margin 0.0508)) - (pad 35 smd rect (at 41.7835 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 34 smd rect (at 39.4975 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 143 /USB2_N) (solder_mask_margin 0.0508)) - (pad 33 smd rect (at 37.2115 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 142 /USB2_P) (solder_mask_margin 0.0508)) - (pad 32 smd rect (at 34.9255 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 95 /POWER_EN_5V) (solder_mask_margin 0.0508)) + (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 17 "Net-(C62-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 18 "Net-(C62-Pad1)") (solder_mask_margin 0.0508)) + (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 175 "Net-(R45-Pad2)") (solder_mask_margin 0.0508)) + (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 19 "Net-(C66-Pad2)") (solder_mask_margin 0.0508)) + (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 21 "Net-(R52-Pad1)") (solder_mask_margin 0.0508)) + (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 297 /VCC) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D669E90) + (at 88.2689 106.5924 270) + (path /5D0328DE/5D42E225/5D42D1B4) + (fp_text reference U6 (at -1.27 -1.27 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_arc (start 1.6256 -0.9144) (end 2.3368 -0.9398) (angle 180) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 -0.9144) (end 2.3876 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start -0.0762 -0.9144) (end 0.9144 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start -0.0762 4.5466) (end -0.0762 -0.9144) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 4.5466) (end -0.0762 4.5466) (layer F.SilkS) (width 0.3048)) + (fp_line (start 3.4036 -0.9144) (end 3.4036 4.5466) (layer F.SilkS) (width 0.3048)) + (pad 9 smd rect (at 1.651 1.9558 270) (size 2.9972 3.5052) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 31 smd rect (at 32.6395 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 262 /GPIO23) (solder_mask_margin 0.0508)) - (pad 30 smd rect (at 30.3535 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 172 /GPIO22) (solder_mask_margin 0.0508)) - (pad 29 smd rect (at 28.0675 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 108 /GPIO21) (solder_mask_margin 0.0508)) - (pad 28 smd rect (at 25.7815 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 106 /GPIO20) (solder_mask_margin 0.0508)) - (pad 27 smd rect (at 23.4955 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 104 /GPIO19) (solder_mask_margin 0.0508)) - (pad 26 smd rect (at 21.2095 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 112 /GPIO18) (solder_mask_margin 0.0508)) - (pad 25 smd rect (at 18.9235 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 98 /GPIO17) (solder_mask_margin 0.0508)) - (pad 24 smd rect (at 16.6375 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 103 /GPIO16) (solder_mask_margin 0.0508)) - (pad 23 smd rect (at 14.3515 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 105 /GPIO15) (solder_mask_margin 0.0508)) - (pad 22 smd rect (at 12.0655 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 107 /GPIO14) (solder_mask_margin 0.0508)) - (pad 21 smd rect (at 9.7795 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 109 /GPIO13) (solder_mask_margin 0.0508)) - (pad 20 smd rect (at 7.4935 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 110 /GPIO12) (solder_mask_margin 0.0508)) - (pad 19 smd rect (at 5.2075 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 111 /UART_SOUT) (solder_mask_margin 0.0508)) - (pad 18 smd rect (at 2.9215 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 113 /UART_SIN) (solder_mask_margin 0.0508)) - (pad 17 smd rect (at 0.6355 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 114 /GPIO4) (solder_mask_margin 0.0508)) - (pad 16 smd rect (at -1.6505 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 15 smd rect (at -3.9365 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 14 smd rect (at -6.2225 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 95 /5V0_2GPA) (solder_mask_margin 0.0508)) - (pad 13 smd rect (at -8.5085 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 12 smd rect (at -10.7945 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 94 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) + (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 2 "Net-(C12-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 3 "Net-(C12-Pad1)") (solder_mask_margin 0.0508)) + (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 160 "Net-(R11-Pad1)") (solder_mask_margin 0.0508)) + (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 4 "Net-(C16-Pad2)") (solder_mask_margin 0.0508)) + (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 6 "Net-(R58-Pad1)") (solder_mask_margin 0.0508)) + (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) + (net 297 /VCC) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:S8S1 (layer Top) (tedit 0) (tstamp 5D669EA2) + (at 88.3451 124.2708 270) + (path /5D032C38/5D14FFA1) + (fp_text reference WDT1 (at 0 -6.31 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) + ) + (fp_text value ATTINY13 (at -0.03 0.6 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_circle (center 0.63 -5.27) (end 0.936103 -5.27) (layer F.SilkS) (width 0.127)) + (fp_line (start 4 -1) (end -0.01 -1) (layer F.SilkS) (width 0.127)) + (fp_line (start 4 -5.98) (end 4 -1) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.01 -5.98) (end 4 -5.98) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.01 -1) (end -0.01 -5.98) (layer F.SilkS) (width 0.127)) + (pad 7 smd rect (at 4.46 -4.11 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 213 /WL_SLK) (solder_mask_margin 0.0508)) + (pad 8 smd rect (at 4.46 -5.47 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) + (pad 5 smd rect (at 4.46 -1.48 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 212 /WL_MOSI) (solder_mask_margin 0.0508)) + (pad 6 smd rect (at 4.46 -2.84 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 176 /WL_MISO) (solder_mask_margin 0.0508)) + (pad 2 smd rect (at -0.54 -4.11 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 70 "Net-(WDT1-Pad2)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.54 -5.47 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 98 /watchdog/~WR_RST) (solder_mask_margin 0.0508)) + (pad 4 smd rect (at -0.54 -1.48 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 11 smd rect (at -13.0805 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 3 smd rect (at -0.54 -2.84 270) (size 1.27 0.51) (layers Top F.Paste F.Mask) + (net 128 /watchdog/RST_J-) (solder_mask_margin 0.0508)) + ) + + (module LibreRouter_MegaBoard:SMARTPRJ_CRYSTAL-3.2-2.5 (layer Top) (tedit 0) (tstamp 5D669EBB) + (at 130.6869 204.8396 270) + (path /5D032896/5D497A3C) + (fp_text reference X2 (at 2.8435 0.7532) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) + ) + (fp_text value "YSX321SL 12MHz" (at -1.6 2.25 90) (layer F.Fab) + (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) + ) + (fp_line (start -1.6 -1.25) (end 1.6 -1.25) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.6 1.25) (end -1.6 -1.25) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.6 1.25) (end -1.6 1.25) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.6 -1.25) (end 1.6 1.25) (layer F.SilkS) (width 0.127)) + (pad 4 smd rect (at -1.15 -0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 10 smd rect (at -15.365 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 115 /GPIO3) (solder_mask_margin 0.0508)) - (pad 9 smd rect (at -17.6525 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 116 /WD_PCIe0_WAKE) (solder_mask_margin 0.0508)) - (pad 8 smd rect (at -19.9385 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 117 /GPIO1) (solder_mask_margin 0.0508)) - (pad 7 smd rect (at -22.2245 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 118 /GPIO0) (solder_mask_margin 0.0508)) - (pad 6 smd rect (at -24.5105 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 99 /RST_B) (solder_mask_margin 0.0508)) - (pad 5 smd rect (at -26.7965 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 4 smd rect (at -29.0825 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - (pad 3 smd rect (at -31.3685 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 209 /COM_B_2G) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at -33.6545 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) - (net 210 /COM_A_2G) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -35.9405 34.26) (size 2.29 1.14) (layers Top F.Paste F.Mask) + (pad 3 smd rect (at 1.15 -0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) + (net 91 "Net-(C61-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 1.15 0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -1.15 0.925) (size 1.05 1.3) (layers Top F.Paste F.Mask) + (net 92 "Net-(C63-Pad1)") (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66A02D) (at 85.5765 61.0754 270) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42D488) - (fp_text reference C13 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference C13 (at -1.0679 0.6135 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -6981,15 +7910,15 @@ (net 8 "Net-(C13-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66A03D) + (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5E693E63) (at 81.7157 70.0926 270) (descr "RESISTOR

\nchip") (path /5D0328DE/5D42CD47/5D42D571) - (fp_text reference R14 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference R14 (at -1.3221 1.439 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "53.6K 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -7003,20 +7932,20 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 175 "Net-(R14-Pad2)") (solder_mask_margin 0.0508)) + (net 162 "Net-(R14-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66A04D) (at 81.7157 72.1754 270) (descr "RESISTOR

\nchip") (path /5D0328DE/5D42CD47/5D42D5CB) - (fp_text reference R15 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference R15 (at -0.8014 0.8167 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "10k 1%" (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -7032,15 +7961,15 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 175 "Net-(R14-Pad2)") (solder_mask_margin 0.0508)) + (net 162 "Net-(R14-Pad2)") (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66A05D) (at 92.9171 64.6062 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42DBCD) - (fp_text reference C28 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference C28 (at -0.9258 1.9519 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) @@ -7061,7 +7990,7 @@ (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) @@ -7070,8 +7999,8 @@ (at 89.9961 68.5686 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42D229) - (fp_text reference C29 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference C29 (at -2.0434 -0.2071 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) hide (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) @@ -7094,18 +8023,18 @@ (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66A08E) (at 84.2303 72.658 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42D659) - (fp_text reference C32 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference C32 (at -1.1925 -0.2833 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 2.7nF (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -7124,11 +8053,11 @@ (net 10 "Net-(C32-Pad1)") (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D66A09E) + (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5E6943EA) (at 86.7703 65.3428 270) (path /5D0328DE/5D42CD47/5D42D1B4) - (fp_text reference U2 (at -1.27 -1.27 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference U2 (at 1.0655 4.7664 180) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value RT7272 (at -1.27 6.35 90) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) @@ -7144,30 +8073,30 @@ (pad 4 smd roundrect (at -1.2192 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 1 GND) (solder_mask_margin 0.0508)) (pad 3 smd roundrect (at -1.2192 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 96 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) + (net 94 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) (pad 2 smd roundrect (at -1.2192 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 7 "Net-(C13-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd roundrect (at -1.2192 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 8 "Net-(C13-Pad1)") (solder_mask_margin 0.0508)) (pad 5 smd roundrect (at 4.5466 3.81) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 175 "Net-(R14-Pad2)") (solder_mask_margin 0.0508)) + (net 162 "Net-(R14-Pad2)") (solder_mask_margin 0.0508)) (pad 6 smd roundrect (at 4.5466 2.54) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 9 "Net-(C32-Pad2)") (solder_mask_margin 0.0508)) (pad 7 smd roundrect (at 4.5466 1.27) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 11 "Net-(R19-Pad1)") (solder_mask_margin 0.0508)) (pad 8 smd roundrect (at 4.5466 0) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66A0B0) (at 85.2463 72.658 270) (descr "RESISTOR

\nchip") (path /5D0328DE/5D42CD47/5D42D2DE) - (fp_text reference R19 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference R19 (at 1.129 0.2833 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 180k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -7190,8 +8119,8 @@ (at 92.1551 68.5686 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D43058C) - (fp_text reference C36 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference C36 (at -2.1069 -0.1436 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value "10uF, 35V" (at -0.889 2.286 90) (layer F.Fab) hide (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) @@ -7214,18 +8143,18 @@ (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66A0D4) (at 83.2143 72.658 90) (descr "RESISTOR

\nchip") (path /5D0328DE/5D42CD47/5D42D605) - (fp_text reference R37 (at -1.905 -0.635 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text reference R37 (at -3.415 -0.4103 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) (fp_text value 24k (at -1.905 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -7248,8 +8177,8 @@ (at 90.7581 64.6062 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42DAC0) - (fp_text reference C38 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference C38 (at 1.2967 -1.1596 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "22uF, 10V" (at -0.889 2.286 90) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) @@ -7270,7 +8199,7 @@ (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -1 0 90) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) @@ -7279,11 +8208,11 @@ (at 96.2953 64.0728 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42DC2B) - (fp_text reference C71 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text reference C71 (at 1.2078 0.5422 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -7297,7 +8226,7 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) @@ -7306,11 +8235,11 @@ (at 95.2793 64.0728 90) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D42CD47/5D42DCB2) - (fp_text reference C72 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text reference C72 (at 1.2078 0.3517 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_text value "0.1uF, 10V" (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -7324,44 +8253,19 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 90) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C1206 (layer Top) (tedit 0) (tstamp 5D66A118) - (at 239.8053 192.5206) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D4FF644) - (fp_text reference C49 (at -1.27 -1.143) (layer F.SilkS) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left top)) - ) - (fp_text value "10nF, 2KV" (at -1.27 2.413) (layer F.Fab) - (effects (font (size 0.9652 0.9652) (thickness 0.077216)) (justify left top)) - ) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) - (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer F.Fab) (width 0.1016)) - (fp_line (start 2.473 -0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -2.473 0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 2.473 0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -2.473 -0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1.4 0) (size 1.6 1.8) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1.4 0) (size 1.6 1.8) (layers Top F.Paste F.Mask) - (net 90 "Net-(C49-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:2X13 (layer Top) (tedit 0) (tstamp 5D66A1A2) + (module LibreRouter_MegaBoard:2X13 (layer Top) (tedit 0) (tstamp 5E15BBF3) (at 107.6237 160.3388 270) (descr "PIN HEADER") (path /5D446377) - (fp_text reference GPIO1 (at -16.51 -3.175) (layer F.SilkS) + (fp_text reference GPIO1 (at -17.2352 2.6201) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) ) - (fp_text value Conn_02x13 (at -16.51 4.445 90) (layer F.Fab) + (fp_text value Conn_02x13 (at -19.39928 -5.13706 180) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) (fp_poly (pts (xy 14.986 1.524) (xy 15.494 1.524) (xy 15.494 1.016) (xy 14.986 1.016)) (layer F.SilkS) (width 0)) @@ -7483,77 +8387,77 @@ (fp_line (start -15.875 2.54) (end -14.605 2.54) (layer F.SilkS) (width 0.1524)) (fp_line (start -16.51 1.905) (end -15.875 2.54) (layer F.SilkS) (width 0.1524)) (pad 26 thru_hole circle (at 15.24 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (net 297 /VCC) (solder_mask_margin 0.0508)) (pad 25 thru_hole circle (at 15.24 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 24 thru_hole circle (at 12.7 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 103 /GPIO16) (solder_mask_margin 0.0508)) + (net 288 /GPIO16-GPS_UART_TX) (solder_mask_margin 0.0508)) (pad 23 thru_hole circle (at 12.7 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 104 /GPIO19) (solder_mask_margin 0.0508)) + (net 101 /GPIO19) (solder_mask_margin 0.0508)) (pad 22 thru_hole circle (at 10.16 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 105 /GPIO15) (solder_mask_margin 0.0508)) + (net 289 /GPIO15-GPS_UART_RX) (solder_mask_margin 0.0508)) (pad 21 thru_hole circle (at 10.16 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 106 /GPIO20) (solder_mask_margin 0.0508)) + (net 102 /GPIO20) (solder_mask_margin 0.0508)) (pad 20 thru_hole circle (at 7.62 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 107 /GPIO14) (solder_mask_margin 0.0508)) + (net 290 /GPIO14-PCIe1_nDISABLE) (solder_mask_margin 0.0508)) (pad 19 thru_hole circle (at 7.62 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 108 /GPIO21) (solder_mask_margin 0.0508)) + (net 103 /GPIO21) (solder_mask_margin 0.0508)) (pad 18 thru_hole circle (at 5.08 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 109 /GPIO13) (solder_mask_margin 0.0508)) + (net 291 /GPIO13-GPS_PPS) (solder_mask_margin 0.0508)) (pad 17 thru_hole circle (at 5.08 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) + (net 81 /5V_1) (solder_mask_margin 0.0508)) (pad 16 thru_hole circle (at 2.54 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 110 /GPIO12) (solder_mask_margin 0.0508)) + (net 292 /GPIO12-PCIe0_nDISABLE) (solder_mask_margin 0.0508)) (pad 15 thru_hole circle (at 2.54 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 14 thru_hole circle (at 0 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 111 /UART_SOUT) (solder_mask_margin 0.0508)) + (net 104 /UART_SOUT) (solder_mask_margin 0.0508)) (pad 13 thru_hole circle (at 0 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 112 /GPIO18) (solder_mask_margin 0.0508)) + (net 105 /GPIO18) (solder_mask_margin 0.0508)) (pad 12 thru_hole circle (at -2.54 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 113 /UART_SIN) (solder_mask_margin 0.0508)) + (net 106 /UART_SIN) (solder_mask_margin 0.0508)) (pad 11 thru_hole circle (at -2.54 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 98 /GPIO17) (solder_mask_margin 0.0508)) + (net 96 /GPIO17) (solder_mask_margin 0.0508)) (pad 10 thru_hole circle (at -5.08 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 114 /GPIO4) (solder_mask_margin 0.0508)) + (net 107 /GPIO4) (solder_mask_margin 0.0508)) (pad 9 thru_hole circle (at -5.08 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 80 /+3V3) (solder_mask_margin 0.0508)) + (net 79 /+3V3) (solder_mask_margin 0.0508)) (pad 8 thru_hole circle (at -7.62 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 115 /GPIO3) (solder_mask_margin 0.0508)) + (net 283 "Net-(GPIO1-Pad8)") (solder_mask_margin 0.0508)) (pad 7 thru_hole circle (at -7.62 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 6 thru_hole circle (at -10.16 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 116 /WD_PCIe0_WAKE) (solder_mask_margin 0.0508)) + (net 284 "Net-(GPIO1-Pad6)") (solder_mask_margin 0.0508)) (pad 5 thru_hole circle (at -10.16 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 99 /RST_B) (solder_mask_margin 0.0508)) + (net 287 "Net-(GPIO1-Pad5)") (solder_mask_margin 0.0508)) (pad 4 thru_hole circle (at -12.7 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 117 /GPIO1) (solder_mask_margin 0.0508)) + (net 285 "Net-(GPIO1-Pad4)") (solder_mask_margin 0.0508)) (pad 3 thru_hole circle (at -12.7 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 97 /POWER_EN_5V) (solder_mask_margin 0.0508)) + (net 95 /POWER_EN_5V) (solder_mask_margin 0.0508)) (pad 2 thru_hole circle (at -15.24 -1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 118 /GPIO0) (solder_mask_margin 0.0508)) + (net 286 "Net-(GPIO1-Pad2)") (solder_mask_margin 0.0508)) (pad 1 thru_hole circle (at -15.24 1.27 270) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 96 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) + (net 94 /POWER_EN_3.3V) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:MA04-1 (layer Top) (tedit 0) (tstamp 5D66A2BC) - (at 149.7877 198.007) + (at 137.11174 199.42048 90) (descr "PIN HEADER") (path /5D08F117) - (fp_text reference USB1 (at -5.08 -1.651) (layer F.SilkS) + (fp_text reference USB1 (at 6.68528 -2.05994 180) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) ) - (fp_text value Conn_01x04 (at 0.635 -1.651) (layer F.Fab) + (fp_text value Conn_01x04 (at 0.635 -1.651 90) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) ) (fp_poly (pts (xy 3.556 0.254) (xy 4.064 0.254) (xy 4.064 -0.254) (xy 3.556 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy 1.016 0.254) (xy 1.524 0.254) (xy 1.524 -0.254) (xy 1.016 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy -4.064 0.254) (xy -3.556 0.254) (xy -3.556 -0.254) (xy -4.064 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy -1.524 0.254) (xy -1.016 0.254) (xy -1.016 -0.254) (xy -1.524 -0.254)) (layer F.Fab) (width 0)) - (fp_text user 4 (at 5.334 0.635) (layer F.SilkS) + (fp_text user 4 (at 5.334 0.635 90) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) ) - (fp_text user 1 (at -6.223 0.635) (layer F.SilkS) + (fp_text user 1 (at -6.223 0.635 90) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) ) (fp_line (start 4.445 1.27) (end 3.175 1.27) (layer F.SilkS) (width 0.1524)) @@ -7582,61 +8486,36 @@ (fp_line (start -2.54 0.635) (end -3.175 1.27) (layer F.SilkS) (width 0.1524)) (fp_line (start -3.175 -1.27) (end -2.54 -0.635) (layer F.SilkS) (width 0.1524)) (fp_line (start -4.445 -1.27) (end -3.175 -1.27) (layer F.SilkS) (width 0.1524)) - (pad 4 thru_hole oval (at 3.81 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (pad 4 thru_hole oval (at 3.81 0 180) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 3 thru_hole oval (at 1.27 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 263 /USB_hub/USB_1_P) (solder_mask_margin 0.0508)) - (pad 2 thru_hole oval (at -1.27 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 264 /USB_hub/USB_1_N) (solder_mask_margin 0.0508)) - (pad 1 thru_hole oval (at -3.81 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 83 /5V_1) (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R1206 (layer Bottom) (tedit 0) (tstamp 5D66A2E3) - (at 215.3197 192.038) - (descr "RESISTOR

\nchip") - (path /5D032DC8/5D670C78) - (fp_text reference R25 (at -1.397 1.143 180) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify right bottom mirror)) - ) - (fp_text value 0 (at -1.397 -2.413 180) (layer B.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom mirror)) - ) - (fp_line (start -2.667 -1.016) (end -2.667 1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start 2.667 -1.016) (end -2.667 -1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start 2.667 1.016) (end 2.667 -1.016) (layer B.SilkS) (width 0.127)) - (fp_line (start -2.667 1.016) (end 2.667 1.016) (layer B.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.3 -0.7) (xy 0.3 -0.7) (xy 0.3 0.7) (xy -0.3 0.7)) (layer B.Adhes) (width 0)) - (fp_poly (pts (xy 0.9525 -0.8763) (xy 1.6891 -0.8763) (xy 1.6891 0.8763) (xy 0.9525 0.8763)) (layer B.Fab) (width 0)) - (fp_poly (pts (xy -1.6891 -0.8763) (xy -0.9525 -0.8763) (xy -0.9525 0.8763) (xy -1.6891 0.8763)) (layer B.Fab) (width 0)) - (fp_line (start 0.9525 0.8128) (end -0.9652 0.8128) (layer B.Fab) (width 0.1524)) - (fp_line (start 0.9525 -0.8128) (end -0.9652 -0.8128) (layer B.Fab) (width 0.1524)) - (pad 1 smd rect (at -1.71 0) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) - (net 180 /12V_POE) (solder_mask_margin 0.0508)) - (pad 2 smd rect (at 1.71 0) (size 1.52 1.6) (layers Bottom B.Paste B.Mask) - (net 169 /ethernet_frontend/MCT6) (solder_mask_margin 0.0508)) + (pad 3 thru_hole oval (at 1.27 0 180) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 239 /USB_hub/USB_1_P) (solder_mask_margin 0.0508)) + (pad 2 thru_hole oval (at -1.27 0 180) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 240 /USB_hub/USB_1_N) (solder_mask_margin 0.0508)) + (pad 1 thru_hole oval (at -3.81 0 180) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 81 /5V_1) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:MA05-1 (layer Top) (tedit 0) (tstamp 5D66A2F1) - (at 91.1137 50.814) + (module LibreRouter_MegaBoard:MA05-1 (layer Top) (tedit 0) (tstamp 5E69554E) + (at 89.42324 166.58336 180) (descr "PIN HEADER") (path /5D984000) - (fp_text reference GPS1 (at -6.35 -1.651) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + (fp_text reference GPS1 (at 1.64084 2.01676) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right bottom)) ) (fp_text value Conn_01x05 (at -2.54 2.921) (layer F.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) + (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify right bottom)) ) (fp_poly (pts (xy 2.286 0.254) (xy 2.794 0.254) (xy 2.794 -0.254) (xy 2.286 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy 4.826 0.254) (xy 5.334 0.254) (xy 5.334 -0.254) (xy 4.826 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy -0.254 0.254) (xy 0.254 0.254) (xy 0.254 -0.254) (xy -0.254 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy -5.334 0.254) (xy -4.826 0.254) (xy -4.826 -0.254) (xy -5.334 -0.254)) (layer F.Fab) (width 0)) (fp_poly (pts (xy -2.794 0.254) (xy -2.286 0.254) (xy -2.286 -0.254) (xy -2.794 -0.254)) (layer F.Fab) (width 0)) - (fp_text user 5 (at 4.445 -1.651) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + (fp_text user 5 (at 4.4196 -3.18262) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right bottom)) ) - (fp_text user 1 (at -5.715 2.921) (layer F.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify left bottom)) + (fp_text user 1 (at -5.88518 -3.24104) (layer F.SilkS) + (effects (font (size 1.2065 1.2065) (thickness 0.127)) (justify right bottom)) ) (fp_line (start 3.175 1.27) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) (fp_line (start 1.27 0.635) (end 1.905 1.27) (layer F.SilkS) (width 0.1524)) @@ -7670,27 +8549,27 @@ (fp_line (start -3.81 0.635) (end -4.445 1.27) (layer F.SilkS) (width 0.1524)) (fp_line (start -4.445 -1.27) (end -3.81 -0.635) (layer F.SilkS) (width 0.1524)) (fp_line (start -5.715 -1.27) (end -4.445 -1.27) (layer F.SilkS) (width 0.1524)) - (pad 5 thru_hole oval (at 5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (pad 5 thru_hole oval (at 5.08 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 4 thru_hole oval (at 2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 109 /GPIO13) (solder_mask_margin 0.0508)) - (pad 3 thru_hole oval (at 0 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 103 /GPIO16) (solder_mask_margin 0.0508)) - (pad 2 thru_hole oval (at -2.54 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 105 /GPIO15) (solder_mask_margin 0.0508)) - (pad 1 thru_hole oval (at -5.08 0 90) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (pad 4 thru_hole oval (at 2.54 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 291 /GPIO13-GPS_PPS) (solder_mask_margin 0.0508)) + (pad 3 thru_hole oval (at 0 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 288 /GPIO16-GPS_UART_TX) (solder_mask_margin 0.0508)) + (pad 2 thru_hole oval (at -2.54 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 289 /GPIO15-GPS_UART_RX) (solder_mask_margin 0.0508)) + (pad 1 thru_hole oval (at -5.08 0 270) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) + (net 79 /+3V3) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66A348) - (at 87.4307 170.194) + (at 88.02116 173.3436 270) (descr "RESISTOR

\nchip") (path /5D032C56/5D44BE47) - (fp_text reference R23 (at -1.905 -0.635 180) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left top)) + (fp_text reference R23 (at -1.09096 1.3462 270) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify right top)) ) - (fp_text value 330 (at -1.905 1.397 180) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify left top)) + (fp_text value 330 (at -1.905 1.397 270) (layer F.Fab) + (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify right top)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -7703,44 +8582,17 @@ (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 178 "Net-(R23-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66A370) - (at 92.8917 168.797) - (descr "RESISTOR

\nchip") - (path /5D032C56/5D44A619) - (fp_text reference R26 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) - ) - (fp_text value 330 (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) - ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 106 /GPIO20) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 181 "Net-(R26-Pad1)") (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 165 "Net-(R23-Pad1)") (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:MA03-1 (layer Top) (tedit 0) (tstamp 5D66D992) (at 117.03812 98.52152 270) (descr "PIN HEADER") (path /5D361FBF) - (fp_text reference SV1 (at -3.81 -1.651) (layer F.SilkS) + (fp_text reference SV1 (at -4.28752 1.78562) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.12065)) (justify left bottom)) ) (fp_text value Conn_01x03 (at -3.81 2.921 90) (layer F.Fab) @@ -7770,22 +8622,22 @@ (fp_line (start -1.905 -1.27) (end -1.27 -0.635) (layer F.SilkS) (width 0.1524)) (fp_line (start -3.175 -1.27) (end -1.905 -1.27) (layer F.SilkS) (width 0.1524)) (pad 3 thru_hole oval (at 2.54 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 209 /COM_B_2G) (solder_mask_margin 0.0508)) + (net 194 /COM_B_2G) (solder_mask_margin 0.0508)) (pad 2 thru_hole oval (at 0 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 thru_hole oval (at -2.54 0) (size 3.048 1.524) (drill 1.016) (layers *.Cu *.Mask) - (net 210 /COM_A_2G) (solder_mask_margin 0.0508)) + (net 195 /COM_A_2G) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D66D9D8) (at 134.5477 67.705 270) (descr "CAPACITOR

\nchip") (path /5D529F8F) - (fp_text reference C1 (at -1.016 0.762 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text reference C1 (at 2.526 0.5627 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_text value 10pF (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) @@ -7801,18 +8653,18 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 72 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) + (net 71 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D66D9E8) (at 138.2307 67.705 270) (descr "CAPACITOR

\nchip") (path /5D4B9F8C) - (fp_text reference C2 (at -1.016 0.762 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text reference C2 (at 2.5895 0.3087 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_text value 33pF (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) @@ -7828,18 +8680,18 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 73 /pcie0/SIM_DATA) (solder_mask_margin 0.0508)) + (net 72 /pcie0/SIM_DATA) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D66D9F8) (at 139.2467 67.705 270) (descr "CAPACITOR

\nchip") (path /5D494A43) - (fp_text reference C3 (at -1.016 0.762 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text reference C3 (at 2.653 0.2452 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_text value 33pF (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) @@ -7855,18 +8707,18 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 74 /pcie0/SIM_CLK) (solder_mask_margin 0.0508)) + (net 73 /pcie0/SIM_CLK) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D66DA08) (at 136.9607 67.705 270) (descr "CAPACITOR

\nchip") (path /5D46F7C7) - (fp_text reference C4 (at -1.016 0.762 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text reference C4 (at 2.5895 -0.0088 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_text value 33pF (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) @@ -7882,18 +8734,18 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 75 /pcie0/SIM_RST) (solder_mask_margin 0.0508)) + (net 74 /pcie0/SIM_RST) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D66DA18) (at 135.5637 67.705 270) (descr "CAPACITOR

\nchip") (path /5D529D79) - (fp_text reference C6 (at -1.016 0.762 90) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (fp_text reference C6 (at 2.526 0.2452 90) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_text value "0.1uF, 10V" (at -1.143 -1.397 90) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top mirror)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top mirror)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) @@ -7909,18 +8761,18 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 72 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) + (net 71 /pcie0/SIM_VCC) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66DA28) (at 126.5428 54.93004 270) (descr "CAPACITOR

\nchip") (path /5D2A0499) - (fp_text reference C7 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference C7 (at -2.98704 0.3048 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 33pF (at -1.143 1.397 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -7936,7 +8788,7 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5DF9398E) @@ -7944,10 +8796,10 @@ (descr "CAPACITOR

\nchip") (path /5D2A0651) (fp_text reference C8 (at -1.016 -0.762 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 10pF (at -2.25298 -0.75692 90) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -7963,41 +8815,41 @@ (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Bottom) (tedit 0) (tstamp 5D66DA48) (at 245.73738 99.16414 180) (descr "CAPACITOR

\nchip") (path /5D2A06B3) - (fp_text reference C9 (at -1.016 0.762) (layer B.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (fp_text reference C9 (at -2.92354 -0.35814) (layer B.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) (fp_text value 33pF (at -1.143 -1.397) (layer B.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom mirror)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom mirror)) ) - (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) - (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer B.SilkS) (width 0.127)) - (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) - (net 77 /+3V3_PCIE) (solder_mask_margin 0.0508)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -0.5715 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -1.016 -0.4445) (layer B.SilkS) (width 0.127)) + (fp_line (start -0.508 0.4445) (end -1.016 0.4445) (layer B.SilkS) (width 0.127)) + (fp_poly (pts (xy -0.1999 -0.3) (xy 0.1999 -0.3) (xy 0.1999 0.3) (xy -0.1999 0.3)) (layer B.Adhes) (width 0)) + (fp_line (start -1.092 -0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 -0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) (net 1 GND) (solder_mask_margin 0.0508)) + (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Bottom B.Paste B.Mask) + (net 76 /+3V3_PCIE) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66DA6D) (at 94.6697 85.612 180) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D488) - (fp_text reference C21 (at -1.016 -0.762) (layer F.SilkS) + (fp_text reference C21 (at -3.3235 -0.3797) (layer F.SilkS) (effects (font (size 0.77216 0.77216) (thickness 0.065024)) (justify right bottom)) ) (fp_text value "0.1uF, 10V" (at -1.143 1.397) (layer F.Fab) @@ -8024,11 +8876,11 @@ (at 88.4467 81.294 180) (descr "RESISTOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D571) - (fp_text reference R34 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference R34 (at -1.1772 0.6236) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "53.6K 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -8042,20 +8894,20 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 188 "Net-(R34-Pad2)") (solder_mask_margin 0.0508)) + (net 174 "Net-(R34-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5DF986EF) (at 86.2877 81.294 180) (descr "RESISTOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D5CB) - (fp_text reference R35 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (fp_text reference R35 (at -0.8089 0.6236) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_text value "10k 1%" (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right bottom)) ) (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) @@ -8071,15 +8923,15 @@ (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 188 "Net-(R34-Pad2)") (solder_mask_margin 0.0508)) + (net 174 "Net-(R34-Pad2)") (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66DA9D) (at 91.3677 89.803) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D4FC17D/5D42DBCD) - (fp_text reference C22 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text reference C22 (at -0.1182 -2.046) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) (fp_text value "22uF, 10V" (at -0.889 2.286) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) @@ -8100,7 +8952,7 @@ (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 1 0) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) @@ -8109,42 +8961,42 @@ (at 87.4307 89.803) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D4FC17D/5D43058C) - (fp_text reference C23 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text reference C23 (at -2.2772 1.0147 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_text value "10uF, 35V" (at -0.889 2.286) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) (pad 2 smd rect (at 1 0) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5D66DACE) (at 83.8747 84.596) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D659) - (fp_text reference C24 (at -1.016 -0.762) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference C24 (at -1.312 -0.4585) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 2.7nF (at -1.143 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_line (start 1.016 0.4445) (end 0.508 0.4445) (layer F.SilkS) (width 0.127)) (fp_line (start 1.016 -0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) @@ -8166,7 +9018,7 @@ (module LibreRouter_MegaBoard:RT8250-SOP8 (layer Top) (tedit 0) (tstamp 5D66DADE) (at 91.1137 86.882 180) (path /5D0328DE/5D4FC17D/5D42D1B4) - (fp_text reference U3 (at -1.27 -1.27) (layer F.SilkS) + (fp_text reference U3 (at -1.27 6.0592) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right top)) ) (fp_text value RT7272 (at -1.27 6.35) (layer F.Fab) @@ -8183,81 +9035,81 @@ (pad 4 smd roundrect (at -1.2192 3.81 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 1 GND) (solder_mask_margin 0.0508)) (pad 3 smd roundrect (at -1.2192 2.54 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 97 /POWER_EN_5V) (solder_mask_margin 0.0508)) + (net 95 /POWER_EN_5V) (solder_mask_margin 0.0508)) (pad 2 smd roundrect (at -1.2192 1.27 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 22 "Net-(C21-Pad2)") (solder_mask_margin 0.0508)) (pad 1 smd roundrect (at -1.2192 0 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 23 "Net-(C21-Pad1)") (solder_mask_margin 0.0508)) (pad 5 smd roundrect (at 4.5466 3.81 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 188 "Net-(R34-Pad2)") (solder_mask_margin 0.0508)) + (net 174 "Net-(R34-Pad2)") (solder_mask_margin 0.0508)) (pad 6 smd roundrect (at 4.5466 2.54 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 24 "Net-(C24-Pad2)") (solder_mask_margin 0.0508)) (pad 7 smd roundrect (at 4.5466 1.27 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) (net 26 "Net-(R36-Pad1)") (solder_mask_margin 0.0508)) (pad 8 smd roundrect (at 4.5466 0 270) (size 0.6096 1.8796) (layers Top F.Paste F.Mask) (roundrect_rratio 0.39) - (net 81 /+12V) (solder_mask_margin 0.0508)) + (net 297 /VCC) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66DAF0) (at 83.8747 85.612 180) (descr "RESISTOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D2DE) - (fp_text reference R36 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference R36 (at 1.439 0.2807) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 180k (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (pad 1 smd rect (at -0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 26 "Net-(R36-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0 180) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:R0402 (layer Top) (tedit 0) (tstamp 5D66DB00) (at 83.8747 83.58) (descr "RESISTOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D605) - (fp_text reference R38 (at -1.905 -0.635) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify right top)) + (fp_text reference R38 (at -1.312 -0.649) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify right top)) ) (fp_text value 24k (at -1.905 1.397) (layer F.Fab) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) - (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) - (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) - (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) + (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.092 0.483) (end -1.092 0.483) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.092 0.483) (end -1.092 -0.483) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -0.508 -0.4445) (end -1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 -0.4445) (end -1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.016 0.4445) (end -0.508 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 0.508 0.4445) (end 1.016 0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 0.4445) (end 1.016 -0.4445) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.016 -0.4445) (end 0.508 -0.4445) (layer F.SilkS) (width 0.127)) (pad 1 smd rect (at -0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 25 "Net-(C24-Pad1)") (solder_mask_margin 0.0508)) + (pad 2 smd rect (at 0.4572 0) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) + (net 1 GND) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0805 (layer Top) (tedit 0) (tstamp 5D66DB10) (at 91.3677 91.962) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D4FC17D/5D42DAC0) - (fp_text reference C25 (at -1.651 -1.143) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left top)) + (fp_text reference C25 (at -1.0707 1.3322) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left top)) ) (fp_text value "22uF, 10V" (at -0.889 2.286) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left top)) @@ -8278,7 +9130,7 @@ (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 1 0) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) @@ -8287,31 +9139,31 @@ (at 87.4307 91.962) (descr "CAPACITOR

\nchip") (path /5D0328DE/5D4FC17D/5D42D229) - (fp_text reference C26 (at -1.651 -1.143 90) (layer F.SilkS) - (effects (font (size 0.77216 0.77216) (thickness 0.061772)) (justify left bottom)) + (fp_text reference C26 (at -2.2645 1.1417 90) (layer F.SilkS) + (effects (font (size 0.77216 0.77216) (thickness 0.0889)) (justify left bottom)) ) (fp_text value "10uF, 35V" (at -0.889 2.286) (layer F.Fab) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) ) - (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) - (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) - (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) - (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) - (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) - (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) - (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.973 -0.983) (end 1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start 1.973 0.983) (end -1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -1.973 0.983) (end -1.973 -0.983) (layer Dwgs.User) (width 0.0508)) + (fp_line (start -0.381 -0.66) (end 0.381 -0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start -0.356 0.66) (end 0.381 0.66) (layer F.Fab) (width 0.1016)) + (fp_line (start 1.973 -0.983) (end 1.973 0.983) (layer Dwgs.User) (width 0.0508)) + (fp_poly (pts (xy -1.0922 0.7239) (xy -0.3421 0.7239) (xy -0.3421 -0.7262) (xy -1.0922 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy 0.3556 0.7239) (xy 1.1057 0.7239) (xy 1.1057 -0.7262) (xy 0.3556 -0.7262)) (layer F.Fab) (width 0)) + (fp_poly (pts (xy -0.1001 0.4001) (xy 0.1001 0.4001) (xy 0.1001 -0.4001) (xy -0.1001 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.016 -1.016) (end -1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 -1.016) (end -1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start -1.905 1.016) (end -1.016 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.143 -1.016) (end 1.905 -1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 -1.016) (end 1.905 1.016) (layer F.SilkS) (width 0.127)) + (fp_line (start 1.905 1.016) (end 1.143 1.016) (layer F.SilkS) (width 0.127)) + (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) + (net 297 /VCC) (solder_mask_margin 0.0508)) (pad 2 smd rect (at 1 0) (size 1 1.4) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1 0) (size 1 1.4) (layers Top F.Paste F.Mask) - (net 81 /+12V) (solder_mask_margin 0.0508)) ) (module LibreRouter_MegaBoard:C0402 (layer Top) (tedit 0) (tstamp 5DF8F951) @@ -8336,61 +9188,56 @@ (fp_line (start 1.092 -0.483) (end 1.092 0.483) (layer Dwgs.User) (width 0.0508)) (fp_line (start -1.092 -0.483) (end 1.092 -0.483) (layer Dwgs.User) (width 0.0508)) (pad 2 smd rect (at 0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) - (net 82 /5V_PCIE) (solder_mask_margin 0.0508)) + (net 80 /5V_PCIE) (solder_mask_margin 0.0508)) (pad 1 smd rect (at -0.4572 0 270) (size 0.6096 0.6096) (layers Top F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.0508)) ) - (module LibreRouter_MegaBoard:C1206 (layer Bottom) (tedit 0) (tstamp 5D66DB81) - (at 229.5437 194.451 270) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D6301C9) - (fp_text reference C40 (at -1.27 1.143 90) (layer B.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom mirror)) - ) - (fp_text value "10nF, 2KV" (at -1.27 -2.413 90) (layer B.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right bottom mirror)) - ) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_poly (pts (xy 0.9517 -0.8491) (xy 1.7018 -0.8491) (xy 1.7018 0.8509) (xy 0.9517 0.8509)) (layer B.Fab) (width 0)) - (fp_poly (pts (xy -1.7018 -0.8509) (xy -0.9517 -0.8509) (xy -0.9517 0.8491) (xy -1.7018 0.8491)) (layer B.Fab) (width 0)) - (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer B.Fab) (width 0.1016)) - (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer B.Fab) (width 0.1016)) - (fp_line (start 2.473 0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -2.473 -0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 2.473 -0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -2.473 0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1.4 0 270) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1.4 0 270) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) - (net 88 "Net-(C40-Pad1)") (solder_mask_margin 0.0508)) - ) - - (module LibreRouter_MegaBoard:C1206 (layer Bottom) (tedit 0) (tstamp 5D66DB8F) - (at 220.9077 194.451) - (descr "CAPACITOR

\nchip") - (path /5D032DC8/5D63CAC9) - (fp_text reference C41 (at -1.27 1.143) (layer B.SilkS) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom mirror)) - ) - (fp_text value "10nF, 2KV" (at -1.27 -2.413) (layer B.Fab) - (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify right bottom mirror)) - ) - (fp_poly (pts (xy -0.1999 -0.4001) (xy 0.1999 -0.4001) (xy 0.1999 0.4001) (xy -0.1999 0.4001)) (layer B.Adhes) (width 0)) - (fp_poly (pts (xy 0.9517 -0.8491) (xy 1.7018 -0.8491) (xy 1.7018 0.8509) (xy 0.9517 0.8509)) (layer B.Fab) (width 0)) - (fp_poly (pts (xy -1.7018 -0.8509) (xy -0.9517 -0.8509) (xy -0.9517 0.8491) (xy -1.7018 0.8491)) (layer B.Fab) (width 0)) - (fp_line (start -0.965 -0.787) (end 0.965 -0.787) (layer B.Fab) (width 0.1016)) - (fp_line (start -0.965 0.787) (end 0.965 0.787) (layer B.Fab) (width 0.1016)) - (fp_line (start 2.473 0.983) (end 2.473 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -2.473 -0.983) (end -2.473 0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start 2.473 -0.983) (end -2.473 -0.983) (layer Dwgs.User) (width 0.0508)) - (fp_line (start -2.473 0.983) (end 2.473 0.983) (layer Dwgs.User) (width 0.0508)) - (pad 2 smd rect (at 1.4 0) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) - (net 1 GND) (solder_mask_margin 0.0508)) - (pad 1 smd rect (at -1.4 0) (size 1.6 1.8) (layers Bottom B.Paste B.Mask) - (net 89 "Net-(C41-Pad1)") (solder_mask_margin 0.0508)) - ) - + (gr_text "LibreRouter.org\nMegaBoard v1.4.0\n" (at 225.57 217.97) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text 1 (at 114.681 95.631) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (gr_text 1 (at 93.3958 162.5346) (layer F.SilkS) + (effects (font (size 1.1938 1.1938) (thickness 0.127))) + ) + (gr_line (start 197.8697 163.6025) (end 197.8697 164.7455) (layer Dwgs.User) (width 0.15) (tstamp CA31E990)) + (gr_line (start 197.8697 161.3165) (end 197.8697 162.4595) (layer Dwgs.User) (width 0.15) (tstamp CA31FCD0)) + (gr_line (start 197.8697 159.0305) (end 197.8697 160.1735) (layer Dwgs.User) (width 0.15) (tstamp CA321010)) + (gr_line (start 197.8697 156.7445) (end 197.8697 157.8875) (layer Dwgs.User) (width 0.15) (tstamp CA322350)) + (gr_line (start 197.8697 154.4585) (end 197.8697 155.6015) (layer Dwgs.User) (width 0.15) (tstamp CA323690)) + (gr_line (start 197.8697 152.1725) (end 197.8697 153.3155) (layer Dwgs.User) (width 0.15) (tstamp CA3249D0)) + (gr_line (start 197.8697 149.8865) (end 197.8697 151.0295) (layer Dwgs.User) (width 0.15) (tstamp CA325D10)) + (gr_line (start 197.8697 147.6005) (end 197.8697 148.7435) (layer Dwgs.User) (width 0.15) (tstamp CA327050)) + (gr_line (start 163.9607 118.5175) (end 163.9607 119.4065) (layer Dwgs.User) (width 0.15) (tstamp CD3759F0)) + (gr_line (start 163.9607 119.4065) (end 164.2147 119.1525) (layer Dwgs.User) (width 0.15) (tstamp CD375ED0)) + (gr_line (start 164.2147 119.1525) (end 163.7067 119.1525) (layer Dwgs.User) (width 0.15) (tstamp CD3763B0)) + (gr_line (start 163.7067 119.1525) (end 163.9607 119.4065) (layer Dwgs.User) (width 0.15) (tstamp CD376890)) + (gr_line (start 165.4847 184.621) (end 150.1177 184.621) (layer Dwgs.User) (width 0.15) (tstamp CD384210)) + (gr_line (start 195.5837 133.8845) (end 197.8697 133.8845) (layer Dwgs.User) (width 0.15) (tstamp CA32DF00)) + (gr_line (start 197.8697 133.8845) (end 197.8697 135.0275) (layer Dwgs.User) (width 0.15) (tstamp CA32E3D0)) + (gr_line (start 197.8697 135.0275) (end 195.5837 135.0275) (layer Dwgs.User) (width 0.15) (tstamp CA32E8B0)) + (gr_line (start 195.5837 135.0275) (end 195.5837 133.8845) (layer Dwgs.User) (width 0.15) (tstamp CA32ED80)) + (gr_line (start 195.5837 131.5985) (end 197.8697 131.5985) (layer Dwgs.User) (width 0.15) (tstamp CA32F240)) + (gr_line (start 197.8697 131.5985) (end 197.8697 132.7415) (layer Dwgs.User) (width 0.15) (tstamp CA32F710)) + (gr_line (start 197.8697 132.7415) (end 195.5837 132.7415) (layer Dwgs.User) (width 0.15) (tstamp CA32FBF0)) + (gr_line (start 195.5837 132.7415) (end 195.5837 131.5985) (layer Dwgs.User) (width 0.15) (tstamp CA3300C0)) + (gr_line (start 195.5837 129.3125) (end 197.8697 129.3125) (layer Dwgs.User) (width 0.15) (tstamp CA330580)) + (gr_line (start 197.8697 129.3125) (end 197.8697 130.4555) (layer Dwgs.User) (width 0.15) (tstamp CA330A50)) + (gr_line (start 197.8697 130.4555) (end 195.5837 130.4555) (layer Dwgs.User) (width 0.15) (tstamp CA330F30)) + (gr_line (start 195.5837 130.4555) (end 195.5837 129.3125) (layer Dwgs.User) (width 0.15) (tstamp CA331400)) + (gr_line (start 195.5837 127.0265) (end 197.8697 127.0265) (layer Dwgs.User) (width 0.15) (tstamp CA3318C0)) + (gr_line (start 197.8697 127.0265) (end 197.8697 128.1695) (layer Dwgs.User) (width 0.15) (tstamp CA331D90)) + (gr_line (start 197.8697 128.1695) (end 195.5837 128.1695) (layer Dwgs.User) (width 0.15) (tstamp CA332270)) + (gr_line (start 195.5837 128.1695) (end 195.5837 127.0265) (layer Dwgs.User) (width 0.15) (tstamp CA332740)) + (gr_line (start 195.5837 124.7405) (end 197.8697 124.7405) (layer Dwgs.User) (width 0.15) (tstamp CA332C00)) + (gr_line (start 197.8697 124.7405) (end 197.8697 125.8835) (layer Dwgs.User) (width 0.15) (tstamp CA3330D0)) + (gr_line (start 197.8697 125.8835) (end 195.5837 125.8835) (layer Dwgs.User) (width 0.15) (tstamp CA3335B0)) + (gr_line (start 195.5837 125.8835) (end 195.5837 124.7405) (layer Dwgs.User) (width 0.15) (tstamp CA333A80)) + (gr_text IO20 (at 104.5757 169.94) (layer F.Fab) (tstamp CAAA5AE0) + (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) + ) (gr_line (start 134.926491 145.221281) (end 124.926491 145.221281) (layer Dwgs.User) (width 0.15) (tstamp CD39F3A0)) (gr_line (start 169.6122 90.768) (end 170.7552 90.768) (layer Dwgs.User) (width 0.15) (tstamp CA96EF50)) (gr_line (start 167.3262 90.768) (end 168.4692 90.768) (layer Dwgs.User) (width 0.15) (tstamp CA970290)) @@ -8405,7 +9252,7 @@ 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(xy 104.328761 61.324147) - (xy 104.351999 61.400754) (xy 104.359749 61.415254) (xy 104.36088 61.426736) (xy 104.368107 61.450561) (xy 104.379843 61.472517) - (xy 104.395637 61.491763) (xy 106.234597 63.330723) (xy 106.253843 63.346517) (xy 106.275799 63.358253) (xy 106.299624 63.36548) - (xy 106.3244 63.36792) (xy 114.196594 63.36792) (xy 120.900557 70.071883) (xy 120.919803 70.087677) (xy 120.941759 70.099413) - (xy 120.965584 70.10664) (xy 120.99036 70.10908) (xy 125.01372 70.10908) (xy 125.01372 73.312754) (xy 122.460117 75.866357) - (xy 122.444323 75.885603) (xy 122.432587 75.907559) (xy 122.42536 75.931384) (xy 122.42292 75.95616) (xy 122.42292 80.12176) - (xy 120.529886 80.12176) (xy 119.07012 78.661994) (xy 119.07012 71.1454) (xy 119.06768 71.120624) (xy 119.060453 71.096799) - (xy 119.048717 71.074843) (xy 119.032923 71.055597) (xy 113.180763 65.203437) (xy 113.161517 65.187643) (xy 113.139561 65.175907) - (xy 113.115736 65.16868) (xy 113.09096 65.16624) (xy 106.30408 65.16624) (xy 106.279304 65.16868) (xy 106.255479 65.175907) - (xy 106.233523 65.187643) (xy 106.214277 65.203437) (xy 105.15516 66.262554) (xy 105.130603 66.272726) (xy 105.05156 66.32554) - (xy 104.98434 66.39276) (xy 104.931526 66.471803) (xy 104.921354 66.49636) (xy 104.227997 67.189717) (xy 104.212203 67.208963) - (xy 104.200467 67.230919) (xy 104.19324 67.254744) (xy 104.1908 67.27952) (xy 104.1908 72.81164) (xy 104.19324 72.836416) - (xy 104.200467 72.860241) (xy 104.212203 72.882197) (xy 104.227997 72.901443) (xy 105.147477 73.820923) (xy 105.166723 73.836717) - (xy 105.188679 73.848453) (xy 105.212504 73.85568) (xy 105.23728 73.85812) (xy 108.92028 73.85812) (xy 108.92028 75.29576) - (xy 104.390726 75.29576) (xy 103.10876 74.013794) (xy 103.10876 53.95976) (xy 104.35844 53.95976) + (xy 95.51924 120.39854) (xy 94.897288 120.39854) (xy 94.48292 119.984172) (xy 94.48292 119.765763) (xy 94.48464 119.7483) + (xy 94.48464 119.1387) (xy 94.48292 119.121237) (xy 94.48292 118.80342) (xy 94.479016 118.763778) (xy 94.467452 118.725659) + (xy 94.438776 118.676962) (xy 94.129372 118.2878) (xy 95.51924 118.2878) ) ) ) diff --git a/designs/mega_board/LibreRouter_MegaBoard.pretty/C1206.kicad_mod b/designs/mega_board/LibreRouter_MegaBoard.pretty/C1206.kicad_mod index 6e4d498..ed3f7cc 100644 --- a/designs/mega_board/LibreRouter_MegaBoard.pretty/C1206.kicad_mod +++ b/designs/mega_board/LibreRouter_MegaBoard.pretty/C1206.kicad_mod @@ -1,4 +1,4 @@ -(module C1206 (layer F.Cu) (tedit 0) +(module C1206 (layer F.Cu) (tedit 5E693595) (descr "CAPACITOR

\nchip") (fp_text reference C41 (at -1.27 -1.143 -180) (layer F.SilkS) (effects (font (size 1.2065 1.2065) (thickness 0.09652)) (justify left bottom)) @@ -15,6 +15,13 @@ (fp_poly (pts (xy -1.7018 0.8509) (xy -0.9517 0.8509) (xy -0.9517 -0.8491) (xy -1.7018 -0.8491)) (layer F.Fab) (width 0)) (fp_poly (pts (xy 0.9517 0.8491) (xy 1.7018 0.8491) (xy 1.7018 -0.8509) (xy 0.9517 -0.8509)) (layer F.Fab) (width 0)) (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) + (fp_line (start -1.75 -1) (end -2.5 -1) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -1) (end -2.5 1) (layer F.SilkS) (width 0.127)) + (fp_line (start -2.5 1) (end -1.75 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2 -1) (end 2.5 -1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.5 -1) (end 2.5 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.5 1) (end 1.75 1) (layer F.SilkS) (width 0.12)) + (fp_line (start 2 -1) (end 1.75 -1) (layer F.SilkS) (width 0.12)) (pad 1 smd rect (at -1.4 0) (size 1.6 1.8) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.0508)) (pad 2 smd rect (at 1.4 0) (size 1.6 1.8) (layers F.Cu F.Paste F.Mask) diff --git a/designs/mega_board/LibreRouter_MegaBoard.pretty/CUI_PJ-002A_noedge.kicad_mod b/designs/mega_board/LibreRouter_MegaBoard.pretty/CUI_PJ-002A_noedge.kicad_mod new file mode 100644 index 0000000..2463446 --- /dev/null +++ b/designs/mega_board/LibreRouter_MegaBoard.pretty/CUI_PJ-002A_noedge.kicad_mod @@ -0,0 +1,35 @@ +(module CUI_PJ-002A_noedge (layer F.Cu) (tedit 5E68FE4F) + (fp_text reference CUI_PJ-002A (at 1.85153 -6.77062) (layer F.SilkS) + (effects (font (size 1.00083 1.00083) (thickness 0.05))) + ) + (fp_text value VAL** (at 2.48793 5.78184) (layer F.SilkS) + (effects (font (size 1.00118 1.00118) (thickness 0.05))) + ) + (fp_line (start 0.5 -1.75) (end 0.5 1.75) (layer F.Mask) (width 0.0001)) + (fp_line (start -0.7 -4.5) (end 13.7 -4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start 13.7 -4.5) (end 13.7 4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start 13.7 4.5) (end -0.7 4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start -0.7 4.5) (end -0.7 -4.5) (layer Eco2.User) (width 0.127)) + (fp_line (start 13.7 -4.5) (end 13.7 4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start 13.7 4.5) (end -0.7 4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7 -4.5) (end 0.45 -4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7 4.5) (end -0.7 2.65) (layer F.SilkS) (width 0.127)) + (fp_line (start 5.55 -4.5) (end 13.7 -4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -0.7 -2.55) (end -0.7 -4.5) (layer F.SilkS) (width 0.127)) + (fp_line (start -1 -4.75) (end 0.45 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 0.45 -4.75) (end 0.45 -6.1) (layer Eco1.User) (width 0.05)) + (fp_line (start 0.45 -6.1) (end 5.55 -6.1) (layer Eco1.User) (width 0.05)) + (fp_line (start 5.55 -6.1) (end 5.55 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 5.55 -4.75) (end 14 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 14 -4.75) (end 14 4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start 14 4.75) (end -1 4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start -1 4.75) (end -1 2.35) (layer Eco1.User) (width 0.05)) + (fp_circle (center -2 0) (end -1.8 0) (layer F.SilkS) (width 0.4)) + (fp_line (start -1 -2.25) (end -1 -4.75) (layer Eco1.User) (width 0.05)) + (fp_line (start -1 -2.25) (end -1.55 -2.25) (layer Eco1.User) (width 0.05)) + (fp_line (start -1.55 -2.25) (end -1.55 2.35) (layer Eco1.User) (width 0.05)) + (fp_line (start -1.55 2.35) (end -1 2.35) (layer Eco1.User) (width 0.05)) + (pad 1 thru_hole oval (at 0 0 90) (size 5 2.5) (drill oval 3.7 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 6 0 90) (size 4.5 2.25) (drill oval 3.5 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 3 -4.7 180) (size 4.5 2.25) (drill oval 3.5 1) (layers *.Cu *.Mask)) +) diff --git a/designs/mega_board/LibreRouter_MegaBoard.pretty/EG1213.kicad_mod b/designs/mega_board/LibreRouter_MegaBoard.pretty/EG1213.kicad_mod new file mode 100644 index 0000000..9ac4c29 --- /dev/null +++ b/designs/mega_board/LibreRouter_MegaBoard.pretty/EG1213.kicad_mod @@ -0,0 +1,20 @@ +(module EG1213 (layer F.Cu) (tedit 5E162B36) + (fp_text reference REF** (at 7.5692 -2.0828) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value EG1213 (at 0 -2.794) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -5 -1.9) (end 5 -1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 -1.9) (end 5 1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 1.9) (end -5 1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start -5 1.9) (end -5 -1.9) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.5 1.9) (end -2.5 6.9) (layer F.Fab) (width 0.15)) + (fp_line (start -2.5 6.9) (end 2.5 6.9) (layer F.Fab) (width 0.15)) + (fp_line (start 2.5 6.9) (end 2.5 1.9) (layer F.Fab) (width 0.15)) + (pad 1 thru_hole circle (at -2 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)) + (pad 2 thru_hole circle (at 0 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)) + (pad 3 thru_hole circle (at 2 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)) + (pad S thru_hole circle (at -4.85 0) (size 1.4 1.4) (drill 1.4) (layers *.Cu *.Mask)) + (pad S thru_hole circle (at 4.85 0) (size 1.4 1.4) (drill 1.4) (layers *.Cu *.Mask)) +) diff --git a/designs/mega_board/LibreRouter_MegaBoard.pro b/designs/mega_board/LibreRouter_MegaBoard.pro index 79e5d16..0f1bb4c 100644 --- a/designs/mega_board/LibreRouter_MegaBoard.pro +++ b/designs/mega_board/LibreRouter_MegaBoard.pro @@ -1,4 +1,4 @@ -update=Mon 16 Dec 2019 06:45:46 PM CET +update=Wed 08 Jan 2020 08:14:28 PM CET version=1 last_client=kicad [general] @@ -46,8 +46,10 @@ TrackWidth5=0.508 TrackWidth6=0.6 TrackWidth7=0.6096 TrackWidth8=0.8128 -TrackWidth9=1.6764 -TrackWidth10=2.54 +TrackWidth9=1.016 +TrackWidth10=1.6764 +TrackWidth11=2.1844 +TrackWidth12=2.54 ViaDiameter1=0.8 ViaDrill1=0.4 dPairWidth1=0.2 diff --git a/designs/mega_board/LibreRouter_MegaBoard.sch b/designs/mega_board/LibreRouter_MegaBoard.sch index 95ac011..e4000e7 100644 --- a/designs/mega_board/LibreRouter_MegaBoard.sch +++ b/designs/mega_board/LibreRouter_MegaBoard.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A2 23386 16535 @@ -20,72 +19,76 @@ U 5D032850 F0 "Core9558" 50 F1 "Core9558.sch" 50 F2 "3V3" I L 8650 1200 50 -F3 "S17_P3_TRX0+" I R 13550 10150 50 -F4 "S17_P3_TRX0-" I R 13550 10050 50 -F5 "S17_P3_TRX1+" I R 13550 10350 50 -F6 "S17_P3_TRX1-" I R 13550 10250 50 -F7 "S17_P3_TRX2+" I R 13550 10550 50 -F8 "S17_P3_TRX2-" I R 13550 10450 50 -F9 "S17_P3_TRX3+" I R 13550 10750 50 -F10 "S17_P3_TRX3-" I R 13550 10650 50 -F11 "S17_P4_TRX0+" I R 13550 8850 50 -F12 "S17_P4_TRX0-" I R 13550 8750 50 -F13 "S17_P4_TRX1+" I R 13550 9050 50 -F14 "S17_P4_TRX1-" I R 13550 8950 50 -F15 "S17_P4_TRX2+" I R 13550 9250 50 -F16 "S17_P4_TRX2-" I R 13550 9150 50 -F17 "S17_P4_TRX3+" I R 13550 9450 50 -F18 "S17_P4_TRX3-" I R 13550 9350 50 +F3 "S17_P3_TRX0+" I R 13550 8600 50 +F4 "S17_P3_TRX0-" I R 13550 8500 50 +F5 "S17_P3_TRX1+" I R 13550 8800 50 +F6 "S17_P3_TRX1-" I R 13550 8700 50 +F7 "S17_P3_TRX2+" I R 13550 9000 50 +F8 "S17_P3_TRX2-" I R 13550 8900 50 +F9 "S17_P3_TRX3+" I R 13550 9200 50 +F10 "S17_P3_TRX3-" I R 13550 9100 50 +F11 "S17_P4_TRX0+" I R 13550 7300 50 +F12 "S17_P4_TRX0-" I R 13550 7200 50 +F13 "S17_P4_TRX1+" I R 13550 7500 50 +F14 "S17_P4_TRX1-" I R 13550 7400 50 +F15 "S17_P4_TRX2+" I R 13550 7700 50 +F16 "S17_P4_TRX2-" I R 13550 7600 50 +F17 "S17_P4_TRX3+" I R 13550 7900 50 +F18 "S17_P4_TRX3-" I R 13550 7800 50 F19 "5V_1" I L 8650 1100 50 F20 "S17_LEDN_3" I L 8650 3150 50 F21 "S17_LEDN1000_3" I L 8650 2950 50 F22 "S17_LEDN_4" I L 8650 3050 50 F23 "S17_LEDN1000_4" I L 8650 2850 50 -F24 "SPI_CS_L" I L 8650 12400 50 -F25 "SPI_CLK" I L 8650 12500 50 -F26 "SPI_MOSI" I L 8650 12700 50 -F27 "SPI_MISO" I L 8650 12600 50 -F28 "PCIE1_TX_P_CONN" I R 13550 6650 50 -F29 "PCIE1_TX_N_CONN" I R 13550 6550 50 -F30 "PCIE1_RX_P_CONN" I R 13550 6450 50 -F31 "PCIE1_RX_N_CONN" I R 13550 6350 50 -F32 "PCIE1_CLK_P_CONN" I R 13550 6250 50 -F33 "PCIE1_CLK_N_CONN" I R 13550 6150 50 -F34 "PCIE0_CLK_P_CONN" I R 13550 2750 50 -F35 "PCIE0_CLK_N_CONN" I R 13550 2650 50 -F36 "PCIE0_RX_P_CONN" I R 13550 2950 50 -F37 "PCIE0_RX_N_CONN" I R 13550 2850 50 -F38 "PCIE0_TX_P_CONN" I R 13550 3150 50 -F39 "PCIE0_TX_N_CONN" I R 13550 3050 50 -F40 "PCIE1_RST_L" I R 13550 6050 50 -F41 "PCIE0_RST_L" I R 13550 2550 50 -F42 "GPIO23" I L 8650 2150 50 -F43 "USB1_DP" I R 13550 12600 50 -F44 "USB1_DM" I R 13550 12700 50 -F45 "USB0_DP" I R 13550 3450 50 -F46 "USB0_DM" I R 13550 3350 50 -F47 "GPIO22" I L 8650 2750 50 -F48 "GPIO21" I L 8650 9150 50 -F49 "GPIO20" I L 8650 2650 50 -F50 "GPIO19" I L 8650 9050 50 -F51 "GPIO18" I L 8650 8950 50 -F52 "GPIO17" I L 8650 4650 50 -F53 "GPIO16" I L 8650 10400 50 -F54 "GPIO15" I L 8650 10300 50 -F55 "GPIO14" I L 8650 8850 50 -F56 "GPIO13" I L 8650 10500 50 -F57 "GPIO12" I L 8650 8750 50 -F58 "COM_A_2G" I L 8650 11050 50 -F59 "COM_B_2G" I L 8650 11250 50 -F60 "UART_SIN" I L 8650 6400 50 -F61 "UART_SOUT" I L 8650 6500 50 -F62 "RST_B" I L 8650 12300 50 -F63 "GPIO4" I L 8650 8650 50 -F64 "5V0_2GPA" I L 8650 1000 50 -F65 "GPIO0-EJTAG_TCK" I L 8650 8050 50 -F66 "GPIO1-EJTAG_TDI" I L 8650 8150 50 -F67 "GPIO2-EJTAG_TDO" I L 8650 8250 50 -F68 "GPIO3-EJTAG_TMS" I L 8650 8350 50 +F24 "PCIE1_TX_P_CONN" I R 13550 5500 50 +F25 "PCIE1_TX_N_CONN" I R 13550 5400 50 +F26 "PCIE1_RX_P_CONN" I R 13550 5300 50 +F27 "PCIE1_RX_N_CONN" I R 13550 5200 50 +F28 "PCIE1_CLK_P_CONN" I R 13550 5100 50 +F29 "PCIE1_CLK_N_CONN" I R 13550 5000 50 +F30 "PCIE0_CLK_P_CONN" I R 13550 2750 50 +F31 "PCIE0_CLK_N_CONN" I R 13550 2650 50 +F32 "PCIE0_RX_P_CONN" I R 13550 2950 50 +F33 "PCIE0_RX_N_CONN" I R 13550 2850 50 +F34 "PCIE0_TX_P_CONN" I R 13550 3150 50 +F35 "PCIE0_TX_N_CONN" I R 13550 3050 50 +F36 "PCIE1_RST_L" I R 13550 4900 50 +F37 "PCIE0_RST_L" I R 13550 2550 50 +F38 "GPIO23" I L 8650 2150 50 +F39 "USB1_DP" I R 13550 12600 50 +F40 "USB1_DM" I R 13550 12700 50 +F41 "USB0_DP" I R 13550 3450 50 +F42 "USB0_DM" I R 13550 3350 50 +F43 "GPIO22" I L 8650 2750 50 +F44 "GPIO21" I L 8650 9150 50 +F45 "GPIO20" I L 8650 2650 50 +F46 "GPIO19" I L 8650 9050 50 +F47 "GPIO18" I L 8650 8950 50 +F48 "GPIO17" I L 8650 4650 50 +F49 "GPIO16" I L 8650 10400 50 +F50 "GPIO15" I L 8650 10300 50 +F51 "GPIO14" I L 8650 8850 50 +F52 "GPIO13" I L 8650 10500 50 +F53 "GPIO12" I L 8650 8750 50 +F54 "COM_A_2G" I L 8650 11050 50 +F55 "COM_B_2G" I L 8650 11250 50 +F56 "UART_SIN" I L 8650 6400 50 +F57 "UART_SOUT" I L 8650 6500 50 +F58 "RST_B" I L 8650 12300 50 +F59 "GPIO4" I L 8650 8650 50 +F60 "5V0_2GPA" I L 8650 1000 50 +F61 "GPIO0-EJTAG_TCK" I L 8650 8050 50 +F62 "GPIO1-EJTAG_TDI" I L 8650 8150 50 +F63 "GPIO2-EJTAG_TDO" I L 8650 8250 50 +F64 "GPIO3-EJTAG_TMS" I L 8650 8350 50 +F65 "S17_P0_TRX0+" I R 13550 10800 50 +F66 "S17_P0_TRX0-" I R 13550 10700 50 +F67 "S17_P0_TRX1+" I R 13550 11000 50 +F68 "S17_P0_TRX1-" I R 13550 10900 50 +F69 "S17_P0_TRX2+" I R 13550 11200 50 +F70 "S17_P0_TRX2-" I R 13550 11100 50 +F71 "S17_P0_TRX3+" I R 13550 11400 50 +F72 "S17_P0_TRX3-" I R 13550 11300 50 $EndSheet $Sheet S 16250 12200 900 1850 @@ -116,12 +119,13 @@ F5 "3.3V_1_ENABLE" I L 3800 15500 50 F6 "5V_0_ENABLE" I L 3800 15600 50 F7 "5V_1_ENABLE" I L 3800 15700 50 F8 "5V_2_ENABLE" I L 3800 15800 50 -F9 "12V_OUT" B R 5450 15250 50 -F10 "5V_0" B R 5450 14850 50 -F11 "5V_1" B R 5450 14950 50 -F12 "5V_2" B R 5450 15050 50 -F13 "12V_IN" B L 3800 14450 50 -F14 "12V_POE" B L 3800 15200 50 +F9 "5V_0" B R 5450 14850 50 +F10 "5V_1" B R 5450 14950 50 +F11 "5V_2" B R 5450 15050 50 +F12 "POE_A" B L 3800 14900 50 +F13 "POE_B" B L 3800 15000 50 +F14 "VCC_OUT" B R 5450 15250 50 +F15 "VCC_IN" B L 3800 14450 50 $EndSheet $Sheet S 3400 12000 1200 950 @@ -237,111 +241,113 @@ NoConn ~ 17400 12600 NoConn ~ 21050 13300 NoConn ~ 19350 13950 Wire Wire Line - 18050 8450 18050 8750 + 18050 6900 18050 7200 Wire Wire Line - 18050 8750 17750 8750 + 18050 7200 17750 7200 Wire Wire Line - 17750 8850 18150 8850 + 17750 7300 18150 7300 Wire Wire Line - 18150 8850 18150 8550 + 18150 7300 18150 7000 Wire Wire Line - 18150 8550 20000 8550 + 18150 7000 20000 7000 Wire Wire Line - 17750 9050 18250 9050 + 17750 7500 18250 7500 Wire Wire Line - 18250 9050 18250 8650 + 18250 7500 18250 7100 Wire Wire Line - 17750 9150 18350 9150 + 17750 7600 18350 7600 Wire Wire Line - 18350 9150 18350 8750 + 18350 7600 18350 7200 Wire Wire Line - 17750 9250 18450 9250 + 17750 7700 18450 7700 Wire Wire Line - 18450 9250 18450 8850 + 18450 7700 18450 7300 Wire Wire Line - 17750 9450 18550 9450 + 17750 7900 18550 7900 Wire Wire Line - 18550 9450 18550 9050 + 18550 7900 18550 7500 Wire Wire Line - 17750 9350 18650 9350 + 17750 7800 18650 7800 Wire Wire Line - 18650 9350 18650 9150 + 18650 7800 18650 7600 Wire Wire Line - 18050 9750 18050 10050 + 18050 8200 18050 8500 Wire Wire Line - 18050 10050 17750 10050 + 18050 8500 17750 8500 Wire Wire Line - 17750 10150 18150 10150 + 17750 8600 18150 8600 Wire Wire Line - 18150 10150 18150 9850 + 18150 8600 18150 8300 Wire Wire Line - 17750 10350 18250 10350 + 17750 8800 18250 8800 Wire Wire Line - 18250 10350 18250 9950 + 18250 8800 18250 8400 Wire Wire Line - 17750 10450 18350 10450 + 17750 8900 18350 8900 Wire Wire Line - 18350 10450 18350 10050 + 18350 8900 18350 8500 Wire Wire Line - 17750 10550 18450 10550 + 17750 9000 18450 9000 Wire Wire Line - 18450 10550 18450 10150 + 18450 9000 18450 8600 Wire Wire Line - 17750 10750 18550 10750 + 17750 9200 18550 9200 Wire Wire Line - 18550 10750 18550 10350 + 18550 9200 18550 8800 Wire Wire Line - 17750 10650 18650 10650 + 17750 9100 18650 9100 Wire Wire Line - 18650 10650 18650 10450 + 18650 9100 18650 8900 $Sheet -S 16250 8650 1500 2400 +S 16250 7100 1500 3000 U 5D032DC8 F0 "ethernet_frontend" 50 F1 "ethernet_frontend.sch" 50 -F2 "AM_TRX0_N" B R 17750 8750 50 -F3 "AM_TRX0_P" B R 17750 8850 50 -F4 "AM_TRX1_N" B R 17750 8950 50 -F5 "AM_TRX1_P" B R 17750 9050 50 -F6 "AM_TRX2_N" B R 17750 9150 50 -F7 "AM_TRX2_P" B R 17750 9250 50 -F8 "AM_TRX3_N" B R 17750 9350 50 -F9 "AM_TRX3_P" B R 17750 9450 50 -F10 "BM_TRX0_N" B R 17750 10050 50 -F11 "BM_TRX0_P" B R 17750 10150 50 -F12 "BM_TRX1_N" B R 17750 10250 50 -F13 "BM_TRX1_P" B R 17750 10350 50 -F14 "BM_TRX2_N" B R 17750 10450 50 -F15 "BM_TRX2_P" B R 17750 10550 50 -F16 "BM_TRX3_N" B R 17750 10650 50 -F17 "BM_TRX3_P" B R 17750 10750 50 -F18 "BT_TRX0_N" B L 16250 10050 50 -F19 "BT_TRX0_P" B L 16250 10150 50 -F20 "BT_TRX1_N" B L 16250 10250 50 -F21 "BT_TRX1_P" B L 16250 10350 50 -F22 "BT_TRX2_N" B L 16250 10450 50 -F23 "BT_TRX2_P" B L 16250 10550 50 -F24 "BT_TRX3_N" B L 16250 10650 50 -F25 "BT_TRX3_P" B L 16250 10750 50 -F26 "AT_TRX0_N" B L 16250 8750 50 -F27 "AT_TRX0_P" B L 16250 8850 50 -F28 "AT_TRX1_N" B L 16250 8950 50 -F29 "AT_TRX1_P" B L 16250 9050 50 -F30 "AT_TRX2_N" B L 16250 9150 50 -F31 "AT_TRX2_P" B L 16250 9250 50 -F32 "AT_TRX3_N" B L 16250 9350 50 -F33 "AT_TRX3_P" B L 16250 9450 50 -F34 "POE_INJECTION_EN" I L 16250 9600 50 -F35 "POE_12V" O R 17750 10900 50 -F36 "POE_INJECTION" I L 16250 9750 50 -F37 "DISCHARGE" I L 16250 10950 50 +F2 "AM_TRX0_N" B R 17750 7200 50 +F3 "AM_TRX0_P" B R 17750 7300 50 +F4 "AM_TRX1_N" B R 17750 7400 50 +F5 "AM_TRX1_P" B R 17750 7500 50 +F6 "AM_TRX2_N" B R 17750 7600 50 +F7 "AM_TRX2_P" B R 17750 7700 50 +F8 "AM_TRX3_N" B R 17750 7800 50 +F9 "AM_TRX3_P" B R 17750 7900 50 +F10 "BM_TRX0_N" B R 17750 8500 50 +F11 "BM_TRX0_P" B R 17750 8600 50 +F12 "BM_TRX1_N" B R 17750 8700 50 +F13 "BM_TRX1_P" B R 17750 8800 50 +F14 "BM_TRX2_N" B R 17750 8900 50 +F15 "BM_TRX2_P" B R 17750 9000 50 +F16 "BM_TRX3_N" B R 17750 9100 50 +F17 "BM_TRX3_P" B R 17750 9200 50 +F18 "BT_TRX0_N" B L 16250 8500 50 +F19 "BT_TRX0_P" B L 16250 8600 50 +F20 "BT_TRX1_N" B L 16250 8700 50 +F21 "BT_TRX1_P" B L 16250 8800 50 +F22 "BT_TRX2_N" B L 16250 8900 50 +F23 "BT_TRX2_P" B L 16250 9000 50 +F24 "BT_TRX3_N" B L 16250 9100 50 +F25 "BT_TRX3_P" B L 16250 9200 50 +F26 "AT_TRX0_N" B L 16250 7200 50 +F27 "AT_TRX0_P" B L 16250 7300 50 +F28 "AT_TRX1_N" B L 16250 7400 50 +F29 "AT_TRX1_P" B L 16250 7500 50 +F30 "AT_TRX2_N" B L 16250 7600 50 +F31 "AT_TRX2_P" B L 16250 7700 50 +F32 "AT_TRX3_N" B L 16250 7800 50 +F33 "AT_TRX3_P" B L 16250 7900 50 +F34 "DISCHARGE" I L 16250 9400 50 +F35 "POE_INJECT_SOFT_EN" I R 17750 9800 50 +F36 "POE_A" O R 17750 8050 50 +F37 "POE_INJECT_V" I R 17750 9700 50 +F38 "POE_INJECT_HARD_EN" I R 17750 9900 50 +F39 "POE_B" O R 17750 9350 50 $EndSheet $Comp L sim_card_shielded:SIM_Card SIM_CARD_CON_6MICRO0 U 1 1 5D0C3185 P 21350 2950 -F 0 "SIM_CARD_CON_6MICRO0" H 21700 3550 50 0000 L CNN -F 1 "SIM_Card" H 21550 3400 50 0000 L CNN +F 0 "SIM_CARD_CON_6MICRO0" H 21000 3550 50 0000 L CNN +F 1 "SIM_Card" H 21100 3400 50 0000 L CNN F 2 "LibreRouter_MegaBoard:SIM-MICRO-PUSH" H 21350 3300 50 0001 C CNN F 3 " ~" H 21300 2950 50 0001 C CNN 1 21350 2950 @@ -379,44 +385,44 @@ PCIe_0_TX_N Text Label 14750 3150 0 50 ~ 0 PCIe_0_TX_P $Sheet -S 16250 5500 2050 1600 +S 16250 4350 2050 1600 U 5D1650F5 F0 "sheet5D1650DF" 50 F1 "pcie_daughterboard.sch" 50 -F2 "SIM_VCC" I R 18300 6150 50 -F3 "SIM_RST" I R 18300 6250 50 -F4 "SIM_CLK" I R 18300 6350 50 -F5 "SIM_DATA" I R 18300 6650 50 -F6 "SIM_VPP" I R 18300 6550 50 -F7 "USB_N" I L 16250 6850 50 -F8 "USB_P" I L 16250 6950 50 -F9 "PCIe_CLK_N" I L 16250 6150 50 -F10 "PCIe_CLK_P" I L 16250 6250 50 -F11 "PCIe_RX_N" I L 16250 6350 50 -F12 "PCIe_RX_P" I L 16250 6450 50 -F13 "PCIe_TX_N" I L 16250 6550 50 -F14 "PCIe_TX_P" I L 16250 6650 50 -F15 "3V3" I L 16250 5600 50 -F16 "WAKE#" I R 18300 5650 50 -F17 "LED_WLAN" I R 18300 6050 50 -F18 "PCIe_RST" I L 16250 6050 50 -F19 "DISABLE" I R 18300 5850 50 -F20 "CLKREQ#" I R 18300 5750 50 -F21 "5V" I L 16250 5700 50 +F2 "SIM_VCC" I R 18300 5000 50 +F3 "SIM_RST" I R 18300 5100 50 +F4 "SIM_CLK" I R 18300 5200 50 +F5 "SIM_DATA" I R 18300 5500 50 +F6 "SIM_VPP" I R 18300 5400 50 +F7 "USB_N" I L 16250 5700 50 +F8 "USB_P" I L 16250 5800 50 +F9 "PCIe_CLK_N" I L 16250 5000 50 +F10 "PCIe_CLK_P" I L 16250 5100 50 +F11 "PCIe_RX_N" I L 16250 5200 50 +F12 "PCIe_RX_P" I L 16250 5300 50 +F13 "PCIe_TX_N" I L 16250 5400 50 +F14 "PCIe_TX_P" I L 16250 5500 50 +F15 "3V3" I L 16250 4450 50 +F16 "WAKE#" I R 18300 4500 50 +F17 "LED_WLAN" I R 18300 4900 50 +F18 "PCIe_RST" I L 16250 4900 50 +F19 "DISABLE" I R 18300 4700 50 +F20 "CLKREQ#" I R 18300 4600 50 +F21 "5V" I L 16250 4550 50 $EndSheet -Text Label 14750 6050 0 50 ~ 0 +Text Label 14750 4900 0 50 ~ 0 PCIe_1_RST -Text Label 14750 6150 0 50 ~ 0 +Text Label 14750 5000 0 50 ~ 0 PCIe_1_CLK_N -Text Label 14750 6250 0 50 ~ 0 +Text Label 14750 5100 0 50 ~ 0 PCIe_1_CLK_P -Text Label 14750 6350 0 50 ~ 0 +Text Label 14750 5200 0 50 ~ 0 PCIe_1_RX_N -Text Label 14750 6450 0 50 ~ 0 +Text Label 14750 5300 0 50 ~ 0 PCIe_1_RX_P -Text Label 14750 6550 0 50 ~ 0 +Text Label 14750 5400 0 50 ~ 0 PCIe_1_TX_N -Text Label 14750 6650 0 50 ~ 0 +Text Label 14750 5500 0 50 ~ 0 PCIe_1_TX_P Text Label 5600 14450 0 50 ~ 0 +3V3 @@ -443,32 +449,32 @@ Text Label 15850 2200 0 50 ~ 0 Wire Wire Line 15850 2200 16250 2200 Wire Wire Line - 15750 5600 16250 5600 -Text Label 15850 5700 0 50 ~ 0 + 15750 4450 16250 4450 +Text Label 15850 4550 0 50 ~ 0 5V_PCIE Wire Wire Line - 15850 5700 16250 5700 + 15850 4550 16250 4550 Wire Wire Line - 18300 6150 18450 6150 + 18300 5000 18450 5000 Wire Wire Line - 18300 6250 18450 6250 + 18300 5100 18450 5100 Wire Wire Line - 18300 6350 18450 6350 + 18300 5200 18450 5200 Wire Wire Line - 18300 6550 18450 6550 + 18300 5400 18450 5400 Wire Wire Line - 18300 6650 18450 6650 + 18300 5500 18450 5500 Wire Wire Line - 16100 6850 16250 6850 + 16100 5700 16250 5700 Wire Wire Line - 16100 6950 16250 6950 -NoConn ~ 18450 6550 -NoConn ~ 18450 6650 -NoConn ~ 18450 6150 -NoConn ~ 18450 6250 -NoConn ~ 18450 6350 -NoConn ~ 16100 6850 -NoConn ~ 16100 6950 + 16100 5800 16250 5800 +NoConn ~ 18450 5400 +NoConn ~ 18450 5500 +NoConn ~ 18450 5000 +NoConn ~ 18450 5100 +NoConn ~ 18450 5200 +NoConn ~ 16100 5700 +NoConn ~ 16100 5800 $Comp L Connector:TestPoint TP1 U 1 1 5D13FB87 @@ -494,26 +500,26 @@ Text Label 19450 2550 0 50 ~ 0 $Comp L Connector:TestPoint TP2 U 1 1 5D158FCC -P 19400 5750 -F 0 "TP2" H 19458 5870 50 0000 L CNN -F 1 "TEST-POINT0.8MM" H 19458 5779 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:TEST_POINT_0.8MM" H 19600 5750 50 0001 C CNN -F 3 "~" H 19600 5750 50 0001 C CNN -F 4 "DNP" H 19400 5750 50 0001 C CNN "DNP" - 1 19400 5750 +P 19400 4600 +F 0 "TP2" H 19458 4720 50 0000 L CNN +F 1 "TEST-POINT0.8MM" H 19458 4629 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:TEST_POINT_0.8MM" H 19600 4600 50 0001 C CNN +F 3 "~" H 19600 4600 50 0001 C CNN +F 4 "DNP" H 19400 4600 50 0001 C CNN "DNP" + 1 19400 4600 1 0 0 -1 $EndComp Wire Wire Line - 18300 5650 18650 5650 + 18300 4500 18650 4500 Wire Wire Line - 18300 5850 18650 5850 + 18300 4700 18650 4700 Wire Wire Line - 18300 6050 18650 6050 + 18300 4900 18650 4900 Wire Wire Line - 18300 5750 19400 5750 -Text Label 18650 5750 0 50 ~ 0 + 18300 4600 19400 4600 +Text Label 18650 4600 0 50 ~ 0 CLKREQ_L_1 -Text Label 18650 6050 0 50 ~ 0 +Text Label 18650 4900 0 50 ~ 0 5G_WLAN_LED_1 Text Label 2950 2100 0 50 ~ 0 +3V3 @@ -557,8 +563,8 @@ L Connector:Barrel_Jack_Switch J1 U 1 1 5D1DA32E P 1600 14550 F 0 "J1" H 1500 14900 50 0000 C CNN -F 1 "12V_JACK" H 1550 14800 50 0000 C CNN -F 2 "LibreRouter_MegaBoard:POWER_JACK_SLOT" H 1650 14510 50 0001 C CNN +F 1 "DC_IN_JACK" H 1550 14800 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:CUI_PJ-002A_noedge" H 1650 14510 50 0001 C CNN F 3 "~" H 1650 14510 50 0001 C CNN F 4 "CUI Devices" H 1600 14550 50 0001 C CNN "Manufacturer" F 5 "PJ-002A" H 1600 14550 50 0001 C CNN "Manufacturer PN" @@ -583,38 +589,22 @@ Wire Wire Line Connection ~ 1900 14650 Wire Wire Line 1900 14650 1900 14850 -Text Label 14750 8850 0 50 ~ 0 +Text Label 14750 7300 0 50 ~ 0 S17_P4_TRX_0_P -Text Label 14750 8750 0 50 ~ 0 +Text Label 14750 7200 0 50 ~ 0 S17_P4_TRX_0_N -Text Label 14750 9050 0 50 ~ 0 +Text Label 14750 7500 0 50 ~ 0 S17_P4_TRX_1_P -Text Label 14750 8950 0 50 ~ 0 +Text Label 14750 7400 0 50 ~ 0 S17_P4_TRX_1_N -Text Label 14750 9250 0 50 ~ 0 +Text Label 14750 7700 0 50 ~ 0 S17_P4_TRX_2_P -Text Label 14750 9150 0 50 ~ 0 +Text Label 14750 7600 0 50 ~ 0 S17_P4_TRX_2_N -Text Label 14750 9450 0 50 ~ 0 +Text Label 14750 7900 0 50 ~ 0 S17_P4_TRX_3_P -Text Label 14750 9350 0 50 ~ 0 +Text Label 14750 7800 0 50 ~ 0 S17_P4_TRX_3_N -Text Label 14750 10150 0 50 ~ 0 -S17_P3_TRX_0_P -Text Label 14750 10050 0 50 ~ 0 -S17_P3_TRX_0_N -Text Label 14750 10350 0 50 ~ 0 -S17_P3_TRX_1_P -Text Label 14750 10250 0 50 ~ 0 -S17_P3_TRX_1_N -Text Label 14750 10550 0 50 ~ 0 -S17_P3_TRX_2_P -Text Label 14750 10450 0 50 ~ 0 -S17_P3_TRX_2_N -Text Label 14750 10750 0 50 ~ 0 -S17_P3_TRX_3_P -Text Label 14750 10650 0 50 ~ 0 -S17_P3_TRX_3_N Text Label 8000 1200 0 50 ~ 0 +3V3 Text Label 8000 1100 0 50 ~ 0 @@ -671,245 +661,195 @@ Wire Wire Line 3950 11150 4050 11150 Wire Wire Line 4050 11150 4050 11350 -$Comp -L Connector_Generic:Conn_02x13_Odd_Even GPIO1 -U 1 1 5D446377 -P 3750 8650 -F 0 "GPIO1" H 3800 9550 50 0000 C CNN -F 1 "Conn_02x13" H 3800 9450 50 0000 C CNN -F 2 "LibreRouter_MegaBoard:2X13" H 3750 8650 50 0001 C CNN -F 3 "~" H 3750 8650 50 0001 C CNN -F 4 "Würth Elektronik" H 3750 8650 50 0001 C CNN "Manufacturer" -F 5 "61302621121" H 3750 8650 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 3750 8650 50 0001 C CNN "Supplier" -F 7 "732-5304-ND" H 3750 8650 50 0001 C CNN "Supplier PN" - 1 3750 8650 - 1 0 0 -1 -$EndComp Wire Wire Line - 7950 8650 8650 8650 -Text Label 7950 8650 0 50 ~ 0 + 7700 8650 8650 8650 +Text Label 7700 8650 0 50 ~ 0 GPIO4 Wire Wire Line - 7950 8750 8650 8750 -Text Label 7950 8750 0 50 ~ 0 -GPIO12 -Text Label 7900 10500 0 50 ~ 0 -GPIO13 -Wire Wire Line - 7950 8850 8650 8850 -Text Label 7950 8850 0 50 ~ 0 -GPIO14 -Text Label 7900 10300 0 50 ~ 0 -GPIO15 -Text Label 7900 10400 0 50 ~ 0 -GPIO16 + 7700 8750 8650 8750 +Text Label 4050 10500 0 50 ~ 0 +GPIO13-GPS_PPS +Wire Wire Line + 7700 8850 8650 8850 Text Label 7950 4650 0 50 ~ 0 GPIO17 Wire Wire Line - 7950 8950 8650 8950 -Text Label 7950 8950 0 50 ~ 0 + 7700 8950 8650 8950 +Text Label 7700 8950 0 50 ~ 0 GPIO18 Wire Wire Line - 7950 9050 8650 9050 -Text Label 7950 9050 0 50 ~ 0 + 7700 9050 8650 9050 +Text Label 7700 9050 0 50 ~ 0 GPIO19 Wire Wire Line - 7950 9150 8650 9150 -Text Label 7950 9150 0 50 ~ 0 + 7700 9150 8650 9150 +Text Label 7700 9150 0 50 ~ 0 GPIO21 -Text Label 7900 8050 0 50 ~ 0 -GPIO0 -Text Label 7900 8150 0 50 ~ 0 -GPIO1 -Text Label 7900 8350 0 50 ~ 0 -GPIO3 Text Label 7900 6400 0 50 ~ 0 UART_SIN Text Label 7900 6500 0 50 ~ 0 UART_SOUT Wire Wire Line - 4050 8450 4250 8450 + 5550 8600 5750 8600 Wire Wire Line - 4250 8550 4050 8550 + 5750 8700 5550 8700 Wire Wire Line - 4050 8650 4250 8650 + 5550 8800 5750 8800 Wire Wire Line - 4050 8750 4250 8750 + 5550 8900 5750 8900 Wire Wire Line - 4050 8850 4250 8850 + 5550 9000 5750 9000 Wire Wire Line - 4250 8950 4050 8950 + 5750 9100 5550 9100 Wire Wire Line - 4050 9050 4250 9050 + 5550 9200 5750 9200 Wire Wire Line - 4050 9150 4250 9150 + 5550 9300 5750 9300 Wire Wire Line - 4050 9250 4250 9250 -Text Label 4250 8450 0 50 ~ 0 + 5550 9400 5750 9400 +Text Label 5750 8600 0 50 ~ 0 GPIO4 -Text Label 4250 8550 0 50 ~ 0 +Text Label 5750 8700 0 50 ~ 0 UART_SIN -Text Label 4250 8650 0 50 ~ 0 +Text Label 5750 8800 0 50 ~ 0 UART_SOUT Wire Wire Line - 3350 8050 3550 8050 -Wire Wire Line - 3550 8150 3350 8150 + 4850 8200 5050 8200 Wire Wire Line - 3350 8250 3550 8250 + 5050 8300 4850 8300 Wire Wire Line - 3350 8450 3550 8450 + 4850 8600 5050 8600 Wire Wire Line - 3550 8550 3350 8550 + 5050 8700 4850 8700 Wire Wire Line - 3350 8650 3550 8650 + 4850 8800 5050 8800 Wire Wire Line - 3350 8850 3550 8850 + 4850 9000 5050 9000 Wire Wire Line - 3550 8950 3350 8950 + 5050 9100 4850 9100 Wire Wire Line - 3350 9050 3550 9050 + 4850 9200 5050 9200 Wire Wire Line - 3350 9150 3550 9150 -Text Label 4250 8750 0 50 ~ 0 -GPIO12 -Text Label 4250 8850 0 50 ~ 0 -GPIO13 -Text Label 4250 8950 0 50 ~ 0 -GPIO14 -Text Label 4250 9050 0 50 ~ 0 -GPIO15 -Text Label 4250 9150 0 50 ~ 0 -GPIO16 + 4850 9300 5050 9300 Text Label 5600 15250 0 50 ~ 0 -+12V +VCC Wire Wire Line 5600 15250 5450 15250 -Text Label 4250 9250 0 50 ~ 0 -+12V -Text Label 3350 8050 2 50 ~ 0 +Text Label 5750 9400 0 50 ~ 0 +VCC +Text Label 4850 8200 2 50 ~ 0 POWER_EN_3.3V -Text Label 3350 8150 2 50 ~ 0 +Text Label 4850 8300 2 50 ~ 0 POWER_EN_5V -Text Label 3350 8250 2 50 ~ 0 -RST_B Text Label 7900 12300 0 50 ~ 0 RST_B $Comp L power:GND #PWR0107 U 1 1 5D61DC25 -P 3450 9500 -F 0 "#PWR0107" H 3450 9250 50 0001 C CNN -F 1 "GND" H 3455 9327 50 0000 C CNN -F 2 "" H 3450 9500 50 0001 C CNN -F 3 "" H 3450 9500 50 0001 C CNN - 1 3450 9500 +P 4950 9500 +F 0 "#PWR0107" H 4950 9250 50 0001 C CNN +F 1 "GND" H 4955 9327 50 0000 C CNN +F 2 "" H 4950 9500 50 0001 C CNN +F 3 "" H 4950 9500 50 0001 C CNN + 1 4950 9500 1 0 0 -1 $EndComp Wire Wire Line - 3450 9500 3450 9250 + 4950 9500 4950 9400 Wire Wire Line - 3450 8350 3550 8350 -Connection ~ 3450 8750 + 4950 8500 5050 8500 +Connection ~ 4950 8900 Wire Wire Line - 3450 8750 3550 8750 + 4950 8900 5050 8900 Wire Wire Line - 3450 8750 3450 8350 -Connection ~ 3450 9250 + 4950 8900 4950 8500 +Connection ~ 4950 9400 Wire Wire Line - 3450 9250 3450 8750 + 4950 9400 4950 8900 Wire Wire Line - 3450 9250 3550 9250 -Text Label 3350 8550 2 50 ~ 0 + 4950 9400 5050 9400 +Text Label 4850 8700 2 50 ~ 0 GPIO17 -Text Label 3350 8650 2 50 ~ 0 +Text Label 4850 8800 2 50 ~ 0 GPIO18 -Text Label 3350 8450 2 50 ~ 0 +Text Label 4850 8600 2 50 ~ 0 +3V3 -Text Label 3350 8850 2 50 ~ 0 +Text Label 4850 9000 2 50 ~ 0 5V_1 -Text Label 3350 8950 2 50 ~ 0 +Text Label 4850 9100 2 50 ~ 0 GPIO21 -Text Label 3350 9050 2 50 ~ 0 +Text Label 4850 9200 2 50 ~ 0 GPIO20 -Text Label 3350 9150 2 50 ~ 0 +Text Label 4850 9300 2 50 ~ 0 GPIO19 $Comp L Device:R R67 U 1 1 5D6C52AE -P 4950 8600 -F 0 "R67" H 5000 8550 50 0000 L CNN -F 1 "10k 1%" H 4950 8450 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:R0402" V 4880 8600 50 0001 C CNN -F 3 "~" H 4950 8600 50 0001 C CNN -F 4 "Panasonic Electronic Components" H 4950 8600 50 0001 C CNN "Manufacturer" -F 5 "ERJ-PA2F1002X" H 4950 8600 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 4950 8600 50 0001 C CNN "Supplier" -F 7 "P17230DKR-ND" H 4950 8600 50 0001 C CNN "Supplier PN" - 1 4950 8600 +P 2350 9100 +F 0 "R67" H 2400 9050 50 0000 L CNN +F 1 "10k 1%" H 2350 8950 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:R0402" V 2280 9100 50 0001 C CNN +F 3 "~" H 2350 9100 50 0001 C CNN +F 4 "Panasonic Electronic Components" H 2350 9100 50 0001 C CNN "Manufacturer" +F 5 "ERJ-PA2F1002X" H 2350 9100 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 2350 9100 50 0001 C CNN "Supplier" +F 7 "P17230DKR-ND" H 2350 9100 50 0001 C CNN "Supplier PN" + 1 2350 9100 1 0 0 -1 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13567 50 0000 C CNN +F 1 "Conn_02x03" H 6250 13476 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:2X03" H 6200 13250 50 0001 C CNN +F 3 "~" H 6200 13250 50 0001 C CNN +F 4 "Würth Elektronik" H 6200 13250 50 0001 C CNN "Manufacturer" +F 5 "61300621121" H 6200 13250 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 6200 13250 50 0001 C CNN "Supplier" +F 7 "732-5295-ND" H 6200 13250 50 0001 C CNN "Supplier PN" + 1 6200 13250 -1 0 0 -1 $EndComp $Comp @@ -1125,90 +1063,80 @@ Wire Wire Line $Comp L power:GND #PWR0113 U 1 1 5E5311AA -P 5150 13450 -F 0 "#PWR0113" H 5150 13200 50 0001 C CNN -F 1 "GND" H 5155 13277 50 0000 C CNN -F 2 "" H 5150 13450 50 0001 C CNN -F 3 "" H 5150 13450 50 0001 C CNN - 1 5150 13450 +P 5900 13450 +F 0 "#PWR0113" H 5900 13200 50 0001 C CNN +F 1 "GND" H 5905 13277 50 0000 C CNN +F 2 "" H 5900 13450 50 0001 C CNN +F 3 "" H 5900 13450 50 0001 C CNN + 1 5900 13450 -1 0 0 -1 $EndComp Wire Wire Line - 5150 13350 5150 13450 -Text Label 7900 12700 0 50 ~ 0 + 5900 13350 5900 13450 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"ERJ-2GE0R00X" H 7050 13150 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 7050 13150 50 0001 C CNN "Supplier" +F 7 "P0.0JDKR-ND" H 7050 13150 50 0001 C CNN "Supplier PN" + 1 7050 13150 0 -1 1 0 $EndComp Wire Wire Line - 6150 13150 6000 13150 -Connection ~ 6000 13150 + 6900 13150 6750 13150 +Connection ~ 6750 13150 Wire Wire Line - 6450 13150 6950 13150 -Text Label 5400 12100 2 50 ~ 0 + 7200 13150 7700 13150 +Text Label 5800 12100 2 50 ~ 0 +3V3 Wire Wire Line - 5150 13150 5050 13150 -Wire Wire Line - 5050 13150 5050 12100 -Connection ~ 5050 12100 -Wire Wire Line - 5050 12100 4600 12100 -Wire Wire Line - 5400 12100 5050 12100 + 5900 13150 5800 13150 $Comp L PushSwitchShielded:push_switch_SH S2 U 1 1 5D2895FD @@ -1231,15 +1159,6 @@ Wire Wire Line 3950 4950 3950 5300 Wire Wire Line 3950 4650 3600 4650 -Wire Wire Line - 4050 8350 4950 8350 -Wire Wire Line - 4950 8750 4950 8850 -Wire Wire Line - 4950 8450 4950 8350 -Connection ~ 4950 8350 -Wire Wire Line - 4950 8350 8650 8350 Wire Wire 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9450 + 16250 7700 13550 7700 Wire Wire Line - 13550 10050 16250 10050 + 13550 7800 16250 7800 Wire Wire Line - 16250 10150 13550 10150 -Wire Wire Line - 13550 10250 16250 10250 -Wire Wire Line - 16250 10350 13550 10350 -Wire Wire Line - 13550 10450 16250 10450 -Wire Wire Line - 16250 10550 13550 10550 -Wire Wire Line - 13550 10650 16250 10650 -Wire Wire Line - 13550 10750 16250 10750 -Text Notes 16900 11550 0 236 ~ 0 + 13550 7900 16250 7900 +Text Notes 17250 11700 0 236 ~ 0 Ethernet Ports & POE I/O -Wire Notes Line - 22000 7350 22000 700 -Text Notes 17650 1300 0 236 ~ 0 +Text Notes 15350 1150 0 236 ~ 0 PCIe daughterboards Wire Notes Line - 22000 7750 22000 11700 -Text Label 3050 15200 0 50 ~ 0 -12V_POE -Text Label 18300 10900 0 50 ~ 0 -12V_POE -Wire Wire Line - 17750 10900 18300 10900 + 22000 6200 22000 11800 Wire Wire Line 13550 12600 16250 12600 Wire Wire Line @@ -1487,15 +1382,6 @@ Wire Wire Line 3950 11250 8650 11250 Wire Wire Line 8650 4650 3950 4650 -Wire Wire Line - 5900 12500 8650 12500 -Connection ~ 5900 12500 -Wire Wire Line - 6000 12600 8650 12600 -Connection ~ 6000 12600 -Wire Wire Line - 4800 12700 8650 12700 -Connection ~ 4800 12700 Wire Wire Line 4600 12300 8650 12300 Text Label 7900 11050 0 50 ~ 0 @@ -1539,24 +1425,20 @@ Text Notes 1050 4350 0 236 ~ 0 Toggle Button Text Notes 1000 6900 0 236 ~ 0 UART\nHEADER -Text Notes 1000 7900 0 236 ~ 0 +Text Notes 4250 7800 0 236 ~ 0 Expose IOs Wire Notes Line 22000 14650 22000 11900 Text Notes 15500 14600 0 236 ~ 0 USB Interface Wire Notes Line - 12550 700 12550 7350 -Wire Notes Line - 12550 7350 22000 7350 + 12550 6100 22000 6100 Wire Notes Line 12550 700 22000 700 Wire Notes Line - 12550 7750 12550 11700 + 12550 6200 22000 6200 Wire Notes Line - 12550 7750 22000 7750 -Wire Notes Line - 12550 11700 22000 11700 + 12550 11800 22000 11800 Wire Notes Line 12550 11900 12550 14650 Wire Notes Line @@ -3077,23 +2959,23 @@ $EndBitmap $Comp L power:GND #PWR0114 U 1 1 5D211686 -P 14800 5600 -F 0 "#PWR0114" H 14800 5350 50 0001 C CNN -F 1 "GND" H 14805 5427 50 0000 C CNN -F 2 "" H 14800 5600 50 0001 C CNN -F 3 "" H 14800 5600 50 0001 C CNN - 1 14800 5600 +P 14800 4450 +F 0 "#PWR0114" H 14800 4200 50 0001 C CNN +F 1 "GND" H 14805 4277 50 0000 C CNN +F 2 "" H 14800 4450 50 0001 C CNN +F 3 "" H 14800 4450 50 0001 C CNN + 1 14800 4450 1 0 0 -1 $EndComp Wire Wire Line - 14800 5600 14800 5550 + 14800 4450 14800 4400 Wire Wire Line - 14800 5550 15300 5550 + 14800 4400 15300 4400 Wire Wire Line - 15300 5550 15300 5500 -Connection ~ 14800 5550 + 15300 4400 15300 4350 +Connection ~ 14800 4400 Wire Wire Line - 14800 5550 14800 5500 + 14800 4400 14800 4350 $Comp L Device:C C7 U 1 1 5D2A0499 @@ -3112,49 +2994,49 @@ $EndComp $Comp L Device:C C8 U 1 1 5D2A0651 -P 17000 4500 -F 0 "C8" H 17115 4546 50 0000 L CNN -F 1 "10pF" H 17115 4455 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:C0402" H 17038 4350 50 0001 C CNN -F 3 "~" H 17000 4500 50 0001 C CNN -F 4 "Murata Electronics" H 17000 4500 50 0001 C CNN "Manufacturer" -F 5 "GCM1555C1H100JA16D" H 17000 4500 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 17000 4500 50 0001 C CNN "Supplier" -F 7 "490-10668-6-ND" H 17000 4500 50 0001 C CNN "Supplier PN" - 1 17000 4500 +P 20600 1350 +F 0 "C8" H 20715 1396 50 0000 L CNN +F 1 "10pF" H 20715 1305 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:C0402" H 20638 1200 50 0001 C CNN +F 3 "~" H 20600 1350 50 0001 C CNN +F 4 "Murata Electronics" H 20600 1350 50 0001 C CNN "Manufacturer" +F 5 "GCM1555C1H100JA16D" H 20600 1350 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 20600 1350 50 0001 C CNN "Supplier" +F 7 "490-10668-6-ND" H 20600 1350 50 0001 C CNN "Supplier PN" + 1 20600 1350 1 0 0 -1 $EndComp $Comp L Device:C C9 U 1 1 5D2A06B3 -P 15300 5350 -F 0 "C9" H 15415 5396 50 0000 L CNN -F 1 "33pF" H 15415 5305 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:C0402" H 15338 5200 50 0001 C CNN -F 3 "~" H 15300 5350 50 0001 C CNN -F 4 "Murata Electronics" H 15300 5350 50 0001 C CNN "Manufacturer" -F 5 "GCM1555C1H330JA16J" H 15300 5350 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 15300 5350 50 0001 C CNN "Supplier" -F 7 "490-17750-6-ND" H 15300 5350 50 0001 C CNN "Supplier PN" - 1 15300 5350 +P 15300 4200 +F 0 "C9" H 15415 4246 50 0000 L CNN +F 1 "33pF" H 15415 4155 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:C0402" H 15338 4050 50 0001 C CNN +F 3 "~" H 15300 4200 50 0001 C CNN +F 4 "Murata Electronics" H 15300 4200 50 0001 C CNN "Manufacturer" +F 5 "GCM1555C1H330JA16J" H 15300 4200 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 15300 4200 50 0001 C CNN "Supplier" +F 7 "490-17750-6-ND" H 15300 4200 50 0001 C CNN "Supplier PN" + 1 15300 4200 1 0 0 -1 $EndComp $Comp L Device:CP C? U 1 1 5D2A0A2B -P 17450 4500 +P 21050 1350 AR Path="/5D032C97/5D2A0A2B" Ref="C?" Part="1" AR Path="/5D1650F5/5D2A0A2B" Ref="C?" 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1 14800 5350 +P 14800 4200 +F 0 "C39" H 14500 4200 50 0000 L CNN +F 1 "47uF, 6.3V" H 14300 4100 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:C1206" H 14838 4050 50 0001 C CNN +F 3 "~" H 14800 4200 50 0001 C CNN +F 4 "DigiKey" H 14800 4200 50 0001 C CNN "Supplier" +F 5 "Murata Electronics" H 14800 4200 50 0001 C CNN "Manufacturer" +F 6 "GRM31CE70J476ME15L" H 14800 4200 50 0001 C CNN "Manufacturer PN" +F 7 "490-9967-6-ND" H 14800 4200 50 0001 C CNN "Supplier PN" + 1 14800 4200 1 0 0 -1 $EndComp $Comp @@ -3402,7 +3280,7 @@ Wire Wire Line Wire Wire Line 3450 15800 3800 15800 Wire Wire Line - 3050 15200 3800 15200 + 3050 15000 3800 15000 $Comp L Connector_Generic:Conn_01x02 J3 U 1 1 5D605BA6 @@ -3440,8 +3318,6 @@ Wire Wire Line Wire Wire Line 2550 14450 3800 14450 Connection ~ 2550 14450 -Wire Wire Line - 3400 4950 3400 5300 $Comp L power:GND #PWR0120 U 1 1 5D08F236 @@ -3453,49 +3329,43 @@ F 3 "" H 19050 13900 50 0001 C CNN 1 19050 13900 1 0 0 -1 $EndComp -Text Label 15800 9600 0 50 ~ 0 -GPIO1 -Text Label 15800 9750 0 50 ~ 0 -+12V -Wire Wire Line - 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"Manufacturer PN" + 1 17050 11050 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C143 +U 1 1 5EA54D01 +P 17050 10750 +F 0 "C143" V 17200 10850 50 0000 C CNN +F 1 "33nF" V 17200 10600 50 0000 C CNN +F 2 "Capacitor_SMD:C_0603_1608Metric" H 17088 10600 50 0001 C CNN +F 3 "~" H 17050 10750 50 0001 C CNN +F 4 "Murata Electronics" H 17050 10750 50 0001 C CNN "Manufacturer" +F 5 "DigiKey" H 17050 10750 50 0001 C CNN "Supplier" +F 6 "490-5765-6-ND" H 17050 10750 50 0001 C CNN "Supplier PN" +F 7 "GCJ188R71H332KA01D" H 17050 10750 50 0001 C CNN "Manufacturer PN" + 1 17050 10750 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C142 +U 1 1 5EA54D07 +P 17050 10450 +F 0 "C142" V 17200 10550 50 0000 C CNN +F 1 "33nF" V 17200 10300 50 0000 C CNN +F 2 "Capacitor_SMD:C_0603_1608Metric" H 17088 10300 50 0001 C CNN +F 3 "~" H 17050 10450 50 0001 C CNN +F 4 "Murata Electronics" H 17050 10450 50 0001 C CNN "Manufacturer" +F 5 "DigiKey" H 17050 10450 50 0001 C CNN "Supplier" +F 6 "490-5765-6-ND" H 17050 10450 50 0001 C CNN "Supplier PN" +F 7 "GCJ188R71H332KA01D" H 17050 10450 50 0001 C CNN "Manufacturer PN" + 1 17050 10450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 16900 11050 16800 11050 +Wire Wire Line + 16800 11050 16800 10950 +Wire Wire Line + 16800 10950 16650 10950 +Wire Wire Line + 16900 11350 16750 11350 +Wire Wire Line + 16750 11350 16750 11050 +Wire Wire Line + 16750 11050 16650 11050 +Wire Wire Line + 16900 10750 16800 10750 +Wire Wire Line + 16800 10750 16800 10850 +Wire Wire Line + 16800 10850 16650 10850 +Wire Wire Line + 16900 10450 16750 10450 Wire Wire Line - 17450 4800 17000 4800 + 16750 10450 16750 10750 Wire Wire Line - 17000 4800 17000 4650 -Connection ~ 17000 4800 + 16750 10750 16650 10750 Wire Wire Line - 17000 4350 17000 4100 + 17350 11350 17200 11350 Wire Wire Line - 17000 4100 16550 4100 + 17350 11050 17200 11050 Wire Wire Line - 17000 4100 17450 4100 + 17350 10750 17200 10750 Wire Wire Line - 17450 4100 17450 4350 -Connection ~ 17000 4100 + 17350 10450 17200 10450 +Text Label 1450 8600 0 50 ~ 0 +GPIO0-EJTAG_TCK +Text Label 1450 8300 0 50 ~ 0 +GPIO1-EJTAG_TDI +Text Label 1450 8500 0 50 ~ 0 +GPIO3-EJTAG_TMS +Text Label 1450 8400 0 50 ~ 0 +GPIO2-EJTAG_TDO +$Comp +L power:GND #PWR0198 +U 1 1 5E96054A +P 3900 9000 +F 0 "#PWR0198" H 3900 8750 50 0001 C CNN +F 1 "GND" H 3905 8827 50 0000 C CNN +F 2 "" H 3900 9000 50 0001 C CNN +F 3 "" H 3900 9000 50 0001 C CNN + 1 3900 9000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2950 8500 2350 8500 +Wire Wire Line + 2350 8500 2350 8950 +Wire Wire Line + 1450 8500 2350 8500 +Connection ~ 2350 8500 +Wire Wire Line + 1450 8400 2200 8400 +Wire Wire Line + 2200 8400 2200 7800 +Connection ~ 2200 8400 +Wire Wire Line + 2200 8400 2950 8400 +Wire Wire Line + 2350 9500 1850 9500 +Wire Wire Line + 1850 9500 1850 9250 +Wire Wire Line + 2800 9250 2800 9500 +Wire Wire Line + 2800 9500 2350 9500 +Connection ~ 2350 9500 +Wire Wire Line + 2350 9500 2350 9250 +Text Label 3600 8800 0 50 ~ 0 ++3V3 +Text Notes 900 7900 0 236 ~ 0 +JTAG +Wire Notes Line + 4150 9900 4150 7400 +Text Label 1450 8700 0 50 ~ 0 +RST_B +$Comp +L Connector_Generic:Conn_02x07_Odd_Even J9 +U 1 1 5F339737 +P 3150 8500 +F 0 "J9" H 3200 9017 50 0000 C CNN +F 1 "EJTAG" H 3200 8926 50 0000 C CNN +F 2 "Connector_PinSocket_2.54mm:PinSocket_2x07_P2.54mm_Vertical" H 3150 8500 50 0001 C CNN +F 3 "~" H 3150 8500 50 0001 C CNN +F 4 "DNP" H 3150 8500 50 0001 C CNN "DNP" + 1 3150 8500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1450 8600 1850 8600 +Wire Wire Line + 1450 8300 2800 8300 +Wire Wire Line + 2800 8950 2800 8300 +Connection ~ 2800 8300 +Wire Wire Line + 2800 8300 2950 8300 +Wire Wire Line + 1850 8950 1850 8600 +Connection ~ 1850 8600 +Wire Wire Line + 1850 8600 2950 8600 +$Comp +L Connector:TestPoint TP4 +U 1 1 5F57CF5E +P 2700 7800 +F 0 "TP4" H 2758 7920 50 0000 L CNN +F 1 "JTAG_TRST" H 2758 7829 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:TEST_POINT_0.8MM" H 2900 7800 50 0001 C CNN +F 3 "~" H 2900 7800 50 0001 C CNN +F 4 "DNP" H 2700 7800 50 0001 C CNN "DNP" + 1 2700 7800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2700 7800 2700 8200 +Wire Wire Line + 2700 8200 2950 8200 +Wire Wire Line + 1450 8700 2950 8700 +NoConn ~ 2950 8800 +NoConn ~ 3450 8700 +Wire Wire Line + 3450 8800 3600 8800 +Wire Wire Line + 3450 8200 3900 8200 +Wire Wire Line + 3900 8200 3900 8300 +Wire Wire Line + 3450 8300 3900 8300 +Connection ~ 3900 8300 +Wire Wire Line + 3900 8300 3900 8400 +Wire Wire Line + 3450 8400 3900 8400 +Connection ~ 3900 8400 +Wire Wire Line + 3900 8400 3900 8500 +Wire Wire Line + 3450 8500 3900 8500 +Connection ~ 3900 8500 +Wire Wire Line + 3900 8500 3900 8600 +Wire Wire Line + 3450 8600 3900 8600 +Connection ~ 3900 8600 +Wire Wire Line + 3900 8600 3900 9000 +Text Label 7950 8250 0 50 ~ 0 +GPIO2-EJTAG_TDO +Text Label 7950 8350 0 50 ~ 0 +GPIO3-EJTAG_TMS +Text Label 7950 8150 0 50 ~ 0 +GPIO1-EJTAG_TDI +Text Label 7950 8050 0 50 ~ 0 +GPIO0-EJTAG_TCK +Wire Wire Line + 7950 8050 8650 8050 +Wire Wire Line + 7950 8150 8650 8150 +Wire Wire Line + 8650 8250 7950 8250 +Wire Wire Line + 7950 8350 8650 8350 +NoConn ~ 5550 8200 +NoConn ~ 5550 8300 +NoConn ~ 5550 8400 +NoConn ~ 5550 8500 +$Comp +L Connector_Generic:Conn_02x13_Odd_Even GPIO1 +U 1 1 5D446377 +P 5250 8800 +F 0 "GPIO1" H 5300 9700 50 0000 C CNN +F 1 "Conn_02x13" H 5300 9600 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:2X13" H 5250 8800 50 0001 C CNN +F 3 "~" H 5250 8800 50 0001 C CNN +F 4 "Würth Elektronik" H 5250 8800 50 0001 C CNN "Manufacturer" +F 5 "61302621121" H 5250 8800 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 5250 8800 50 0001 C CNN "Supplier" +F 7 "732-5304-ND" H 5250 8800 50 0001 C CNN "Supplier PN" + 1 5250 8800 + 1 0 0 -1 +$EndComp +NoConn ~ 5050 8400 +Text Label 7650 9650 0 50 ~ 0 +WD_PCIe0_WAKE +Text Label 7500 9650 2 50 ~ 0 +GPIO2-EJTAG_TDO +Text Label 7650 9500 0 50 ~ 0 +POE_INJECT_SOFT_EN +Text Label 18450 9800 0 50 ~ 0 +POE_INJECT_SOFT_EN +Text Label 7500 9500 2 50 ~ 0 +GPIO1-EJTAG_TDI +Wire Wire Line + 7650 9500 7500 9500 +Text Label 7650 9800 0 50 ~ 0 +WD_PCIe1_WAKE +Text Label 7500 9800 2 50 ~ 0 +GPIO3-EJTAG_TMS +Wire Wire Line + 7500 9800 7650 9800 +Text Label 18650 4500 0 50 ~ 0 +WD_PCIe1_WAKE +Text Label 4050 10400 0 50 ~ 0 +GPIO16-GPS_UART_TX +Text Label 4050 10300 0 50 ~ 0 +GPIO15-GPS_UART_RX +Text Label 5750 9200 0 50 ~ 0 +GPIO15-GPS_UART_RX +Text Label 5750 9300 0 50 ~ 0 +GPIO16-GPS_UART_TX +Text Label 5750 9000 0 50 ~ 0 +GPIO13-GPS_PPS +Text Label 5750 8900 0 50 ~ 0 +GPIO12-PCIe0_nDISABLE +Text Label 5750 9100 0 50 ~ 0 +GPIO14-PCIe1_nDISABLE +Text Label 18650 2350 0 50 ~ 0 +GPIO12-PCIe0_nDISABLE +Text Label 18650 4700 0 50 ~ 0 +GPIO14-PCIe1_nDISABLE +Wire Wire Line + 7500 9650 7650 9650 +Text Notes 6850 9350 0 50 ~ 0 +Alternate GPIO functions +Wire Notes Line + 6750 9250 8500 9250 +Wire Notes Line + 8500 9250 8500 9900 +Wire Notes Line + 6750 9250 6750 9900 +Text Label 7700 8750 0 50 ~ 0 +GPIO12-PCIe0_nDISABLE +Text Label 7700 8850 0 50 ~ 0 +GPIO14-PCIe1_nDISABLE +Wire Wire Line + 3400 4950 3400 5050 +Connection ~ 3400 5050 +Wire Wire Line + 3400 5050 3400 5300 +Text Notes 2000 14400 0 50 ~ 0 +9V - 32V $EndSCHEMATC diff --git a/designs/mega_board/LibreRouter_MegaBoard_BOM.csv b/designs/mega_board/LibreRouter_MegaBoard_BOM.csv new file mode 100644 index 0000000..5fd997e --- /dev/null +++ b/designs/mega_board/LibreRouter_MegaBoard_BOM.csv @@ -0,0 +1,75 @@ +"/home/san/somecode/librerouter/board/designs/mega_board/LibreRouter_MegaBoard.sch, Wed 11 Mar 2020 09:42:51 PM -03, Eeschema 5.1.5, /home/san/somecode/librerouter/board/designs/mega_board/bom_generator.py, 257" +"Ref","Qnty","Value","Cmp name","Manufacturer","Manufacturer PN","Supplier","Supplier PN","DNP","Footprint","Description" +"2G_WLAN1, 5G_WLAN1, P4_1000, STATUS1, ","4","3mm/GREEN","LED","","","","","","LibreRouter_MegaBoard:LED3MM","Light emitting diode" +"5G_WLAN0, P3_1000, USB_LED1, ","3","3mm/BLUE","LED","","","","","","LibreRouter_MegaBoard:LED3MM","Light emitting diode" +"C1, C8, ","2","10pF","C","Murata Electronics","GCM1555C1H100JA16D","DigiKey","490-10668-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C2, C3, C4, C7, C9, ","5","33pF","C","Murata Electronics","GCM1555C1H330JA16J","DigiKey","490-17750-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C5, C6, C10, C11, C12, C13, C21, C30, C33, C34, C35, C37, C42, C57, C58, C59, C62, C71, C72, C75, C91, C92, C102, C103, C110, C111, C116, C121, C124, C137, ","30","0.1uF, 10V","C","Murata Electronics","GCM155R71A104KA55D","DigiKey","490-16434-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C14, C17, C22, C25, C28, C31, C38, C46, C64, C67, ","10","22uF, 10V","C","Murata Electronics","GRM21BR61A226ME51L","DigiKey","490-10511-6-ND","","LibreRouter_MegaBoard:C0805","Unpolarized capacitor" +"C15, C19, C23, C26, C29, C36, C44, C53, C65, C68, ","10","10uF, 35V","C","Murata Electronics","GRM21BR6YA106ME43L","DigiKey","490-10515-6-ND","","LibreRouter_MegaBoard:C0805","Unpolarized capacitor" +"C16, C24, C32, C45, C66, ","5","2.7nF","C","Murata Electronics","GRM1557U1A272JA01D","DigiKey","490-6275-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C18, C27, C43, ","3","470uF","CP","Nichicon","UCM1A471MCL1GS","DigiKey","493-14524-6-ND","","LibreRouter_MegaBoard:UD-6,3X7,7_NICHICON","Polarized capacitor" +"C20, C39, ","2","47uF, 6.3V","C","Murata Electronics","GRM31CE70J476ME15L","DigiKey","490-9967-6-ND","","LibreRouter_MegaBoard:C1206","Unpolarized capacitor" +"C40, C41, C49, ","3","10nF, 2KV","C","Murata Electronics","GCJ31CR73A103KXJ3L","DigiKey","490-16694-6-ND","","LibreRouter_MegaBoard:C1206","Unpolarized capacitor" +"C54, C56, C60, ","3","10uF, 10V","C","Murata Electronics","GRM188D71A106MA73D","DigiKey","490-7200-6-ND","","LibreRouter_MegaBoard:C0603","Unpolarized capacitor" +"C55, ","1","100uF, 16V","CP","Nichicon","UCL1C101MCL1GS","DigiKey","493-3919-6-ND","","LibreRouter_MegaBoard:UD-6,3X5,8_NICHICON","Polarized capacitor" +"C61, C63, ","2","18pF","C","Murata Electronics","GCM1555C1H180JA16D","DigiKey","490-12650-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C76, ","1","1000uF, 35V","CP","Rubycon","35PX1000MEFC10X20","DigiKey","1189-1745-ND","","LibreRouter_MegaBoard:E3,5-10","Polarized capacitor" +"C90, C100, ","2","0.1uF, 50V","C","Murata Electronics","GRM155R71H104KE14J","DigiKey","490-13342-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C125, C126, ","2","0.01uF","C","Murata Electronics","GRM155R71H103KA88J","DigiKey","490-6351-6-ND","","LibreRouter_MegaBoard:C0402","Unpolarized capacitor" +"C130, ","1","10uF, 10V","C","Murata Electronics","GRM21BR71A106KA73K","DigiKey","490-14381-6-ND","","LibreRouter_MegaBoard:C0805","Unpolarized capacitor" +"C138, C139, C140, C141, C142, C143, C144, C145, ","8","33nF","C","Murata Electronics","GCJ188R71H332KA01D","DigiKey","490-5765-6-ND","","Capacitor_SMD:C_0603_1608Metric","Unpolarized capacitor" +"D2, ","1","SS14","D_Schottky","ON Semiconductor","SS14","DigiKey","SS14CT-ND","","LibreRouter_MegaBoard:DO214AC","Schottky diode" +"D3, D4, D6, D7, D8, D9, D10, D11, ","8","BS05C","D_TVS","Bincheng Electronics","BV05C","DigiKey","","","LibreRouter_MegaBoard:SOD-323","Bidirectional transient-voltage-suppression diode" +"D5, D12, D15, D17, D18, ","5","ESD7951ST5G","D_TVS","ON Semiconductor","ESD7951ST5G","DigiKey","ESD7951ST5GOSDKR-ND","","LibreRouter_MegaBoard:SOD−923","Bidirectional transient-voltage-suppression diode" +"D13, D14, D26, D27, D28, ","5","MBRS540T3","D_Schottky","ON Semiconductor","MBRS540T3G","DigiKey","MBRS540T3GOSDKR-ND","","LibreRouter_MegaBoard:SMC","Schottky diode" +"D25, ","1","SMBJ40CA","D_TVS","Littelfuse Inc.","SMBJ40CA","DigiKey","SMBJ40CALFDKR-ND","","LibreRouter_MegaBoard:DO-214AA","Bidirectional transient-voltage-suppression diode" +"EARTH1, ","1","M4","Conn_01x04","","","","","","LibreRouter_MegaBoard:M4","Generic connector, single row, 01x04, script generated (kicad-library-utils/schlib/autogen/connector/)" +"GPIO1, ","1","Conn_02x13","Conn_02x13_Odd_Even","Würth Elektronik","61302621121","DigiKey","732-5304-ND","","LibreRouter_MegaBoard:2X13","Generic connector, double row, 02x13, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)" +"J1, ","1","12V_JACK","Barrel_Jack_Switch","CUI Devices","PJ-002A","DigiKey","CP-002A-ND","","LibreRouter_MegaBoard:CUI_PJ-002A_noedge","DC Barrel Jack with an internal switch" +"J2, ","1","ETHERNET_2PORT","ETHERNET_2PORT","Amphenol ICC (Commercial Products)","RJHSE-5380-02","DigiKey","RJHSE-5380-02-ND","","LibreRouter_MegaBoard:ETHERNET-1X2","" +"J3, ","1","Conn_01x02","Conn_01x02","On Shore Technology Inc.","ED555/2DS","DigiKey","ED1514-ND","","LibreRouter_MegaBoard:KF350-2P","Generic connector, single row, 01x02, script generated (kicad-library-utils/schlib/autogen/connector/)" +"J5, ","1","USB-CON-A-DUALC39472","USB-CON-A-DUALC39472","Würth Elektronik","61400826021","DigiKey","732-2107-ND","","LibreRouter_MegaBoard:USB-DUAL-JS-AF10-002","" +"J6, ","1","Hack ETH","Conn_02x05_Odd_Even","","","","","","Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Vertical","Generic connector, double row, 02x05, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)" +"JP8, ","1","Conn_01x02","Conn_01x02","Würth Elektronik","61300211121","DigiKey","732-5315-ND","","LibreRouter_MegaBoard:1X02","Generic connector, single row, 01x02, script generated (kicad-library-utils/schlib/autogen/connector/)" +"L1, ","1","4A, GR30-400","Polyfuse","Littelfuse Inc.","RUEF400-2","DigiKey","RUEF400-2HFCT-ND","","LibreRouter_MegaBoard:GR72-135","Resettable fuse, polymeric positive temperature coefficient" +"L2, L3, L4, L5, L8, ","5","6.8uH, SWPA6045S6R8MT","L_Core_Ferrite","Abracon LLC","ASPI-6045S-6R8M-T","DigiKey","535-13046-6-ND","","LibreRouter_MegaBoard:SWPA6028S","Inductor with ferrite core" +"P1, P2, P3, P4, P5, P6, P7, P8, ","8","3R420L","3R420L","Bincheng Electronics","LTB3D090L","","","","LibreRouter_MegaBoard:GDT-LT-B3D090L","" +"P3_100, P4_100, PWR1, ","3","3mm/RED","LED","","","","","","LibreRouter_MegaBoard:LED3MM","Light emitting diode" +"PCIE0, PCIE1, ","2","f5521gw","PCIe_Conn","Molex","0679105700","DigiKey","WM7125DKR-ND","","LibreRouter_MegaBoard:MINI-PCI-E-FULL","" +"Q9, Q12, ","2","Si4435DDY-T1","P-MOSFET_SO8","Vishay Siliconix","SI4435DDY-T1-E3","DigiKey","SI4435DDY-T1-E3DKR-ND","","LibreRouter_MegaBoard:SI4435","" +"Q11, ","1","BSS138-7-F","NMOSFET","Diodes Incorporated","BSS138-7-F","DigiKey","BSS138-FDIDKR-ND","","LibreRouter_MegaBoard:SOT-23","" +"R1, R4, R5, R6, R29, R30, R31, ","8","75","R","Panasonic Electronic Components","ERJ-2BWFR075X","DigiKey","P.075ATDKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R3, ","1","4.7k","R","Panasonic Electronic Components","ERJ-2GEJ472X","DigiKey","P4.7KJDKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R7, R17, R21, R23, R24, R26, R27, R28, R77, R123, R124, ","11","330","R","Panasonic Electronic Components","ERJ-PA2F3300X","DigiKey","P17221DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R8, R22, ","2","0","R","Panasonic Electronic Components","ERJ-8GEY0R00V","DigiKey","P0.0EDKR-ND","","LibreRouter_MegaBoard:R1206","Resistor" +"R9, R10, R14, R34, R45, ","5","53.6K 1%","R","Panasonic Electronic Components","ERJ-2RKF5362X","DigiKey","P53.6KLDKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R11, R12, R15, R35, R43, R47, R53, R63, R64, R66, R67, R68, ","12","10k 1%","R","Panasonic Electronic Components","ERJ-PA2F1002X","DigiKey","P17230DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R13, R19, R36, R52, R58, ","5","180k","R","Panasonic Electronic Components","ERJ-PA2F1803X","DigiKey","P124450DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R16, R37, R38, R54, R59, ","5","24k","R","Panasonic Electronic Components","ERJ-PA2F2402X","DigiKey","P124459DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R18, R57, R60, R82, R83, R84, R86, R125, ","8","100k","R","Panasonic Electronic Components","ERJ-PA2F1003X","DigiKey","P17236DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R32, R126, ","2","68k","R","Panasonic Electronic Components","ERJ-PA2F6802X","DigiKey","P17235DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R33, R127, ","2","0 1/10W","R","Panasonic Electronic Components","ERJ-3GEY0R00V","DigiKey","P0.0GDKR-ND","","LibreRouter_MegaBoard:R0603","Resistor" +"R44, R85, ","2","47k","R","Panasonic Electronic Components","ERJ-PA2F4702X","DigiKey","P17234DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R50, R80, R99, R100, R101, R102, R107, R108, R109, R110, R111, R112, R117, R118, ","14","0","R","Panasonic Electronic Components","ERJ-2GE0R00X","DigiKey","P0.0JDKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R81, ","1","2.7k 1%","R","Panasonic Electronic Components","ERJ-PA2F2701X","DigiKey","P124463DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"R106, R116, ","2","1.5k","R","Panasonic Electronic Components","ERJ-PA2F1501X","DigiKey","P17225DKR-ND","","LibreRouter_MegaBoard:R0402","Resistor" +"S2, ","1","push_switch_SH","push_switch_SH","","","","","","LibreRouter_MegaBoard:SWITCH_6X6X5","" +"SIM_CARD_CON_6MICRO0, ","1","SIM_Card","SIM_Card","","","","","","LibreRouter_MegaBoard:SIM-MICRO-PUSH","SIM Card" +"SW1, ","1","SW_SPDT","SW_SPDT","E-Switch","EG1213","DigiKey","EG1906-ND","","LibreRouter_MegaBoard:EG1213","Switch, single pole double throw" +"T1, ","1","QT48A03","QT48A03","TNK","","","","","LibreRouter_MegaBoard:QT48103","" +"U2, U3, U4, U5, U6, ","5","RT7272","RT7272","Richtek USA Inc.","RT7272AGSP","DigiKey","RT7272AGSPDKR-ND","","LibreRouter_MegaBoard:RT8250-SOP8","" +"U12, ","1","USB_HUB_FE1.1S","FE1.1s","Tangming","FE1.1s","","","","LibreRouter_MegaBoard:USB_HUB_FE1.1S","" +"UART1, ","1","Conn_01x04","Conn_01x04","Würth Elektronik","61300411121","DigiKey","732-5317-ND","","LibreRouter_MegaBoard:1X04","Generic connector, single row, 01x04, script generated (kicad-library-utils/schlib/autogen/connector/)" +"V1, ","1","BC301N-D","BC301N-D","Bincheng Electronics","BC301N-D","","","","LibreRouter_MegaBoard:BC301N-D","" +"WDT1, ","1","ATTINY13","ATtiny13-20SSU-MCU_Microchip_ATtiny","Microchip Technology","ATTINY13A-SSUR","DigiKey","ATTINY13A-SSURDKR-ND","","LibreRouter_MegaBoard:S8S1","" +"WDT_CON1, ","1","Conn_02x03","Conn_02x03_Odd_Even","Würth Elektronik","61300621121","DigiKey","732-5295-ND","","LibreRouter_MegaBoard:2X03","Generic connector, double row, 02x03, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)" +"X2, ","1","YSX321SL 12MHz","Crystal_GND24_Small-Device","ECS Inc.","ECS-120-20-33-CKM-TR","DigiKey","XC1810DKR-ND","","LibreRouter_MegaBoard:SMARTPRJ_CRYSTAL-3.2-2.5","" +"GPS1, ","1","Conn_01x05","Conn_01x05","Würth Elektronik","61300511121","DigiKey","732-5318-ND","DNP","LibreRouter_MegaBoard:MA05-1","Generic connector, single row, 01x05, script generated (kicad-library-utils/schlib/autogen/connector/)" +"H1, H2, H3, H4, ","4","MountingHole","MountingHole","","","","","DNP","MountingHole:MountingHole_3mm","Mounting Hole without connection" +"R2, ","8","75","R","Panasonic Electronic Components","ERJ-2BWFR075X","DigiKey","P.075ATDKR-ND","DNP","LibreRouter_MegaBoard:R0402","Resistor" +"R20, R49, R96, R98, ","4","TBD","R","","","","","DNP","LibreRouter_MegaBoard:R0402","Resistor" +"SV1, ","1","Conn_01x03","Conn_01x03","Würth Elektronik","61300311121","DigiKey","732-5316-ND","DNP","LibreRouter_MegaBoard:MA03-1","Generic connector, single row, 01x03, script generated (kicad-library-utils/schlib/autogen/connector/)" +"TP1, TP2, TP3, ","3","TEST-POINT0.8MM","TestPoint","","","","","DNP","LibreRouter_MegaBoard:TEST_POINT_0.8MM","test point" +"U1, ","1","CORE9558_V2","Core9558","","","","","DNP","LibreRouter_MegaBoard:DRAGINO_CORE9558","" +"USB1, ","1","Conn_01x04","Conn_01x04","Würth Elektronik","61300411121","DigiKey","732-5317-ND","DNP","LibreRouter_MegaBoard:MA04-1","Generic connector, single row, 01x04, script generated (kicad-library-utils/schlib/autogen/connector/)" diff --git a/designs/mega_board/USB_hub.sch b/designs/mega_board/USB_hub.sch index aa620fd..e8a75a4 100644 --- a/designs/mega_board/USB_hub.sch +++ b/designs/mega_board/USB_hub.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 diff --git a/designs/mega_board/bom_generator.py b/designs/mega_board/bom_generator.py new file mode 100644 index 0000000..5ddedcd --- /dev/null +++ b/designs/mega_board/bom_generator.py @@ -0,0 +1,99 @@ +# +# Example python script to generate a BOM from a KiCad generic netlist +# +# Example: Sorted and Grouped CSV BOM +# + +FIELDS = [ + ('Value', lambda c: c.getValue()), + ('Cmp name', lambda c: c.getPartName()), + ('Manufacturer', None), + ('Manufacturer PN', None), + ('Supplier', None), + ('Supplier PN', None), + ('DNP', None), + ('Footprint', lambda c: c.getFootprint()), + ('Description', lambda c: c.getDescription()), +] + +FIELD_NAMES = [f[0] for f in FIELDS] + +def get_value(component, field): + if field[1] is None: + return component.getField(field[0]) + else: + return field[1](component) + +""" + @package + Generate a comma delimited list (csv file type). + Components are sorted by ref and grouped by value with same footprint. + Components with DNP field (do not place) are also grouped. + Fields are (if exist) + 'Ref', 'Qnty', and fields defined in FIELDS list + + Command line: + python "pathToFile/bom_csv_grouped_by_value_with_fp.py" "%I" "%O.csv" +""" + +import sys + +sys.path.append("/usr/share/kicad/plugins/") +# Import the KiCad python helper module and the csv formatter +import kicad_netlist_reader +import csv + +# Generate an instance of a generic netlist, and load the netlist tree from +# the command line option. If the file doesn't exist, execution will stop +net = kicad_netlist_reader.netlist(sys.argv[1]) + +# Open a file to write to, if the file cannot be opened output to stdout +# instead +try: + f = open(sys.argv[2], 'w') +except IOError: + e = "Can't open output file for writing: " + sys.argv[2] + print(__file__, ":", e, sys.stderr) + f = sys.stdout + +# Create a new csv writer object to use as the output formatter +out = csv.writer(f, lineterminator='\n', delimiter=',', quotechar='\"', quoting=csv.QUOTE_ALL) + + +# Output a set of rows for a header providing general information +out.writerow(["%s, %s, %s, %s, %s" % (net.getSource(), net.getDate(), net.getTool(), sys.argv[0], len(net.components))]) +out.writerow(['Ref', 'Qnty'] + FIELD_NAMES) + +# Get all of the components in groups of matching parts + values +# (see ky_generic_netlist_reader.py) +grouped = net.groupComponents() + +# Output all of the component information +for group in grouped: + refs = "" + + # Add the reference of every component in the group and keep a reference + # to the component so that the other data can be filled in once per group + c = None + for component in group: + if not component.getField("DNP"): + refs += component.getRef() + ", " + c = component + if c is not None: + out.writerow([refs, len(group)] + [get_value(c, field) for field in FIELDS]) + +# Output all of the component information +for group in grouped: + refs = "" + + # Add the reference of every component in the group and keep a reference + # to the component so that the other data can be filled in once per group + c = None + for component in group: + if component.getField("DNP"): + refs += component.getRef() + ", " + c = component + + if c is not None: + # Fill in the component groups common data + out.writerow([refs, len(group)] + [get_value(c, field) for field in FIELDS]) diff --git a/designs/mega_board/ethernet_frontend.sch b/designs/mega_board/ethernet_frontend.sch index 2d66e3f..cb5e6b8 100644 --- a/designs/mega_board/ethernet_frontend.sch +++ b/designs/mega_board/ethernet_frontend.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A3 16535 11693 @@ -14,1548 +13,1496 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text HLabel 1350 7500 0 50 BiDi ~ 0 +Text HLabel 1350 6700 0 50 BiDi ~ 0 AT_TRX0_N -Text HLabel 1350 7900 0 50 BiDi ~ 0 +Text HLabel 1350 7100 0 50 BiDi ~ 0 AT_TRX0_P -Text HLabel 1350 5700 0 50 BiDi ~ 0 +Text HLabel 1350 4900 0 50 BiDi ~ 0 AT_TRX1_N -Text HLabel 1350 6100 0 50 BiDi ~ 0 +Text HLabel 1350 5300 0 50 BiDi ~ 0 AT_TRX1_P -Text HLabel 1350 4000 0 50 BiDi ~ 0 +Text HLabel 1350 3200 0 50 BiDi ~ 0 AT_TRX2_N -Text HLabel 1350 4400 0 50 BiDi ~ 0 +Text HLabel 1350 3600 0 50 BiDi ~ 0 AT_TRX2_P -Text HLabel 1350 2200 0 50 BiDi ~ 0 +Text HLabel 1350 1400 0 50 BiDi ~ 0 AT_TRX3_N -Text HLabel 1350 2600 0 50 BiDi ~ 0 +Text HLabel 1350 1800 0 50 BiDi ~ 0 AT_TRX3_P -Text HLabel 7000 7500 0 50 BiDi ~ 0 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0001 C CNN +F 3 "~" H 1700 1600 50 0001 C CNN +F 4 "DigiKey" H 1700 1600 50 0001 C CNN "Supplier" +F 5 "Bincheng Electronics" H 1700 1600 50 0001 C CNN "Manufacturer" +F 6 "BV05C" H 1700 1600 50 0001 C CNN "Manufacturer PN" + 1 1700 1600 0 1 1 0 $EndComp Wire Wire Line - 1700 2250 1700 2200 + 1700 1450 1700 1400 Wire Wire Line - 1700 2200 2150 2200 + 1700 1400 2150 1400 Wire Wire Line - 2150 2200 2150 2300 + 2150 1400 2150 1500 Wire Wire Line - 1700 2550 1700 2600 + 1700 1750 1700 1800 Wire Wire Line - 1700 2600 2150 2600 + 1700 1800 2150 1800 Wire Wire Line - 2150 2600 2150 2500 + 2150 1800 2150 1700 Wire Wire Line - 1350 2200 1700 2200 -Connection ~ 1700 2200 + 1350 1400 1700 1400 +Connection ~ 1700 1400 Wire Wire Line - 1350 2600 1700 2600 -Connection ~ 1700 2600 + 1350 1800 1700 1800 +Connection ~ 1700 1800 $Comp L 3R420L:3R420L P1 U 1 1 5D47AAF5 -P 4600 2400 -F 0 "P1" H 4778 2446 50 0000 L CNN -F 1 "3R420L" H 4778 2355 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:GDT-LT-B3D090L" H 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"LibreRouter_MegaBoard:R0402" V 14030 6900 50 0001 C CNN +F 3 "~" H 14100 6900 50 0001 C CNN +F 4 "Panasonic Electronic Components" H 14100 6900 50 0001 C CNN "Manufacturer" +F 5 "ERJ-PA2F4702X" H 14100 6900 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 14100 6900 50 0001 C CNN "Supplier" +F 7 "P17234DKR-ND" H 14100 6900 50 0001 C CNN "Supplier PN" + 1 14100 6900 + 0 1 1 0 $EndComp $Comp L power:GND #PWR0189 U 1 1 5D88FE9A -P 13300 8950 -F 0 "#PWR0189" H 13300 8700 50 0001 C CNN -F 1 "GND" H 13305 8777 50 0000 C CNN -F 2 "" H 13300 8950 50 0001 C CNN -F 3 "" H 13300 8950 50 0001 C CNN - 1 13300 8950 +P 13450 7650 +F 0 "#PWR0189" H 13450 7400 50 0001 C CNN +F 1 "GND" H 13455 7477 50 0000 C CNN +F 2 "" H 13450 7650 50 0001 C CNN +F 3 "" H 13450 7650 50 0001 C CNN + 1 13450 7650 1 0 0 -1 $EndComp Wire Wire Line - 13300 8950 13300 8900 -Wire Wire Line - 13700 8700 13700 8900 -Wire Wire Line - 13700 8900 13300 8900 -Connection ~ 13300 8900 -Wire Wire Line - 13300 8900 13300 8300 + 14250 7250 14600 7250 Wire Wire Line - 14100 8200 14450 8200 + 15150 5200 15150 5050 Wire Wire Line - 14750 7450 14750 7300 + 15150 4750 15150 4600 Wire Wire Line - 14750 7000 14750 6850 + 15150 4300 15150 4200 Wire Wire Line - 14750 6550 14750 6450 + 15150 4200 15450 4200 Wire Wire Line - 14750 6450 15050 6450 + 15150 4200 14900 4200 +Connection ~ 15150 4200 Wire Wire Line - 14750 6450 14500 6450 -Connection ~ 14750 6450 + 13500 4550 13700 4550 Wire Wire Line - 13100 6800 13300 6800 + 13200 4550 13200 4200 Wire Wire Line - 12800 6800 12800 6450 + 13200 4200 13600 4200 Wire Wire Line - 12800 6450 13200 6450 + 13200 4200 12950 4200 +Connection ~ 13200 4200 +Text Label 14200 3700 0 50 ~ 0 +POE_A +Text HLabel 12550 4200 0 50 Input ~ 0 +POE_INJECT_V Wire Wire Line - 12800 6450 12550 6450 -Connection ~ 12800 6450 -Wire Wire Line - 13300 7200 13300 7900 -Text Label 13800 6450 0 50 ~ 0 -POE_OUT -Text HLabel 12550 6450 0 50 Input ~ 0 -POE_INJECTION -Wire Wire Line - 14200 6450 13600 6450 -Text Label 9800 8350 0 50 ~ 0 + 14600 4200 14200 4200 +Text Label 9800 7550 0 50 ~ 0 DISCHARGE -Text Label 4150 8350 0 50 ~ 0 +Text Label 4150 7550 0 50 ~ 0 DISCHARGE -Text Label 4150 6550 0 50 ~ 0 +Text Label 4150 5750 0 50 ~ 0 DISCHARGE -Text Label 4150 4850 0 50 ~ 0 +Text Label 4150 4050 0 50 ~ 0 DISCHARGE -Text Label 4150 3050 0 50 ~ 0 +Text Label 4150 2250 0 50 ~ 0 DISCHARGE -Text Label 9800 3050 0 50 ~ 0 +Text Label 9800 2250 0 50 ~ 0 DISCHARGE -Text Label 9800 4850 0 50 ~ 0 +Text Label 9800 4050 0 50 ~ 0 DISCHARGE -Text Label 9800 6550 0 50 ~ 0 +Text Label 9800 5750 0 50 ~ 0 DISCHARGE Text Label 2150 1000 0 50 ~ 0 DISCHARGE @@ -1563,48 +1510,240 @@ Text HLabel 1500 1000 0 50 Input ~ 0 DISCHARGE Wire Wire Line 2150 1000 1500 1000 -Text Notes 12050 7350 0 31 ~ 0 +Text Notes 12450 5100 0 31 ~ 0 This series resitor between \nPMOS gate and NMOS D is \nto keep PMOS Vgs at nomila \nvalues when the input POE \nvoltage is used at full range $Comp L p-mosfet_so8:P-MOSFET_SO8 Q9 U 1 1 5DD0095A -P 13400 6450 -F 0 "Q9" V 13666 6468 59 0000 C CNN -F 1 "Si4435DDY-T1" V 13561 6468 59 0000 C CNN -F 2 "LibreRouter_MegaBoard:SI4435" H 13400 6450 50 0001 C CNN -F 3 "" H 13400 6450 50 0001 C CNN -F 4 "Vishay Siliconix" H 13400 6450 50 0001 C CNN "Manufacturer" -F 5 "SI4435DDY-T1-E3" H 13400 6450 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 13400 6450 50 0001 C CNN "Supplier" -F 7 "SI4435DDY-T1-E3DKR-ND" H 13400 6450 50 0001 C CNN "Supplier PN" - 1 13400 6450 +P 13800 4200 +F 0 "Q9" V 14066 4218 59 0000 C CNN +F 1 "Si4435DDY-T1" V 13961 4218 59 0000 C CNN +F 2 "LibreRouter_MegaBoard:SI4435" H 13800 4200 50 0001 C CNN +F 3 "" H 13800 4200 50 0001 C CNN +F 4 "Vishay Siliconix" H 13800 4200 50 0001 C CNN "Manufacturer" +F 5 "SI4435DDY-T1-E3" H 13800 4200 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 13800 4200 50 0001 C CNN "Supplier" +F 7 "SI4435DDY-T1-E3DKR-ND" H 13800 4200 50 0001 C CNN "Supplier PN" + 1 13800 4200 0 -1 -1 0 $EndComp $Comp L nmosfet:NMOSFET Q11 U 1 1 5DD00C18 -P 13300 8100 -F 0 "Q11" H 13408 8153 59 0000 L CNN -F 1 "BSS138-7-F" H 13408 8048 59 0000 L CNN -F 2 "LibreRouter_MegaBoard:SOT-23" H 13300 8100 50 0001 C CNN -F 3 "" H 13300 8100 50 0001 C CNN -F 4 "Diodes Incorporated" H 13300 8100 50 0001 C CNN "Manufacturer" -F 5 "BSS138-7-F" H 13300 8100 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 13300 8100 50 0001 C CNN "Supplier" -F 7 "BSS138-FDIDKR-ND" H 13300 8100 50 0001 C CNN "Supplier PN" - 1 13300 8100 +P 13450 7150 +F 0 "Q11" H 13558 7203 59 0000 L CNN +F 1 "BSS138-7-F" H 13558 7098 59 0000 L CNN +F 2 "LibreRouter_MegaBoard:SOT-23" H 13450 7150 50 0001 C CNN +F 3 "" H 13450 7150 50 0001 C CNN +F 4 "Diodes Incorporated" H 13450 7150 50 0001 C CNN "Manufacturer" +F 5 "BSS138-7-F" H 13450 7150 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 13450 7150 50 0001 C CNN "Supplier" +F 7 "BSS138-FDIDKR-ND" H 13450 7150 50 0001 C CNN "Supplier PN" + 1 13450 7150 -1 0 0 -1 $EndComp Wire Wire Line - 13300 6650 13300 6800 -Connection ~ 13300 6800 + 13700 4400 13700 4550 +Connection ~ 13700 4550 +Wire Wire Line + 13700 4550 13700 4650 +$Comp +L Device:D_Schottky D? +U 1 1 5E485211 +P 12800 4200 +AR Path="/5D0328DE/5E485211" Ref="D?" Part="1" +AR Path="/5D032DC8/5E485211" Ref="D28" Part="1" +F 0 "D28" H 12800 3984 50 0000 C CNN +F 1 "MBRS540T3" H 12800 4075 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:SMC" H 12800 4200 50 0001 C CNN +F 3 "~" H 12800 4200 50 0001 C CNN +F 4 "ON Semiconductor" H 12800 4200 50 0001 C CNN "Manufacturer" +F 5 "MBRS540T3G" H 12800 4200 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 12800 4200 50 0001 C CNN "Supplier" +F 7 "MBRS540T3GOSDKR-ND" H 12800 4200 50 0001 C CNN "Supplier PN" + 1 12800 4200 + -1 0 0 1 +$EndComp +Wire Wire Line + 12550 4200 12650 4200 +Wire Wire Line + 13650 7250 13800 7250 +Text HLabel 14600 6900 2 50 Input ~ 0 +POE_INJECT_HARD_EN +Wire Wire Line + 13800 7250 13800 6900 +Wire Wire Line + 13800 6900 13950 6900 +Connection ~ 13800 7250 +Wire Wire Line + 13800 7250 13950 7250 +Wire Wire Line + 14250 6900 14600 6900 +Text Label 12750 6600 0 50 ~ 0 +POE_INJECT_CTRL +Wire Wire Line + 12750 6600 13450 6600 +Wire Wire Line + 13450 6600 13450 6950 +Wire Wire Line + 13450 7350 13450 7650 +Wire Wire Line + 13200 3700 14200 3700 +Wire Wire Line + 14200 3700 14200 4200 +Connection ~ 14200 4200 +Wire Wire Line + 14200 4200 14000 4200 +Text Label 13800 5150 0 50 ~ 0 +POE_INJECT_CTRL +Wire Wire Line + 13700 4950 13700 5150 +Wire Wire Line + 13700 5150 13800 5150 +Text HLabel 13200 1700 0 50 Output ~ 0 +POE_B +$Comp +L power:GND #PWR0197 +U 1 1 5E611D89 +P 15150 3200 +F 0 "#PWR0197" H 15150 2950 50 0001 C CNN +F 1 "GND" H 15155 3027 50 0000 C CNN +F 2 "" H 15150 3200 50 0001 C CNN +F 3 "" H 15150 3200 50 0001 C CNN + 1 15150 3200 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R127 +U 1 1 5E611D93 +P 14750 2200 +F 0 "R127" V 14650 2200 50 0000 C CNN +F 1 "0 1/10W" V 14550 2300 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:R0603" V 14680 2200 50 0001 C CNN +F 3 "~" H 14750 2200 50 0001 C CNN +F 4 "Panasonic Electronic Components" H 14750 2200 50 0001 C CNN "Manufacturer" +F 5 "DigiKey" H 14750 2200 50 0001 C CNN "Supplier" +F 6 "ERJ-3GEY0R00V" H 14750 2200 50 0001 C CNN "Manufacturer PN" +F 7 "P0.0GDKR-ND" H 14750 2200 50 0001 C CNN "Supplier PN" + 1 14750 2200 + 0 1 1 0 +$EndComp +$Comp +L Device:R R126 +U 1 1 5E611D9D +P 13700 2800 +F 0 "R126" H 13550 2800 50 0000 C CNN +F 1 "68k" H 13550 2900 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:R0402" V 13630 2800 50 0001 C CNN +F 3 "~" H 13700 2800 50 0001 C CNN +F 4 "Panasonic Electronic Components" H 13700 2800 50 0001 C CNN "Manufacturer" +F 5 "ERJ-PA2F6802X" H 13700 2800 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 13700 2800 50 0001 C CNN "Supplier" +F 7 "P17235DKR-ND" H 13700 2800 50 0001 C CNN "Supplier PN" + 1 13700 2800 + -1 0 0 1 +$EndComp +$Comp +L Device:R R125 +U 1 1 5E611DA7 +P 13350 2550 +F 0 "R125" V 13450 2650 50 0000 C CNN +F 1 "100k" V 13450 2450 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:R0402" V 13280 2550 50 0001 C CNN +F 3 "~" H 13350 2550 50 0001 C CNN +F 4 "Panasonic Electronic Components" H 13350 2550 50 0001 C CNN "Manufacturer" +F 5 "ERJ-PA2F1003X" H 13350 2550 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 13350 2550 50 0001 C CNN "Supplier" +F 7 "P17236DKR-ND" H 13350 2550 50 0001 C CNN "Supplier PN" + 1 13350 2550 + 0 1 1 0 +$EndComp +Wire Wire Line + 15150 3200 15150 3050 +Wire Wire Line + 15150 2750 15150 2600 +Wire Wire Line + 15150 2300 15150 2200 +Wire Wire Line + 15150 2200 15450 2200 +Wire Wire Line + 15150 2200 14900 2200 +Connection ~ 15150 2200 +Wire Wire Line + 13500 2550 13700 2550 +Wire Wire Line + 13200 2550 13200 2200 +Wire Wire Line + 13200 2200 13600 2200 +Wire Wire Line + 13200 2200 12950 2200 +Connection ~ 13200 2200 +Text Label 14200 1700 0 50 ~ 0 +POE_B +Text HLabel 12550 2200 0 50 Input ~ 0 +POE_INJECT_V +Wire Wire Line + 14600 2200 14200 2200 +$Comp +L p-mosfet_so8:P-MOSFET_SO8 Q12 +U 1 1 5E611DC0 +P 13800 2200 +F 0 "Q12" V 14066 2218 59 0000 C CNN +F 1 "Si4435DDY-T1" V 13961 2218 59 0000 C CNN +F 2 "LibreRouter_MegaBoard:SI4435" H 13800 2200 50 0001 C CNN +F 3 "" H 13800 2200 50 0001 C CNN +F 4 "Vishay Siliconix" H 13800 2200 50 0001 C CNN "Manufacturer" +F 5 "SI4435DDY-T1-E3" H 13800 2200 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 13800 2200 50 0001 C CNN "Supplier" +F 7 "SI4435DDY-T1-E3DKR-ND" H 13800 2200 50 0001 C CNN "Supplier PN" + 1 13800 2200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 13700 2400 13700 2550 +Connection ~ 13700 2550 +Wire Wire Line + 13700 2550 13700 2650 +$Comp +L Device:D_Schottky D? +U 1 1 5E611DCD +P 12800 2200 +AR Path="/5D0328DE/5E611DCD" Ref="D?" Part="1" +AR Path="/5D032DC8/5E611DCD" Ref="D27" Part="1" +F 0 "D27" H 12800 1984 50 0000 C CNN +F 1 "MBRS540T3" H 12800 2075 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:SMC" H 12800 2200 50 0001 C CNN +F 3 "~" H 12800 2200 50 0001 C CNN +F 4 "ON Semiconductor" H 12800 2200 50 0001 C CNN "Manufacturer" +F 5 "MBRS540T3G" H 12800 2200 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 12800 2200 50 0001 C CNN "Supplier" +F 7 "MBRS540T3GOSDKR-ND" H 12800 2200 50 0001 C CNN "Supplier PN" + 1 12800 2200 + -1 0 0 1 +$EndComp +Wire Wire Line + 12550 2200 12650 2200 +Wire Wire Line + 13200 1700 14200 1700 Wire Wire Line - 13300 6800 13300 6900 + 14200 1700 14200 2200 +Connection ~ 14200 2200 Wire Wire Line - 13500 8200 13700 8200 + 14200 2200 14000 2200 +Text Label 13800 3150 0 50 ~ 0 +POE_INJECT_CTRL Wire Wire Line - 13700 8400 13700 8200 -Connection ~ 13700 8200 + 13700 2950 13700 3150 Wire Wire Line - 13700 8200 13800 8200 + 13700 3150 13800 3150 +Wire Notes Line + 11800 1150 16000 1150 +Wire Notes Line + 16000 1150 16000 8800 +Wire Notes Line + 16000 8800 11800 8800 +Wire Notes Line + 11800 8800 11800 1150 +Text Notes 12200 8600 0 50 ~ 0 +POE input-output control $EndSCHEMATC diff --git a/designs/mega_board/led_interface.sch b/designs/mega_board/led_interface.sch index a3bbb02..af50c5c 100644 --- a/designs/mega_board/led_interface.sch +++ b/designs/mega_board/led_interface.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 diff --git a/designs/mega_board/pcie_daughterboard.sch b/designs/mega_board/pcie_daughterboard.sch index 3c9d9f2..e6dc333 100644 --- a/designs/mega_board/pcie_daughterboard.sch +++ b/designs/mega_board/pcie_daughterboard.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 @@ -151,7 +150,7 @@ U 1 1 5D19F8AF P 6650 5850 AR Path="/5D032C97/5D19F8AF" Ref="#PWR0173" Part="1" AR Path="/5D1650F5/5D19F8AF" Ref="#PWR0190" Part="1" -F 0 "#PWR0173" H 6650 5600 50 0001 C CNN +F 0 "#PWR0190" H 6650 5600 50 0001 C CNN F 1 "GND" H 6655 5677 50 0000 C CNN F 2 "" H 6650 5850 50 0001 C CNN F 3 "" H 6650 5850 50 0001 C CNN @@ -348,7 +347,7 @@ U 1 1 5D1C58DE P 2800 2100 AR Path="/5D032C97/5D1C58DE" Ref="#PWR0174" Part="1" AR Path="/5D1650F5/5D1C58DE" Ref="#PWR0191" Part="1" -F 0 "#PWR0174" H 2800 1850 50 0001 C CNN +F 0 "#PWR0191" H 2800 1850 50 0001 C CNN F 1 "GND" H 2805 1927 50 0000 C CNN F 2 "" H 2800 2100 50 0001 C CNN F 3 "" H 2800 2100 50 0001 C CNN @@ -385,7 +384,7 @@ U 1 1 5D1D537C P 1700 2100 AR Path="/5D032C97/5D1D537C" Ref="#PWR0175" Part="1" AR Path="/5D1650F5/5D1D537C" Ref="#PWR0192" Part="1" -F 0 "#PWR0175" H 1700 1850 50 0001 C CNN +F 0 "#PWR0192" H 1700 1850 50 0001 C CNN F 1 "GND" H 1705 1927 50 0000 C CNN F 2 "" H 1700 2100 50 0001 C CNN F 3 "" H 1700 2100 50 0001 C CNN @@ -501,7 +500,7 @@ U 1 1 5D20ABC1 P 4650 5850 AR Path="/5D032C97/5D20ABC1" Ref="#PWR0176" Part="1" AR Path="/5D1650F5/5D20ABC1" Ref="#PWR0193" Part="1" -F 0 "#PWR0176" H 4650 5600 50 0001 C CNN +F 0 "#PWR0193" H 4650 5600 50 0001 C CNN F 1 "GND" H 4655 5677 50 0000 C CNN F 2 "" H 4650 5850 50 0001 C CNN F 3 "" H 4650 5850 50 0001 C CNN diff --git a/designs/mega_board/power_supply.sch b/designs/mega_board/power_supply.sch index 941ab27..487ef15 100644 --- a/designs/mega_board/power_supply.sch +++ b/designs/mega_board/power_supply.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 @@ -14,10 +13,10 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text HLabel 5400 1100 2 50 BiDi ~ 0 -12V_OUT -Text HLabel 1550 1400 0 50 BiDi ~ 0 -12V_IN +Text HLabel 5350 1400 2 50 BiDi ~ 0 +VCC_OUT +Text HLabel 1500 1900 0 50 BiDi ~ 0 +VCC_IN Text HLabel 9650 1600 2 50 BiDi ~ 0 5V_0 Text HLabel 9650 3300 2 50 BiDi ~ 0 @@ -28,25 +27,16 @@ Text HLabel 4650 3300 2 50 BiDi ~ 0 3.3V_0 Text HLabel 4650 5300 2 50 BiDi ~ 0 3.3V_1 -Text HLabel 1550 900 0 50 BiDi ~ 0 -12V_POE -$Sheet -S 3300 5150 950 1000 -U 5D42CD47 -F0 "3.3V_1" 50 -F1 "rt7272_dcdc_3v3.sch" 50 -F2 "ENABLE" I L 3300 5950 50 -F3 "3.3V" B R 4250 5300 50 -F4 "12V" B L 3300 5300 50 -$EndSheet +Text HLabel 1500 1400 0 50 BiDi ~ 0 +POE_A $Sheet S 3300 3150 950 1000 U 5D42E225 F0 "3.3V_0" 50 F1 "rt7272_dcdc_3v3.sch" 50 F2 "ENABLE" I L 3300 3950 50 -F3 "12V" B L 3300 3300 50 -F4 "3.3V" B R 4250 3300 50 +F3 "3.3V" B R 4250 3300 50 +F4 "VCC" B L 3300 3300 50 $EndSheet $Comp L Device:R R60 @@ -121,8 +111,8 @@ U 5D4FC17D F0 "5V_0" 50 F1 "rt7272_dcdc_5v.sch" 50 F2 "ENABLE" I L 8250 2250 50 -F3 "12V" B L 8250 1600 50 -F4 "5V" B R 9250 1600 50 +F3 "5V" B R 9250 1600 50 +F4 "VCC" B L 8250 1600 50 $EndSheet Wire Wire Line 8250 1600 6800 1600 @@ -136,8 +126,8 @@ U 5D4FE12B F0 "5V_1" 50 F1 "rt7272_dcdc_5v.sch" 50 F2 "ENABLE" I L 8250 3950 50 -F3 "12V" B L 8250 3300 50 -F4 "5V" B R 9250 3300 50 +F3 "5V" B R 9250 3300 50 +F4 "VCC" B L 8250 3300 50 $EndSheet $Comp L Device:R R18 @@ -206,8 +196,8 @@ U 5D4FEB2F F0 "5V_2" 50 F1 "rt7272_dcdc_5v.sch" 50 F2 "ENABLE" I L 8250 5950 50 -F3 "12V" B L 8250 5300 50 -F4 "5V" B R 9250 5300 50 +F3 "5V" B R 9250 5300 50 +F4 "VCC" B L 8250 5300 50 $EndSheet Wire Wire Line 8250 5300 6800 5300 @@ -228,207 +218,237 @@ Wire Wire Line $Comp L Device:D_Schottky D13 U 1 1 5D502FE5 -P 2200 900 -F 0 "D13" H 2200 684 50 0000 C CNN -F 1 "MBRS540T3" H 2200 775 50 0000 C CNN -F 2 "LibreRouter_MegaBoard:SMC" H 2200 900 50 0001 C CNN -F 3 "~" H 2200 900 50 0001 C CNN -F 4 "ON Semiconductor" H 2200 900 50 0001 C CNN "Manufacturer" -F 5 "MBRS540T3G" H 2200 900 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 2200 900 50 0001 C CNN "Supplier" -F 7 "MBRS540T3GOSDKR-ND" H 2200 900 50 0001 C CNN "Supplier PN" - 1 2200 900 +P 2150 1400 +F 0 "D13" H 2150 1184 50 0000 C CNN +F 1 "MBRS540T3" H 2150 1275 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:SMC" H 2150 1400 50 0001 C CNN +F 3 "~" H 2150 1400 50 0001 C CNN +F 4 "ON Semiconductor" H 2150 1400 50 0001 C CNN "Manufacturer" +F 5 "MBRS540T3G" H 2150 1400 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 2150 1400 50 0001 C CNN "Supplier" +F 7 "MBRS540T3GOSDKR-ND" H 2150 1400 50 0001 C CNN "Supplier PN" + 1 2150 1400 -1 0 0 1 $EndComp $Comp L Device:D_TVS D25 U 1 1 5D5030DB -P 3650 1450 -F 0 "D25" V 3604 1529 50 0000 L CNN -F 1 "SMBJ40CA" V 3695 1529 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:DO-214AA" H 3650 1450 50 0001 C CNN -F 3 "~" H 3650 1450 50 0001 C CNN -F 4 "Littelfuse Inc." H 3650 1450 50 0001 C CNN "Manufacturer" -F 5 "SMBJ40CA" H 3650 1450 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 3650 1450 50 0001 C CNN "Supplier" -F 7 "SMBJ40CALFDKR-ND" H 3650 1450 50 0001 C CNN "Supplier PN" - 1 3650 1450 +P 3600 1750 +F 0 "D25" V 3554 1829 50 0000 L CNN +F 1 "SMBJ40CA" V 3645 1829 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:DO-214AA" H 3600 1750 50 0001 C CNN +F 3 "~" H 3600 1750 50 0001 C CNN +F 4 "Littelfuse Inc." H 3600 1750 50 0001 C CNN "Manufacturer" +F 5 "SMBJ40CA" H 3600 1750 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 3600 1750 50 0001 C CNN "Supplier" +F 7 "SMBJ40CALFDKR-ND" H 3600 1750 50 0001 C CNN "Supplier PN" + 1 3600 1750 0 1 1 0 $EndComp $Comp L Device:D_Schottky D2 U 1 1 5D503196 -P 4450 1450 -F 0 "D2" V 4404 1529 50 0000 L CNN -F 1 "SS14" V 4495 1529 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:DO214AC" H 4450 1450 50 0001 C CNN -F 3 "~" H 4450 1450 50 0001 C CNN -F 4 "ON Semiconductor" H 4450 1450 50 0001 C CNN "Manufacturer" -F 5 "SS14" H 4450 1450 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 4450 1450 50 0001 C CNN "Supplier" -F 7 "SS14CT-ND" H 4450 1450 50 0001 C CNN "Supplier PN" - 1 4450 1450 +P 4400 1750 +F 0 "D2" V 4354 1829 50 0000 L CNN +F 1 "SS14" V 4445 1829 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:DO214AC" H 4400 1750 50 0001 C CNN +F 3 "~" H 4400 1750 50 0001 C CNN +F 4 "ON Semiconductor" H 4400 1750 50 0001 C CNN "Manufacturer" +F 5 "SS14" H 4400 1750 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 4400 1750 50 0001 C CNN "Supplier" +F 7 "SS14CT-ND" H 4400 1750 50 0001 C CNN "Supplier PN" + 1 4400 1750 0 1 1 0 $EndComp $Comp L Device:CP C76 U 1 1 5D503338 -P 5150 1450 -F 0 "C76" H 5300 1450 50 0000 L CNN -F 1 "1000uF, 35V" H 5200 1350 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:E3,5-10" H 5188 1300 50 0001 C CNN -F 3 "~" H 5150 1450 50 0001 C CNN -F 4 "DigiKey" H 5150 1450 50 0001 C CNN "Supplier" -F 5 "Rubycon" H 5150 1450 50 0001 C CNN "Manufacturer" -F 6 "35PX1000MEFC10X20" H 5150 1450 50 0001 C CNN "Manufacturer PN" -F 7 "1189-1745-ND" H 5150 1450 50 0001 C CNN "Supplier PN" - 1 5150 1450 +P 5100 1750 +F 0 "C76" H 5250 1750 50 0000 L CNN +F 1 "1000uF, 35V" H 5150 1650 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:E3,5-10" H 5138 1600 50 0001 C CNN +F 3 "~" H 5100 1750 50 0001 C CNN +F 4 "DigiKey" H 5100 1750 50 0001 C CNN "Supplier" +F 5 "Rubycon" H 5100 1750 50 0001 C CNN "Manufacturer" +F 6 "35PX1000MEFC10X20" H 5100 1750 50 0001 C CNN "Manufacturer PN" +F 7 "1189-1745-ND" H 5100 1750 50 0001 C CNN "Supplier PN" + 1 5100 1750 1 0 0 -1 $EndComp $Comp L Device:D_Schottky D14 U 1 1 5D5033BC -P 2200 1400 -F 0 "D14" H 2200 1184 50 0000 C CNN -F 1 "MBRS540T3" H 2200 1275 50 0000 C CNN -F 2 "LibreRouter_MegaBoard:SMC" H 2200 1400 50 0001 C CNN -F 3 "~" H 2200 1400 50 0001 C CNN -F 4 "ON Semiconductor" H 2200 1400 50 0001 C CNN "Manufacturer" -F 5 "MBRS540T3G" H 2200 1400 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 2200 1400 50 0001 C CNN "Supplier" -F 7 "MBRS540T3GOSDKR-ND" H 2200 1400 50 0001 C CNN "Supplier PN" - 1 2200 1400 +P 2150 1900 +F 0 "D14" H 2150 1684 50 0000 C CNN +F 1 "MBRS540T3" H 2150 1775 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:SMC" H 2150 1900 50 0001 C CNN +F 3 "~" H 2150 1900 50 0001 C CNN +F 4 "ON Semiconductor" H 2150 1900 50 0001 C CNN "Manufacturer" +F 5 "MBRS540T3G" H 2150 1900 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 2150 1900 50 0001 C CNN "Supplier" +F 7 "MBRS540T3GOSDKR-ND" H 2150 1900 50 0001 C CNN "Supplier PN" + 1 2150 1900 -1 0 0 1 $EndComp $Comp L power:GND #PWR0135 U 1 1 5D503417 -P 3650 1800 -F 0 "#PWR0135" H 3650 1550 50 0001 C CNN -F 1 "GND" H 3655 1627 50 0000 C CNN -F 2 "" H 3650 1800 50 0001 C CNN -F 3 "" H 3650 1800 50 0001 C CNN - 1 3650 1800 +P 3600 2100 +F 0 "#PWR0135" H 3600 1850 50 0001 C CNN +F 1 "GND" H 3605 1927 50 0000 C CNN +F 2 "" H 3600 2100 50 0001 C CNN +F 3 "" H 3600 2100 50 0001 C CNN + 1 3600 2100 1 0 0 -1 $EndComp $Comp L power:GND #PWR0136 U 1 1 5D50343B -P 4450 1800 -F 0 "#PWR0136" H 4450 1550 50 0001 C CNN -F 1 "GND" H 4455 1627 50 0000 C CNN -F 2 "" H 4450 1800 50 0001 C CNN -F 3 "" H 4450 1800 50 0001 C CNN - 1 4450 1800 +P 4400 2100 +F 0 "#PWR0136" H 4400 1850 50 0001 C CNN +F 1 "GND" H 4405 1927 50 0000 C CNN +F 2 "" H 4400 2100 50 0001 C CNN +F 3 "" H 4400 2100 50 0001 C CNN + 1 4400 2100 1 0 0 -1 $EndComp $Comp L power:GND #PWR0137 U 1 1 5D503458 -P 5150 1800 -F 0 "#PWR0137" H 5150 1550 50 0001 C CNN -F 1 "GND" H 5155 1627 50 0000 C CNN -F 2 "" H 5150 1800 50 0001 C CNN -F 3 "" H 5150 1800 50 0001 C CNN - 1 5150 1800 +P 5100 2100 +F 0 "#PWR0137" H 5100 1850 50 0001 C CNN +F 1 "GND" H 5105 1927 50 0000 C CNN +F 2 "" H 5100 2100 50 0001 C CNN +F 3 "" H 5100 2100 50 0001 C CNN + 1 5100 2100 1 0 0 -1 $EndComp $Comp L Device:Polyfuse L1 U 1 1 5D503666 -P 4100 1100 -F 0 "L1" V 3875 1100 50 0000 C CNN -F 1 "4A, GR30-400" V 3966 1100 50 0000 C CNN -F 2 "LibreRouter_MegaBoard:GR72-135" H 4150 900 50 0001 L CNN -F 3 "~" H 4100 1100 50 0001 C CNN -F 4 "Littelfuse Inc." H 4100 1100 50 0001 C CNN "Manufacturer" -F 5 "RUEF400-2" H 4100 1100 50 0001 C CNN "Manufacturer PN" -F 6 "DigiKey" H 4100 1100 50 0001 C CNN "Supplier" -F 7 "RUEF400-2HFCT-ND" H 4100 1100 50 0001 C CNN "Supplier PN" - 1 4100 1100 +P 4050 1400 +F 0 "L1" V 3825 1400 50 0000 C CNN +F 1 "4A, GR30-400" V 3916 1400 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:GR72-135" H 4100 1200 50 0001 L CNN +F 3 "~" H 4050 1400 50 0001 C CNN +F 4 "Littelfuse Inc." H 4050 1400 50 0001 C CNN "Manufacturer" +F 5 "RUEF400-2" H 4050 1400 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 4050 1400 50 0001 C CNN "Supplier" +F 7 "RUEF400-2HFCT-ND" H 4050 1400 50 0001 C CNN "Supplier PN" + 1 4050 1400 0 1 1 0 $EndComp $Comp L BC301N-D:BC301N-D U? U 1 1 5D504AD9 -P 2900 1450 +P 2850 1750 AR Path="/5D504AD9" Ref="U?" Part="1" AR Path="/5D0328DE/5D504AD9" Ref="V1" Part="1" -F 0 "V1" H 3086 1496 50 0000 L CNN -F 1 "BC301N-D" H 3086 1405 50 0000 L CNN -F 2 "LibreRouter_MegaBoard:BC301N-D" H 2900 1450 50 0001 C CNN -F 3 "" H 2900 1450 50 0001 C CNN -F 4 "Bincheng Electronics" H 2900 1450 50 0001 C CNN "Manufacturer" -F 5 "BC301N-D" H 2900 1450 50 0001 C CNN "Manufacturer PN" - 1 2900 1450 +F 0 "V1" H 3036 1796 50 0000 L CNN +F 1 "BC301N-D" H 3036 1705 50 0000 L CNN +F 2 "LibreRouter_MegaBoard:BC301N-D" H 2850 1750 50 0001 C CNN +F 3 "" H 2850 1750 50 0001 C CNN +F 4 "Bincheng Electronics" H 2850 1750 50 0001 C CNN "Manufacturer" +F 5 "BC301N-D" H 2850 1750 50 0001 C CNN "Manufacturer PN" + 1 2850 1750 1 0 0 -1 $EndComp $Comp L power:GND #PWR0138 U 1 1 5D505643 -P 2900 1800 -F 0 "#PWR0138" H 2900 1550 50 0001 C CNN -F 1 "GND" H 2905 1627 50 0000 C CNN -F 2 "" H 2900 1800 50 0001 C CNN -F 3 "" H 2900 1800 50 0001 C CNN - 1 2900 1800 +P 2850 2100 +F 0 "#PWR0138" H 2850 1850 50 0001 C CNN +F 1 "GND" H 2855 1927 50 0000 C CNN +F 2 "" H 2850 2100 50 0001 C CNN +F 3 "" H 2850 2100 50 0001 C CNN + 1 2850 2100 1 0 0 -1 $EndComp Wire Wire Line - 4250 1100 4450 1100 -Wire Wire Line - 5150 1100 5150 1300 -Wire Wire Line - 4450 1300 4450 1100 -Connection ~ 4450 1100 + 4200 1400 4400 1400 Wire Wire Line - 4450 1100 5150 1100 + 5100 1400 5100 1600 Wire Wire Line - 5150 1800 5150 1600 + 4400 1600 4400 1400 +Connection ~ 4400 1400 Wire Wire Line - 4450 1600 4450 1800 + 4400 1400 5100 1400 Wire Wire Line - 5150 1100 5400 1100 -Connection ~ 5150 1100 + 5100 2100 5100 1900 Wire Wire Line - 3950 1100 3650 1100 + 4400 1900 4400 2100 Wire Wire Line - 2900 1100 2900 1200 -Connection ~ 2900 1100 + 5100 1400 5350 1400 +Connection ~ 5100 1400 Wire Wire Line - 2500 1100 2500 1400 + 3900 1400 3600 1400 Wire Wire Line - 2500 1400 2350 1400 -Connection ~ 2500 1100 + 2850 1400 2850 1500 +Connection ~ 2850 1400 Wire Wire Line - 2500 1100 2900 1100 + 2450 1900 2300 1900 Wire Wire Line - 2350 900 2500 900 + 2450 1400 2850 1400 Wire Wire Line - 2500 900 2500 1100 + 2300 1400 2450 1400 Wire Wire Line - 1550 900 2050 900 + 1500 1400 2000 1400 Wire Wire Line - 1550 1400 2050 1400 + 1500 1900 2000 1900 Wire Wire Line - 2900 1700 2900 1800 + 2850 2000 2850 2100 Wire Wire Line - 3650 1600 3650 1800 + 3600 1900 3600 2100 Wire Wire Line - 3650 1300 3650 1100 -Connection ~ 3650 1100 + 3600 1600 3600 1400 +Connection ~ 3600 1400 Wire Wire Line - 3650 1100 2900 1100 -Text Label 5250 1100 0 50 ~ 0 -12V + 3600 1400 2850 1400 +Text Label 5200 1400 0 50 ~ 0 +VCC Text Label 6800 1600 0 50 ~ 0 -12V +VCC Text Label 6800 3300 0 50 ~ 0 -12V +VCC Text Label 6800 5300 0 50 ~ 0 -12V +VCC Text Label 1850 5300 0 50 ~ 0 -12V +VCC Text Label 1850 3300 0 50 ~ 0 -12V +VCC +Text HLabel 1500 900 0 50 BiDi ~ 0 +POE_B +$Comp +L Device:D_Schottky D26 +U 1 1 5E6FC475 +P 2150 900 +F 0 "D26" H 2150 684 50 0000 C CNN +F 1 "MBRS540T3" H 2150 775 50 0000 C CNN +F 2 "LibreRouter_MegaBoard:SMC" H 2150 900 50 0001 C CNN +F 3 "~" H 2150 900 50 0001 C CNN +F 4 "ON Semiconductor" H 2150 900 50 0001 C CNN "Manufacturer" +F 5 "MBRS540T3G" H 2150 900 50 0001 C CNN "Manufacturer PN" +F 6 "DigiKey" H 2150 900 50 0001 C CNN "Supplier" +F 7 "MBRS540T3GOSDKR-ND" H 2150 900 50 0001 C CNN "Supplier PN" + 1 2150 900 + -1 0 0 1 +$EndComp +Wire Wire Line + 2300 900 2450 900 +Wire Wire Line + 1500 900 2000 900 +Connection ~ 2450 1400 +Wire Wire Line + 2450 1400 2450 1900 +Wire Wire Line + 2450 900 2450 1400 +$Sheet +S 3300 5150 950 1000 +U 5D42CD47 +F0 "3.3V_1" 50 +F1 "rt7272_dcdc_3v3.sch" 50 +F2 "ENABLE" I L 3300 5950 50 +F3 "3.3V" B R 4250 5300 50 +F4 "VCC" B L 3300 5300 50 +$EndSheet $EndSCHEMATC diff --git a/designs/mega_board/rt7272_dcdc_3v3.sch b/designs/mega_board/rt7272_dcdc_3v3.sch index 173f6c7..2e5533b 100644 --- a/designs/mega_board/rt7272_dcdc_3v3.sch +++ b/designs/mega_board/rt7272_dcdc_3v3.sch @@ -1,10 +1,9 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 6 14 +Sheet 9 14 Title "" Date "" Rev "" @@ -21,7 +20,7 @@ P 5600 3500 AR Path="/5D0328DE/5D42CD47/5D42D1B4" Ref="U2" Part="1" AR Path="/5D0328DE/5D42E225/5D42D1B4" Ref="U6" Part="1" AR Path="/5D42D1B4" Ref="U?" Part="1" -F 0 "U4" H 5600 4015 50 0000 C CNN +F 0 "U2" H 5600 4015 50 0000 C CNN F 1 "RT7272" H 5600 3924 50 0000 C CNN F 2 "LibreRouter_MegaBoard:RT8250-SOP8" H 5600 3500 50 0001 C CNN F 3 "" H 5600 3500 50 0001 C CNN @@ -38,7 +37,7 @@ U 1 1 5D42D229 P 3350 3450 AR Path="/5D0328DE/5D42CD47/5D42D229" Ref="C29" Part="1" AR Path="/5D0328DE/5D42E225/5D42D229" Ref="C15" Part="1" -F 0 "C53" H 3500 3450 50 0000 L CNN +F 0 "C29" H 3500 3450 50 0000 L CNN F 1 "10uF, 35V" H 3400 3350 50 0000 L CNN F 2 "LibreRouter_MegaBoard:C0805" H 3388 3300 50 0001 C CNN F 3 "~" H 3350 3450 50 0001 C CNN @@ -55,7 +54,7 @@ U 1 1 5D42D2DE P 4400 3650 AR Path="/5D0328DE/5D42CD47/5D42D2DE" Ref="R19" Part="1" AR Path="/5D0328DE/5D42E225/5D42D2DE" Ref="R58" Part="1" -F 0 "R13" H 4470 3696 50 0000 L CNN +F 0 "R19" H 4470 3696 50 0000 L CNN F 1 "180k" H 4470 3605 50 0000 L CNN F 2 "LibreRouter_MegaBoard:R0402" V 4330 3650 50 0001 C CNN F 3 "~" H 4400 3650 50 0001 C CNN @@ -72,7 +71,7 @@ U 1 1 5D42D3B9 P 7450 3350 AR Path="/5D0328DE/5D42CD47/5D42D3B9" Ref="L2" Part="1" AR Path="/5D0328DE/5D42E225/5D42D3B9" Ref="L8" Part="1" -F 0 "L3" V 7675 3350 50 0000 C CNN +F 0 "L2" V 7675 3350 50 0000 C CNN F 1 "6.8uH, SWPA6045S6R8MT" V 7600 3150 50 0000 C CNN F 2 "LibreRouter_MegaBoard:SWPA6028S" H 7450 3350 50 0001 C CNN F 3 "~" H 7450 3350 50 0001 C CNN @@ -89,7 +88,7 @@ U 1 1 5D42D488 P 6400 3100 AR Path="/5D0328DE/5D42CD47/5D42D488" Ref="C13" Part="1" AR Path="/5D0328DE/5D42E225/5D42D488" Ref="C12" Part="1" -F 0 "C30" V 6148 3100 50 0000 C CNN +F 0 "C13" V 6148 3100 50 0000 C CNN F 1 "0.1uF, 10V" V 6239 3100 50 0000 C CNN F 2 "LibreRouter_MegaBoard:C0402" H 6438 2950 50 0001 C CNN F 3 "~" H 6400 3100 50 0001 C CNN @@ -106,7 +105,7 @@ U 1 1 5D42D571 P 7900 3600 AR Path="/5D0328DE/5D42CD47/5D42D571" Ref="R14" Part="1" AR Path="/5D0328DE/5D42E225/5D42D571" Ref="R9" Part="1" -F 0 "R10" H 7970 3646 50 0000 L CNN +F 0 "R14" H 7970 3646 50 0000 L CNN F 1 "53.6K 1%" H 7970 3555 50 0000 L CNN F 2 "LibreRouter_MegaBoard:R0402" V 7830 3600 50 0001 C CNN F 3 "~" H 7900 3600 50 0001 C CNN @@ -123,7 +122,7 @@ U 1 1 5D42D5CB P 7900 4000 AR Path="/5D0328DE/5D42CD47/5D42D5CB" Ref="R15" Part="1" AR Path="/5D0328DE/5D42E225/5D42D5CB" Ref="R11" Part="1" -F 0 "R12" H 7970 4046 50 0000 L CNN +F 0 "R15" H 7970 4046 50 0000 L CNN F 1 "10k 1%" H 7970 3955 50 0000 L CNN F 2 "LibreRouter_MegaBoard:R0402" V 7830 4000 50 0001 C CNN F 3 "~" H 7900 4000 50 0001 C CNN @@ -140,7 +139,7 @@ U 1 1 5D42D605 P 6350 4350 AR Path="/5D0328DE/5D42CD47/5D42D605" Ref="R37" Part="1" AR Path="/5D0328DE/5D42E225/5D42D605" Ref="R59" Part="1" -F 0 "R16" H 6420 4396 50 0000 L CNN +F 0 "R37" H 6420 4396 50 0000 L CNN F 1 "24k" H 6420 4305 50 0000 L CNN F 2 "LibreRouter_MegaBoard:R0402" V 6280 4350 50 0001 C CNN F 3 "~" H 6350 4350 50 0001 C CNN @@ -157,7 +156,7 @@ U 1 1 5D42D659 P 6350 3950 AR Path="/5D0328DE/5D42CD47/5D42D659" Ref="C32" Part="1" AR Path="/5D0328DE/5D42E225/5D42D659" Ref="C16" Part="1" -F 0 "C45" H 6235 3904 50 0000 R CNN +F 0 "C32" H 6235 3904 50 0000 R CNN F 1 "2.7nF" H 6235 3995 50 0000 R CNN F 2 "LibreRouter_MegaBoard:C0402" H 6388 3800 50 0001 C CNN F 3 "~" H 6350 3950 50 0001 C CNN @@ -207,7 +206,7 @@ U 1 1 5D42DAC0 P 8550 3800 AR Path="/5D0328DE/5D42CD47/5D42DAC0" Ref="C38" Part="1" AR Path="/5D0328DE/5D42E225/5D42DAC0" Ref="C17" Part="1" -F 0 "C46" H 8400 3800 50 0000 R CNN +F 0 "C38" H 8400 3800 50 0000 R CNN F 1 "22uF, 10V" H 8500 3900 50 0000 R CNN F 2 "LibreRouter_MegaBoard:C0805" H 8588 3650 50 0001 C CNN F 3 "~" H 8550 3800 50 0001 C CNN @@ -224,7 +223,7 @@ U 1 1 5D42DBCD P 9200 3800 AR Path="/5D0328DE/5D42CD47/5D42DBCD" Ref="C28" Part="1" AR Path="/5D0328DE/5D42E225/5D42DBCD" Ref="C14" Part="1" -F 0 "C31" H 9050 3800 50 0000 R CNN +F 0 "C28" H 9050 3800 50 0000 R CNN F 1 "22uF, 10V" H 9150 3900 50 0000 R CNN F 2 "LibreRouter_MegaBoard:C0805" H 9238 3650 50 0001 C CNN F 3 "~" H 9200 3800 50 0001 C CNN @@ -241,7 +240,7 @@ U 1 1 5D42DC2B P 9850 3800 AR Path="/5D0328DE/5D42CD47/5D42DC2B" Ref="C71" Part="1" AR Path="/5D0328DE/5D42E225/5D42DC2B" Ref="C91" Part="1" -F 0 "C102" H 9700 3800 50 0000 R CNN +F 0 "C71" H 9700 3800 50 0000 R CNN F 1 "0.1uF, 10V" H 9800 3900 50 0000 R CNN F 2 "LibreRouter_MegaBoard:C0402" H 9888 3650 50 0001 C CNN F 3 "~" H 9850 3800 50 0001 C CNN @@ -258,7 +257,7 @@ U 1 1 5D42DCB2 P 10550 3800 AR Path="/5D0328DE/5D42CD47/5D42DCB2" Ref="C72" Part="1" AR Path="/5D0328DE/5D42E225/5D42DCB2" Ref="C92" Part="1" -F 0 "C92" H 10400 3800 50 0000 R CNN +F 0 "C72" H 10400 3800 50 0000 R CNN F 1 "0.1uF, 10V" H 10500 3900 50 0000 R CNN F 2 "LibreRouter_MegaBoard:C0402" H 10588 3650 50 0001 C CNN F 3 "~" H 10550 3800 50 0001 C CNN @@ -275,7 +274,7 @@ U 1 1 5D42DD90 P 7900 4250 AR Path="/5D0328DE/5D42CD47/5D42DD90" Ref="#PWR0139" Part="1" AR Path="/5D0328DE/5D42E225/5D42DD90" Ref="#PWR0145" Part="1" -F 0 "#PWR0145" H 7900 4000 50 0001 C CNN +F 0 "#PWR0139" H 7900 4000 50 0001 C CNN F 1 "GND" H 7905 4077 50 0000 C CNN F 2 "" H 7900 4250 50 0001 C CNN F 3 "" H 7900 4250 50 0001 C CNN @@ -288,7 +287,7 @@ U 1 1 5D42DDBC P 9550 4250 AR Path="/5D0328DE/5D42CD47/5D42DDBC" Ref="#PWR0140" Part="1" AR Path="/5D0328DE/5D42E225/5D42DDBC" Ref="#PWR0146" Part="1" -F 0 "#PWR0146" H 9550 4000 50 0001 C CNN +F 0 "#PWR0140" H 9550 4000 50 0001 C CNN F 1 "GND" H 9555 4077 50 0000 C CNN F 2 "" H 9550 4250 50 0001 C CNN F 3 "" H 9550 4250 50 0001 C CNN @@ -350,7 +349,7 @@ U 1 1 5D42FF27 P 6350 4600 AR Path="/5D0328DE/5D42CD47/5D42FF27" Ref="#PWR0141" Part="1" AR Path="/5D0328DE/5D42E225/5D42FF27" Ref="#PWR0147" Part="1" -F 0 "#PWR0147" H 6350 4350 50 0001 C CNN +F 0 "#PWR0141" H 6350 4350 50 0001 C CNN F 1 "GND" H 6355 4427 50 0000 C CNN F 2 "" H 6350 4600 50 0001 C CNN F 3 "" H 6350 4600 50 0001 C CNN @@ -365,7 +364,7 @@ U 1 1 5D43058C P 2700 3450 AR Path="/5D0328DE/5D42CD47/5D43058C" Ref="C36" Part="1" AR Path="/5D0328DE/5D42E225/5D43058C" Ref="C19" Part="1" -F 0 "C44" H 2850 3450 50 0000 L CNN +F 0 "C36" H 2850 3450 50 0000 L CNN F 1 "10uF, 35V" H 2750 3350 50 0000 L CNN F 2 "LibreRouter_MegaBoard:C0805" H 2738 3300 50 0001 C CNN F 3 "~" H 2700 3450 50 0001 C CNN @@ -379,7 +378,7 @@ $EndComp Text HLabel 4400 3350 0 50 Input ~ 0 ENABLE Text HLabel 2200 3250 0 50 BiDi ~ 0 -12V +VCC Text HLabel 10650 3350 2 50 BiDi ~ 0 3.3V Wire Wire Line @@ -406,7 +405,7 @@ U 1 1 5D4322E2 P 3000 3750 AR Path="/5D0328DE/5D42CD47/5D4322E2" Ref="#PWR0142" Part="1" AR Path="/5D0328DE/5D42E225/5D4322E2" Ref="#PWR0148" Part="1" -F 0 "#PWR0148" H 3000 3500 50 0001 C CNN +F 0 "#PWR0142" H 3000 3500 50 0001 C CNN F 1 "GND" H 3005 3577 50 0000 C CNN F 2 "" H 3000 3750 50 0001 C CNN F 3 "" H 3000 3750 50 0001 C CNN @@ -422,7 +421,7 @@ U 1 1 5D4323C5 P 4400 4000 AR Path="/5D0328DE/5D42CD47/5D4323C5" Ref="#PWR0143" Part="1" AR Path="/5D0328DE/5D42E225/5D4323C5" Ref="#PWR0149" Part="1" -F 0 "#PWR0149" H 4400 3750 50 0001 C CNN +F 0 "#PWR0143" H 4400 3750 50 0001 C CNN F 1 "GND" H 4405 3827 50 0000 C CNN F 2 "" H 4400 4000 50 0001 C CNN F 3 "" H 4400 4000 50 0001 C CNN @@ -435,7 +434,7 @@ U 1 1 5D4323EC P 4900 4000 AR Path="/5D0328DE/5D42CD47/5D4323EC" Ref="#PWR0144" Part="1" AR Path="/5D0328DE/5D42E225/5D4323EC" Ref="#PWR0150" Part="1" -F 0 "#PWR0150" H 4900 3750 50 0001 C CNN +F 0 "#PWR0144" H 4900 3750 50 0001 C CNN F 1 "GND" H 4905 3827 50 0000 C CNN F 2 "" H 4900 4000 50 0001 C CNN F 3 "" H 4900 4000 50 0001 C CNN diff --git a/designs/mega_board/rt7272_dcdc_5v.sch b/designs/mega_board/rt7272_dcdc_5v.sch index 4506b9b..eccce3b 100644 --- a/designs/mega_board/rt7272_dcdc_5v.sch +++ b/designs/mega_board/rt7272_dcdc_5v.sch @@ -1,10 +1,9 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 8 14 +Sheet 7 14 Title "" Date "" Rev "" @@ -366,7 +365,7 @@ $EndComp Text HLabel 3850 3450 0 50 Input ~ 0 ENABLE Text HLabel 1650 3350 0 50 BiDi ~ 0 -12V +VCC Text HLabel 10100 3450 2 50 BiDi ~ 0 5V Wire Wire Line diff --git a/designs/mega_board/watchdog.sch b/designs/mega_board/watchdog.sch index f2db0c2..404e3e9 100644 --- a/designs/mega_board/watchdog.sch +++ b/designs/mega_board/watchdog.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:LibreRouter_MegaBoard-cache EELAYER 30 0 EELAYER END $Descr A4 11693 8268 @@ -31,7 +30,7 @@ RST_J+ Text HLabel 6250 3500 2 50 Input ~ 0 RST_J- $Comp -L MCU_Microchip_ATtiny:ATtiny13-20SSU WDT1 +L LibreRouter_MegaBoard-rescue:ATtiny13-20SSU-MCU_Microchip_ATtiny WDT1 U 1 1 5D14FFA1 P 4700 3400 F 0 "WDT1" H 4750 3450 50 0000 R CNN