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lines changed Original file line number Diff line number Diff line change @@ -42,19 +42,18 @@ read_verilog -defer {{ name }}
4242read_verilog -defer -sv {{ name }}
4343{% elif attr .hdl == "vhdl" %}
4444{% if loop .first %}
45- # VHDL Generics
46- {% set generics = "-gFREQ=125000000 -gSECS=1" %}
47- ghdl {{ gflags }} {{ generics }} {{ top }}
45+ {% if params %} # VHDL Generics
46+ ghdl {{ gflags }}{% for key , value in params .items () %} -g{{ key }}={{ value }}{% endfor %} {{ top }}
47+ {% else %}
48+ ghdl {{ gflags }} {{ top }}
4849{% endif %}
4950{% endif %}
50- {% endfor %}
5151{% endif %}
52-
53- {#
54- {% if params %}# Verilog Parameters
52+ {% if loop .last and attr .hdl in ["vlog" , "slog" ] and params %} # Verilog Parameters
5553chparam{% for key , value in params .items () %} -set {{ key }} {{ value }}{% endfor %}
5654{% endif %}
57- #}
55+ {% endfor %}
56+ {% endif %}
5857
5958# Top-level specification and Syntesis
6059{% if family in ['ice40' , 'ecp5' ] %}
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