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Modify tests to be able of run pytest from project root
1 parent 6220dbd commit cc89caf

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3 files changed

+56
-36
lines changed

3 files changed

+56
-36
lines changed

Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ lint:
1111
git diff --check --cached
1212

1313
test:
14-
cd tests; pytest
14+
pytest
1515

1616
clean:
1717
py3clean .

tests/test_data.py

Lines changed: 45 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2,41 +2,59 @@
22

33
from pyfpga.vivado import Vivado
44

5+
tdir = Path(__file__).parent.resolve()
6+
57
pattern = {
68
'project': 'EXAMPLE',
79
'part': 'PARTNAME',
810
'includes': [
9-
Path('fakedata/dir1').resolve().as_posix(),
10-
Path('fakedata/dir2').resolve().as_posix(),
11-
Path('fakedata/dir3').resolve().as_posix()
11+
Path(tdir / 'fakedata/dir1').resolve().as_posix(),
12+
Path(tdir / 'fakedata/dir2').resolve().as_posix(),
13+
Path(tdir / 'fakedata/dir3').resolve().as_posix()
1214
],
1315
'files': {
14-
Path('fakedata/vhdl0.vhdl').resolve().as_posix(): {
16+
Path(tdir / 'fakedata/vhdl0.vhdl').resolve().as_posix(): {
1517
'hdl': 'vhdl', 'lib': 'LIB'
1618
},
17-
Path('fakedata/dir1/vhdl1.vhdl').resolve().as_posix(): {
19+
Path(tdir / 'fakedata/dir1/vhdl1.vhdl').resolve().as_posix(): {
1820
'hdl': 'vhdl', 'lib': 'LIB'
1921
},
20-
Path('fakedata/dir2/vhdl2.vhdl').resolve().as_posix(): {
22+
Path(tdir / 'fakedata/dir2/vhdl2.vhdl').resolve().as_posix(): {
2123
'hdl': 'vhdl', 'lib': 'LIB'
2224
},
23-
Path('fakedata/dir3/vhdl3.vhdl').resolve().as_posix(): {
25+
Path(tdir / 'fakedata/dir3/vhdl3.vhdl').resolve().as_posix(): {
2426
'hdl': 'vhdl', 'lib': 'LIB'
2527
},
26-
Path('fakedata/vlog0.v').resolve().as_posix(): {'hdl': 'vlog'},
27-
Path('fakedata/dir1/vlog1.v').resolve().as_posix(): {'hdl': 'vlog'},
28-
Path('fakedata/dir2/vlog2.v').resolve().as_posix(): {'hdl': 'vlog'},
29-
Path('fakedata/dir3/vlog3.v').resolve().as_posix(): {'hdl': 'vlog'},
30-
Path('fakedata/slog0.sv').resolve().as_posix(): {'hdl': 'slog'},
31-
Path('fakedata/dir1/slog1.sv').resolve().as_posix(): {'hdl': 'slog'},
32-
Path('fakedata/dir2/slog2.sv').resolve().as_posix(): {'hdl': 'slog'},
33-
Path('fakedata/dir3/slog3.sv').resolve().as_posix(): {'hdl': 'slog'}
28+
Path(tdir / 'fakedata/vlog0.v').resolve().as_posix(): {
29+
'hdl': 'vlog'
30+
},
31+
Path(tdir / 'fakedata/dir1/vlog1.v').resolve().as_posix(): {
32+
'hdl': 'vlog'
33+
},
34+
Path(tdir / 'fakedata/dir2/vlog2.v').resolve().as_posix(): {
35+
'hdl': 'vlog'
36+
},
37+
Path(tdir / 'fakedata/dir3/vlog3.v').resolve().as_posix(): {
38+
'hdl': 'vlog'
39+
},
40+
Path(tdir / 'fakedata/slog0.sv').resolve().as_posix(): {
41+
'hdl': 'slog'
42+
},
43+
Path(tdir / 'fakedata/dir1/slog1.sv').resolve().as_posix(): {
44+
'hdl': 'slog'
45+
},
46+
Path(tdir / 'fakedata/dir2/slog2.sv').resolve().as_posix(): {
47+
'hdl': 'slog'
48+
},
49+
Path(tdir / 'fakedata/dir3/slog3.sv').resolve().as_posix(): {
50+
'hdl': 'slog'
51+
}
3452
},
3553
'top': 'TOPNAME',
3654
'constraints': {
37-
Path('fakedata/cons/all.xdc').resolve().as_posix(): 'all',
38-
Path('fakedata/cons/syn.xdc').resolve().as_posix(): 'syn',
39-
Path('fakedata/cons/par.xdc').resolve().as_posix(): 'par'
55+
Path(tdir / 'fakedata/cons/all.xdc').resolve().as_posix(): 'all',
56+
Path(tdir / 'fakedata/cons/syn.xdc').resolve().as_posix(): 'syn',
57+
Path(tdir / 'fakedata/cons/par.xdc').resolve().as_posix(): 'par'
4058
},
4159
'params': {
4260
'PAR1': 'VAL1',
@@ -65,15 +83,15 @@ def test_data():
6583
prj = Vivado('EXAMPLE')
6684
prj.set_part('PARTNAME')
6785
prj.set_top('TOPNAME')
68-
prj.add_include('fakedata/dir1')
69-
prj.add_include('fakedata/dir2')
70-
prj.add_include('fakedata/dir3')
71-
prj.add_slog('fakedata/**/*.sv')
72-
prj.add_vhdl('fakedata/**/*.vhdl', 'LIB')
73-
prj.add_vlog('fakedata/**/*.v')
74-
prj.add_cons('fakedata/cons/all.xdc')
75-
prj.add_cons('fakedata/cons/syn.xdc', 'syn')
76-
prj.add_cons('fakedata/cons/par.xdc', 'par')
86+
prj.add_include(str(tdir / 'fakedata/dir1'))
87+
prj.add_include(str(tdir / 'fakedata/dir2'))
88+
prj.add_include(str(tdir / 'fakedata/dir3'))
89+
prj.add_slog(str(tdir / 'fakedata/**/*.sv'))
90+
prj.add_vhdl(str(tdir / 'fakedata/**/*.vhdl'), 'LIB')
91+
prj.add_vlog(str(tdir / 'fakedata/**/*.v'))
92+
prj.add_cons(str(tdir / 'fakedata/cons/all.xdc'))
93+
prj.add_cons(str(tdir / 'fakedata/cons/syn.xdc'), 'syn')
94+
prj.add_cons(str(tdir / 'fakedata/cons/par.xdc'), 'par')
7795
prj.add_param('PAR1', 'VAL1')
7896
prj.add_param('PAR2', 'VAL2')
7997
prj.add_param('PAR3', 'VAL3')

tests/test_tools.py

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
from pathlib import Path
22
from pyfpga.factory import Factory
33

4+
tdir = Path(__file__).parent.resolve()
5+
46

57
def test_ise():
68
tool = 'ise'
@@ -45,15 +47,15 @@ def generate(tool, part):
4547
prj = Factory(tool, odir=f'results/{tool}')
4648
prj.set_part(part)
4749
prj.set_top('TOPNAME')
48-
prj.add_include('fakedata/dir1')
49-
prj.add_include('fakedata/dir2')
50+
prj.add_include(str(tdir / 'fakedata/dir1'))
51+
prj.add_include(str(tdir / 'fakedata/dir2'))
5052
if tool != 'ise':
51-
prj.add_slog('fakedata/**/*.sv')
52-
prj.add_vhdl('fakedata/**/*.vhdl', 'LIB')
53-
prj.add_vlog('fakedata/**/*.v')
54-
prj.add_cons('fakedata/cons/all.xdc')
55-
prj.add_cons('fakedata/cons/syn.xdc', 'syn')
56-
prj.add_cons('fakedata/cons/par.xdc', 'par')
53+
prj.add_slog(str(tdir / 'fakedata/**/*.sv'))
54+
prj.add_vhdl(str(tdir / 'fakedata/**/*.vhdl'), 'LIB')
55+
prj.add_vlog(str(tdir / 'fakedata/**/*.v'))
56+
prj.add_cons(str(tdir / 'fakedata/cons/all.xdc'))
57+
prj.add_cons(str(tdir / 'fakedata/cons/syn.xdc'), 'syn')
58+
prj.add_cons(str(tdir / 'fakedata/cons/par.xdc'), 'par')
5759
prj.add_param('PAR1', 'VAL1')
5860
prj.add_param('PAR2', 'VAL2')
5961
prj.add_define('DEF1', 'VAL1')

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