diff --git a/.gitignore b/.gitignore index d70f0cd5e..68bb5bfbd 100644 --- a/.gitignore +++ b/.gitignore @@ -36,6 +36,9 @@ host/tests/Makefile docs/_build *.vcd tests/results.xml +sim_build +Makefile +*.out examples/lx9/device/src/SiTCP # PyDev files diff --git a/README.md b/README.md new file mode 100644 index 000000000..2e3b50c7d --- /dev/null +++ b/README.md @@ -0,0 +1,64 @@ +# Basil + +[![Build status](https://github.com/SiLab-Bonn/basil/workflows/Regression%20Tests/badge.svg)](https://github.com/silab-bonn/basil/actions?query=workflow%3A%22Regression+Tests%22) +[![Documentation](https://readthedocs.org/projects/basil/badge/?version=latest)](http://basil.rtfd.org) + +Basil is a modular data acquisition (DAQ) framework developed by [SiLab](https://silab-bonn.github.io/) for the characterization of [monolithic](https://en.wikipedia.org/wiki/Monolithic_active_pixel_sensor) and [hybrid](https://en.wikipedia.org/wiki/Hybrid_pixel_detector) pixel detectors. It comprises a library of HDL modules (written in Verilog) for custom FPGA readout boards, paired with a collection of Python code that control the hardware over USB, Ethernet, or serial interfaces from a host PC. Basil also includes Python drivers for common lab instruments such as power supplies, oscilloscopes, and other bench equipment. + +## Features + +**Firmware:** +- Very simple single master bus definition +- Multiple basic modules (SPI, SEQ, GPIO, I2C, JTAG) +- Multiple interfaces (UART, USB2, USB3, Ethernet) + +**Software:** +- Layer structure following hardware +- Generation based on YAML file +- Register abstract layer (RAL) +- Simulator interface allows software test against simulated RTL (thanks to [cocotb](https://github.com/cocotb/cocotb)) + +## Installation + +Install via PyPI: + +```bash +pip install basil-daq +``` + +> **Note:** The PyPI package may be outdated. Installing from source (below) is recommended to get the latest version. + +Or install from source: + +```bash +git clone https://github.com/SiLab-Bonn/basil.git +cd basil +pip install -e . +``` + +## Support + +Please use GitHub's [issue tracker](https://github.com/SiLab-Bonn/basil/issues) for bug reports/feature requests/questions. + +*For CERN users*: Feel free to subscribe to the [basil mailing list](https://e-groups.cern.ch/e-groups/EgroupsSubscription.do?egroupName=basil-devel). + +## Documentation + +Documentation can be found at: https://basil.rtfd.org + +## Example Projects + +- [TJ-Monopix2](https://github.com/SiLab-Bonn/tj-monopix2-daq) - DAQ for TJ-Monopix2 depleted monolithic pixel sensor +- [BDAQ53](https://gitlab.cern.ch/silab/bdaq53) - Readout system for ATLAS ITkPix (RD53) chips +- [LF-Monopix2](https://github.com/SiLab-Bonn/lf-monopix2-daq) - DAQ for LF-Monopix2 depleted monolithic pixel sensor +- [FRIDA](https://github.com/kcaisley/frida) - DAQ for FRIDA, an ADC test array for frame-based imaging detectors + +## License + +If not stated otherwise: + +**Host Software:** +The host software is distributed under the BSD 3-Clause ("BSD New" or "BSD Simplified") License. + +**FPGA Firmware:** +The FPGA code is distributed under the GNU Lesser General Public License, version 3.0 (LGPLv3). diff --git a/README.rst b/README.rst deleted file mode 100644 index 35add651f..000000000 --- a/README.rst +++ /dev/null @@ -1,78 +0,0 @@ -=============================================== -Basil -=============================================== - -|gha-status| |rtd-status| - -.. |gha-status| image:: https://github.com/SiLab-Bonn/basil/workflows/Regression%20Tests/badge.svg - :target: https://github.com/silab-bonn/basil/actions?query=workflow%3A%22Regression+Tests%22 - :alt: Build status - -.. |rtd-status| image:: https://readthedocs.org/projects/basil/badge/?version=latest - :target: http://basil.rtfd.org - :alt: Documentation - -Basil is a modular data acquisition (DAQ) framework developed by `SiLab `_ for the characterization of `monolithic `_ and `hybrid `_ pixel detectors. It comprises a library of HDL modules (written in Verilog) for custom FPGA readout boards, paired with a collection of Python code that control the hardware over USB, Ethernet, or serial interfaces from a host PC. Basil also includes Python drivers for common lab instruments such as power supplies, oscilloscopes, and other bench equipment. - -Features -======== -Firmware: - - very simple single master bus definition - - multiple basic modules (SPI, SEQ, GPIO, I2C, JTAG) - - multiple interfaces (UART, USB2, USB3, Ethernet) -Software: - - layer structure following hardware - - generation based on yaml file - - register abstract layer (RAL) - - simulator interface allows software test against simulated RTL (thanks to `cocotb `_) - -Installation -============ - -Install via PyPI: - -.. code-block:: bash - - pip install basil-daq - -.. note:: - - The PyPI package may be outdated. Installing from source (below) is recommended to get the latest version. - -Or install from source: - -.. code-block:: bash - - git clone https://github.com/SiLab-Bonn/basil.git - cd basil - pip install -e . - -Support -======= - -Please use GitHub's `issue tracker `_ for bug reports/feature requests/questions. - -*For CERN users*: Feel free to subscribe to the `basil mailing list `_ - -Documentation -============= - -Documentation can be found under: https://basil.rtfd.org - -Example Projects -================ -- `TJ-Monopix2 `_ - DAQ for TJ-Monopix2 depleted monolithic pixel sensor -- `BDAQ53 `_ - Readout system for ATLAS ITkPix (RD53) chips -- `LF-Monopix2 `_ - DAQ for LF-Monopix2 depleted monolithic pixel sensor -- `FRIDA `_ - DAQ for FRIDA, an ADC test array for frame-based imaging detectors - -License -======= - -If not stated otherwise. - -Host Software: - The host software is distributed under the BSD 3-Clause ("BSD New" or "BSD Simplified") License. - -FPGA Firmware: - The FPGA code is distributed under the GNU Lesser General Public License, version 3.0 (LGPLv3). diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index a41a0a9b1..085b81b67 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -4,33 +4,100 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # +"""Fast SPI receive interface for reading variable-width serial data. + +Provides a register-level hardware layer to arm/disarm capture, query +frame-size configuration, check for lost words, and parse 32-bit FIFO +words into (identifier, frame_counter, spi_data) tuples. +""" from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class fast_spi_rx(RegisterHardwareLayer): - """Fast SPI interface""" + """Fast SPI interface with variable data width support. + + The module outputs 32-bit words containing: + - IDENTIFIER (4 bits) + - Frame counter (28 - DATA_SIZE bits) + - SPI data (DATA_SIZE bits) + + The DATA_SIZE parameter must match the DATA_SIZE parameter used in the + FPGA firmware (fast_spi_rx_core.v). + + Captured data is read via the dedicated FIFO output ports (not the register + bus). At the system level, these feed into a SiTCP FIFO stream accessed + through daq["fifo0"].get_data(). + """ _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, "VERSION": {"descr": {"addr": 0, "size": 8, "properties": ["ro"]}}, "EN": {"descr": {"addr": 2, "size": 1, "offset": 0}}, "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, + "DATA_SIZE": {"descr": {"addr": 4, "size": 8, "properties": ["ro"]}}, } - _require_version = "==0" + _require_version = "==1" def __init__(self, intf, conf): + """Initialize the fast_spi_rx hardware layer. + + Args: + intf: The low-level interface to the hardware. + conf: Configuration dictionary passed to the base class. + + """ super(fast_spi_rx, self).__init__(intf, conf) + def get_size(self): + """Return the DATA_SIZE (SPI data width in bits) used for parsing captured words. + + Reads the value from the hardware DATA_SIZE register (addr 4). + """ + return self.DATA_SIZE + def reset(self): - """Soft reset the module.""" + """Soft reset the module. Clears internal counters and shift registers on the next SEQ_CLK edge.""" self.RESET = 0 def set_en(self, value): + """Arm/disarm capture. + + When enabled, serial data on SDI is captured on each rising edge of + SEQ_CLK while SEN is high. + """ self.EN = value def get_en(self): + """Return whether capture is armed (True) or disarmed (False).""" return self.EN def get_lost_count(self): + """Return the count of lost data words due to CDC FIFO overflow. + + Non-zero indicates the capture rate exceeded the readout rate. + """ return self.LOST_COUNT + + def parse_word(self, word): + """Parse a 32-bit FIFO word into (identifier, frame_counter, spi_data). + + The split between frame counter and captured data is determined + by get_size(). Useful for parsing words read via daq["fifo0"].get_data(). + + Args: + word: A 32-bit integer from the fast_spi_rx output FIFO. + + Returns: + tuple: (identifier, frame_counter, spi_data) + + """ + data_size = self.get_size() + identifier = (word >> 28) & 0xF + spi_data = word & ((1 << data_size) - 1) + frame_counter_bits = 28 - data_size + if frame_counter_bits > 0: + frame_counter = (word >> data_size) & ((1 << frame_counter_bits) - 1) + else: + frame_counter = 0 + return identifier, frame_counter, spi_data diff --git a/basil/HL/gpio.py b/basil/HL/gpio.py index 17222415b..7c82fd339 100644 --- a/basil/HL/gpio.py +++ b/basil/HL/gpio.py @@ -5,13 +5,16 @@ # ------------------------------------------------------------ # +"""GPIO hardware layer for Basil.""" + from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class gpio(RegisterHardwareLayer): - """GPIO interface""" + """GPIO interface.""" def __init__(self, intf, conf): + """Initialize GPIO interface.""" self._registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, "VERSION": {"descr": {"addr": 0, "size": 8, "properties": ["ro"]}}, @@ -35,6 +38,7 @@ def __init__(self, intf, conf): super(gpio, self).__init__(intf, conf) def init(self): + """Initialize the hardware.""" super(gpio, self).init() if "output_en" in self._init: self.OUTPUT_EN = self._init["output_en"] @@ -44,13 +48,17 @@ def reset(self): self.RESET = 0 def set_output_en(self, value): + """Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" self.OUTPUT_EN = value def get_output_en(self): + """Return the output enable mask. Each bit indicates whether the corresponding pin is in output mode (1) or input mode (0).""" return self.OUTPUT_EN def set_data(self, value): + """Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" self.OUTPUT = value def get_data(self): + """Read the GPIO INPUT register. Returns the current logic levels on all pins as a byte array. Reads the physical pin state regardless of direction configuration.""" return self.INPUT diff --git a/basil/HL/ka3005p.py b/basil/HL/ka3005p.py new file mode 100644 index 000000000..2c4bca40a --- /dev/null +++ b/basil/HL/ka3005p.py @@ -0,0 +1,89 @@ +# +# ------------------------------------------------------------ +# Copyright (c) All rights reserved +# SiLab, Institute of Physics, University of Bonn +# ------------------------------------------------------------ +# + +"""Driver for the Korad KA3005P programmable DC power supply.""" + +import logging +from time import sleep + +from basil.HL.HardwareLayer import HardwareLayer + +logger = logging.getLogger(__name__) + + +class ka3005p(HardwareLayer): + """Driver for the Korad KA3005P programmable DC power supply. + + Communicates over a serial (RS-232) interface. Up to 30 V / 5 A. + """ + + def __init__(self, intf, conf): + super(ka3005p, self).__init__(intf, conf) + + def init(self): + """Initialize the power supply. + + Sets a safe current limit of 100 mA to protect the DUT. + """ + super(ka3005p, self).init() + self.set_current(0.1) + + def set_voltage(self, voltage): + """Set the output voltage. + + Args: + voltage: Output voltage in volts. Clipped to 30 V max. + """ + if voltage > 30: + voltage = 30 + cmd = "VSET1:%.2f" % round(voltage, 2) + self._intf.write(cmd) + sleep(0.05) + + def set_current(self, current): + """Set the output current limit. + + Args: + current: Current limit in amps. Clipped to 5 A max. + """ + if current > 5: + current = 5 + cmd = "ISET1:%.3f" % round(current, 3) + self._intf.write(cmd) + sleep(0.05) + + def enable_output(self): + """Enable the DC output (OUT1).""" + self._intf.write("OUT1") + sleep(0.5) + + def disable_output(self): + """Disable the DC output (OUT0).""" + self._intf.write("OUT0") + sleep(0.1) + + def get_voltage(self): + """Read back the actual output voltage. + + Returns: + float: Output voltage in volts. + """ + self._intf.write("VOUT1?") + sleep(0.1) + response = self._intf.read() + return float(response) + + def get_current(self): + """Read back the actual output current. + + Returns: + float: Output current in amps. + """ + self._intf.write("IOUT1?") + sleep(0.1) + response = self._intf.read() + return float(response) diff --git a/basil/HL/pulse_gen.py b/basil/HL/pulse_gen.py index 7ef0035d4..f80b3732f 100644 --- a/basil/HL/pulse_gen.py +++ b/basil/HL/pulse_gen.py @@ -5,11 +5,13 @@ # ------------------------------------------------------------ # +"""Register-based interface to the pulse_gen hardware block.""" + from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class pulse_gen(RegisterHardwareLayer): - """Pulser generator""" + """Pulse generator.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -24,60 +26,70 @@ class pulse_gen(RegisterHardwareLayer): _require_version = "==3" def __init__(self, intf, conf): + """Initialize pulse generator layer.""" super(pulse_gen, self).__init__(intf, conf) def start(self): - """ - Software start of pulse at random time - """ + """Software start of pulse at random time.""" self.START = 0 def reset(self): + """Soft reset the pulse generator. Clears internal state on the next clock edge.""" self.RESET = 0 def set_delay(self, value): - """ - Pulse delay w.r.t. shift register finish signal [in clock cycles(?)] + """Set the pulse delay in clock cycles from start. + + The delay is relative to the start trigger (software .start() or EXT_START pin). """ self.DELAY = value def get_delay(self): + """Return the pulse delay in clock cycles.""" return self.DELAY def set_width(self, value): - """ - Pulse width in terms of clock cycles - """ + """Set the pulse width in terms of clock cycles.""" self.WIDTH = value def get_width(self): + """Return the pulse width in clock cycles.""" return self.WIDTH def set_repeat(self, value): - """ - Pulse repetition in range of 0-255 - """ + """Set the repeat count. 0 = repeat forever. The pulse repeats with the configured DELAY and WIDTH each time. Max 255.""" self.REPEAT = value def get_repeat(self): + """Return the repeat count.""" return self.REPEAT def is_done(self): + """Return True if the pulse generator has finished all repetitions, False if still active. Alias of is_ready.""" return self.is_ready @property def is_ready(self): + """Return True when the pulse generator is idle and ready to accept a new start trigger. + + Reads the READY register (addr 1, bit 0). While the pulse is running + (including all configured repetitions) this reads False. + + The `@property` decorator makes this an attribute-like access - call it + without parentheses as ``daq["pulse0"].is_ready``, not ``.is_ready()``. + + `.is_done()` is an alias that returns the same value. + """ return self.READY def set_en(self, value): - """ + """Configure whether the pulse synchronizes with an external trigger. + If true: The pulse comes with a fixed delay with respect to the external trigger (EXT_START). If false: The pulse comes only at software start. """ self.EN = value def get_en(self): - """ - Return info if pulse starts with a fixed delay w.r.t. shift register finish signal (true) or if it only starts with .start() (false) - """ + """Return whether the pulse uses a fixed delay w.r.t. the shift register finish signal.""" return self.EN diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index 33860ef1b..6846f209b 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -4,12 +4,13 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # +"""Sequence generator driver for the seq_gen FPGA module.""" from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class seq_gen(RegisterHardwareLayer): - """Sequencer generator controller interface for seq_gen FPGA module.""" + """Sequence generator controller interface for seq_gen FPGA module.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -30,87 +31,170 @@ class seq_gen(RegisterHardwareLayer): _require_version = "==3" def __init__(self, intf, conf): + """Initialize the sequencer driver.""" super(seq_gen, self).__init__(intf, conf) self._seq_mem_offset = 64 # in bytes def init(self): + """Initialize the sequencer and read the memory size from hardware.""" super(seq_gen, self).init() self._seq_mem_size = self.get_mem_size() def reset(self): + """Soft reset the sequencer. + + Clears internal counters and output state on the next clock edge. + Must have a rising edge on the sequencer clock before new data is + written to memory. + """ self.RESET = 0 def start(self): + """Start the sequencer. + + Writes to the START register (addr 1). The sequence begins on the + next SEQ_CLK edge after the write. Only effective when DONE/READY + is high (sequence not already running). + """ self.START = 0 def set_size(self, value): + """Set the number of output words in the sequence. + + Each word contains OUT_BITS (one sample per track). Addresses 4-7. + """ self.SIZE = value def get_size(self): + """Return the configured sequence size in output words.""" return self.SIZE def set_wait(self, value): + """Set wait cycles inserted between repetitions. + + Only applies when REPEAT > 0. Addresses 8-11. + """ self.WAIT = value def get_wait(self): + """Return the configured wait cycles between repetitions.""" return self.WAIT def set_clk_divide(self, value): + """Set the clock division factor for SEQ_CLK. + + The sequencer advances one step every CLK_DIV + 1 clock cycles. + Default: 1 (divide by 1, i.e. full rate). Address 3. + """ self.CLK_DIV = value def get_clk_divide(self): + """Return the clock division factor.""" return self.CLK_DIV def set_repeat_start(self, value): + """Set the repeat start position. + + When repeating, the sequence jumps to this position instead of + starting from 0. Addresses 16-19. + """ self.REPEAT_START = value def get_repeat_start(self): + """Return the repeat start position.""" return self.REPEAT_START def set_repeat(self, value): + """Set the repeat count. + + 0 = repeat forever. The sequence repeats from REP_START (or 0) + each time. Addresses 12-15. + """ self.REPEAT = value def get_repeat(self): + """Return the repeat count.""" return self.REPEAT def is_done(self): + """Return True if the sequencer has finished its sequence. + + Includes all repeats. Returns False while running. Aliases is_ready. + """ return self.is_ready @property def is_ready(self): + """Read the DONE/READY register (addr 1, bit 0). + + Returns True when the sequencer is idle and ready to accept a new + start trigger. While the sequence is running (including all + configured repetitions) this reads False. + + The ``@property`` decorator makes this an attribute-like access — + call it without parentheses as ``daq["seq0"].is_ready``, not + ``.is_ready()``. + + ``.is_done()`` and ``.get_done()`` are aliases that return the + same value. + """ return self.READY def get_done(self): + """Alias for is_ready. Returns True if sequencer is finished.""" return self.is_ready def set_en_ext_start(self, value): + """Enable or disable external start via the SEQ_EXT_START pin. + + When enabled (1), the SEQ_EXT_START pin rising edge triggers the + sequence. When disabled (0), only software .start() works. + Address 2. + """ self.EN_EXT_START = value def get_en_ext_start(self): + """Return whether external start is enabled.""" return self.EN_EXT_START def set_nested_start(self, value): + """Set the nested loop start position. Addresses 20-23.""" self.NESTED_START = value def get_nested_start(self): + """Return the nested loop start position.""" return self.NESTED_START def set_nested_stop(self, value): + """Set the nested loop stop position. Addresses 24-27.""" self.NESTED_STOP = value def get_nested_stop(self): + """Return the nested loop stop position.""" return self.NESTED_STOP def set_nested_repeat(self, value): + """Set the nested loop repeat count. 0 = disabled. Addresses 28-31.""" self.NESTED_REPEAT = value def get_nested_repeat(self): + """Return the nested loop repeat count.""" return self.NESTED_REPEAT def get_mem_size(self): + """Return the memory size in bytes.""" return self.MEM_BYTES def set_data(self, data, addr=0): + """Write sequencer memory (the pattern data) via the bus interface. + + Data is interleaved per track by the TrackRegister RL. + + Args: + data: Bytes to write to sequencer memory. + addr: Optional byte offset into memory. + + """ if self._seq_mem_size < len(data): raise ValueError( "Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._seq_mem_size) @@ -118,6 +202,16 @@ def set_data(self, data, addr=0): self._intf.write(self._conf["base_addr"] + self._seq_mem_offset + addr, data) def get_data(self, size=None, addr=0): + """Read sequencer memory (the pattern data) via the bus interface. + + Args: + size: Number of bytes to read (default: all). + addr: Optional byte offset into memory. + + Returns: + bytes: The pattern data. + + """ if size and self._seq_mem_size < size: raise ValueError("Size is too big") if not size: diff --git a/basil/HL/sitcp_fifo.py b/basil/HL/sitcp_fifo.py index 2a417f3bf..b230f01c3 100644 --- a/basil/HL/sitcp_fifo.py +++ b/basil/HL/sitcp_fifo.py @@ -21,6 +21,7 @@ class sitcp_fifo(HardwareLayer): _version = 0 + # Adding these registers via these magic methods is essentially a poor man's version of _registers dict def __getitem__(self, name): if name == "RESET": self._intf.reset() # returns None @@ -38,7 +39,7 @@ def __setitem__(self, name, value): super(sitcp_fifo, self).__setitem__(name, value) def __getattr__(self, name): - """called only on last resort if there are no attributes in the instance that match the name""" + """Called only as a last resort if there are no attributes in the instance that match the name""" if name.isupper(): return self[name] else: diff --git a/basil/HL/spi.py b/basil/HL/spi.py index 02fe7336e..befdca83b 100644 --- a/basil/HL/spi.py +++ b/basil/HL/spi.py @@ -4,6 +4,7 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # +"""Serial programming interface (SPI) driver for FPGA-based SPI modules.""" from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer @@ -25,89 +26,93 @@ class spi(RegisterHardwareLayer): _require_version = "==2" def __init__(self, intf, conf): + """Initialize SPI driver.""" super(spi, self).__init__(intf, conf) self._spi_mem_offset = 16 # in bytes def init(self): + """Initialize hardware layer and query memory bytes.""" super(spi, self).init() self._mem_bytes = self.MEM_BYTES def reset(self): - """Soft reset the module.""" + """Soft reset the SPI module. Aborts any in-progress transfer, clears internal state.""" self.RESET = 0 def start(self): - """ - Starts the shifting data - """ + """Start shifting data.""" self.START = 0 def set_size(self, value): - """ - Number of clock cycles for shifting in data - ex. length of matrix shift register (number of pixels daisy chained) + """Set the number of clock cycles for shifting in data. + + For example, length of matrix shift register (number of pixels daisy chained). """ self.SIZE = value def get_size(self): - """ - Get size of shift register length - """ + """Get size of shift register length.""" return self.SIZE def set_wait(self, value): - """ - Sets time delay between repetitions in clock cycles + """Set the time delay between repetitions in clock cycles. + + Time delay between repetitions in clock cycles. """ self.WAIT = value def get_wait(self): - """ - Gets time delay between repetitions in clock cycles - """ + """Get time delay between repetitions in clock cycles.""" return self.WAIT def set_repeat(self, value): - """ - If 0: Repeat sequence forever - Other: Number of repetitions of sequence with delay 'wait' + """Set the number of repetitions of the sequence with delay 'wait'. + + If 0: Repeat sequence forever. + Otherwise: Number of repetitions of sequence with delay 'wait'. """ self.REPEAT = value def get_repeat(self): - """ - Gets Number of repetitions of sequence with delay 'wait' (if 0 --> repeat forever) - """ + """Get number of repetitions of sequence with delay 'wait' (if 0 --> repeat forever).""" return self.REPEAT def set_en(self, value): - """ - Enable start on external EXT_START signal (inside FPGA) + """Enable start on external EXT_START signal (inside FPGA). + + When enabled, the SPI transfer starts on the external EXT_START signal. """ self.EN = value def get_en(self): - """ - Gets state of enable. - """ + """Return the enable state.""" return self.EN def is_done(self): - """ - Get the status of transfer/sequence. + """Return True if the SPI transfer is complete, False if still in progress. + + Aliases is_ready. """ return self.is_ready @property def is_ready(self): + """Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" return self.READY def get_mem_size(self): + """Return the SPI memory size in bytes (from MEM_BYTES register at address 14-15). This is the maximum single transfer size.""" return self.MEM_BYTES def set_data(self, data, addr=0): - """ - Sets data for outgoing stream + """Write data to the SPI transmit memory at the bus memory offset. + + Data bytes are shifted out MSB-first on SDI. + + Args: + data (bytes): Data to write. + addr (int, optional): Byte offset into memory. + """ if self._mem_bytes < len(data): raise ValueError("Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._mem_bytes)) @@ -115,8 +120,14 @@ def set_data(self, data, addr=0): # This needs to be changed to return written value def get_data(self, size=None, addr=None): - """ - Gets data for incoming stream + """Read data from the SPI receive memory at the bus memory offset. + + Incoming bytes captured from SDO are stored here. + + Args: + size (int, optional): Number of bytes to read (default all). + addr (int, optional): Byte offset into memory. + """ # readback memory offset if addr is None: diff --git a/basil/dut.py b/basil/dut.py index e118629f5..2310d63d5 100644 --- a/basil/dut.py +++ b/basil/dut.py @@ -20,7 +20,7 @@ from yaml import safe_load logging.basicConfig( - level=logging.INFO, format="%(asctime)s - %(name)s - [%(levelname)-8s] (%(threadName)-10s) %(message)s" + level=logging.INFO, format="%(asctime)s - %(name)s - [%(levelname)s] (%(threadName)-10s) %(message)s" ) diff --git a/basil/firmware/modules/bram_fifo/bram_fifo.v b/basil/firmware/modules/bram_fifo/bram_fifo.v index 51b5bf060..8eec9d4c1 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BRAM_FIFO +`define BRAM_FIFO + +`include "bram_fifo/bram_fifo_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -112,3 +118,5 @@ bram_fifo_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/bram_fifo/bram_fifo_core.v b/basil/firmware/modules/bram_fifo/bram_fifo_core.v index 95c6527a7..bc7a0eda4 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo_core.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo_core.v @@ -4,9 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BRAM_FIFO_CORE +`define BRAM_FIFO_CORE + +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module bram_fifo_core #( parameter DEPTH = 32'h8000, parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent @@ -161,3 +167,5 @@ always @(posedge BUS_CLK) begin end endmodule + +`endif diff --git a/basil/firmware/modules/cmd_seq/cmd_seq.v b/basil/firmware/modules/cmd_seq/cmd_seq.v index d04e3bfaf..1836d499d 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CMD_SEQ +`define CMD_SEQ + +`include "cmd_seq/cmd_seq_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -76,3 +82,5 @@ cmd_seq_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/cmd_seq/cmd_seq_core.v b/basil/firmware/modules/cmd_seq/cmd_seq_core.v index f8d5bf33f..6d0992015 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq_core.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq_core.v @@ -4,9 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CMD_SEQ_CORE +`define CMD_SEQ_CORE + +`include "utils/flag_domain_crossing.v" +`include "utils/3_stage_synchronizer.v" + `timescale 1ps/1ps `default_nettype none + module cmd_seq_core #( parameter ABUSWIDTH = 16, parameter OUTPUTS = 1, // from (0 : 8] @@ -470,3 +477,5 @@ always @(posedge BUS_CLK) CONF_READY <= 1; endmodule + +`endif diff --git a/basil/firmware/modules/fast_spi_rx/README.rst b/basil/firmware/modules/fast_spi_rx/README.rst index 160ec45e5..479968bbd 100644 --- a/basil/firmware/modules/fast_spi_rx/README.rst +++ b/basil/firmware/modules/fast_spi_rx/README.rst @@ -1,6 +1,78 @@ +======================================== +**fast_spi_rx** - Fast serial receiver +======================================== -===================================== -**fast_spi_rx** - Fast SPI receiver -===================================== +This module can continuous capture serial data on each rising edge of it's capture clock. +Received data is packed into 32-bit words and propagated to a FIFO data interface. +While originally intended for SPI (hence the naming), it can be used for any serial data. -Allows continuous serial data receive. Received data are propagated to FIFO data interface. +**Unit tests** + +Unit tests for this module have not yet been implemented. + +**Usage notes** + +* **Data output format**: Each 32-bit FIFO word is formatted as + ``[31:28] IDENTIFIER, [27:N] Frame counter, [N-1:0] Captured data`` + where ``N = DATA_SIZE``. The IDENTIFIER field differentiates multiple + fast_spi_rx instances merged into the same downstream FIFO stream. + The frame counter increments on every SEN falling edge, allowing + reconstruction of multi-word captures. When a capture spans multiple + FIFO words, all words carry the same frame counter value. +* **FIFO flush behavior**: A FIFO word is written when DATA_SIZE bits have + been captured, or when SEN falls (flushing any partially-filled word). + An incomplete frame is never lost — it is always written to the FIFO + when SEN goes low. +* **Reset**: The soft reset (RESET register write or BUS_RST) is + synchronised to SEQ_CLK via a CDC synchroniser. At least one rising + edge of SEQ_CLK must occur after reset is released for it to take + effect. If SEQ_CLK is not running when reset is asserted, the reset + will not complete. + +Parameters +---------- + +--------------+---------------------+-----------------------------------------------------------------+ + | Name | Default | Description | + +==============+=====================+=================================================================+ + | ABUSWIDTH | 16 | Width of the bus address bus | + +--------------+---------------------+-----------------------------------------------------------------+ + | IDENTIFIER | 4'b0001 | Instance identifier packed into bits [31:28] of each FIFO word | + +--------------+---------------------+-----------------------------------------------------------------+ + | DATA_SIZE | 16 | Number of serial data bits packed into a single FIFO word | + +--------------+---------------------+-----------------------------------------------------------------+ + +Pins +---- + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | Name | Size | Direction | Description | + +===============+=====================+=======================+======================================================+ + | SEQ_CLK | 1 | input | Capture clock (serial data sampled on rising edge) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | SDI | 1 | input | Serial data input (sampled on SEQ_CLK rising edge) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | SEN | 1 | input | Serial enable (active high, frames the capture) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | FIFO_READ | 1 | input | Read strobe (pop one word from the output FIFO) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | FIFO_EMPTY | 1 | output | FIFO empty flag | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | FIFO_DATA | 32 | output | FIFO data output (32-bit word) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + +Registers +--------- + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | Name | Address | Bits | r/w | Default | Description | + +===============+=====================+========+=======+=============+==================================================================+ + | RESET | 0 | | wo | | Soft reset (synchronous to SEQ_CLK, takes effect on next edge) | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | VERSION | 0 | [7:0] | ro | | Firmware version | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | EN | 2 | [0] | r/w | 0 | Enable capture (set high to arm) | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | LOST_COUNT | 3 | [7:0] | ro | 0 | Lost data counter (incremented on CDC FIFO overflow) | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + +**Unit tests** + +Unit tests for this module have not yet been implemented. diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v index a409a4316..7faf65a5c 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ + +`ifndef FAST_SPI_RX +`define FAST_SPI_RX + +`include "fast_spi_rx/fast_spi_rx_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -12,7 +19,8 @@ module fast_spi_rx #( parameter HIGHADDR = 16'h0000, parameter ABUSWIDTH = 16, - parameter IDENTIFIER = 4'b0001 + parameter IDENTIFIER = 4'b0001, + parameter DATA_SIZE = 16 ) ( input wire BUS_CLK, input wire [ABUSWIDTH-1:0] BUS_ADD, @@ -55,7 +63,8 @@ bus_to_ip #( fast_spi_rx_core #( .ABUSWIDTH(ABUSWIDTH), - .IDENTIFIER(IDENTIFIER) + .IDENTIFIER(IDENTIFIER), + .DATA_SIZE(DATA_SIZE) ) i_fast_spi_rx_core ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), @@ -75,3 +84,5 @@ fast_spi_rx_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index 6559dd2ec..ebe0f9ae8 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -4,12 +4,21 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FAST_SPI_RX_CORE +`define FAST_SPI_RX_CORE + +`include "utils/cdc_pulse_sync.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module fast_spi_rx_core #( parameter ABUSWIDTH = 16, - parameter IDENTIFIER = 4'b0001 + parameter IDENTIFIER = 4'b0001, + parameter DATA_SIZE = 16 ) ( input wire SCLK, input wire SDI, @@ -28,9 +37,9 @@ module fast_spi_rx_core #( input wire BUS_RD ); -localparam VERSION = 0; +localparam VERSION = 1; -//output format #ID (as parameter IDENTIFIER + 12 id-frame + 16 bit data) +// Output format #ID (as parameter IDENTIFIER + 12 id-frame + 16 bit data) wire SOFT_RST; assign SOFT_RST = (BUS_ADD==0 && BUS_WR); @@ -52,6 +61,8 @@ end reg [7:0] LOST_DATA_CNT; +localparam DATA_SIZE_READ = DATA_SIZE; + always @(posedge BUS_CLK) begin if(BUS_RD) begin if(BUS_ADD == 0) @@ -60,6 +71,8 @@ always @(posedge BUS_CLK) begin BUS_DATA_OUT <= {7'b0, CONF_EN}; else if(BUS_ADD == 3) BUS_DATA_OUT <= LOST_DATA_CNT; + else if(BUS_ADD == 4) + BUS_DATA_OUT <= DATA_SIZE_READ; else BUS_DATA_OUT <= 8'b0; end @@ -67,6 +80,7 @@ end wire RST_SYNC; wire RST_SOFT_SYNC; +// Reset is synchronized by the sclk cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SCLK), .pulse_out(RST_SOFT_SYNC)); assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; @@ -84,7 +98,7 @@ end wire RST_LONG; assign RST_LONG = sync_cnt[7]; -reg [11:0] frame_cnt; +reg [27-DATA_SIZE:0] frame_cnt; wire SEN_START, SEN_FINISH; reg SEN_DLY; always @(posedge SCLK) begin @@ -112,16 +126,16 @@ always @(posedge SCLK) begin bit_cnt <= bit_cnt + 1; end -assign cdc_fifo_write = ( (bit_cnt == 15) || SEN_FINISH ) && CONF_EN_SYNC; +assign cdc_fifo_write = ( (bit_cnt == DATA_SIZE - 1) || SEN_FINISH ) && CONF_EN_SYNC; -reg [15:0] spi_data; +reg [DATA_SIZE-1:0] spi_data; always @(posedge SCLK) begin if(RST_SYNC | SEN_FINISH) spi_data <= 0; else if(cdc_fifo_write) - spi_data <= {15'b0, SDI}; + spi_data <= {{(DATA_SIZE-1){1'b0}}, SDI}; else if(SEN) - spi_data <= {spi_data[14:0], SDI}; + spi_data <= {spi_data[DATA_SIZE-2:0], SDI}; end wire fifo_full,cdc_fifo_empty; @@ -135,7 +149,7 @@ always @(posedge SCLK) begin end wire [31:0] cdc_data; -assign cdc_data = {IDENTIFIER, frame_cnt[11:0], spi_data}; +assign cdc_data = {IDENTIFIER, frame_cnt[27-DATA_SIZE:0], spi_data}; wire [31:0] cdc_data_out; cdc_syncfifo #( @@ -172,3 +186,5 @@ generic_fifo #( //assign FIFO_DATA[31:30] = 0; endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/decode_8b10b.v b/basil/firmware/modules/fei4_rx/decode_8b10b.v index 776a1ee15..0c33c0892 100644 --- a/basil/firmware/modules/fei4_rx/decode_8b10b.v +++ b/basil/firmware/modules/fei4_rx/decode_8b10b.v @@ -15,6 +15,9 @@ * notice is preserved. * per Widmer and Franaszek */ +`ifndef DECODE_8B10B +`define DECODE_8B10B + `timescale 1ps/1ps `default_nettype none @@ -171,3 +174,5 @@ module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err); (disp6p & disp4p) | (disp6n & disp4n)); endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/fei4_rx.v b/basil/firmware/modules/fei4_rx/fei4_rx.v index 723371b8c..8504e5b7a 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FEI4_RX +`define FEI4_RX + +`include "fei4_rx/fei4_rx_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -101,3 +107,5 @@ fei4_rx_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/fei4_rx_core.v b/basil/firmware/modules/fei4_rx/fei4_rx_core.v index 959057468..02b4d897f 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx_core.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx_core.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FEI4_RX_CORE +`define FEI4_RX_CORE + +`include "utils/3_stage_synchronizer.v" +`include "fei4_rx/receiver_logic.v" + `timescale 1ps/1ps `default_nettype none @@ -258,3 +264,5 @@ receiver_logic #( ); endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/rec_sync.v b/basil/firmware/modules/fei4_rx/rec_sync.v index a113680bf..cbd674415 100644 --- a/basil/firmware/modules/fei4_rx/rec_sync.v +++ b/basil/firmware/modules/fei4_rx/rec_sync.v @@ -4,6 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef REC_SYNC +`define REC_SYNC + +`include "utils/flag_domain_crossing.v" + `timescale 1ps/1ps `default_nettype none @@ -169,3 +174,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/receiver_logic.v b/basil/firmware/modules/fei4_rx/receiver_logic.v index 574c95b0c..e12a46292 100644 --- a/basil/firmware/modules/fei4_rx/receiver_logic.v +++ b/basil/firmware/modules/fei4_rx/receiver_logic.v @@ -4,6 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef RECEIVER_LOGIC +`define RECEIVER_LOGIC + +`include "utils/flag_domain_crossing.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" +`include "fei4_rx/sync_master.v" +`include "fei4_rx/rec_sync.v" +`include "fei4_rx/decode_8b10b.v" + `timescale 1ps/1ps `default_nettype none @@ -282,3 +292,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/sync_master.v b/basil/firmware/modules/fei4_rx/sync_master.v index 556b1506f..7ff1b9ea8 100644 --- a/basil/firmware/modules/fei4_rx/sync_master.v +++ b/basil/firmware/modules/fei4_rx/sync_master.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SYNC_MASTER +`define SYNC_MASTER + `timescale 1ps/1ps `default_nettype none @@ -185,3 +188,5 @@ assign dz[1] = DATA_IN_DLY[0]; //FDC ff_dz1(.D(dz[0]), .C(clk90), .CLR(rst), .Q(dz[1]))/*synthesis rloc = "x3y0" */; endmodule + +`endif diff --git a/basil/firmware/modules/fx3_if/FX3_IF.v b/basil/firmware/modules/fx3_if/FX3_IF.v index c541ed0ae..62748782d 100644 --- a/basil/firmware/modules/fx3_if/FX3_IF.v +++ b/basil/firmware/modules/fx3_if/FX3_IF.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FX3_IF +`define FX3_IF + `timescale 1ps/1ps `default_nettype none @@ -363,3 +366,5 @@ for (gen = 0; gen < 32; gen = gen + 1) endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v index e88771bed..158bf7963 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef GPAC_ADC_IOBUF +`define GPAC_ADC_IOBUF + `timescale 1ps/1ps `default_nettype none @@ -182,3 +185,5 @@ assign ADC_IN3 = adc_out_sync[3]; `endif endmodule + +`endif diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v index 545122ed7..e7aa1ddd0 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef GPAC_ADC_RX +`define GPAC_ADC_RX + +`include "gpac_adc_rx/gpac_adc_rx_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -84,3 +90,5 @@ gpac_adc_rx_core #( endmodule + +`endif diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v index c3fd49488..4bdf1d67c 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v @@ -4,9 +4,19 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef GPAC_ADC_RX_CORE +`define GPAC_ADC_RX_CORE + +`include "utils/cdc_reset_sync.v" +`include "utils/cdc_pulse_sync.v" +`include "utils/pulse_gen_rising.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module gpac_adc_rx_core #( parameter ABUSWIDTH = 16, parameter [1:0] ADC_ID = 0, @@ -286,3 +296,5 @@ always @(posedge BUS_CLK) CONF_DONE <= 1; endmodule + +`endif diff --git a/basil/firmware/modules/gpio/README.rst b/basil/firmware/modules/gpio/README.rst index 0a6092118..bb594a90c 100644 --- a/basil/firmware/modules/gpio/README.rst +++ b/basil/firmware/modules/gpio/README.rst @@ -9,6 +9,17 @@ General purpose input output (gpio) is a generic pins whose behavior, including `test_SimGpio.v `_ `test_SimGpio.py `_ +**Usage notes** + +* **StdRegister usage**: Rather than reading/writing the raw `INPUT` and + `OUTPUT` bytes directly, instantiate a ``StdRegister`` in the basil + configuration YAML with named fields for each GPIO bit. This provides + access like ``daq["gpio0"]["RST_B"] = 1`` followed by `.write()` to push + the full byte to hardware. +* **Direction**: Each pin's direction is set by `IO_DIRECTION` at compile + time. Runtime direction changes via the `DIRECTION` register require + `IO_TRI` to be enabled for the corresponding pin. + **Parameters:** +--------------+---------------------+-----------------------------------------------------------------+ | Name | Default | Description | @@ -28,16 +39,16 @@ General purpose input output (gpio) is a generic pins whose behavior, including +--------------+---------------------+-----------------------------------------------------------------+ **Registers:** - +------------+---------------------+----------------------------------------+ - | Name | Address | Description | - +============+=====================+========================================+ - | RESET | 0 | Soft reset active on write to address | - +------------+---------------------+----------------------------------------+ - | INPUT | 1 to BYTE | Readback of state of pin | - +------------+---------------------+----------------------------------------+ - | OUTPUT | 1+BYTE to 2*BYTE | Set output state on pin | - +------------+---------------------+----------------------------------------+ - | DIRECTION | 1+2*BYTE to 3*BYTE | Tri-state pin (if enabled) | - +------------+---------------------+----------------------------------------+ + +------------+---------------------+-------------------------------------------------------+ + | Name | Address | Description | + +============+=====================+=======================================================+ + | RESET | 0 | Soft reset active on write to address | + +------------+---------------------+-------------------------------------------------------+ + | INPUT | 1 to BYTE | Readback of state of pin | + +------------+---------------------+-------------------------------------------------------+ + | OUTPUT | 1+BYTE to 2*BYTE | Set output state on pin | + +------------+---------------------+-------------------------------------------------------+ + | DIRECTION | 1+2*BYTE to 3*BYTE | Tri-state pin (if enabled) | + +------------+---------------------+-------------------------------------------------------+ Where: BYTE = IO_WIDTH/8+1 diff --git a/basil/firmware/modules/gpio/gpio.v b/basil/firmware/modules/gpio/gpio.v index 6b09545b3..c67e13282 100644 --- a/basil/firmware/modules/gpio/gpio.v +++ b/basil/firmware/modules/gpio/gpio.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef GPIO +`define GPIO + +`include "gpio/gpio_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -65,3 +71,5 @@ gpio_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/gpio/gpio_core.v b/basil/firmware/modules/gpio/gpio_core.v index 47a36905c..769382f41 100644 --- a/basil/firmware/modules/gpio/gpio_core.v +++ b/basil/firmware/modules/gpio/gpio_core.v @@ -5,11 +5,15 @@ * ------------------------------------------------------------ */ + +`ifndef GPIO_CORE +`define GPIO_CORE + module gpio_core #( parameter ABUSWIDTH = 16, parameter IO_WIDTH = 8, - parameter IO_DIRECTION = 0, - parameter IO_TRI = 0 + parameter [IO_WIDTH-1:0] IO_DIRECTION = {0,0,0,0,0,0,0,0,0}, + parameter [IO_WIDTH-1:0] IO_TRI = {0,0,0,0,0,0,0,0,0} ) ( BUS_CLK, BUS_RST, @@ -24,14 +28,14 @@ module gpio_core #( localparam VERSION = 0; -// -------- +// ---- // ORDER: // 0 - RESET // 1*B - INPUT (readback) // 2*B - OUTPUT // 3*B - DIRECTION/OUTPUT_ENABLE // B = IO_WIDTH/8+1 -//---- +// ---- input wire BUS_CLK; input wire BUS_RST; @@ -42,7 +46,7 @@ input wire BUS_RD; input wire BUS_WR; inout wire [IO_WIDTH-1:0] IO; -// CORE // +// CORE wire SOFT_RST; //0 localparam IO_BYTES = ((IO_WIDTH-1)/8)+1; @@ -104,3 +108,5 @@ always @(*) endmodule + +`endif diff --git a/basil/firmware/modules/gpio/gpio_sbus.v b/basil/firmware/modules/gpio/gpio_sbus.v index e3c824a0f..6f783c394 100644 --- a/basil/firmware/modules/gpio/gpio_sbus.v +++ b/basil/firmware/modules/gpio/gpio_sbus.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef GPIO_SBUS +`define GPIO_SBUS + +`include "gpio/gpio_core.v" +`include "utils/sbus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -70,3 +76,5 @@ gpio_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/i2c/i2c.v b/basil/firmware/modules/i2c/i2c.v index b1f9c715c..c3b7cda25 100644 --- a/basil/firmware/modules/i2c/i2c.v +++ b/basil/firmware/modules/i2c/i2c.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef I2C +`define I2C + +`include "i2c/i2c_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -69,3 +75,5 @@ i2c_core #( endmodule + +`endif diff --git a/basil/firmware/modules/i2c/i2c_core.v b/basil/firmware/modules/i2c/i2c_core.v index 2df6acdd0..4b48173c7 100644 --- a/basil/firmware/modules/i2c/i2c_core.v +++ b/basil/firmware/modules/i2c/i2c_core.v @@ -4,9 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef I2C_CORE +`define I2C_CORE + +`include "utils/cdc_pulse_sync.v" + `timescale 1ps/1ps `default_nettype none + module i2c_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 1, @@ -343,3 +349,5 @@ always @(posedge BUS_CLK) endmodule + +`endif diff --git a/tests/jtag_tap.v b/basil/firmware/modules/includes/jtag_tap.v similarity index 95% rename from tests/jtag_tap.v rename to basil/firmware/modules/includes/jtag_tap.v index 9d0b2a908..d979f26f3 100644 --- a/tests/jtag_tap.v +++ b/basil/firmware/modules/includes/jtag_tap.v @@ -1,3 +1,6 @@ +`ifndef JTAG_TAP +`define JTAG_TAP + `timescale 1ps / 1ps /* JTAG TAP interface @@ -49,16 +52,20 @@ ///////////////////////////// //`include "simulator_features.v" ///////////////////////////// -`define UNIQUE //unique -`define FINISH_WITH_ERROR_EXIT_CODE //$finish -`define ASSERT_FALSE $display( "ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE +`define UNIQUE +`define FINISH_WITH_ERROR_EXIT_CODE + +// WARNING: __FILE__ and __LINE only available in SystemVerilog 2009 and later +// A Verilog only solution would be: define ASSERT_FALSE $display( "ERROR: Assertion failed in module %m." ); `FINISH_WITH_ERROR_EXIT_CODE +`define ASSERT_FALSE $display("ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE ///////////////////////////// //`include "tap_defines.v" //////////////////////////// // This is similar to the IDCODE that the or1200 CPU uses, // only the new part number (IQ) is the or1200's value + 100 (decimal). -`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // or1200 uses 32'h149511c3. +// The or1200 uses 32'h149511c3. +`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // 0001 bits [31:28], version // 0100100110110101 bits [27:12], part number (IQ), 01001001010101010001 + 100 (decimal) // 00011100001 bits [11: 1], manufacturer id (flextronics) @@ -67,17 +74,19 @@ // JTAG Instructions. The Instruction Register is 4 bits long at the moment, // but 3 bits would do. However, this optimisation is probably not worth the trouble. -`define JTAG_INSTRUCTION_EXTEST 4'b0000 // Not supported at the moment. -`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 // Not supported at the moment. -`define JTAG_INSTRUCTION_IDCODE 4'b0010 // Supported. +// EXTEST and SAMPLE_PRELOAD are not supported at the moment; IDCODE is supported. +`define JTAG_INSTRUCTION_EXTEST 4'b0000 +`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 +`define JTAG_INSTRUCTION_IDCODE 4'b0010 // The following command is specific to OR10. Because the Xilinx TAP primitives have just 1 or 2 user-defined // JTAG instructions, all OR10 debug operations is performed with a single DEBUG instruction, // which can be mapped to one of Xilinx' user-defined instructions when using that interface. // If it weren't for this limitation, it would have been more comfortable to define // several JTAG instructions for the different types of OR10 debug operations. -`define JTAG_INSTRUCTION_DEBUG 4'b1000 // Specific to OR10, see comment above. -`define JTAG_INSTRUCTION_MBIST 4'b1001 // Not supported at the moment. -`define JTAG_INSTRUCTION_BYPASS 4'b1111 // Supported. According to the JTAG specification, the BYPASS instruction opcode must be all 1's. +// DEBUG is specific to OR10; MBIST is not supported. BYPASS must be all 1's. +`define JTAG_INSTRUCTION_DEBUG 4'b1000 +`define JTAG_INSTRUCTION_MBIST 4'b1001 +`define JTAG_INSTRUCTION_BYPASS 4'b1111 module jtag_tap #( parameter TRACE_JTAG_DATA = 0, @@ -568,3 +577,5 @@ module jtag_tap end endmodule + +`endif diff --git a/basil/firmware/modules/jtag_master/jtag_master.v b/basil/firmware/modules/jtag_master/jtag_master.v index b20cd8593..9ad1010be 100644 --- a/basil/firmware/modules/jtag_master/jtag_master.v +++ b/basil/firmware/modules/jtag_master/jtag_master.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef JTAG_MASTER +`define JTAG_MASTER + +`include "jtag_master/jtag_master_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -79,3 +85,5 @@ jtag_master_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/jtag_master/jtag_master_core.v b/basil/firmware/modules/jtag_master/jtag_master_core.v index 418769896..1791cf6a7 100644 --- a/basil/firmware/modules/jtag_master/jtag_master_core.v +++ b/basil/firmware/modules/jtag_master/jtag_master_core.v @@ -4,9 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef JTAG_MASTER_CORE +`define JTAG_MASTER_CORE + +`include "utils/ramb_8_to_n.v" +`include "utils/cdc_reset_sync.v" +`include "utils/cdc_pulse_sync.v" +`include "utils/CG_MOD_pos.v" `default_nettype none + module jtag_master_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16 @@ -475,3 +483,5 @@ always @(negedge JTAG_CLK) /// endmodule + +`endif diff --git a/basil/firmware/modules/m26_rx/m26_rx.v b/basil/firmware/modules/m26_rx/m26_rx.v index b40d06354..226d2f36f 100644 --- a/basil/firmware/modules/m26_rx/m26_rx.v +++ b/basil/firmware/modules/m26_rx/m26_rx.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef M26_RX +`define M26_RX + +`include "m26_rx/m26_rx_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -87,3 +93,5 @@ m26_rx_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/m26_rx/m26_rx_ch.v b/basil/firmware/modules/m26_rx/m26_rx_ch.v index d7a9067bb..f952c0830 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_ch.v +++ b/basil/firmware/modules/m26_rx/m26_rx_ch.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef M26_RX_CH +`define M26_RX_CH + module m26_rx_ch ( input wire RST, @@ -119,3 +123,5 @@ always @(posedge CLK_RX) DATA <= data_sr[15:0]; endmodule + +`endif diff --git a/basil/firmware/modules/m26_rx/m26_rx_core.v b/basil/firmware/modules/m26_rx/m26_rx_core.v index 95990e348..ac0ca3c9b 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_core.v +++ b/basil/firmware/modules/m26_rx/m26_rx_core.v @@ -4,9 +4,19 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef M26_RX_CORE +`define M26_RX_CORE + +`include "utils/flag_domain_crossing.v" +`include "utils/3_stage_synchronizer.v" +`include "m26_rx/m26_rx_ch.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module m26_rx_core #( parameter ABUSWIDTH = 16, parameter HEADER = 0, @@ -37,6 +47,9 @@ module m26_rx_core #( localparam VERSION = 2; +reg M26_FRAME_START; +reg WRITE_FRAME; + //output format #ID (as parameter IDENTIFIER + 1 frame start + 16 bit data) // writing to register 0 asserts soft reset @@ -296,7 +309,6 @@ always @(posedge CLK_RX) begin end end -reg M26_FRAME_START; always @(posedge CLK_RX) begin M26_FRAME_START <= FRAME_START_CH0; end @@ -306,7 +318,6 @@ assign cdc_data[17] = m26_data_lost; // M26 data loss flag assign cdc_data[16] = M26_FRAME_START; // start of M26 frame flag assign cdc_data[15:0] = data_field; // M26 data -reg WRITE_FRAME; always @(posedge CLK_RX) begin if (RST_SYNC) WRITE_FRAME <= 1'b0; @@ -404,3 +415,5 @@ assign FIFO_DATA[31:24] = HEADER[7:0]; endmodule + +`endif diff --git a/basil/firmware/modules/pulse_gen/README.rst b/basil/firmware/modules/pulse_gen/README.rst index 0c7c3b112..d86d82061 100644 --- a/basil/firmware/modules/pulse_gen/README.rst +++ b/basil/firmware/modules/pulse_gen/README.rst @@ -9,6 +9,17 @@ Simple pulse generator with configurable delay and width. `test_SimSeq.v `_ `test_SimSeq.py `_ +**Usage notes** + +* **Start**: The pulse can be started via a write to the ``START`` register + (software start), or via the ``EXT_START`` pin with ``EN`` set (external start). +* **Repeat mode**: A value of 0 in the ``REPEAT`` register causes the pulse to + repeat forever. +* **START and READY share the same address**: The ``START`` (write-only) and + ``READY`` (read-only) registers are aliased at the same address. Writing to + address 1 triggers a start, reading address 1 returns the ready flag. + This pattern is consistent across seq_gen, spi, and pulse_gen. + **Pins:** +---------------+---------------------+-----------------------+------------------------------------------------------+ | Name | Size | Direction | Description | @@ -24,15 +35,16 @@ Simple pulse generator with configurable delay and width. +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +===============+==================================+========+=======+=============+============================================================================================+ - | START | 1 | | wo | | software start on write to address | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | READY | 1 | [0] | ro | 0 | indicate finish | + |RESET / VERSION| 0 | | wo/ro | | Soft reset on write / Firmware version | + +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ + | START / READY | 1 | | wo/ro | 0 | Software start on write / Indicate finish | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | EN | 2 | [0] | r/w | 0 | enable external start | + | EN | 2 | [0] | r/w | 0 | Enable external start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DELAY | 6 - 3 | [31:0] | r/w | 0 | pulse delay from start | + | DELAY | 6 - 3 | [31:0] | r/w | 0 | Pulse delay from start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | WIDTH | 10 - 7 | [31:0] | r/w | 0 | pulse width | + | WIDTH | 10 - 7 | [31:0] | r/w | 0 | Pulse width | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REPEAT | 11 - 14 | [31:0] | r/w | 1 | repeat count (0 ->forever) | + | REPEAT | 14 - 11 | [31:0] | r/w | 1 | Repeat count (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ diff --git a/basil/firmware/modules/pulse_gen/pulse_gen.v b/basil/firmware/modules/pulse_gen/pulse_gen.v index 6e136a1ca..725aa2321 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef PULSE_GEN +`define PULSE_GEN + +`include "pulse_gen/pulse_gen_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -63,3 +69,5 @@ pulse_gen_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/pulse_gen/pulse_gen_core.v b/basil/firmware/modules/pulse_gen/pulse_gen_core.v index 3b7a75c16..4dd94daaf 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen_core.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen_core.v @@ -4,9 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef PULSE_GEN_CORE +`define PULSE_GEN_CORE + +`include "utils/3_stage_synchronizer.v" +`include "utils/cdc_pulse_sync.v" + `timescale 1ps/1ps `default_nettype none + module pulse_gen_core #( parameter ABUSWIDTH = 16 ) ( @@ -225,3 +232,5 @@ always @(posedge BUS_CLK) CONF_DONE <= 1; endmodule + +`endif diff --git a/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v b/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v index 70f11500a..eed9df538 100644 --- a/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +++ b/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef RRP_ARBITER +`define RRP_ARBITER + `timescale 1ps/1ps `default_nettype none @@ -107,3 +110,5 @@ endgenerate assign READ_GRANT = select & {WIDTH{READY_OUT}} & WRITE_REQ; endmodule + +`endif diff --git a/basil/firmware/modules/seq_gen/README.rst b/basil/firmware/modules/seq_gen/README.rst index 1a0497f30..305571380 100644 --- a/basil/firmware/modules/seq_gen/README.rst +++ b/basil/firmware/modules/seq_gen/README.rst @@ -3,13 +3,32 @@ **seq_gen** - Pattern generator ================================ -Module implements a simple sequencer/pattern generator base on block ram. Supports 2 levels of internal loops and external start. -For OUT_BITS != 8 user need to provide block memory module (seq_gen_blk_mem) with proper size. +Module implements a simple sequencer/pattern generator based on block ram. Supports 2 levels of internal loops and external start. **Unit test/Example:** `test_SimSeq.v `_ `test_SimSeq.py `_ +**Usage notes** + +* **Tracks**: The seq_gen supports OUT_BITS from 1 to at least 256. Each output bit + is a separate track. To fill track data in software, instantiate a + ``TrackRegister`` in the basil configuration YAML. This provides named track + access like ``daq["seq0"]["INIT"][0:40] = bitarray("...")``. +* **Start**: The sequence can be started via a write to the ``START`` register + (software start), or via the `SEQ_EXT_START` pin with ``EN_EXT_START`` set + (external start). The external start is typically driven by a GPIO or + pulse_gen output. +* **Repeat mode**: A value of 0 in the ``REPEAT`` register causes the sequence to + repeat forever (until reset or reconfiguration). +* **Output hold**: When the sequence finishes or stops, the last output state + is held on ``SEQ_OUT`` — it does not return to zero. The sequencer does not + reset its outputs on completion. +* **START and READY share the same address**: The ``START`` (write-only) and + ``DONE`` (read-only) registers are aliased at the same address. Writing to + address 1 triggers a start, reading address 1 returns the done flag. + This pattern is consistent across seq_gen, spi, and pulse_gen. + **Parameters:** +--------------+---------------------+-------------------------------------------------------------------------+ | Name | Default | Description | @@ -25,7 +44,7 @@ For OUT_BITS != 8 user need to provide block memory module (seq_gen_blk_mem) wit +===============+=====================+=======================+======================================================+ | SEQ_EXT_START | 1 | input | external start signal (synchronous to SEQ_CLK) | +---------------+---------------------+-----------------------+------------------------------------------------------+ - | SEQ_CLK | 1 | input | external clock used for friving sequence | + | SEQ_CLK | 1 | input | external clock used for driving sequence | +---------------+---------------------+-----------------------+------------------------------------------------------+ | SEQ_OUT | OUT_BITS | output | sequencer output | +---------------+---------------------+-----------------------+------------------------------------------------------+ @@ -34,29 +53,30 @@ For OUT_BITS != 8 user need to provide block memory module (seq_gen_blk_mem) wit +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +===============+==================================+========+=======+=============+============================================================================================+ - | START | 1 | | wo | | start transfer on write to address | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DONE | 1 | [0] | ro | 0 | indicate transfer finish | + |RESET / VERSION| 0 | | wo/ro | | Soft reset on write / Firmware version | + +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ + | START / DONE | 1 | | wo/ro | 0 | Start sequence on write / Indicates sequence finished | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | EN_EXT_START | 2 | [0] | r/w | 0 | enable external start | + | EN_EXT_START | 2 | [0] | r/w | 0 | Enable external start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | CLK_DIV | 3 | [7:0] | r/w | 1 | internal division factor for SEQ_CLK | + | CLK_DIV | 3 | [7:0] | r/w | 1 | Internal division factor for SEQ_CLK | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | COUNT | 7 - 4 | [31:0] | r/w | out_words | set the size of sequence (in output words) | + | SIZE | 7 - 4 | [31:0] | r/w | out_words | Set the size of sequence (in output words) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | WAIT | 11 - 8 | [31:0] | r/w | 0 | waits after every sequence if REPEAT != 0 repeat transfer count (0 -> forever) | + | WAIT | 11 - 8 | [31:0] | r/w | 0 | Waits after every sequence if REPEAT != 0 (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REPEAT | 15 - 12 | [31:0] | r/w | 1 | repeat sequence count (0 -> forever) | + | REPEAT | 15 - 12 | [31:0] | r/w | 1 | Repeat sequence count (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REP_START | 19 - 16 | [31:0] | r/w | 0 | position from which pattern will start in repeat mode (a first sequence always start at 0) | + | REP_START | 19 - 16 | [31:0] | r/w | 0 | Position from which pattern will start in repeat mode (first sequence always starts at 0) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_START | 23 - 20 | [31:0] | r/w | 0 | position from which pattern will start for nested loop | + | NESTED_START | 23 - 20 | [31:0] | r/w | 0 | Position from which pattern will start for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_STOP | 27 - 24 | [31:0] | r/w | 0 | position to which pattern will stop for nested loop | + | NESTED_STOP | 27 - 24 | [31:0] | r/w | 0 | Position to which pattern will stop for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_REPEAT | 31 - 28 | [31:0] | r/w | 0 | repeat count for nested loop | + | NESTED_REPEAT | 31 - 28 | [31:0] | r/w | 0 | Repeat count for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | MEM_BYTES | 35 - 32 | [31:0] | r/w | MEM_BYTE | memory size | + | MEM_BYTES | 35 - 32 | [31:0] | ro | MEM_BYTES | Memory size (read only) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DATA | 64 to 64+MEM_BYTES-1 | | r/w | unknown | memory for pattern | + | DATA | 64 to 64+MEM_BYTES-1 | | r/w | unknown | Memory for pattern | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ diff --git a/basil/firmware/modules/seq_gen/seq_gen.v b/basil/firmware/modules/seq_gen/seq_gen.v index a6a51d353..13e9df463 100644 --- a/basil/firmware/modules/seq_gen/seq_gen.v +++ b/basil/firmware/modules/seq_gen/seq_gen.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SEQ_GEN +`define SEQ_GEN + +`include "seq_gen/seq_gen_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -68,3 +74,5 @@ seq_gen_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index c81a69542..4baecd8ab 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -4,9 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SEQ_GEN_CORE +`define SEQ_GEN_CORE + +`include "utils/ramb_8_to_n.v" +`include "utils/cdc_pulse_sync.v" + `timescale 1ps/1ps `default_nettype none + module seq_gen_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16384, @@ -64,8 +71,8 @@ always @(posedge BUS_CLK) begin status_regs[6] <= DEF_BIT_OUT[23:16]; // -||- status_regs[7] <= DEF_BIT_OUT[31:24]; // -||- - status_regs[8] <= 0; // wait - status_regs[9] <= 0; // -||- + status_regs[8] <= 0; // wait + status_regs[9] <= 0; // -||- status_regs[10] <= 0; // -||- status_regs[11] <= 0; // -||- @@ -74,7 +81,7 @@ always @(posedge BUS_CLK) begin status_regs[14] <= 0; // -||- status_regs[15] <= 0; // -||- - status_regs[16] <= 0; //repeat start + status_regs[16] <= 0; // repeat start status_regs[17] <= 0; // -||- status_regs[18] <= 0; // -||- status_regs[19] <= 0; // -||- @@ -89,7 +96,7 @@ always @(posedge BUS_CLK) begin status_regs[26] <= 0; // -||- status_regs[27] <= 0; // -||- - status_regs[28] <= 0; // nested loop repat count + status_regs[28] <= 0; // nested loop repeat count status_regs[29] <= 0; // -||- status_regs[30] <= 0; // -||- status_regs[31] <= 0; // -||- @@ -210,7 +217,7 @@ wire RST_SOFT_SYNC; cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SEQ_CLK), .pulse_out(RST_SOFT_SYNC)); assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; -wire START_SYNC_CDC; +wire START_SYNC_CDC; wire START_SYNC; cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SEQ_CLK), .pulse_out(START_SYNC_CDC)); @@ -295,3 +302,5 @@ always @(posedge BUS_CLK) endmodule + +`endif diff --git a/basil/firmware/modules/seq_rec/seq_rec.v b/basil/firmware/modules/seq_rec/seq_rec.v index 6a81e5625..5142308c7 100644 --- a/basil/firmware/modules/seq_rec/seq_rec.v +++ b/basil/firmware/modules/seq_rec/seq_rec.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SEQ_REC +`define SEQ_REC + +`include "seq_rec/seq_rec_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -66,3 +72,5 @@ seq_rec_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/seq_rec/seq_rec_core.v b/basil/firmware/modules/seq_rec/seq_rec_core.v index f5e8f35b2..f1cff9a77 100644 --- a/basil/firmware/modules/seq_rec/seq_rec_core.v +++ b/basil/firmware/modules/seq_rec/seq_rec_core.v @@ -4,15 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SEQ_REC_CORE +`define SEQ_REC_CORE + +`include "utils/flag_domain_crossing.v" +`include "utils/3_stage_synchronizer.v" +`include "utils/cdc_pulse_sync.v" +`include "utils/ramb_8_to_n.v" + `timescale 1ps/1ps `default_nettype none -/* - * Possible extra options: - * - delay block that allow SEQ_EXT_START in past (enabled by parameter - for speed needed applications a simple memory circular buffer) - * - SEQ_EXT_START selections as pulse or as gate/enable - * - multi window recording (sorted with but multiple times) - */ module seq_rec_core #( parameter MEM_BYTES = 2*1024, @@ -246,3 +248,5 @@ always @(posedge BUS_CLK) CONF_READY <= 1'b1; endmodule + +`endif diff --git a/basil/firmware/modules/spi/README.rst b/basil/firmware/modules/spi/README.rst index e8f888be3..6cfa3860e 100644 --- a/basil/firmware/modules/spi/README.rst +++ b/basil/firmware/modules/spi/README.rst @@ -9,6 +9,17 @@ Module implements master serial peripheral interface. Supports simple internal l `test_SimSpi.v `_ `test_SimSpi.py `_ +**Usage notes** + +* **External start**: When ``EN`` is set, the SPI transfer can be triggered via + the ``EXT_START`` pin instead of a software write to ``START``. +* **Repeat mode**: A value of 0 in the ``REPEAT`` register causes the transfer + to repeat forever. +* **START and DONE share the same address**: The ``START`` (write-only) and + ``DONE`` (read-only) registers are aliased at the same address. Writing to + address 1 triggers a start, reading address 1 returns the done flag. + This pattern is consistent across seq_gen, spi, and pulse_gen. + **Parameters:** +--------------+---------------------+------------------------------------------------------------------------+ | Name | Default | Description | @@ -39,21 +50,19 @@ Module implements master serial peripheral interface. Supports simple internal l +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +==============+==================================+========+=======+=============+=============================================+ - | START | 1 | | wo | | start transfer on write to address | - +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DONE | 1 | [0] | ro | 0 | indicate transfer finish | + |START / DONE |1 | |wo/ro |0 |Start transfer / Indicate transfer finish | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | BIT_OUT | 4 - 3 | [15:0] | r/w | MEM_BYTES*8 | set the size of transfer in bits | + | SIZE | 4 - 3 | [15:0] | r/w | MEM_BYTES*8 | Set the size of transfer in bits | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | WAIT | 8 - 5 | [31:0] | r/w | 4 | waits after every transfer if REPEAT != 0 | + | WAIT | 8 - 5 | [31:0] | r/w | 4 | Waits after every transfer if REPEAT != 0 | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | REPEAT | 12 - 9 | [31:0] | r/w | 1 | repeat transfer count (0 -> forever) | + | REPEAT | 12 - 9 | [31:0] | r/w | 1 | Repeat transfer count (0 -> forever) | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | CONF_EN | 13 | [0] | r/w | 0 | enable external start (0-> soft start only) | + | EN | 13 | [0] | r/w | 0 | Enable external start (0 -> soft start only)| +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | MEM_BYTES | 15 - 14 | [15:0] | ro | MEM_BYTES | byte size of memory | + | MEM_BYTES | 15 - 14 | [15:0] | ro | MEM_BYTES | Byte size of memory | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DATA_OUT | 16 to 16+MEM_BYTES-1 | | r/w | unknown | memory for outgoing data | + | DATA_OUT | 16 to 16+MEM_BYTES-1 | | r/w | unknown | Memory for outgoing data | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DATA_IN | 16+MEM_BYTES to 16+2*MEM_BYTES-1 | | r/w | unknown | memory for incoming data | + | DATA_IN | 16+MEM_BYTES to 16+2*MEM_BYTES-1 | | r/w | unknown | Memory for incoming data | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ diff --git a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v index a14a4eff9..93295d91b 100644 --- a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v +++ b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v @@ -3,42 +3,106 @@ * Copyright (c) All rights reserved * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ + * + * Asymmetric true dual-port BRAM: 2048 x 8-bit (Port A) / 16384 x 1-bit (Port B). + * Total capacity: 16,384 bits → inferred as RAMB18E1 on 7-series (Kintex-7). + * + * Replaces the legacy RAMB16_S1_S9 primitive (Spartan-3/Virtex-4 era), + * which is unsupported in Vivado. + * + * Inference strategy: + * Underlying array is 16384 × 1-bit. Port B (1-bit) accesses it directly. + * Port A (8-bit) uses a single always block with a procedural for loop + * that expands to 8 consecutive 1-bit locations at {ADDRA, i[2:0]}. + * Vivado sees only two clocked ports and infers a single RAMB18E1 in + * true dual-port (TDP) mode with asymmetric widths. + * (* ram_style = "block" *) attribute forces BRAM over distributed RAM. + * + * Port mapping (unchanged from original): + * Port A: 8-bit wide, 2048 deep — ADDRA[10:0], DINA[7:0], DOUTA[7:0], WEA + * Port B: 1-bit wide, 16384 deep — ADDRB[13:0], DINB[0], DOUTB[0], WEB + * + * Read behaviour: read-first on both ports (consistent with legacy primitive). + * ------------------------------------------------------------ */ +`ifndef BLK_MEM_GEN_8_TO_1_2K +`define BLK_MEM_GEN_8_TO_1_2K + `timescale 1ps/1ps `default_nettype none -module blk_mem_gen_8_to_1_2k ( + +module blk_mem_gen_8_to_1_2k #( + // Disable a port's write logic when its write enable is tied low. + // This avoids elaborating unused cross-clock RAM write paths. + parameter PORT_A_WRITABLE = 1, + parameter PORT_B_WRITABLE = 1 +) ( CLKA, CLKB, DOUTA, DOUTB, WEA, WEB, ADDRA, ADDRB, DINA, DINB ); -input wire CLKA; -input wire CLKB; -output wire [7 : 0] DOUTA; -output wire [0 : 0] DOUTB; -input wire [0 : 0] WEA; -input wire [0 : 0] WEB; -input wire [10 : 0] ADDRA; -input wire [13 : 0] ADDRB; -input wire [7 : 0] DINA; -input wire [0 : 0] DINB; - -RAMB16_S1_S9 dpram ( - .CLKA(CLKB), - .CLKB(CLKA), - .ENB(1'b1), - .WEA(WEB), - .WEB(WEA), - .ENA(1'b1), - .SSRA(1'b0), - .SSRB(1'b0), - .DIPB(1'b0), - .ADDRA(ADDRB), - .ADDRB(ADDRA), - .DIA(DINB), - .DIB(DINA), - .DOA(DOUTB), - .DOB(DOUTA), - .DOPB() -); +input wire CLKA; +input wire CLKB; +output reg [7 : 0] DOUTA; +output reg [0 : 0] DOUTB; +input wire [0 : 0] WEA; +input wire [0 : 0] WEB; +input wire [10 : 0] ADDRA; +input wire [13 : 0] ADDRB; +input wire [7 : 0] DINA; +input wire [0 : 0] DINB; + +// ------------------------------------------------------------------- +// Underlying array: 16384 × 1-bit, total 16,384 bits. +// Vivado infers a single RAMB18E1 in true-dual-port mode with +// asymmetric widths (Port A = 8-bit, Port B = 1-bit). +// ------------------------------------------------------------------- + +(* ram_style = "block" *) +reg [0:0] ram [0:16383]; + +// ------------------------------ +// Port A — 8-bit synchronous (procedural for loop, one port) +// +// ADDRA[10:0] selects a word; bit i lives at {ADDRA, i[2:0]}. +// The procedural for loop exposes only a single write port, +// matching the Vivado BRAM inference requirements. +// ------------------------------ +integer i; + +generate + if (PORT_A_WRITABLE) begin : port_a_read_write + always @(posedge CLKA) begin + for (i = 0; i < 8; i = i + 1) begin + DOUTA[i] <= ram[{ADDRA, i[2:0]}]; + if (WEA) + ram[{ADDRA, i[2:0]}] <= DINA[i]; + end + end + end else begin : port_a_read_only + always @(posedge CLKA) begin + for (i = 0; i < 8; i = i + 1) + DOUTA[i] <= ram[{ADDRA, i[2:0]}]; + end + end +endgenerate + +// ------------------------------ +// Port B — 1-bit synchronous (simple, one port) +// ------------------------------ +generate + if (PORT_B_WRITABLE) begin : port_b_read_write + always @(posedge CLKB) begin + DOUTB <= ram[ADDRB]; + if (WEB) + ram[ADDRB] <= DINB[0]; + end + end else begin : port_b_read_only + always @(posedge CLKB) + DOUTB <= ram[ADDRB]; + end +endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/spi/spi.v b/basil/firmware/modules/spi/spi.v index 5aceab75d..0a4411cb7 100644 --- a/basil/firmware/modules/spi/spi.v +++ b/basil/firmware/modules/spi/spi.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SPI +`define SPI + +`include "spi/spi_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -79,3 +85,5 @@ spi_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/spi/spi_core.v b/basil/firmware/modules/spi/spi_core.v index 34f2e98ad..f39b918a4 100644 --- a/basil/firmware/modules/spi/spi_core.v +++ b/basil/firmware/modules/spi/spi_core.v @@ -4,270 +4,281 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`timescale 1ps/1ps +`ifndef SPI_CORE +`define SPI_CORE + +`include "spi/blk_mem_gen_8_to_1_2k.v" +`include "utils/cdc_pulse_sync.v" +`include "utils/CG_MOD_pos.v" + +`timescale 1ps / 1ps `default_nettype none + module spi_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16 ) ( - input wire BUS_CLK, - input wire BUS_RST, - input wire [ABUSWIDTH-1:0] BUS_ADD, + input wire BUS_CLK, + input wire BUS_RST, + input wire [ABUSWIDTH-1:0] BUS_ADD, /* verilator lint_off UNOPTFLAT */ // Clocked and safe in synthesis, else circular logic data_in -> memory -> data_out - input wire [7:0] BUS_DATA_IN, + input wire [ 7:0] BUS_DATA_IN, /* verilator lint_on UNOPTFLAT */ - input wire BUS_RD, - input wire BUS_WR, - output reg [7:0] BUS_DATA_OUT, + input wire BUS_RD, + input wire BUS_WR, + output reg [ 7:0] BUS_DATA_OUT, input wire SPI_CLK, output wire SCLK, - input wire SDO, - output reg SDI, - input wire EXT_START, + input wire SDO, + output reg SDI, + input wire EXT_START, output reg SEN, output reg SLD ); -localparam VERSION = 2; - -reg [7:0] status_regs [15:0]; - -wire RST; -wire SOFT_RST; - -assign RST = BUS_RST || SOFT_RST; - -localparam DEF_BIT_OUT = 8*MEM_BYTES; - -always @(posedge BUS_CLK) begin - if(RST) begin - status_regs[0] <= 0; - status_regs[1] <= 0; - status_regs[2] <= 0; - status_regs[3] <= DEF_BIT_OUT[7:0]; //bits - status_regs[4] <= DEF_BIT_OUT[15:8]; //bits - status_regs[5] <= 4; //wait - status_regs[6] <= 0; //wait - status_regs[7] <= 0; //wait - status_regs[8] <= 0; //wait - status_regs[9] <= 1; //repeat - status_regs[10] <= 0; //repeat - status_regs[11] <= 0; //repeat - status_regs[12] <= 0; //repeat - status_regs[13] <= 0; //0:enable external start + localparam VERSION = 2; + + reg [7:0] status_regs[15:0]; + + wire RST; + wire SOFT_RST; + + assign RST = BUS_RST || SOFT_RST; + + localparam DEF_BIT_OUT = 8 * MEM_BYTES; + + always @(posedge BUS_CLK) begin + if (RST) begin + status_regs[0] <= 0; + status_regs[1] <= 0; + status_regs[2] <= 0; + status_regs[3] <= DEF_BIT_OUT[7:0]; //bits + status_regs[4] <= DEF_BIT_OUT[15:8]; //bits + status_regs[5] <= 4; //wait + status_regs[6] <= 0; //wait + status_regs[7] <= 0; //wait + status_regs[8] <= 0; //wait + status_regs[9] <= 1; //repeat + status_regs[10] <= 0; //repeat + status_regs[11] <= 0; //repeat + status_regs[12] <= 0; //repeat + status_regs[13] <= 0; //0:enable external start + end else if (BUS_WR && BUS_ADD < 16) status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; + end + + reg [7:0] BUS_IN_MEM; + reg [7:0] BUS_OUT_MEM; + + wire START; + assign SOFT_RST = (BUS_ADD == 0 && BUS_WR); + assign START = (BUS_ADD == 1 && BUS_WR); + + wire [15:0] CONF_BIT_OUT; + assign CONF_BIT_OUT = {status_regs[4], status_regs[3]}; + + // TODO: not yet used + wire [7:0] CONF_CLK_DIV; + assign CONF_CLK_DIV = status_regs[2]; + reg CONF_DONE; + + wire [31:0] CONF_WAIT; + assign CONF_WAIT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]}; + + wire [31:0] CONF_REPEAT; + assign CONF_REPEAT = {status_regs[12], status_regs[11], status_regs[10], status_regs[9]}; + + wire CONF_EN; + assign CONF_EN = status_regs[13][0]; + + reg [7:0] BUS_DATA_OUT_REG; + always @(posedge BUS_CLK) begin + if (BUS_RD) begin + if (BUS_ADD == 0) BUS_DATA_OUT_REG <= VERSION; + else if (BUS_ADD == 1) BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; + else if (BUS_ADD == 13) BUS_DATA_OUT_REG <= {7'b0, CONF_EN}; + else if (BUS_ADD == 14) BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; + else if (BUS_ADD == 15) BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; + else if (BUS_ADD < 16) BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]]; end - else if(BUS_WR && BUS_ADD < 16) - status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; -end - -reg [7:0] BUS_IN_MEM; -reg [7:0] BUS_OUT_MEM; - -wire START; -assign SOFT_RST = (BUS_ADD==0 && BUS_WR); -assign START = (BUS_ADD==1 && BUS_WR); - -wire [15:0] CONF_BIT_OUT; -assign CONF_BIT_OUT = {status_regs[4],status_regs[3]}; - -// TODO: not yet used -wire [7:0] CONF_CLK_DIV; -assign CONF_CLK_DIV = status_regs[2]; -reg CONF_DONE; - -wire [31:0] CONF_WAIT; -assign CONF_WAIT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]}; - -wire [31:0] CONF_REPEAT; -assign CONF_REPEAT = {status_regs[12], status_regs[11], status_regs[10], status_regs[9]}; - -wire CONF_EN; -assign CONF_EN = status_regs[13][0]; - -reg [7:0] BUS_DATA_OUT_REG; -always @(posedge BUS_CLK) begin - if(BUS_RD) begin - if(BUS_ADD == 0) - BUS_DATA_OUT_REG <= VERSION; - else if(BUS_ADD == 1) - BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; - else if(BUS_ADD == 13) - BUS_DATA_OUT_REG <= {7'b0, CONF_EN}; - else if(BUS_ADD == 14) - BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; - else if(BUS_ADD == 15) - BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; - else if (BUS_ADD < 16) - BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]]; + end + + // if one has a synchronous memory need this to give data on next clock after read + // limitation: this module still needs to be addressed + reg [ABUSWIDTH-1:0] PREV_BUS_ADD; + always @(posedge BUS_CLK) begin + if (BUS_RD) begin + PREV_BUS_ADD <= BUS_ADD; end -end - -// if one has a synchronous memory need this to give data on next clock after read -// limitation: this module still needs to be addressed -reg [ABUSWIDTH-1:0] PREV_BUS_ADD; -always @(posedge BUS_CLK) begin - if(BUS_RD) begin - PREV_BUS_ADD <= BUS_ADD; + end + + always @(*) begin + if (PREV_BUS_ADD < 16) BUS_DATA_OUT = BUS_DATA_OUT_REG; + else if (PREV_BUS_ADD < 16 + MEM_BYTES) BUS_DATA_OUT = BUS_IN_MEM; + else if (PREV_BUS_ADD < 16 + MEM_BYTES + MEM_BYTES) BUS_DATA_OUT = BUS_OUT_MEM; + else BUS_DATA_OUT = 8'hxx; + end + + reg [32:0] out_bit_cnt; + + + wire [13:0] memout_addrb; + assign memout_addrb = out_bit_cnt; + wire [10:0] memout_addra; + assign memout_addra = (BUS_ADD - 16); + + reg [7:0] BUS_DATA_IN_IB; + wire [7:0] BUS_IN_MEM_IB; + wire [7:0] BUS_OUT_MEM_IB; + integer i; + always @(*) begin + for (i = 0; i < 8; i = i + 1) begin + BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i]; + BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i]; + BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i]; end -end - -always @(*) begin - if(PREV_BUS_ADD < 16) - BUS_DATA_OUT = BUS_DATA_OUT_REG; - else if(PREV_BUS_ADD < 16+MEM_BYTES) - BUS_DATA_OUT = BUS_IN_MEM; - else if(PREV_BUS_ADD < 16+MEM_BYTES+MEM_BYTES) - BUS_DATA_OUT = BUS_OUT_MEM; - else - BUS_DATA_OUT = 8'hxx; -end - -reg [32:0] out_bit_cnt; - - -wire [13:0] memout_addrb; -assign memout_addrb = out_bit_cnt; -wire [10:0] memout_addra; -assign memout_addra = (BUS_ADD-16); - -reg [7:0] BUS_DATA_IN_IB; -wire [7:0] BUS_IN_MEM_IB; -wire [7:0] BUS_OUT_MEM_IB; -integer i; -always @(*) begin - for(i=0;i<8;i=i+1) begin - BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i]; - BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i]; - BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i]; - end -end - -wire SDI_MEM; - -blk_mem_gen_8_to_1_2k memout( - .CLKA(BUS_CLK), - .CLKB(SPI_CLK), - .DOUTA(BUS_IN_MEM_IB), - .DOUTB(SDI_MEM), - .WEA(BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES), - .WEB(1'b0), - .ADDRA(memout_addra), - .ADDRB(memout_addrb), - .DINA(BUS_DATA_IN_IB), - .DINB(1'b0) -); - - -wire [10:0] ADDRA_MIN; -assign ADDRA_MIN = (BUS_ADD-16-MEM_BYTES); -wire [13:0] ADDRB_MIN; -assign ADDRB_MIN = out_bit_cnt-1; -reg SEN_INT; - -blk_mem_gen_8_to_1_2k memin( - .CLKA(BUS_CLK), - .CLKB(SPI_CLK), - .DOUTA(BUS_OUT_MEM_IB), - .DOUTB(), - .WEA(1'b0), - .WEB(SEN_INT), - .ADDRA(ADDRA_MIN), - .ADDRB(ADDRB_MIN), - .DINA(BUS_DATA_IN_IB), - .DINB(SDO) -); - -wire RST_SYNC; -wire RST_SOFT_SYNC; -cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SPI_CLK), .pulse_out(RST_SOFT_SYNC)); -assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; - -wire START_SYNC; -cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SPI_CLK), .pulse_out(START_SYNC)); - -wire EXT_START_PULSE; -reg [2:0] EXT_START_FF; -always @(posedge SPI_CLK) // first stage + end + + wire SDI_MEM; + + blk_mem_gen_8_to_1_2k #( + .PORT_A_WRITABLE(1), + .PORT_B_WRITABLE(0) + ) memout ( + .CLKA (BUS_CLK), + .CLKB (SPI_CLK), + .DOUTA(BUS_IN_MEM_IB), + .DOUTB(SDI_MEM), + .WEA (BUS_WR && BUS_ADD >= 16 && BUS_ADD < 16 + MEM_BYTES), + .WEB (1'b0), + .ADDRA(memout_addra), + .ADDRB(memout_addrb), + .DINA (BUS_DATA_IN_IB), + .DINB (1'b0) + ); + + + wire [10:0] ADDRA_MIN; + assign ADDRA_MIN = (BUS_ADD - 16 - MEM_BYTES); + wire [13:0] ADDRB_MIN; + assign ADDRB_MIN = out_bit_cnt - 1; + reg SEN_INT; + + blk_mem_gen_8_to_1_2k #( + .PORT_A_WRITABLE(0), + .PORT_B_WRITABLE(1) + ) memin ( + .CLKA (BUS_CLK), + .CLKB (SPI_CLK), + .DOUTA(BUS_OUT_MEM_IB), + .DOUTB(), + .WEA (1'b0), + .WEB (SEN_INT), + .ADDRA(ADDRA_MIN), + .ADDRB(ADDRB_MIN), + .DINA (BUS_DATA_IN_IB), + .DINB (SDO) + ); + + wire RST_SYNC; + wire RST_SOFT_SYNC; + cdc_pulse_sync rst_pulse_sync ( + .clk_in(BUS_CLK), + .pulse_in(RST), + .clk_out(SPI_CLK), + .pulse_out(RST_SOFT_SYNC) + ); + assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; + + wire START_SYNC; + cdc_pulse_sync start_pulse_sync ( + .clk_in(BUS_CLK), + .pulse_in(START), + .clk_out(SPI_CLK), + .pulse_out(START_SYNC) + ); + + wire EXT_START_PULSE; + reg [2:0] EXT_START_FF; + always @(posedge SPI_CLK) // first stage begin EXT_START_FF[0] <= EXT_START; EXT_START_FF[1] <= EXT_START_FF[0]; EXT_START_FF[2] <= EXT_START_FF[1]; -end -assign EXT_START_PULSE = !EXT_START_FF[2] & EXT_START_FF[1]; - -wire [32:0] STOP_BIT; -assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT; -reg [31:0] REPEAT_COUNT; - -wire REP_START; -assign REP_START = (out_bit_cnt == STOP_BIT && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT)); - -reg REP_START_DLY; -always @(posedge SPI_CLK) - REP_START_DLY <= REP_START; - -always @(posedge SPI_CLK) - if (RST_SYNC) - SEN_INT <= 0; - else if(START_SYNC || (EXT_START_PULSE && CONF_EN) || REP_START_DLY) - SEN_INT <= 1; - else if(out_bit_cnt == CONF_BIT_OUT) - SEN_INT <= 0; - -always @(posedge SPI_CLK) - if (RST_SYNC) - out_bit_cnt <= 0; - else if(START_SYNC || (EXT_START_PULSE && CONF_EN)) - out_bit_cnt <= 1; - else if(out_bit_cnt == STOP_BIT) - out_bit_cnt <= 0; - //else if(out_bit_cnt == CONF_BIT_OUT & REPEAT_COUNT == CONF_REPEAT & CONF_REPEAT!=0) - // out_bit_cnt <= 0; - else if(REP_START_DLY) - out_bit_cnt <= 1; - else if(out_bit_cnt != 0) - out_bit_cnt <= out_bit_cnt + 1; - -always @(posedge SPI_CLK) - if (RST_SYNC || START_SYNC || (EXT_START_PULSE && CONF_EN)) - REPEAT_COUNT <= 1; - else if(out_bit_cnt == STOP_BIT) - REPEAT_COUNT <= REPEAT_COUNT + 1; + end + assign EXT_START_PULSE = !EXT_START_FF[2] & EXT_START_FF[1]; + wire [32:0] STOP_BIT; + assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT; + reg [31:0] REPEAT_COUNT; -reg [1:0] sync_ld; -always @(posedge SPI_CLK) begin - sync_ld[0] <= SEN_INT; - sync_ld[1] <= sync_ld[0]; -end + wire REP_START; + assign REP_START = (out_bit_cnt == STOP_BIT && (CONF_REPEAT == 0 || REPEAT_COUNT < CONF_REPEAT)); -always @(posedge SPI_CLK) - SLD <= (sync_ld[1]==1 && sync_ld[0]==0); + reg REP_START_DLY; + always @(posedge SPI_CLK) REP_START_DLY <= REP_START; -wire DONE = out_bit_cnt == STOP_BIT && REPEAT_COUNT >= CONF_REPEAT; -wire DONE_SYNC, EXT_START_PULSE_SYNC; -cdc_pulse_sync done_pulse_sync (.clk_in(SPI_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC)); -cdc_pulse_sync done_pulse_ext_start (.clk_in(SPI_CLK), .pulse_in(EXT_START_PULSE), .clk_out(BUS_CLK), .pulse_out(EXT_START_PULSE_SYNC)); + always @(posedge SPI_CLK) + if (RST_SYNC) SEN_INT <= 0; + else if (START_SYNC || (EXT_START_PULSE && CONF_EN) || REP_START_DLY) SEN_INT <= 1; + else if (out_bit_cnt == CONF_BIT_OUT) SEN_INT <= 0; -always @(posedge BUS_CLK) - if(RST) - CONF_DONE <= 1; - else if(START || (EXT_START_PULSE_SYNC && CONF_EN)) - CONF_DONE <= 0; - else if(DONE_SYNC) - CONF_DONE <= 1; + always @(posedge SPI_CLK) + if (RST_SYNC) out_bit_cnt <= 0; + else if (START_SYNC || (EXT_START_PULSE && CONF_EN)) out_bit_cnt <= 1; + else if (out_bit_cnt == STOP_BIT) out_bit_cnt <= 0; + //else if(out_bit_cnt == CONF_BIT_OUT & REPEAT_COUNT == CONF_REPEAT & CONF_REPEAT!=0) + // out_bit_cnt <= 0; + else if (REP_START_DLY) out_bit_cnt <= 1; + else if (out_bit_cnt != 0) out_bit_cnt <= out_bit_cnt + 1; -CG_MOD_pos icg2(.ck_in(SPI_CLK), .enable(SEN), .ck_out(SCLK)); + always @(posedge SPI_CLK) + if (RST_SYNC || START_SYNC || (EXT_START_PULSE && CONF_EN)) REPEAT_COUNT <= 1; + else if (out_bit_cnt == STOP_BIT) REPEAT_COUNT <= REPEAT_COUNT + 1; -always @(negedge SPI_CLK) - SDI <= SDI_MEM & SEN_INT; -always @(negedge SPI_CLK) - SEN <= SEN_INT; + reg [1:0] sync_ld; + always @(posedge SPI_CLK) begin + sync_ld[0] <= SEN_INT; + sync_ld[1] <= sync_ld[0]; + end + + always @(posedge SPI_CLK) SLD <= (sync_ld[1] == 1 && sync_ld[0] == 0); + + wire DONE = out_bit_cnt == STOP_BIT && REPEAT_COUNT >= CONF_REPEAT; + wire DONE_SYNC, EXT_START_PULSE_SYNC; + cdc_pulse_sync done_pulse_sync ( + .clk_in(SPI_CLK), + .pulse_in(DONE), + .clk_out(BUS_CLK), + .pulse_out(DONE_SYNC) + ); + cdc_pulse_sync done_pulse_ext_start ( + .clk_in(SPI_CLK), + .pulse_in(EXT_START_PULSE), + .clk_out(BUS_CLK), + .pulse_out(EXT_START_PULSE_SYNC) + ); + + always @(posedge BUS_CLK) + if (RST) CONF_DONE <= 1; + else if (START || (EXT_START_PULSE_SYNC && CONF_EN)) CONF_DONE <= 0; + else if (DONE_SYNC) CONF_DONE <= 1; + + CG_MOD_pos icg2 ( + .ck_in (SPI_CLK), + .enable(SEN), + .ck_out(SCLK) + ); + + always @(negedge SPI_CLK) SDI <= SDI_MEM & SEN_INT; + + always @(negedge SPI_CLK) SEN <= SEN_INT; endmodule + +`endif diff --git a/basil/firmware/modules/sram_fifo/sram_fifo.v b/basil/firmware/modules/sram_fifo/sram_fifo.v index e13099913..297b29ac2 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SRAM_FIFO +`define SRAM_FIFO + +`include "sram_fifo/sram_fifo_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -101,3 +107,5 @@ sram_fifo_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/sram_fifo/sram_fifo_core.v b/basil/firmware/modules/sram_fifo/sram_fifo_core.v index 63c21dbaf..71ae42442 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo_core.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo_core.v @@ -4,9 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef SRAM_FIFO_CORE +`define SRAM_FIFO_CORE + +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module sram_fifo_core #( parameter DEPTH = 21'h10_0000, parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent @@ -306,3 +312,5 @@ always @(posedge BUS_CLK) begin end endmodule + +`endif diff --git a/basil/firmware/modules/tb/silbusb.v b/basil/firmware/modules/tb/silbusb.v index b21534fb9..7ecaaf059 100644 --- a/basil/firmware/modules/tb/silbusb.v +++ b/basil/firmware/modules/tb/silbusb.v @@ -10,6 +10,9 @@ * $Date:: $: */ +`ifndef SILIBUSB +`define SILIBUSB + module SiLibUSB (input FCLK); reg RD_B; @@ -103,3 +106,5 @@ module SiLibUSB (input FCLK); endtask endmodule + +`endif diff --git a/basil/firmware/modules/tb/uartlib.v b/basil/firmware/modules/tb/uartlib.v index 1b405c96f..ff6cf9118 100644 --- a/basil/firmware/modules/tb/uartlib.v +++ b/basil/firmware/modules/tb/uartlib.v @@ -1,3 +1,6 @@ +`ifndef UARTLIB +`define UARTLIB + `timescale 1ns / 100ps module uartlib( @@ -97,3 +100,5 @@ module uartlib( endtask endmodule + +`endif diff --git a/basil/firmware/modules/tdc_s3/tdc_s3.v b/basil/firmware/modules/tdc_s3/tdc_s3.v index feb624812..2cba13591 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TDC_S3 +`define TDC_S3 + +`include "tdc_s3/tdc_s3_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -105,3 +111,5 @@ tdc_s3_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tdc_s3/tdc_s3_core.v b/basil/firmware/modules/tdc_s3/tdc_s3_core.v index f9e6ac7b1..521326884 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3_core.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3_core.v @@ -4,9 +4,19 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TDC_S3_CORE +`define TDC_S3_CORE + +`include "utils/flag_domain_crossing.v" +`include "utils/3_stage_synchronizer.v" +`include "utils/ddr_des.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module tdc_s3_core #( parameter DATA_IDENTIFIER = 4'b0100, parameter CLKDV = 4, // factor of CLK160 to DV_CLK, minimal divider of 2 @@ -690,3 +700,5 @@ end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/controller.v b/basil/firmware/modules/tdl_tdc/controller.v index 3575f2fef..54dffefe1 100644 --- a/basil/firmware/modules/tdl_tdc/controller.v +++ b/basil/firmware/modules/tdl_tdc/controller.v @@ -2,6 +2,9 @@ // multiplexer, controling the corse counter, arming, calibration // states and the trigger distance mode. Furthermore counts successful events // and tdl misses. +`ifndef CONTROLLER +`define CONTROLLER + module controller #( parameter state_bits = 4, parameter mux_bits =2 @@ -149,6 +152,8 @@ always @(posedge CLK) begin end MISSED: miss_cnt <= miss_cnt + 1; + default: begin + end endcase end @@ -224,7 +229,10 @@ always @(posedge CLK) begin CALIB_HIT: state <= CALIB; MISSED: state <= IDLE_TRIG; RESET: state <= IDLE; + default: state <= RESET; endcase end end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v index fd8746a3d..8f6a57132 100644 --- a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v @@ -1,5 +1,8 @@ //`include "tdl_tdc/counter/slimfast_multioption_counter.xdc" //`include "tdl_tdc/counter/signal_clipper.vhdl" +`ifndef SLIMFAST_MULTIOPTION_COUNTER +`define SLIMFAST_MULTIOPTION_COUNTER + `include "utils/pulse_gen_rising.v" //`default_nettype none @@ -167,3 +170,5 @@ assign countout[outputwidth-1] = SFC_slow_counts[size-3]; assign countout[outputwidth-2:0] = {SFC_slow_counts[size-4:0],fast_counts}; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v index c8c8c5650..2b0b2c4d6 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +++ b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v @@ -24,6 +24,9 @@ //-- -- //--------------------------------------------------------------------- +`ifndef CARRYSAMPLER_SPARTAN6_20PS +`define CARRYSAMPLER_SPARTAN6_20PS + module CHAIN_CELL (CINIT, CI, CO, DO, CLK); output wire [3:0] DO; @@ -110,3 +113,5 @@ module carry_sampler_spartan6 (d, q, CLK); `endif endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v index c98039893..739a7e97a 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +++ b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v @@ -1,3 +1,6 @@ +`ifndef SAMPLE_DESER +`define SAMPLE_DESER + module sample_deser #( parameter dlyline_bits = 96, parameter internally_rising = 1'b1, @@ -113,3 +116,5 @@ always @(posedge CLK_SLOW) begin end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/priority_encoder.v b/basil/firmware/modules/tdl_tdc/priority_encoder.v index ef2337ac8..f041266e8 100644 --- a/basil/firmware/modules/tdl_tdc/priority_encoder.v +++ b/basil/firmware/modules/tdl_tdc/priority_encoder.v @@ -4,6 +4,9 @@ //* SiLab, Physics Institute, University of Bonn //* ------------------------------------------------------------ //*/ +`ifndef PRIORITY_ENCODER +`define PRIORITY_ENCODER + module priority_encoder( input wire CLK, input wire [96-1:0] sample, @@ -70,3 +73,5 @@ end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/sw_interface.v b/basil/firmware/modules/tdl_tdc/sw_interface.v index fe317b8a5..91f015234 100644 --- a/basil/firmware/modules/tdl_tdc/sw_interface.v +++ b/basil/firmware/modules/tdl_tdc/sw_interface.v @@ -1,4 +1,10 @@ +`ifndef TDC_SW_INTERFACE +`define TDC_SW_INTERFACE + `include "tdl_tdc/utils/graycode_2stage_cdc.v" +`include "utils/bus_to_ip.v" +`include "utils/flag_domain_crossing.v" +`include "utils/3_stage_synchronizer.v" module tdc_sw_interface #( parameter VERSION = 8'b00000000, @@ -250,3 +256,5 @@ assign arm_flag = ~ext_arm_clk_ff & ext_arm_clk; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/tdl_supersampler.v b/basil/firmware/modules/tdl_tdc/tdl_supersampler.v index c8f9221dc..efa224d08 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +++ b/basil/firmware/modules/tdl_tdc/tdl_supersampler.v @@ -1,3 +1,6 @@ +`ifndef TDL_AND_DETECTOR +`define TDL_AND_DETECTOR + `include "tdl_tdc/delayline/carrysampler_spartan6_20ps.v" `include "tdl_tdc/delayline/sample_deser.v" @@ -46,3 +49,5 @@ sample_deser #( assign sample = internally_rising ? hit_sample : ~hit_sample; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc.v b/basil/firmware/modules/tdl_tdc/tdl_tdc.v index 8deafa99f..fab6f125c 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc.v @@ -5,8 +5,14 @@ * ------------------------------------------------------------ */ +`ifndef TDL_TDC +`define TDL_TDC + `include "tdl_tdc/sw_interface.v" `include "tdl_tdc/tdl_tdc_core.v" +`include "utils/bus_to_ip.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" module tdl_tdc #( parameter BASEADDR = 32'h0000, @@ -167,3 +173,5 @@ tdc_sw_interface #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v b/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v index 5270f1a3f..92cffd016 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v @@ -5,6 +5,9 @@ * ------------------------------------------------------------ */ +`ifndef TDC_CORE +`define TDC_CORE + `include "tdl_tdc/tdl_supersampler.v" `include "tdl_tdc/counter/slimfast_multioption_counter.v" `include "tdl_tdc/controller.v" @@ -205,3 +208,5 @@ word_broker #( .out_word(out_word) ); endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/utils/delay_n.v b/basil/firmware/modules/tdl_tdc/utils/delay_n.v index 7d0bcc4fb..cbe949af9 100644 --- a/basil/firmware/modules/tdl_tdc/utils/delay_n.v +++ b/basil/firmware/modules/tdl_tdc/utils/delay_n.v @@ -1,3 +1,6 @@ +`ifndef DELAY_N +`define DELAY_N + module delay_n #( parameter n = 3, parameter width = 8 @@ -21,3 +24,5 @@ end assign delayed_signal = delay_taps[n-1]; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v b/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v index b71463885..934f4c609 100644 --- a/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +++ b/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v @@ -1,3 +1,6 @@ +`ifndef GRAYCODE_2STAGE_CDC +`define GRAYCODE_2STAGE_CDC + module graycode_2stage_cdc #(DATA_WIDTH = 8) ( input wire IN_CLK, input wire OUT_CLK, @@ -26,3 +29,5 @@ end assign data_out_clk = data_bus_clk; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/word_broker.v b/basil/firmware/modules/tdl_tdc/word_broker.v index b77458e19..84ebb55fc 100644 --- a/basil/firmware/modules/tdl_tdc/word_broker.v +++ b/basil/firmware/modules/tdl_tdc/word_broker.v @@ -1,3 +1,6 @@ +`ifndef WORD_BROKER +`define WORD_BROKER + module word_broker #( parameter DATA_IDENTIFIER = 4'b0100, parameter state_bits = 4, @@ -124,3 +127,5 @@ always @(posedge CLK) begin end endmodule + +`endif diff --git a/basil/firmware/modules/timestamp/timestamp.v b/basil/firmware/modules/timestamp/timestamp.v index 062dcf8cd..fa6ba5561 100644 --- a/basil/firmware/modules/timestamp/timestamp.v +++ b/basil/firmware/modules/timestamp/timestamp.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TIMESTAMP +`define TIMESTAMP + +`include "timestamp/timestamp_core.v" +`include "utils/bus_to_ip.v" + `timescale 1ps/1ps `default_nettype none @@ -78,3 +84,5 @@ timestamp_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/timestamp/timestamp_core.v b/basil/firmware/modules/timestamp/timestamp_core.v index a404e68a0..dc502f528 100644 --- a/basil/firmware/modules/timestamp/timestamp_core.v +++ b/basil/firmware/modules/timestamp/timestamp_core.v @@ -4,9 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TIMESTAMP_CORE +`define TIMESTAMP_CORE + +`include "utils/cdc_pulse_sync.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none + module timestamp_core #( parameter ABUSWIDTH = 16, parameter IDENTIFIER = 4'b0001 @@ -211,3 +219,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tlu/tlu_controller.v b/basil/firmware/modules/tlu/tlu_controller.v index 6a013f7e2..312b273f0 100644 --- a/basil/firmware/modules/tlu/tlu_controller.v +++ b/basil/firmware/modules/tlu/tlu_controller.v @@ -4,6 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TLU_CONTROLLER +`define TLU_CONTROLLER + +`include "tlu/tlu_controller_core.v" +`include "utils/bus_to_ip.v" `timescale 1ps/1ps `default_nettype none @@ -120,3 +125,5 @@ tlu_controller_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tlu/tlu_controller_core.v b/basil/firmware/modules/tlu/tlu_controller_core.v index 07028e7d7..ef63dcf99 100644 --- a/basil/firmware/modules/tlu/tlu_controller_core.v +++ b/basil/firmware/modules/tlu/tlu_controller_core.v @@ -4,6 +4,14 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TLU_CONTROLLER_CORE +`define TLU_CONTROLLER_CORE + +`include "utils/flag_domain_crossing.v" +`include "utils/3_stage_synchronizer.v" +`include "tlu/tlu_controller_fsm.v" +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none @@ -15,6 +23,8 @@ * * TLU controller supporting EUDET TLU 0.1/0.2 */ +`default_nettype none + module tlu_controller_core #( parameter ABUSWIDTH = 16, @@ -926,3 +936,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/tlu/tlu_controller_fsm.v b/basil/firmware/modules/tlu/tlu_controller_fsm.v index 866556c3e..5c243d822 100644 --- a/basil/firmware/modules/tlu/tlu_controller_fsm.v +++ b/basil/firmware/modules/tlu/tlu_controller_fsm.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef TLU_CONTROLLER_FSM +`define TLU_CONTROLLER_FSM + `timescale 1ps/1ps `default_nettype none + module tlu_controller_fsm #( parameter DIVISOR = 8, parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17, @@ -548,6 +552,10 @@ begin FIFO_ACKNOWLEDGED <= 1'b1; end + default: + begin + end + endcase end end @@ -581,3 +589,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/uart/uart.v b/basil/firmware/modules/uart/uart.v index 0ec3193ef..89eae9cb6 100644 --- a/basil/firmware/modules/uart/uart.v +++ b/basil/firmware/modules/uart/uart.v @@ -1,3 +1,6 @@ +`ifndef UART +`define UART + `timescale 1ns / 1ps // Documented Verilog UART // Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz) @@ -194,3 +197,5 @@ always @(posedge clk) begin //or posedge rst end endmodule + +`endif diff --git a/basil/firmware/modules/uart/uart_master.v b/basil/firmware/modules/uart/uart_master.v index 9d71e93a3..23a25b2c9 100644 --- a/basil/firmware/modules/uart/uart_master.v +++ b/basil/firmware/modules/uart/uart_master.v @@ -12,6 +12,9 @@ * Initial version: M. Lemarenko */ +`ifndef UART_MASTER +`define UART_MASTER + module uart_master( input UART_CLK_X4, input UART_RST, @@ -271,3 +274,5 @@ always @(posedge clk or posedge UART_RST) endmodule + +`endif diff --git a/basil/firmware/modules/utils/3_stage_synchronizer.v b/basil/firmware/modules/utils/3_stage_synchronizer.v index 12f2d145b..ffe065e13 100644 --- a/basil/firmware/modules/utils/3_stage_synchronizer.v +++ b/basil/firmware/modules/utils/3_stage_synchronizer.v @@ -4,10 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef THREE_STAGE_SYNCHRONIZER +`define THREE_STAGE_SYNCHRONIZER + `timescale 1ps/1ps `default_nettype none -// synchronizing asynchronous signals/flags, prevents metastable events module three_stage_synchronizer #( parameter WIDTH = 1 @@ -39,3 +41,5 @@ end assign OUT = out_d_ff_3; endmodule + +`endif diff --git a/basil/firmware/modules/utils/BUFG_sim.v b/basil/firmware/modules/utils/BUFG.v similarity index 88% rename from basil/firmware/modules/utils/BUFG_sim.v rename to basil/firmware/modules/utils/BUFG.v index e42bb0e7e..d25320eb7 100644 --- a/basil/firmware/modules/utils/BUFG_sim.v +++ b/basil/firmware/modules/utils/BUFG.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BUFG_SIM +`define BUFG_SIM + `timescale 1ps/1ps `default_nettype none @@ -16,3 +19,5 @@ module BUFG ( assign O = I; endmodule + +`endif diff --git a/basil/firmware/modules/utils/CG_MOD_neg.v b/basil/firmware/modules/utils/CG_MOD_neg.v index d62302473..e6fa98234 100644 --- a/basil/firmware/modules/utils/CG_MOD_neg.v +++ b/basil/firmware/modules/utils/CG_MOD_neg.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CG_MOD_NEG +`define CG_MOD_NEG + `timescale 1ps/1ps `default_nettype none @@ -27,3 +30,5 @@ if (ck_in) assign ck_out = ck_in | ~enl; endmodule + +`endif diff --git a/basil/firmware/modules/utils/CG_MOD_pos.v b/basil/firmware/modules/utils/CG_MOD_pos.v index fb8c08e3c..e499c65da 100644 --- a/basil/firmware/modules/utils/CG_MOD_pos.v +++ b/basil/firmware/modules/utils/CG_MOD_pos.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CG_MOD_POS +`define CG_MOD_POS + `timescale 1ps/1ps `default_nettype none @@ -28,3 +31,5 @@ if (ck_inb) assign ck_out = ck_in & enl; endmodule + +`endif diff --git a/basil/firmware/modules/utils/DCM_sim.v b/basil/firmware/modules/utils/DCM.v similarity index 97% rename from basil/firmware/modules/utils/DCM_sim.v rename to basil/firmware/modules/utils/DCM.v index e04df01fd..bd2e070a9 100644 --- a/basil/firmware/modules/utils/DCM_sim.v +++ b/basil/firmware/modules/utils/DCM.v @@ -1,9 +1,13 @@ /** Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx */ +`ifndef DCM_SIM +`define DCM_SIM + `timescale 1ps/1ps `default_nettype none + module clock_divider_sim #( parameter DIVISOR = 2 ) ( @@ -129,5 +133,8 @@ clock_divider_sim #( ); assign LOCKED = 1'b1; +assign PSDONE = 1'b0; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUF.v b/basil/firmware/modules/utils/IBUF.v new file mode 100644 index 000000000..5f27a7c62 --- /dev/null +++ b/basil/firmware/modules/utils/IBUF.v @@ -0,0 +1,26 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`ifndef IBUF_SIM +`define IBUF_SIM + +`timescale 1ps/1ps +`default_nettype none + + +module IBUF #( + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT" +) ( + output wire O, + input wire I +); + +assign O = I; + +endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUFDS_sim.v b/basil/firmware/modules/utils/IBUFDS.v similarity index 76% rename from basil/firmware/modules/utils/IBUFDS_sim.v rename to basil/firmware/modules/utils/IBUFDS.v index b7ff8d7ba..1ba1de2df 100644 --- a/basil/firmware/modules/utils/IBUFDS_sim.v +++ b/basil/firmware/modules/utils/IBUFDS.v @@ -4,12 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef IBUFDS_SIM +`define IBUFDS_SIM + `timescale 1ps/1ps `default_nettype none module IBUFDS #( parameter DIFF_TERM = "TRUE", - parameter IOSTANDARD = "LVDS_25" + parameter IBUF_LOW_PWR = "FALSE", + parameter IOSTANDARD = "LVDS_25" ) ( output wire O, input wire I, IB @@ -18,3 +22,5 @@ module IBUFDS #( assign O = I && !IB; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUFG.v b/basil/firmware/modules/utils/IBUFG.v new file mode 100644 index 000000000..a50b38a18 --- /dev/null +++ b/basil/firmware/modules/utils/IBUFG.v @@ -0,0 +1,26 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`ifndef IBUFG_SIM +`define IBUFG_SIM + +`timescale 1ps/1ps +`default_nettype none + + +module IBUFG #( + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT" +) ( + output wire O, + input wire I +); + +assign O = I; + +endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUFGDS_sim.v b/basil/firmware/modules/utils/IBUFGDS.v similarity index 76% rename from basil/firmware/modules/utils/IBUFGDS_sim.v rename to basil/firmware/modules/utils/IBUFGDS.v index d9ef8bb0e..a83f6bb20 100644 --- a/basil/firmware/modules/utils/IBUFGDS_sim.v +++ b/basil/firmware/modules/utils/IBUFGDS.v @@ -4,12 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef IBUFGDS_SIM +`define IBUFGDS_SIM + `timescale 1ps/1ps `default_nettype none module IBUFGDS #( parameter DIFF_TERM = "TRUE", - parameter IOSTANDARD = "LVDS_25" + parameter IBUF_LOW_PWR = "FALSE", + parameter IOSTANDARD = "LVDS_25" ) ( output wire O, input wire I, IB @@ -18,3 +22,5 @@ module IBUFGDS #( assign O = I && !IB; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_sim.v b/basil/firmware/modules/utils/IDDR.v similarity index 94% rename from basil/firmware/modules/utils/IDDR_sim.v rename to basil/firmware/modules/utils/IDDR.v index 3e9e2610e..20dde34ea 100644 --- a/basil/firmware/modules/utils/IDDR_sim.v +++ b/basil/firmware/modules/utils/IDDR.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef IDDR_SIM +`define IDDR_SIM + `timescale 1ps/1ps `default_nettype none @@ -42,3 +45,5 @@ end endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_s3.v b/basil/firmware/modules/utils/IDDR_s3.v index 1746699c0..89025c792 100644 --- a/basil/firmware/modules/utils/IDDR_s3.v +++ b/basil/firmware/modules/utils/IDDR_s3.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef IDDR_S3_SIM +`define IDDR_S3_SIM + `timescale 1ps/1ps `default_nettype none @@ -25,3 +28,5 @@ IFDDRRSE IFDDRRSE_inst ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_s3_noibuf.v b/basil/firmware/modules/utils/IDDR_s3_noibuf.v index b96a51f3c..f82b800de 100644 --- a/basil/firmware/modules/utils/IDDR_s3_noibuf.v +++ b/basil/firmware/modules/utils/IDDR_s3_noibuf.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef IDDR_S3_NOIBUF_SIM +`define IDDR_S3_NOIBUF_SIM + `timescale 1ps/1ps `default_nettype none @@ -34,3 +37,5 @@ FDRSE F1 ( defparam F1.INIT = "0"; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_s6.v b/basil/firmware/modules/utils/IDDR_s6.v index 335c03e1c..a46dd756d 100644 --- a/basil/firmware/modules/utils/IDDR_s6.v +++ b/basil/firmware/modules/utils/IDDR_s6.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef IDDR_S6_SIM +`define IDDR_S6_SIM + `timescale 1ps/1ps `default_nettype none @@ -25,3 +28,5 @@ IDDR2 IDDR2_inst ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/IOBUF.v b/basil/firmware/modules/utils/IOBUF.v new file mode 100644 index 000000000..99e057481 --- /dev/null +++ b/basil/firmware/modules/utils/IOBUF.v @@ -0,0 +1,31 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`ifndef IOBUF_SIM +`define IOBUF_SIM + +`timescale 1ps/1ps +`default_nettype none + + +module IOBUF #( + parameter DRIVE = 12, + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SLEW = "SLOW" +) ( + inout wire IO, + input wire I, + output wire O, + input wire T +); + +assign IO = T ? 1'bz : I; +assign O = IO; + +endmodule + +`endif diff --git a/basil/firmware/modules/utils/OBUF.v b/basil/firmware/modules/utils/OBUF.v new file mode 100644 index 000000000..eb457ecfc --- /dev/null +++ b/basil/firmware/modules/utils/OBUF.v @@ -0,0 +1,27 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`ifndef OBUF_SIM +`define OBUF_SIM + +`timescale 1ps/1ps +`default_nettype none + + +module OBUF #( + parameter DRIVE = 12, + parameter IOSTANDARD = "DEFAULT", + parameter SLEW = "SLOW" +) ( + output wire O, + input wire I +); + +assign O = I; + +endmodule + +`endif diff --git a/basil/firmware/modules/utils/OBUFDS_sim.v b/basil/firmware/modules/utils/OBUFDS.v similarity index 76% rename from basil/firmware/modules/utils/OBUFDS_sim.v rename to basil/firmware/modules/utils/OBUFDS.v index 8d27c3cc9..65ca9f7b9 100644 --- a/basil/firmware/modules/utils/OBUFDS_sim.v +++ b/basil/firmware/modules/utils/OBUFDS.v @@ -4,11 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef OBUFDS_SIM +`define OBUFDS_SIM + `timescale 1ps/1ps `default_nettype none module OBUFDS #( - parameter IOSTANDARD = "LVDS_25" + parameter IOSTANDARD = "LVDS_25", + parameter SLEW = "SLOW" ) ( output wire O, OB, input wire I @@ -18,3 +22,5 @@ assign O = I; assign OB = !I; endmodule + +`endif diff --git a/basil/firmware/modules/utils/ODDR_sim.v b/basil/firmware/modules/utils/ODDR.v similarity index 57% rename from basil/firmware/modules/utils/ODDR_sim.v rename to basil/firmware/modules/utils/ODDR.v index 1f92be176..f35a0e829 100644 --- a/basil/firmware/modules/utils/ODDR_sim.v +++ b/basil/firmware/modules/utils/ODDR.v @@ -4,14 +4,25 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef ODDR_SIM +`define ODDR_SIM + `timescale 1ps/1ps `default_nettype none -module ODDR ( - input wire D1, D2, - input wire C, CE, R, S, - output wire Q +module ODDR #( + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", + parameter INIT = 1'b0, + parameter SRTYPE = "SYNC" +)( + output wire Q, + input wire C, + input wire CE, + input wire D1, + input wire D2, + input wire R, + input wire S ); reg Q1, Q2; @@ -25,3 +36,5 @@ always @(negedge C) assign Q = C ? Q1 & CE : Q2 & CE; endmodule + +`endif diff --git a/basil/firmware/modules/utils/ODDR_s3.v b/basil/firmware/modules/utils/ODDR_s3.v index c823d2205..8032682cf 100644 --- a/basil/firmware/modules/utils/ODDR_s3.v +++ b/basil/firmware/modules/utils/ODDR_s3.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef ODDR_S3_SIM +`define ODDR_S3_SIM + `timescale 1ps/1ps `default_nettype none @@ -26,3 +29,5 @@ OFDDRRSE OFDDRRSE_INST ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/ODDR_s6.v b/basil/firmware/modules/utils/ODDR_s6.v index 1245c4d7b..e10f104a8 100644 --- a/basil/firmware/modules/utils/ODDR_s6.v +++ b/basil/firmware/modules/utils/ODDR_s6.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef ODDR_S6_SIM +`define ODDR_S6_SIM + `timescale 1ps/1ps `default_nettype none @@ -26,3 +29,5 @@ ODDR2 ODDR2_inst ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v b/basil/firmware/modules/utils/RAMB16_S1_S2.v similarity index 95% rename from basil/firmware/modules/utils/RAMB16_S1_S2_sim.v rename to basil/firmware/modules/utils/RAMB16_S1_S2.v index 508dd1640..0b9a46ad7 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S2.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef RAMB16_S1_S2_SIM +`define RAMB16_S1_S2_SIM + `timescale 1ps/1ps `default_nettype none @@ -29,6 +32,8 @@ input wire SSRB; input wire DIPB; output wire DOPB; +assign DOPB = 1'b0; + parameter WIDTHA = 1; parameter SIZEA = 16384; parameter ADDRWIDTHA = 14; @@ -68,3 +73,5 @@ end endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v b/basil/firmware/modules/utils/RAMB16_S1_S9.v similarity index 95% rename from basil/firmware/modules/utils/RAMB16_S1_S9_sim.v rename to basil/firmware/modules/utils/RAMB16_S1_S9.v index fc782ce52..cfc679695 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S9.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef RAMB16_S1_S9_SIM +`define RAMB16_S1_S9_SIM + `timescale 1ps/1ps `default_nettype none @@ -29,6 +32,8 @@ input wire SSRB; input wire DIPB; output wire DOPB; +assign DOPB = 1'b0; + parameter WIDTHA = 1; parameter SIZEA = 16384; parameter ADDRWIDTHA = 14; @@ -71,3 +76,5 @@ end endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/utils/README.rst b/basil/firmware/modules/utils/README.rst index 2f463fc93..4c06a61d9 100644 --- a/basil/firmware/modules/utils/README.rst +++ b/basil/firmware/modules/utils/README.rst @@ -18,12 +18,13 @@ Various Verilog modules used by basil. - flag_domain_crossing - flag_domain_crossing_ce - generic_fifo +- IDDR - IDDR_s3 -- IDDR_sim +- ODDR - ODDR_s3 - pulse_gen_rising -- RAMB16_S1_S2_sim -- RAMB16_S1_S9_sim +- RAMB16_S1_S2 +- RAMB16_S1_S9 - rbcp_to_bus - reset_gen - simple_arbiter diff --git a/basil/firmware/modules/utils/bus_to_ip.v b/basil/firmware/modules/utils/bus_to_ip.v index 7e284e7b8..ab1908b98 100644 --- a/basil/firmware/modules/utils/bus_to_ip.v +++ b/basil/firmware/modules/utils/bus_to_ip.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BUS_TO_IP +`define BUS_TO_IP + `timescale 1ps/1ps `default_nettype none @@ -42,3 +45,5 @@ assign IP_DATA_IN = BUS_DATA; assign BUS_DATA = (CS && BUS_WR) ? {DBUSWIDTH{1'bz}} : (CS ? IP_DATA_OUT : {DBUSWIDTH{1'bz}}); endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_pulse_sync.v b/basil/firmware/modules/utils/cdc_pulse_sync.v index c1b3dfa87..74c5baed4 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CDC_PULSE_SYNC +`define CDC_PULSE_SYNC + `timescale 1ps/1ps `default_nettype none + // Closed loop solution module cdc_pulse_sync ( @@ -45,6 +49,7 @@ always @(posedge clk_out) begin out_sync_ff_3 <= out_sync_ff_2; end +// Fire output for one clock period, when transition is detected assign pulse_out = !out_sync_ff_3 && out_sync_ff_2; (* ASYNC_REG = "TRUE" *) reg aq_sync_ff_1; @@ -57,3 +62,5 @@ end assign aq_sync = aq_sync_ff_2; endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v b/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v index e31130241..900edb781 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CDC_PULSE_SYNC_CNT +`define CDC_PULSE_SYNC_CNT + `timescale 1ps/1ps `default_nettype none @@ -35,3 +38,5 @@ end assign pulse_out = !out_sync_ff_3 && out_sync_ff_2; endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_reset_sync.v b/basil/firmware/modules/utils/cdc_reset_sync.v index c6de1b81d..72e174364 100644 --- a/basil/firmware/modules/utils/cdc_reset_sync.v +++ b/basil/firmware/modules/utils/cdc_reset_sync.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CDC_RESET_SYNC +`define CDC_RESET_SYNC + `timescale 1ps/1ps `default_nettype none + // Closed loop solution module cdc_reset_sync ( @@ -52,3 +56,5 @@ end assign aq_sync = aq_sync_ff_2; endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_syncfifo.v b/basil/firmware/modules/utils/cdc_syncfifo.v index 89b0d4b19..bfc92fdef 100644 --- a/basil/firmware/modules/utils/cdc_syncfifo.v +++ b/basil/firmware/modules/utils/cdc_syncfifo.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CDC_SYNCFIFO +`define CDC_SYNCFIFO + `timescale 1ps/1ps `default_nettype none @@ -116,8 +119,6 @@ always @(posedge wclk) endmodule - - module rptr_empty #( parameter ADDRSIZE = 2 ) ( @@ -221,3 +222,5 @@ always @(posedge rclk) else {rq2_wptr,cdc_sync_rq1_wptr} <= {cdc_sync_rq1_wptr,wptr}; endmodule + +`endif diff --git a/basil/firmware/modules/utils/clock_divider.v b/basil/firmware/modules/utils/clock_divider.v index 1a1cf1b9b..6c6328ae4 100644 --- a/basil/firmware/modules/utils/clock_divider.v +++ b/basil/firmware/modules/utils/clock_divider.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef CLOCK_DIVIDER +`define CLOCK_DIVIDER + `timescale 1ps/1ps `default_nettype none + // clock divider generating clock and clock enable module clock_divider #( @@ -96,3 +100,5 @@ always @(posedge CLK or posedge RESET) end endmodule + +`endif diff --git a/basil/firmware/modules/utils/clock_multiplier.v b/basil/firmware/modules/utils/clock_multiplier.v index 209a2e903..a16fb5c6d 100644 --- a/basil/firmware/modules/utils/clock_multiplier.v +++ b/basil/firmware/modules/utils/clock_multiplier.v @@ -1,3 +1,6 @@ +`ifndef CLOCK_MULTIPLIER +`define CLOCK_MULTIPLIER + `timescale 1ps / 1ps module clock_multiplier #( @@ -28,3 +31,5 @@ initial begin end endmodule + +`endif diff --git a/basil/firmware/modules/utils/ddr_des.v b/basil/firmware/modules/utils/ddr_des.v index a2a96d42f..1e909fc46 100644 --- a/basil/firmware/modules/utils/ddr_des.v +++ b/basil/firmware/modules/utils/ddr_des.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef DDR_DES +`define DDR_DES + `timescale 1ps/1ps `default_nettype none @@ -57,3 +60,5 @@ always @(posedge WCLK) OUT <= DATA_IN_SR; endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_32_to_8.v b/basil/firmware/modules/utils/fifo_32_to_8.v index 3b3ad49f7..bd50a50d6 100644 --- a/basil/firmware/modules/utils/fifo_32_to_8.v +++ b/basil/firmware/modules/utils/fifo_32_to_8.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FIFO_32_TO_8 +`define FIFO_32_TO_8 + `timescale 1ps/1ps `default_nettype none @@ -62,3 +65,5 @@ assign FIFO_DATA_OUT_BYTE[3] = DATA_BUF[31:24]; assign DATA_OUT = FIFO_DATA_OUT_BYTE[byte_cnt]; endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_64_to_16.v b/basil/firmware/modules/utils/fifo_64_to_16.v index e70ffcbc8..2aee21855 100644 --- a/basil/firmware/modules/utils/fifo_64_to_16.v +++ b/basil/firmware/modules/utils/fifo_64_to_16.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FIFO_64_TO_16 +`define FIFO_64_TO_16 + `timescale 1ps/1ps `default_nettype none @@ -62,3 +65,5 @@ assign FIFO_DATA_OUT_BYTE[3] = DATA_BUF[63:48]; assign DATA_OUT = FIFO_DATA_OUT_BYTE[byte_cnt]; endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_8_to_32.v b/basil/firmware/modules/utils/fifo_8_to_32.v index 4821a8d9c..a87e70f3b 100644 --- a/basil/firmware/modules/utils/fifo_8_to_32.v +++ b/basil/firmware/modules/utils/fifo_8_to_32.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FIFO_8_TO_32 +`define FIFO_8_TO_32 + `timescale 1ps/1ps `default_nettype none @@ -110,3 +113,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_8_to_64.v b/basil/firmware/modules/utils/fifo_8_to_64.v index 0069872b1..4a65a8553 100644 --- a/basil/firmware/modules/utils/fifo_8_to_64.v +++ b/basil/firmware/modules/utils/fifo_8_to_64.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FIFO_8_TO_64 +`define FIFO_8_TO_64 + `timescale 1ps/1ps `default_nettype none @@ -118,3 +121,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/flag_domain_crossing.v b/basil/firmware/modules/utils/flag_domain_crossing.v index da526a3ff..a3cf71c77 100644 --- a/basil/firmware/modules/utils/flag_domain_crossing.v +++ b/basil/firmware/modules/utils/flag_domain_crossing.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FLAG_DOMAIN_CROSSING +`define FLAG_DOMAIN_CROSSING + `timescale 1ps/1ps `default_nettype none + // synchronize flag (signal lasts just one clock cycle) to new clock domain (CLK_B) module flag_domain_crossing( @@ -49,3 +53,5 @@ end assign FLAG_OUT_CLK_B = (flag_out_d_ff_3 ^ flag_out_d_ff_2); // XOR endmodule + +`endif diff --git a/basil/firmware/modules/utils/fx2_to_bus.v b/basil/firmware/modules/utils/fx2_to_bus.v index 89a87268c..576f670fe 100644 --- a/basil/firmware/modules/utils/fx2_to_bus.v +++ b/basil/firmware/modules/utils/fx2_to_bus.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef FX2_TO_BUS +`define FX2_TO_BUS + `timescale 1ps/1ps `default_nettype none @@ -39,3 +42,5 @@ assign BUS_RD = ~RD_B & RD_B_FF; assign BUS_WR = ~WR_B; endmodule + +`endif diff --git a/basil/firmware/modules/utils/generic_fifo.v b/basil/firmware/modules/utils/generic_fifo.v index 181e984f3..9bbfdfacc 100644 --- a/basil/firmware/modules/utils/generic_fifo.v +++ b/basil/firmware/modules/utils/generic_fifo.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef GENERIC_FIFO +`define GENERIC_FIFO + `timescale 1ps/1ps `default_nettype none @@ -135,3 +138,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/pulse_gen_rising.v b/basil/firmware/modules/utils/pulse_gen_rising.v index 659d2f122..a43103560 100644 --- a/basil/firmware/modules/utils/pulse_gen_rising.v +++ b/basil/firmware/modules/utils/pulse_gen_rising.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef PULSE_GEN_RISING +`define PULSE_GEN_RISING + `timescale 1ps/1ps `default_nettype none @@ -21,3 +24,5 @@ always @(posedge clk_in) assign out = !ff && in; endmodule + +`endif diff --git a/basil/firmware/modules/utils/ramb_8_to_n.v b/basil/firmware/modules/utils/ramb_8_to_n.v index d86d69082..61e55ea81 100644 --- a/basil/firmware/modules/utils/ramb_8_to_n.v +++ b/basil/firmware/modules/utils/ramb_8_to_n.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef RAMB_8_TO_N +`define RAMB_8_TO_N + module ramb_8_to_n (clkA, clkB, weA, @@ -127,3 +131,5 @@ endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/utils/rbcp_to_bus.v b/basil/firmware/modules/utils/rbcp_to_bus.v index 81e8acb8c..c2587ae5b 100644 --- a/basil/firmware/modules/utils/rbcp_to_bus.v +++ b/basil/firmware/modules/utils/rbcp_to_bus.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef RBCP_TO_BUS +`define RBCP_TO_BUS + `timescale 1ps/1ps `default_nettype none @@ -65,3 +68,5 @@ chipscope_ila ichipscope_ila */ endmodule + +`endif diff --git a/basil/firmware/modules/utils/reset_gen.v b/basil/firmware/modules/utils/reset_gen.v index 6e829733b..34faa4531 100644 --- a/basil/firmware/modules/utils/reset_gen.v +++ b/basil/firmware/modules/utils/reset_gen.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef RESET_GEN +`define RESET_GEN + `timescale 1ps/1ps `default_nettype none @@ -29,3 +32,5 @@ always @(posedge CLK) assign RST = (rst_cnt != 0 ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/rgmii_io.v b/basil/firmware/modules/utils/rgmii_io.v index 0ba6f03dd..485c4ee3f 100644 --- a/basil/firmware/modules/utils/rgmii_io.v +++ b/basil/firmware/modules/utils/rgmii_io.v @@ -9,6 +9,9 @@ /////////////////////////////////////////////////////////////////////////////// +`ifndef RGMII_IO +`define RGMII_IO + module rgmii_io ( //----------------------------------------------------------------------- //-- Pad side signals @@ -353,3 +356,5 @@ assign gmii_col_int = (gmii_tx_en_int | gmii_tx_er_int) & (gmii_rx_dv_reg | gmii assign gmii_crs_int = (gmii_tx_en_int | gmii_tx_er_int) | (gmii_rx_dv_reg | gmii_rx_er_reg); endmodule // rgmii_io + +`endif diff --git a/basil/firmware/modules/utils/sbus_to_ip.v b/basil/firmware/modules/utils/sbus_to_ip.v index 03b87980a..507a8fe7b 100644 --- a/basil/firmware/modules/utils/sbus_to_ip.v +++ b/basil/firmware/modules/utils/sbus_to_ip.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef SBUS_TO_IP +`define SBUS_TO_IP + module sbus_to_ip #( parameter BASEADDR = 0, @@ -47,3 +51,5 @@ end assign BUS_DATA_OUT = (CS_PREV ? IP_DATA_OUT : {DBUSWIDTH{1'b0}}); endmodule + +`endif diff --git a/basil/firmware/modules/utils/simple_arbiter.v b/basil/firmware/modules/utils/simple_arbiter.v index e35818b01..1b11f74a1 100644 --- a/basil/firmware/modules/utils/simple_arbiter.v +++ b/basil/firmware/modules/utils/simple_arbiter.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef ARBITER +`define ARBITER + `timescale 1ps/1ps `default_nettype none @@ -29,3 +32,5 @@ wire [2*WIDTH-1:0] double_grant = double_req & ~(double_req-base); assign grant = double_grant[WIDTH-1:0] | double_grant[2*WIDTH-1:WIDTH]; endmodule + +`endif diff --git a/basil/firmware/modules/utils/tcp_to_bus.v b/basil/firmware/modules/utils/tcp_to_bus.v index 691deb0d6..70cdb4f5d 100644 --- a/basil/firmware/modules/utils/tcp_to_bus.v +++ b/basil/firmware/modules/utils/tcp_to_bus.v @@ -5,6 +5,9 @@ * ------------------------------------------------------------ */ +`ifndef TCP_TO_BUS +`define TCP_TO_BUS + `timescale 1ps / 1ps `default_nettype none @@ -153,3 +156,5 @@ assign BUS_ADD = (TCP_TO_BUS_WR) ? TCP_TO_BUS_ADD : RBCP_ADDR; assign BUS_DATA = (BUS_WR) ? ((TCP_TO_BUS_WR) ? TCP_RX_DATA : RBCP_WD) : 8'bz; endmodule + +`endif diff --git a/docs/_static/silab.ico b/docs/_static/silab.ico new file mode 100644 index 000000000..ed3ea69a5 Binary files /dev/null and b/docs/_static/silab.ico differ diff --git a/docs/conf.py b/docs/conf.py index ab096052a..a4dde085c 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -116,6 +116,7 @@ # a list of builtin themes. html_theme = "sphinx_book_theme" html_logo = "_static/logo_silab.png" +html_favicon = "_static/silab.ico" html_theme_options = { "repository_url": "https://github.com/SiLab-Bonn/basil", "use_repository_button": True, diff --git a/examples/mio_pixel/tests/test_Sim_mio_pixel.py b/examples/mio_pixel/tests/test_Sim_mio_pixel.py index edb898607..ead5db39a 100644 --- a/examples/mio_pixel/tests/test_Sim_mio_pixel.py +++ b/examples/mio_pixel/tests/test_Sim_mio_pixel.py @@ -32,15 +32,15 @@ def setUp(self): os.path.join(fw_path, "utils/reset_gen.v"), os.path.join(fw_path, "utils/bus_to_ip.v"), os.path.join(fw_path, "rrp_arbiter/rrp_arbiter.v"), - os.path.join(fw_path, "utils/ODDR_sim.v"), + os.path.join(fw_path, "utils/ODDR.v"), os.path.join(fw_path, "utils/generic_fifo.v"), os.path.join(fw_path, "utils/cdc_pulse_sync.v"), os.path.join(fw_path, "utils/fx2_to_bus.v"), - os.path.join(fw_path, "utils/BUFG_sim.v"), + os.path.join(fw_path, "utils/BUFG.v"), os.path.join(fw_path, "utils/cdc_syncfifo.v"), os.path.join(fw_path, "utils/ddr_des.v"), - os.path.join(fw_path, "utils/IDDR_sim.v"), - os.path.join(fw_path, "utils/DCM_sim.v"), + os.path.join(fw_path, "utils/IDDR.v"), + os.path.join(fw_path, "utils/DCM.v"), os.path.join(fw_path, "utils/clock_divider.v"), os.path.join(fw_path, "utils/clock_multiplier.v"), os.path.join(fw_path, "utils/flag_domain_crossing.v"), diff --git a/examples/mio_sram_test/tests/test_Sim.py b/examples/mio_sram_test/tests/test_Sim.py index 4faf303da..b1a184b38 100644 --- a/examples/mio_sram_test/tests/test_Sim.py +++ b/examples/mio_sram_test/tests/test_Sim.py @@ -28,7 +28,7 @@ def setUp(self): os.path.join(fw_path, "utils/reset_gen.v"), os.path.join(fw_path, "utils/bus_to_ip.v"), os.path.join(fw_path, "rrp_arbiter/rrp_arbiter.v"), - os.path.join(fw_path, "utils/ODDR_sim.v"), + os.path.join(fw_path, "utils/ODDR.v"), os.path.join(fw_path, "utils/generic_fifo.v"), os.path.join(fw_path, "utils/cdc_pulse_sync.v"), os.path.join(fw_path, "utils/3_stage_synchronizer.v"), diff --git a/pyproject.toml b/pyproject.toml index a95631034..0feb3236b 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -7,8 +7,8 @@ name = "basil_daq" dynamic = ["version"] license = { "text" = "BSD 3-Clause ('BSD New' or 'BSD Simplified') License" } description = "Basil is a modular data acquisition system and system testing framework in Python.\nIt also provides generic FPGA firmware modules for different hardware platforms and drivers for wide range of lab appliances." -readme = {file = "README.rst", content-type = "text/x-rst"} -requires-python = ">=3.10" +readme = "README.md" +requires-python = ">=3.10,<3.14" authors = [ {name = "Tomasz Hemperek", email="hemperek@uni-bonn.de"}, {name = "Jens Janssen", email="janssen@physik.uni-bonn.de"}, @@ -27,6 +27,10 @@ dependencies = [ "GitPython", "six", "ruamel.yaml", + "cocotb>=2.0.1", + "cocotb-bus>=0.3.0", + "pytest>=9.0.3", + "cocotb-test>=0.2.6", ] [project.urls] @@ -35,6 +39,17 @@ dependencies = [ [project.optional-dependencies] hw = ["pyserial", "PyVISA"] +test = [ + "coverage", + "coveralls", + "cocotb>=2.0.1", + "cocotb-bus>=0.3.0", + "cocotb-test>=0.2.6", + "pytest>=9.0.3", + "pytest-cov", + "PyVISA", + "pyvisa-sim", +] [tool.setuptools] include-package-data = true @@ -51,3 +66,6 @@ profile = "black" [tool.ruff] # Set the maximum line length to 180. line-length = 120 + +[tool.uv.sources] +cocotb-test = { git = "https://github.com/themperek/cocotb-test.git", rev = "4e6b7db" } diff --git a/tests/test_SimAdcRx.v b/tests/test_SimAdcRx.v index b7adc288d..c23678a64 100644 --- a/tests/test_SimAdcRx.v +++ b/tests/test_SimAdcRx.v @@ -7,35 +7,12 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "utils/cdc_pulse_sync.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - `include "spi/spi.v" -`include "spi/spi_core.v" -`include "spi/blk_mem_gen_8_to_1_2k.v" -`include "utils/RAMB16_S1_S9_sim.v" - -`include "utils/CG_MOD_pos.v" - -`include "gpac_adc_rx/gpac_adc_rx_core.v" `include "gpac_adc_rx/gpac_adc_rx.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" - -`include "utils/generic_fifo.v" -`include "utils/cdc_syncfifo.v" -`include "utils/pulse_gen_rising.v" `include "utils/clock_divider.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/cdc_reset_sync.v" module tb ( input wire BUS_CLK, diff --git a/tests/test_SimCmdSeq.v b/tests/test_SimCmdSeq.v index f8b41eebe..ecd70b4d6 100644 --- a/tests/test_SimCmdSeq.v +++ b/tests/test_SimCmdSeq.v @@ -7,23 +7,10 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - `include "cmd_seq/cmd_seq.v" -`include "cmd_seq/cmd_seq_core.v" - `include "seq_rec/seq_rec.v" -`include "seq_rec/seq_rec_core.v" -`include "utils/ramb_8_to_n.v" - -// `include "utils/glbl.v" -`include "utils/ODDR_sim.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/flag_domain_crossing.v" +`include "utils/ODDR.v" module tb ( input wire BUS_CLK, @@ -106,7 +93,7 @@ end reg CMD_DATA_FF; always @(posedge BUS_CLK) begin - CMD_DATA_FF <= CMD_DATA; // delay data, SEQ_EXT_START signal hast to come first by 1 clock cycle + CMD_DATA_FF <= CMD_DATA; // delay data, SEQ_EXT_START signal has to come first by 1 clock cycle end reg CMD_READY_FF, CMD_READY_FF2, CMD_READY_FF3; diff --git a/tests/test_SimFifo8to32.v b/tests/test_SimFifo8to32.v index 15d4c508a..7b86f6b3a 100644 --- a/tests/test_SimFifo8to32.v +++ b/tests/test_SimFifo8to32.v @@ -14,14 +14,9 @@ `endif `ifndef BASIL_SBUS -`include "utils/bus_to_ip.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/fifo_8_to_32.v" -`include "utils/generic_fifo.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" +`include "utils/fifo_8_to_32.v" +`include "utils/cdc_syncfifo.v" `else $fatal("Sbus modules not implemented yet"); `endif diff --git a/tests/test_SimGpio.v b/tests/test_SimGpio.v index 588d206e0..be780baa0 100644 --- a/tests/test_SimGpio.v +++ b/tests/test_SimGpio.v @@ -13,9 +13,7 @@ `define SPLIT_BUS `endif -`include "gpio/gpio_core.v" `ifndef BASIL_SBUS - `include "utils/bus_to_ip.v" `include "gpio/gpio.v" `else `include "utils/sbus_to_ip.v" diff --git a/tests/test_SimI2c.v b/tests/test_SimI2c.v index d81722f2f..10360d4d5 100644 --- a/tests/test_SimI2c.v +++ b/tests/test_SimI2c.v @@ -8,17 +8,10 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "i2c/i2c.v" -`include "i2c/i2c_core.v" - -`include "utils/cdc_pulse_sync.v" `include "utils/clock_divider.v" - - -`include "utils/ODDR_sim.v" -`include "utils/IDDR_sim.v" +`include "utils/ODDR.v" +`include "utils/IDDR.v" module i2c_slave_model ( diff --git a/tests/test_SimJtagGpio.py b/tests/test_SimJtagGpio.py index 3b54f2ae7..38e97d593 100644 --- a/tests/test_SimJtagGpio.py +++ b/tests/test_SimJtagGpio.py @@ -159,10 +159,11 @@ class TestSimJtagGpio(unittest.TestCase): def setUp(self): + test_dir = os.path.dirname(__file__) cocotb_compile_and_run( [ - os.path.join(os.path.dirname(__file__), "jtag_tap.v"), - os.path.join(os.path.dirname(__file__), "test_SimJtagGpio.v"), + os.path.join(test_dir, "../basil/firmware/modules/includes/jtag_tap.v"), + os.path.join(test_dir, "test_SimJtagGpio.v"), ] ) diff --git a/tests/test_SimJtagGpio.v b/tests/test_SimJtagGpio.v index a344aa70a..1d1fe1c1a 100644 --- a/tests/test_SimJtagGpio.v +++ b/tests/test_SimJtagGpio.v @@ -7,8 +7,6 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "gpio/gpio_core.v" `include "gpio/gpio.v" module tb ( diff --git a/tests/test_SimJtagMaster.py b/tests/test_SimJtagMaster.py index ae7773e42..1f67d77e5 100644 --- a/tests/test_SimJtagMaster.py +++ b/tests/test_SimJtagMaster.py @@ -164,10 +164,11 @@ class TestSimJtagMaster(unittest.TestCase): def setUp(self): + test_dir = os.path.dirname(__file__) cocotb_compile_and_run( [ - os.path.join(os.path.dirname(__file__), "jtag_tap.v"), - os.path.join(os.path.dirname(__file__), "test_SimJtagMaster.v"), + os.path.join(test_dir, "../basil/firmware/modules/includes/jtag_tap.v"), + os.path.join(test_dir, "test_SimJtagMaster.v"), ] ) diff --git a/tests/test_SimJtagMaster.v b/tests/test_SimJtagMaster.v index 4283560f3..f668d9688 100644 --- a/tests/test_SimJtagMaster.v +++ b/tests/test_SimJtagMaster.v @@ -7,28 +7,11 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "gpio/gpio_core.v" `include "gpio/gpio.v" - -`include "spi/blk_mem_gen_8_to_1_2k.v" -`include "utils/ramb_8_to_n.v" `include "jtag_master/jtag_master.v" -`include "jtag_master/jtag_master_core.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - -`include "utils/cdc_pulse_sync.v" -`include "utils/cdc_reset_sync.v" -`include "utils/CG_MOD_pos.v" -`include "utils/clock_divider.v" - -`include "utils/RAMB16_S1_S9_sim.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" -`include "utils/generic_fifo.v" +`include "utils/clock_divider.v" module tb ( input wire BUS_CLK, @@ -154,8 +137,8 @@ gpio #( .IO(debug_reg1) ); -output reg wr_fifo_FF; -output reg fifo_strobe; +reg wr_fifo_FF; +wire fifo_strobe; always @(posedge BUS_CLK) begin wr_fifo_FF <= wr_fifo; diff --git a/tests/test_SimM26.v b/tests/test_SimM26.v index e974321a1..c2f9ee76c 100644 --- a/tests/test_SimM26.v +++ b/tests/test_SimM26.v @@ -7,25 +7,10 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - `include "m26_rx/m26_rx.v" -`include "m26_rx/m26_rx_core.v" -`include "m26_rx/m26_rx_ch.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/generic_fifo.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/flag_domain_crossing.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" -`include "utils/IDDR_sim.v" +`include "utils/IDDR.v" module tb ( input wire BUS_CLK, diff --git a/tests/test_SimSeq.v b/tests/test_SimSeq.v index e98c689f6..ad7cf2a19 100644 --- a/tests/test_SimSeq.v +++ b/tests/test_SimSeq.v @@ -7,21 +7,9 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" - `include "seq_rec/seq_rec.v" -`include "seq_rec/seq_rec_core.v" - -`include "utils/3_stage_synchronizer.v" -`include "utils/flag_domain_crossing.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/ramb_8_to_n.v" module tb ( diff --git a/tests/test_SimSpi.v b/tests/test_SimSpi.v index a21bbeff6..b14aa1308 100644 --- a/tests/test_SimSpi.v +++ b/tests/test_SimSpi.v @@ -14,30 +14,12 @@ `endif `ifndef BASIL_SBUS - `include "utils/bus_to_ip.v" - `include "gpio/gpio_core.v" `include "gpio/gpio.v" - `include "spi/spi.v" - `include "spi/spi_core.v" - `include "spi/blk_mem_gen_8_to_1_2k.v" - `include "pulse_gen/pulse_gen.v" - `include "pulse_gen/pulse_gen_core.v" - - `include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" - `include "fast_spi_rx/fast_spi_rx.v" - `include "fast_spi_rx/fast_spi_rx_core.v" - - `include "utils/cdc_syncfifo.v" - `include "utils/generic_fifo.v" - `include "utils/cdc_pulse_sync.v" - `include "utils/CG_MOD_pos.v" `include "utils/clock_divider.v" - `include "utils/3_stage_synchronizer.v" - `include "utils/RAMB16_S1_S9_sim.v" `else $fatal("Sbus modules not implemented yet"); `endif diff --git a/tests/test_SimTdc.v b/tests/test_SimTdc.v index 821ba43a0..3890de4a1 100644 --- a/tests/test_SimTdc.v +++ b/tests/test_SimTdc.v @@ -8,28 +8,13 @@ `timescale 1ps / 1ps `include "utils/clock_multiplier.v" -`include "utils/DCM_sim.v" -`include "utils/IDDR_sim.v" +`include "utils/DCM.v" +`include "utils/IDDR.v" `include "utils/ddr_des.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - -`include "tdc_s3/tdc_s3_core.v" `include "tdc_s3/tdc_s3.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" -`include "utils/bus_to_ip.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/flag_domain_crossing.v" -`include "utils/generic_fifo.v" -`include "utils/3_stage_synchronizer.v" - module tb ( input wire BUS_CLK, diff --git a/tests/test_SimTdl_Tdc.v b/tests/test_SimTdl_Tdc.v index cd80d49d1..2823731f6 100644 --- a/tests/test_SimTdl_Tdc.v +++ b/tests/test_SimTdl_Tdc.v @@ -9,17 +9,11 @@ `timescale 1ps / 1ps `include "utils/clock_multiplier.v" +`include "utils/DCM.v" `include "utils/clock_divider.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - -`include "tdl_tdc/tdc.v" - -`include "bram_fifo/bram_fifo_core.v" +`include "tdl_tdc/tdl_tdc.v" `include "bram_fifo/bram_fifo.v" - `include "utils/bus_to_ip.v" @@ -61,7 +55,7 @@ assign TDC_IN[2] = SEQ_OUT[1]; assign TDC_ARM = SEQ_OUT[2]; assign TDC_EXT_EN = SEQ_OUT[3]; -wire CLK_160, CLK_480, CLK_160_TO_DCM, +wire CLK_160, CLK_480, CLK_160_TO_DCM; DCM #( .CLKFX_MULTIPLY(20), @@ -106,7 +100,7 @@ wire [2:0] TDC_FIFO_EMPTY; wire [31:0] TDC_FIFO_DATA [2:0]; wire [2:0] TDC_FIFO_READ; // First TDC module: creates fast sampled trigger signal to use it for other TDC modules. -tdc #( +tdl_tdc #( .BASEADDR(TDC_BASEADDR), .HIGHADDR(TDC_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), @@ -119,9 +113,9 @@ tdc #( .bus_wr(BUS_WR), .bus_rd(BUS_RD), - .CLK480(CLK480), - .CLK160(CLK160), - .CALIB_CLK(CLK125RX), + .CLK480(CLK_480), + .CLK160(CLK_160), + .CALIB_CLK(BUS_CLK), .tdc_in(TDC_IN[0]), .trig_in(TDC_TRIGGER_IN), @@ -137,7 +131,7 @@ tdc #( genvar i; generate for (i = 1; i < 3; i = i + 1) begin: tdc_gen - tdc #( + tdl_tdc #( .BASEADDR(TDC_BASEADDR + 32'h0100*i), .HIGHADDR(TDC_HIGHADDR + 21'h0100*i), .ABUSWIDTH(ABUSWIDTH), @@ -150,9 +144,9 @@ generate .bus_wr(BUS_WR), .bus_rd(BUS_RD), - .CLK480(CLK480), - .CLK160(CLK160), - .CALIB_CLK(CLK125RX), + .CLK480(CLK_480), + .CLK160(CLK_160), + .CALIB_CLK(BUS_CLK), .tdc_in(TDC_IN[i]), .trig_in(TDC_TRIGGER_IN), diff --git a/tests/test_SimTimestamp.v b/tests/test_SimTimestamp.v index 6ecbccd6b..4b5e87cd9 100644 --- a/tests/test_SimTimestamp.v +++ b/tests/test_SimTimestamp.v @@ -8,27 +8,12 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "gpio/gpio_core.v" `include "gpio/gpio.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" -`include "utils/clock_multiplier.v" - -`include "bram_fifo/bram_fifo_core.v" -`include "bram_fifo/bram_fifo.v" - `include "timestamp/timestamp.v" -`include "timestamp/timestamp_core.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/generic_fifo.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/CG_MOD_pos.v" +`include "bram_fifo/bram_fifo.v" `include "utils/clock_divider.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/RAMB16_S1_S9_sim.v" +`include "utils/clock_multiplier.v" module tb ( diff --git a/tests/test_SimTlu.v b/tests/test_SimTlu.v index 27d73cac9..3a30df3a7 100644 --- a/tests/test_SimTlu.v +++ b/tests/test_SimTlu.v @@ -7,24 +7,11 @@ `timescale 1ps / 1ps -`include "gpio/gpio_core.v" `include "gpio/gpio.v" - -`include "tlu/tlu_controller_core.v" -`include "tlu/tlu_controller_fsm.v" `include "tlu/tlu_controller.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" - -`include "utils/bus_to_ip.v" - `include "utils/cdc_syncfifo.v" `include "utils/flag_domain_crossing.v" -`include "utils/generic_fifo.v" -`include "utils/3_stage_synchronizer.v" - -`include "utils/cdc_pulse_sync.v" module tlu_model ( input wire SYS_CLK, SYS_RST, TLU_CLOCK, TLU_BUSY, ENABLE,