From 94da26cec656074d67d7250a422d3ba186d9afdd Mon Sep 17 00:00:00 2001 From: kcaisley Date: Thu, 2 Apr 2026 17:35:48 +0200 Subject: [PATCH 01/43] misc: update readme, add icon --- README.md | 64 +++++++++++++++++++++++++++++++++ README.rst | 78 ----------------------------------------- docs/_static/silab.ico | Bin 0 -> 1078 bytes docs/conf.py | 1 + pyproject.toml | 2 +- 5 files changed, 66 insertions(+), 79 deletions(-) create mode 100644 README.md delete mode 100644 README.rst create mode 100644 docs/_static/silab.ico diff --git a/README.md b/README.md new file mode 100644 index 000000000..2e3b50c7d --- /dev/null +++ b/README.md @@ -0,0 +1,64 @@ +# Basil + +[![Build status](https://github.com/SiLab-Bonn/basil/workflows/Regression%20Tests/badge.svg)](https://github.com/silab-bonn/basil/actions?query=workflow%3A%22Regression+Tests%22) +[![Documentation](https://readthedocs.org/projects/basil/badge/?version=latest)](http://basil.rtfd.org) + +Basil is a modular data acquisition (DAQ) framework developed by [SiLab](https://silab-bonn.github.io/) for the characterization of [monolithic](https://en.wikipedia.org/wiki/Monolithic_active_pixel_sensor) and [hybrid](https://en.wikipedia.org/wiki/Hybrid_pixel_detector) pixel detectors. It comprises a library of HDL modules (written in Verilog) for custom FPGA readout boards, paired with a collection of Python code that control the hardware over USB, Ethernet, or serial interfaces from a host PC. Basil also includes Python drivers for common lab instruments such as power supplies, oscilloscopes, and other bench equipment. + +## Features + +**Firmware:** +- Very simple single master bus definition +- Multiple basic modules (SPI, SEQ, GPIO, I2C, JTAG) +- Multiple interfaces (UART, USB2, USB3, Ethernet) + +**Software:** +- Layer structure following hardware +- Generation based on YAML file +- Register abstract layer (RAL) +- Simulator interface allows software test against simulated RTL (thanks to [cocotb](https://github.com/cocotb/cocotb)) + +## Installation + +Install via PyPI: + +```bash +pip install basil-daq +``` + +> **Note:** The PyPI package may be outdated. Installing from source (below) is recommended to get the latest version. + +Or install from source: + +```bash +git clone https://github.com/SiLab-Bonn/basil.git +cd basil +pip install -e . +``` + +## Support + +Please use GitHub's [issue tracker](https://github.com/SiLab-Bonn/basil/issues) for bug reports/feature requests/questions. + +*For CERN users*: Feel free to subscribe to the [basil mailing list](https://e-groups.cern.ch/e-groups/EgroupsSubscription.do?egroupName=basil-devel). + +## Documentation + +Documentation can be found at: https://basil.rtfd.org + +## Example Projects + +- [TJ-Monopix2](https://github.com/SiLab-Bonn/tj-monopix2-daq) - DAQ for TJ-Monopix2 depleted monolithic pixel sensor +- [BDAQ53](https://gitlab.cern.ch/silab/bdaq53) - Readout system for ATLAS ITkPix (RD53) chips +- [LF-Monopix2](https://github.com/SiLab-Bonn/lf-monopix2-daq) - DAQ for LF-Monopix2 depleted monolithic pixel sensor +- [FRIDA](https://github.com/kcaisley/frida) - DAQ for FRIDA, an ADC test array for frame-based imaging detectors + +## License + +If not stated otherwise: + +**Host Software:** +The host software is distributed under the BSD 3-Clause ("BSD New" or "BSD Simplified") License. + +**FPGA Firmware:** +The FPGA code is distributed under the GNU Lesser General Public License, version 3.0 (LGPLv3). diff --git a/README.rst b/README.rst deleted file mode 100644 index 35add651f..000000000 --- a/README.rst +++ /dev/null @@ -1,78 +0,0 @@ -=============================================== -Basil -=============================================== - -|gha-status| |rtd-status| - -.. |gha-status| image:: https://github.com/SiLab-Bonn/basil/workflows/Regression%20Tests/badge.svg - :target: https://github.com/silab-bonn/basil/actions?query=workflow%3A%22Regression+Tests%22 - :alt: Build status - -.. |rtd-status| image:: https://readthedocs.org/projects/basil/badge/?version=latest - :target: http://basil.rtfd.org - :alt: Documentation - -Basil is a modular data acquisition (DAQ) framework developed by `SiLab `_ for the characterization of `monolithic `_ and `hybrid `_ pixel detectors. It comprises a library of HDL modules (written in Verilog) for custom FPGA readout boards, paired with a collection of Python code that control the hardware over USB, Ethernet, or serial interfaces from a host PC. Basil also includes Python drivers for common lab instruments such as power supplies, oscilloscopes, and other bench equipment. - -Features -======== -Firmware: - - very simple single master bus definition - - multiple basic modules (SPI, SEQ, GPIO, I2C, JTAG) - - multiple interfaces (UART, USB2, USB3, Ethernet) -Software: - - layer structure following hardware - - generation based on yaml file - - register abstract layer (RAL) - - simulator interface allows software test against simulated RTL (thanks to `cocotb `_) - -Installation -============ - -Install via PyPI: - -.. code-block:: bash - - pip install basil-daq - -.. note:: - - The PyPI package may be outdated. Installing from source (below) is recommended to get the latest version. - -Or install from source: - -.. code-block:: bash - - git clone https://github.com/SiLab-Bonn/basil.git - cd basil - pip install -e . - -Support -======= - -Please use GitHub's `issue tracker `_ for bug reports/feature requests/questions. - -*For CERN users*: Feel free to subscribe to the `basil mailing list `_ - -Documentation -============= - -Documentation can be found under: https://basil.rtfd.org - -Example Projects -================ -- `TJ-Monopix2 `_ - DAQ for TJ-Monopix2 depleted monolithic pixel sensor -- `BDAQ53 `_ - Readout system for ATLAS ITkPix (RD53) chips -- `LF-Monopix2 `_ - DAQ for LF-Monopix2 depleted monolithic pixel sensor -- `FRIDA `_ - DAQ for FRIDA, an ADC test array for frame-based imaging detectors - -License -======= - -If not stated otherwise. - -Host Software: - The host software is distributed under the BSD 3-Clause ("BSD New" or "BSD Simplified") License. - -FPGA Firmware: - The FPGA code is distributed under the GNU Lesser General Public License, version 3.0 (LGPLv3). diff --git a/docs/_static/silab.ico b/docs/_static/silab.ico new file mode 100644 index 0000000000000000000000000000000000000000..ed3ea69a5c746832b137a0731f6342bcf2ae7ebd GIT binary patch literal 1078 zcmbVLF>V4e5S#-f8kD;qa8<-FLgDfxo)kaLg-c6(fifip1qEU=V`JwO5k<)!d+XWR zU9Zg^&|!gb9008Fu>fAV8is;*9q_UQcJz(ZJ+)(;#54A}c#>qiFNSX}sU9H&5|)23 z(~8PRF1`LPu1U^ar6zkhrUp|aoY5&UfOKSm{8qq};(?9O*oBzkf?8A4ewAV`Y*WK# z&K>MhaL${Od*I0ODn7^Tr^SoUa2C(tRzK$xU0m6pI0`Z??^m#!V&&PNnm>H&Z`N-) zPvv>u+4;pA`?GDZI&4Mj(;pLn1&vCt7g9D)jBBkPzncjNrt9;Z$RL;?fH#M Of0D{8_Ou4BTi_EsV!e<6 literal 0 HcmV?d00001 diff --git a/docs/conf.py b/docs/conf.py index ab096052a..a4dde085c 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -116,6 +116,7 @@ # a list of builtin themes. html_theme = "sphinx_book_theme" html_logo = "_static/logo_silab.png" +html_favicon = "_static/silab.ico" html_theme_options = { "repository_url": "https://github.com/SiLab-Bonn/basil", "use_repository_button": True, diff --git a/pyproject.toml b/pyproject.toml index a95631034..c9d164fbc 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -7,7 +7,7 @@ name = "basil_daq" dynamic = ["version"] license = { "text" = "BSD 3-Clause ('BSD New' or 'BSD Simplified') License" } description = "Basil is a modular data acquisition system and system testing framework in Python.\nIt also provides generic FPGA firmware modules for different hardware platforms and drivers for wide range of lab appliances." -readme = {file = "README.rst", content-type = "text/x-rst"} +readme = "README.md" requires-python = ">=3.10" authors = [ {name = "Tomasz Hemperek", email="hemperek@uni-bonn.de"}, From bf1aa85b3211857a7516573578a878de5aac107c Mon Sep 17 00:00:00 2001 From: kcaisley Date: Mon, 20 Apr 2026 20:58:58 +0200 Subject: [PATCH 02/43] fix(spi): replace legacy RAMB16_S1_S9 with inferred BRAM --- .../modules/spi/blk_mem_gen_8_to_1_2k.v | 80 ++++++++++++------- 1 file changed, 51 insertions(+), 29 deletions(-) diff --git a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v index a14a4eff9..89c7e5a2c 100644 --- a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v +++ b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v @@ -3,6 +3,23 @@ * Copyright (c) All rights reserved * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ + * + * Asymmetric true dual-port BRAM: 2048 x 8-bit (Port A) / 16384 x 1-bit (Port B). + * Total capacity: 16,384 bits — inferred as RAMB18 on Xilinx 7-series and later. + * + * Replaces the legacy RAMB16_S1_S9 primitive which is no longer supported in + * Vivado 2025.x and causes functional issues in synthesis. + * + * Port mapping (unchanged from original module interface): + * Port A: 8-bit wide, 2048 deep — ADDRA[10:0], DINA[7:0], DOUTA[7:0], WEA + * Port B: 1-bit wide, 16384 deep — ADDRB[13:0], DINB[0], DOUTB[0], WEB + * + * Bit addressing: ADDRB[13:3] selects the 8-bit word; ADDRB[2:0] selects the + * bit within that word (0 = LSB, 7 = MSB), matching the RAMB16_S1_S9 convention. + * + * Read behaviour: read-first (output reflects the value before any write in the + * same cycle), consistent with the RAMB16_S1_S9 default configuration. + * ------------------------------------------------------------ */ `timescale 1ps/1ps `default_nettype none @@ -11,34 +28,39 @@ module blk_mem_gen_8_to_1_2k ( CLKA, CLKB, DOUTA, DOUTB, WEA, WEB, ADDRA, ADDRB, DINA, DINB ); -input wire CLKA; -input wire CLKB; -output wire [7 : 0] DOUTA; -output wire [0 : 0] DOUTB; -input wire [0 : 0] WEA; -input wire [0 : 0] WEB; -input wire [10 : 0] ADDRA; -input wire [13 : 0] ADDRB; -input wire [7 : 0] DINA; -input wire [0 : 0] DINB; +input wire CLKA; +input wire CLKB; +output reg [7 : 0] DOUTA; +output reg [0 : 0] DOUTB; +input wire [0 : 0] WEA; +input wire [0 : 0] WEB; +input wire [10 : 0] ADDRA; +input wire [13 : 0] ADDRB; +input wire [7 : 0] DINA; +input wire [0 : 0] DINB; -RAMB16_S1_S9 dpram ( - .CLKA(CLKB), - .CLKB(CLKA), - .ENB(1'b1), - .WEA(WEB), - .WEB(WEA), - .ENA(1'b1), - .SSRA(1'b0), - .SSRB(1'b0), - .DIPB(1'b0), - .ADDRA(ADDRB), - .ADDRB(ADDRA), - .DIA(DINB), - .DIB(DINA), - .DOA(DOUTB), - .DOB(DOUTA), - .DOPB() -); +// 2048 words x 8 bits = 16,384 bits — Vivado infers this as a single RAMB18. +(* ram_style = "block" *) +reg [7:0] ram [0:2047]; + +// ----------------------------------------------------------------------- +// Port A: 8-bit synchronous read/write +// ----------------------------------------------------------------------- +always @(posedge CLKA) begin + DOUTA <= ram[ADDRA]; // read-first: capture old value + if (WEA) + ram[ADDRA] <= DINA; +end + +// ----------------------------------------------------------------------- +// Port B: 1-bit synchronous read/write +// ADDRB[13:3] — word address (maps to same address space as ADDRA) +// ADDRB[ 2:0] — bit index within the 8-bit word (0 = LSB) +// ----------------------------------------------------------------------- +always @(posedge CLKB) begin + DOUTB <= ram[ADDRB[13:3]][ADDRB[2:0]]; // read-first + if (WEB) + ram[ADDRB[13:3]][ADDRB[2:0]] <= DINB[0]; +end -endmodule +endmodule \ No newline at end of file From 2c1b413b972086f68fed7dd92f9522d73c6b6720 Mon Sep 17 00:00:00 2001 From: kcaisley Date: Wed, 29 Apr 2026 17:09:26 +0200 Subject: [PATCH 03/43] fix: replace 8-bit array with flat 1-bit array for RAMB18E1 inference --- .../modules/spi/blk_mem_gen_8_to_1_2k.v | 67 ++++++++++++------- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v index 89c7e5a2c..e7ce76950 100644 --- a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v +++ b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v @@ -5,20 +5,24 @@ * ------------------------------------------------------------ * * Asymmetric true dual-port BRAM: 2048 x 8-bit (Port A) / 16384 x 1-bit (Port B). - * Total capacity: 16,384 bits — inferred as RAMB18 on Xilinx 7-series and later. + * Total capacity: 16,384 bits → inferred as RAMB18E1 on 7-series (Kintex-7). * - * Replaces the legacy RAMB16_S1_S9 primitive which is no longer supported in - * Vivado 2025.x and causes functional issues in synthesis. + * Replaces the legacy RAMB16_S1_S9 primitive (Spartan-3/Virtex-4 era), + * which is unsupported in Vivado. * - * Port mapping (unchanged from original module interface): - * Port A: 8-bit wide, 2048 deep — ADDRA[10:0], DINA[7:0], DOUTA[7:0], WEA - * Port B: 1-bit wide, 16384 deep — ADDRB[13:0], DINB[0], DOUTB[0], WEB + * Inference strategy: + * Underlying array is 16384 × 1-bit. Port B (1-bit) accesses it directly. + * Port A (8-bit) uses a single always block with a procedural for loop + * that expands to 8 consecutive 1-bit locations at {ADDRA, i[2:0]}. + * Vivado sees only two clocked ports and infers a single RAMB18E1 in + * true dual-port (TDP) mode with asymmetric widths. + * (* ram_style = "block" *) attribute forces BRAM over distributed RAM. * - * Bit addressing: ADDRB[13:3] selects the 8-bit word; ADDRB[2:0] selects the - * bit within that word (0 = LSB, 7 = MSB), matching the RAMB16_S1_S9 convention. + * Port mapping (unchanged from original): + * Port A: 8-bit wide, 2048 deep — ADDRA[10:0], DINA[7:0], DOUTA[7:0], WEA + * Port B: 1-bit wide, 16384 deep — ADDRB[13:0], DINB[0], DOUTB[0], WEB * - * Read behaviour: read-first (output reflects the value before any write in the - * same cycle), consistent with the RAMB16_S1_S9 default configuration. + * Read behaviour: read-first on both ports (consistent with legacy primitive). * ------------------------------------------------------------ */ `timescale 1ps/1ps @@ -39,28 +43,39 @@ input wire [13 : 0] ADDRB; input wire [7 : 0] DINA; input wire [0 : 0] DINB; -// 2048 words x 8 bits = 16,384 bits — Vivado infers this as a single RAMB18. +// ------------------------------------------------------------------- +// Underlying array: 16384 × 1-bit, total 16,384 bits. +// Vivado infers a single RAMB18E1 in true-dual-port mode with +// asymmetric widths (Port A = 8-bit, Port B = 1-bit). +// ------------------------------------------------------------------- + (* ram_style = "block" *) -reg [7:0] ram [0:2047]; +reg [0:0] ram [0:16383]; + +// ------------------------------ +// Port A — 8-bit synchronous (procedural for loop, one port) +// +// ADDRA[10:0] selects a word; bit i lives at {ADDRA, i[2:0]}. +// The procedural for loop exposes only a single write port, +// matching the Vivado BRAM inference requirements. +// ------------------------------ +integer i; -// ----------------------------------------------------------------------- -// Port A: 8-bit synchronous read/write -// ----------------------------------------------------------------------- always @(posedge CLKA) begin - DOUTA <= ram[ADDRA]; // read-first: capture old value - if (WEA) - ram[ADDRA] <= DINA; + for (i = 0; i < 8; i = i + 1) begin + DOUTA[i] <= ram[{ADDRA, i[2:0]}]; + if (WEA) + ram[{ADDRA, i[2:0]}] <= DINA[i]; + end end -// ----------------------------------------------------------------------- -// Port B: 1-bit synchronous read/write -// ADDRB[13:3] — word address (maps to same address space as ADDRA) -// ADDRB[ 2:0] — bit index within the 8-bit word (0 = LSB) -// ----------------------------------------------------------------------- +// ------------------------------ +// Port B — 1-bit synchronous (simple, one port) +// ------------------------------ always @(posedge CLKB) begin - DOUTB <= ram[ADDRB[13:3]][ADDRB[2:0]]; // read-first + DOUTB <= ram[ADDRB]; if (WEB) - ram[ADDRB[13:3]][ADDRB[2:0]] <= DINB[0]; + ram[ADDRB] <= DINB[0]; end -endmodule \ No newline at end of file +endmodule From 507b474d20922a3d719ca2f3f7eb7744eb39d7c3 Mon Sep 17 00:00:00 2001 From: kcaisley Date: Thu, 30 Apr 2026 15:29:05 +0200 Subject: [PATCH 04/43] Update imports --- basil/firmware/modules/fast_spi_rx/fast_spi_rx.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v index a409a4316..da60b198c 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ + +`include "fast_spi_rx/fast_spi_rx_core.v" + `timescale 1ps/1ps `default_nettype none From 3b546c970aca70589bcb413d5b8336aec09aed1e Mon Sep 17 00:00:00 2001 From: kcaisley Date: Thu, 30 Apr 2026 18:39:37 +0200 Subject: [PATCH 05/43] fix: add guarded includes for shared utility modules Add `ifndef/`define/`endif guards around `bus_to_ip.v` and `cdc_pulse_sync.v` includes in all basil module files that use them. These two utilities are shared across multiple module subtrees (fast_spi_rx, pulse_gen, gpio, spi, seq_gen), so the include guards prevent MODDUP warnings when the module tree is pulled in from a common parent (e.g. daq_core.v). Only a subset of missing imports are addressed here as a starting point for testing the import pattern. All other transitive dependencies across the basil module tree should be wired up following the same pattern. --- basil/firmware/modules/fast_spi_rx/fast_spi_rx.v | 5 +++++ basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v | 8 ++++++++ basil/firmware/modules/gpio/gpio.v | 7 +++++++ basil/firmware/modules/pulse_gen/pulse_gen.v | 7 +++++++ basil/firmware/modules/pulse_gen/pulse_gen_core.v | 7 +++++++ basil/firmware/modules/seq_gen/seq_gen.v | 7 +++++++ basil/firmware/modules/seq_gen/seq_gen_core.v | 7 +++++++ basil/firmware/modules/spi/spi.v | 7 +++++++ basil/firmware/modules/spi/spi_core.v | 8 ++++++++ 9 files changed, 63 insertions(+) diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v index da60b198c..585e553da 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v @@ -6,6 +6,11 @@ */ `include "fast_spi_rx/fast_spi_rx_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index 6559dd2ec..565b8559f 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -4,6 +4,14 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif +`include "utils/cdc_syncfifo.v" +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/gpio/gpio.v b/basil/firmware/modules/gpio/gpio.v index 6b09545b3..211a9314d 100644 --- a/basil/firmware/modules/gpio/gpio.v +++ b/basil/firmware/modules/gpio/gpio.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "gpio/gpio_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/pulse_gen/pulse_gen.v b/basil/firmware/modules/pulse_gen/pulse_gen.v index 6e136a1ca..5e43a7254 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "pulse_gen/pulse_gen_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/pulse_gen/pulse_gen_core.v b/basil/firmware/modules/pulse_gen/pulse_gen_core.v index 3b7a75c16..0b5c1bd70 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen_core.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen_core.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "utils/3_stage_synchronizer.v" +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/seq_gen/seq_gen.v b/basil/firmware/modules/seq_gen/seq_gen.v index a6a51d353..20c345de8 100644 --- a/basil/firmware/modules/seq_gen/seq_gen.v +++ b/basil/firmware/modules/seq_gen/seq_gen.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "seq_gen/seq_gen_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index c81a69542..1b2d022b7 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "utils/ramb_8_to_n.v" +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/spi/spi.v b/basil/firmware/modules/spi/spi.v index 5aceab75d..e0c7ebfe6 100644 --- a/basil/firmware/modules/spi/spi.v +++ b/basil/firmware/modules/spi/spi.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "spi/spi_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/spi/spi_core.v b/basil/firmware/modules/spi/spi_core.v index 34f2e98ad..9c8871cd5 100644 --- a/basil/firmware/modules/spi/spi_core.v +++ b/basil/firmware/modules/spi/spi_core.v @@ -4,6 +4,14 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "spi/blk_mem_gen_8_to_1_2k.v" +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif +`include "utils/CG_MOD_pos.v" + `timescale 1ps/1ps `default_nettype none From 6bd888cca2c82d294973fc8d708938d6e7f32d51 Mon Sep 17 00:00:00 2001 From: kcaisley Date: Mon, 4 May 2026 17:56:54 +0200 Subject: [PATCH 06/43] chore(firmware): Adding explicit imports, with guard statement, to support linting --- basil/firmware/modules/bram_fifo/bram_fifo.v | 7 +++++++ .../modules/bram_fifo/bram_fifo_core.v | 2 ++ basil/firmware/modules/cmd_seq/cmd_seq.v | 7 +++++++ basil/firmware/modules/cmd_seq/cmd_seq_core.v | 11 +++++++++++ basil/firmware/modules/fei4_rx/fei4_rx.v | 7 +++++++ basil/firmware/modules/fei4_rx/fei4_rx_core.v | 7 +++++++ basil/firmware/modules/fei4_rx/rec_sync.v | 6 ++++++ .../firmware/modules/fei4_rx/receiver_logic.v | 15 +++++++++++++++ .../firmware/modules/gpac_adc_rx/gpac_adc_rx.v | 7 +++++++ .../modules/gpac_adc_rx/gpac_adc_rx_core.v | 18 ++++++++++++++++++ basil/firmware/modules/gpio/gpio_sbus.v | 7 +++++++ basil/firmware/modules/i2c/i2c.v | 7 +++++++ basil/firmware/modules/i2c/i2c_core.v | 6 ++++++ .../firmware/modules/jtag_master/jtag_master.v | 7 +++++++ .../modules/jtag_master/jtag_master_core.v | 12 ++++++++++++ basil/firmware/modules/m26_rx/m26_rx.v | 7 +++++++ basil/firmware/modules/m26_rx/m26_rx_core.v | 18 ++++++++++++++++++ basil/firmware/modules/seq_rec/seq_rec.v | 7 +++++++ basil/firmware/modules/seq_rec/seq_rec_core.v | 17 +++++++++++++++++ basil/firmware/modules/sram_fifo/sram_fifo.v | 7 +++++++ .../modules/sram_fifo/sram_fifo_core.v | 2 ++ basil/firmware/modules/tdc_s3/tdc_s3.v | 7 +++++++ basil/firmware/modules/tdc_s3/tdc_s3_core.v | 18 ++++++++++++++++++ basil/firmware/modules/tdl_tdc/sw_interface.v | 15 +++++++++++++++ basil/firmware/modules/tdl_tdc/tdl_tdc.v | 11 +++++++++++ basil/firmware/modules/timestamp/timestamp.v | 7 +++++++ .../modules/timestamp/timestamp_core.v | 12 ++++++++++++ basil/firmware/modules/tlu/tlu_controller.v | 6 ++++++ .../firmware/modules/tlu/tlu_controller_core.v | 17 +++++++++++++++++ 29 files changed, 277 insertions(+) diff --git a/basil/firmware/modules/bram_fifo/bram_fifo.v b/basil/firmware/modules/bram_fifo/bram_fifo.v index 51b5bf060..3dac60a4a 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "bram_fifo/bram_fifo_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/bram_fifo/bram_fifo_core.v b/basil/firmware/modules/bram_fifo/bram_fifo_core.v index 95c6527a7..ce6175f59 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo_core.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo_core.v @@ -4,6 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/cmd_seq/cmd_seq.v b/basil/firmware/modules/cmd_seq/cmd_seq.v index d04e3bfaf..9dbec5377 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "cmd_seq/cmd_seq_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/cmd_seq/cmd_seq_core.v b/basil/firmware/modules/cmd_seq/cmd_seq_core.v index f8d5bf33f..9a5823931 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq_core.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq_core.v @@ -4,6 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fei4_rx/fei4_rx.v b/basil/firmware/modules/fei4_rx/fei4_rx.v index 723371b8c..dc5938da8 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "fei4_rx/fei4_rx_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fei4_rx/fei4_rx_core.v b/basil/firmware/modules/fei4_rx/fei4_rx_core.v index 959057468..503959cad 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx_core.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx_core.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif +`include "fei4_rx/receiver_logic.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fei4_rx/rec_sync.v b/basil/firmware/modules/fei4_rx/rec_sync.v index a113680bf..6d8390852 100644 --- a/basil/firmware/modules/fei4_rx/rec_sync.v +++ b/basil/firmware/modules/fei4_rx/rec_sync.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fei4_rx/receiver_logic.v b/basil/firmware/modules/fei4_rx/receiver_logic.v index 574c95b0c..481675ee1 100644 --- a/basil/firmware/modules/fei4_rx/receiver_logic.v +++ b/basil/firmware/modules/fei4_rx/receiver_logic.v @@ -4,6 +4,21 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" +`include "fei4_rx/sync_master.v" +`include "fei4_rx/rec_sync.v" +`include "fei4_rx/decode_8b10b.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v index 545122ed7..94d4d55c3 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "gpac_adc_rx/gpac_adc_rx_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v index c3fd49488..7c58284ca 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v @@ -4,6 +4,24 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// cdc_reset_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_RESET_SYNC_V +`include "utils/cdc_reset_sync.v" +`define CDC_RESET_SYNC_V +`endif +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif +`include "utils/pulse_gen_rising.v" +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/gpio/gpio_sbus.v b/basil/firmware/modules/gpio/gpio_sbus.v index e3c824a0f..5827a64e9 100644 --- a/basil/firmware/modules/gpio/gpio_sbus.v +++ b/basil/firmware/modules/gpio/gpio_sbus.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "gpio/gpio_core.v" +// sbus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef SBUS_TO_IP_V +`include "utils/sbus_to_ip.v" +`define SBUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/i2c/i2c.v b/basil/firmware/modules/i2c/i2c.v index b1f9c715c..a0e95c1c7 100644 --- a/basil/firmware/modules/i2c/i2c.v +++ b/basil/firmware/modules/i2c/i2c.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "i2c/i2c_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/i2c/i2c_core.v b/basil/firmware/modules/i2c/i2c_core.v index 2df6acdd0..3d36562d9 100644 --- a/basil/firmware/modules/i2c/i2c_core.v +++ b/basil/firmware/modules/i2c/i2c_core.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/jtag_master/jtag_master.v b/basil/firmware/modules/jtag_master/jtag_master.v index b20cd8593..f173f298a 100644 --- a/basil/firmware/modules/jtag_master/jtag_master.v +++ b/basil/firmware/modules/jtag_master/jtag_master.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "jtag_master/jtag_master_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/jtag_master/jtag_master_core.v b/basil/firmware/modules/jtag_master/jtag_master_core.v index 418769896..beb5f0c85 100644 --- a/basil/firmware/modules/jtag_master/jtag_master_core.v +++ b/basil/firmware/modules/jtag_master/jtag_master_core.v @@ -4,6 +4,18 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "utils/ramb_8_to_n.v" +// cdc_reset_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_RESET_SYNC_V +`include "utils/cdc_reset_sync.v" +`define CDC_RESET_SYNC_V +`endif +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif +`include "utils/CG_MOD_pos.v" `default_nettype none diff --git a/basil/firmware/modules/m26_rx/m26_rx.v b/basil/firmware/modules/m26_rx/m26_rx.v index b40d06354..883fb7f1d 100644 --- a/basil/firmware/modules/m26_rx/m26_rx.v +++ b/basil/firmware/modules/m26_rx/m26_rx.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "m26_rx/m26_rx_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/m26_rx/m26_rx_core.v b/basil/firmware/modules/m26_rx/m26_rx_core.v index 95990e348..9ec42bb61 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_core.v +++ b/basil/firmware/modules/m26_rx/m26_rx_core.v @@ -4,6 +4,24 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif +`include "m26_rx/m26_rx_ch.v" +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/seq_rec/seq_rec.v b/basil/firmware/modules/seq_rec/seq_rec.v index 6a81e5625..db74c9ecf 100644 --- a/basil/firmware/modules/seq_rec/seq_rec.v +++ b/basil/firmware/modules/seq_rec/seq_rec.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "seq_rec/seq_rec_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/seq_rec/seq_rec_core.v b/basil/firmware/modules/seq_rec/seq_rec_core.v index f5e8f35b2..f3695472f 100644 --- a/basil/firmware/modules/seq_rec/seq_rec_core.v +++ b/basil/firmware/modules/seq_rec/seq_rec_core.v @@ -4,6 +4,23 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif +`include "utils/ramb_8_to_n.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/sram_fifo/sram_fifo.v b/basil/firmware/modules/sram_fifo/sram_fifo.v index e13099913..b23345d66 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "sram_fifo/sram_fifo_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/sram_fifo/sram_fifo_core.v b/basil/firmware/modules/sram_fifo/sram_fifo_core.v index 63c21dbaf..519414f0e 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo_core.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo_core.v @@ -4,6 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/tdc_s3/tdc_s3.v b/basil/firmware/modules/tdc_s3/tdc_s3.v index feb624812..ecc615d05 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "tdc_s3/tdc_s3_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/tdc_s3/tdc_s3_core.v b/basil/firmware/modules/tdc_s3/tdc_s3_core.v index f9e6ac7b1..175420da7 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3_core.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3_core.v @@ -4,6 +4,24 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif +`include "utils/ddr_des.v" +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/tdl_tdc/sw_interface.v b/basil/firmware/modules/tdl_tdc/sw_interface.v index fe317b8a5..cbed4b8cb 100644 --- a/basil/firmware/modules/tdl_tdc/sw_interface.v +++ b/basil/firmware/modules/tdl_tdc/sw_interface.v @@ -1,4 +1,19 @@ `include "tdl_tdc/utils/graycode_2stage_cdc.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif module tdc_sw_interface #( parameter VERSION = 8'b00000000, diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc.v b/basil/firmware/modules/tdl_tdc/tdl_tdc.v index 8deafa99f..ead1dee2f 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc.v @@ -7,6 +7,17 @@ `include "tdl_tdc/sw_interface.v" `include "tdl_tdc/tdl_tdc_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" module tdl_tdc #( parameter BASEADDR = 32'h0000, diff --git a/basil/firmware/modules/timestamp/timestamp.v b/basil/firmware/modules/timestamp/timestamp.v index 062dcf8cd..a3f303c5b 100644 --- a/basil/firmware/modules/timestamp/timestamp.v +++ b/basil/firmware/modules/timestamp/timestamp.v @@ -4,6 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "timestamp/timestamp_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/timestamp/timestamp_core.v b/basil/firmware/modules/timestamp/timestamp_core.v index a404e68a0..3728eea29 100644 --- a/basil/firmware/modules/timestamp/timestamp_core.v +++ b/basil/firmware/modules/timestamp/timestamp_core.v @@ -4,6 +4,18 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// cdc_pulse_sync is shared across several basil modules; guard against double inclusion +`ifndef CDC_PULSE_SYNC_V +`include "utils/cdc_pulse_sync.v" +`define CDC_PULSE_SYNC_V +`endif +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" + `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/tlu/tlu_controller.v b/basil/firmware/modules/tlu/tlu_controller.v index 6a013f7e2..939332ee1 100644 --- a/basil/firmware/modules/tlu/tlu_controller.v +++ b/basil/firmware/modules/tlu/tlu_controller.v @@ -4,6 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`include "tlu/tlu_controller_core.v" +// bus_to_ip is shared across several basil modules; guard against double inclusion +`ifndef BUS_TO_IP_V +`include "utils/bus_to_ip.v" +`define BUS_TO_IP_V +`endif `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/tlu/tlu_controller_core.v b/basil/firmware/modules/tlu/tlu_controller_core.v index 07028e7d7..096ee3d61 100644 --- a/basil/firmware/modules/tlu/tlu_controller_core.v +++ b/basil/firmware/modules/tlu/tlu_controller_core.v @@ -4,6 +4,23 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +// flag_domain_crossing is shared across several basil modules; guard against double inclusion +`ifndef FLAG_DOMAIN_CROSSING_V +`include "utils/flag_domain_crossing.v" +`define FLAG_DOMAIN_CROSSING_V +`endif +// three_stage_synchronizer is shared across several basil modules; guard against double inclusion +`ifndef THREE_STAGE_SYNCHRONIZER_V +`include "utils/3_stage_synchronizer.v" +`define THREE_STAGE_SYNCHRONIZER_V +`endif +`include "tlu/tlu_controller_fsm.v" +// cdc_syncfifo is shared across several basil modules; guard against double inclusion +`ifndef CDC_SYNCFIFO_V +`include "utils/cdc_syncfifo.v" +`define CDC_SYNCFIFO_V +`endif +`include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none From 43d5fe0be1324dd392f83360264db744af7578aa Mon Sep 17 00:00:00 2001 From: kcaisley Date: Tue, 5 May 2026 15:40:10 +0200 Subject: [PATCH 07/43] fix: Change alignment of INFO statements in logging --- basil/dut.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/basil/dut.py b/basil/dut.py index e118629f5..2310d63d5 100644 --- a/basil/dut.py +++ b/basil/dut.py @@ -20,7 +20,7 @@ from yaml import safe_load logging.basicConfig( - level=logging.INFO, format="%(asctime)s - %(name)s - [%(levelname)-8s] (%(threadName)-10s) %(message)s" + level=logging.INFO, format="%(asctime)s - %(name)s - [%(levelname)s] (%(threadName)-10s) %(message)s" ) From 1d9288695b907bffa28c51c60048adddf0755c43 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Tue, 5 May 2026 23:22:11 +0200 Subject: [PATCH 08/43] feat(utils): add address-map bus checker utility Add a standalone Python script for verifying and documenting FPGA/ASIC register address maps. The tool: - Parses Verilog module port/parameter definitions for bus interfaces - Parses YAML register-map descriptions (basil-style) - Generates Markdown tables and ASCII-address-space diagrams - Detects overlapping address ranges and out-of-range assignments Useful as a CI gate to catch address-map bugs before synthesis. --- basil/utils/bus_check.py | 784 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 784 insertions(+) create mode 100644 basil/utils/bus_check.py diff --git a/basil/utils/bus_check.py b/basil/utils/bus_check.py new file mode 100644 index 000000000..eaf16b246 --- /dev/null +++ b/basil/utils/bus_check.py @@ -0,0 +1,784 @@ +#!/usr/bin/env python3 +""" +Basil Bus Address Map Generator and Verification Tool + +This utility: +1. Parses Verilog modules to extract default BASEADDR/HIGHADDR parameters +2. Parses YAML configuration files to extract configured addresses +3. Cross-checks Verilog defaults against YAML configurations +4. Detects address range overlaps +5. Generates markdown tables and ASCII diagrams of the address map + +Usage: + # As a module + python -m basil.utils.check_bus + + # With custom paths + python -m basil.utils.check_bus --verilog-glob "basil/firmware/modules/**/*.v" \ + --yaml-glob "examples/**/*.yaml" + + # As pre-commit hook + python -m basil.utils.check_bus --quiet +""" + +import argparse +import glob +import re +import sys +from pathlib import Path +from collections import defaultdict + +try: + import yaml + HAS_YAML = True +except ImportError: + HAS_YAML = False + + +def parse_verilog_modules(verilog_glob, base_dir=None): + """ + Extract module names and address parameters from Verilog files. + + This parses: + 1. Module declarations with BASEADDR/HIGHADDR parameters + 2. Localparam/parameter definitions (e.g., SEQ_GEN_BASEADDR = 32'h10000) + 3. Module instantiations with .BASEADDR()/.HIGHADDR() parameter assignments + + Args: + verilog_glob: Glob pattern for Verilog files + base_dir: Base directory for relative paths (default: current dir) + + Returns: + dict: {module_name: {baseaddr, highaddr, file, line, instantiation_name, type}} + """ + if base_dir is None: + base_dir = Path.cwd() + else: + base_dir = Path(base_dir) + + modules = {} + + for v_path in Path(base_dir).glob(verilog_glob): + if not v_path.is_file(): + continue + + try: + with open(v_path, 'r', encoding='utf-8') as f: + content = f.read() + except (IOError, UnicodeDecodeError): + continue + + # First pass: Find all localparam/parameter definitions that look like addresses + # These are typically named *BASEADDR or *HIGHADDR + # Build a dict of name -> raw value string first + localparam_defs = {} + param_pattern = re.compile( + r'^(?:\s*)?(?:localparam|parameter)\s+(?:integer\s+)?(\w+)\s*=\s*([^;]+);', + re.MULTILINE | re.IGNORECASE + ) + + for match in param_pattern.finditer(content): + param_name = match.group(1) + param_value_expr = match.group(2).strip() + + # Only care about params that look like address parameters + if 'ADDR' in param_name.upper(): + localparam_defs[param_name] = param_value_expr + + # Now resolve all localparam values (handle references to other localparams) + localparams = {} + for param_name, param_value_expr in localparam_defs.items(): + value = resolve_verilog_expression(param_value_expr, content, localparams) + if value is not None: + localparams[param_name] = value + else: + # Try to parse directly as a literal + try: + localparams[param_name] = parse_verilog_value(param_value_expr) + except (ValueError, AttributeError): + pass + + # Second pass: Find all module declarations with BASEADDR/HIGHADDR parameters + module_pattern = re.compile( + r'module\s+(\w+)\s*#\s*\((.*?)\)\s*\([^)]*\)', + re.DOTALL + ) + + for match in module_pattern.finditer(content): + module_name = match.group(1) + params_block = match.group(2) + + # Extract BASEADDR and HIGHADDR + baseaddr = None + highaddr = None + + for param_match in re.finditer( + r'parameter\s+(BASEADDR|HIGHADDR)\s*=\s*(\w+)', + params_block, + re.IGNORECASE + ): + param_name = param_match.group(1).upper() + param_value_str = param_match.group(2) + value = parse_verilog_value(param_value_str) + + if param_name == "BASEADDR": + baseaddr = value + elif param_name == "HIGHADDR": + highaddr = value + + if baseaddr is not None: + modules[module_name] = { + 'file': str(v_path.relative_to(base_dir)), + 'baseaddr': baseaddr, + 'highaddr': highaddr if highaddr is not None else baseaddr, + 'type': 'verilog', + 'instantiation_name': None + } + + # Third pass: Find module instantiations with BASEADDR/HIGHADDR + # We need to search inside module bodies only, not module declarations. + # Strategy: Find each module body (between 'module' and 'endmodule'), + # then search for instantiations within it. + + module_body_pattern = re.compile( + r'module\s+\w+[^;]*;(.+?)endmodule', + re.DOTALL + ) + + for body_match in module_body_pattern.finditer(content): + module_body = body_match.group(1) + body_offset = body_match.start(1) + + # Find instantiations within this module body + # Pattern: module_type #( ... ) instance_name ( + inst_decl_pattern = re.compile( + r'(\w+)\s*#\s*\((.*?)\)\s+(\w+)\s*\(', + re.DOTALL + ) + + for match in inst_decl_pattern.finditer(module_body): + module_type = match.group(1) + params_block = match.group(2) + instance_name = match.group(3) + + # Now parse the params_block for BASEADDR and HIGHADDR + baseaddr = None + highaddr = None + + # Look for .BASEADDR(value) or .BASEADDR (value) + baseaddr_match = re.search( + r'\.BASEADDR\s*\(([^)]+)\)', + params_block, + re.IGNORECASE + ) + if baseaddr_match: + baseaddr_expr = baseaddr_match.group(1).strip() + baseaddr = resolve_verilog_expression(baseaddr_expr, content, localparams) + + # Look for .HIGHADDR(value) or .HIGHADDR (value) + highaddr_match = re.search( + r'\.HIGHADDR\s*\(([^)]+)\)', + params_block, + re.IGNORECASE + ) + if highaddr_match: + highaddr_expr = highaddr_match.group(1).strip() + highaddr = resolve_verilog_expression(highaddr_expr, content, localparams) + + if baseaddr is not None: + modules[instance_name] = { + 'file': str(v_path.relative_to(base_dir)), + 'baseaddr': baseaddr, + 'highaddr': highaddr if highaddr is not None else baseaddr, + 'type': module_type, + 'instantiation_name': instance_name + } + + return modules + + +def resolve_verilog_expression(expr, content, localparams=None): + """ + Resolve a Verilog expression to an integer value. + + Handles: + - Literal values: 32'h10000, 16'h0000, etc. + - Localparam references: SEQ_GEN_BASEADDR + - Simple identifiers that might be defined elsewhere + + Args: + expr: The expression string to resolve + content: Full Verilog file content for localparam lookup + localparams: Optional dict of already-parsed localparams for faster lookup + + Returns: + int or None if cannot be resolved + """ + expr = expr.strip() + + # If it's a simple identifier, look for localparam definitions first + # (before trying literal parse, which would return 0 for identifiers) + if re.match(r'^[a-zA-Z_][a-zA-Z0-9_]*$', expr): + # Check pre-parsed localparams first + if localparams and expr in localparams: + return localparams[expr] + + # Look for localparam or parameter definitions in content + param_pattern = re.compile( + rf'^(?:localparam|parameter)\s+(?:integer\s+)?{expr}\s*=\s*([^;]+);', + re.MULTILINE | re.IGNORECASE + ) + match = param_pattern.search(content) + if match: + param_value_expr = match.group(1).strip() + # Recursively resolve the value expression + return resolve_verilog_expression(param_value_expr, content, localparams) + + # Try to parse as a literal value + try: + value = parse_verilog_value(expr) + # parse_verilog_value returns 0 for unparseable identifiers, + # so we need to distinguish between actual 0 and failed parse + if value == 0 and not re.match(r'^\s*(0+|0x0+|\d+\'[hdb]0+)\s*$', expr, re.IGNORECASE): + return None + return value + except (ValueError, AttributeError): + pass + + return None + + +def parse_verilog_value(value_str): + """ + Parse a Verilog parameter value string into an integer. + + Handles formats like: + - 16'h0000 + - 8'hFF + - 32'd1024 + - 1024 + - 32'h10000 + """ + value_str = value_str.strip() + + # Hex with width prefix: 16'h0000, 8'hFF, 32'h10000 + hex_match = re.match(r'\d+\'h([0-9a-fA-F]+)', value_str) + if hex_match: + return int(hex_match.group(1), 16) + + # Decimal with width prefix: 32'd1024 + dec_match = re.match(r'\d+\'d(\d+)', value_str) + if dec_match: + return int(dec_match.group(1), 10) + + # Binary with width prefix: 8'b1010 + bin_match = re.match(r'\d+\'b([01]+)', value_str) + if bin_match: + return int(bin_match.group(1), 2) + + # Plain hex: h0000, 'h0000 + if value_str.startswith("h") or value_str.startswith("'h"): + hex_str = value_str[2:] if value_str.startswith("h") else value_str[1:] + return int(hex_str, 16) + + # Plain decimal + try: + return int(value_str, 10) + except ValueError: + # If we can't parse it, return 0 + return 0 + + +def parse_yaml_configs(yaml_glob, base_dir=None): + """ + Extract hw_drivers and their addresses from YAML files. + + Args: + yaml_glob: Glob pattern for YAML files + base_dir: Base directory for relative paths + + Returns: + dict: {driver_type: [{name, base_addr, size, high_addr, file, line}]} + """ + if not HAS_YAML: + print("Error: PyYAML is required. Install with: pip install pyyaml", file=sys.stderr) + sys.exit(1) + + if base_dir is None: + base_dir = Path.cwd() + else: + base_dir = Path(base_dir) + + drivers = defaultdict(list) + + for yaml_path in Path(base_dir).glob(yaml_glob): + if not yaml_path.is_file(): + continue + + try: + with open(yaml_path, 'r', encoding='utf-8') as f: + config = yaml.safe_load(f) + except (yaml.YAMLError, IOError): + continue + + if not config or not isinstance(config, dict): + continue + + if 'hw_drivers' in config: + for idx, driver in enumerate(config['hw_drivers']): + if not isinstance(driver, dict): + continue + if 'base_addr' not in driver or 'type' not in driver: + continue + + driver_type = driver['type'] + base_addr = driver['base_addr'] + # Handle both 'size' and 'mem_size' - mem_size is the address range, size is register size + size = driver.get('size', driver.get('mem_size', 0)) + + # Handle string hex addresses like "0x10000" + if isinstance(base_addr, str): + if base_addr.startswith('0x'): + base_addr = int(base_addr, 16) + else: + base_addr = int(base_addr, 10) + + if isinstance(size, str): + if size.startswith('0x'): + size = int(size, 16) + else: + size = int(size, 10) + + high_addr = base_addr + size - 1 if size > 0 else base_addr + + entry = { + 'file': str(yaml_path.relative_to(base_dir)), + 'name': driver.get('name', f'unnamed_{idx}'), + 'type': driver_type, + 'base_addr': base_addr, + 'size': size, + 'high_addr': high_addr, + 'yaml_type': 'hw_driver' + } + drivers[driver_type].append(entry) + + return drivers + + +def generate_address_map(verilog_modules, yaml_drivers): + """ + Generate address map from Verilog and cross-check against YAML. + + The table is built from Verilog modules. For each Verilog module, we try to + find a matching YAML driver by module type. If found, we verify the addresses + match. If not found, we warn that the YAML config is missing. + + Args: + verilog_modules: Dict of Verilog modules from parse_verilog_modules + yaml_drivers: Dict of YAML drivers from parse_yaml_configs + + Returns: + tuple: (address_map_list, issues_list) + """ + address_map = [] + issues = [] + + # Build lookup structures for YAML drivers + # yaml_by_type: {module_type: [driver1, driver2, ...]} + yaml_by_type = {} + for driver_type, driver_list in yaml_drivers.items(): + yaml_by_type[driver_type] = driver_list + + # Track which YAML drivers have been matched to Verilog + matched_yaml = set() + + # Process Verilog modules - this is the primary data source + for module_name, module_info in verilog_modules.items(): + module_type = module_info.get('type', module_name) + v_base = module_info['baseaddr'] + v_high = module_info['highaddr'] + v_size = v_high - v_base + 1 + + # Try to find matching YAML driver(s) by module type + yaml_matches = yaml_by_type.get(module_type, []) + + # Find the best match: same base address + best_match = None + for yd in yaml_matches: + if yd['base_addr'] == v_base: + best_match = yd + matched_yaml.add(id(yd)) + break + + # If no exact base address match, take the first one of this type + if not best_match and yaml_matches: + best_match = yaml_matches[0] + matched_yaml.add(id(best_match)) + + # Build the table row + row = { + 'module': module_name, + 'type': module_type, + 'base_addr': v_base, + 'high_addr': v_high, + 'size': v_size, + 'verilog_file': module_info['file'], + 'yaml_name': best_match['name'] if best_match else None, + 'yaml_file': best_match['file'] if best_match else None, + 'yaml_base': best_match['base_addr'] if best_match else None, + 'yaml_high': best_match['high_addr'] if best_match else None, + 'status': 'OK' + } + + # Determine status and generate issues + if not best_match: + row['status'] = 'MISSING_YAML' + issues.append({ + 'type': 'missing_yaml', + 'severity': 'warning', + 'module': module_name, + 'module_type': module_type, + 'verilog_file': module_info['file'], + 'verilog_addr': (v_base, v_high), + 'message': f"Verilog module '{module_name}' ({module_type}) has no matching YAML config" + }) + elif best_match['base_addr'] != v_base or best_match['high_addr'] != v_high: + row['status'] = 'MISMATCH' + issues.append({ + 'type': 'address_mismatch', + 'severity': 'warning', + 'module': module_name, + 'module_type': module_type, + 'verilog_file': module_info['file'], + 'yaml_file': best_match['file'], + 'verilog_addr': (v_base, v_high), + 'yaml_addr': (best_match['base_addr'], best_match['high_addr']), + 'message': f"Verilog module '{module_name}' ({module_type}) address mismatch" + }) + else: + row['status'] = 'OK' + + address_map.append(row) + + # Warn about YAML drivers that weren't matched to any Verilog module + for driver_type, driver_list in yaml_drivers.items(): + for driver in driver_list: + if id(driver) not in matched_yaml: + issues.append({ + 'type': 'unmatched_yaml', + 'severity': 'info', + 'module': driver['name'], + 'module_type': driver_type, + 'yaml_file': driver['file'], + 'yaml_addr': (driver['base_addr'], driver['high_addr']), + 'message': f"YAML driver '{driver['name']}' ({driver_type}) at {format_address(driver['base_addr'])}-{format_address(driver['high_addr'])} not found in Verilog" + }) + + return address_map, issues + + +def check_overlaps(address_map): + """ + Check for address range overlaps in the Verilog address map. + + Args: + address_map: List of address entries + + Returns: + list: List of overlap issues + """ + overlaps = [] + + for i, entry1 in enumerate(address_map): + for j, entry2 in enumerate(address_map): + if i >= j: + continue + + # Check if ranges truly overlap (not just adjacent) + if (entry1['base_addr'] < entry2['high_addr'] and + entry2['base_addr'] < entry1['high_addr']): + + # Only report if they're different instances + if entry1['module'] != entry2['module']: + overlaps.append({ + 'type': 'address_overlap', + 'severity': 'error', + 'module1': entry1['module'], + 'module2': entry2['module'], + 'range1': (entry1['base_addr'], entry1['high_addr']), + 'range2': (entry2['base_addr'], entry2['high_addr']), + 'file1': entry1['verilog_file'], + 'file2': entry2['verilog_file'], + 'message': f"Address overlap between {entry1['module']} and {entry2['module']}" + }) + + return overlaps + + +def format_address(addr, width=8): + """Format an address as hex with consistent width.""" + return f"0x{addr:0{width}X}" + + +def generate_markdown_table(address_map): + """Generate an aligned plain-text table of the address map.""" + if not address_map: + return "No address entries found." + + # Sort by base_addr + sorted_map = sorted(address_map, key=lambda x: x['base_addr']) + + # Calculate column widths + headers = ["Instance", "Module", "Base Address", "High Address", "Size", "File", "YAML Match"] + rows = [] + for entry in sorted_map: + size = entry['size'] + size_str = f"{size:,}" if size > 0 else "N/A" + + # Build YAML match info + if entry['status'] == 'OK': + yaml_match = entry['yaml_name'] if entry.get('yaml_name') else "OK" + elif entry['status'] == 'MISSING_YAML': + yaml_match = "MISSING" + elif entry['status'] == 'MISMATCH': + yaml_match = f"MISMATCH ({format_address(entry['yaml_base'])}-{format_address(entry['yaml_high'])})" + else: + yaml_match = "?" + + rows.append([ + entry['module'], + entry['type'], + format_address(entry['base_addr']), + format_address(entry['high_addr']), + size_str, + entry['verilog_file'], + yaml_match + ]) + + # Determine max width for each column + col_widths = [len(h) for h in headers] + for row in rows: + for i, cell in enumerate(row): + col_widths[i] = max(col_widths[i], len(cell)) + + # Build formatted output + lines = [] + # Header row + header_row = " ".join(h.ljust(col_widths[i]) for i, h in enumerate(headers)) + lines.append(header_row) + lines.append("-" * len(header_row)) + # Data rows + for row in rows: + lines.append(" ".join(cell.ljust(col_widths[i]) for i, cell in enumerate(row))) + + return "\n".join(lines) + + +def generate_ascii_diagram(address_map): + """Generate an ASCII memory map diagram from Verilog entries.""" + if not address_map: + return "No address entries found for diagram." + + # Sort all entries by base address + sorted_map = sorted(address_map, key=lambda x: x['base_addr']) + + lines = [] + lines.append("Basil Bus Address Map Diagram") + lines.append("=" * 70) + lines.append("") + + for entry in sorted_map: + base = entry['base_addr'] + high = entry['high_addr'] + size = entry['size'] + + # Format size with appropriate units + if size >= 1024 * 1024: + size_str = f"{size / (1024 * 1024):.2f}MB" + elif size >= 1024: + size_str = f"{size / 1024:.2f}KB" + else: + size_str = f"{size}B" if size > 0 else "N/A" + + base_hex = format_address(base) + high_hex = format_address(high) + + # Show status indicator + status = entry.get('status', '?') + if status == 'OK': + indicator = "[OK]" + elif status == 'MISSING_YAML': + indicator = "[NO YAML]" + elif status == 'MISMATCH': + indicator = "[MISMATCH]" + else: + indicator = "[?]" + + label = f"{entry['module']} [{entry['type']}]" + + lines.append( + f"{indicator:10s} {base_hex} - {high_hex} : " + f"{label} ({size_str})" + ) + + return "\n".join(lines) + + +def print_issues(issues, overlaps, quiet=False): + """Print issues found during analysis.""" + all_issues = issues + overlaps + + if not all_issues: + if not quiet: + print("OK: No issues found - Verilog and YAML addresses are consistent!") + return 0 + + error_count = sum(1 for i in all_issues if i['severity'] == 'error') + warning_count = sum(1 for i in all_issues if i['severity'] == 'warning') + info_count = sum(1 for i in all_issues if i['severity'] == 'info') + + if not quiet: + print(f"\nFound {error_count} error(s), {warning_count} warning(s), {info_count} info(s)") + print() + + for issue in all_issues: + severity_label = { + 'error': '[ERROR]', + 'warning': '[WARN] ', + 'info': '[INFO] ' + }.get(issue['severity'], '[ ]') + + if not quiet or issue['severity'] in ['error', 'warning']: + print(f"{severity_label} {issue['type'].replace('_', ' ').title()}") + print(f" {issue['message']}") + + if 'module' in issue: + print(f" Module: {issue['module']}") + if 'yaml_file' in issue: + print(f" YAML file: {issue['yaml_file']}") + if 'verilog_file' in issue: + print(f" Verilog file: {issue['verilog_file']}") + if 'verilog_addr' in issue: + v_base, v_high = issue['verilog_addr'] + print(f" Verilog address: {format_address(v_base)} - {format_address(v_high)}") + if 'verilog_default' in issue: + v_base, v_high = issue['verilog_default'] + print(f" Verilog default: {format_address(v_base)} - {format_address(v_high)}") + if 'yaml_addr' in issue: + y_base, y_high = issue['yaml_addr'] + print(f" YAML address: {format_address(y_base)} - {format_address(y_high)}") + if 'yaml_configured' in issue: + y_base, y_high = issue['yaml_configured'] + print(f" YAML configured: {format_address(y_base)} - {format_address(y_high)}") + if 'range1' in issue: + r1_base, r1_high = issue['range1'] + r2_base, r2_high = issue['range2'] + print(f" Range 1: {format_address(r1_base)} - {format_address(r1_high)}") + print(f" Range 2: {format_address(r2_base)} - {format_address(r2_high)}") + print() + + return 1 if error_count > 0 else 0 + + +def main(): + """Main entry point for the script.""" + parser = argparse.ArgumentParser( + description="Generate and verify Basil bus address map", + formatter_class=argparse.RawDescriptionHelpFormatter, + epilog=""" +Examples: + # Check all Basil files + python -m basil.utils.check_bus + + # Check specific paths + python -m basil.utils.check_bus --verilog-glob "basil/firmware/modules/**/*.v" \\ + --yaml-glob "examples/**/*.yaml" + + # As pre-commit hook (exits with error code on issues) + python -m basil.utils.check_bus --quiet + + # Examples: + python check_bus.py --verilog-glob "firmware/src/**/*.v" --yaml-glob "**/*.yaml" --base-dir ~/libs/tj-monopix2-daq + python check_bus.py --verilog-glob "firmware/src/**/*.v" --yaml-glob "**/*.yaml" --base-dir ~/libs/obelix1-daq + python check_bus.py --verilog-glob "design/fpga/daq_core.v" --yaml-glob "flow/scans/map_fpga.yaml" --base-dir /local/frida +""" + ) + + parser.add_argument( + '--verilog-glob', + default='basil/firmware/modules/**/*.v', + help='Glob pattern for Verilog files (relative to base-dir)' + ) + parser.add_argument( + '--yaml-glob', + default='**/*.yaml', + help='Glob pattern for YAML configuration files (relative to base-dir)' + ) + parser.add_argument( + '--base-dir', + default='.', + help='Base directory for glob patterns (default: current directory)' + ) + parser.add_argument( + '--output', + type=str, + default=None, + help='Output file for address map (default: stdout)' + ) + # Note: Overlap checking is always enabled + parser.add_argument( + '--quiet', + action='store_true', + help='Suppress non-error output (useful for pre-commit hooks)' + ) + parser.add_argument( + '--no-color', + action='store_true', + help='Disable colored output' + ) + + args = parser.parse_args() + + # Resolve base directory + base_dir = Path(args.base_dir).resolve() + + # Parse Verilog modules + verilog_modules = parse_verilog_modules(args.verilog_glob, base_dir) + + # Parse YAML configurations + yaml_drivers = parse_yaml_configs(args.yaml_glob, base_dir) + yaml_driver_count = sum(len(v) for v in yaml_drivers.values()) + + # Generate address map and check for issues + address_map, issues = generate_address_map(verilog_modules, yaml_drivers) + + # Always check for overlaps + overlaps = check_overlaps(address_map) + + # Generate output - just the table + output_lines = [] + output_lines.append("# Basil Bus Address Map") + output_lines.append("") + output_lines.append(generate_markdown_table(address_map)) + + # Write output + output_text = "\n".join(output_lines) + + if args.output: + with open(args.output, 'w', encoding='utf-8') as f: + f.write(output_text) + if not args.quiet: + print(f"\nAddress map written to: {args.output}") + else: + print(output_text) + + # Print issues and return appropriate exit code + exit_code = print_issues(issues, overlaps, quiet=args.quiet) + + # Summary is implicit in the output + + sys.exit(exit_code) + + +if __name__ == '__main__': + main() From 75fd93fdb57f6ad654352ba12e87929de3236edf Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Tue, 12 May 2026 15:47:30 +0200 Subject: [PATCH 09/43] chore: Cleanup typos --- basil/firmware/modules/seq_gen/seq_gen_core.v | 8 ++++---- basil/firmware/modules/utils/cdc_pulse_sync.v | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index 1b2d022b7..5fae307eb 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -71,8 +71,8 @@ always @(posedge BUS_CLK) begin status_regs[6] <= DEF_BIT_OUT[23:16]; // -||- status_regs[7] <= DEF_BIT_OUT[31:24]; // -||- - status_regs[8] <= 0; // wait - status_regs[9] <= 0; // -||- + status_regs[8] <= 0; // wait + status_regs[9] <= 0; // -||- status_regs[10] <= 0; // -||- status_regs[11] <= 0; // -||- @@ -81,7 +81,7 @@ always @(posedge BUS_CLK) begin status_regs[14] <= 0; // -||- status_regs[15] <= 0; // -||- - status_regs[16] <= 0; //repeat start + status_regs[16] <= 0; // repeat start status_regs[17] <= 0; // -||- status_regs[18] <= 0; // -||- status_regs[19] <= 0; // -||- @@ -96,7 +96,7 @@ always @(posedge BUS_CLK) begin status_regs[26] <= 0; // -||- status_regs[27] <= 0; // -||- - status_regs[28] <= 0; // nested loop repat count + status_regs[28] <= 0; // nested loop repeat count status_regs[29] <= 0; // -||- status_regs[30] <= 0; // -||- status_regs[31] <= 0; // -||- diff --git a/basil/firmware/modules/utils/cdc_pulse_sync.v b/basil/firmware/modules/utils/cdc_pulse_sync.v index c1b3dfa87..ec46bfff9 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync.v @@ -45,6 +45,7 @@ always @(posedge clk_out) begin out_sync_ff_3 <= out_sync_ff_2; end +// Fire output for one clock period, when transition is detected assign pulse_out = !out_sync_ff_3 && out_sync_ff_2; (* ASYNC_REG = "TRUE" *) reg aq_sync_ff_1; From 41c6498bfdc4b21bc8bb7868b69e50915210b4e8 Mon Sep 17 00:00:00 2001 From: kcaisley Date: Wed, 6 May 2026 17:49:57 +0200 Subject: [PATCH 10/43] feat: update primitive module names and add simulation models - Rename _sim.v files to match module names (BUFG, IBUFDS, etc.) - Add new simulation models for missing primitives (IBUF, OBUF, IOBUF, ODDR, PLLE2_BASE) - Add behavioral implementations for buffer primitives - Keep copyright headers and formatting consistent with existing style --- .../modules/utils/{BUFG_sim.v => BUFG.v} | 0 .../modules/utils/{ODDR_sim.v => IBUF.v} | 17 ++----- .../modules/utils/{IBUFDS_sim.v => IBUFDS.v} | 3 +- .../utils/{IBUFGDS_sim.v => IBUFGDS.v} | 0 .../modules/utils/{IDDR_sim.v => IDDR.v} | 0 basil/firmware/modules/utils/IOBUF.v | 21 +++++++++ basil/firmware/modules/utils/OBUF.v | 18 ++++++++ .../modules/utils/{OBUFDS_sim.v => OBUFDS.v} | 0 basil/firmware/modules/utils/ODDR.v | 39 ++++++++++++++++ basil/firmware/modules/utils/PLLE2_BASE.v | 44 +++++++++++++++++++ 10 files changed, 128 insertions(+), 14 deletions(-) rename basil/firmware/modules/utils/{BUFG_sim.v => BUFG.v} (100%) rename basil/firmware/modules/utils/{ODDR_sim.v => IBUF.v} (58%) rename basil/firmware/modules/utils/{IBUFDS_sim.v => IBUFDS.v} (84%) rename basil/firmware/modules/utils/{IBUFGDS_sim.v => IBUFGDS.v} (100%) rename basil/firmware/modules/utils/{IDDR_sim.v => IDDR.v} (100%) create mode 100644 basil/firmware/modules/utils/IOBUF.v create mode 100644 basil/firmware/modules/utils/OBUF.v rename basil/firmware/modules/utils/{OBUFDS_sim.v => OBUFDS.v} (100%) create mode 100644 basil/firmware/modules/utils/ODDR.v create mode 100644 basil/firmware/modules/utils/PLLE2_BASE.v diff --git a/basil/firmware/modules/utils/BUFG_sim.v b/basil/firmware/modules/utils/BUFG.v similarity index 100% rename from basil/firmware/modules/utils/BUFG_sim.v rename to basil/firmware/modules/utils/BUFG.v diff --git a/basil/firmware/modules/utils/ODDR_sim.v b/basil/firmware/modules/utils/IBUF.v similarity index 58% rename from basil/firmware/modules/utils/ODDR_sim.v rename to basil/firmware/modules/utils/IBUF.v index 1f92be176..f4bf337f4 100644 --- a/basil/firmware/modules/utils/ODDR_sim.v +++ b/basil/firmware/modules/utils/IBUF.v @@ -8,20 +8,11 @@ `default_nettype none -module ODDR ( - input wire D1, D2, - input wire C, CE, R, S, - output wire Q +module IBUF ( + output wire O, + input wire I ); -reg Q1, Q2; - -always @(posedge C) - Q1 <= D1; - -always @(negedge C) - Q2 <= D2; - -assign Q = C ? Q1 & CE : Q2 & CE; +assign O = I; endmodule diff --git a/basil/firmware/modules/utils/IBUFDS_sim.v b/basil/firmware/modules/utils/IBUFDS.v similarity index 84% rename from basil/firmware/modules/utils/IBUFDS_sim.v rename to basil/firmware/modules/utils/IBUFDS.v index b7ff8d7ba..97063b439 100644 --- a/basil/firmware/modules/utils/IBUFDS_sim.v +++ b/basil/firmware/modules/utils/IBUFDS.v @@ -9,7 +9,8 @@ module IBUFDS #( parameter DIFF_TERM = "TRUE", - parameter IOSTANDARD = "LVDS_25" + parameter IBUF_LOW_PWR = "FALSE", + parameter IOSTANDARD = "LVDS_25" ) ( output wire O, input wire I, IB diff --git a/basil/firmware/modules/utils/IBUFGDS_sim.v b/basil/firmware/modules/utils/IBUFGDS.v similarity index 100% rename from basil/firmware/modules/utils/IBUFGDS_sim.v rename to basil/firmware/modules/utils/IBUFGDS.v diff --git a/basil/firmware/modules/utils/IDDR_sim.v b/basil/firmware/modules/utils/IDDR.v similarity index 100% rename from basil/firmware/modules/utils/IDDR_sim.v rename to basil/firmware/modules/utils/IDDR.v diff --git a/basil/firmware/modules/utils/IOBUF.v b/basil/firmware/modules/utils/IOBUF.v new file mode 100644 index 000000000..b168d7742 --- /dev/null +++ b/basil/firmware/modules/utils/IOBUF.v @@ -0,0 +1,21 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`timescale 1ps/1ps +`default_nettype none + + +module IOBUF ( + inout wire IO, + input wire I, + output wire O, + input wire T +); + +assign IO = T ? I : 1'bz; +assign O = T ? IO : 1'b0; + +endmodule diff --git a/basil/firmware/modules/utils/OBUF.v b/basil/firmware/modules/utils/OBUF.v new file mode 100644 index 000000000..0b0d77a5b --- /dev/null +++ b/basil/firmware/modules/utils/OBUF.v @@ -0,0 +1,18 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`timescale 1ps/1ps +`default_nettype none + + +module OBUF ( + output wire O, + input wire I +); + +assign O = I; + +endmodule diff --git a/basil/firmware/modules/utils/OBUFDS_sim.v b/basil/firmware/modules/utils/OBUFDS.v similarity index 100% rename from basil/firmware/modules/utils/OBUFDS_sim.v rename to basil/firmware/modules/utils/OBUFDS.v diff --git a/basil/firmware/modules/utils/ODDR.v b/basil/firmware/modules/utils/ODDR.v new file mode 100644 index 000000000..a040c323e --- /dev/null +++ b/basil/firmware/modules/utils/ODDR.v @@ -0,0 +1,39 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`timescale 1ps/1ps +`default_nettype none + + +module ODDR #( + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", + parameter INIT = 1'b0, + parameter SRTYPE = "SYNC" +)( + output reg Q, + input wire C, + input wire CE, + input wire D1, + input wire D2, + input wire R, + input wire S +); + +always @(posedge C or negedge C) begin + if (R) begin + Q <= INIT; + end else if (CE) begin + if (DDR_CLK_EDGE == "OPPOSITE_EDGE") begin + if (C) Q <= D2; + else Q <= D1; + end else begin + if (C) Q <= D1; + else Q <= D2; + end + end +end + +endmodule diff --git a/basil/firmware/modules/utils/PLLE2_BASE.v b/basil/firmware/modules/utils/PLLE2_BASE.v new file mode 100644 index 000000000..3529e0644 --- /dev/null +++ b/basil/firmware/modules/utils/PLLE2_BASE.v @@ -0,0 +1,44 @@ +// Blackbox simulation model for PLLE2_BASE primitive +// Xilinx PLL base module +(* blackbox *) +module PLLE2_BASE #( + parameter BANDWIDTH = "OPTIMIZED", + parameter CLKFBOUT_MULT = 4, + parameter CLKFBOUT_PHASE = 0.0, + parameter CLKIN1_PERIOD = 0.0, + parameter DIVCLK_DIVIDE = 1, + parameter REF_JITTER1 = 0.0, + parameter STARTUP_WAIT = "FALSE", + parameter CLKOUT0_DIVIDE = 1, + parameter CLKOUT0_DUTY_CYCLE = 50.0, + parameter CLKOUT0_PHASE = 0.0, + parameter CLKOUT1_DIVIDE = 1, + parameter CLKOUT1_DUTY_CYCLE = 50.0, + parameter CLKOUT1_PHASE = 0.0, + parameter CLKOUT2_DIVIDE = 1, + parameter CLKOUT2_DUTY_CYCLE = 50.0, + parameter CLKOUT2_PHASE = 0.0, + parameter CLKOUT3_DIVIDE = 1, + parameter CLKOUT3_DUTY_CYCLE = 50.0, + parameter CLKOUT3_PHASE = 0.0, + parameter CLKOUT4_DIVIDE = 1, + parameter CLKOUT4_DUTY_CYCLE = 50.0, + parameter CLKOUT4_PHASE = 0.0, + parameter CLKOUT5_DIVIDE = 1, + parameter CLKOUT5_DUTY_CYCLE = 50.0, + parameter CLKOUT5_PHASE = 0.0 +)( + output wire CLKFBOUT, + output wire CLKOUT0, + output wire CLKOUT1, + output wire CLKOUT2, + output wire CLKOUT3, + output wire CLKOUT4, + output wire CLKOUT5, + output wire LOCKED, + input wire CLKIN1, + input wire PWRDWN, + input wire RST, + input wire CLKFBIN +); +endmodule From 24166e26dbb5fa328ada2032c7d25facf734f3f5 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 08:56:21 +0200 Subject: [PATCH 11/43] feat(fast_spi_rx): Add variable DATA_SIZE support with convenience methods - Add DATA_SIZE parameter to fast_spi_rx_core.v and fast_spi_rx.v - Frame counter width, SPI data width, and bit counter threshold all depend on DATA_SIZE - Add get_data_size() and parse_word() to Python driver for variable-width FIFO word parsing - Add FIFO_DATA register (addr 4, 32-bit) to register map - Fix minor whitespace/comment formatting in sitcp_fifo.py and seq_gen_core.v --- basil/HL/fast_spi_rx.py | 57 ++++++++++++++++++- basil/HL/sitcp_fifo.py | 3 +- .../modules/fast_spi_rx/fast_spi_rx.v | 6 +- .../modules/fast_spi_rx/fast_spi_rx_core.v | 18 +++--- basil/firmware/modules/seq_gen/seq_gen_core.v | 2 +- 5 files changed, 73 insertions(+), 13 deletions(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index a41a0a9b1..9076ef908 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -9,18 +9,38 @@ class fast_spi_rx(RegisterHardwareLayer): - """Fast SPI interface""" + """Fast SPI interface with variable data width support. + + The module outputs 32-bit words containing: + - IDENTIFIER (4 bits) + - Frame counter (28 - DATA_SIZE bits) + - SPI data (DATA_SIZE bits) + + The DATA_SIZE parameter must match the DATA_SIZE parameter used in the + FPGA firmware (fast_spi_rx_core.v). + """ _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, "VERSION": {"descr": {"addr": 0, "size": 8, "properties": ["ro"]}}, "EN": {"descr": {"addr": 2, "size": 1, "offset": 0}}, "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, + "FIFO_DATA": {"descr": {"addr": 4, "size": 32, "properties": ["ro"]}}, } _require_version = "==0" def __init__(self, intf, conf): super(fast_spi_rx, self).__init__(intf, conf) + # DATA_SIZE: number of bits for SPI data in the FIFO output + # Must match the DATA_SIZE parameter in the FPGA firmware + self._data_size = conf.get("DATA_SIZE", 16) # default 16 for backward compatibility + if self._data_size < 1 or self._data_size > 28: + raise ValueError("DATA_SIZE must be between 1 and 28") + + @property + def data_size(self): + """Return the configured DATA_SIZE.""" + return self._data_size def reset(self): """Soft reset the module.""" @@ -34,3 +54,38 @@ def get_en(self): def get_lost_count(self): return self.LOST_COUNT + + def get_data_size(self): + """Return the configured DATA_SIZE.""" + return self._data_size + + def parse_word(self, word): + """Parse a 32-bit FIFO word into (identifier, frame_counter, spi_data) tuples. + + Args: + word: A 32-bit integer from the FIFO. + + Returns: + tuple: (identifier, frame_counter, spi_data) + """ + identifier = (word >> 28) & 0xF + spi_data = word & ((1 << self._data_size) - 1) + frame_counter_bits = 28 - self._data_size + if frame_counter_bits > 0: + frame_counter = (word >> self._data_size) & ((1 << frame_counter_bits) - 1) + else: + frame_counter = 0 + return identifier, frame_counter, spi_data + + def get_parsed_data(self): + """Read and parse FIFO data into (frame_counter, spi_data).""" + word = self.FIFO_DATA # Uses register access, reads 4 bytes from addr 4 + if word is None: + return None, None + spi_data = word & ((1 << self._data_size) - 1) + frame_counter_bits = 28 - self._data_size + if frame_counter_bits > 0: + frame_counter = (word >> self._data_size) & ((1 << frame_counter_bits) - 1) + else: + frame_counter = 0 + return frame_counter, spi_data diff --git a/basil/HL/sitcp_fifo.py b/basil/HL/sitcp_fifo.py index 2a417f3bf..b230f01c3 100644 --- a/basil/HL/sitcp_fifo.py +++ b/basil/HL/sitcp_fifo.py @@ -21,6 +21,7 @@ class sitcp_fifo(HardwareLayer): _version = 0 + # Adding these registers via these magic methods is essentially a poor man's version of _registers dict def __getitem__(self, name): if name == "RESET": self._intf.reset() # returns None @@ -38,7 +39,7 @@ def __setitem__(self, name, value): super(sitcp_fifo, self).__setitem__(name, value) def __getattr__(self, name): - """called only on last resort if there are no attributes in the instance that match the name""" + """Called only as a last resort if there are no attributes in the instance that match the name""" if name.isupper(): return self[name] else: diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v index 585e553da..781cc43b8 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v @@ -20,7 +20,8 @@ module fast_spi_rx #( parameter HIGHADDR = 16'h0000, parameter ABUSWIDTH = 16, - parameter IDENTIFIER = 4'b0001 + parameter IDENTIFIER = 4'b0001, + parameter DATA_SIZE = 16 ) ( input wire BUS_CLK, input wire [ABUSWIDTH-1:0] BUS_ADD, @@ -63,7 +64,8 @@ bus_to_ip #( fast_spi_rx_core #( .ABUSWIDTH(ABUSWIDTH), - .IDENTIFIER(IDENTIFIER) + .IDENTIFIER(IDENTIFIER), + .DATA_SIZE(DATA_SIZE) ) i_fast_spi_rx_core ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index 565b8559f..b415a0559 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -17,7 +17,8 @@ module fast_spi_rx_core #( parameter ABUSWIDTH = 16, - parameter IDENTIFIER = 4'b0001 + parameter IDENTIFIER = 4'b0001, + parameter DATA_SIZE = 16 ) ( input wire SCLK, input wire SDI, @@ -38,7 +39,7 @@ module fast_spi_rx_core #( localparam VERSION = 0; -//output format #ID (as parameter IDENTIFIER + 12 id-frame + 16 bit data) +// Output format #ID (as parameter IDENTIFIER + 12 id-frame + 16 bit data) wire SOFT_RST; assign SOFT_RST = (BUS_ADD==0 && BUS_WR); @@ -75,6 +76,7 @@ end wire RST_SYNC; wire RST_SOFT_SYNC; +// Reset is syncrhonized by the sclk cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SCLK), .pulse_out(RST_SOFT_SYNC)); assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; @@ -92,7 +94,7 @@ end wire RST_LONG; assign RST_LONG = sync_cnt[7]; -reg [11:0] frame_cnt; +reg [27-DATA_SIZE:0] frame_cnt; wire SEN_START, SEN_FINISH; reg SEN_DLY; always @(posedge SCLK) begin @@ -120,16 +122,16 @@ always @(posedge SCLK) begin bit_cnt <= bit_cnt + 1; end -assign cdc_fifo_write = ( (bit_cnt == 15) || SEN_FINISH ) && CONF_EN_SYNC; +assign cdc_fifo_write = ( (bit_cnt == DATA_SIZE - 1) || SEN_FINISH ) && CONF_EN_SYNC; -reg [15:0] spi_data; +reg [DATA_SIZE-1:0] spi_data; always @(posedge SCLK) begin if(RST_SYNC | SEN_FINISH) spi_data <= 0; else if(cdc_fifo_write) - spi_data <= {15'b0, SDI}; + spi_data <= {DATA_SIZE-1'b0, SDI}; else if(SEN) - spi_data <= {spi_data[14:0], SDI}; + spi_data <= {spi_data[DATA_SIZE-2:0], SDI}; end wire fifo_full,cdc_fifo_empty; @@ -143,7 +145,7 @@ always @(posedge SCLK) begin end wire [31:0] cdc_data; -assign cdc_data = {IDENTIFIER, frame_cnt[11:0], spi_data}; +assign cdc_data = {IDENTIFIER, frame_cnt[27-DATA_SIZE:0], spi_data}; wire [31:0] cdc_data_out; cdc_syncfifo #( diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index 5fae307eb..603ba05ea 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -217,7 +217,7 @@ wire RST_SOFT_SYNC; cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SEQ_CLK), .pulse_out(RST_SOFT_SYNC)); assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; -wire START_SYNC_CDC; +wire START_SYNC_CDC; wire START_SYNC; cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SEQ_CLK), .pulse_out(START_SYNC_CDC)); From a14cb2b66d67649069a849cdddbec6afbaf4268e Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:17 +0200 Subject: [PATCH 12/43] docs(fast_spi_rx): Add comprehensive docstrings to all methods Document set_en/get_en, get_lost_count, set_size/get_size, parse_word, and improve existing reset docstring with reset behavior details. --- basil/HL/fast_spi_rx.py | 56 +++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index 9076ef908..b3ee7f613 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -18,6 +18,10 @@ class fast_spi_rx(RegisterHardwareLayer): The DATA_SIZE parameter must match the DATA_SIZE parameter used in the FPGA firmware (fast_spi_rx_core.v). + + Captured data is read via the dedicated FIFO output ports (not the register + bus). At the system level, these feed into a SiTCP FIFO stream accessed + through daq["fifo0"].get_data(). """ _registers = { @@ -25,7 +29,6 @@ class fast_spi_rx(RegisterHardwareLayer): "VERSION": {"descr": {"addr": 0, "size": 8, "properties": ["ro"]}}, "EN": {"descr": {"addr": 2, "size": 1, "offset": 0}}, "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, - "FIFO_DATA": {"descr": {"addr": 4, "size": 32, "properties": ["ro"]}}, } _require_version = "==0" @@ -37,55 +40,54 @@ def __init__(self, intf, conf): if self._data_size < 1 or self._data_size > 28: raise ValueError("DATA_SIZE must be between 1 and 28") - @property - def data_size(self): - """Return the configured DATA_SIZE.""" + def set_size(self, value): + """Set the Python-only DATA_SIZE attribute tracking the SPI data width in bits. + + Must match the DATA_SIZE parameter set in the FPGA firmware (fast_spi_rx_core.v). + Valid range: 1-28. + """ + if value < 1 or value > 28: + raise ValueError("DATA_SIZE must be between 1 and 28") + self._data_size = value + + def get_size(self): + """Return the DATA_SIZE (SPI data width in bits) used for parsing captured words.""" return self._data_size def reset(self): - """Soft reset the module.""" + """Soft reset the module. Clears internal counters and shift registers on the next SEQ_CLK edge.""" self.RESET = 0 def set_en(self, value): + """Arm/disarm capture. When enabled, serial data on SDI is captured on each rising edge of SEQ_CLK while SEN is high.""" self.EN = value def get_en(self): + """Return whether capture is armed (True) or disarmed (False).""" return self.EN def get_lost_count(self): + """Return the count of lost data words due to CDC FIFO overflow. Non-zero indicates the capture rate exceeded the readout rate.""" return self.LOST_COUNT - def get_data_size(self): - """Return the configured DATA_SIZE.""" - return self._data_size - def parse_word(self, word): - """Parse a 32-bit FIFO word into (identifier, frame_counter, spi_data) tuples. + """Parse a 32-bit FIFO word into (identifier, frame_counter, spi_data). + + The split between frame counter and captured data is determined + by get_size(). Useful for parsing words read via daq["fifo0"].get_data(). Args: - word: A 32-bit integer from the FIFO. + word: A 32-bit integer from the fast_spi_rx output FIFO. Returns: tuple: (identifier, frame_counter, spi_data) """ + data_size = self.get_size() identifier = (word >> 28) & 0xF - spi_data = word & ((1 << self._data_size) - 1) - frame_counter_bits = 28 - self._data_size + spi_data = word & ((1 << data_size) - 1) + frame_counter_bits = 28 - data_size if frame_counter_bits > 0: - frame_counter = (word >> self._data_size) & ((1 << frame_counter_bits) - 1) + frame_counter = (word >> data_size) & ((1 << frame_counter_bits) - 1) else: frame_counter = 0 return identifier, frame_counter, spi_data - - def get_parsed_data(self): - """Read and parse FIFO data into (frame_counter, spi_data).""" - word = self.FIFO_DATA # Uses register access, reads 4 bytes from addr 4 - if word is None: - return None, None - spi_data = word & ((1 << self._data_size) - 1) - frame_counter_bits = 28 - self._data_size - if frame_counter_bits > 0: - frame_counter = (word >> self._data_size) & ((1 << frame_counter_bits) - 1) - else: - frame_counter = 0 - return frame_counter, spi_data From 90fdc824a05e894e2147fce8469d33832b0ab4c1 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:22 +0200 Subject: [PATCH 13/43] docs(gpio): Document set_output_en, get_output_en, set_data, get_data Explain output enable mask, IO_TRI requirement, and StdRegister usage. --- basil/HL/gpio.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/basil/HL/gpio.py b/basil/HL/gpio.py index 17222415b..8d563fc9c 100644 --- a/basil/HL/gpio.py +++ b/basil/HL/gpio.py @@ -44,13 +44,17 @@ def reset(self): self.RESET = 0 def set_output_en(self, value): + """Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" self.OUTPUT_EN = value def get_output_en(self): + """Return the output enable mask. Each bit indicates whether the corresponding pin is in output mode (1) or input mode (0).""" return self.OUTPUT_EN def set_data(self, value): + """Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" self.OUTPUT = value def get_data(self): + """Read the GPIO INPUT register. Returns the current logic levels on all pins as a byte array. Reads the physical pin state regardless of direction configuration.""" return self.INPUT From 77629b58cf68a4c621679f667e73818292cd14ba Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:27 +0200 Subject: [PATCH 14/43] docs(pulse_gen): Document is_ready, get_width, set_delay, reset, set_repeat, get_repeat, is_done Clarify delay is in clock cycles, explain @property decorator and relationship between is_ready and is_done. --- basil/HL/pulse_gen.py | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/basil/HL/pulse_gen.py b/basil/HL/pulse_gen.py index 7ef0035d4..5ed8b771d 100644 --- a/basil/HL/pulse_gen.py +++ b/basil/HL/pulse_gen.py @@ -9,7 +9,7 @@ class pulse_gen(RegisterHardwareLayer): - """Pulser generator""" + """Pulse generator""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -33,15 +33,18 @@ def start(self): self.START = 0 def reset(self): + """Soft reset the pulse generator. Clears internal state on the next clock edge.""" self.RESET = 0 def set_delay(self, value): """ - Pulse delay w.r.t. shift register finish signal [in clock cycles(?)] + Set the pulse delay in clock cycles from start. + The delay is relative to the start trigger (software .start() or EXT_START pin). """ self.DELAY = value def get_delay(self): + """Return the pulse delay in clock cycles.""" return self.DELAY def set_width(self, value): @@ -51,22 +54,32 @@ def set_width(self, value): self.WIDTH = value def get_width(self): + """Return the pulse width in clock cycles.""" return self.WIDTH def set_repeat(self, value): - """ - Pulse repetition in range of 0-255 - """ + """Set the repeat count. 0 = repeat forever. The pulse repeats with the configured DELAY and WIDTH each time. Max 255.""" self.REPEAT = value def get_repeat(self): + """Return the repeat count.""" return self.REPEAT def is_done(self): + """Return True if the pulse generator has finished all repetitions, False if still active. Alias of is_ready.""" return self.is_ready @property def is_ready(self): + """Read the READY register (addr 1, bit 0). Returns True when the pulse generator + is idle and ready to accept a new start trigger. While the pulse is running + (including all configured repetitions) this reads False. + + The `@property` decorator makes this an attribute-like access — call it + without parentheses as ``daq["pulse0"].is_ready``, not ``.is_ready()``. + + `.is_done()` is an alias that returns the same value. + """ return self.READY def set_en(self, value): From ae1d045fda265f27ba91abcdf9427aa30cdac3f2 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:33 +0200 Subject: [PATCH 15/43] docs(seq_gen): Add docstrings to all 22 methods and properties Document all registers, start/reset behavior, repeat mode (0=forever), external start, nested loops, and property/alias relationships. --- basil/HL/seq_gen.py | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index 33860ef1b..4dd065c3f 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -9,7 +9,7 @@ class seq_gen(RegisterHardwareLayer): - """Sequencer generator controller interface for seq_gen FPGA module.""" + """Sequence generator controller interface for seq_gen FPGA module.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -38,70 +38,98 @@ def init(self): self._seq_mem_size = self.get_mem_size() def reset(self): + """Soft reset the sequencer. Clears internal counters and output state on the next clock edge. Must have a rising edge on the sequencer clock before new data is written to memory.""" self.RESET = 0 def start(self): + """Start the sequencer. Writes to the START register (addr 1). The sequence begins on the next SEQ_CLK edge after the write. Only effective when DONE/READY is high (sequence not already running).""" self.START = 0 def set_size(self, value): + """Set the number of output words in the sequence. Each word contains OUT_BITS (one sample per track). Addresses 4-7.""" self.SIZE = value def get_size(self): + """Return the configured sequence size in output words.""" return self.SIZE def set_wait(self, value): + """Set wait cycles inserted between repetitions. Only applies when REPEAT > 0. Addresses 8-11.""" self.WAIT = value def get_wait(self): + """Return the configured wait cycles between repetitions.""" return self.WAIT def set_clk_divide(self, value): + """Set the clock division factor for SEQ_CLK. The sequencer advances one step every CLK_DIV + 1 clock cycles. Default: 1 (divide by 1, i.e. full rate). Address 3.""" self.CLK_DIV = value def get_clk_divide(self): + """Return the clock division factor.""" return self.CLK_DIV def set_repeat_start(self, value): + """Set the repeat start position. When repeating, the sequence jumps to this position instead of starting from 0. Addresses 16-19.""" self.REPEAT_START = value def get_repeat_start(self): + """Return the repeat start position.""" return self.REPEAT_START def set_repeat(self, value): + """Set the repeat count. 0 = repeat forever. The sequence repeats from REP_START (or 0) each time. Addresses 12-15.""" self.REPEAT = value def get_repeat(self): + """Return the repeat count.""" return self.REPEAT def is_done(self): + """Return True if the sequencer has finished its sequence (including all repeats), False if running. Aliases is_ready.""" return self.is_ready @property def is_ready(self): + """Read the DONE/READY register (addr 1, bit 0). Returns True when the sequencer + is idle and ready to accept a new start trigger. While the sequence is running + (including all configured repetitions) this reads False. + + The ``@property`` decorator makes this an attribute-like access — call it + without parentheses as ``daq["seq0"].is_ready``, not ``.is_ready()``. + + ``.is_done()`` and ``.get_done()`` are aliases that return the same value. + """ return self.READY def get_done(self): + """Alias for is_ready. Returns True if sequencer is finished.""" return self.is_ready def set_en_ext_start(self, value): + """Enable or disable external start via the SEQ_EXT_START pin. When enabled (1), the SEQ_EXT_START pin rising edge triggers the sequence. When disabled (0), only software .start() works. Address 2.""" self.EN_EXT_START = value def get_en_ext_start(self): + """Return whether external start is enabled.""" return self.EN_EXT_START def set_nested_start(self, value): + """Set the nested loop start position. Addresses 20-23.""" self.NESTED_START = value def get_nested_start(self): return self.NESTED_START def set_nested_stop(self, value): + """Set the nested loop stop position. Addresses 24-27.""" self.NESTED_STOP = value def get_nested_stop(self): return self.NESTED_STOP def set_nested_repeat(self, value): + """Set the nested loop repeat count. 0 = disabled. Addresses 28-31.""" self.NESTED_REPEAT = value def get_nested_repeat(self): @@ -111,6 +139,7 @@ def get_mem_size(self): return self.MEM_BYTES def set_data(self, data, addr=0): + """Write sequencer memory (the pattern data) via the bus interface at the memory offset. Data is interleaved per track by the TrackRegister RL. Args are bytes to write and optional byte address offset.""" if self._seq_mem_size < len(data): raise ValueError( "Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._seq_mem_size) @@ -118,6 +147,7 @@ def set_data(self, data, addr=0): self._intf.write(self._conf["base_addr"] + self._seq_mem_offset + addr, data) def get_data(self, size=None, addr=0): + """Read sequencer memory (the pattern data) via the bus interface. Returns bytes. Args are number of bytes to read and optional byte address offset.""" if size and self._seq_mem_size < size: raise ValueError("Size is too big") if not size: From d70badf58ccef9a01b019b805599ad4fd51a4750 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:37 +0200 Subject: [PATCH 16/43] docs(spi): Document get_mem_size, is_ready, is_done, improve set_data, get_data, reset Document READY register, memory size, and clarify reset aborts transfers. --- basil/HL/spi.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/basil/HL/spi.py b/basil/HL/spi.py index 02fe7336e..6deae6da8 100644 --- a/basil/HL/spi.py +++ b/basil/HL/spi.py @@ -33,7 +33,7 @@ def init(self): self._mem_bytes = self.MEM_BYTES def reset(self): - """Soft reset the module.""" + """Soft reset the SPI module. Aborts any in-progress transfer, clears internal state.""" self.RESET = 0 def start(self): @@ -94,20 +94,23 @@ def get_en(self): def is_done(self): """ - Get the status of transfer/sequence. + Return True if the SPI transfer is complete, False if still in progress. Aliases is_ready. """ return self.is_ready @property def is_ready(self): + """Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" return self.READY def get_mem_size(self): + """Return the SPI memory size in bytes (from MEM_BYTES register at address 14-15). This is the maximum single transfer size.""" return self.MEM_BYTES def set_data(self, data, addr=0): """ - Sets data for outgoing stream + Write data to the SPI transmit memory at the bus memory offset. Data bytes are shifted out MSB-first on SDI. + Args: data (bytes), addr (int, optional byte offset into memory). """ if self._mem_bytes < len(data): raise ValueError("Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._mem_bytes)) @@ -116,7 +119,8 @@ def set_data(self, data, addr=0): # This needs to be changed to return written value def get_data(self, size=None, addr=None): """ - Gets data for incoming stream + Read data from the SPI receive memory at the bus memory offset. Incoming bytes captured from SDO are stored here. + Args: size (int, number of bytes to read, default all), addr (int, optional byte offset). """ # readback memory offset if addr is None: From 007e63b2746210addaa6e5714405599e0dce9848 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:42 +0200 Subject: [PATCH 17/43] docs(fast_spi_rx): Rewrite README with consistent format and usage notes Add unit test placeholder, usage notes (data format, FIFO flush, reset), and standardize section order to match seq_gen/spi/gpio/pulse_gen. --- basil/firmware/modules/fast_spi_rx/README.rst | 80 ++++++++++++++++++- 1 file changed, 76 insertions(+), 4 deletions(-) diff --git a/basil/firmware/modules/fast_spi_rx/README.rst b/basil/firmware/modules/fast_spi_rx/README.rst index 160ec45e5..479968bbd 100644 --- a/basil/firmware/modules/fast_spi_rx/README.rst +++ b/basil/firmware/modules/fast_spi_rx/README.rst @@ -1,6 +1,78 @@ +======================================== +**fast_spi_rx** - Fast serial receiver +======================================== -===================================== -**fast_spi_rx** - Fast SPI receiver -===================================== +This module can continuous capture serial data on each rising edge of it's capture clock. +Received data is packed into 32-bit words and propagated to a FIFO data interface. +While originally intended for SPI (hence the naming), it can be used for any serial data. -Allows continuous serial data receive. Received data are propagated to FIFO data interface. +**Unit tests** + +Unit tests for this module have not yet been implemented. + +**Usage notes** + +* **Data output format**: Each 32-bit FIFO word is formatted as + ``[31:28] IDENTIFIER, [27:N] Frame counter, [N-1:0] Captured data`` + where ``N = DATA_SIZE``. The IDENTIFIER field differentiates multiple + fast_spi_rx instances merged into the same downstream FIFO stream. + The frame counter increments on every SEN falling edge, allowing + reconstruction of multi-word captures. When a capture spans multiple + FIFO words, all words carry the same frame counter value. +* **FIFO flush behavior**: A FIFO word is written when DATA_SIZE bits have + been captured, or when SEN falls (flushing any partially-filled word). + An incomplete frame is never lost — it is always written to the FIFO + when SEN goes low. +* **Reset**: The soft reset (RESET register write or BUS_RST) is + synchronised to SEQ_CLK via a CDC synchroniser. At least one rising + edge of SEQ_CLK must occur after reset is released for it to take + effect. If SEQ_CLK is not running when reset is asserted, the reset + will not complete. + +Parameters +---------- + +--------------+---------------------+-----------------------------------------------------------------+ + | Name | Default | Description | + +==============+=====================+=================================================================+ + | ABUSWIDTH | 16 | Width of the bus address bus | + +--------------+---------------------+-----------------------------------------------------------------+ + | IDENTIFIER | 4'b0001 | Instance identifier packed into bits [31:28] of each FIFO word | + +--------------+---------------------+-----------------------------------------------------------------+ + | DATA_SIZE | 16 | Number of serial data bits packed into a single FIFO word | + +--------------+---------------------+-----------------------------------------------------------------+ + +Pins +---- + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | Name | Size | Direction | Description | + +===============+=====================+=======================+======================================================+ + | SEQ_CLK | 1 | input | Capture clock (serial data sampled on rising edge) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | SDI | 1 | input | Serial data input (sampled on SEQ_CLK rising edge) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | SEN | 1 | input | Serial enable (active high, frames the capture) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | FIFO_READ | 1 | input | Read strobe (pop one word from the output FIFO) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | FIFO_EMPTY | 1 | output | FIFO empty flag | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + | FIFO_DATA | 32 | output | FIFO data output (32-bit word) | + +---------------+---------------------+-----------------------+------------------------------------------------------+ + +Registers +--------- + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | Name | Address | Bits | r/w | Default | Description | + +===============+=====================+========+=======+=============+==================================================================+ + | RESET | 0 | | wo | | Soft reset (synchronous to SEQ_CLK, takes effect on next edge) | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | VERSION | 0 | [7:0] | ro | | Firmware version | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | EN | 2 | [0] | r/w | 0 | Enable capture (set high to arm) | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + | LOST_COUNT | 3 | [7:0] | ro | 0 | Lost data counter (incremented on CDC FIFO overflow) | + +---------------+---------------------+--------+-------+-------------+------------------------------------------------------------------+ + +**Unit tests** + +Unit tests for this module have not yet been implemented. From cc81ab3e346c6c93954a94dce5ac984533351501 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:48 +0200 Subject: [PATCH 18/43] docs(seq_gen): Add usage notes, fix typos, capitalize descriptions Add operational notes on tracks, start/repeat modes, output hold, and START/READY address aliasing. Fix 'friving' typo. --- basil/firmware/modules/seq_gen/README.rst | 55 ++++++++++++++++------- 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/basil/firmware/modules/seq_gen/README.rst b/basil/firmware/modules/seq_gen/README.rst index 1a0497f30..f5af8e2a6 100644 --- a/basil/firmware/modules/seq_gen/README.rst +++ b/basil/firmware/modules/seq_gen/README.rst @@ -3,13 +3,32 @@ **seq_gen** - Pattern generator ================================ -Module implements a simple sequencer/pattern generator base on block ram. Supports 2 levels of internal loops and external start. -For OUT_BITS != 8 user need to provide block memory module (seq_gen_blk_mem) with proper size. +Module implements a simple sequencer/pattern generator based on block ram. Supports 2 levels of internal loops and external start. **Unit test/Example:** `test_SimSeq.v `_ `test_SimSeq.py `_ +**Usage notes** + +* **Tracks**: The seq_gen supports OUT_BITS from 1 to at least 256. Each output bit + is a separate track. To fill track data in software, instantiate a + `TrackRegister` in the basil configuration YAML. This provides named track + access like ``daq["seq0"]["INIT"][0:40] = bitarray("...")``. +* **Start**: The sequence can be started via a write to the `START` register + (software start), or via the `SEQ_EXT_START` pin with `EN_EXT_START` set + (external start). The external start is typically driven by a GPIO or + pulse_gen output. +* **Repeat mode**: A value of 0 in the `REPEAT` register causes the sequence to + repeat forever (until reset or reconfiguration). +* **Output hold**: When the sequence finishes or stops, the last output state + is held on `SEQ_OUT` — it does not return to zero. The sequencer does not + reset its outputs on completion. +* **START and READY share the same address**: The `START` (write-only) and + `DONE` (read-only) registers are aliased at the same address. Writing to + address 1 triggers a start, reading address 1 returns the done flag. + This pattern is consistent across seq_gen, spi, and pulse_gen. + **Parameters:** +--------------+---------------------+-------------------------------------------------------------------------+ | Name | Default | Description | @@ -25,7 +44,7 @@ For OUT_BITS != 8 user need to provide block memory module (seq_gen_blk_mem) wit +===============+=====================+=======================+======================================================+ | SEQ_EXT_START | 1 | input | external start signal (synchronous to SEQ_CLK) | +---------------+---------------------+-----------------------+------------------------------------------------------+ - | SEQ_CLK | 1 | input | external clock used for friving sequence | + | SEQ_CLK | 1 | input | external clock used for driving sequence | +---------------+---------------------+-----------------------+------------------------------------------------------+ | SEQ_OUT | OUT_BITS | output | sequencer output | +---------------+---------------------+-----------------------+------------------------------------------------------+ @@ -34,29 +53,33 @@ For OUT_BITS != 8 user need to provide block memory module (seq_gen_blk_mem) wit +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +===============+==================================+========+=======+=============+============================================================================================+ - | START | 1 | | wo | | start transfer on write to address | + | RESET | 0 | | wo | | Soft reset on write | + +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ + | VERSION | 0 | [7:0] | ro | | Firmware version | + +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ + | START | 1 | | wo | | Start sequence on write | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DONE | 1 | [0] | ro | 0 | indicate transfer finish | + | DONE | 1 | [0] | ro | 0 | Indicates sequence finished | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | EN_EXT_START | 2 | [0] | r/w | 0 | enable external start | + | EN_EXT_START | 2 | [0] | r/w | 0 | Enable external start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | CLK_DIV | 3 | [7:0] | r/w | 1 | internal division factor for SEQ_CLK | + | CLK_DIV | 3 | [7:0] | r/w | 1 | Internal division factor for SEQ_CLK | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | COUNT | 7 - 4 | [31:0] | r/w | out_words | set the size of sequence (in output words) | + | SIZE | 7 - 4 | [31:0] | r/w | out_words | Set the size of sequence (in output words) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | WAIT | 11 - 8 | [31:0] | r/w | 0 | waits after every sequence if REPEAT != 0 repeat transfer count (0 -> forever) | + | WAIT | 11 - 8 | [31:0] | r/w | 0 | Waits after every sequence if REPEAT != 0 (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REPEAT | 15 - 12 | [31:0] | r/w | 1 | repeat sequence count (0 -> forever) | + | REPEAT | 15 - 12 | [31:0] | r/w | 1 | Repeat sequence count (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REP_START | 19 - 16 | [31:0] | r/w | 0 | position from which pattern will start in repeat mode (a first sequence always start at 0) | + | REP_START | 19 - 16 | [31:0] | r/w | 0 | Position from which pattern will start in repeat mode (first sequence always starts at 0) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_START | 23 - 20 | [31:0] | r/w | 0 | position from which pattern will start for nested loop | + | NESTED_START | 23 - 20 | [31:0] | r/w | 0 | Position from which pattern will start for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_STOP | 27 - 24 | [31:0] | r/w | 0 | position to which pattern will stop for nested loop | + | NESTED_STOP | 27 - 24 | [31:0] | r/w | 0 | Position to which pattern will stop for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_REPEAT | 31 - 28 | [31:0] | r/w | 0 | repeat count for nested loop | + | NESTED_REPEAT | 31 - 28 | [31:0] | r/w | 0 | Repeat count for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | MEM_BYTES | 35 - 32 | [31:0] | r/w | MEM_BYTE | memory size | + | MEM_BYTES | 35 - 32 | [31:0] | ro | MEM_BYTES | Memory size (read only) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DATA | 64 to 64+MEM_BYTES-1 | | r/w | unknown | memory for pattern | + | DATA | 64 to 64+MEM_BYTES-1 | | r/w | unknown | Memory for pattern | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ From 281377c5f1bc3847aeb0d1cf18c251ebcf431831 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:52 +0200 Subject: [PATCH 19/43] docs(spi): Add usage notes, fix register names, capitalize descriptions Rename BIT_OUT to SIZE, CONF_EN to EN. Add notes on external start, repeat mode, and START/DONE address aliasing. --- basil/firmware/modules/spi/README.rst | 29 ++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/basil/firmware/modules/spi/README.rst b/basil/firmware/modules/spi/README.rst index e8f888be3..3845a0cb2 100644 --- a/basil/firmware/modules/spi/README.rst +++ b/basil/firmware/modules/spi/README.rst @@ -9,6 +9,17 @@ Module implements master serial peripheral interface. Supports simple internal l `test_SimSpi.v `_ `test_SimSpi.py `_ +**Usage notes** + +* **External start**: When `EN` is set, the SPI transfer can be triggered via + the `EXT_START` pin instead of a software write to `START`. +* **Repeat mode**: A value of 0 in the `REPEAT` register causes the transfer + to repeat forever. +* **START and DONE share the same address**: The `START` (write-only) and + `DONE` (read-only) registers are aliased at the same address. Writing to + address 1 triggers a start, reading address 1 returns the done flag. + This pattern is consistent across seq_gen, spi, and pulse_gen. + **Parameters:** +--------------+---------------------+------------------------------------------------------------------------+ | Name | Default | Description | @@ -39,21 +50,21 @@ Module implements master serial peripheral interface. Supports simple internal l +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +==============+==================================+========+=======+=============+=============================================+ - | START | 1 | | wo | | start transfer on write to address | + | START | 1 | | wo | | Start transfer on write to address | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DONE | 1 | [0] | ro | 0 | indicate transfer finish | + | DONE | 1 | [0] | ro | 0 | Indicate transfer finish | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | BIT_OUT | 4 - 3 | [15:0] | r/w | MEM_BYTES*8 | set the size of transfer in bits | + | SIZE | 4 - 3 | [15:0] | r/w | MEM_BYTES*8 | Set the size of transfer in bits | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | WAIT | 8 - 5 | [31:0] | r/w | 4 | waits after every transfer if REPEAT != 0 | + | WAIT | 8 - 5 | [31:0] | r/w | 4 | Waits after every transfer if REPEAT != 0 | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | REPEAT | 12 - 9 | [31:0] | r/w | 1 | repeat transfer count (0 -> forever) | + | REPEAT | 12 - 9 | [31:0] | r/w | 1 | Repeat transfer count (0 -> forever) | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | CONF_EN | 13 | [0] | r/w | 0 | enable external start (0-> soft start only) | + | EN | 13 | [0] | r/w | 0 | Enable external start (0 -> soft start only)| +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | MEM_BYTES | 15 - 14 | [15:0] | ro | MEM_BYTES | byte size of memory | + | MEM_BYTES | 15 - 14 | [15:0] | ro | MEM_BYTES | Byte size of memory | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DATA_OUT | 16 to 16+MEM_BYTES-1 | | r/w | unknown | memory for outgoing data | + | DATA_OUT | 16 to 16+MEM_BYTES-1 | | r/w | unknown | Memory for outgoing data | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DATA_IN | 16+MEM_BYTES to 16+2*MEM_BYTES-1 | | r/w | unknown | memory for incoming data | + | DATA_IN | 16+MEM_BYTES to 16+2*MEM_BYTES-1 | | r/w | unknown | Memory for incoming data | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ From f736bcf10a99f4811618850804ee1976caf82b21 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:53:56 +0200 Subject: [PATCH 20/43] docs(gpio): Add StdRegister usage notes, capitalize descriptions Document StdRegister field-level access and pin direction behavior. --- basil/firmware/modules/gpio/README.rst | 33 +++++++++++++++++--------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/basil/firmware/modules/gpio/README.rst b/basil/firmware/modules/gpio/README.rst index 0a6092118..8815d6619 100644 --- a/basil/firmware/modules/gpio/README.rst +++ b/basil/firmware/modules/gpio/README.rst @@ -9,6 +9,17 @@ General purpose input output (gpio) is a generic pins whose behavior, including `test_SimGpio.v `_ `test_SimGpio.py `_ +**Usage notes** + +* **StdRegister usage**: Rather than reading/writing the raw `INPUT` and + `OUTPUT` bytes directly, instantiate a `StdRegister` in the basil + configuration YAML with named fields for each GPIO bit. This provides + access like ``daq["gpio0"]["RST_B"] = 1`` followed by `.write()` to push + the full byte to hardware. +* **Direction**: Each pin's direction is set by `IO_DIRECTION` at compile + time. Runtime direction changes via the `DIRECTION` register require + `IO_TRI` to be enabled for the corresponding pin. + **Parameters:** +--------------+---------------------+-----------------------------------------------------------------+ | Name | Default | Description | @@ -28,16 +39,16 @@ General purpose input output (gpio) is a generic pins whose behavior, including +--------------+---------------------+-----------------------------------------------------------------+ **Registers:** - +------------+---------------------+----------------------------------------+ - | Name | Address | Description | - +============+=====================+========================================+ - | RESET | 0 | Soft reset active on write to address | - +------------+---------------------+----------------------------------------+ - | INPUT | 1 to BYTE | Readback of state of pin | - +------------+---------------------+----------------------------------------+ - | OUTPUT | 1+BYTE to 2*BYTE | Set output state on pin | - +------------+---------------------+----------------------------------------+ - | DIRECTION | 1+2*BYTE to 3*BYTE | Tri-state pin (if enabled) | - +------------+---------------------+----------------------------------------+ + +------------+---------------------+-------------------------------------------------------+ + | Name | Address | Description | + +============+=====================+=======================================================+ + | RESET | 0 | Soft reset active on write to address | + +------------+---------------------+-------------------------------------------------------+ + | INPUT | 1 to BYTE | Readback of state of pin | + +------------+---------------------+-------------------------------------------------------+ + | OUTPUT | 1+BYTE to 2*BYTE | Set output state on pin | + +------------+---------------------+-------------------------------------------------------+ + | DIRECTION | 1+2*BYTE to 3*BYTE | Tri-state pin (if enabled) | + +------------+---------------------+-------------------------------------------------------+ Where: BYTE = IO_WIDTH/8+1 From 2e9b603497c5457b5973164970b41554b27af363 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:54:01 +0200 Subject: [PATCH 21/43] docs(pulse_gen): Add usage notes, capitalize descriptions, fix REPEAT address Add notes on start/repeat modes and START/READY address aliasing. --- basil/firmware/modules/pulse_gen/README.rst | 23 +++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/basil/firmware/modules/pulse_gen/README.rst b/basil/firmware/modules/pulse_gen/README.rst index 0c7c3b112..7f423ccec 100644 --- a/basil/firmware/modules/pulse_gen/README.rst +++ b/basil/firmware/modules/pulse_gen/README.rst @@ -9,6 +9,17 @@ Simple pulse generator with configurable delay and width. `test_SimSeq.v `_ `test_SimSeq.py `_ +**Usage notes** + +* **Start**: The pulse can be started via a write to the `START` register + (software start), or via the `EXT_START` pin with `EN` set (external start). +* **Repeat mode**: A value of 0 in the `REPEAT` register causes the pulse to + repeat forever. +* **START and READY share the same address**: The `START` (write-only) and + `READY` (read-only) registers are aliased at the same address. Writing to + address 1 triggers a start, reading address 1 returns the ready flag. + This pattern is consistent across seq_gen, spi, and pulse_gen. + **Pins:** +---------------+---------------------+-----------------------+------------------------------------------------------+ | Name | Size | Direction | Description | @@ -24,15 +35,15 @@ Simple pulse generator with configurable delay and width. +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +===============+==================================+========+=======+=============+============================================================================================+ - | START | 1 | | wo | | software start on write to address | + | START | 1 | | wo | | Software start on write to address | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | READY | 1 | [0] | ro | 0 | indicate finish | + | READY | 1 | [0] | ro | 0 | Indicate finish | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | EN | 2 | [0] | r/w | 0 | enable external start | + | EN | 2 | [0] | r/w | 0 | Enable external start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DELAY | 6 - 3 | [31:0] | r/w | 0 | pulse delay from start | + | DELAY | 6 - 3 | [31:0] | r/w | 0 | Pulse delay from start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | WIDTH | 10 - 7 | [31:0] | r/w | 0 | pulse width | + | WIDTH | 10 - 7 | [31:0] | r/w | 0 | Pulse width | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REPEAT | 11 - 14 | [31:0] | r/w | 1 | repeat count (0 ->forever) | + | REPEAT | 14 - 11 | [31:0] | r/w | 1 | Repeat count (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ From a1f06755b1118e76d35d8019d010a862614c412c Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 16:54:33 +0200 Subject: [PATCH 22/43] fix(docs): Use double backticks for register names in READMEs In RST, single backticks render as italics, not monospace. Switch all register/pin names to double backticks (START, DONE, READY, EN, etc.) so they render as code font. --- basil/firmware/modules/gpio/README.rst | 2 +- basil/firmware/modules/pulse_gen/README.rst | 10 +++++----- basil/firmware/modules/seq_gen/README.rst | 14 +++++++------- basil/firmware/modules/spi/README.rst | 10 +++++----- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/basil/firmware/modules/gpio/README.rst b/basil/firmware/modules/gpio/README.rst index 8815d6619..bb594a90c 100644 --- a/basil/firmware/modules/gpio/README.rst +++ b/basil/firmware/modules/gpio/README.rst @@ -12,7 +12,7 @@ General purpose input output (gpio) is a generic pins whose behavior, including **Usage notes** * **StdRegister usage**: Rather than reading/writing the raw `INPUT` and - `OUTPUT` bytes directly, instantiate a `StdRegister` in the basil + `OUTPUT` bytes directly, instantiate a ``StdRegister`` in the basil configuration YAML with named fields for each GPIO bit. This provides access like ``daq["gpio0"]["RST_B"] = 1`` followed by `.write()` to push the full byte to hardware. diff --git a/basil/firmware/modules/pulse_gen/README.rst b/basil/firmware/modules/pulse_gen/README.rst index 7f423ccec..1755ba4ed 100644 --- a/basil/firmware/modules/pulse_gen/README.rst +++ b/basil/firmware/modules/pulse_gen/README.rst @@ -11,12 +11,12 @@ Simple pulse generator with configurable delay and width. **Usage notes** -* **Start**: The pulse can be started via a write to the `START` register - (software start), or via the `EXT_START` pin with `EN` set (external start). -* **Repeat mode**: A value of 0 in the `REPEAT` register causes the pulse to +* **Start**: The pulse can be started via a write to the ``START`` register + (software start), or via the ``EXT_START`` pin with ``EN`` set (external start). +* **Repeat mode**: A value of 0 in the ``REPEAT`` register causes the pulse to repeat forever. -* **START and READY share the same address**: The `START` (write-only) and - `READY` (read-only) registers are aliased at the same address. Writing to +* **START and READY share the same address**: The ``START`` (write-only) and + ``READY`` (read-only) registers are aliased at the same address. Writing to address 1 triggers a start, reading address 1 returns the ready flag. This pattern is consistent across seq_gen, spi, and pulse_gen. diff --git a/basil/firmware/modules/seq_gen/README.rst b/basil/firmware/modules/seq_gen/README.rst index f5af8e2a6..46546abb9 100644 --- a/basil/firmware/modules/seq_gen/README.rst +++ b/basil/firmware/modules/seq_gen/README.rst @@ -13,19 +13,19 @@ Module implements a simple sequencer/pattern generator based on block ram. Suppo * **Tracks**: The seq_gen supports OUT_BITS from 1 to at least 256. Each output bit is a separate track. To fill track data in software, instantiate a - `TrackRegister` in the basil configuration YAML. This provides named track + ``TrackRegister`` in the basil configuration YAML. This provides named track access like ``daq["seq0"]["INIT"][0:40] = bitarray("...")``. -* **Start**: The sequence can be started via a write to the `START` register - (software start), or via the `SEQ_EXT_START` pin with `EN_EXT_START` set +* **Start**: The sequence can be started via a write to the ``START`` register + (software start), or via the `SEQ_EXT_START` pin with ``EN_EXT_START`` set (external start). The external start is typically driven by a GPIO or pulse_gen output. -* **Repeat mode**: A value of 0 in the `REPEAT` register causes the sequence to +* **Repeat mode**: A value of 0 in the ``REPEAT`` register causes the sequence to repeat forever (until reset or reconfiguration). * **Output hold**: When the sequence finishes or stops, the last output state - is held on `SEQ_OUT` — it does not return to zero. The sequencer does not + is held on ``SEQ_OUT`` — it does not return to zero. The sequencer does not reset its outputs on completion. -* **START and READY share the same address**: The `START` (write-only) and - `DONE` (read-only) registers are aliased at the same address. Writing to +* **START and READY share the same address**: The ``START`` (write-only) and + ``DONE`` (read-only) registers are aliased at the same address. Writing to address 1 triggers a start, reading address 1 returns the done flag. This pattern is consistent across seq_gen, spi, and pulse_gen. diff --git a/basil/firmware/modules/spi/README.rst b/basil/firmware/modules/spi/README.rst index 3845a0cb2..5238d423a 100644 --- a/basil/firmware/modules/spi/README.rst +++ b/basil/firmware/modules/spi/README.rst @@ -11,12 +11,12 @@ Module implements master serial peripheral interface. Supports simple internal l **Usage notes** -* **External start**: When `EN` is set, the SPI transfer can be triggered via - the `EXT_START` pin instead of a software write to `START`. -* **Repeat mode**: A value of 0 in the `REPEAT` register causes the transfer +* **External start**: When ``EN`` is set, the SPI transfer can be triggered via + the ``EXT_START`` pin instead of a software write to ``START``. +* **Repeat mode**: A value of 0 in the ``REPEAT`` register causes the transfer to repeat forever. -* **START and DONE share the same address**: The `START` (write-only) and - `DONE` (read-only) registers are aliased at the same address. Writing to +* **START and DONE share the same address**: The ``START`` (write-only) and + ``DONE`` (read-only) registers are aliased at the same address. Writing to address 1 triggers a start, reading address 1 returns the done flag. This pattern is consistent across seq_gen, spi, and pulse_gen. From 53a6d7542d1f876ff85d3a53cfb7080417ada10f Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 17:00:32 +0200 Subject: [PATCH 23/43] docs(firmware): Merge shared-address registers in README tables Combine RESET/VERSION (addr 0) and START/DONE/READY (addr 1) into single rows with slashed names and wo/ro access notation, making the address aliasing clear in the register tables themselves. --- basil/firmware/modules/pulse_gen/README.rst | 5 +++-- basil/firmware/modules/seq_gen/README.rst | 7 ++----- basil/firmware/modules/spi/README.rst | 4 +--- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/basil/firmware/modules/pulse_gen/README.rst b/basil/firmware/modules/pulse_gen/README.rst index 1755ba4ed..d86d82061 100644 --- a/basil/firmware/modules/pulse_gen/README.rst +++ b/basil/firmware/modules/pulse_gen/README.rst @@ -35,9 +35,10 @@ Simple pulse generator with configurable delay and width. +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +===============+==================================+========+=======+=============+============================================================================================+ - | START | 1 | | wo | | Software start on write to address | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | READY | 1 | [0] | ro | 0 | Indicate finish | + |RESET / VERSION| 0 | | wo/ro | | Soft reset on write / Firmware version | + +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ + | START / READY | 1 | | wo/ro | 0 | Software start on write / Indicate finish | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | EN | 2 | [0] | r/w | 0 | Enable external start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ diff --git a/basil/firmware/modules/seq_gen/README.rst b/basil/firmware/modules/seq_gen/README.rst index 46546abb9..305571380 100644 --- a/basil/firmware/modules/seq_gen/README.rst +++ b/basil/firmware/modules/seq_gen/README.rst @@ -53,13 +53,10 @@ Module implements a simple sequencer/pattern generator based on block ram. Suppo +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +===============+==================================+========+=======+=============+============================================================================================+ - | RESET | 0 | | wo | | Soft reset on write | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | VERSION | 0 | [7:0] | ro | | Firmware version | + |RESET / VERSION| 0 | | wo/ro | | Soft reset on write / Firmware version | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | START | 1 | | wo | | Start sequence on write | - +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DONE | 1 | [0] | ro | 0 | Indicates sequence finished | + | START / DONE | 1 | | wo/ro | 0 | Start sequence on write / Indicates sequence finished | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | EN_EXT_START | 2 | [0] | r/w | 0 | Enable external start | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ diff --git a/basil/firmware/modules/spi/README.rst b/basil/firmware/modules/spi/README.rst index 5238d423a..6cfa3860e 100644 --- a/basil/firmware/modules/spi/README.rst +++ b/basil/firmware/modules/spi/README.rst @@ -50,9 +50,7 @@ Module implements master serial peripheral interface. Supports simple internal l +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ | Name | Address | Bits | r/w | Default | Description | +==============+==================================+========+=======+=============+=============================================+ - | START | 1 | | wo | | Start transfer on write to address | - +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ - | DONE | 1 | [0] | ro | 0 | Indicate transfer finish | + |START / DONE |1 | |wo/ro |0 |Start transfer / Indicate transfer finish | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ | SIZE | 4 - 3 | [15:0] | r/w | MEM_BYTES*8 | Set the size of transfer in bits | +--------------+----------------------------------+--------+-------+-------------+---------------------------------------------+ From cc3f30b79a7c172a4ef450850db573dba0b8aecd Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 17:21:35 +0200 Subject: [PATCH 24/43] fix(fastrx): Bump fastrx driver version, since I changed API --- basil/HL/fast_spi_rx.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index b3ee7f613..b0e593613 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -30,7 +30,7 @@ class fast_spi_rx(RegisterHardwareLayer): "EN": {"descr": {"addr": 2, "size": 1, "offset": 0}}, "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, } - _require_version = "==0" + _require_version = "==1" def __init__(self, intf, conf): super(fast_spi_rx, self).__init__(intf, conf) From 095739f6248c4e7049e8de716fe1e87f8637e68c Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 17:54:53 +0200 Subject: [PATCH 25/43] feat(fast_spi_rx): Expose DATA_SIZE as read-only register at addr 4 - Add DATA_SIZE register (addr 4, ro) to the register decode in fast_spi_rx_core.v so the hardware parameter can be read back - Remove set_size from the Python driver; get_size now reads HW - Remove DATA_SIZE from YAML config (no longer needed) - Fix typo 'syncrhonized' -> 'synchronized' in fast_spi_rx_core.v - Fix docstring style: opening """ on its own line for multi-line - Delete bus_check.py utility (to be rewritten later) - Add Kian, Christian, and Rasmus to authors list in pyproject.toml --- basil/HL/fast_spi_rx.py | 36 +- basil/HL/gpio.py | 9 +- basil/HL/pulse_gen.py | 18 +- basil/HL/seq_gen.py | 36 +- basil/HL/spi.py | 6 +- .../modules/fast_spi_rx/fast_spi_rx_core.v | 6 +- basil/utils/bus_check.py | 784 ------------------ pyproject.toml | 5 +- 8 files changed, 71 insertions(+), 829 deletions(-) delete mode 100644 basil/utils/bus_check.py diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index b0e593613..7d3fd04d6 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -29,37 +29,30 @@ class fast_spi_rx(RegisterHardwareLayer): "VERSION": {"descr": {"addr": 0, "size": 8, "properties": ["ro"]}}, "EN": {"descr": {"addr": 2, "size": 1, "offset": 0}}, "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, + "DATA_SIZE": {"descr": {"addr": 4, "size": 8, "properties": ["ro"]}}, } - _require_version = "==1" + _require_version = "==0" def __init__(self, intf, conf): super(fast_spi_rx, self).__init__(intf, conf) - # DATA_SIZE: number of bits for SPI data in the FIFO output - # Must match the DATA_SIZE parameter in the FPGA firmware - self._data_size = conf.get("DATA_SIZE", 16) # default 16 for backward compatibility - if self._data_size < 1 or self._data_size > 28: - raise ValueError("DATA_SIZE must be between 1 and 28") - - def set_size(self, value): - """Set the Python-only DATA_SIZE attribute tracking the SPI data width in bits. - - Must match the DATA_SIZE parameter set in the FPGA firmware (fast_spi_rx_core.v). - Valid range: 1-28. - """ - if value < 1 or value > 28: - raise ValueError("DATA_SIZE must be between 1 and 28") - self._data_size = value def get_size(self): - """Return the DATA_SIZE (SPI data width in bits) used for parsing captured words.""" - return self._data_size + """ + Return the DATA_SIZE (SPI data width in bits) used for parsing captured words. + Reads the value from the hardware DATA_SIZE register (addr 4). + """ + return self.DATA_SIZE def reset(self): """Soft reset the module. Clears internal counters and shift registers on the next SEQ_CLK edge.""" self.RESET = 0 def set_en(self, value): - """Arm/disarm capture. When enabled, serial data on SDI is captured on each rising edge of SEQ_CLK while SEN is high.""" + """ + Arm/disarm capture. + When enabled, serial data on SDI is captured on each rising edge of + SEQ_CLK while SEN is high. + """ self.EN = value def get_en(self): @@ -67,7 +60,10 @@ def get_en(self): return self.EN def get_lost_count(self): - """Return the count of lost data words due to CDC FIFO overflow. Non-zero indicates the capture rate exceeded the readout rate.""" + """ + Return the count of lost data words due to CDC FIFO overflow. + Non-zero indicates the capture rate exceeded the readout rate. + """ return self.LOST_COUNT def parse_word(self, word): diff --git a/basil/HL/gpio.py b/basil/HL/gpio.py index 8d563fc9c..981d955a5 100644 --- a/basil/HL/gpio.py +++ b/basil/HL/gpio.py @@ -9,7 +9,8 @@ class gpio(RegisterHardwareLayer): - """GPIO interface""" + """ + GPIO interface""" def __init__(self, intf, conf): self._registers = { @@ -44,7 +45,8 @@ def reset(self): self.RESET = 0 def set_output_en(self, value): - """Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" + """ + Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" self.OUTPUT_EN = value def get_output_en(self): @@ -52,7 +54,8 @@ def get_output_en(self): return self.OUTPUT_EN def set_data(self, value): - """Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" + """ + Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" self.OUTPUT = value def get_data(self): diff --git a/basil/HL/pulse_gen.py b/basil/HL/pulse_gen.py index 5ed8b771d..d046ed685 100644 --- a/basil/HL/pulse_gen.py +++ b/basil/HL/pulse_gen.py @@ -9,7 +9,8 @@ class pulse_gen(RegisterHardwareLayer): - """Pulse generator""" + """ + Pulse generator""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -33,7 +34,8 @@ def start(self): self.START = 0 def reset(self): - """Soft reset the pulse generator. Clears internal state on the next clock edge.""" + """ + Soft reset the pulse generator. Clears internal state on the next clock edge.""" self.RESET = 0 def set_delay(self, value): @@ -44,7 +46,8 @@ def set_delay(self, value): self.DELAY = value def get_delay(self): - """Return the pulse delay in clock cycles.""" + """ + Return the pulse delay in clock cycles.""" return self.DELAY def set_width(self, value): @@ -54,7 +57,8 @@ def set_width(self, value): self.WIDTH = value def get_width(self): - """Return the pulse width in clock cycles.""" + """ + Return the pulse width in clock cycles.""" return self.WIDTH def set_repeat(self, value): @@ -62,7 +66,8 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """Return the repeat count.""" + """ + Return the repeat count.""" return self.REPEAT def is_done(self): @@ -71,7 +76,8 @@ def is_done(self): @property def is_ready(self): - """Read the READY register (addr 1, bit 0). Returns True when the pulse generator + """ + Read the READY register (addr 1, bit 0). Returns True when the pulse generator is idle and ready to accept a new start trigger. While the pulse is running (including all configured repetitions) this reads False. diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index 4dd065c3f..b75a2d18e 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -9,7 +9,8 @@ class seq_gen(RegisterHardwareLayer): - """Sequence generator controller interface for seq_gen FPGA module.""" + """ + Sequence generator controller interface for seq_gen FPGA module.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -42,7 +43,8 @@ def reset(self): self.RESET = 0 def start(self): - """Start the sequencer. Writes to the START register (addr 1). The sequence begins on the next SEQ_CLK edge after the write. Only effective when DONE/READY is high (sequence not already running).""" + """ + Start the sequencer. Writes to the START register (addr 1). The sequence begins on the next SEQ_CLK edge after the write. Only effective when DONE/READY is high (sequence not already running).""" self.START = 0 def set_size(self, value): @@ -50,7 +52,8 @@ def set_size(self, value): self.SIZE = value def get_size(self): - """Return the configured sequence size in output words.""" + """ + Return the configured sequence size in output words.""" return self.SIZE def set_wait(self, value): @@ -58,7 +61,8 @@ def set_wait(self, value): self.WAIT = value def get_wait(self): - """Return the configured wait cycles between repetitions.""" + """ + Return the configured wait cycles between repetitions.""" return self.WAIT def set_clk_divide(self, value): @@ -66,7 +70,8 @@ def set_clk_divide(self, value): self.CLK_DIV = value def get_clk_divide(self): - """Return the clock division factor.""" + """ + Return the clock division factor.""" return self.CLK_DIV def set_repeat_start(self, value): @@ -74,7 +79,8 @@ def set_repeat_start(self, value): self.REPEAT_START = value def get_repeat_start(self): - """Return the repeat start position.""" + """ + Return the repeat start position.""" return self.REPEAT_START def set_repeat(self, value): @@ -82,7 +88,8 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """Return the repeat count.""" + """ + Return the repeat count.""" return self.REPEAT def is_done(self): @@ -91,7 +98,8 @@ def is_done(self): @property def is_ready(self): - """Read the DONE/READY register (addr 1, bit 0). Returns True when the sequencer + """ + Read the DONE/READY register (addr 1, bit 0). Returns True when the sequencer is idle and ready to accept a new start trigger. While the sequence is running (including all configured repetitions) this reads False. @@ -103,7 +111,8 @@ def is_ready(self): return self.READY def get_done(self): - """Alias for is_ready. Returns True if sequencer is finished.""" + """ + Alias for is_ready. Returns True if sequencer is finished.""" return self.is_ready def set_en_ext_start(self, value): @@ -111,7 +120,8 @@ def set_en_ext_start(self, value): self.EN_EXT_START = value def get_en_ext_start(self): - """Return whether external start is enabled.""" + """ + Return whether external start is enabled.""" return self.EN_EXT_START def set_nested_start(self, value): @@ -122,7 +132,8 @@ def get_nested_start(self): return self.NESTED_START def set_nested_stop(self, value): - """Set the nested loop stop position. Addresses 24-27.""" + """ + Set the nested loop stop position. Addresses 24-27.""" self.NESTED_STOP = value def get_nested_stop(self): @@ -139,7 +150,8 @@ def get_mem_size(self): return self.MEM_BYTES def set_data(self, data, addr=0): - """Write sequencer memory (the pattern data) via the bus interface at the memory offset. Data is interleaved per track by the TrackRegister RL. Args are bytes to write and optional byte address offset.""" + """ + Write sequencer memory (the pattern data) via the bus interface at the memory offset. Data is interleaved per track by the TrackRegister RL. Args are bytes to write and optional byte address offset.""" if self._seq_mem_size < len(data): raise ValueError( "Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._seq_mem_size) diff --git a/basil/HL/spi.py b/basil/HL/spi.py index 6deae6da8..e958fce2e 100644 --- a/basil/HL/spi.py +++ b/basil/HL/spi.py @@ -9,7 +9,8 @@ class spi(RegisterHardwareLayer): - """Implement serial programming interface (SPI) driver.""" + """ + Implement serial programming interface (SPI) driver.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -100,7 +101,8 @@ def is_done(self): @property def is_ready(self): - """Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" + """ + Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" return self.READY def get_mem_size(self): diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index b415a0559..c1c688753 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -61,6 +61,8 @@ end reg [7:0] LOST_DATA_CNT; +localparam DATA_SIZE_READ = DATA_SIZE; + always @(posedge BUS_CLK) begin if(BUS_RD) begin if(BUS_ADD == 0) @@ -69,6 +71,8 @@ always @(posedge BUS_CLK) begin BUS_DATA_OUT <= {7'b0, CONF_EN}; else if(BUS_ADD == 3) BUS_DATA_OUT <= LOST_DATA_CNT; + else if(BUS_ADD == 4) + BUS_DATA_OUT <= DATA_SIZE_READ; else BUS_DATA_OUT <= 8'b0; end @@ -76,7 +80,7 @@ end wire RST_SYNC; wire RST_SOFT_SYNC; -// Reset is syncrhonized by the sclk +// Reset is synchronized by the sclk cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SCLK), .pulse_out(RST_SOFT_SYNC)); assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; diff --git a/basil/utils/bus_check.py b/basil/utils/bus_check.py deleted file mode 100644 index eaf16b246..000000000 --- a/basil/utils/bus_check.py +++ /dev/null @@ -1,784 +0,0 @@ -#!/usr/bin/env python3 -""" -Basil Bus Address Map Generator and Verification Tool - -This utility: -1. Parses Verilog modules to extract default BASEADDR/HIGHADDR parameters -2. Parses YAML configuration files to extract configured addresses -3. Cross-checks Verilog defaults against YAML configurations -4. Detects address range overlaps -5. Generates markdown tables and ASCII diagrams of the address map - -Usage: - # As a module - python -m basil.utils.check_bus - - # With custom paths - python -m basil.utils.check_bus --verilog-glob "basil/firmware/modules/**/*.v" \ - --yaml-glob "examples/**/*.yaml" - - # As pre-commit hook - python -m basil.utils.check_bus --quiet -""" - -import argparse -import glob -import re -import sys -from pathlib import Path -from collections import defaultdict - -try: - import yaml - HAS_YAML = True -except ImportError: - HAS_YAML = False - - -def parse_verilog_modules(verilog_glob, base_dir=None): - """ - Extract module names and address parameters from Verilog files. - - This parses: - 1. Module declarations with BASEADDR/HIGHADDR parameters - 2. Localparam/parameter definitions (e.g., SEQ_GEN_BASEADDR = 32'h10000) - 3. Module instantiations with .BASEADDR()/.HIGHADDR() parameter assignments - - Args: - verilog_glob: Glob pattern for Verilog files - base_dir: Base directory for relative paths (default: current dir) - - Returns: - dict: {module_name: {baseaddr, highaddr, file, line, instantiation_name, type}} - """ - if base_dir is None: - base_dir = Path.cwd() - else: - base_dir = Path(base_dir) - - modules = {} - - for v_path in Path(base_dir).glob(verilog_glob): - if not v_path.is_file(): - continue - - try: - with open(v_path, 'r', encoding='utf-8') as f: - content = f.read() - except (IOError, UnicodeDecodeError): - continue - - # First pass: Find all localparam/parameter definitions that look like addresses - # These are typically named *BASEADDR or *HIGHADDR - # Build a dict of name -> raw value string first - localparam_defs = {} - param_pattern = re.compile( - r'^(?:\s*)?(?:localparam|parameter)\s+(?:integer\s+)?(\w+)\s*=\s*([^;]+);', - re.MULTILINE | re.IGNORECASE - ) - - for match in param_pattern.finditer(content): - param_name = match.group(1) - param_value_expr = match.group(2).strip() - - # Only care about params that look like address parameters - if 'ADDR' in param_name.upper(): - localparam_defs[param_name] = param_value_expr - - # Now resolve all localparam values (handle references to other localparams) - localparams = {} - for param_name, param_value_expr in localparam_defs.items(): - value = resolve_verilog_expression(param_value_expr, content, localparams) - if value is not None: - localparams[param_name] = value - else: - # Try to parse directly as a literal - try: - localparams[param_name] = parse_verilog_value(param_value_expr) - except (ValueError, AttributeError): - pass - - # Second pass: Find all module declarations with BASEADDR/HIGHADDR parameters - module_pattern = re.compile( - r'module\s+(\w+)\s*#\s*\((.*?)\)\s*\([^)]*\)', - re.DOTALL - ) - - for match in module_pattern.finditer(content): - module_name = match.group(1) - params_block = match.group(2) - - # Extract BASEADDR and HIGHADDR - baseaddr = None - highaddr = None - - for param_match in re.finditer( - r'parameter\s+(BASEADDR|HIGHADDR)\s*=\s*(\w+)', - params_block, - re.IGNORECASE - ): - param_name = param_match.group(1).upper() - param_value_str = param_match.group(2) - value = parse_verilog_value(param_value_str) - - if param_name == "BASEADDR": - baseaddr = value - elif param_name == "HIGHADDR": - highaddr = value - - if baseaddr is not None: - modules[module_name] = { - 'file': str(v_path.relative_to(base_dir)), - 'baseaddr': baseaddr, - 'highaddr': highaddr if highaddr is not None else baseaddr, - 'type': 'verilog', - 'instantiation_name': None - } - - # Third pass: Find module instantiations with BASEADDR/HIGHADDR - # We need to search inside module bodies only, not module declarations. - # Strategy: Find each module body (between 'module' and 'endmodule'), - # then search for instantiations within it. - - module_body_pattern = re.compile( - r'module\s+\w+[^;]*;(.+?)endmodule', - re.DOTALL - ) - - for body_match in module_body_pattern.finditer(content): - module_body = body_match.group(1) - body_offset = body_match.start(1) - - # Find instantiations within this module body - # Pattern: module_type #( ... ) instance_name ( - inst_decl_pattern = re.compile( - r'(\w+)\s*#\s*\((.*?)\)\s+(\w+)\s*\(', - re.DOTALL - ) - - for match in inst_decl_pattern.finditer(module_body): - module_type = match.group(1) - params_block = match.group(2) - instance_name = match.group(3) - - # Now parse the params_block for BASEADDR and HIGHADDR - baseaddr = None - highaddr = None - - # Look for .BASEADDR(value) or .BASEADDR (value) - baseaddr_match = re.search( - r'\.BASEADDR\s*\(([^)]+)\)', - params_block, - re.IGNORECASE - ) - if baseaddr_match: - baseaddr_expr = baseaddr_match.group(1).strip() - baseaddr = resolve_verilog_expression(baseaddr_expr, content, localparams) - - # Look for .HIGHADDR(value) or .HIGHADDR (value) - highaddr_match = re.search( - r'\.HIGHADDR\s*\(([^)]+)\)', - params_block, - re.IGNORECASE - ) - if highaddr_match: - highaddr_expr = highaddr_match.group(1).strip() - highaddr = resolve_verilog_expression(highaddr_expr, content, localparams) - - if baseaddr is not None: - modules[instance_name] = { - 'file': str(v_path.relative_to(base_dir)), - 'baseaddr': baseaddr, - 'highaddr': highaddr if highaddr is not None else baseaddr, - 'type': module_type, - 'instantiation_name': instance_name - } - - return modules - - -def resolve_verilog_expression(expr, content, localparams=None): - """ - Resolve a Verilog expression to an integer value. - - Handles: - - Literal values: 32'h10000, 16'h0000, etc. - - Localparam references: SEQ_GEN_BASEADDR - - Simple identifiers that might be defined elsewhere - - Args: - expr: The expression string to resolve - content: Full Verilog file content for localparam lookup - localparams: Optional dict of already-parsed localparams for faster lookup - - Returns: - int or None if cannot be resolved - """ - expr = expr.strip() - - # If it's a simple identifier, look for localparam definitions first - # (before trying literal parse, which would return 0 for identifiers) - if re.match(r'^[a-zA-Z_][a-zA-Z0-9_]*$', expr): - # Check pre-parsed localparams first - if localparams and expr in localparams: - return localparams[expr] - - # Look for localparam or parameter definitions in content - param_pattern = re.compile( - rf'^(?:localparam|parameter)\s+(?:integer\s+)?{expr}\s*=\s*([^;]+);', - re.MULTILINE | re.IGNORECASE - ) - match = param_pattern.search(content) - if match: - param_value_expr = match.group(1).strip() - # Recursively resolve the value expression - return resolve_verilog_expression(param_value_expr, content, localparams) - - # Try to parse as a literal value - try: - value = parse_verilog_value(expr) - # parse_verilog_value returns 0 for unparseable identifiers, - # so we need to distinguish between actual 0 and failed parse - if value == 0 and not re.match(r'^\s*(0+|0x0+|\d+\'[hdb]0+)\s*$', expr, re.IGNORECASE): - return None - return value - except (ValueError, AttributeError): - pass - - return None - - -def parse_verilog_value(value_str): - """ - Parse a Verilog parameter value string into an integer. - - Handles formats like: - - 16'h0000 - - 8'hFF - - 32'd1024 - - 1024 - - 32'h10000 - """ - value_str = value_str.strip() - - # Hex with width prefix: 16'h0000, 8'hFF, 32'h10000 - hex_match = re.match(r'\d+\'h([0-9a-fA-F]+)', value_str) - if hex_match: - return int(hex_match.group(1), 16) - - # Decimal with width prefix: 32'd1024 - dec_match = re.match(r'\d+\'d(\d+)', value_str) - if dec_match: - return int(dec_match.group(1), 10) - - # Binary with width prefix: 8'b1010 - bin_match = re.match(r'\d+\'b([01]+)', value_str) - if bin_match: - return int(bin_match.group(1), 2) - - # Plain hex: h0000, 'h0000 - if value_str.startswith("h") or value_str.startswith("'h"): - hex_str = value_str[2:] if value_str.startswith("h") else value_str[1:] - return int(hex_str, 16) - - # Plain decimal - try: - return int(value_str, 10) - except ValueError: - # If we can't parse it, return 0 - return 0 - - -def parse_yaml_configs(yaml_glob, base_dir=None): - """ - Extract hw_drivers and their addresses from YAML files. - - Args: - yaml_glob: Glob pattern for YAML files - base_dir: Base directory for relative paths - - Returns: - dict: {driver_type: [{name, base_addr, size, high_addr, file, line}]} - """ - if not HAS_YAML: - print("Error: PyYAML is required. Install with: pip install pyyaml", file=sys.stderr) - sys.exit(1) - - if base_dir is None: - base_dir = Path.cwd() - else: - base_dir = Path(base_dir) - - drivers = defaultdict(list) - - for yaml_path in Path(base_dir).glob(yaml_glob): - if not yaml_path.is_file(): - continue - - try: - with open(yaml_path, 'r', encoding='utf-8') as f: - config = yaml.safe_load(f) - except (yaml.YAMLError, IOError): - continue - - if not config or not isinstance(config, dict): - continue - - if 'hw_drivers' in config: - for idx, driver in enumerate(config['hw_drivers']): - if not isinstance(driver, dict): - continue - if 'base_addr' not in driver or 'type' not in driver: - continue - - driver_type = driver['type'] - base_addr = driver['base_addr'] - # Handle both 'size' and 'mem_size' - mem_size is the address range, size is register size - size = driver.get('size', driver.get('mem_size', 0)) - - # Handle string hex addresses like "0x10000" - if isinstance(base_addr, str): - if base_addr.startswith('0x'): - base_addr = int(base_addr, 16) - else: - base_addr = int(base_addr, 10) - - if isinstance(size, str): - if size.startswith('0x'): - size = int(size, 16) - else: - size = int(size, 10) - - high_addr = base_addr + size - 1 if size > 0 else base_addr - - entry = { - 'file': str(yaml_path.relative_to(base_dir)), - 'name': driver.get('name', f'unnamed_{idx}'), - 'type': driver_type, - 'base_addr': base_addr, - 'size': size, - 'high_addr': high_addr, - 'yaml_type': 'hw_driver' - } - drivers[driver_type].append(entry) - - return drivers - - -def generate_address_map(verilog_modules, yaml_drivers): - """ - Generate address map from Verilog and cross-check against YAML. - - The table is built from Verilog modules. For each Verilog module, we try to - find a matching YAML driver by module type. If found, we verify the addresses - match. If not found, we warn that the YAML config is missing. - - Args: - verilog_modules: Dict of Verilog modules from parse_verilog_modules - yaml_drivers: Dict of YAML drivers from parse_yaml_configs - - Returns: - tuple: (address_map_list, issues_list) - """ - address_map = [] - issues = [] - - # Build lookup structures for YAML drivers - # yaml_by_type: {module_type: [driver1, driver2, ...]} - yaml_by_type = {} - for driver_type, driver_list in yaml_drivers.items(): - yaml_by_type[driver_type] = driver_list - - # Track which YAML drivers have been matched to Verilog - matched_yaml = set() - - # Process Verilog modules - this is the primary data source - for module_name, module_info in verilog_modules.items(): - module_type = module_info.get('type', module_name) - v_base = module_info['baseaddr'] - v_high = module_info['highaddr'] - v_size = v_high - v_base + 1 - - # Try to find matching YAML driver(s) by module type - yaml_matches = yaml_by_type.get(module_type, []) - - # Find the best match: same base address - best_match = None - for yd in yaml_matches: - if yd['base_addr'] == v_base: - best_match = yd - matched_yaml.add(id(yd)) - break - - # If no exact base address match, take the first one of this type - if not best_match and yaml_matches: - best_match = yaml_matches[0] - matched_yaml.add(id(best_match)) - - # Build the table row - row = { - 'module': module_name, - 'type': module_type, - 'base_addr': v_base, - 'high_addr': v_high, - 'size': v_size, - 'verilog_file': module_info['file'], - 'yaml_name': best_match['name'] if best_match else None, - 'yaml_file': best_match['file'] if best_match else None, - 'yaml_base': best_match['base_addr'] if best_match else None, - 'yaml_high': best_match['high_addr'] if best_match else None, - 'status': 'OK' - } - - # Determine status and generate issues - if not best_match: - row['status'] = 'MISSING_YAML' - issues.append({ - 'type': 'missing_yaml', - 'severity': 'warning', - 'module': module_name, - 'module_type': module_type, - 'verilog_file': module_info['file'], - 'verilog_addr': (v_base, v_high), - 'message': f"Verilog module '{module_name}' ({module_type}) has no matching YAML config" - }) - elif best_match['base_addr'] != v_base or best_match['high_addr'] != v_high: - row['status'] = 'MISMATCH' - issues.append({ - 'type': 'address_mismatch', - 'severity': 'warning', - 'module': module_name, - 'module_type': module_type, - 'verilog_file': module_info['file'], - 'yaml_file': best_match['file'], - 'verilog_addr': (v_base, v_high), - 'yaml_addr': (best_match['base_addr'], best_match['high_addr']), - 'message': f"Verilog module '{module_name}' ({module_type}) address mismatch" - }) - else: - row['status'] = 'OK' - - address_map.append(row) - - # Warn about YAML drivers that weren't matched to any Verilog module - for driver_type, driver_list in yaml_drivers.items(): - for driver in driver_list: - if id(driver) not in matched_yaml: - issues.append({ - 'type': 'unmatched_yaml', - 'severity': 'info', - 'module': driver['name'], - 'module_type': driver_type, - 'yaml_file': driver['file'], - 'yaml_addr': (driver['base_addr'], driver['high_addr']), - 'message': f"YAML driver '{driver['name']}' ({driver_type}) at {format_address(driver['base_addr'])}-{format_address(driver['high_addr'])} not found in Verilog" - }) - - return address_map, issues - - -def check_overlaps(address_map): - """ - Check for address range overlaps in the Verilog address map. - - Args: - address_map: List of address entries - - Returns: - list: List of overlap issues - """ - overlaps = [] - - for i, entry1 in enumerate(address_map): - for j, entry2 in enumerate(address_map): - if i >= j: - continue - - # Check if ranges truly overlap (not just adjacent) - if (entry1['base_addr'] < entry2['high_addr'] and - entry2['base_addr'] < entry1['high_addr']): - - # Only report if they're different instances - if entry1['module'] != entry2['module']: - overlaps.append({ - 'type': 'address_overlap', - 'severity': 'error', - 'module1': entry1['module'], - 'module2': entry2['module'], - 'range1': (entry1['base_addr'], entry1['high_addr']), - 'range2': (entry2['base_addr'], entry2['high_addr']), - 'file1': entry1['verilog_file'], - 'file2': entry2['verilog_file'], - 'message': f"Address overlap between {entry1['module']} and {entry2['module']}" - }) - - return overlaps - - -def format_address(addr, width=8): - """Format an address as hex with consistent width.""" - return f"0x{addr:0{width}X}" - - -def generate_markdown_table(address_map): - """Generate an aligned plain-text table of the address map.""" - if not address_map: - return "No address entries found." - - # Sort by base_addr - sorted_map = sorted(address_map, key=lambda x: x['base_addr']) - - # Calculate column widths - headers = ["Instance", "Module", "Base Address", "High Address", "Size", "File", "YAML Match"] - rows = [] - for entry in sorted_map: - size = entry['size'] - size_str = f"{size:,}" if size > 0 else "N/A" - - # Build YAML match info - if entry['status'] == 'OK': - yaml_match = entry['yaml_name'] if entry.get('yaml_name') else "OK" - elif entry['status'] == 'MISSING_YAML': - yaml_match = "MISSING" - elif entry['status'] == 'MISMATCH': - yaml_match = f"MISMATCH ({format_address(entry['yaml_base'])}-{format_address(entry['yaml_high'])})" - else: - yaml_match = "?" - - rows.append([ - entry['module'], - entry['type'], - format_address(entry['base_addr']), - format_address(entry['high_addr']), - size_str, - entry['verilog_file'], - yaml_match - ]) - - # Determine max width for each column - col_widths = [len(h) for h in headers] - for row in rows: - for i, cell in enumerate(row): - col_widths[i] = max(col_widths[i], len(cell)) - - # Build formatted output - lines = [] - # Header row - header_row = " ".join(h.ljust(col_widths[i]) for i, h in enumerate(headers)) - lines.append(header_row) - lines.append("-" * len(header_row)) - # Data rows - for row in rows: - lines.append(" ".join(cell.ljust(col_widths[i]) for i, cell in enumerate(row))) - - return "\n".join(lines) - - -def generate_ascii_diagram(address_map): - """Generate an ASCII memory map diagram from Verilog entries.""" - if not address_map: - return "No address entries found for diagram." - - # Sort all entries by base address - sorted_map = sorted(address_map, key=lambda x: x['base_addr']) - - lines = [] - lines.append("Basil Bus Address Map Diagram") - lines.append("=" * 70) - lines.append("") - - for entry in sorted_map: - base = entry['base_addr'] - high = entry['high_addr'] - size = entry['size'] - - # Format size with appropriate units - if size >= 1024 * 1024: - size_str = f"{size / (1024 * 1024):.2f}MB" - elif size >= 1024: - size_str = f"{size / 1024:.2f}KB" - else: - size_str = f"{size}B" if size > 0 else "N/A" - - base_hex = format_address(base) - high_hex = format_address(high) - - # Show status indicator - status = entry.get('status', '?') - if status == 'OK': - indicator = "[OK]" - elif status == 'MISSING_YAML': - indicator = "[NO YAML]" - elif status == 'MISMATCH': - indicator = "[MISMATCH]" - else: - indicator = "[?]" - - label = f"{entry['module']} [{entry['type']}]" - - lines.append( - f"{indicator:10s} {base_hex} - {high_hex} : " - f"{label} ({size_str})" - ) - - return "\n".join(lines) - - -def print_issues(issues, overlaps, quiet=False): - """Print issues found during analysis.""" - all_issues = issues + overlaps - - if not all_issues: - if not quiet: - print("OK: No issues found - Verilog and YAML addresses are consistent!") - return 0 - - error_count = sum(1 for i in all_issues if i['severity'] == 'error') - warning_count = sum(1 for i in all_issues if i['severity'] == 'warning') - info_count = sum(1 for i in all_issues if i['severity'] == 'info') - - if not quiet: - print(f"\nFound {error_count} error(s), {warning_count} warning(s), {info_count} info(s)") - print() - - for issue in all_issues: - severity_label = { - 'error': '[ERROR]', - 'warning': '[WARN] ', - 'info': '[INFO] ' - }.get(issue['severity'], '[ ]') - - if not quiet or issue['severity'] in ['error', 'warning']: - print(f"{severity_label} {issue['type'].replace('_', ' ').title()}") - print(f" {issue['message']}") - - if 'module' in issue: - print(f" Module: {issue['module']}") - if 'yaml_file' in issue: - print(f" YAML file: {issue['yaml_file']}") - if 'verilog_file' in issue: - print(f" Verilog file: {issue['verilog_file']}") - if 'verilog_addr' in issue: - v_base, v_high = issue['verilog_addr'] - print(f" Verilog address: {format_address(v_base)} - {format_address(v_high)}") - if 'verilog_default' in issue: - v_base, v_high = issue['verilog_default'] - print(f" Verilog default: {format_address(v_base)} - {format_address(v_high)}") - if 'yaml_addr' in issue: - y_base, y_high = issue['yaml_addr'] - print(f" YAML address: {format_address(y_base)} - {format_address(y_high)}") - if 'yaml_configured' in issue: - y_base, y_high = issue['yaml_configured'] - print(f" YAML configured: {format_address(y_base)} - {format_address(y_high)}") - if 'range1' in issue: - r1_base, r1_high = issue['range1'] - r2_base, r2_high = issue['range2'] - print(f" Range 1: {format_address(r1_base)} - {format_address(r1_high)}") - print(f" Range 2: {format_address(r2_base)} - {format_address(r2_high)}") - print() - - return 1 if error_count > 0 else 0 - - -def main(): - """Main entry point for the script.""" - parser = argparse.ArgumentParser( - description="Generate and verify Basil bus address map", - formatter_class=argparse.RawDescriptionHelpFormatter, - epilog=""" -Examples: - # Check all Basil files - python -m basil.utils.check_bus - - # Check specific paths - python -m basil.utils.check_bus --verilog-glob "basil/firmware/modules/**/*.v" \\ - --yaml-glob "examples/**/*.yaml" - - # As pre-commit hook (exits with error code on issues) - python -m basil.utils.check_bus --quiet - - # Examples: - python check_bus.py --verilog-glob "firmware/src/**/*.v" --yaml-glob "**/*.yaml" --base-dir ~/libs/tj-monopix2-daq - python check_bus.py --verilog-glob "firmware/src/**/*.v" --yaml-glob "**/*.yaml" --base-dir ~/libs/obelix1-daq - python check_bus.py --verilog-glob "design/fpga/daq_core.v" --yaml-glob "flow/scans/map_fpga.yaml" --base-dir /local/frida -""" - ) - - parser.add_argument( - '--verilog-glob', - default='basil/firmware/modules/**/*.v', - help='Glob pattern for Verilog files (relative to base-dir)' - ) - parser.add_argument( - '--yaml-glob', - default='**/*.yaml', - help='Glob pattern for YAML configuration files (relative to base-dir)' - ) - parser.add_argument( - '--base-dir', - default='.', - help='Base directory for glob patterns (default: current directory)' - ) - parser.add_argument( - '--output', - type=str, - default=None, - help='Output file for address map (default: stdout)' - ) - # Note: Overlap checking is always enabled - parser.add_argument( - '--quiet', - action='store_true', - help='Suppress non-error output (useful for pre-commit hooks)' - ) - parser.add_argument( - '--no-color', - action='store_true', - help='Disable colored output' - ) - - args = parser.parse_args() - - # Resolve base directory - base_dir = Path(args.base_dir).resolve() - - # Parse Verilog modules - verilog_modules = parse_verilog_modules(args.verilog_glob, base_dir) - - # Parse YAML configurations - yaml_drivers = parse_yaml_configs(args.yaml_glob, base_dir) - yaml_driver_count = sum(len(v) for v in yaml_drivers.values()) - - # Generate address map and check for issues - address_map, issues = generate_address_map(verilog_modules, yaml_drivers) - - # Always check for overlaps - overlaps = check_overlaps(address_map) - - # Generate output - just the table - output_lines = [] - output_lines.append("# Basil Bus Address Map") - output_lines.append("") - output_lines.append(generate_markdown_table(address_map)) - - # Write output - output_text = "\n".join(output_lines) - - if args.output: - with open(args.output, 'w', encoding='utf-8') as f: - f.write(output_text) - if not args.quiet: - print(f"\nAddress map written to: {args.output}") - else: - print(output_text) - - # Print issues and return appropriate exit code - exit_code = print_issues(issues, overlaps, quiet=args.quiet) - - # Summary is implicit in the output - - sys.exit(exit_code) - - -if __name__ == '__main__': - main() diff --git a/pyproject.toml b/pyproject.toml index c9d164fbc..08d7b3ef4 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -12,7 +12,10 @@ requires-python = ">=3.10" authors = [ {name = "Tomasz Hemperek", email="hemperek@uni-bonn.de"}, {name = "Jens Janssen", email="janssen@physik.uni-bonn.de"}, - {name = "David-Leon Pohl", email="pohl@physik.uni-bonn.de"} + {name = "David-Leon Pohl", email="pohl@physik.uni-bonn.de"}, + {name = "Kian Caisley", email="kcaisley@uni-bonn.de"}, + {name = "Christian Bespin", email="bespin@physik.uni-bonn.de"}, + {name = "Rasmus Partzsch", email="partzsch@physik.uni-bonn.de"}, ] maintainers = [ From 9f24ddb6195ce7c462fa8ba7366fbc2566a07463 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 18:03:34 +0200 Subject: [PATCH 26/43] style(seq_gen): Fix all pydocstyle (D) ruff warnings - Add module-level docstring - Add missing docstrings for __init__, init, get_nested_start, get_nested_stop, get_nested_repeat, get_mem_size - Fix D205: blank line between summary line and description - Break long single-line docstrings into multi-line with summary and description sections --- basil/HL/fast_spi_rx.py | 9 +-- basil/HL/seq_gen.py | 128 ++++++++++++++++++++++++++++------------ 2 files changed, 93 insertions(+), 44 deletions(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index 7d3fd04d6..8f817d765 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -37,8 +37,7 @@ def __init__(self, intf, conf): super(fast_spi_rx, self).__init__(intf, conf) def get_size(self): - """ - Return the DATA_SIZE (SPI data width in bits) used for parsing captured words. + """Return the DATA_SIZE (SPI data width in bits) used for parsing captured words. Reads the value from the hardware DATA_SIZE register (addr 4). """ return self.DATA_SIZE @@ -48,8 +47,7 @@ def reset(self): self.RESET = 0 def set_en(self, value): - """ - Arm/disarm capture. + """Arm/disarm capture. When enabled, serial data on SDI is captured on each rising edge of SEQ_CLK while SEN is high. """ @@ -60,8 +58,7 @@ def get_en(self): return self.EN def get_lost_count(self): - """ - Return the count of lost data words due to CDC FIFO overflow. + """Return the count of lost data words due to CDC FIFO overflow. Non-zero indicates the capture rate exceeded the readout rate. """ return self.LOST_COUNT diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index b75a2d18e..6846f209b 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -4,13 +4,13 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # +"""Sequence generator driver for the seq_gen FPGA module.""" from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class seq_gen(RegisterHardwareLayer): - """ - Sequence generator controller interface for seq_gen FPGA module.""" + """Sequence generator controller interface for seq_gen FPGA module.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -31,127 +31,170 @@ class seq_gen(RegisterHardwareLayer): _require_version = "==3" def __init__(self, intf, conf): + """Initialize the sequencer driver.""" super(seq_gen, self).__init__(intf, conf) self._seq_mem_offset = 64 # in bytes def init(self): + """Initialize the sequencer and read the memory size from hardware.""" super(seq_gen, self).init() self._seq_mem_size = self.get_mem_size() def reset(self): - """Soft reset the sequencer. Clears internal counters and output state on the next clock edge. Must have a rising edge on the sequencer clock before new data is written to memory.""" + """Soft reset the sequencer. + + Clears internal counters and output state on the next clock edge. + Must have a rising edge on the sequencer clock before new data is + written to memory. + """ self.RESET = 0 def start(self): + """Start the sequencer. + + Writes to the START register (addr 1). The sequence begins on the + next SEQ_CLK edge after the write. Only effective when DONE/READY + is high (sequence not already running). """ - Start the sequencer. Writes to the START register (addr 1). The sequence begins on the next SEQ_CLK edge after the write. Only effective when DONE/READY is high (sequence not already running).""" self.START = 0 def set_size(self, value): - """Set the number of output words in the sequence. Each word contains OUT_BITS (one sample per track). Addresses 4-7.""" + """Set the number of output words in the sequence. + + Each word contains OUT_BITS (one sample per track). Addresses 4-7. + """ self.SIZE = value def get_size(self): - """ - Return the configured sequence size in output words.""" + """Return the configured sequence size in output words.""" return self.SIZE def set_wait(self, value): - """Set wait cycles inserted between repetitions. Only applies when REPEAT > 0. Addresses 8-11.""" + """Set wait cycles inserted between repetitions. + + Only applies when REPEAT > 0. Addresses 8-11. + """ self.WAIT = value def get_wait(self): - """ - Return the configured wait cycles between repetitions.""" + """Return the configured wait cycles between repetitions.""" return self.WAIT def set_clk_divide(self, value): - """Set the clock division factor for SEQ_CLK. The sequencer advances one step every CLK_DIV + 1 clock cycles. Default: 1 (divide by 1, i.e. full rate). Address 3.""" + """Set the clock division factor for SEQ_CLK. + + The sequencer advances one step every CLK_DIV + 1 clock cycles. + Default: 1 (divide by 1, i.e. full rate). Address 3. + """ self.CLK_DIV = value def get_clk_divide(self): - """ - Return the clock division factor.""" + """Return the clock division factor.""" return self.CLK_DIV def set_repeat_start(self, value): - """Set the repeat start position. When repeating, the sequence jumps to this position instead of starting from 0. Addresses 16-19.""" + """Set the repeat start position. + + When repeating, the sequence jumps to this position instead of + starting from 0. Addresses 16-19. + """ self.REPEAT_START = value def get_repeat_start(self): - """ - Return the repeat start position.""" + """Return the repeat start position.""" return self.REPEAT_START def set_repeat(self, value): - """Set the repeat count. 0 = repeat forever. The sequence repeats from REP_START (or 0) each time. Addresses 12-15.""" + """Set the repeat count. + + 0 = repeat forever. The sequence repeats from REP_START (or 0) + each time. Addresses 12-15. + """ self.REPEAT = value def get_repeat(self): - """ - Return the repeat count.""" + """Return the repeat count.""" return self.REPEAT def is_done(self): - """Return True if the sequencer has finished its sequence (including all repeats), False if running. Aliases is_ready.""" + """Return True if the sequencer has finished its sequence. + + Includes all repeats. Returns False while running. Aliases is_ready. + """ return self.is_ready @property def is_ready(self): - """ - Read the DONE/READY register (addr 1, bit 0). Returns True when the sequencer - is idle and ready to accept a new start trigger. While the sequence is running - (including all configured repetitions) this reads False. + """Read the DONE/READY register (addr 1, bit 0). + + Returns True when the sequencer is idle and ready to accept a new + start trigger. While the sequence is running (including all + configured repetitions) this reads False. - The ``@property`` decorator makes this an attribute-like access — call it - without parentheses as ``daq["seq0"].is_ready``, not ``.is_ready()``. + The ``@property`` decorator makes this an attribute-like access — + call it without parentheses as ``daq["seq0"].is_ready``, not + ``.is_ready()``. - ``.is_done()`` and ``.get_done()`` are aliases that return the same value. + ``.is_done()`` and ``.get_done()`` are aliases that return the + same value. """ return self.READY def get_done(self): - """ - Alias for is_ready. Returns True if sequencer is finished.""" + """Alias for is_ready. Returns True if sequencer is finished.""" return self.is_ready def set_en_ext_start(self, value): - """Enable or disable external start via the SEQ_EXT_START pin. When enabled (1), the SEQ_EXT_START pin rising edge triggers the sequence. When disabled (0), only software .start() works. Address 2.""" + """Enable or disable external start via the SEQ_EXT_START pin. + + When enabled (1), the SEQ_EXT_START pin rising edge triggers the + sequence. When disabled (0), only software .start() works. + Address 2. + """ self.EN_EXT_START = value def get_en_ext_start(self): - """ - Return whether external start is enabled.""" + """Return whether external start is enabled.""" return self.EN_EXT_START def set_nested_start(self, value): - """Set the nested loop start position. Addresses 20-23.""" + """Set the nested loop start position. Addresses 20-23.""" self.NESTED_START = value def get_nested_start(self): + """Return the nested loop start position.""" return self.NESTED_START def set_nested_stop(self, value): - """ - Set the nested loop stop position. Addresses 24-27.""" + """Set the nested loop stop position. Addresses 24-27.""" self.NESTED_STOP = value def get_nested_stop(self): + """Return the nested loop stop position.""" return self.NESTED_STOP def set_nested_repeat(self, value): - """Set the nested loop repeat count. 0 = disabled. Addresses 28-31.""" + """Set the nested loop repeat count. 0 = disabled. Addresses 28-31.""" self.NESTED_REPEAT = value def get_nested_repeat(self): + """Return the nested loop repeat count.""" return self.NESTED_REPEAT def get_mem_size(self): + """Return the memory size in bytes.""" return self.MEM_BYTES def set_data(self, data, addr=0): + """Write sequencer memory (the pattern data) via the bus interface. + + Data is interleaved per track by the TrackRegister RL. + + Args: + data: Bytes to write to sequencer memory. + addr: Optional byte offset into memory. + """ - Write sequencer memory (the pattern data) via the bus interface at the memory offset. Data is interleaved per track by the TrackRegister RL. Args are bytes to write and optional byte address offset.""" if self._seq_mem_size < len(data): raise ValueError( "Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._seq_mem_size) @@ -159,7 +202,16 @@ def set_data(self, data, addr=0): self._intf.write(self._conf["base_addr"] + self._seq_mem_offset + addr, data) def get_data(self, size=None, addr=0): - """Read sequencer memory (the pattern data) via the bus interface. Returns bytes. Args are number of bytes to read and optional byte address offset.""" + """Read sequencer memory (the pattern data) via the bus interface. + + Args: + size: Number of bytes to read (default: all). + addr: Optional byte offset into memory. + + Returns: + bytes: The pattern data. + + """ if size and self._seq_mem_size < size: raise ValueError("Size is too big") if not size: From f44346348f4e5228d242d5d864f3aa22a4a59418 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 18:14:44 +0200 Subject: [PATCH 27/43] style: Fix all pydocstyle D warnings across HL drivers - Add missing module-level, __init__, and method docstrings - Fix D205: blank line between summary line and description - Fix D200/D212: collapse multi-line single-liners - Fix D400/D401/D415: imperative mood, periods, single-line convention - Fix D413: blank line after Args/Returns sections --- basil/HL/fast_spi_rx.py | 17 +++++++++ basil/HL/gpio.py | 13 +++---- basil/HL/pulse_gen.py | 45 ++++++++++------------- basil/HL/spi.py | 79 ++++++++++++++++++++++------------------- 4 files changed, 85 insertions(+), 69 deletions(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index 8f817d765..2f154a85b 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -4,6 +4,12 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # +"""Fast SPI receive interface for reading variable-width serial data. + +Provides a register-level hardware layer to arm/disarm capture, query +frame-size configuration, check for lost words, and parse 32-bit FIFO +words into (identifier, frame_counter, spi_data) tuples. +""" from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer @@ -34,10 +40,18 @@ class fast_spi_rx(RegisterHardwareLayer): _require_version = "==0" def __init__(self, intf, conf): + """Initialize the fast_spi_rx hardware layer. + + Args: + intf: The low-level interface to the hardware. + conf: Configuration dictionary passed to the base class. + + """ super(fast_spi_rx, self).__init__(intf, conf) def get_size(self): """Return the DATA_SIZE (SPI data width in bits) used for parsing captured words. + Reads the value from the hardware DATA_SIZE register (addr 4). """ return self.DATA_SIZE @@ -48,6 +62,7 @@ def reset(self): def set_en(self, value): """Arm/disarm capture. + When enabled, serial data on SDI is captured on each rising edge of SEQ_CLK while SEN is high. """ @@ -59,6 +74,7 @@ def get_en(self): def get_lost_count(self): """Return the count of lost data words due to CDC FIFO overflow. + Non-zero indicates the capture rate exceeded the readout rate. """ return self.LOST_COUNT @@ -74,6 +90,7 @@ def parse_word(self, word): Returns: tuple: (identifier, frame_counter, spi_data) + """ data_size = self.get_size() identifier = (word >> 28) & 0xF diff --git a/basil/HL/gpio.py b/basil/HL/gpio.py index 981d955a5..7c82fd339 100644 --- a/basil/HL/gpio.py +++ b/basil/HL/gpio.py @@ -5,14 +5,16 @@ # ------------------------------------------------------------ # +"""GPIO hardware layer for Basil.""" + from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class gpio(RegisterHardwareLayer): - """ - GPIO interface""" + """GPIO interface.""" def __init__(self, intf, conf): + """Initialize GPIO interface.""" self._registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, "VERSION": {"descr": {"addr": 0, "size": 8, "properties": ["ro"]}}, @@ -36,6 +38,7 @@ def __init__(self, intf, conf): super(gpio, self).__init__(intf, conf) def init(self): + """Initialize the hardware.""" super(gpio, self).init() if "output_en" in self._init: self.OUTPUT_EN = self._init["output_en"] @@ -45,8 +48,7 @@ def reset(self): self.RESET = 0 def set_output_en(self, value): - """ - Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" + """Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" self.OUTPUT_EN = value def get_output_en(self): @@ -54,8 +56,7 @@ def get_output_en(self): return self.OUTPUT_EN def set_data(self, value): - """ - Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" + """Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" self.OUTPUT = value def get_data(self): diff --git a/basil/HL/pulse_gen.py b/basil/HL/pulse_gen.py index d046ed685..f80b3732f 100644 --- a/basil/HL/pulse_gen.py +++ b/basil/HL/pulse_gen.py @@ -5,12 +5,13 @@ # ------------------------------------------------------------ # +"""Register-based interface to the pulse_gen hardware block.""" + from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class pulse_gen(RegisterHardwareLayer): - """ - Pulse generator""" + """Pulse generator.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -25,40 +26,34 @@ class pulse_gen(RegisterHardwareLayer): _require_version = "==3" def __init__(self, intf, conf): + """Initialize pulse generator layer.""" super(pulse_gen, self).__init__(intf, conf) def start(self): - """ - Software start of pulse at random time - """ + """Software start of pulse at random time.""" self.START = 0 def reset(self): - """ - Soft reset the pulse generator. Clears internal state on the next clock edge.""" + """Soft reset the pulse generator. Clears internal state on the next clock edge.""" self.RESET = 0 def set_delay(self, value): - """ - Set the pulse delay in clock cycles from start. + """Set the pulse delay in clock cycles from start. + The delay is relative to the start trigger (software .start() or EXT_START pin). """ self.DELAY = value def get_delay(self): - """ - Return the pulse delay in clock cycles.""" + """Return the pulse delay in clock cycles.""" return self.DELAY def set_width(self, value): - """ - Pulse width in terms of clock cycles - """ + """Set the pulse width in terms of clock cycles.""" self.WIDTH = value def get_width(self): - """ - Return the pulse width in clock cycles.""" + """Return the pulse width in clock cycles.""" return self.WIDTH def set_repeat(self, value): @@ -66,8 +61,7 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """ - Return the repeat count.""" + """Return the repeat count.""" return self.REPEAT def is_done(self): @@ -76,12 +70,12 @@ def is_done(self): @property def is_ready(self): - """ - Read the READY register (addr 1, bit 0). Returns True when the pulse generator - is idle and ready to accept a new start trigger. While the pulse is running + """Return True when the pulse generator is idle and ready to accept a new start trigger. + + Reads the READY register (addr 1, bit 0). While the pulse is running (including all configured repetitions) this reads False. - The `@property` decorator makes this an attribute-like access — call it + The `@property` decorator makes this an attribute-like access - call it without parentheses as ``daq["pulse0"].is_ready``, not ``.is_ready()``. `.is_done()` is an alias that returns the same value. @@ -89,14 +83,13 @@ def is_ready(self): return self.READY def set_en(self, value): - """ + """Configure whether the pulse synchronizes with an external trigger. + If true: The pulse comes with a fixed delay with respect to the external trigger (EXT_START). If false: The pulse comes only at software start. """ self.EN = value def get_en(self): - """ - Return info if pulse starts with a fixed delay w.r.t. shift register finish signal (true) or if it only starts with .start() (false) - """ + """Return whether the pulse uses a fixed delay w.r.t. the shift register finish signal.""" return self.EN diff --git a/basil/HL/spi.py b/basil/HL/spi.py index e958fce2e..befdca83b 100644 --- a/basil/HL/spi.py +++ b/basil/HL/spi.py @@ -4,13 +4,13 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # +"""Serial programming interface (SPI) driver for FPGA-based SPI modules.""" from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer class spi(RegisterHardwareLayer): - """ - Implement serial programming interface (SPI) driver.""" + """Implement serial programming interface (SPI) driver.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -26,10 +26,12 @@ class spi(RegisterHardwareLayer): _require_version = "==2" def __init__(self, intf, conf): + """Initialize SPI driver.""" super(spi, self).__init__(intf, conf) self._spi_mem_offset = 16 # in bytes def init(self): + """Initialize hardware layer and query memory bytes.""" super(spi, self).init() self._mem_bytes = self.MEM_BYTES @@ -38,71 +40,64 @@ def reset(self): self.RESET = 0 def start(self): - """ - Starts the shifting data - """ + """Start shifting data.""" self.START = 0 def set_size(self, value): - """ - Number of clock cycles for shifting in data - ex. length of matrix shift register (number of pixels daisy chained) + """Set the number of clock cycles for shifting in data. + + For example, length of matrix shift register (number of pixels daisy chained). """ self.SIZE = value def get_size(self): - """ - Get size of shift register length - """ + """Get size of shift register length.""" return self.SIZE def set_wait(self, value): - """ - Sets time delay between repetitions in clock cycles + """Set the time delay between repetitions in clock cycles. + + Time delay between repetitions in clock cycles. """ self.WAIT = value def get_wait(self): - """ - Gets time delay between repetitions in clock cycles - """ + """Get time delay between repetitions in clock cycles.""" return self.WAIT def set_repeat(self, value): - """ - If 0: Repeat sequence forever - Other: Number of repetitions of sequence with delay 'wait' + """Set the number of repetitions of the sequence with delay 'wait'. + + If 0: Repeat sequence forever. + Otherwise: Number of repetitions of sequence with delay 'wait'. """ self.REPEAT = value def get_repeat(self): - """ - Gets Number of repetitions of sequence with delay 'wait' (if 0 --> repeat forever) - """ + """Get number of repetitions of sequence with delay 'wait' (if 0 --> repeat forever).""" return self.REPEAT def set_en(self, value): - """ - Enable start on external EXT_START signal (inside FPGA) + """Enable start on external EXT_START signal (inside FPGA). + + When enabled, the SPI transfer starts on the external EXT_START signal. """ self.EN = value def get_en(self): - """ - Gets state of enable. - """ + """Return the enable state.""" return self.EN def is_done(self): - """ - Return True if the SPI transfer is complete, False if still in progress. Aliases is_ready. + """Return True if the SPI transfer is complete, False if still in progress. + + Aliases is_ready. """ return self.is_ready @property def is_ready(self): - """ - Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" + """Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" return self.READY def get_mem_size(self): @@ -110,9 +105,14 @@ def get_mem_size(self): return self.MEM_BYTES def set_data(self, data, addr=0): - """ - Write data to the SPI transmit memory at the bus memory offset. Data bytes are shifted out MSB-first on SDI. - Args: data (bytes), addr (int, optional byte offset into memory). + """Write data to the SPI transmit memory at the bus memory offset. + + Data bytes are shifted out MSB-first on SDI. + + Args: + data (bytes): Data to write. + addr (int, optional): Byte offset into memory. + """ if self._mem_bytes < len(data): raise ValueError("Size of data (%d bytes) is too big for memory (%d bytes)" % (len(data), self._mem_bytes)) @@ -120,9 +120,14 @@ def set_data(self, data, addr=0): # This needs to be changed to return written value def get_data(self, size=None, addr=None): - """ - Read data from the SPI receive memory at the bus memory offset. Incoming bytes captured from SDO are stored here. - Args: size (int, number of bytes to read, default all), addr (int, optional byte offset). + """Read data from the SPI receive memory at the bus memory offset. + + Incoming bytes captured from SDO are stored here. + + Args: + size (int, optional): Number of bytes to read (default all). + addr (int, optional): Byte offset into memory. + """ # readback memory offset if addr is None: From 3637142c7568d044286b014db7a391255b87b622 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 18:19:03 +0200 Subject: [PATCH 28/43] fix(fast_spi_rx): Bump firmware version to 1 for DATA_SIZE register Add DATA_SIZE read-only register at addr 4 requires version bump from 0 to 1. Update _require_version in Python driver to match. --- basil/HL/fast_spi_rx.py | 2 +- basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index 2f154a85b..085b81b67 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -37,7 +37,7 @@ class fast_spi_rx(RegisterHardwareLayer): "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, "DATA_SIZE": {"descr": {"addr": 4, "size": 8, "properties": ["ro"]}}, } - _require_version = "==0" + _require_version = "==1" def __init__(self, intf, conf): """Initialize the fast_spi_rx hardware layer. diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index c1c688753..8da5d7b67 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -37,7 +37,7 @@ module fast_spi_rx_core #( input wire BUS_RD ); -localparam VERSION = 0; +localparam VERSION = 1; // Output format #ID (as parameter IDENTIFIER + 12 id-frame + 16 bit data) From b53a283f67ea475271f8b49c621bb4da86d52218 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 17:54:53 +0200 Subject: [PATCH 29/43] feat(fast_spi_rx): Expose DATA_SIZE as read-only register at addr 4 - Add DATA_SIZE register (addr 4, ro) to the register decode in fast_spi_rx_core.v so the hardware parameter can be read back - Remove set_size from the Python driver; get_size now reads HW - Remove DATA_SIZE from YAML config (no longer needed) - Fix typo 'syncrhonized' -> 'synchronized' in fast_spi_rx_core.v - Fix docstring style: opening """ on its own line for multi-line - Delete bus_check.py utility (to be rewritten later) - Add Kian, Christian, and Rasmus to authors list in pyproject.toml --- basil/HL/fast_spi_rx.py | 2 +- basil/HL/gpio.py | 6 ++++-- basil/HL/pulse_gen.py | 12 ++++++++---- basil/HL/seq_gen.py | 21 ++++++++++++++------- basil/HL/spi.py | 6 ++++-- 5 files changed, 31 insertions(+), 16 deletions(-) diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index 085b81b67..2f154a85b 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -37,7 +37,7 @@ class fast_spi_rx(RegisterHardwareLayer): "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, "DATA_SIZE": {"descr": {"addr": 4, "size": 8, "properties": ["ro"]}}, } - _require_version = "==1" + _require_version = "==0" def __init__(self, intf, conf): """Initialize the fast_spi_rx hardware layer. diff --git a/basil/HL/gpio.py b/basil/HL/gpio.py index 7c82fd339..b0d5d99eb 100644 --- a/basil/HL/gpio.py +++ b/basil/HL/gpio.py @@ -48,7 +48,8 @@ def reset(self): self.RESET = 0 def set_output_en(self, value): - """Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" + """ + Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" self.OUTPUT_EN = value def get_output_en(self): @@ -56,7 +57,8 @@ def get_output_en(self): return self.OUTPUT_EN def set_data(self, value): - """Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" + """ + Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" self.OUTPUT = value def get_data(self): diff --git a/basil/HL/pulse_gen.py b/basil/HL/pulse_gen.py index f80b3732f..ba41b8074 100644 --- a/basil/HL/pulse_gen.py +++ b/basil/HL/pulse_gen.py @@ -34,7 +34,8 @@ def start(self): self.START = 0 def reset(self): - """Soft reset the pulse generator. Clears internal state on the next clock edge.""" + """ + Soft reset the pulse generator. Clears internal state on the next clock edge.""" self.RESET = 0 def set_delay(self, value): @@ -45,7 +46,8 @@ def set_delay(self, value): self.DELAY = value def get_delay(self): - """Return the pulse delay in clock cycles.""" + """ + Return the pulse delay in clock cycles.""" return self.DELAY def set_width(self, value): @@ -53,7 +55,8 @@ def set_width(self, value): self.WIDTH = value def get_width(self): - """Return the pulse width in clock cycles.""" + """ + Return the pulse width in clock cycles.""" return self.WIDTH def set_repeat(self, value): @@ -61,7 +64,8 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """Return the repeat count.""" + """ + Return the repeat count.""" return self.REPEAT def is_done(self): diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index 6846f209b..3c3c46667 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -10,7 +10,8 @@ class seq_gen(RegisterHardwareLayer): - """Sequence generator controller interface for seq_gen FPGA module.""" + """ + Sequence generator controller interface for seq_gen FPGA module.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -66,7 +67,8 @@ def set_size(self, value): self.SIZE = value def get_size(self): - """Return the configured sequence size in output words.""" + """ + Return the configured sequence size in output words.""" return self.SIZE def set_wait(self, value): @@ -77,7 +79,8 @@ def set_wait(self, value): self.WAIT = value def get_wait(self): - """Return the configured wait cycles between repetitions.""" + """ + Return the configured wait cycles between repetitions.""" return self.WAIT def set_clk_divide(self, value): @@ -89,7 +92,8 @@ def set_clk_divide(self, value): self.CLK_DIV = value def get_clk_divide(self): - """Return the clock division factor.""" + """ + Return the clock division factor.""" return self.CLK_DIV def set_repeat_start(self, value): @@ -101,7 +105,8 @@ def set_repeat_start(self, value): self.REPEAT_START = value def get_repeat_start(self): - """Return the repeat start position.""" + """ + Return the repeat start position.""" return self.REPEAT_START def set_repeat(self, value): @@ -113,7 +118,8 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """Return the repeat count.""" + """ + Return the repeat count.""" return self.REPEAT def is_done(self): @@ -154,7 +160,8 @@ def set_en_ext_start(self, value): self.EN_EXT_START = value def get_en_ext_start(self): - """Return whether external start is enabled.""" + """ + Return whether external start is enabled.""" return self.EN_EXT_START def set_nested_start(self, value): diff --git a/basil/HL/spi.py b/basil/HL/spi.py index befdca83b..0791d2c66 100644 --- a/basil/HL/spi.py +++ b/basil/HL/spi.py @@ -10,7 +10,8 @@ class spi(RegisterHardwareLayer): - """Implement serial programming interface (SPI) driver.""" + """ + Implement serial programming interface (SPI) driver.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -97,7 +98,8 @@ def is_done(self): @property def is_ready(self): - """Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" + """ + Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" return self.READY def get_mem_size(self): From 30c53dbb3c57fd38a3fbc6f8123cf5683fa8897e Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 18:34:21 +0200 Subject: [PATCH 30/43] fix: Remove authors accidentally reintroduced during rebase --- pyproject.toml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 08d7b3ef4..c9d164fbc 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -12,10 +12,7 @@ requires-python = ">=3.10" authors = [ {name = "Tomasz Hemperek", email="hemperek@uni-bonn.de"}, {name = "Jens Janssen", email="janssen@physik.uni-bonn.de"}, - {name = "David-Leon Pohl", email="pohl@physik.uni-bonn.de"}, - {name = "Kian Caisley", email="kcaisley@uni-bonn.de"}, - {name = "Christian Bespin", email="bespin@physik.uni-bonn.de"}, - {name = "Rasmus Partzsch", email="partzsch@physik.uni-bonn.de"}, + {name = "David-Leon Pohl", email="pohl@physik.uni-bonn.de"} ] maintainers = [ From 37b3e10df01ab47df1dd435fb57692102b3c6302 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 20 May 2026 18:43:16 +0200 Subject: [PATCH 31/43] fix: Correct straggling mis-formatted doc strings --- basil/HL/gpio.py | 6 ++---- basil/HL/pulse_gen.py | 12 ++++-------- basil/HL/seq_gen.py | 21 +++++++-------------- basil/HL/spi.py | 6 ++---- 4 files changed, 15 insertions(+), 30 deletions(-) diff --git a/basil/HL/gpio.py b/basil/HL/gpio.py index b0d5d99eb..7c82fd339 100644 --- a/basil/HL/gpio.py +++ b/basil/HL/gpio.py @@ -48,8 +48,7 @@ def reset(self): self.RESET = 0 def set_output_en(self, value): - """ - Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" + """Set the output enable mask. Each bit enables output mode for the corresponding pin (1=output, 0=high-impedance/input). Requires IO_TRI to be configured in the firmware parameter.""" self.OUTPUT_EN = value def get_output_en(self): @@ -57,8 +56,7 @@ def get_output_en(self): return self.OUTPUT_EN def set_data(self, value): - """ - Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" + """Set the GPIO OUTPUT register. Writes the full IO_WIDTH byte to the FPGA, driving output pins to the specified logic levels. Typically used via StdRegister .write() for field-level access.""" self.OUTPUT = value def get_data(self): diff --git a/basil/HL/pulse_gen.py b/basil/HL/pulse_gen.py index ba41b8074..f80b3732f 100644 --- a/basil/HL/pulse_gen.py +++ b/basil/HL/pulse_gen.py @@ -34,8 +34,7 @@ def start(self): self.START = 0 def reset(self): - """ - Soft reset the pulse generator. Clears internal state on the next clock edge.""" + """Soft reset the pulse generator. Clears internal state on the next clock edge.""" self.RESET = 0 def set_delay(self, value): @@ -46,8 +45,7 @@ def set_delay(self, value): self.DELAY = value def get_delay(self): - """ - Return the pulse delay in clock cycles.""" + """Return the pulse delay in clock cycles.""" return self.DELAY def set_width(self, value): @@ -55,8 +53,7 @@ def set_width(self, value): self.WIDTH = value def get_width(self): - """ - Return the pulse width in clock cycles.""" + """Return the pulse width in clock cycles.""" return self.WIDTH def set_repeat(self, value): @@ -64,8 +61,7 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """ - Return the repeat count.""" + """Return the repeat count.""" return self.REPEAT def is_done(self): diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index 3c3c46667..6846f209b 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -10,8 +10,7 @@ class seq_gen(RegisterHardwareLayer): - """ - Sequence generator controller interface for seq_gen FPGA module.""" + """Sequence generator controller interface for seq_gen FPGA module.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -67,8 +66,7 @@ def set_size(self, value): self.SIZE = value def get_size(self): - """ - Return the configured sequence size in output words.""" + """Return the configured sequence size in output words.""" return self.SIZE def set_wait(self, value): @@ -79,8 +77,7 @@ def set_wait(self, value): self.WAIT = value def get_wait(self): - """ - Return the configured wait cycles between repetitions.""" + """Return the configured wait cycles between repetitions.""" return self.WAIT def set_clk_divide(self, value): @@ -92,8 +89,7 @@ def set_clk_divide(self, value): self.CLK_DIV = value def get_clk_divide(self): - """ - Return the clock division factor.""" + """Return the clock division factor.""" return self.CLK_DIV def set_repeat_start(self, value): @@ -105,8 +101,7 @@ def set_repeat_start(self, value): self.REPEAT_START = value def get_repeat_start(self): - """ - Return the repeat start position.""" + """Return the repeat start position.""" return self.REPEAT_START def set_repeat(self, value): @@ -118,8 +113,7 @@ def set_repeat(self, value): self.REPEAT = value def get_repeat(self): - """ - Return the repeat count.""" + """Return the repeat count.""" return self.REPEAT def is_done(self): @@ -160,8 +154,7 @@ def set_en_ext_start(self, value): self.EN_EXT_START = value def get_en_ext_start(self): - """ - Return whether external start is enabled.""" + """Return whether external start is enabled.""" return self.EN_EXT_START def set_nested_start(self, value): diff --git a/basil/HL/spi.py b/basil/HL/spi.py index 0791d2c66..befdca83b 100644 --- a/basil/HL/spi.py +++ b/basil/HL/spi.py @@ -10,8 +10,7 @@ class spi(RegisterHardwareLayer): - """ - Implement serial programming interface (SPI) driver.""" + """Implement serial programming interface (SPI) driver.""" _registers = { "RESET": {"descr": {"addr": 0, "size": 8, "properties": ["writeonly"]}}, @@ -98,8 +97,7 @@ def is_done(self): @property def is_ready(self): - """ - Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" + """Read the DONE/READY register at address 1. Returns True when the transfer is complete, False while shifting.""" return self.READY def get_mem_size(self): From be655090a64f6d4eee27e834e6a0010aaa693eb9 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Fri, 22 May 2026 23:46:06 +0200 Subject: [PATCH 32/43] fix: update Verilog simulation primitives --- .../modules/utils/{DCM_sim.v => DCM.v} | 7 +++++ basil/firmware/modules/utils/IBUF.v | 10 ++++++- basil/firmware/modules/utils/IBUFG.v | 26 +++++++++++++++++ basil/firmware/modules/utils/IBUFGDS.v | 8 ++++- basil/firmware/modules/utils/IOBUF.v | 16 ++++++++-- basil/firmware/modules/utils/OBUF.v | 11 ++++++- basil/firmware/modules/utils/OBUFDS.v | 8 ++++- basil/firmware/modules/utils/ODDR.v | 29 ++++++++++--------- .../{RAMB16_S1_S2_sim.v => RAMB16_S1_S2.v} | 7 +++++ .../{RAMB16_S1_S9_sim.v => RAMB16_S1_S9.v} | 7 +++++ basil/firmware/modules/utils/README.rst | 7 +++-- .../mio_pixel/tests/test_Sim_mio_pixel.py | 8 ++--- examples/mio_sram_test/tests/test_Sim.py | 2 +- tests/test_SimAdcRx.v | 23 --------------- tests/test_SimCmdSeq.v | 17 ++--------- tests/test_SimI2c.v | 11 ++----- tests/test_SimJtagMaster.v | 19 +----------- tests/test_SimM26.v | 17 +---------- tests/test_SimSpi.v | 18 ------------ tests/test_SimTdc.v | 19 ++---------- tests/test_SimTdl_Tdc.v | 12 ++------ tests/test_SimTimestamp.v | 19 ++---------- 22 files changed, 130 insertions(+), 171 deletions(-) rename basil/firmware/modules/utils/{DCM_sim.v => DCM.v} (97%) create mode 100644 basil/firmware/modules/utils/IBUFG.v rename basil/firmware/modules/utils/{RAMB16_S1_S2_sim.v => RAMB16_S1_S2.v} (94%) rename basil/firmware/modules/utils/{RAMB16_S1_S9_sim.v => RAMB16_S1_S9.v} (94%) diff --git a/basil/firmware/modules/utils/DCM_sim.v b/basil/firmware/modules/utils/DCM.v similarity index 97% rename from basil/firmware/modules/utils/DCM_sim.v rename to basil/firmware/modules/utils/DCM.v index e04df01fd..4f05347ca 100644 --- a/basil/firmware/modules/utils/DCM_sim.v +++ b/basil/firmware/modules/utils/DCM.v @@ -1,9 +1,13 @@ /** Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx */ +`ifndef BASIL_UTILS_DCM_V +`define BASIL_UTILS_DCM_V + `timescale 1ps/1ps `default_nettype none + module clock_divider_sim #( parameter DIVISOR = 2 ) ( @@ -129,5 +133,8 @@ clock_divider_sim #( ); assign LOCKED = 1'b1; +assign PSDONE = 1'b0; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUF.v b/basil/firmware/modules/utils/IBUF.v index f4bf337f4..2e28cfbb1 100644 --- a/basil/firmware/modules/utils/IBUF.v +++ b/basil/firmware/modules/utils/IBUF.v @@ -4,11 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IBUF_V +`define BASIL_UTILS_IBUF_V + `timescale 1ps/1ps `default_nettype none -module IBUF ( +module IBUF #( + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT" +) ( output wire O, input wire I ); @@ -16,3 +22,5 @@ module IBUF ( assign O = I; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUFG.v b/basil/firmware/modules/utils/IBUFG.v new file mode 100644 index 000000000..c81100aaa --- /dev/null +++ b/basil/firmware/modules/utils/IBUFG.v @@ -0,0 +1,26 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`ifndef BASIL_UTILS_IBUFG_V +`define BASIL_UTILS_IBUFG_V + +`timescale 1ps/1ps +`default_nettype none + + +module IBUFG #( + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT" +) ( + output wire O, + input wire I +); + +assign O = I; + +endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUFGDS.v b/basil/firmware/modules/utils/IBUFGDS.v index d9ef8bb0e..d301f184c 100644 --- a/basil/firmware/modules/utils/IBUFGDS.v +++ b/basil/firmware/modules/utils/IBUFGDS.v @@ -4,12 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IBUFGDS_V +`define BASIL_UTILS_IBUFGDS_V + `timescale 1ps/1ps `default_nettype none module IBUFGDS #( parameter DIFF_TERM = "TRUE", - parameter IOSTANDARD = "LVDS_25" + parameter IBUF_LOW_PWR = "FALSE", + parameter IOSTANDARD = "LVDS_25" ) ( output wire O, input wire I, IB @@ -18,3 +22,5 @@ module IBUFGDS #( assign O = I && !IB; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IOBUF.v b/basil/firmware/modules/utils/IOBUF.v index b168d7742..d752a03f2 100644 --- a/basil/firmware/modules/utils/IOBUF.v +++ b/basil/firmware/modules/utils/IOBUF.v @@ -4,18 +4,28 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IOBUF_V +`define BASIL_UTILS_IOBUF_V + `timescale 1ps/1ps `default_nettype none -module IOBUF ( +module IOBUF #( + parameter DRIVE = 12, + parameter IBUF_LOW_PWR = "TRUE", + parameter IOSTANDARD = "DEFAULT", + parameter SLEW = "SLOW" +) ( inout wire IO, input wire I, output wire O, input wire T ); -assign IO = T ? I : 1'bz; -assign O = T ? IO : 1'b0; +assign IO = T ? 1'bz : I; +assign O = IO; endmodule + +`endif diff --git a/basil/firmware/modules/utils/OBUF.v b/basil/firmware/modules/utils/OBUF.v index 0b0d77a5b..91c49c849 100644 --- a/basil/firmware/modules/utils/OBUF.v +++ b/basil/firmware/modules/utils/OBUF.v @@ -4,11 +4,18 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_OBUF_V +`define BASIL_UTILS_OBUF_V + `timescale 1ps/1ps `default_nettype none -module OBUF ( +module OBUF #( + parameter DRIVE = 12, + parameter IOSTANDARD = "DEFAULT", + parameter SLEW = "SLOW" +) ( output wire O, input wire I ); @@ -16,3 +23,5 @@ module OBUF ( assign O = I; endmodule + +`endif diff --git a/basil/firmware/modules/utils/OBUFDS.v b/basil/firmware/modules/utils/OBUFDS.v index 8d27c3cc9..655285e4a 100644 --- a/basil/firmware/modules/utils/OBUFDS.v +++ b/basil/firmware/modules/utils/OBUFDS.v @@ -4,11 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_OBUFDS_V +`define BASIL_UTILS_OBUFDS_V + `timescale 1ps/1ps `default_nettype none module OBUFDS #( - parameter IOSTANDARD = "LVDS_25" + parameter IOSTANDARD = "LVDS_25", + parameter SLEW = "SLOW" ) ( output wire O, OB, input wire I @@ -18,3 +22,5 @@ assign O = I; assign OB = !I; endmodule + +`endif diff --git a/basil/firmware/modules/utils/ODDR.v b/basil/firmware/modules/utils/ODDR.v index a040c323e..af5ece84e 100644 --- a/basil/firmware/modules/utils/ODDR.v +++ b/basil/firmware/modules/utils/ODDR.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_ODDR_V +`define BASIL_UTILS_ODDR_V + `timescale 1ps/1ps `default_nettype none @@ -13,7 +16,7 @@ module ODDR #( parameter INIT = 1'b0, parameter SRTYPE = "SYNC" )( - output reg Q, + output wire Q, input wire C, input wire CE, input wire D1, @@ -22,18 +25,16 @@ module ODDR #( input wire S ); -always @(posedge C or negedge C) begin - if (R) begin - Q <= INIT; - end else if (CE) begin - if (DDR_CLK_EDGE == "OPPOSITE_EDGE") begin - if (C) Q <= D2; - else Q <= D1; - end else begin - if (C) Q <= D1; - else Q <= D2; - end - end -end +reg Q1, Q2; + +always @(posedge C) + Q1 <= D1; + +always @(negedge C) + Q2 <= D2; + +assign Q = C ? Q1 & CE : Q2 & CE; endmodule + +`endif diff --git a/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v b/basil/firmware/modules/utils/RAMB16_S1_S2.v similarity index 94% rename from basil/firmware/modules/utils/RAMB16_S1_S2_sim.v rename to basil/firmware/modules/utils/RAMB16_S1_S2.v index 508dd1640..c67b1b1e8 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S2.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_RAMB16_S1_S2_V +`define BASIL_UTILS_RAMB16_S1_S2_V + `timescale 1ps/1ps `default_nettype none @@ -29,6 +32,8 @@ input wire SSRB; input wire DIPB; output wire DOPB; +assign DOPB = 1'b0; + parameter WIDTHA = 1; parameter SIZEA = 16384; parameter ADDRWIDTHA = 14; @@ -68,3 +73,5 @@ end endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v b/basil/firmware/modules/utils/RAMB16_S1_S9.v similarity index 94% rename from basil/firmware/modules/utils/RAMB16_S1_S9_sim.v rename to basil/firmware/modules/utils/RAMB16_S1_S9.v index fc782ce52..e0adc17ab 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S9.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_RAMB16_S1_S9_V +`define BASIL_UTILS_RAMB16_S1_S9_V + `timescale 1ps/1ps `default_nettype none @@ -29,6 +32,8 @@ input wire SSRB; input wire DIPB; output wire DOPB; +assign DOPB = 1'b0; + parameter WIDTHA = 1; parameter SIZEA = 16384; parameter ADDRWIDTHA = 14; @@ -71,3 +76,5 @@ end endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/utils/README.rst b/basil/firmware/modules/utils/README.rst index 2f463fc93..4c06a61d9 100644 --- a/basil/firmware/modules/utils/README.rst +++ b/basil/firmware/modules/utils/README.rst @@ -18,12 +18,13 @@ Various Verilog modules used by basil. - flag_domain_crossing - flag_domain_crossing_ce - generic_fifo +- IDDR - IDDR_s3 -- IDDR_sim +- ODDR - ODDR_s3 - pulse_gen_rising -- RAMB16_S1_S2_sim -- RAMB16_S1_S9_sim +- RAMB16_S1_S2 +- RAMB16_S1_S9 - rbcp_to_bus - reset_gen - simple_arbiter diff --git a/examples/mio_pixel/tests/test_Sim_mio_pixel.py b/examples/mio_pixel/tests/test_Sim_mio_pixel.py index edb898607..ead5db39a 100644 --- a/examples/mio_pixel/tests/test_Sim_mio_pixel.py +++ b/examples/mio_pixel/tests/test_Sim_mio_pixel.py @@ -32,15 +32,15 @@ def setUp(self): os.path.join(fw_path, "utils/reset_gen.v"), os.path.join(fw_path, "utils/bus_to_ip.v"), os.path.join(fw_path, "rrp_arbiter/rrp_arbiter.v"), - os.path.join(fw_path, "utils/ODDR_sim.v"), + os.path.join(fw_path, "utils/ODDR.v"), os.path.join(fw_path, "utils/generic_fifo.v"), os.path.join(fw_path, "utils/cdc_pulse_sync.v"), os.path.join(fw_path, "utils/fx2_to_bus.v"), - os.path.join(fw_path, "utils/BUFG_sim.v"), + os.path.join(fw_path, "utils/BUFG.v"), os.path.join(fw_path, "utils/cdc_syncfifo.v"), os.path.join(fw_path, "utils/ddr_des.v"), - os.path.join(fw_path, "utils/IDDR_sim.v"), - os.path.join(fw_path, "utils/DCM_sim.v"), + os.path.join(fw_path, "utils/IDDR.v"), + os.path.join(fw_path, "utils/DCM.v"), os.path.join(fw_path, "utils/clock_divider.v"), os.path.join(fw_path, "utils/clock_multiplier.v"), os.path.join(fw_path, "utils/flag_domain_crossing.v"), diff --git a/examples/mio_sram_test/tests/test_Sim.py b/examples/mio_sram_test/tests/test_Sim.py index 4faf303da..b1a184b38 100644 --- a/examples/mio_sram_test/tests/test_Sim.py +++ b/examples/mio_sram_test/tests/test_Sim.py @@ -28,7 +28,7 @@ def setUp(self): os.path.join(fw_path, "utils/reset_gen.v"), os.path.join(fw_path, "utils/bus_to_ip.v"), os.path.join(fw_path, "rrp_arbiter/rrp_arbiter.v"), - os.path.join(fw_path, "utils/ODDR_sim.v"), + os.path.join(fw_path, "utils/ODDR.v"), os.path.join(fw_path, "utils/generic_fifo.v"), os.path.join(fw_path, "utils/cdc_pulse_sync.v"), os.path.join(fw_path, "utils/3_stage_synchronizer.v"), diff --git a/tests/test_SimAdcRx.v b/tests/test_SimAdcRx.v index b7adc288d..c23678a64 100644 --- a/tests/test_SimAdcRx.v +++ b/tests/test_SimAdcRx.v @@ -7,35 +7,12 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "utils/cdc_pulse_sync.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - `include "spi/spi.v" -`include "spi/spi_core.v" -`include "spi/blk_mem_gen_8_to_1_2k.v" -`include "utils/RAMB16_S1_S9_sim.v" - -`include "utils/CG_MOD_pos.v" - -`include "gpac_adc_rx/gpac_adc_rx_core.v" `include "gpac_adc_rx/gpac_adc_rx.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" - -`include "utils/generic_fifo.v" -`include "utils/cdc_syncfifo.v" -`include "utils/pulse_gen_rising.v" `include "utils/clock_divider.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/cdc_reset_sync.v" module tb ( input wire BUS_CLK, diff --git a/tests/test_SimCmdSeq.v b/tests/test_SimCmdSeq.v index f8b41eebe..ecd70b4d6 100644 --- a/tests/test_SimCmdSeq.v +++ b/tests/test_SimCmdSeq.v @@ -7,23 +7,10 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - `include "cmd_seq/cmd_seq.v" -`include "cmd_seq/cmd_seq_core.v" - `include "seq_rec/seq_rec.v" -`include "seq_rec/seq_rec_core.v" -`include "utils/ramb_8_to_n.v" - -// `include "utils/glbl.v" -`include "utils/ODDR_sim.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/flag_domain_crossing.v" +`include "utils/ODDR.v" module tb ( input wire BUS_CLK, @@ -106,7 +93,7 @@ end reg CMD_DATA_FF; always @(posedge BUS_CLK) begin - CMD_DATA_FF <= CMD_DATA; // delay data, SEQ_EXT_START signal hast to come first by 1 clock cycle + CMD_DATA_FF <= CMD_DATA; // delay data, SEQ_EXT_START signal has to come first by 1 clock cycle end reg CMD_READY_FF, CMD_READY_FF2, CMD_READY_FF3; diff --git a/tests/test_SimI2c.v b/tests/test_SimI2c.v index d81722f2f..10360d4d5 100644 --- a/tests/test_SimI2c.v +++ b/tests/test_SimI2c.v @@ -8,17 +8,10 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "i2c/i2c.v" -`include "i2c/i2c_core.v" - -`include "utils/cdc_pulse_sync.v" `include "utils/clock_divider.v" - - -`include "utils/ODDR_sim.v" -`include "utils/IDDR_sim.v" +`include "utils/ODDR.v" +`include "utils/IDDR.v" module i2c_slave_model ( diff --git a/tests/test_SimJtagMaster.v b/tests/test_SimJtagMaster.v index 4283560f3..ff13c7543 100644 --- a/tests/test_SimJtagMaster.v +++ b/tests/test_SimJtagMaster.v @@ -7,28 +7,11 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "gpio/gpio_core.v" `include "gpio/gpio.v" - -`include "spi/blk_mem_gen_8_to_1_2k.v" -`include "utils/ramb_8_to_n.v" `include "jtag_master/jtag_master.v" -`include "jtag_master/jtag_master_core.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - -`include "utils/cdc_pulse_sync.v" -`include "utils/cdc_reset_sync.v" -`include "utils/CG_MOD_pos.v" -`include "utils/clock_divider.v" - -`include "utils/RAMB16_S1_S9_sim.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" -`include "utils/generic_fifo.v" +`include "utils/clock_divider.v" module tb ( input wire BUS_CLK, diff --git a/tests/test_SimM26.v b/tests/test_SimM26.v index e974321a1..c2f9ee76c 100644 --- a/tests/test_SimM26.v +++ b/tests/test_SimM26.v @@ -7,25 +7,10 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - `include "m26_rx/m26_rx.v" -`include "m26_rx/m26_rx_core.v" -`include "m26_rx/m26_rx_ch.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/generic_fifo.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/flag_domain_crossing.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" -`include "utils/IDDR_sim.v" +`include "utils/IDDR.v" module tb ( input wire BUS_CLK, diff --git a/tests/test_SimSpi.v b/tests/test_SimSpi.v index a21bbeff6..b14aa1308 100644 --- a/tests/test_SimSpi.v +++ b/tests/test_SimSpi.v @@ -14,30 +14,12 @@ `endif `ifndef BASIL_SBUS - `include "utils/bus_to_ip.v" - `include "gpio/gpio_core.v" `include "gpio/gpio.v" - `include "spi/spi.v" - `include "spi/spi_core.v" - `include "spi/blk_mem_gen_8_to_1_2k.v" - `include "pulse_gen/pulse_gen.v" - `include "pulse_gen/pulse_gen_core.v" - - `include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" - `include "fast_spi_rx/fast_spi_rx.v" - `include "fast_spi_rx/fast_spi_rx_core.v" - - `include "utils/cdc_syncfifo.v" - `include "utils/generic_fifo.v" - `include "utils/cdc_pulse_sync.v" - `include "utils/CG_MOD_pos.v" `include "utils/clock_divider.v" - `include "utils/3_stage_synchronizer.v" - `include "utils/RAMB16_S1_S9_sim.v" `else $fatal("Sbus modules not implemented yet"); `endif diff --git a/tests/test_SimTdc.v b/tests/test_SimTdc.v index 821ba43a0..3890de4a1 100644 --- a/tests/test_SimTdc.v +++ b/tests/test_SimTdc.v @@ -8,28 +8,13 @@ `timescale 1ps / 1ps `include "utils/clock_multiplier.v" -`include "utils/DCM_sim.v" -`include "utils/IDDR_sim.v" +`include "utils/DCM.v" +`include "utils/IDDR.v" `include "utils/ddr_des.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - -`include "tdc_s3/tdc_s3_core.v" `include "tdc_s3/tdc_s3.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" -`include "utils/bus_to_ip.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/flag_domain_crossing.v" -`include "utils/generic_fifo.v" -`include "utils/3_stage_synchronizer.v" - module tb ( input wire BUS_CLK, diff --git a/tests/test_SimTdl_Tdc.v b/tests/test_SimTdl_Tdc.v index cd80d49d1..1b9403ce8 100644 --- a/tests/test_SimTdl_Tdc.v +++ b/tests/test_SimTdl_Tdc.v @@ -9,17 +9,11 @@ `timescale 1ps / 1ps `include "utils/clock_multiplier.v" +`include "utils/DCM.v" `include "utils/clock_divider.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" -`include "utils/ramb_8_to_n.v" - -`include "tdl_tdc/tdc.v" - -`include "bram_fifo/bram_fifo_core.v" +`include "tdl_tdc/tdl_tdc.v" `include "bram_fifo/bram_fifo.v" - `include "utils/bus_to_ip.v" @@ -61,7 +55,7 @@ assign TDC_IN[2] = SEQ_OUT[1]; assign TDC_ARM = SEQ_OUT[2]; assign TDC_EXT_EN = SEQ_OUT[3]; -wire CLK_160, CLK_480, CLK_160_TO_DCM, +wire CLK_160, CLK_480, CLK_160_TO_DCM; DCM #( .CLKFX_MULTIPLY(20), diff --git a/tests/test_SimTimestamp.v b/tests/test_SimTimestamp.v index 6ecbccd6b..4b5e87cd9 100644 --- a/tests/test_SimTimestamp.v +++ b/tests/test_SimTimestamp.v @@ -8,27 +8,12 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "gpio/gpio_core.v" `include "gpio/gpio.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" -`include "utils/clock_multiplier.v" - -`include "bram_fifo/bram_fifo_core.v" -`include "bram_fifo/bram_fifo.v" - `include "timestamp/timestamp.v" -`include "timestamp/timestamp_core.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/generic_fifo.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/CG_MOD_pos.v" +`include "bram_fifo/bram_fifo.v" `include "utils/clock_divider.v" -`include "utils/3_stage_synchronizer.v" -`include "utils/RAMB16_S1_S9_sim.v" +`include "utils/clock_multiplier.v" module tb ( From 356e84472c7e92d83035c4c79ffbf120c6e5c550 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Fri, 22 May 2026 23:46:19 +0200 Subject: [PATCH 33/43] feat: add KA3005P driver Require the fast_spi_rx hardware layer to match the existing firmware version 1. --- basil/HL/fast_spi_rx.py | 2 +- basil/HL/ka3005p.py | 89 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 basil/HL/ka3005p.py diff --git a/basil/HL/fast_spi_rx.py b/basil/HL/fast_spi_rx.py index 2f154a85b..085b81b67 100644 --- a/basil/HL/fast_spi_rx.py +++ b/basil/HL/fast_spi_rx.py @@ -37,7 +37,7 @@ class fast_spi_rx(RegisterHardwareLayer): "LOST_COUNT": {"descr": {"addr": 3, "size": 8, "properties": ["ro"]}}, "DATA_SIZE": {"descr": {"addr": 4, "size": 8, "properties": ["ro"]}}, } - _require_version = "==0" + _require_version = "==1" def __init__(self, intf, conf): """Initialize the fast_spi_rx hardware layer. diff --git a/basil/HL/ka3005p.py b/basil/HL/ka3005p.py new file mode 100644 index 000000000..2c4bca40a --- /dev/null +++ b/basil/HL/ka3005p.py @@ -0,0 +1,89 @@ +# +# ------------------------------------------------------------ +# Copyright (c) All rights reserved +# SiLab, Institute of Physics, University of Bonn +# ------------------------------------------------------------ +# + +"""Driver for the Korad KA3005P programmable DC power supply.""" + +import logging +from time import sleep + +from basil.HL.HardwareLayer import HardwareLayer + +logger = logging.getLogger(__name__) + + +class ka3005p(HardwareLayer): + """Driver for the Korad KA3005P programmable DC power supply. + + Communicates over a serial (RS-232) interface. Up to 30 V / 5 A. + """ + + def __init__(self, intf, conf): + super(ka3005p, self).__init__(intf, conf) + + def init(self): + """Initialize the power supply. + + Sets a safe current limit of 100 mA to protect the DUT. + """ + super(ka3005p, self).init() + self.set_current(0.1) + + def set_voltage(self, voltage): + """Set the output voltage. + + Args: + voltage: Output voltage in volts. Clipped to 30 V max. + """ + if voltage > 30: + voltage = 30 + cmd = "VSET1:%.2f" % round(voltage, 2) + self._intf.write(cmd) + sleep(0.05) + + def set_current(self, current): + """Set the output current limit. + + Args: + current: Current limit in amps. Clipped to 5 A max. + """ + if current > 5: + current = 5 + cmd = "ISET1:%.3f" % round(current, 3) + self._intf.write(cmd) + sleep(0.05) + + def enable_output(self): + """Enable the DC output (OUT1).""" + self._intf.write("OUT1") + sleep(0.5) + + def disable_output(self): + """Disable the DC output (OUT0).""" + self._intf.write("OUT0") + sleep(0.1) + + def get_voltage(self): + """Read back the actual output voltage. + + Returns: + float: Output voltage in volts. + """ + self._intf.write("VOUT1?") + sleep(0.1) + response = self._intf.read() + return float(response) + + def get_current(self): + """Read back the actual output current. + + Returns: + float: Output current in amps. + """ + self._intf.write("IOUT1?") + sleep(0.1) + response = self._intf.read() + return float(response) From e988ca41860062417ae49d3b9213045e4fd66e22 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Fri, 22 May 2026 23:46:28 +0200 Subject: [PATCH 34/43] feat: add JTAG TAP include module --- basil/firmware/modules/includes/jtag_tap.v | 575 +++++++++++++++++++++ 1 file changed, 575 insertions(+) create mode 100644 basil/firmware/modules/includes/jtag_tap.v diff --git a/basil/firmware/modules/includes/jtag_tap.v b/basil/firmware/modules/includes/jtag_tap.v new file mode 100644 index 000000000..a9b7ed3ed --- /dev/null +++ b/basil/firmware/modules/includes/jtag_tap.v @@ -0,0 +1,575 @@ +`ifndef BASIL_INCLUDES_JTAG_TAP_V +`define BASIL_INCLUDES_JTAG_TAP_V + +`timescale 1ps / 1ps + +/* JTAG TAP interface + + This module can be replaced with special JTAG TAP primitives on Xilinx and Altera FPGAs. + Those primitives have similar interfaces; if you plan to modify this module's interface, + make sure you do not make it incompatible with the other ones. + + About the clock: it would have been easier to use the system clock in this module, + but the JTAG TAP interface should be able to work and do boundary scans + even when the main system clock is disabled. Relying on the JTAG clock + means that somewhere down the line crossing clock domains becomes necessary, + which can slow JTAG firmware transfers down. + + About the delay in the is_tap_state_xxx signals: + The is_tap_state_xxx are all delivered to the submodules delayed by 1 TCK posedge, see + the comment below for more information. I am not sure whether these signals also + get delayed when using the JTAG TAP primitives on Xilinx or Altera FPGAs. + + + Author(s): + Igor Mohor (igorm@opencores.org) + Nathan Yawn (nathan.yawn@opencores.org) + R. Diez (in 2012) + + NOTE: R. Diez has rewritten this module substantially and since then + it has only been tested against the OR10 OpenRISC implementation. + + Copyright (C) 2000 - 2012 Authors + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License version 3 + as published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License version 3 for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program. If not, see . +*/ + +///////////////////////////// +//`include "simulator_features.v" +///////////////////////////// +`define UNIQUE //unique +`define FINISH_WITH_ERROR_EXIT_CODE //$finish +`define ASSERT_FALSE $display( "ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE + +///////////////////////////// +//`include "tap_defines.v" +//////////////////////////// +// This is similar to the IDCODE that the or1200 CPU uses, +// only the new part number (IQ) is the or1200's value + 100 (decimal). +`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // or1200 uses 32'h149511c3. + // 0001 bits [31:28], version + // 0100100110110101 bits [27:12], part number (IQ), 01001001010101010001 + 100 (decimal) + // 00011100001 bits [11: 1], manufacturer id (flextronics) + // 1 bit 0, always "1" as required by the JTAG standard + + +// JTAG Instructions. The Instruction Register is 4 bits long at the moment, +// but 3 bits would do. However, this optimisation is probably not worth the trouble. +`define JTAG_INSTRUCTION_EXTEST 4'b0000 // Not supported at the moment. +`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 // Not supported at the moment. +`define JTAG_INSTRUCTION_IDCODE 4'b0010 // Supported. +// The following command is specific to OR10. Because the Xilinx TAP primitives have just 1 or 2 user-defined +// JTAG instructions, all OR10 debug operations is performed with a single DEBUG instruction, +// which can be mapped to one of Xilinx' user-defined instructions when using that interface. +// If it weren't for this limitation, it would have been more comfortable to define +// several JTAG instructions for the different types of OR10 debug operations. +`define JTAG_INSTRUCTION_DEBUG 4'b1000 // Specific to OR10, see comment above. +`define JTAG_INSTRUCTION_MBIST 4'b1001 // Not supported at the moment. +`define JTAG_INSTRUCTION_BYPASS 4'b1111 // Supported. According to the JTAG specification, the BYPASS instruction opcode must be all 1's. + +module jtag_tap + #( parameter TRACE_JTAG_DATA = 0, + parameter TRACE_STATE_MACHINE_TRANSITIONS = 0 ) + ( + // JTAG pads + input jtag_tms_i, // If unconnected or not used, the JTAG standard requires a value of 1. + input jtag_tck_i, + input jtag_trstn_i, // Test reset. Asynchronous, active at logic level 0. Therefore, if unconnected or not used, apply a value of 1. + input jtag_tdi_i, // If unconnected or not used, the JTAG standard requires a value of 1. + output reg jtag_tdo_o, // This pin should be tri-stated when not shifting data, + // but this module does not support an extra jtag_tdo_enable_o signal yet. + + // These previous state signals are delayed by one TCK clock cycle: + // when a TAP submodule gets the next TCK rising edge, these signals + // indicate what state the TAP was in at the last TCK rising edge. + output reg is_tap_state_test_logic_reset_o, // One TCK posedge delay to reset the submodule is fine, as long as + // the next TCK posedge comes soon enough. + output reg is_tap_state_shift_dr_o, // One TCK posedge delay is fine, as bits are shifted on the next TCK posedge + // after entering the Shift-DR state. + output reg is_tap_state_update_dr_o, // One TCK posedge delay is usually fine, the register update will happen a little later. + // This may be a problem if the next TCK posedge does not come, or takes a long time to come. + output reg is_tap_state_capture_dr_o, // One TCK posedge delay is usually fine, the register capture will happen a little later. + // This may be a problem if the next TCK posedge does not come, or takes a long time to come. + + + // This signal is also delayed by one TCK clock cycle, + // but that does not matter, as the current instruction changes only + // in state Update-IR, and in that state all the is_tap_state_xxx signals are zero. + // When any of the is_tap_state_xxx signals become active again, + // this signal is already available. + output reg is_tap_current_instruction_debug_o, + + // TDI signal from the debug submodule. + //input debug_tdo_i //TH + output reg [31:0] debug_reg //TH + ); + + // Length of the Instruction register. + localparam IR_LENGTH = 4; + + localparam TRACE_PREFIX = "JTAG TAP: "; + + + // TAP State Machine, fully JTAG compliant. + + localparam STATE_test_logic_reset = 4'd0; // The actual state values do not matter. + localparam STATE_run_test_idle = 4'd1; + localparam STATE_select_dr_scan = 4'd2; + localparam STATE_capture_dr = 4'd3; + localparam STATE_shift_dr = 4'd4; + localparam STATE_exit1_dr = 4'd5; + localparam STATE_pause_dr = 4'd6; + localparam STATE_exit2_dr = 4'd7; + localparam STATE_update_dr = 4'd8; + localparam STATE_select_ir_scan = 4'd9; + localparam STATE_capture_ir = 4'd10; + localparam STATE_shift_ir = 4'd11; // Once you enter this state, you'll shift at least 1 bit of information, as the TCK posedge that exits the state does also transfer 1 bit. + localparam STATE_exit1_ir = 4'd12; + localparam STATE_pause_ir = 4'd13; + localparam STATE_exit2_ir = 4'd14; + localparam STATE_update_ir = 4'd15; + + reg [3:0] current_state; // Current state of the TAP controller. + + + reg [IR_LENGTH-1:0] jtag_ir; // The instruction register, when in state Capture-IR, gets a device-dependent status value. + reg [IR_LENGTH-1:0] current_instruction; // This is the content of jtag_ir register latched in state Update-IR. + reg [31:0] idcode_reg; + reg bypass_reg; + + + function automatic [3:0] get_next_state; + input reg [3:0] prev_state; + begin + `UNIQUE case ( prev_state ) + STATE_test_logic_reset: + begin + if(jtag_tms_i) get_next_state = STATE_test_logic_reset; + else get_next_state = STATE_run_test_idle; + end + STATE_run_test_idle: + begin + if(jtag_tms_i) get_next_state = STATE_select_dr_scan; + else get_next_state = STATE_run_test_idle; + end + STATE_select_dr_scan: + begin + if(jtag_tms_i) get_next_state = STATE_select_ir_scan; + else get_next_state = STATE_capture_dr; + end + STATE_capture_dr: + begin + if(jtag_tms_i) get_next_state = STATE_exit1_dr; + else get_next_state = STATE_shift_dr; + end + STATE_shift_dr: + begin + if(jtag_tms_i) get_next_state = STATE_exit1_dr; + else get_next_state = STATE_shift_dr; + end + STATE_exit1_dr: + begin + if(jtag_tms_i) get_next_state = STATE_update_dr; + else get_next_state = STATE_pause_dr; + end + STATE_pause_dr: + begin + if(jtag_tms_i) get_next_state = STATE_exit2_dr; + else get_next_state = STATE_pause_dr; + end + STATE_exit2_dr: + begin + if(jtag_tms_i) get_next_state = STATE_update_dr; + else get_next_state = STATE_shift_dr; + end + STATE_update_dr: + begin + if(jtag_tms_i) get_next_state = STATE_select_dr_scan; + else get_next_state = STATE_run_test_idle; + end + STATE_select_ir_scan: + begin + if(jtag_tms_i) get_next_state = STATE_test_logic_reset; + else get_next_state = STATE_capture_ir; + end + STATE_capture_ir: + begin + if(jtag_tms_i) get_next_state = STATE_exit1_ir; + else get_next_state = STATE_shift_ir; + end + STATE_shift_ir: + begin + if(jtag_tms_i) get_next_state = STATE_exit1_ir; + else get_next_state = STATE_shift_ir; + end + STATE_exit1_ir: + begin + if(jtag_tms_i) get_next_state = STATE_update_ir; + else get_next_state = STATE_pause_ir; + end + STATE_pause_ir: + begin + if(jtag_tms_i) get_next_state = STATE_exit2_ir; + else get_next_state = STATE_pause_ir; + end + STATE_exit2_ir: + begin + if(jtag_tms_i) get_next_state = STATE_update_ir; + else get_next_state = STATE_shift_ir; + end + STATE_update_ir: + begin + if(jtag_tms_i) get_next_state = STATE_select_dr_scan; + else get_next_state = STATE_run_test_idle; + end + endcase + end + endfunction + + + function [16*8-1:0] get_state_name; + input [3:0] state; + begin + `UNIQUE case ( state ) + STATE_test_logic_reset: get_state_name = "Test Logic Reset"; + STATE_run_test_idle: get_state_name = "Run-Test / Idle"; + STATE_select_dr_scan: get_state_name = "Select-DR"; + STATE_capture_dr: get_state_name = "Capture-DR"; + STATE_shift_dr: get_state_name = "Shift-DR"; + STATE_exit1_dr: get_state_name = "Exit1-DR"; + STATE_pause_dr: get_state_name = "Pause-DR"; + STATE_exit2_dr: get_state_name = "Exit2-DR"; + STATE_update_dr: get_state_name = "Update-DR"; + STATE_select_ir_scan: get_state_name = "Select-IR"; + STATE_capture_ir: get_state_name = "Capture-IR"; + STATE_shift_ir: get_state_name = "Shift-IR"; + STATE_exit1_ir: get_state_name = "Exit1-IR"; + STATE_pause_ir: get_state_name = "Pause-IR"; + STATE_exit2_ir: get_state_name = "Exit2-IR"; + STATE_update_ir: get_state_name = "Update-IR"; + endcase + end + endfunction + + + function [14*8-1:0] get_instruction_name; + input [IR_LENGTH-1:0] state; + begin + `UNIQUE case ( state ) + `JTAG_INSTRUCTION_EXTEST: get_instruction_name = "EXTEST"; + `JTAG_INSTRUCTION_SAMPLE_PRELOAD: get_instruction_name = "SAMPLE/PRELOAD"; + `JTAG_INSTRUCTION_IDCODE: get_instruction_name = "IDCODE"; + `JTAG_INSTRUCTION_DEBUG: get_instruction_name = "DEBUG"; + `JTAG_INSTRUCTION_MBIST: get_instruction_name = "MBIST"; + `JTAG_INSTRUCTION_BYPASS: get_instruction_name = "BYPASS"; + default: get_instruction_name = ""; + endcase + end + endfunction + + + task automatic reset_initial; + begin + // See the comments in sibling task 'reset_sync' for more information. + current_state = STATE_test_logic_reset; + current_instruction = `JTAG_INSTRUCTION_IDCODE; + jtag_ir = {IR_LENGTH{1'bx}}; + bypass_reg = 1'bx; + idcode_reg = {32{1'bx}}; + debug_reg = {32{1'b0}}; //TH + is_tap_current_instruction_debug_o = 0; + is_tap_state_test_logic_reset_o = 0; + is_tap_state_shift_dr_o = 0; + is_tap_state_update_dr_o = 0; + is_tap_state_capture_dr_o = 0; + end + endtask + + task automatic reset_sync; + begin + // If you change this task, please update sibling task 'reset_initial' too. + + current_state <= STATE_test_logic_reset; + + // As this JTAG TAP does support the IDCODE instruction, that's the one + // selected upon reset. Otherwise, we should select the BYPASS instruction. + current_instruction <= `JTAG_INSTRUCTION_IDCODE; + + // We do not need to initialise the other registers, as the TAP state machine + // always goes through states Capture-IR or Capture-DR, which initialises them + // when they are needed. + jtag_ir <= {IR_LENGTH{1'bx}}; + bypass_reg <= 1'bx; + idcode_reg <= {32{1'bx}}; + debug_reg <= {32{1'b0}}; + + is_tap_current_instruction_debug_o <= 0; + + is_tap_state_test_logic_reset_o <= 0; + is_tap_state_shift_dr_o <= 0; + is_tap_state_update_dr_o <= 0; + is_tap_state_capture_dr_o <= 0; + end + endtask + + + reg [16*8-1:0] initial_state_name; // We need this temporary variable because of a limitation in Verilator. + + initial + begin + // This is so that, in FPGAs, there is no need to trigger the reset signal at the beginning, + // it can then be hard-wired to '1' and optimised away by the synthesiser. + reset_initial; + + if ( TRACE_STATE_MACHINE_TRANSITIONS ) + begin + initial_state_name = get_state_name( current_state ); + $display( "%sStarting up in initial state '%0s'.", TRACE_PREFIX, initial_state_name ); + end + end + + + task do_capture_dr; + reg [14*8-1:0] instruction_name; + begin + instruction_name = get_instruction_name( current_instruction ); + + case ( current_instruction ) + `JTAG_INSTRUCTION_IDCODE: idcode_reg <= `OPENRISC_CPU_JTAG_IDCODE_VALUE; + `JTAG_INSTRUCTION_BYPASS: bypass_reg <= 0; // Must be 0 according to the JTAG specification. + `JTAG_INSTRUCTION_DEBUG: + begin + // Nothing to do here, a submodule will do all the processing for this command. + end + `JTAG_INSTRUCTION_EXTEST, + `JTAG_INSTRUCTION_SAMPLE_PRELOAD, + `JTAG_INSTRUCTION_MBIST: + begin + $display( "%sInstruction %0s is not supported or has not been fully tested yet.", TRACE_PREFIX, instruction_name ); + `FINISH_WITH_ERROR_EXIT_CODE; + end + default: + begin + `ASSERT_FALSE; + // For all unknown JTAG instructions, the standard requires the bypass register. + bypass_reg <= 0; + end + endcase + end + endtask + + + task do_shift_dr; + begin + case ( current_instruction ) + `JTAG_INSTRUCTION_IDCODE: + idcode_reg <= { jtag_tdi_i, idcode_reg[31:1] }; // Note that this overwrites the IDCODE register. It shouldn't really matter. + + `JTAG_INSTRUCTION_BYPASS: + bypass_reg <= jtag_tdi_i; + + `JTAG_INSTRUCTION_DEBUG: + begin + // Nothing to do here, a submodule will do all the processing for this command. + debug_reg <= { jtag_tdi_i, debug_reg[31:1] }; //TH + end + + default: + begin + // Note that task 'do_capture_dr' already catches all default cases. + `ASSERT_FALSE; + // For all unknown JTAG instructions, the standard requires the bypass register. + bypass_reg <= jtag_tdi_i; + end + endcase + end + endtask + + + task automatic tck_posedge; + reg [14*8-1:0] instruction_name; + begin + case ( current_state ) + STATE_test_logic_reset: reset_sync; + + STATE_capture_ir: + jtag_ir <= { 2'b01, // Some fixed status value to help debugging this module, + // we don't actually have any status to report. + + 2'b01 }; // Bits [1:0] must be "01" according to the JTAG specification, + // which helps tell whether a device in the JTAG chain supports the IDCODE instruction + // or not (in which case it would be in BYPASS mode, and its first bit would then be 0). + + STATE_update_ir: + begin + if ( TRACE_STATE_MACHINE_TRANSITIONS ) + begin + instruction_name = get_instruction_name( jtag_ir ); + $display( "%sCurrent instruction set to %0s.", TRACE_PREFIX, instruction_name ); + end + + current_instruction <= jtag_ir; + + is_tap_current_instruction_debug_o <= 0; + + case ( jtag_ir ) + `JTAG_INSTRUCTION_DEBUG: is_tap_current_instruction_debug_o <= 1; + default: + begin + // Nothing to do here. + end + endcase + end + + STATE_shift_ir: + jtag_ir <= { jtag_tdi_i, jtag_ir[IR_LENGTH-1:1] }; + + STATE_capture_dr: + do_capture_dr; + + STATE_shift_dr: + do_shift_dr; + + default: + begin + // Nothing to do here. + end + endcase + end + endtask + + + task automatic switch_to_next_state; + reg [3:0] next_state; + reg [16*8-1:0] prev_state_name; + reg [16*8-1:0] next_state_name; + begin + next_state = get_next_state( current_state ); + + if ( TRACE_JTAG_DATA || TRACE_STATE_MACHINE_TRANSITIONS ) + begin + prev_state_name = get_state_name( current_state ); + + if ( next_state == current_state ) + begin + if ( TRACE_JTAG_DATA ) + $display( "%sTCK posedge, TMS=%0d, TDI=%0d while in state '%0s'.", + TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, prev_state_name ); + end + else + begin + next_state_name = get_state_name( next_state ); + + if ( TRACE_JTAG_DATA ) + $display( "%sTCK posedge, TMS=%0d, TDI=%0d, changing state from '%0s' to '%0s'.", + TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, prev_state_name, next_state_name ); + + if ( TRACE_STATE_MACHINE_TRANSITIONS ) + $display( "%sChanging state from '%0s' to '%0s'.", + TRACE_PREFIX, prev_state_name, next_state_name ); + end + end + + current_state <= next_state; + + is_tap_state_test_logic_reset_o <= 0; + is_tap_state_shift_dr_o <= 0; + is_tap_state_update_dr_o <= 0; + is_tap_state_capture_dr_o <= 0; + + case ( next_state ) + STATE_test_logic_reset: is_tap_state_test_logic_reset_o <= 1; + STATE_shift_dr: is_tap_state_shift_dr_o <= 1; + STATE_update_dr: is_tap_state_update_dr_o <= 1; + STATE_capture_dr: is_tap_state_capture_dr_o <= 1; + default: + begin + // Nothing to do here. + end + endcase + end + endtask + + + task automatic tck_negedge; + reg [16*8-1:0] state_name; + begin + if ( TRACE_JTAG_DATA ) + begin + state_name = get_state_name( current_state ); + $display( "%sTCK negedge, TMS=%0d, TDI=%0d while in state '%0s'.", + TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, state_name ); + end + + // According to the JTAG specification TDO changes state at the negative edge of TCK. + // This is from the documentation about Xilinx BSCAN_SPARTAN6 (which allows access to the FPGA's JTAG TAP): + // TDO input driven from the user fabric logic. This signal is + // internally sampled on the falling edge before being driven out + // to the FPGA TDO pin. + + if ( current_state == STATE_shift_ir ) + jtag_tdo_o <= jtag_ir[0]; + else + begin + case ( current_instruction ) + `JTAG_INSTRUCTION_IDCODE: jtag_tdo_o <= idcode_reg[0]; + `JTAG_INSTRUCTION_DEBUG: jtag_tdo_o <= debug_reg[0]; //debug_tdo_i; TH + `JTAG_INSTRUCTION_SAMPLE_PRELOAD: jtag_tdo_o <= 0; // Boundary scan not supported. + `JTAG_INSTRUCTION_EXTEST: jtag_tdo_o <= 0; // Boundary scan not supported. + `JTAG_INSTRUCTION_MBIST: jtag_tdo_o <= 0; // MBIST not supported. + default: jtag_tdo_o <= bypass_reg; + endcase + end + end + endtask + + + always @( posedge jtag_tck_i or negedge jtag_trstn_i ) + begin + // These 2 conditions must be combined in a single always block, + // otherwise Verilator complains that current_state has 2 drivers, + // as the reset is asynchronous. + + if ( jtag_trstn_i == 0 ) + begin + if ( TRACE_STATE_MACHINE_TRANSITIONS ) + $display( "%sAsync reset signal TRST asserted (the value is now 0).", TRACE_PREFIX ); + + reset_sync; + end + else + begin + tck_posedge; + switch_to_next_state; + end + end + + always @( negedge jtag_tck_i ) + begin + tck_negedge; + end + + always @( posedge jtag_trstn_i ) + begin + if ( TRACE_STATE_MACHINE_TRANSITIONS ) + $display( "%sAsync reset signal TRST deasserted (the value is now 1).", TRACE_PREFIX ); + end + +endmodule + +`endif From 6f7fef7eef578226311ed276a70956e90a8af4bd Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Fri, 22 May 2026 23:46:46 +0200 Subject: [PATCH 35/43] refactor: normalize Verilog include guards --- basil/firmware/modules/bram_fifo/bram_fifo.v | 9 ++++---- .../modules/bram_fifo/bram_fifo_core.v | 6 +++++ basil/firmware/modules/cmd_seq/cmd_seq.v | 9 ++++---- basil/firmware/modules/cmd_seq/cmd_seq_core.v | 14 +++++------ .../modules/fast_spi_rx/fast_spi_rx.v | 9 ++++---- .../modules/fast_spi_rx/fast_spi_rx_core.v | 10 ++++---- basil/firmware/modules/fei4_rx/decode_8b10b.v | 5 ++++ basil/firmware/modules/fei4_rx/fei4_rx.v | 9 ++++---- basil/firmware/modules/fei4_rx/fei4_rx_core.v | 9 ++++---- basil/firmware/modules/fei4_rx/rec_sync.v | 9 ++++---- .../firmware/modules/fei4_rx/receiver_logic.v | 13 ++++------- basil/firmware/modules/fei4_rx/sync_master.v | 5 ++++ basil/firmware/modules/fx3_if/FX3_IF.v | 5 ++++ .../modules/gpac_adc_rx/gpac_adc_iobuf.v | 5 ++++ .../modules/gpac_adc_rx/gpac_adc_rx.v | 9 ++++---- .../modules/gpac_adc_rx/gpac_adc_rx_core.v | 18 +++++---------- basil/firmware/modules/gpio/gpio.v | 9 ++++---- basil/firmware/modules/gpio/gpio_core.v | 6 +++++ basil/firmware/modules/gpio/gpio_sbus.v | 9 ++++---- basil/firmware/modules/i2c/i2c.v | 9 ++++---- basil/firmware/modules/i2c/i2c_core.v | 10 ++++---- .../modules/jtag_master/jtag_master.v | 9 ++++---- .../modules/jtag_master/jtag_master_core.v | 14 +++++------ basil/firmware/modules/m26_rx/m26_rx.v | 9 ++++---- basil/firmware/modules/m26_rx/m26_rx_ch.v | 6 +++++ basil/firmware/modules/m26_rx/m26_rx_core.v | 23 ++++++++----------- basil/firmware/modules/pulse_gen/pulse_gen.v | 9 ++++---- .../modules/pulse_gen/pulse_gen_core.v | 10 ++++---- .../modules/rrp_arbiter/rrp_arbiter.v | 5 ++++ basil/firmware/modules/seq_gen/seq_gen.v | 9 ++++---- basil/firmware/modules/seq_gen/seq_gen_core.v | 10 ++++---- basil/firmware/modules/seq_rec/seq_rec.v | 9 ++++---- basil/firmware/modules/seq_rec/seq_rec_core.v | 23 ++++--------------- .../modules/spi/blk_mem_gen_8_to_1_2k.v | 6 +++++ basil/firmware/modules/spi/spi.v | 9 ++++---- basil/firmware/modules/spi/spi_core.v | 10 ++++---- basil/firmware/modules/sram_fifo/sram_fifo.v | 9 ++++---- .../modules/sram_fifo/sram_fifo_core.v | 6 +++++ basil/firmware/modules/tb/silbusb.v | 5 ++++ basil/firmware/modules/tb/uartlib.v | 5 ++++ basil/firmware/modules/tdc_s3/tdc_s3.v | 9 ++++---- basil/firmware/modules/tdc_s3/tdc_s3_core.v | 18 +++++---------- basil/firmware/modules/tdl_tdc/controller.v | 5 ++++ .../counter/slimfast_multioption_counter.v | 5 ++++ .../delayline/carrysampler_spartan6_20ps.v | 5 ++++ .../modules/tdl_tdc/delayline/sample_deser.v | 5 ++++ .../modules/tdl_tdc/priority_encoder.v | 5 ++++ basil/firmware/modules/tdl_tdc/sw_interface.v | 17 ++++---------- .../modules/tdl_tdc/tdl_supersampler.v | 5 ++++ basil/firmware/modules/tdl_tdc/tdl_tdc.v | 13 ++++------- basil/firmware/modules/tdl_tdc/tdl_tdc_core.v | 5 ++++ .../firmware/modules/tdl_tdc/utils/delay_n.v | 5 ++++ .../tdl_tdc/utils/graycode_2stage_cdc.v | 5 ++++ basil/firmware/modules/tdl_tdc/word_broker.v | 5 ++++ basil/firmware/modules/timestamp/timestamp.v | 9 ++++---- .../modules/timestamp/timestamp_core.v | 14 +++++------ basil/firmware/modules/tlu/tlu_controller.v | 9 ++++---- .../modules/tlu/tlu_controller_core.v | 19 ++++++--------- .../firmware/modules/tlu/tlu_controller_fsm.v | 6 +++++ basil/firmware/modules/uart/uart.v | 5 ++++ basil/firmware/modules/uart/uart_master.v | 5 ++++ .../modules/utils/3_stage_synchronizer.v | 6 ++++- basil/firmware/modules/utils/BUFG.v | 5 ++++ basil/firmware/modules/utils/CG_MOD_neg.v | 5 ++++ basil/firmware/modules/utils/CG_MOD_pos.v | 5 ++++ basil/firmware/modules/utils/IBUFDS.v | 5 ++++ basil/firmware/modules/utils/IDDR.v | 5 ++++ basil/firmware/modules/utils/IDDR_s3.v | 5 ++++ basil/firmware/modules/utils/IDDR_s3_noibuf.v | 5 ++++ basil/firmware/modules/utils/IDDR_s6.v | 5 ++++ basil/firmware/modules/utils/ODDR_s3.v | 5 ++++ basil/firmware/modules/utils/ODDR_s6.v | 5 ++++ basil/firmware/modules/utils/PLLE2_BASE.v | 5 ++++ basil/firmware/modules/utils/bus_to_ip.v | 5 ++++ basil/firmware/modules/utils/cdc_pulse_sync.v | 6 +++++ .../modules/utils/cdc_pulse_sync_cnt.v | 5 ++++ basil/firmware/modules/utils/cdc_reset_sync.v | 6 +++++ basil/firmware/modules/utils/cdc_syncfifo.v | 7 ++++-- basil/firmware/modules/utils/clock_divider.v | 6 +++++ .../firmware/modules/utils/clock_multiplier.v | 5 ++++ basil/firmware/modules/utils/ddr_des.v | 5 ++++ basil/firmware/modules/utils/fifo_32_to_8.v | 5 ++++ basil/firmware/modules/utils/fifo_64_to_16.v | 5 ++++ basil/firmware/modules/utils/fifo_8_to_32.v | 5 ++++ basil/firmware/modules/utils/fifo_8_to_64.v | 5 ++++ .../modules/utils/flag_domain_crossing.v | 6 +++++ basil/firmware/modules/utils/fx2_to_bus.v | 5 ++++ basil/firmware/modules/utils/generic_fifo.v | 5 ++++ .../firmware/modules/utils/pulse_gen_rising.v | 5 ++++ basil/firmware/modules/utils/ramb_8_to_n.v | 6 +++++ basil/firmware/modules/utils/rbcp_to_bus.v | 5 ++++ basil/firmware/modules/utils/reset_gen.v | 5 ++++ basil/firmware/modules/utils/rgmii_io.v | 5 ++++ basil/firmware/modules/utils/sbus_to_ip.v | 6 +++++ basil/firmware/modules/utils/simple_arbiter.v | 5 ++++ basil/firmware/modules/utils/tcp_to_bus.v | 5 ++++ tests/test_SimFifo8to32.v | 9 ++------ tests/test_SimGpio.v | 2 -- tests/test_SimJtagGpio.v | 2 -- tests/test_SimSeq.v | 12 ---------- tests/test_SimTlu.v | 13 ----------- 101 files changed, 510 insertions(+), 259 deletions(-) diff --git a/basil/firmware/modules/bram_fifo/bram_fifo.v b/basil/firmware/modules/bram_fifo/bram_fifo.v index 3dac60a4a..4766b14f0 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_BRAM_FIFO_BRAM_FIFO_V +`define BASIL_BRAM_FIFO_BRAM_FIFO_V + `include "bram_fifo/bram_fifo_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -119,3 +118,5 @@ bram_fifo_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/bram_fifo/bram_fifo_core.v b/basil/firmware/modules/bram_fifo/bram_fifo_core.v index ce6175f59..a9caefece 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo_core.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo_core.v @@ -4,11 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_BRAM_FIFO_BRAM_FIFO_CORE_V +`define BASIL_BRAM_FIFO_BRAM_FIFO_CORE_V + `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module bram_fifo_core #( parameter DEPTH = 32'h8000, parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent @@ -163,3 +167,5 @@ always @(posedge BUS_CLK) begin end endmodule + +`endif diff --git a/basil/firmware/modules/cmd_seq/cmd_seq.v b/basil/firmware/modules/cmd_seq/cmd_seq.v index 9dbec5377..dca07d687 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_CMD_SEQ_CMD_SEQ_V +`define BASIL_CMD_SEQ_CMD_SEQ_V + `include "cmd_seq/cmd_seq_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -83,3 +82,5 @@ cmd_seq_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/cmd_seq/cmd_seq_core.v b/basil/firmware/modules/cmd_seq/cmd_seq_core.v index 9a5823931..1900c08b0 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq_core.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq_core.v @@ -4,20 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_CMD_SEQ_CMD_SEQ_CORE_V +`define BASIL_CMD_SEQ_CMD_SEQ_CORE_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif `timescale 1ps/1ps `default_nettype none + module cmd_seq_core #( parameter ABUSWIDTH = 16, parameter OUTPUTS = 1, // from (0 : 8] @@ -481,3 +477,5 @@ always @(posedge BUS_CLK) CONF_READY <= 1; endmodule + +`endif diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v index 781cc43b8..7025c2bdf 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v @@ -5,12 +5,11 @@ * ------------------------------------------------------------ */ +`ifndef BASIL_FAST_SPI_RX_FAST_SPI_RX_V +`define BASIL_FAST_SPI_RX_FAST_SPI_RX_V + `include "fast_spi_rx/fast_spi_rx_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -85,3 +84,5 @@ fast_spi_rx_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index 8da5d7b67..32369d865 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -4,17 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V +`ifndef BASIL_FAST_SPI_RX_FAST_SPI_RX_CORE_V +`define BASIL_FAST_SPI_RX_FAST_SPI_RX_CORE_V + `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `include "utils/cdc_syncfifo.v" `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module fast_spi_rx_core #( parameter ABUSWIDTH = 16, parameter IDENTIFIER = 4'b0001, @@ -186,3 +186,5 @@ generic_fifo #( //assign FIFO_DATA[31:30] = 0; endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/decode_8b10b.v b/basil/firmware/modules/fei4_rx/decode_8b10b.v index 776a1ee15..797288794 100644 --- a/basil/firmware/modules/fei4_rx/decode_8b10b.v +++ b/basil/firmware/modules/fei4_rx/decode_8b10b.v @@ -15,6 +15,9 @@ * notice is preserved. * per Widmer and Franaszek */ +`ifndef BASIL_FEI4_RX_DECODE_8B10B_V +`define BASIL_FEI4_RX_DECODE_8B10B_V + `timescale 1ps/1ps `default_nettype none @@ -171,3 +174,5 @@ module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err); (disp6p & disp4p) | (disp6n & disp4n)); endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/fei4_rx.v b/basil/firmware/modules/fei4_rx/fei4_rx.v index dc5938da8..dfb67d839 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_FEI4_RX_FEI4_RX_V +`define BASIL_FEI4_RX_FEI4_RX_V + `include "fei4_rx/fei4_rx_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -108,3 +107,5 @@ fei4_rx_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/fei4_rx_core.v b/basil/firmware/modules/fei4_rx/fei4_rx_core.v index 503959cad..50721024f 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx_core.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx_core.v @@ -4,11 +4,10 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V +`ifndef BASIL_FEI4_RX_FEI4_RX_CORE_V +`define BASIL_FEI4_RX_FEI4_RX_CORE_V + `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif `include "fei4_rx/receiver_logic.v" `timescale 1ps/1ps @@ -265,3 +264,5 @@ receiver_logic #( ); endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/rec_sync.v b/basil/firmware/modules/fei4_rx/rec_sync.v index 6d8390852..d437c4195 100644 --- a/basil/firmware/modules/fei4_rx/rec_sync.v +++ b/basil/firmware/modules/fei4_rx/rec_sync.v @@ -4,11 +4,10 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_FEI4_RX_REC_SYNC_V +`define BASIL_FEI4_RX_REC_SYNC_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif `timescale 1ps/1ps `default_nettype none @@ -175,3 +174,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/receiver_logic.v b/basil/firmware/modules/fei4_rx/receiver_logic.v index 481675ee1..b63bd107e 100644 --- a/basil/firmware/modules/fei4_rx/receiver_logic.v +++ b/basil/firmware/modules/fei4_rx/receiver_logic.v @@ -4,16 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_FEI4_RX_RECEIVER_LOGIC_V +`define BASIL_FEI4_RX_RECEIVER_LOGIC_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" `include "fei4_rx/sync_master.v" `include "fei4_rx/rec_sync.v" @@ -297,3 +292,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/fei4_rx/sync_master.v b/basil/firmware/modules/fei4_rx/sync_master.v index 556b1506f..8da6caae8 100644 --- a/basil/firmware/modules/fei4_rx/sync_master.v +++ b/basil/firmware/modules/fei4_rx/sync_master.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_FEI4_RX_SYNC_MASTER_V +`define BASIL_FEI4_RX_SYNC_MASTER_V + `timescale 1ps/1ps `default_nettype none @@ -185,3 +188,5 @@ assign dz[1] = DATA_IN_DLY[0]; //FDC ff_dz1(.D(dz[0]), .C(clk90), .CLR(rst), .Q(dz[1]))/*synthesis rloc = "x3y0" */; endmodule + +`endif diff --git a/basil/firmware/modules/fx3_if/FX3_IF.v b/basil/firmware/modules/fx3_if/FX3_IF.v index c541ed0ae..75dde9a56 100644 --- a/basil/firmware/modules/fx3_if/FX3_IF.v +++ b/basil/firmware/modules/fx3_if/FX3_IF.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_FX3_IF_FX3_IF_V +`define BASIL_FX3_IF_FX3_IF_V + `timescale 1ps/1ps `default_nettype none @@ -363,3 +366,5 @@ for (gen = 0; gen < 32; gen = gen + 1) endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v index e88771bed..efc7c6140 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_GPAC_ADC_RX_GPAC_ADC_IOBUF_V +`define BASIL_GPAC_ADC_RX_GPAC_ADC_IOBUF_V + `timescale 1ps/1ps `default_nettype none @@ -182,3 +185,5 @@ assign ADC_IN3 = adc_out_sync[3]; `endif endmodule + +`endif diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v index 94d4d55c3..88a84036b 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_GPAC_ADC_RX_GPAC_ADC_RX_V +`define BASIL_GPAC_ADC_RX_GPAC_ADC_RX_V + `include "gpac_adc_rx/gpac_adc_rx_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -91,3 +90,5 @@ gpac_adc_rx_core #( endmodule + +`endif diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v index 7c58284ca..07ac2015d 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v @@ -4,27 +4,19 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// cdc_reset_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_RESET_SYNC_V +`ifndef BASIL_GPAC_ADC_RX_GPAC_ADC_RX_CORE_V +`define BASIL_GPAC_ADC_RX_GPAC_ADC_RX_CORE_V + `include "utils/cdc_reset_sync.v" -`define CDC_RESET_SYNC_V -`endif -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `include "utils/pulse_gen_rising.v" -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module gpac_adc_rx_core #( parameter ABUSWIDTH = 16, parameter [1:0] ADC_ID = 0, @@ -304,3 +296,5 @@ always @(posedge BUS_CLK) CONF_DONE <= 1; endmodule + +`endif diff --git a/basil/firmware/modules/gpio/gpio.v b/basil/firmware/modules/gpio/gpio.v index 211a9314d..f2f12e03e 100644 --- a/basil/firmware/modules/gpio/gpio.v +++ b/basil/firmware/modules/gpio/gpio.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_GPIO_GPIO_V +`define BASIL_GPIO_GPIO_V + `include "gpio/gpio_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -72,3 +71,5 @@ gpio_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/gpio/gpio_core.v b/basil/firmware/modules/gpio/gpio_core.v index 47a36905c..8669b5f88 100644 --- a/basil/firmware/modules/gpio/gpio_core.v +++ b/basil/firmware/modules/gpio/gpio_core.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef BASIL_GPIO_GPIO_CORE_V +`define BASIL_GPIO_GPIO_CORE_V + module gpio_core #( parameter ABUSWIDTH = 16, parameter IO_WIDTH = 8, @@ -104,3 +108,5 @@ always @(*) endmodule + +`endif diff --git a/basil/firmware/modules/gpio/gpio_sbus.v b/basil/firmware/modules/gpio/gpio_sbus.v index 5827a64e9..fec4c15b6 100644 --- a/basil/firmware/modules/gpio/gpio_sbus.v +++ b/basil/firmware/modules/gpio/gpio_sbus.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_GPIO_GPIO_SBUS_V +`define BASIL_GPIO_GPIO_SBUS_V + `include "gpio/gpio_core.v" -// sbus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef SBUS_TO_IP_V `include "utils/sbus_to_ip.v" -`define SBUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -77,3 +76,5 @@ gpio_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/i2c/i2c.v b/basil/firmware/modules/i2c/i2c.v index a0e95c1c7..fa1ad4af8 100644 --- a/basil/firmware/modules/i2c/i2c.v +++ b/basil/firmware/modules/i2c/i2c.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_I2C_I2C_V +`define BASIL_I2C_I2C_V + `include "i2c/i2c_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -76,3 +75,5 @@ i2c_core #( endmodule + +`endif diff --git a/basil/firmware/modules/i2c/i2c_core.v b/basil/firmware/modules/i2c/i2c_core.v index 3d36562d9..f5d2e0789 100644 --- a/basil/firmware/modules/i2c/i2c_core.v +++ b/basil/firmware/modules/i2c/i2c_core.v @@ -4,15 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V +`ifndef BASIL_I2C_I2C_CORE_V +`define BASIL_I2C_I2C_CORE_V + `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `timescale 1ps/1ps `default_nettype none + module i2c_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 1, @@ -349,3 +349,5 @@ always @(posedge BUS_CLK) endmodule + +`endif diff --git a/basil/firmware/modules/jtag_master/jtag_master.v b/basil/firmware/modules/jtag_master/jtag_master.v index f173f298a..9cb551af4 100644 --- a/basil/firmware/modules/jtag_master/jtag_master.v +++ b/basil/firmware/modules/jtag_master/jtag_master.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_JTAG_MASTER_JTAG_MASTER_V +`define BASIL_JTAG_MASTER_JTAG_MASTER_V + `include "jtag_master/jtag_master_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -86,3 +85,5 @@ jtag_master_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/jtag_master/jtag_master_core.v b/basil/firmware/modules/jtag_master/jtag_master_core.v index beb5f0c85..91a06a85d 100644 --- a/basil/firmware/modules/jtag_master/jtag_master_core.v +++ b/basil/firmware/modules/jtag_master/jtag_master_core.v @@ -4,21 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_JTAG_MASTER_JTAG_MASTER_CORE_V +`define BASIL_JTAG_MASTER_JTAG_MASTER_CORE_V + `include "utils/ramb_8_to_n.v" -// cdc_reset_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_RESET_SYNC_V `include "utils/cdc_reset_sync.v" -`define CDC_RESET_SYNC_V -`endif -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `include "utils/CG_MOD_pos.v" `default_nettype none + module jtag_master_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16 @@ -487,3 +483,5 @@ always @(negedge JTAG_CLK) /// endmodule + +`endif diff --git a/basil/firmware/modules/m26_rx/m26_rx.v b/basil/firmware/modules/m26_rx/m26_rx.v index 883fb7f1d..430facde2 100644 --- a/basil/firmware/modules/m26_rx/m26_rx.v +++ b/basil/firmware/modules/m26_rx/m26_rx.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_M26_RX_M26_RX_V +`define BASIL_M26_RX_M26_RX_V + `include "m26_rx/m26_rx_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -94,3 +93,5 @@ m26_rx_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/m26_rx/m26_rx_ch.v b/basil/firmware/modules/m26_rx/m26_rx_ch.v index d7a9067bb..0013ed701 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_ch.v +++ b/basil/firmware/modules/m26_rx/m26_rx_ch.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef BASIL_M26_RX_M26_RX_CH_V +`define BASIL_M26_RX_M26_RX_CH_V + module m26_rx_ch ( input wire RST, @@ -119,3 +123,5 @@ always @(posedge CLK_RX) DATA <= data_sr[15:0]; endmodule + +`endif diff --git a/basil/firmware/modules/m26_rx/m26_rx_core.v b/basil/firmware/modules/m26_rx/m26_rx_core.v index 9ec42bb61..50c3bc9f5 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_core.v +++ b/basil/firmware/modules/m26_rx/m26_rx_core.v @@ -4,27 +4,19 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_M26_RX_M26_RX_CORE_V +`define BASIL_M26_RX_M26_RX_CORE_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif `include "m26_rx/m26_rx_ch.v" -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module m26_rx_core #( parameter ABUSWIDTH = 16, parameter HEADER = 0, @@ -55,6 +47,9 @@ module m26_rx_core #( localparam VERSION = 2; +reg M26_FRAME_START; +reg WRITE_FRAME; + //output format #ID (as parameter IDENTIFIER + 1 frame start + 16 bit data) // writing to register 0 asserts soft reset @@ -314,7 +309,6 @@ always @(posedge CLK_RX) begin end end -reg M26_FRAME_START; always @(posedge CLK_RX) begin M26_FRAME_START <= FRAME_START_CH0; end @@ -324,7 +318,6 @@ assign cdc_data[17] = m26_data_lost; // M26 data loss flag assign cdc_data[16] = M26_FRAME_START; // start of M26 frame flag assign cdc_data[15:0] = data_field; // M26 data -reg WRITE_FRAME; always @(posedge CLK_RX) begin if (RST_SYNC) WRITE_FRAME <= 1'b0; @@ -422,3 +415,5 @@ assign FIFO_DATA[31:24] = HEADER[7:0]; endmodule + +`endif diff --git a/basil/firmware/modules/pulse_gen/pulse_gen.v b/basil/firmware/modules/pulse_gen/pulse_gen.v index 5e43a7254..eb9bb81a6 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_PULSE_GEN_PULSE_GEN_V +`define BASIL_PULSE_GEN_PULSE_GEN_V + `include "pulse_gen/pulse_gen_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -70,3 +69,5 @@ pulse_gen_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/pulse_gen/pulse_gen_core.v b/basil/firmware/modules/pulse_gen/pulse_gen_core.v index 0b5c1bd70..616631145 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen_core.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen_core.v @@ -4,16 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_PULSE_GEN_PULSE_GEN_CORE_V +`define BASIL_PULSE_GEN_PULSE_GEN_CORE_V + `include "utils/3_stage_synchronizer.v" -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `timescale 1ps/1ps `default_nettype none + module pulse_gen_core #( parameter ABUSWIDTH = 16 ) ( @@ -232,3 +232,5 @@ always @(posedge BUS_CLK) CONF_DONE <= 1; endmodule + +`endif diff --git a/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v b/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v index 70f11500a..7adb02bf7 100644 --- a/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +++ b/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_RRP_ARBITER_RRP_ARBITER_V +`define BASIL_RRP_ARBITER_RRP_ARBITER_V + `timescale 1ps/1ps `default_nettype none @@ -107,3 +110,5 @@ endgenerate assign READ_GRANT = select & {WIDTH{READY_OUT}} & WRITE_REQ; endmodule + +`endif diff --git a/basil/firmware/modules/seq_gen/seq_gen.v b/basil/firmware/modules/seq_gen/seq_gen.v index 20c345de8..5058f7869 100644 --- a/basil/firmware/modules/seq_gen/seq_gen.v +++ b/basil/firmware/modules/seq_gen/seq_gen.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SEQ_GEN_SEQ_GEN_V +`define BASIL_SEQ_GEN_SEQ_GEN_V + `include "seq_gen/seq_gen_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -75,3 +74,5 @@ seq_gen_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index 603ba05ea..eace2622a 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -4,16 +4,16 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SEQ_GEN_SEQ_GEN_CORE_V +`define BASIL_SEQ_GEN_SEQ_GEN_CORE_V + `include "utils/ramb_8_to_n.v" -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `timescale 1ps/1ps `default_nettype none + module seq_gen_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16384, @@ -302,3 +302,5 @@ always @(posedge BUS_CLK) endmodule + +`endif diff --git a/basil/firmware/modules/seq_rec/seq_rec.v b/basil/firmware/modules/seq_rec/seq_rec.v index db74c9ecf..40d04d0be 100644 --- a/basil/firmware/modules/seq_rec/seq_rec.v +++ b/basil/firmware/modules/seq_rec/seq_rec.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SEQ_REC_SEQ_REC_V +`define BASIL_SEQ_REC_SEQ_REC_V + `include "seq_rec/seq_rec_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -73,3 +72,5 @@ seq_rec_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/seq_rec/seq_rec_core.v b/basil/firmware/modules/seq_rec/seq_rec_core.v index f3695472f..398d652d7 100644 --- a/basil/firmware/modules/seq_rec/seq_rec_core.v +++ b/basil/firmware/modules/seq_rec/seq_rec_core.v @@ -4,32 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_SEQ_REC_SEQ_REC_CORE_V +`define BASIL_SEQ_REC_SEQ_REC_CORE_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `include "utils/ramb_8_to_n.v" `timescale 1ps/1ps `default_nettype none -/* - * Possible extra options: - * - delay block that allow SEQ_EXT_START in past (enabled by parameter - for speed needed applications a simple memory circular buffer) - * - SEQ_EXT_START selections as pulse or as gate/enable - * - multi window recording (sorted with but multiple times) - */ module seq_rec_core #( parameter MEM_BYTES = 2*1024, @@ -263,3 +248,5 @@ always @(posedge BUS_CLK) CONF_READY <= 1'b1; endmodule + +`endif diff --git a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v index e7ce76950..386eb13ef 100644 --- a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v +++ b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v @@ -25,9 +25,13 @@ * Read behaviour: read-first on both ports (consistent with legacy primitive). * ------------------------------------------------------------ */ +`ifndef BASIL_SPI_BLK_MEM_GEN_8_TO_1_2K_V +`define BASIL_SPI_BLK_MEM_GEN_8_TO_1_2K_V + `timescale 1ps/1ps `default_nettype none + module blk_mem_gen_8_to_1_2k ( CLKA, CLKB, DOUTA, DOUTB, WEA, WEB, ADDRA, ADDRB, DINA, DINB ); @@ -79,3 +83,5 @@ always @(posedge CLKB) begin end endmodule + +`endif diff --git a/basil/firmware/modules/spi/spi.v b/basil/firmware/modules/spi/spi.v index e0c7ebfe6..a0dc73b7d 100644 --- a/basil/firmware/modules/spi/spi.v +++ b/basil/firmware/modules/spi/spi.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SPI_SPI_V +`define BASIL_SPI_SPI_V + `include "spi/spi_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -86,3 +85,5 @@ spi_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/spi/spi_core.v b/basil/firmware/modules/spi/spi_core.v index 9c8871cd5..ff68f68b2 100644 --- a/basil/firmware/modules/spi/spi_core.v +++ b/basil/firmware/modules/spi/spi_core.v @@ -4,17 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SPI_SPI_CORE_V +`define BASIL_SPI_SPI_CORE_V + `include "spi/blk_mem_gen_8_to_1_2k.v" -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif `include "utils/CG_MOD_pos.v" `timescale 1ps/1ps `default_nettype none + module spi_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16 @@ -279,3 +279,5 @@ always @(negedge SPI_CLK) SEN <= SEN_INT; endmodule + +`endif diff --git a/basil/firmware/modules/sram_fifo/sram_fifo.v b/basil/firmware/modules/sram_fifo/sram_fifo.v index b23345d66..333802309 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SRAM_FIFO_SRAM_FIFO_V +`define BASIL_SRAM_FIFO_SRAM_FIFO_V + `include "sram_fifo/sram_fifo_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -108,3 +107,5 @@ sram_fifo_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/sram_fifo/sram_fifo_core.v b/basil/firmware/modules/sram_fifo/sram_fifo_core.v index 519414f0e..6ec03b6ee 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo_core.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo_core.v @@ -4,11 +4,15 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_SRAM_FIFO_SRAM_FIFO_CORE_V +`define BASIL_SRAM_FIFO_SRAM_FIFO_CORE_V + `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module sram_fifo_core #( parameter DEPTH = 21'h10_0000, parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent @@ -308,3 +312,5 @@ always @(posedge BUS_CLK) begin end endmodule + +`endif diff --git a/basil/firmware/modules/tb/silbusb.v b/basil/firmware/modules/tb/silbusb.v index b21534fb9..cad833163 100644 --- a/basil/firmware/modules/tb/silbusb.v +++ b/basil/firmware/modules/tb/silbusb.v @@ -10,6 +10,9 @@ * $Date:: $: */ +`ifndef BASIL_TB_SILBUSB_V +`define BASIL_TB_SILBUSB_V + module SiLibUSB (input FCLK); reg RD_B; @@ -103,3 +106,5 @@ module SiLibUSB (input FCLK); endtask endmodule + +`endif diff --git a/basil/firmware/modules/tb/uartlib.v b/basil/firmware/modules/tb/uartlib.v index 1b405c96f..34ea147ab 100644 --- a/basil/firmware/modules/tb/uartlib.v +++ b/basil/firmware/modules/tb/uartlib.v @@ -1,3 +1,6 @@ +`ifndef BASIL_TB_UARTLIB_V +`define BASIL_TB_UARTLIB_V + `timescale 1ns / 100ps module uartlib( @@ -97,3 +100,5 @@ module uartlib( endtask endmodule + +`endif diff --git a/basil/firmware/modules/tdc_s3/tdc_s3.v b/basil/firmware/modules/tdc_s3/tdc_s3.v index ecc615d05..97e2e0d8b 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_TDC_S3_TDC_S3_V +`define BASIL_TDC_S3_TDC_S3_V + `include "tdc_s3/tdc_s3_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -112,3 +111,5 @@ tdc_s3_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tdc_s3/tdc_s3_core.v b/basil/firmware/modules/tdc_s3/tdc_s3_core.v index 175420da7..3edadf407 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3_core.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3_core.v @@ -4,27 +4,19 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_TDC_S3_TDC_S3_CORE_V +`define BASIL_TDC_S3_TDC_S3_CORE_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif `include "utils/ddr_des.v" -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module tdc_s3_core #( parameter DATA_IDENTIFIER = 4'b0100, parameter CLKDV = 4, // factor of CLK160 to DV_CLK, minimal divider of 2 @@ -708,3 +700,5 @@ end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/controller.v b/basil/firmware/modules/tdl_tdc/controller.v index 3575f2fef..3503a757d 100644 --- a/basil/firmware/modules/tdl_tdc/controller.v +++ b/basil/firmware/modules/tdl_tdc/controller.v @@ -2,6 +2,9 @@ // multiplexer, controling the corse counter, arming, calibration // states and the trigger distance mode. Furthermore counts successful events // and tdl misses. +`ifndef BASIL_TDL_TDC_CONTROLLER_V +`define BASIL_TDL_TDC_CONTROLLER_V + module controller #( parameter state_bits = 4, parameter mux_bits =2 @@ -228,3 +231,5 @@ always @(posedge CLK) begin end end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v index fd8746a3d..34963a768 100644 --- a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v @@ -1,5 +1,8 @@ //`include "tdl_tdc/counter/slimfast_multioption_counter.xdc" //`include "tdl_tdc/counter/signal_clipper.vhdl" +`ifndef BASIL_TDL_TDC_COUNTER_SLIMFAST_MULTIOPTION_COUNTER_V +`define BASIL_TDL_TDC_COUNTER_SLIMFAST_MULTIOPTION_COUNTER_V + `include "utils/pulse_gen_rising.v" //`default_nettype none @@ -167,3 +170,5 @@ assign countout[outputwidth-1] = SFC_slow_counts[size-3]; assign countout[outputwidth-2:0] = {SFC_slow_counts[size-4:0],fast_counts}; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v index c8c8c5650..81d8236fa 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +++ b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v @@ -24,6 +24,9 @@ //-- -- //--------------------------------------------------------------------- +`ifndef BASIL_TDL_TDC_DELAYLINE_CARRYSAMPLER_SPARTAN6_20PS_V +`define BASIL_TDL_TDC_DELAYLINE_CARRYSAMPLER_SPARTAN6_20PS_V + module CHAIN_CELL (CINIT, CI, CO, DO, CLK); output wire [3:0] DO; @@ -110,3 +113,5 @@ module carry_sampler_spartan6 (d, q, CLK); `endif endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v index c98039893..ada34826a 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +++ b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v @@ -1,3 +1,6 @@ +`ifndef BASIL_TDL_TDC_DELAYLINE_SAMPLE_DESER_V +`define BASIL_TDL_TDC_DELAYLINE_SAMPLE_DESER_V + module sample_deser #( parameter dlyline_bits = 96, parameter internally_rising = 1'b1, @@ -113,3 +116,5 @@ always @(posedge CLK_SLOW) begin end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/priority_encoder.v b/basil/firmware/modules/tdl_tdc/priority_encoder.v index ef2337ac8..e16ff9fc2 100644 --- a/basil/firmware/modules/tdl_tdc/priority_encoder.v +++ b/basil/firmware/modules/tdl_tdc/priority_encoder.v @@ -4,6 +4,9 @@ //* SiLab, Physics Institute, University of Bonn //* ------------------------------------------------------------ //*/ +`ifndef BASIL_TDL_TDC_PRIORITY_ENCODER_V +`define BASIL_TDL_TDC_PRIORITY_ENCODER_V + module priority_encoder( input wire CLK, input wire [96-1:0] sample, @@ -70,3 +73,5 @@ end endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/sw_interface.v b/basil/firmware/modules/tdl_tdc/sw_interface.v index cbed4b8cb..37f247c09 100644 --- a/basil/firmware/modules/tdl_tdc/sw_interface.v +++ b/basil/firmware/modules/tdl_tdc/sw_interface.v @@ -1,19 +1,10 @@ +`ifndef BASIL_TDL_TDC_SW_INTERFACE_V +`define BASIL_TDL_TDC_SW_INTERFACE_V + `include "tdl_tdc/utils/graycode_2stage_cdc.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif module tdc_sw_interface #( parameter VERSION = 8'b00000000, @@ -265,3 +256,5 @@ assign arm_flag = ~ext_arm_clk_ff & ext_arm_clk; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/tdl_supersampler.v b/basil/firmware/modules/tdl_tdc/tdl_supersampler.v index c8f9221dc..3837b5fcc 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +++ b/basil/firmware/modules/tdl_tdc/tdl_supersampler.v @@ -1,3 +1,6 @@ +`ifndef BASIL_TDL_TDC_TDL_SUPERSAMPLER_V +`define BASIL_TDL_TDC_TDL_SUPERSAMPLER_V + `include "tdl_tdc/delayline/carrysampler_spartan6_20ps.v" `include "tdl_tdc/delayline/sample_deser.v" @@ -46,3 +49,5 @@ sample_deser #( assign sample = internally_rising ? hit_sample : ~hit_sample; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc.v b/basil/firmware/modules/tdl_tdc/tdl_tdc.v index ead1dee2f..543940be0 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc.v @@ -5,18 +5,13 @@ * ------------------------------------------------------------ */ +`ifndef BASIL_TDL_TDC_TDL_TDC_V +`define BASIL_TDL_TDC_TDL_TDC_V + `include "tdl_tdc/sw_interface.v" `include "tdl_tdc/tdl_tdc_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" module tdl_tdc #( @@ -178,3 +173,5 @@ tdc_sw_interface #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v b/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v index 5270f1a3f..fe3f339ee 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v @@ -5,6 +5,9 @@ * ------------------------------------------------------------ */ +`ifndef BASIL_TDL_TDC_TDL_TDC_CORE_V +`define BASIL_TDL_TDC_TDL_TDC_CORE_V + `include "tdl_tdc/tdl_supersampler.v" `include "tdl_tdc/counter/slimfast_multioption_counter.v" `include "tdl_tdc/controller.v" @@ -205,3 +208,5 @@ word_broker #( .out_word(out_word) ); endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/utils/delay_n.v b/basil/firmware/modules/tdl_tdc/utils/delay_n.v index 7d0bcc4fb..0a38a8edf 100644 --- a/basil/firmware/modules/tdl_tdc/utils/delay_n.v +++ b/basil/firmware/modules/tdl_tdc/utils/delay_n.v @@ -1,3 +1,6 @@ +`ifndef BASIL_TDL_TDC_UTILS_DELAY_N_V +`define BASIL_TDL_TDC_UTILS_DELAY_N_V + module delay_n #( parameter n = 3, parameter width = 8 @@ -21,3 +24,5 @@ end assign delayed_signal = delay_taps[n-1]; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v b/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v index b71463885..c1cca058f 100644 --- a/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +++ b/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v @@ -1,3 +1,6 @@ +`ifndef BASIL_TDL_TDC_UTILS_GRAYCODE_2STAGE_CDC_V +`define BASIL_TDL_TDC_UTILS_GRAYCODE_2STAGE_CDC_V + module graycode_2stage_cdc #(DATA_WIDTH = 8) ( input wire IN_CLK, input wire OUT_CLK, @@ -26,3 +29,5 @@ end assign data_out_clk = data_bus_clk; endmodule + +`endif diff --git a/basil/firmware/modules/tdl_tdc/word_broker.v b/basil/firmware/modules/tdl_tdc/word_broker.v index b77458e19..b90cae2f8 100644 --- a/basil/firmware/modules/tdl_tdc/word_broker.v +++ b/basil/firmware/modules/tdl_tdc/word_broker.v @@ -1,3 +1,6 @@ +`ifndef BASIL_TDL_TDC_WORD_BROKER_V +`define BASIL_TDL_TDC_WORD_BROKER_V + module word_broker #( parameter DATA_IDENTIFIER = 4'b0100, parameter state_bits = 4, @@ -124,3 +127,5 @@ always @(posedge CLK) begin end endmodule + +`endif diff --git a/basil/firmware/modules/timestamp/timestamp.v b/basil/firmware/modules/timestamp/timestamp.v index a3f303c5b..e9820b281 100644 --- a/basil/firmware/modules/timestamp/timestamp.v +++ b/basil/firmware/modules/timestamp/timestamp.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_TIMESTAMP_TIMESTAMP_V +`define BASIL_TIMESTAMP_TIMESTAMP_V + `include "timestamp/timestamp_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -85,3 +84,5 @@ timestamp_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/timestamp/timestamp_core.v b/basil/firmware/modules/timestamp/timestamp_core.v index 3728eea29..cb86cdd84 100644 --- a/basil/firmware/modules/timestamp/timestamp_core.v +++ b/basil/firmware/modules/timestamp/timestamp_core.v @@ -4,21 +4,17 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// cdc_pulse_sync is shared across several basil modules; guard against double inclusion -`ifndef CDC_PULSE_SYNC_V +`ifndef BASIL_TIMESTAMP_TIMESTAMP_CORE_V +`define BASIL_TIMESTAMP_TIMESTAMP_CORE_V + `include "utils/cdc_pulse_sync.v" -`define CDC_PULSE_SYNC_V -`endif -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" `timescale 1ps/1ps `default_nettype none + module timestamp_core #( parameter ABUSWIDTH = 16, parameter IDENTIFIER = 4'b0001 @@ -223,3 +219,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tlu/tlu_controller.v b/basil/firmware/modules/tlu/tlu_controller.v index 939332ee1..31eea8b0f 100644 --- a/basil/firmware/modules/tlu/tlu_controller.v +++ b/basil/firmware/modules/tlu/tlu_controller.v @@ -4,12 +4,11 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_TLU_TLU_CONTROLLER_V +`define BASIL_TLU_TLU_CONTROLLER_V + `include "tlu/tlu_controller_core.v" -// bus_to_ip is shared across several basil modules; guard against double inclusion -`ifndef BUS_TO_IP_V `include "utils/bus_to_ip.v" -`define BUS_TO_IP_V -`endif `timescale 1ps/1ps `default_nettype none @@ -126,3 +125,5 @@ tlu_controller_core #( ); endmodule + +`endif diff --git a/basil/firmware/modules/tlu/tlu_controller_core.v b/basil/firmware/modules/tlu/tlu_controller_core.v index 096ee3d61..a503ab150 100644 --- a/basil/firmware/modules/tlu/tlu_controller_core.v +++ b/basil/firmware/modules/tlu/tlu_controller_core.v @@ -4,22 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -// flag_domain_crossing is shared across several basil modules; guard against double inclusion -`ifndef FLAG_DOMAIN_CROSSING_V +`ifndef BASIL_TLU_TLU_CONTROLLER_CORE_V +`define BASIL_TLU_TLU_CONTROLLER_CORE_V + `include "utils/flag_domain_crossing.v" -`define FLAG_DOMAIN_CROSSING_V -`endif -// three_stage_synchronizer is shared across several basil modules; guard against double inclusion -`ifndef THREE_STAGE_SYNCHRONIZER_V `include "utils/3_stage_synchronizer.v" -`define THREE_STAGE_SYNCHRONIZER_V -`endif `include "tlu/tlu_controller_fsm.v" -// cdc_syncfifo is shared across several basil modules; guard against double inclusion -`ifndef CDC_SYNCFIFO_V `include "utils/cdc_syncfifo.v" -`define CDC_SYNCFIFO_V -`endif `include "utils/generic_fifo.v" `timescale 1ps/1ps @@ -32,6 +23,8 @@ * * TLU controller supporting EUDET TLU 0.1/0.2 */ +`default_nettype none + module tlu_controller_core #( parameter ABUSWIDTH = 16, @@ -943,3 +936,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/tlu/tlu_controller_fsm.v b/basil/firmware/modules/tlu/tlu_controller_fsm.v index 866556c3e..a0b654c58 100644 --- a/basil/firmware/modules/tlu/tlu_controller_fsm.v +++ b/basil/firmware/modules/tlu/tlu_controller_fsm.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_TLU_TLU_CONTROLLER_FSM_V +`define BASIL_TLU_TLU_CONTROLLER_FSM_V + `timescale 1ps/1ps `default_nettype none + module tlu_controller_fsm #( parameter DIVISOR = 8, parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17, @@ -581,3 +585,5 @@ chipscope_ila ichipscope_ila `endif endmodule + +`endif diff --git a/basil/firmware/modules/uart/uart.v b/basil/firmware/modules/uart/uart.v index 0ec3193ef..fed561193 100644 --- a/basil/firmware/modules/uart/uart.v +++ b/basil/firmware/modules/uart/uart.v @@ -1,3 +1,6 @@ +`ifndef BASIL_UART_UART_V +`define BASIL_UART_UART_V + `timescale 1ns / 1ps // Documented Verilog UART // Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz) @@ -194,3 +197,5 @@ always @(posedge clk) begin //or posedge rst end endmodule + +`endif diff --git a/basil/firmware/modules/uart/uart_master.v b/basil/firmware/modules/uart/uart_master.v index 9d71e93a3..e370ac846 100644 --- a/basil/firmware/modules/uart/uart_master.v +++ b/basil/firmware/modules/uart/uart_master.v @@ -12,6 +12,9 @@ * Initial version: M. Lemarenko */ +`ifndef BASIL_UART_UART_MASTER_V +`define BASIL_UART_UART_MASTER_V + module uart_master( input UART_CLK_X4, input UART_RST, @@ -271,3 +274,5 @@ always @(posedge clk or posedge UART_RST) endmodule + +`endif diff --git a/basil/firmware/modules/utils/3_stage_synchronizer.v b/basil/firmware/modules/utils/3_stage_synchronizer.v index 12f2d145b..d15dc3370 100644 --- a/basil/firmware/modules/utils/3_stage_synchronizer.v +++ b/basil/firmware/modules/utils/3_stage_synchronizer.v @@ -4,10 +4,12 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_3_STAGE_SYNCHRONIZER_V +`define BASIL_UTILS_3_STAGE_SYNCHRONIZER_V + `timescale 1ps/1ps `default_nettype none -// synchronizing asynchronous signals/flags, prevents metastable events module three_stage_synchronizer #( parameter WIDTH = 1 @@ -39,3 +41,5 @@ end assign OUT = out_d_ff_3; endmodule + +`endif diff --git a/basil/firmware/modules/utils/BUFG.v b/basil/firmware/modules/utils/BUFG.v index e42bb0e7e..c3bf680f6 100644 --- a/basil/firmware/modules/utils/BUFG.v +++ b/basil/firmware/modules/utils/BUFG.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_BUFG_V +`define BASIL_UTILS_BUFG_V + `timescale 1ps/1ps `default_nettype none @@ -16,3 +19,5 @@ module BUFG ( assign O = I; endmodule + +`endif diff --git a/basil/firmware/modules/utils/CG_MOD_neg.v b/basil/firmware/modules/utils/CG_MOD_neg.v index d62302473..5c46f3c52 100644 --- a/basil/firmware/modules/utils/CG_MOD_neg.v +++ b/basil/firmware/modules/utils/CG_MOD_neg.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CG_MOD_NEG_V +`define BASIL_UTILS_CG_MOD_NEG_V + `timescale 1ps/1ps `default_nettype none @@ -27,3 +30,5 @@ if (ck_in) assign ck_out = ck_in | ~enl; endmodule + +`endif diff --git a/basil/firmware/modules/utils/CG_MOD_pos.v b/basil/firmware/modules/utils/CG_MOD_pos.v index fb8c08e3c..f3f1aa209 100644 --- a/basil/firmware/modules/utils/CG_MOD_pos.v +++ b/basil/firmware/modules/utils/CG_MOD_pos.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CG_MOD_POS_V +`define BASIL_UTILS_CG_MOD_POS_V + `timescale 1ps/1ps `default_nettype none @@ -28,3 +31,5 @@ if (ck_inb) assign ck_out = ck_in & enl; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IBUFDS.v b/basil/firmware/modules/utils/IBUFDS.v index 97063b439..464d25f41 100644 --- a/basil/firmware/modules/utils/IBUFDS.v +++ b/basil/firmware/modules/utils/IBUFDS.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IBUFDS_V +`define BASIL_UTILS_IBUFDS_V + `timescale 1ps/1ps `default_nettype none @@ -19,3 +22,5 @@ module IBUFDS #( assign O = I && !IB; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR.v b/basil/firmware/modules/utils/IDDR.v index 3e9e2610e..dba89a11d 100644 --- a/basil/firmware/modules/utils/IDDR.v +++ b/basil/firmware/modules/utils/IDDR.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IDDR_V +`define BASIL_UTILS_IDDR_V + `timescale 1ps/1ps `default_nettype none @@ -42,3 +45,5 @@ end endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_s3.v b/basil/firmware/modules/utils/IDDR_s3.v index 1746699c0..4ce99c0f6 100644 --- a/basil/firmware/modules/utils/IDDR_s3.v +++ b/basil/firmware/modules/utils/IDDR_s3.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IDDR_S3_V +`define BASIL_UTILS_IDDR_S3_V + `timescale 1ps/1ps `default_nettype none @@ -25,3 +28,5 @@ IFDDRRSE IFDDRRSE_inst ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_s3_noibuf.v b/basil/firmware/modules/utils/IDDR_s3_noibuf.v index b96a51f3c..8e6bcba43 100644 --- a/basil/firmware/modules/utils/IDDR_s3_noibuf.v +++ b/basil/firmware/modules/utils/IDDR_s3_noibuf.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IDDR_S3_NOIBUF_V +`define BASIL_UTILS_IDDR_S3_NOIBUF_V + `timescale 1ps/1ps `default_nettype none @@ -34,3 +37,5 @@ FDRSE F1 ( defparam F1.INIT = "0"; endmodule + +`endif diff --git a/basil/firmware/modules/utils/IDDR_s6.v b/basil/firmware/modules/utils/IDDR_s6.v index 335c03e1c..ebf49f25c 100644 --- a/basil/firmware/modules/utils/IDDR_s6.v +++ b/basil/firmware/modules/utils/IDDR_s6.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_IDDR_S6_V +`define BASIL_UTILS_IDDR_S6_V + `timescale 1ps/1ps `default_nettype none @@ -25,3 +28,5 @@ IDDR2 IDDR2_inst ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/ODDR_s3.v b/basil/firmware/modules/utils/ODDR_s3.v index c823d2205..18c8f8e58 100644 --- a/basil/firmware/modules/utils/ODDR_s3.v +++ b/basil/firmware/modules/utils/ODDR_s3.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_ODDR_S3_V +`define BASIL_UTILS_ODDR_S3_V + `timescale 1ps/1ps `default_nettype none @@ -26,3 +29,5 @@ OFDDRRSE OFDDRRSE_INST ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/ODDR_s6.v b/basil/firmware/modules/utils/ODDR_s6.v index 1245c4d7b..9f1e27368 100644 --- a/basil/firmware/modules/utils/ODDR_s6.v +++ b/basil/firmware/modules/utils/ODDR_s6.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_ODDR_S6_V +`define BASIL_UTILS_ODDR_S6_V + `timescale 1ps/1ps `default_nettype none @@ -26,3 +29,5 @@ ODDR2 ODDR2_inst ( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/PLLE2_BASE.v b/basil/firmware/modules/utils/PLLE2_BASE.v index 3529e0644..d8167c861 100644 --- a/basil/firmware/modules/utils/PLLE2_BASE.v +++ b/basil/firmware/modules/utils/PLLE2_BASE.v @@ -1,5 +1,8 @@ // Blackbox simulation model for PLLE2_BASE primitive // Xilinx PLL base module +`ifndef BASIL_UTILS_PLLE2_BASE_V +`define BASIL_UTILS_PLLE2_BASE_V + (* blackbox *) module PLLE2_BASE #( parameter BANDWIDTH = "OPTIMIZED", @@ -42,3 +45,5 @@ module PLLE2_BASE #( input wire CLKFBIN ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/bus_to_ip.v b/basil/firmware/modules/utils/bus_to_ip.v index 7e284e7b8..632a9cebf 100644 --- a/basil/firmware/modules/utils/bus_to_ip.v +++ b/basil/firmware/modules/utils/bus_to_ip.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_BUS_TO_IP_V +`define BASIL_UTILS_BUS_TO_IP_V + `timescale 1ps/1ps `default_nettype none @@ -42,3 +45,5 @@ assign IP_DATA_IN = BUS_DATA; assign BUS_DATA = (CS && BUS_WR) ? {DBUSWIDTH{1'bz}} : (CS ? IP_DATA_OUT : {DBUSWIDTH{1'bz}}); endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_pulse_sync.v b/basil/firmware/modules/utils/cdc_pulse_sync.v index ec46bfff9..15176e443 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CDC_PULSE_SYNC_V +`define BASIL_UTILS_CDC_PULSE_SYNC_V + `timescale 1ps/1ps `default_nettype none + // Closed loop solution module cdc_pulse_sync ( @@ -58,3 +62,5 @@ end assign aq_sync = aq_sync_ff_2; endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v b/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v index e31130241..7972ea387 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CDC_PULSE_SYNC_CNT_V +`define BASIL_UTILS_CDC_PULSE_SYNC_CNT_V + `timescale 1ps/1ps `default_nettype none @@ -35,3 +38,5 @@ end assign pulse_out = !out_sync_ff_3 && out_sync_ff_2; endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_reset_sync.v b/basil/firmware/modules/utils/cdc_reset_sync.v index c6de1b81d..696968352 100644 --- a/basil/firmware/modules/utils/cdc_reset_sync.v +++ b/basil/firmware/modules/utils/cdc_reset_sync.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CDC_RESET_SYNC_V +`define BASIL_UTILS_CDC_RESET_SYNC_V + `timescale 1ps/1ps `default_nettype none + // Closed loop solution module cdc_reset_sync ( @@ -52,3 +56,5 @@ end assign aq_sync = aq_sync_ff_2; endmodule + +`endif diff --git a/basil/firmware/modules/utils/cdc_syncfifo.v b/basil/firmware/modules/utils/cdc_syncfifo.v index 89b0d4b19..5bbff936b 100644 --- a/basil/firmware/modules/utils/cdc_syncfifo.v +++ b/basil/firmware/modules/utils/cdc_syncfifo.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CDC_SYNCFIFO_V +`define BASIL_UTILS_CDC_SYNCFIFO_V + `timescale 1ps/1ps `default_nettype none @@ -116,8 +119,6 @@ always @(posedge wclk) endmodule - - module rptr_empty #( parameter ADDRSIZE = 2 ) ( @@ -221,3 +222,5 @@ always @(posedge rclk) else {rq2_wptr,cdc_sync_rq1_wptr} <= {cdc_sync_rq1_wptr,wptr}; endmodule + +`endif diff --git a/basil/firmware/modules/utils/clock_divider.v b/basil/firmware/modules/utils/clock_divider.v index 1a1cf1b9b..96fbe436b 100644 --- a/basil/firmware/modules/utils/clock_divider.v +++ b/basil/firmware/modules/utils/clock_divider.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_CLOCK_DIVIDER_V +`define BASIL_UTILS_CLOCK_DIVIDER_V + `timescale 1ps/1ps `default_nettype none + // clock divider generating clock and clock enable module clock_divider #( @@ -96,3 +100,5 @@ always @(posedge CLK or posedge RESET) end endmodule + +`endif diff --git a/basil/firmware/modules/utils/clock_multiplier.v b/basil/firmware/modules/utils/clock_multiplier.v index 209a2e903..67e4ff113 100644 --- a/basil/firmware/modules/utils/clock_multiplier.v +++ b/basil/firmware/modules/utils/clock_multiplier.v @@ -1,3 +1,6 @@ +`ifndef BASIL_UTILS_CLOCK_MULTIPLIER_V +`define BASIL_UTILS_CLOCK_MULTIPLIER_V + `timescale 1ps / 1ps module clock_multiplier #( @@ -28,3 +31,5 @@ initial begin end endmodule + +`endif diff --git a/basil/firmware/modules/utils/ddr_des.v b/basil/firmware/modules/utils/ddr_des.v index a2a96d42f..2b967d78e 100644 --- a/basil/firmware/modules/utils/ddr_des.v +++ b/basil/firmware/modules/utils/ddr_des.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_DDR_DES_V +`define BASIL_UTILS_DDR_DES_V + `timescale 1ps/1ps `default_nettype none @@ -57,3 +60,5 @@ always @(posedge WCLK) OUT <= DATA_IN_SR; endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_32_to_8.v b/basil/firmware/modules/utils/fifo_32_to_8.v index 3b3ad49f7..73c53279d 100644 --- a/basil/firmware/modules/utils/fifo_32_to_8.v +++ b/basil/firmware/modules/utils/fifo_32_to_8.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_FIFO_32_TO_8_V +`define BASIL_UTILS_FIFO_32_TO_8_V + `timescale 1ps/1ps `default_nettype none @@ -62,3 +65,5 @@ assign FIFO_DATA_OUT_BYTE[3] = DATA_BUF[31:24]; assign DATA_OUT = FIFO_DATA_OUT_BYTE[byte_cnt]; endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_64_to_16.v b/basil/firmware/modules/utils/fifo_64_to_16.v index e70ffcbc8..ef3dad691 100644 --- a/basil/firmware/modules/utils/fifo_64_to_16.v +++ b/basil/firmware/modules/utils/fifo_64_to_16.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_FIFO_64_TO_16_V +`define BASIL_UTILS_FIFO_64_TO_16_V + `timescale 1ps/1ps `default_nettype none @@ -62,3 +65,5 @@ assign FIFO_DATA_OUT_BYTE[3] = DATA_BUF[63:48]; assign DATA_OUT = FIFO_DATA_OUT_BYTE[byte_cnt]; endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_8_to_32.v b/basil/firmware/modules/utils/fifo_8_to_32.v index 4821a8d9c..d77e307b0 100644 --- a/basil/firmware/modules/utils/fifo_8_to_32.v +++ b/basil/firmware/modules/utils/fifo_8_to_32.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_FIFO_8_TO_32_V +`define BASIL_UTILS_FIFO_8_TO_32_V + `timescale 1ps/1ps `default_nettype none @@ -110,3 +113,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/fifo_8_to_64.v b/basil/firmware/modules/utils/fifo_8_to_64.v index 0069872b1..855ea34ca 100644 --- a/basil/firmware/modules/utils/fifo_8_to_64.v +++ b/basil/firmware/modules/utils/fifo_8_to_64.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_FIFO_8_TO_64_V +`define BASIL_UTILS_FIFO_8_TO_64_V + `timescale 1ps/1ps `default_nettype none @@ -118,3 +121,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/flag_domain_crossing.v b/basil/firmware/modules/utils/flag_domain_crossing.v index da526a3ff..b2c621c1f 100644 --- a/basil/firmware/modules/utils/flag_domain_crossing.v +++ b/basil/firmware/modules/utils/flag_domain_crossing.v @@ -4,9 +4,13 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_FLAG_DOMAIN_CROSSING_V +`define BASIL_UTILS_FLAG_DOMAIN_CROSSING_V + `timescale 1ps/1ps `default_nettype none + // synchronize flag (signal lasts just one clock cycle) to new clock domain (CLK_B) module flag_domain_crossing( @@ -49,3 +53,5 @@ end assign FLAG_OUT_CLK_B = (flag_out_d_ff_3 ^ flag_out_d_ff_2); // XOR endmodule + +`endif diff --git a/basil/firmware/modules/utils/fx2_to_bus.v b/basil/firmware/modules/utils/fx2_to_bus.v index 89a87268c..8d6576660 100644 --- a/basil/firmware/modules/utils/fx2_to_bus.v +++ b/basil/firmware/modules/utils/fx2_to_bus.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_FX2_TO_BUS_V +`define BASIL_UTILS_FX2_TO_BUS_V + `timescale 1ps/1ps `default_nettype none @@ -39,3 +42,5 @@ assign BUS_RD = ~RD_B & RD_B_FF; assign BUS_WR = ~WR_B; endmodule + +`endif diff --git a/basil/firmware/modules/utils/generic_fifo.v b/basil/firmware/modules/utils/generic_fifo.v index 181e984f3..74fd24173 100644 --- a/basil/firmware/modules/utils/generic_fifo.v +++ b/basil/firmware/modules/utils/generic_fifo.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_GENERIC_FIFO_V +`define BASIL_UTILS_GENERIC_FIFO_V + `timescale 1ps/1ps `default_nettype none @@ -135,3 +138,5 @@ generic_fifo #( ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/pulse_gen_rising.v b/basil/firmware/modules/utils/pulse_gen_rising.v index 659d2f122..c11d16c6e 100644 --- a/basil/firmware/modules/utils/pulse_gen_rising.v +++ b/basil/firmware/modules/utils/pulse_gen_rising.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_PULSE_GEN_RISING_V +`define BASIL_UTILS_PULSE_GEN_RISING_V + `timescale 1ps/1ps `default_nettype none @@ -21,3 +24,5 @@ always @(posedge clk_in) assign out = !ff && in; endmodule + +`endif diff --git a/basil/firmware/modules/utils/ramb_8_to_n.v b/basil/firmware/modules/utils/ramb_8_to_n.v index d86d69082..f50da3b78 100644 --- a/basil/firmware/modules/utils/ramb_8_to_n.v +++ b/basil/firmware/modules/utils/ramb_8_to_n.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef BASIL_UTILS_RAMB_8_TO_N_V +`define BASIL_UTILS_RAMB_8_TO_N_V + module ramb_8_to_n (clkA, clkB, weA, @@ -127,3 +131,5 @@ endgenerate endmodule + +`endif diff --git a/basil/firmware/modules/utils/rbcp_to_bus.v b/basil/firmware/modules/utils/rbcp_to_bus.v index 81e8acb8c..b713ab711 100644 --- a/basil/firmware/modules/utils/rbcp_to_bus.v +++ b/basil/firmware/modules/utils/rbcp_to_bus.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_RBCP_TO_BUS_V +`define BASIL_UTILS_RBCP_TO_BUS_V + `timescale 1ps/1ps `default_nettype none @@ -65,3 +68,5 @@ chipscope_ila ichipscope_ila */ endmodule + +`endif diff --git a/basil/firmware/modules/utils/reset_gen.v b/basil/firmware/modules/utils/reset_gen.v index 6e829733b..ce1507538 100644 --- a/basil/firmware/modules/utils/reset_gen.v +++ b/basil/firmware/modules/utils/reset_gen.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_RESET_GEN_V +`define BASIL_UTILS_RESET_GEN_V + `timescale 1ps/1ps `default_nettype none @@ -29,3 +32,5 @@ always @(posedge CLK) assign RST = (rst_cnt != 0 ); endmodule + +`endif diff --git a/basil/firmware/modules/utils/rgmii_io.v b/basil/firmware/modules/utils/rgmii_io.v index 0ba6f03dd..57067f2ab 100644 --- a/basil/firmware/modules/utils/rgmii_io.v +++ b/basil/firmware/modules/utils/rgmii_io.v @@ -9,6 +9,9 @@ /////////////////////////////////////////////////////////////////////////////// +`ifndef BASIL_UTILS_RGMII_IO_V +`define BASIL_UTILS_RGMII_IO_V + module rgmii_io ( //----------------------------------------------------------------------- //-- Pad side signals @@ -353,3 +356,5 @@ assign gmii_col_int = (gmii_tx_en_int | gmii_tx_er_int) & (gmii_rx_dv_reg | gmii assign gmii_crs_int = (gmii_tx_en_int | gmii_tx_er_int) | (gmii_rx_dv_reg | gmii_rx_er_reg); endmodule // rgmii_io + +`endif diff --git a/basil/firmware/modules/utils/sbus_to_ip.v b/basil/firmware/modules/utils/sbus_to_ip.v index 03b87980a..d2d1bacd9 100644 --- a/basil/firmware/modules/utils/sbus_to_ip.v +++ b/basil/firmware/modules/utils/sbus_to_ip.v @@ -5,6 +5,10 @@ * ------------------------------------------------------------ */ + +`ifndef BASIL_UTILS_SBUS_TO_IP_V +`define BASIL_UTILS_SBUS_TO_IP_V + module sbus_to_ip #( parameter BASEADDR = 0, @@ -47,3 +51,5 @@ end assign BUS_DATA_OUT = (CS_PREV ? IP_DATA_OUT : {DBUSWIDTH{1'b0}}); endmodule + +`endif diff --git a/basil/firmware/modules/utils/simple_arbiter.v b/basil/firmware/modules/utils/simple_arbiter.v index e35818b01..1d73d2b6a 100644 --- a/basil/firmware/modules/utils/simple_arbiter.v +++ b/basil/firmware/modules/utils/simple_arbiter.v @@ -4,6 +4,9 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_SIMPLE_ARBITER_V +`define BASIL_UTILS_SIMPLE_ARBITER_V + `timescale 1ps/1ps `default_nettype none @@ -29,3 +32,5 @@ wire [2*WIDTH-1:0] double_grant = double_req & ~(double_req-base); assign grant = double_grant[WIDTH-1:0] | double_grant[2*WIDTH-1:WIDTH]; endmodule + +`endif diff --git a/basil/firmware/modules/utils/tcp_to_bus.v b/basil/firmware/modules/utils/tcp_to_bus.v index 691deb0d6..ce4122eb5 100644 --- a/basil/firmware/modules/utils/tcp_to_bus.v +++ b/basil/firmware/modules/utils/tcp_to_bus.v @@ -5,6 +5,9 @@ * ------------------------------------------------------------ */ +`ifndef BASIL_UTILS_TCP_TO_BUS_V +`define BASIL_UTILS_TCP_TO_BUS_V + `timescale 1ps / 1ps `default_nettype none @@ -153,3 +156,5 @@ assign BUS_ADD = (TCP_TO_BUS_WR) ? TCP_TO_BUS_ADD : RBCP_ADDR; assign BUS_DATA = (BUS_WR) ? ((TCP_TO_BUS_WR) ? TCP_RX_DATA : RBCP_WD) : 8'bz; endmodule + +`endif diff --git a/tests/test_SimFifo8to32.v b/tests/test_SimFifo8to32.v index 15d4c508a..7b86f6b3a 100644 --- a/tests/test_SimFifo8to32.v +++ b/tests/test_SimFifo8to32.v @@ -14,14 +14,9 @@ `endif `ifndef BASIL_SBUS -`include "utils/bus_to_ip.v" - -`include "utils/cdc_syncfifo.v" -`include "utils/fifo_8_to_32.v" -`include "utils/generic_fifo.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" +`include "utils/fifo_8_to_32.v" +`include "utils/cdc_syncfifo.v" `else $fatal("Sbus modules not implemented yet"); `endif diff --git a/tests/test_SimGpio.v b/tests/test_SimGpio.v index 588d206e0..be780baa0 100644 --- a/tests/test_SimGpio.v +++ b/tests/test_SimGpio.v @@ -13,9 +13,7 @@ `define SPLIT_BUS `endif -`include "gpio/gpio_core.v" `ifndef BASIL_SBUS - `include "utils/bus_to_ip.v" `include "gpio/gpio.v" `else `include "utils/sbus_to_ip.v" diff --git a/tests/test_SimJtagGpio.v b/tests/test_SimJtagGpio.v index a344aa70a..1d1fe1c1a 100644 --- a/tests/test_SimJtagGpio.v +++ b/tests/test_SimJtagGpio.v @@ -7,8 +7,6 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" -`include "gpio/gpio_core.v" `include "gpio/gpio.v" module tb ( diff --git a/tests/test_SimSeq.v b/tests/test_SimSeq.v index e98c689f6..ad7cf2a19 100644 --- a/tests/test_SimSeq.v +++ b/tests/test_SimSeq.v @@ -7,21 +7,9 @@ `timescale 1ps / 1ps -`include "utils/bus_to_ip.v" - `include "pulse_gen/pulse_gen.v" -`include "pulse_gen/pulse_gen_core.v" - `include "seq_gen/seq_gen.v" -`include "seq_gen/seq_gen_core.v" - `include "seq_rec/seq_rec.v" -`include "seq_rec/seq_rec_core.v" - -`include "utils/3_stage_synchronizer.v" -`include "utils/flag_domain_crossing.v" -`include "utils/cdc_pulse_sync.v" -`include "utils/ramb_8_to_n.v" module tb ( diff --git a/tests/test_SimTlu.v b/tests/test_SimTlu.v index 27d73cac9..3a30df3a7 100644 --- a/tests/test_SimTlu.v +++ b/tests/test_SimTlu.v @@ -7,24 +7,11 @@ `timescale 1ps / 1ps -`include "gpio/gpio_core.v" `include "gpio/gpio.v" - -`include "tlu/tlu_controller_core.v" -`include "tlu/tlu_controller_fsm.v" `include "tlu/tlu_controller.v" - -`include "bram_fifo/bram_fifo_core.v" `include "bram_fifo/bram_fifo.v" - -`include "utils/bus_to_ip.v" - `include "utils/cdc_syncfifo.v" `include "utils/flag_domain_crossing.v" -`include "utils/generic_fifo.v" -`include "utils/3_stage_synchronizer.v" - -`include "utils/cdc_pulse_sync.v" module tlu_model ( input wire SYS_CLK, SYS_RST, TLU_CLOCK, TLU_BUSY, ENABLE, From bcbeb0fac5d45f3cd4184211a5db334a7f035eb3 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Fri, 22 May 2026 23:48:07 +0200 Subject: [PATCH 36/43] chore: update simulation test config --- .gitignore | 3 +++ pyproject.toml | 20 +++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index d70f0cd5e..68bb5bfbd 100644 --- a/.gitignore +++ b/.gitignore @@ -36,6 +36,9 @@ host/tests/Makefile docs/_build *.vcd tests/results.xml +sim_build +Makefile +*.out examples/lx9/device/src/SiTCP # PyDev files diff --git a/pyproject.toml b/pyproject.toml index c9d164fbc..0feb3236b 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -8,7 +8,7 @@ dynamic = ["version"] license = { "text" = "BSD 3-Clause ('BSD New' or 'BSD Simplified') License" } description = "Basil is a modular data acquisition system and system testing framework in Python.\nIt also provides generic FPGA firmware modules for different hardware platforms and drivers for wide range of lab appliances." readme = "README.md" -requires-python = ">=3.10" +requires-python = ">=3.10,<3.14" authors = [ {name = "Tomasz Hemperek", email="hemperek@uni-bonn.de"}, {name = "Jens Janssen", email="janssen@physik.uni-bonn.de"}, @@ -27,6 +27,10 @@ dependencies = [ "GitPython", "six", "ruamel.yaml", + "cocotb>=2.0.1", + "cocotb-bus>=0.3.0", + "pytest>=9.0.3", + "cocotb-test>=0.2.6", ] [project.urls] @@ -35,6 +39,17 @@ dependencies = [ [project.optional-dependencies] hw = ["pyserial", "PyVISA"] +test = [ + "coverage", + "coveralls", + "cocotb>=2.0.1", + "cocotb-bus>=0.3.0", + "cocotb-test>=0.2.6", + "pytest>=9.0.3", + "pytest-cov", + "PyVISA", + "pyvisa-sim", +] [tool.setuptools] include-package-data = true @@ -51,3 +66,6 @@ profile = "black" [tool.ruff] # Set the maximum line length to 180. line-length = 120 + +[tool.uv.sources] +cocotb-test = { git = "https://github.com/themperek/cocotb-test.git", rev = "4e6b7db" } From 0b6a99239aa739b816071b82d696c941d9f43f95 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Sat, 23 May 2026 00:43:13 +0200 Subject: [PATCH 37/43] fix: clean up Verilator simulation lint issues --- basil/firmware/modules/gpio/gpio_core.v | 4 ++-- basil/firmware/modules/tdl_tdc/controller.v | 3 +++ basil/firmware/modules/tlu/tlu_controller_fsm.v | 4 ++++ tests/test_SimJtagMaster.v | 4 ++-- tests/test_SimTdl_Tdc.v | 16 ++++++++-------- 5 files changed, 19 insertions(+), 12 deletions(-) diff --git a/basil/firmware/modules/gpio/gpio_core.v b/basil/firmware/modules/gpio/gpio_core.v index 8669b5f88..06379318d 100644 --- a/basil/firmware/modules/gpio/gpio_core.v +++ b/basil/firmware/modules/gpio/gpio_core.v @@ -12,8 +12,8 @@ module gpio_core #( parameter ABUSWIDTH = 16, parameter IO_WIDTH = 8, - parameter IO_DIRECTION = 0, - parameter IO_TRI = 0 + parameter [IO_WIDTH-1:0] IO_DIRECTION = 0, + parameter [IO_WIDTH-1:0] IO_TRI = 0 ) ( BUS_CLK, BUS_RST, diff --git a/basil/firmware/modules/tdl_tdc/controller.v b/basil/firmware/modules/tdl_tdc/controller.v index 3503a757d..2ca1575dd 100644 --- a/basil/firmware/modules/tdl_tdc/controller.v +++ b/basil/firmware/modules/tdl_tdc/controller.v @@ -152,6 +152,8 @@ always @(posedge CLK) begin end MISSED: miss_cnt <= miss_cnt + 1; + default: begin + end endcase end @@ -227,6 +229,7 @@ always @(posedge CLK) begin CALIB_HIT: state <= CALIB; MISSED: state <= IDLE_TRIG; RESET: state <= IDLE; + default: state <= RESET; endcase end end diff --git a/basil/firmware/modules/tlu/tlu_controller_fsm.v b/basil/firmware/modules/tlu/tlu_controller_fsm.v index a0b654c58..fea57a478 100644 --- a/basil/firmware/modules/tlu/tlu_controller_fsm.v +++ b/basil/firmware/modules/tlu/tlu_controller_fsm.v @@ -552,6 +552,10 @@ begin FIFO_ACKNOWLEDGED <= 1'b1; end + default: + begin + end + endcase end end diff --git a/tests/test_SimJtagMaster.v b/tests/test_SimJtagMaster.v index ff13c7543..f668d9688 100644 --- a/tests/test_SimJtagMaster.v +++ b/tests/test_SimJtagMaster.v @@ -137,8 +137,8 @@ gpio #( .IO(debug_reg1) ); -output reg wr_fifo_FF; -output reg fifo_strobe; +reg wr_fifo_FF; +wire fifo_strobe; always @(posedge BUS_CLK) begin wr_fifo_FF <= wr_fifo; diff --git a/tests/test_SimTdl_Tdc.v b/tests/test_SimTdl_Tdc.v index 1b9403ce8..2823731f6 100644 --- a/tests/test_SimTdl_Tdc.v +++ b/tests/test_SimTdl_Tdc.v @@ -100,7 +100,7 @@ wire [2:0] TDC_FIFO_EMPTY; wire [31:0] TDC_FIFO_DATA [2:0]; wire [2:0] TDC_FIFO_READ; // First TDC module: creates fast sampled trigger signal to use it for other TDC modules. -tdc #( +tdl_tdc #( .BASEADDR(TDC_BASEADDR), .HIGHADDR(TDC_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), @@ -113,9 +113,9 @@ tdc #( .bus_wr(BUS_WR), .bus_rd(BUS_RD), - .CLK480(CLK480), - .CLK160(CLK160), - .CALIB_CLK(CLK125RX), + .CLK480(CLK_480), + .CLK160(CLK_160), + .CALIB_CLK(BUS_CLK), .tdc_in(TDC_IN[0]), .trig_in(TDC_TRIGGER_IN), @@ -131,7 +131,7 @@ tdc #( genvar i; generate for (i = 1; i < 3; i = i + 1) begin: tdc_gen - tdc #( + tdl_tdc #( .BASEADDR(TDC_BASEADDR + 32'h0100*i), .HIGHADDR(TDC_HIGHADDR + 21'h0100*i), .ABUSWIDTH(ABUSWIDTH), @@ -144,9 +144,9 @@ generate .bus_wr(BUS_WR), .bus_rd(BUS_RD), - .CLK480(CLK480), - .CLK160(CLK160), - .CALIB_CLK(CLK125RX), + .CLK480(CLK_480), + .CLK160(CLK_160), + .CALIB_CLK(BUS_CLK), .tdc_in(TDC_IN[i]), .trig_in(TDC_TRIGGER_IN), From 3d35ef54ac34c7f1fd33fbe2e148bc55ccff1bde Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Sat, 23 May 2026 01:11:50 +0200 Subject: [PATCH 38/43] refactor: share JTAG TAP simulation source --- basil/firmware/modules/includes/jtag_tap.v | 23 +- tests/jtag_tap.v | 570 --------------------- tests/test_SimJtagGpio.py | 5 +- tests/test_SimJtagMaster.py | 5 +- 4 files changed, 19 insertions(+), 584 deletions(-) delete mode 100644 tests/jtag_tap.v diff --git a/basil/firmware/modules/includes/jtag_tap.v b/basil/firmware/modules/includes/jtag_tap.v index a9b7ed3ed..a4ecc18a5 100644 --- a/basil/firmware/modules/includes/jtag_tap.v +++ b/basil/firmware/modules/includes/jtag_tap.v @@ -52,16 +52,17 @@ ///////////////////////////// //`include "simulator_features.v" ///////////////////////////// -`define UNIQUE //unique -`define FINISH_WITH_ERROR_EXIT_CODE //$finish -`define ASSERT_FALSE $display( "ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE +`define UNIQUE +`define FINISH_WITH_ERROR_EXIT_CODE +`define ASSERT_FALSE $display( "ERROR: Assertion failed in module %m." ); `FINISH_WITH_ERROR_EXIT_CODE ///////////////////////////// //`include "tap_defines.v" //////////////////////////// // This is similar to the IDCODE that the or1200 CPU uses, // only the new part number (IQ) is the or1200's value + 100 (decimal). -`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // or1200 uses 32'h149511c3. +// The or1200 uses 32'h149511c3. +`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // 0001 bits [31:28], version // 0100100110110101 bits [27:12], part number (IQ), 01001001010101010001 + 100 (decimal) // 00011100001 bits [11: 1], manufacturer id (flextronics) @@ -70,17 +71,19 @@ // JTAG Instructions. The Instruction Register is 4 bits long at the moment, // but 3 bits would do. However, this optimisation is probably not worth the trouble. -`define JTAG_INSTRUCTION_EXTEST 4'b0000 // Not supported at the moment. -`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 // Not supported at the moment. -`define JTAG_INSTRUCTION_IDCODE 4'b0010 // Supported. +// EXTEST and SAMPLE_PRELOAD are not supported at the moment; IDCODE is supported. +`define JTAG_INSTRUCTION_EXTEST 4'b0000 +`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 +`define JTAG_INSTRUCTION_IDCODE 4'b0010 // The following command is specific to OR10. Because the Xilinx TAP primitives have just 1 or 2 user-defined // JTAG instructions, all OR10 debug operations is performed with a single DEBUG instruction, // which can be mapped to one of Xilinx' user-defined instructions when using that interface. // If it weren't for this limitation, it would have been more comfortable to define // several JTAG instructions for the different types of OR10 debug operations. -`define JTAG_INSTRUCTION_DEBUG 4'b1000 // Specific to OR10, see comment above. -`define JTAG_INSTRUCTION_MBIST 4'b1001 // Not supported at the moment. -`define JTAG_INSTRUCTION_BYPASS 4'b1111 // Supported. According to the JTAG specification, the BYPASS instruction opcode must be all 1's. +// DEBUG is specific to OR10; MBIST is not supported. BYPASS must be all 1's. +`define JTAG_INSTRUCTION_DEBUG 4'b1000 +`define JTAG_INSTRUCTION_MBIST 4'b1001 +`define JTAG_INSTRUCTION_BYPASS 4'b1111 module jtag_tap #( parameter TRACE_JTAG_DATA = 0, diff --git a/tests/jtag_tap.v b/tests/jtag_tap.v deleted file mode 100644 index 9d0b2a908..000000000 --- a/tests/jtag_tap.v +++ /dev/null @@ -1,570 +0,0 @@ -`timescale 1ps / 1ps - -/* JTAG TAP interface - - This module can be replaced with special JTAG TAP primitives on Xilinx and Altera FPGAs. - Those primitives have similar interfaces; if you plan to modify this module's interface, - make sure you do not make it incompatible with the other ones. - - About the clock: it would have been easier to use the system clock in this module, - but the JTAG TAP interface should be able to work and do boundary scans - even when the main system clock is disabled. Relying on the JTAG clock - means that somewhere down the line crossing clock domains becomes necessary, - which can slow JTAG firmware transfers down. - - About the delay in the is_tap_state_xxx signals: - The is_tap_state_xxx are all delivered to the submodules delayed by 1 TCK posedge, see - the comment below for more information. I am not sure whether these signals also - get delayed when using the JTAG TAP primitives on Xilinx or Altera FPGAs. - - - Author(s): - Igor Mohor (igorm@opencores.org) - Nathan Yawn (nathan.yawn@opencores.org) - R. Diez (in 2012) - - NOTE: R. Diez has rewritten this module substantially and since then - it has only been tested against the OR10 OpenRISC implementation. - - Copyright (C) 2000 - 2012 Authors - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU Lesser General Public License version 3 - as published by the Free Software Foundation. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU Lesser General Public License version 3 for more details. - - You should have received a copy of the GNU Lesser General Public License - along with this program. If not, see . -*/ - -///////////////////////////// -//`include "simulator_features.v" -///////////////////////////// -`define UNIQUE //unique -`define FINISH_WITH_ERROR_EXIT_CODE //$finish -`define ASSERT_FALSE $display( "ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE - -///////////////////////////// -//`include "tap_defines.v" -//////////////////////////// -// This is similar to the IDCODE that the or1200 CPU uses, -// only the new part number (IQ) is the or1200's value + 100 (decimal). -`define OPENRISC_CPU_JTAG_IDCODE_VALUE 32'h149B51C3 // or1200 uses 32'h149511c3. - // 0001 bits [31:28], version - // 0100100110110101 bits [27:12], part number (IQ), 01001001010101010001 + 100 (decimal) - // 00011100001 bits [11: 1], manufacturer id (flextronics) - // 1 bit 0, always "1" as required by the JTAG standard - - -// JTAG Instructions. The Instruction Register is 4 bits long at the moment, -// but 3 bits would do. However, this optimisation is probably not worth the trouble. -`define JTAG_INSTRUCTION_EXTEST 4'b0000 // Not supported at the moment. -`define JTAG_INSTRUCTION_SAMPLE_PRELOAD 4'b0001 // Not supported at the moment. -`define JTAG_INSTRUCTION_IDCODE 4'b0010 // Supported. -// The following command is specific to OR10. Because the Xilinx TAP primitives have just 1 or 2 user-defined -// JTAG instructions, all OR10 debug operations is performed with a single DEBUG instruction, -// which can be mapped to one of Xilinx' user-defined instructions when using that interface. -// If it weren't for this limitation, it would have been more comfortable to define -// several JTAG instructions for the different types of OR10 debug operations. -`define JTAG_INSTRUCTION_DEBUG 4'b1000 // Specific to OR10, see comment above. -`define JTAG_INSTRUCTION_MBIST 4'b1001 // Not supported at the moment. -`define JTAG_INSTRUCTION_BYPASS 4'b1111 // Supported. According to the JTAG specification, the BYPASS instruction opcode must be all 1's. - -module jtag_tap - #( parameter TRACE_JTAG_DATA = 0, - parameter TRACE_STATE_MACHINE_TRANSITIONS = 0 ) - ( - // JTAG pads - input jtag_tms_i, // If unconnected or not used, the JTAG standard requires a value of 1. - input jtag_tck_i, - input jtag_trstn_i, // Test reset. Asynchronous, active at logic level 0. Therefore, if unconnected or not used, apply a value of 1. - input jtag_tdi_i, // If unconnected or not used, the JTAG standard requires a value of 1. - output reg jtag_tdo_o, // This pin should be tri-stated when not shifting data, - // but this module does not support an extra jtag_tdo_enable_o signal yet. - - // These previous state signals are delayed by one TCK clock cycle: - // when a TAP submodule gets the next TCK rising edge, these signals - // indicate what state the TAP was in at the last TCK rising edge. - output reg is_tap_state_test_logic_reset_o, // One TCK posedge delay to reset the submodule is fine, as long as - // the next TCK posedge comes soon enough. - output reg is_tap_state_shift_dr_o, // One TCK posedge delay is fine, as bits are shifted on the next TCK posedge - // after entering the Shift-DR state. - output reg is_tap_state_update_dr_o, // One TCK posedge delay is usually fine, the register update will happen a little later. - // This may be a problem if the next TCK posedge does not come, or takes a long time to come. - output reg is_tap_state_capture_dr_o, // One TCK posedge delay is usually fine, the register capture will happen a little later. - // This may be a problem if the next TCK posedge does not come, or takes a long time to come. - - - // This signal is also delayed by one TCK clock cycle, - // but that does not matter, as the current instruction changes only - // in state Update-IR, and in that state all the is_tap_state_xxx signals are zero. - // When any of the is_tap_state_xxx signals become active again, - // this signal is already available. - output reg is_tap_current_instruction_debug_o, - - // TDI signal from the debug submodule. - //input debug_tdo_i //TH - output reg [31:0] debug_reg //TH - ); - - // Length of the Instruction register. - localparam IR_LENGTH = 4; - - localparam TRACE_PREFIX = "JTAG TAP: "; - - - // TAP State Machine, fully JTAG compliant. - - localparam STATE_test_logic_reset = 4'd0; // The actual state values do not matter. - localparam STATE_run_test_idle = 4'd1; - localparam STATE_select_dr_scan = 4'd2; - localparam STATE_capture_dr = 4'd3; - localparam STATE_shift_dr = 4'd4; - localparam STATE_exit1_dr = 4'd5; - localparam STATE_pause_dr = 4'd6; - localparam STATE_exit2_dr = 4'd7; - localparam STATE_update_dr = 4'd8; - localparam STATE_select_ir_scan = 4'd9; - localparam STATE_capture_ir = 4'd10; - localparam STATE_shift_ir = 4'd11; // Once you enter this state, you'll shift at least 1 bit of information, as the TCK posedge that exits the state does also transfer 1 bit. - localparam STATE_exit1_ir = 4'd12; - localparam STATE_pause_ir = 4'd13; - localparam STATE_exit2_ir = 4'd14; - localparam STATE_update_ir = 4'd15; - - reg [3:0] current_state; // Current state of the TAP controller. - - - reg [IR_LENGTH-1:0] jtag_ir; // The instruction register, when in state Capture-IR, gets a device-dependent status value. - reg [IR_LENGTH-1:0] current_instruction; // This is the content of jtag_ir register latched in state Update-IR. - reg [31:0] idcode_reg; - reg bypass_reg; - - - function automatic [3:0] get_next_state; - input reg [3:0] prev_state; - begin - `UNIQUE case ( prev_state ) - STATE_test_logic_reset: - begin - if(jtag_tms_i) get_next_state = STATE_test_logic_reset; - else get_next_state = STATE_run_test_idle; - end - STATE_run_test_idle: - begin - if(jtag_tms_i) get_next_state = STATE_select_dr_scan; - else get_next_state = STATE_run_test_idle; - end - STATE_select_dr_scan: - begin - if(jtag_tms_i) get_next_state = STATE_select_ir_scan; - else get_next_state = STATE_capture_dr; - end - STATE_capture_dr: - begin - if(jtag_tms_i) get_next_state = STATE_exit1_dr; - else get_next_state = STATE_shift_dr; - end - STATE_shift_dr: - begin - if(jtag_tms_i) get_next_state = STATE_exit1_dr; - else get_next_state = STATE_shift_dr; - end - STATE_exit1_dr: - begin - if(jtag_tms_i) get_next_state = STATE_update_dr; - else get_next_state = STATE_pause_dr; - end - STATE_pause_dr: - begin - if(jtag_tms_i) get_next_state = STATE_exit2_dr; - else get_next_state = STATE_pause_dr; - end - STATE_exit2_dr: - begin - if(jtag_tms_i) get_next_state = STATE_update_dr; - else get_next_state = STATE_shift_dr; - end - STATE_update_dr: - begin - if(jtag_tms_i) get_next_state = STATE_select_dr_scan; - else get_next_state = STATE_run_test_idle; - end - STATE_select_ir_scan: - begin - if(jtag_tms_i) get_next_state = STATE_test_logic_reset; - else get_next_state = STATE_capture_ir; - end - STATE_capture_ir: - begin - if(jtag_tms_i) get_next_state = STATE_exit1_ir; - else get_next_state = STATE_shift_ir; - end - STATE_shift_ir: - begin - if(jtag_tms_i) get_next_state = STATE_exit1_ir; - else get_next_state = STATE_shift_ir; - end - STATE_exit1_ir: - begin - if(jtag_tms_i) get_next_state = STATE_update_ir; - else get_next_state = STATE_pause_ir; - end - STATE_pause_ir: - begin - if(jtag_tms_i) get_next_state = STATE_exit2_ir; - else get_next_state = STATE_pause_ir; - end - STATE_exit2_ir: - begin - if(jtag_tms_i) get_next_state = STATE_update_ir; - else get_next_state = STATE_shift_ir; - end - STATE_update_ir: - begin - if(jtag_tms_i) get_next_state = STATE_select_dr_scan; - else get_next_state = STATE_run_test_idle; - end - endcase - end - endfunction - - - function [16*8-1:0] get_state_name; - input [3:0] state; - begin - `UNIQUE case ( state ) - STATE_test_logic_reset: get_state_name = "Test Logic Reset"; - STATE_run_test_idle: get_state_name = "Run-Test / Idle"; - STATE_select_dr_scan: get_state_name = "Select-DR"; - STATE_capture_dr: get_state_name = "Capture-DR"; - STATE_shift_dr: get_state_name = "Shift-DR"; - STATE_exit1_dr: get_state_name = "Exit1-DR"; - STATE_pause_dr: get_state_name = "Pause-DR"; - STATE_exit2_dr: get_state_name = "Exit2-DR"; - STATE_update_dr: get_state_name = "Update-DR"; - STATE_select_ir_scan: get_state_name = "Select-IR"; - STATE_capture_ir: get_state_name = "Capture-IR"; - STATE_shift_ir: get_state_name = "Shift-IR"; - STATE_exit1_ir: get_state_name = "Exit1-IR"; - STATE_pause_ir: get_state_name = "Pause-IR"; - STATE_exit2_ir: get_state_name = "Exit2-IR"; - STATE_update_ir: get_state_name = "Update-IR"; - endcase - end - endfunction - - - function [14*8-1:0] get_instruction_name; - input [IR_LENGTH-1:0] state; - begin - `UNIQUE case ( state ) - `JTAG_INSTRUCTION_EXTEST: get_instruction_name = "EXTEST"; - `JTAG_INSTRUCTION_SAMPLE_PRELOAD: get_instruction_name = "SAMPLE/PRELOAD"; - `JTAG_INSTRUCTION_IDCODE: get_instruction_name = "IDCODE"; - `JTAG_INSTRUCTION_DEBUG: get_instruction_name = "DEBUG"; - `JTAG_INSTRUCTION_MBIST: get_instruction_name = "MBIST"; - `JTAG_INSTRUCTION_BYPASS: get_instruction_name = "BYPASS"; - default: get_instruction_name = ""; - endcase - end - endfunction - - - task automatic reset_initial; - begin - // See the comments in sibling task 'reset_sync' for more information. - current_state = STATE_test_logic_reset; - current_instruction = `JTAG_INSTRUCTION_IDCODE; - jtag_ir = {IR_LENGTH{1'bx}}; - bypass_reg = 1'bx; - idcode_reg = {32{1'bx}}; - debug_reg = {32{1'b0}}; //TH - is_tap_current_instruction_debug_o = 0; - is_tap_state_test_logic_reset_o = 0; - is_tap_state_shift_dr_o = 0; - is_tap_state_update_dr_o = 0; - is_tap_state_capture_dr_o = 0; - end - endtask - - task automatic reset_sync; - begin - // If you change this task, please update sibling task 'reset_initial' too. - - current_state <= STATE_test_logic_reset; - - // As this JTAG TAP does support the IDCODE instruction, that's the one - // selected upon reset. Otherwise, we should select the BYPASS instruction. - current_instruction <= `JTAG_INSTRUCTION_IDCODE; - - // We do not need to initialise the other registers, as the TAP state machine - // always goes through states Capture-IR or Capture-DR, which initialises them - // when they are needed. - jtag_ir <= {IR_LENGTH{1'bx}}; - bypass_reg <= 1'bx; - idcode_reg <= {32{1'bx}}; - debug_reg <= {32{1'b0}}; - - is_tap_current_instruction_debug_o <= 0; - - is_tap_state_test_logic_reset_o <= 0; - is_tap_state_shift_dr_o <= 0; - is_tap_state_update_dr_o <= 0; - is_tap_state_capture_dr_o <= 0; - end - endtask - - - reg [16*8-1:0] initial_state_name; // We need this temporary variable because of a limitation in Verilator. - - initial - begin - // This is so that, in FPGAs, there is no need to trigger the reset signal at the beginning, - // it can then be hard-wired to '1' and optimised away by the synthesiser. - reset_initial; - - if ( TRACE_STATE_MACHINE_TRANSITIONS ) - begin - initial_state_name = get_state_name( current_state ); - $display( "%sStarting up in initial state '%0s'.", TRACE_PREFIX, initial_state_name ); - end - end - - - task do_capture_dr; - reg [14*8-1:0] instruction_name; - begin - instruction_name = get_instruction_name( current_instruction ); - - case ( current_instruction ) - `JTAG_INSTRUCTION_IDCODE: idcode_reg <= `OPENRISC_CPU_JTAG_IDCODE_VALUE; - `JTAG_INSTRUCTION_BYPASS: bypass_reg <= 0; // Must be 0 according to the JTAG specification. - `JTAG_INSTRUCTION_DEBUG: - begin - // Nothing to do here, a submodule will do all the processing for this command. - end - `JTAG_INSTRUCTION_EXTEST, - `JTAG_INSTRUCTION_SAMPLE_PRELOAD, - `JTAG_INSTRUCTION_MBIST: - begin - $display( "%sInstruction %0s is not supported or has not been fully tested yet.", TRACE_PREFIX, instruction_name ); - `FINISH_WITH_ERROR_EXIT_CODE; - end - default: - begin - `ASSERT_FALSE; - // For all unknown JTAG instructions, the standard requires the bypass register. - bypass_reg <= 0; - end - endcase - end - endtask - - - task do_shift_dr; - begin - case ( current_instruction ) - `JTAG_INSTRUCTION_IDCODE: - idcode_reg <= { jtag_tdi_i, idcode_reg[31:1] }; // Note that this overwrites the IDCODE register. It shouldn't really matter. - - `JTAG_INSTRUCTION_BYPASS: - bypass_reg <= jtag_tdi_i; - - `JTAG_INSTRUCTION_DEBUG: - begin - // Nothing to do here, a submodule will do all the processing for this command. - debug_reg <= { jtag_tdi_i, debug_reg[31:1] }; //TH - end - - default: - begin - // Note that task 'do_capture_dr' already catches all default cases. - `ASSERT_FALSE; - // For all unknown JTAG instructions, the standard requires the bypass register. - bypass_reg <= jtag_tdi_i; - end - endcase - end - endtask - - - task automatic tck_posedge; - reg [14*8-1:0] instruction_name; - begin - case ( current_state ) - STATE_test_logic_reset: reset_sync; - - STATE_capture_ir: - jtag_ir <= { 2'b01, // Some fixed status value to help debugging this module, - // we don't actually have any status to report. - - 2'b01 }; // Bits [1:0] must be "01" according to the JTAG specification, - // which helps tell whether a device in the JTAG chain supports the IDCODE instruction - // or not (in which case it would be in BYPASS mode, and its first bit would then be 0). - - STATE_update_ir: - begin - if ( TRACE_STATE_MACHINE_TRANSITIONS ) - begin - instruction_name = get_instruction_name( jtag_ir ); - $display( "%sCurrent instruction set to %0s.", TRACE_PREFIX, instruction_name ); - end - - current_instruction <= jtag_ir; - - is_tap_current_instruction_debug_o <= 0; - - case ( jtag_ir ) - `JTAG_INSTRUCTION_DEBUG: is_tap_current_instruction_debug_o <= 1; - default: - begin - // Nothing to do here. - end - endcase - end - - STATE_shift_ir: - jtag_ir <= { jtag_tdi_i, jtag_ir[IR_LENGTH-1:1] }; - - STATE_capture_dr: - do_capture_dr; - - STATE_shift_dr: - do_shift_dr; - - default: - begin - // Nothing to do here. - end - endcase - end - endtask - - - task automatic switch_to_next_state; - reg [3:0] next_state; - reg [16*8-1:0] prev_state_name; - reg [16*8-1:0] next_state_name; - begin - next_state = get_next_state( current_state ); - - if ( TRACE_JTAG_DATA || TRACE_STATE_MACHINE_TRANSITIONS ) - begin - prev_state_name = get_state_name( current_state ); - - if ( next_state == current_state ) - begin - if ( TRACE_JTAG_DATA ) - $display( "%sTCK posedge, TMS=%0d, TDI=%0d while in state '%0s'.", - TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, prev_state_name ); - end - else - begin - next_state_name = get_state_name( next_state ); - - if ( TRACE_JTAG_DATA ) - $display( "%sTCK posedge, TMS=%0d, TDI=%0d, changing state from '%0s' to '%0s'.", - TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, prev_state_name, next_state_name ); - - if ( TRACE_STATE_MACHINE_TRANSITIONS ) - $display( "%sChanging state from '%0s' to '%0s'.", - TRACE_PREFIX, prev_state_name, next_state_name ); - end - end - - current_state <= next_state; - - is_tap_state_test_logic_reset_o <= 0; - is_tap_state_shift_dr_o <= 0; - is_tap_state_update_dr_o <= 0; - is_tap_state_capture_dr_o <= 0; - - case ( next_state ) - STATE_test_logic_reset: is_tap_state_test_logic_reset_o <= 1; - STATE_shift_dr: is_tap_state_shift_dr_o <= 1; - STATE_update_dr: is_tap_state_update_dr_o <= 1; - STATE_capture_dr: is_tap_state_capture_dr_o <= 1; - default: - begin - // Nothing to do here. - end - endcase - end - endtask - - - task automatic tck_negedge; - reg [16*8-1:0] state_name; - begin - if ( TRACE_JTAG_DATA ) - begin - state_name = get_state_name( current_state ); - $display( "%sTCK negedge, TMS=%0d, TDI=%0d while in state '%0s'.", - TRACE_PREFIX, jtag_tms_i, jtag_tdi_i, state_name ); - end - - // According to the JTAG specification TDO changes state at the negative edge of TCK. - // This is from the documentation about Xilinx BSCAN_SPARTAN6 (which allows access to the FPGA's JTAG TAP): - // TDO input driven from the user fabric logic. This signal is - // internally sampled on the falling edge before being driven out - // to the FPGA TDO pin. - - if ( current_state == STATE_shift_ir ) - jtag_tdo_o <= jtag_ir[0]; - else - begin - case ( current_instruction ) - `JTAG_INSTRUCTION_IDCODE: jtag_tdo_o <= idcode_reg[0]; - `JTAG_INSTRUCTION_DEBUG: jtag_tdo_o <= debug_reg[0]; //debug_tdo_i; TH - `JTAG_INSTRUCTION_SAMPLE_PRELOAD: jtag_tdo_o <= 0; // Boundary scan not supported. - `JTAG_INSTRUCTION_EXTEST: jtag_tdo_o <= 0; // Boundary scan not supported. - `JTAG_INSTRUCTION_MBIST: jtag_tdo_o <= 0; // MBIST not supported. - default: jtag_tdo_o <= bypass_reg; - endcase - end - end - endtask - - - always @( posedge jtag_tck_i or negedge jtag_trstn_i ) - begin - // These 2 conditions must be combined in a single always block, - // otherwise Verilator complains that current_state has 2 drivers, - // as the reset is asynchronous. - - if ( jtag_trstn_i == 0 ) - begin - if ( TRACE_STATE_MACHINE_TRANSITIONS ) - $display( "%sAsync reset signal TRST asserted (the value is now 0).", TRACE_PREFIX ); - - reset_sync; - end - else - begin - tck_posedge; - switch_to_next_state; - end - end - - always @( negedge jtag_tck_i ) - begin - tck_negedge; - end - - always @( posedge jtag_trstn_i ) - begin - if ( TRACE_STATE_MACHINE_TRANSITIONS ) - $display( "%sAsync reset signal TRST deasserted (the value is now 1).", TRACE_PREFIX ); - end - -endmodule diff --git a/tests/test_SimJtagGpio.py b/tests/test_SimJtagGpio.py index 3b54f2ae7..38e97d593 100644 --- a/tests/test_SimJtagGpio.py +++ b/tests/test_SimJtagGpio.py @@ -159,10 +159,11 @@ class TestSimJtagGpio(unittest.TestCase): def setUp(self): + test_dir = os.path.dirname(__file__) cocotb_compile_and_run( [ - os.path.join(os.path.dirname(__file__), "jtag_tap.v"), - os.path.join(os.path.dirname(__file__), "test_SimJtagGpio.v"), + os.path.join(test_dir, "../basil/firmware/modules/includes/jtag_tap.v"), + os.path.join(test_dir, "test_SimJtagGpio.v"), ] ) diff --git a/tests/test_SimJtagMaster.py b/tests/test_SimJtagMaster.py index ae7773e42..1f67d77e5 100644 --- a/tests/test_SimJtagMaster.py +++ b/tests/test_SimJtagMaster.py @@ -164,10 +164,11 @@ class TestSimJtagMaster(unittest.TestCase): def setUp(self): + test_dir = os.path.dirname(__file__) cocotb_compile_and_run( [ - os.path.join(os.path.dirname(__file__), "jtag_tap.v"), - os.path.join(os.path.dirname(__file__), "test_SimJtagMaster.v"), + os.path.join(test_dir, "../basil/firmware/modules/includes/jtag_tap.v"), + os.path.join(test_dir, "test_SimJtagMaster.v"), ] ) From 573bb7dcf94f2dc4359f0dec443b1423e7296b82 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Sat, 23 May 2026 01:40:15 +0200 Subject: [PATCH 39/43] fix: satisfy stricter Verilator SPI warnings Verilator treats warnings as fatal where Icarus accepts the code. Size the fast SPI concatenation explicitly and elaborate only the writable RAM ports used by each SPI memory instance. --- .../modules/fast_spi_rx/fast_spi_rx_core.v | 2 +- .../modules/spi/blk_mem_gen_8_to_1_2k.v | 45 ++++++++++++++----- basil/firmware/modules/spi/spi_core.v | 10 ++++- 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index 32369d865..e2a34447d 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -133,7 +133,7 @@ always @(posedge SCLK) begin if(RST_SYNC | SEN_FINISH) spi_data <= 0; else if(cdc_fifo_write) - spi_data <= {DATA_SIZE-1'b0, SDI}; + spi_data <= {{(DATA_SIZE-1){1'b0}}, SDI}; else if(SEN) spi_data <= {spi_data[DATA_SIZE-2:0], SDI}; end diff --git a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v index 386eb13ef..5453f2468 100644 --- a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v +++ b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v @@ -32,7 +32,12 @@ `default_nettype none -module blk_mem_gen_8_to_1_2k ( +module blk_mem_gen_8_to_1_2k #( + // Disable a port's write logic when its write enable is tied low. + // This avoids elaborating unused cross-clock RAM write paths. + parameter PORT_A_WRITABLE = 1, + parameter PORT_B_WRITABLE = 1 +) ( CLKA, CLKB, DOUTA, DOUTB, WEA, WEB, ADDRA, ADDRB, DINA, DINB ); @@ -65,22 +70,38 @@ reg [0:0] ram [0:16383]; // ------------------------------ integer i; -always @(posedge CLKA) begin - for (i = 0; i < 8; i = i + 1) begin - DOUTA[i] <= ram[{ADDRA, i[2:0]}]; - if (WEA) - ram[{ADDRA, i[2:0]}] <= DINA[i]; +generate + if (PORT_A_WRITABLE) begin : port_a_read_write + always @(posedge CLKA) begin + for (i = 0; i < 8; i = i + 1) begin + DOUTA[i] <= ram[{ADDRA, i[2:0]}]; + if (WEA) + ram[{ADDRA, i[2:0]}] <= DINA[i]; + end + end + end else begin : port_a_read_only + always @(posedge CLKA) begin + for (i = 0; i < 8; i = i + 1) + DOUTA[i] <= ram[{ADDRA, i[2:0]}]; + end end -end +endgenerate // ------------------------------ // Port B — 1-bit synchronous (simple, one port) // ------------------------------ -always @(posedge CLKB) begin - DOUTB <= ram[ADDRB]; - if (WEB) - ram[ADDRB] <= DINB[0]; -end +generate + if (PORT_B_WRITABLE) begin : port_b_read_write + always @(posedge CLKB) begin + DOUTB <= ram[ADDRB]; + if (WEB) + ram[ADDRB] <= DINB[0]; + end + end else begin : port_b_read_only + always @(posedge CLKB) + DOUTB <= ram[ADDRB]; + end +endgenerate endmodule diff --git a/basil/firmware/modules/spi/spi_core.v b/basil/firmware/modules/spi/spi_core.v index ff68f68b2..849116cf0 100644 --- a/basil/firmware/modules/spi/spi_core.v +++ b/basil/firmware/modules/spi/spi_core.v @@ -157,7 +157,10 @@ end wire SDI_MEM; -blk_mem_gen_8_to_1_2k memout( +blk_mem_gen_8_to_1_2k #( + .PORT_A_WRITABLE(1), + .PORT_B_WRITABLE(0) +) memout( .CLKA(BUS_CLK), .CLKB(SPI_CLK), .DOUTA(BUS_IN_MEM_IB), @@ -177,7 +180,10 @@ wire [13:0] ADDRB_MIN; assign ADDRB_MIN = out_bit_cnt-1; reg SEN_INT; -blk_mem_gen_8_to_1_2k memin( +blk_mem_gen_8_to_1_2k #( + .PORT_A_WRITABLE(0), + .PORT_B_WRITABLE(1) +) memin( .CLKA(BUS_CLK), .CLKB(SPI_CLK), .DOUTA(BUS_OUT_MEM_IB), From b1e0a3ed0cc18ea5d3bfa2065766627600f5e35a Mon Sep 17 00:00:00 2001 From: kcaisley Date: Tue, 26 May 2026 11:11:41 +0200 Subject: [PATCH 40/43] style(spi): format spi core --- basil/firmware/modules/spi/spi_core.v | 471 +++++++++++++------------- 1 file changed, 233 insertions(+), 238 deletions(-) diff --git a/basil/firmware/modules/spi/spi_core.v b/basil/firmware/modules/spi/spi_core.v index 849116cf0..45b590260 100644 --- a/basil/firmware/modules/spi/spi_core.v +++ b/basil/firmware/modules/spi/spi_core.v @@ -11,7 +11,7 @@ `include "utils/cdc_pulse_sync.v" `include "utils/CG_MOD_pos.v" -`timescale 1ps/1ps +`timescale 1ps / 1ps `default_nettype none @@ -19,270 +19,265 @@ module spi_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16 ) ( - input wire BUS_CLK, - input wire BUS_RST, - input wire [ABUSWIDTH-1:0] BUS_ADD, + input wire BUS_CLK, + input wire BUS_RST, + input wire [ABUSWIDTH-1:0] BUS_ADD, /* verilator lint_off UNOPTFLAT */ // Clocked and safe in synthesis, else circular logic data_in -> memory -> data_out - input wire [7:0] BUS_DATA_IN, + input wire [ 7:0] BUS_DATA_IN, /* verilator lint_on UNOPTFLAT */ - input wire BUS_RD, - input wire BUS_WR, - output reg [7:0] BUS_DATA_OUT, + input wire BUS_RD, + input wire BUS_WR, + output reg [ 7:0] BUS_DATA_OUT, input wire SPI_CLK, output wire SCLK, - input wire SDO, - output reg SDI, - input wire EXT_START, + input wire SDO, + output reg SDI, + input wire EXT_START, output reg SEN, output reg SLD ); -localparam VERSION = 2; - -reg [7:0] status_regs [15:0]; - -wire RST; -wire SOFT_RST; - -assign RST = BUS_RST || SOFT_RST; - -localparam DEF_BIT_OUT = 8*MEM_BYTES; - -always @(posedge BUS_CLK) begin - if(RST) begin - status_regs[0] <= 0; - status_regs[1] <= 0; - status_regs[2] <= 0; - status_regs[3] <= DEF_BIT_OUT[7:0]; //bits - status_regs[4] <= DEF_BIT_OUT[15:8]; //bits - status_regs[5] <= 4; //wait - status_regs[6] <= 0; //wait - status_regs[7] <= 0; //wait - status_regs[8] <= 0; //wait - status_regs[9] <= 1; //repeat - status_regs[10] <= 0; //repeat - status_regs[11] <= 0; //repeat - status_regs[12] <= 0; //repeat - status_regs[13] <= 0; //0:enable external start + localparam VERSION = 2; + + reg [7:0] status_regs[15:0]; + + wire RST; + wire SOFT_RST; + + assign RST = BUS_RST || SOFT_RST; + + localparam DEF_BIT_OUT = 8 * MEM_BYTES; + + always @(posedge BUS_CLK) begin + if (RST) begin + status_regs[0] <= 0; + status_regs[1] <= 0; + status_regs[2] <= 0; + status_regs[3] <= DEF_BIT_OUT[7:0]; //bits + status_regs[4] <= DEF_BIT_OUT[15:8]; //bits + status_regs[5] <= 4; //wait + status_regs[6] <= 0; //wait + status_regs[7] <= 0; //wait + status_regs[8] <= 0; //wait + status_regs[9] <= 1; //repeat + status_regs[10] <= 0; //repeat + status_regs[11] <= 0; //repeat + status_regs[12] <= 0; //repeat + status_regs[13] <= 0; //0:enable external start + end else if (BUS_WR && BUS_ADD < 16) status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; + end + + reg [7:0] BUS_IN_MEM; + reg [7:0] BUS_OUT_MEM; + + wire START; + assign SOFT_RST = (BUS_ADD == 0 && BUS_WR); + assign START = (BUS_ADD == 1 && BUS_WR); + + wire [15:0] CONF_BIT_OUT; + assign CONF_BIT_OUT = {status_regs[4], status_regs[3]}; + + // TODO: not yet used + wire [7:0] CONF_CLK_DIV; + assign CONF_CLK_DIV = status_regs[2]; + reg CONF_DONE; + + wire [31:0] CONF_WAIT; + assign CONF_WAIT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]}; + + wire [31:0] CONF_REPEAT; + assign CONF_REPEAT = {status_regs[12], status_regs[11], status_regs[10], status_regs[9]}; + + wire CONF_EN; + assign CONF_EN = status_regs[13][0]; + + reg [7:0] BUS_DATA_OUT_REG; + always @(posedge BUS_CLK) begin + if (BUS_RD) begin + if (BUS_ADD == 0) BUS_DATA_OUT_REG <= VERSION; + else if (BUS_ADD == 1) BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; + else if (BUS_ADD == 13) BUS_DATA_OUT_REG <= {7'b0, CONF_EN}; + else if (BUS_ADD == 14) BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; + else if (BUS_ADD == 15) BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; + else if (BUS_ADD < 16) BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]]; end - else if(BUS_WR && BUS_ADD < 16) - status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; -end - -reg [7:0] BUS_IN_MEM; -reg [7:0] BUS_OUT_MEM; - -wire START; -assign SOFT_RST = (BUS_ADD==0 && BUS_WR); -assign START = (BUS_ADD==1 && BUS_WR); - -wire [15:0] CONF_BIT_OUT; -assign CONF_BIT_OUT = {status_regs[4],status_regs[3]}; - -// TODO: not yet used -wire [7:0] CONF_CLK_DIV; -assign CONF_CLK_DIV = status_regs[2]; -reg CONF_DONE; - -wire [31:0] CONF_WAIT; -assign CONF_WAIT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]}; - -wire [31:0] CONF_REPEAT; -assign CONF_REPEAT = {status_regs[12], status_regs[11], status_regs[10], status_regs[9]}; - -wire CONF_EN; -assign CONF_EN = status_regs[13][0]; - -reg [7:0] BUS_DATA_OUT_REG; -always @(posedge BUS_CLK) begin - if(BUS_RD) begin - if(BUS_ADD == 0) - BUS_DATA_OUT_REG <= VERSION; - else if(BUS_ADD == 1) - BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; - else if(BUS_ADD == 13) - BUS_DATA_OUT_REG <= {7'b0, CONF_EN}; - else if(BUS_ADD == 14) - BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; - else if(BUS_ADD == 15) - BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; - else if (BUS_ADD < 16) - BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]]; + end + + // if one has a synchronous memory need this to give data on next clock after read + // limitation: this module still needs to be addressed + reg [ABUSWIDTH-1:0] PREV_BUS_ADD; + always @(posedge BUS_CLK) begin + if (BUS_RD) begin + PREV_BUS_ADD <= BUS_ADD; end -end - -// if one has a synchronous memory need this to give data on next clock after read -// limitation: this module still needs to be addressed -reg [ABUSWIDTH-1:0] PREV_BUS_ADD; -always @(posedge BUS_CLK) begin - if(BUS_RD) begin - PREV_BUS_ADD <= BUS_ADD; + end + + always @(*) begin + if (PREV_BUS_ADD < 16) BUS_DATA_OUT = BUS_DATA_OUT_REG; + else if (PREV_BUS_ADD < 16 + MEM_BYTES) BUS_DATA_OUT = BUS_IN_MEM; + else if (PREV_BUS_ADD < 16 + MEM_BYTES + MEM_BYTES) BUS_DATA_OUT = BUS_OUT_MEM; + else BUS_DATA_OUT = 8'hxx; + end + + reg [32:0] out_bit_cnt; + + + wire [13:0] memout_addrb; + assign memout_addrb = out_bit_cnt; + wire [10:0] memout_addra; + assign memout_addra = (BUS_ADD - 16); + + reg [7:0] BUS_DATA_IN_IB; + wire [7:0] BUS_IN_MEM_IB; + wire [7:0] BUS_OUT_MEM_IB; + integer i; + always @(*) begin + for (i = 0; i < 8; i = i + 1) begin + BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i]; + BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i]; + BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i]; end -end - -always @(*) begin - if(PREV_BUS_ADD < 16) - BUS_DATA_OUT = BUS_DATA_OUT_REG; - else if(PREV_BUS_ADD < 16+MEM_BYTES) - BUS_DATA_OUT = BUS_IN_MEM; - else if(PREV_BUS_ADD < 16+MEM_BYTES+MEM_BYTES) - BUS_DATA_OUT = BUS_OUT_MEM; - else - BUS_DATA_OUT = 8'hxx; -end - -reg [32:0] out_bit_cnt; - - -wire [13:0] memout_addrb; -assign memout_addrb = out_bit_cnt; -wire [10:0] memout_addra; -assign memout_addra = (BUS_ADD-16); - -reg [7:0] BUS_DATA_IN_IB; -wire [7:0] BUS_IN_MEM_IB; -wire [7:0] BUS_OUT_MEM_IB; -integer i; -always @(*) begin - for(i=0;i<8;i=i+1) begin - BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i]; - BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i]; - BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i]; - end -end - -wire SDI_MEM; - -blk_mem_gen_8_to_1_2k #( - .PORT_A_WRITABLE(1), - .PORT_B_WRITABLE(0) -) memout( - .CLKA(BUS_CLK), - .CLKB(SPI_CLK), - .DOUTA(BUS_IN_MEM_IB), - .DOUTB(SDI_MEM), - .WEA(BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES), - .WEB(1'b0), - .ADDRA(memout_addra), - .ADDRB(memout_addrb), - .DINA(BUS_DATA_IN_IB), - .DINB(1'b0) -); - - -wire [10:0] ADDRA_MIN; -assign ADDRA_MIN = (BUS_ADD-16-MEM_BYTES); -wire [13:0] ADDRB_MIN; -assign ADDRB_MIN = out_bit_cnt-1; -reg SEN_INT; - -blk_mem_gen_8_to_1_2k #( - .PORT_A_WRITABLE(0), - .PORT_B_WRITABLE(1) -) memin( - .CLKA(BUS_CLK), - .CLKB(SPI_CLK), - .DOUTA(BUS_OUT_MEM_IB), - .DOUTB(), - .WEA(1'b0), - .WEB(SEN_INT), - .ADDRA(ADDRA_MIN), - .ADDRB(ADDRB_MIN), - .DINA(BUS_DATA_IN_IB), - .DINB(SDO) -); - -wire RST_SYNC; -wire RST_SOFT_SYNC; -cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SPI_CLK), .pulse_out(RST_SOFT_SYNC)); -assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; - -wire START_SYNC; -cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SPI_CLK), .pulse_out(START_SYNC)); - -wire EXT_START_PULSE; -reg [2:0] EXT_START_FF; -always @(posedge SPI_CLK) // first stage + end + + wire SDI_MEM; + + blk_mem_gen_8_to_1_2k #( + .PORT_A_WRITABLE(1), + .PORT_B_WRITABLE(0) + ) memout ( + .CLKA (BUS_CLK), + .CLKB (SPI_CLK), + .DOUTA(BUS_IN_MEM_IB), + .DOUTB(SDI_MEM), + .WEA (BUS_WR && BUS_ADD >= 16 && BUS_ADD < 16 + MEM_BYTES), + .WEB (1'b0), + .ADDRA(memout_addra), + .ADDRB(memout_addrb), + .DINA (BUS_DATA_IN_IB), + .DINB (1'b0) + ); + + + wire [10:0] ADDRA_MIN; + assign ADDRA_MIN = (BUS_ADD - 16 - MEM_BYTES); + wire [13:0] ADDRB_MIN; + assign ADDRB_MIN = out_bit_cnt - 1; + reg SEN_INT; + + blk_mem_gen_8_to_1_2k #( + .PORT_A_WRITABLE(0), + .PORT_B_WRITABLE(1) + ) memin ( + .CLKA (BUS_CLK), + .CLKB (SPI_CLK), + .DOUTA(BUS_OUT_MEM_IB), + .DOUTB(), + .WEA (1'b0), + .WEB (SEN_INT), + .ADDRA(ADDRA_MIN), + .ADDRB(ADDRB_MIN), + .DINA (BUS_DATA_IN_IB), + .DINB (SDO) + ); + + wire RST_SYNC; + wire RST_SOFT_SYNC; + cdc_pulse_sync rst_pulse_sync ( + .clk_in(BUS_CLK), + .pulse_in(RST), + .clk_out(SPI_CLK), + .pulse_out(RST_SOFT_SYNC) + ); + assign RST_SYNC = RST_SOFT_SYNC || BUS_RST; + + wire START_SYNC; + cdc_pulse_sync start_pulse_sync ( + .clk_in(BUS_CLK), + .pulse_in(START), + .clk_out(SPI_CLK), + .pulse_out(START_SYNC) + ); + + wire EXT_START_PULSE; + reg [2:0] EXT_START_FF; + always @(posedge SPI_CLK) // first stage begin EXT_START_FF[0] <= EXT_START; EXT_START_FF[1] <= EXT_START_FF[0]; EXT_START_FF[2] <= EXT_START_FF[1]; -end -assign EXT_START_PULSE = !EXT_START_FF[2] & EXT_START_FF[1]; - -wire [32:0] STOP_BIT; -assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT; -reg [31:0] REPEAT_COUNT; - -wire REP_START; -assign REP_START = (out_bit_cnt == STOP_BIT && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT)); - -reg REP_START_DLY; -always @(posedge SPI_CLK) - REP_START_DLY <= REP_START; - -always @(posedge SPI_CLK) - if (RST_SYNC) - SEN_INT <= 0; - else if(START_SYNC || (EXT_START_PULSE && CONF_EN) || REP_START_DLY) - SEN_INT <= 1; - else if(out_bit_cnt == CONF_BIT_OUT) - SEN_INT <= 0; - -always @(posedge SPI_CLK) - if (RST_SYNC) - out_bit_cnt <= 0; - else if(START_SYNC || (EXT_START_PULSE && CONF_EN)) - out_bit_cnt <= 1; - else if(out_bit_cnt == STOP_BIT) - out_bit_cnt <= 0; - //else if(out_bit_cnt == CONF_BIT_OUT & REPEAT_COUNT == CONF_REPEAT & CONF_REPEAT!=0) - // out_bit_cnt <= 0; - else if(REP_START_DLY) - out_bit_cnt <= 1; - else if(out_bit_cnt != 0) - out_bit_cnt <= out_bit_cnt + 1; - -always @(posedge SPI_CLK) - if (RST_SYNC || START_SYNC || (EXT_START_PULSE && CONF_EN)) - REPEAT_COUNT <= 1; - else if(out_bit_cnt == STOP_BIT) - REPEAT_COUNT <= REPEAT_COUNT + 1; + end + assign EXT_START_PULSE = !EXT_START_FF[2] & EXT_START_FF[1]; + wire [32:0] STOP_BIT; + assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT; + reg [31:0] REPEAT_COUNT; -reg [1:0] sync_ld; -always @(posedge SPI_CLK) begin - sync_ld[0] <= SEN_INT; - sync_ld[1] <= sync_ld[0]; -end + wire REP_START; + assign REP_START = (out_bit_cnt == STOP_BIT && (CONF_REPEAT == 0 || REPEAT_COUNT < CONF_REPEAT)); -always @(posedge SPI_CLK) - SLD <= (sync_ld[1]==1 && sync_ld[0]==0); + reg REP_START_DLY; + always @(posedge SPI_CLK) REP_START_DLY <= REP_START; -wire DONE = out_bit_cnt == STOP_BIT && REPEAT_COUNT >= CONF_REPEAT; -wire DONE_SYNC, EXT_START_PULSE_SYNC; -cdc_pulse_sync done_pulse_sync (.clk_in(SPI_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC)); -cdc_pulse_sync done_pulse_ext_start (.clk_in(SPI_CLK), .pulse_in(EXT_START_PULSE), .clk_out(BUS_CLK), .pulse_out(EXT_START_PULSE_SYNC)); + always @(posedge SPI_CLK) + if (RST_SYNC) SEN_INT <= 0; + else if (START_SYNC || (EXT_START_PULSE && CONF_EN) || REP_START_DLY) SEN_INT <= 1; + else if (out_bit_cnt == CONF_BIT_OUT) SEN_INT <= 0; -always @(posedge BUS_CLK) - if(RST) - CONF_DONE <= 1; - else if(START || (EXT_START_PULSE_SYNC && CONF_EN)) - CONF_DONE <= 0; - else if(DONE_SYNC) - CONF_DONE <= 1; + always @(posedge SPI_CLK) + if (RST_SYNC) out_bit_cnt <= 0; + else if (START_SYNC || (EXT_START_PULSE && CONF_EN)) out_bit_cnt <= 1; + else if (out_bit_cnt == STOP_BIT) out_bit_cnt <= 0; + //else if(out_bit_cnt == CONF_BIT_OUT & REPEAT_COUNT == CONF_REPEAT & CONF_REPEAT!=0) + // out_bit_cnt <= 0; + else if (REP_START_DLY) out_bit_cnt <= 1; + else if (out_bit_cnt != 0) out_bit_cnt <= out_bit_cnt + 1; -CG_MOD_pos icg2(.ck_in(SPI_CLK), .enable(SEN), .ck_out(SCLK)); + always @(posedge SPI_CLK) + if (RST_SYNC || START_SYNC || (EXT_START_PULSE && CONF_EN)) REPEAT_COUNT <= 1; + else if (out_bit_cnt == STOP_BIT) REPEAT_COUNT <= REPEAT_COUNT + 1; -always @(negedge SPI_CLK) - SDI <= SDI_MEM & SEN_INT; -always @(negedge SPI_CLK) - SEN <= SEN_INT; + reg [1:0] sync_ld; + always @(posedge SPI_CLK) begin + sync_ld[0] <= SEN_INT; + sync_ld[1] <= sync_ld[0]; + end + + always @(posedge SPI_CLK) SLD <= (sync_ld[1] == 1 && sync_ld[0] == 0); + + wire DONE = out_bit_cnt == STOP_BIT && REPEAT_COUNT >= CONF_REPEAT; + wire DONE_SYNC, EXT_START_PULSE_SYNC; + cdc_pulse_sync done_pulse_sync ( + .clk_in(SPI_CLK), + .pulse_in(DONE), + .clk_out(BUS_CLK), + .pulse_out(DONE_SYNC) + ); + cdc_pulse_sync done_pulse_ext_start ( + .clk_in(SPI_CLK), + .pulse_in(EXT_START_PULSE), + .clk_out(BUS_CLK), + .pulse_out(EXT_START_PULSE_SYNC) + ); + + always @(posedge BUS_CLK) + if (RST) CONF_DONE <= 1; + else if (START || (EXT_START_PULSE_SYNC && CONF_EN)) CONF_DONE <= 0; + else if (DONE_SYNC) CONF_DONE <= 1; + + CG_MOD_pos icg2 ( + .ck_in (SPI_CLK), + .enable(SEN), + .ck_out(SCLK) + ); + + always @(negedge SPI_CLK) SDI <= SDI_MEM & SEN_INT; + + always @(negedge SPI_CLK) SEN <= SEN_INT; endmodule From a9a4475341f6864848d76f852509b56b8625f320 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 27 May 2026 13:46:43 +0200 Subject: [PATCH 41/43] fix(firmwave): Simplify include guard to naming scheme --- basil/firmware/modules/bram_fifo/bram_fifo.v | 4 ++-- basil/firmware/modules/bram_fifo/bram_fifo_core.v | 4 ++-- basil/firmware/modules/cmd_seq/cmd_seq.v | 4 ++-- basil/firmware/modules/cmd_seq/cmd_seq_core.v | 4 ++-- basil/firmware/modules/fast_spi_rx/fast_spi_rx.v | 4 ++-- basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v | 4 ++-- basil/firmware/modules/fei4_rx/decode_8b10b.v | 4 ++-- basil/firmware/modules/fei4_rx/fei4_rx.v | 4 ++-- basil/firmware/modules/fei4_rx/fei4_rx_core.v | 4 ++-- basil/firmware/modules/fei4_rx/rec_sync.v | 4 ++-- basil/firmware/modules/fei4_rx/receiver_logic.v | 4 ++-- basil/firmware/modules/fei4_rx/sync_master.v | 4 ++-- basil/firmware/modules/fx3_if/FX3_IF.v | 4 ++-- basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v | 4 ++-- basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v | 4 ++-- basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v | 4 ++-- basil/firmware/modules/gpio/gpio.v | 4 ++-- basil/firmware/modules/gpio/gpio_core.v | 4 ++-- basil/firmware/modules/gpio/gpio_sbus.v | 4 ++-- basil/firmware/modules/i2c/i2c.v | 4 ++-- basil/firmware/modules/i2c/i2c_core.v | 4 ++-- basil/firmware/modules/includes/jtag_tap.v | 4 ++-- basil/firmware/modules/jtag_master/jtag_master.v | 4 ++-- basil/firmware/modules/jtag_master/jtag_master_core.v | 4 ++-- basil/firmware/modules/m26_rx/m26_rx.v | 4 ++-- basil/firmware/modules/m26_rx/m26_rx_ch.v | 4 ++-- basil/firmware/modules/m26_rx/m26_rx_core.v | 4 ++-- basil/firmware/modules/pulse_gen/pulse_gen.v | 4 ++-- basil/firmware/modules/pulse_gen/pulse_gen_core.v | 4 ++-- basil/firmware/modules/rrp_arbiter/rrp_arbiter.v | 4 ++-- basil/firmware/modules/seq_gen/seq_gen.v | 4 ++-- basil/firmware/modules/seq_gen/seq_gen_core.v | 4 ++-- basil/firmware/modules/seq_rec/seq_rec.v | 4 ++-- basil/firmware/modules/seq_rec/seq_rec_core.v | 4 ++-- basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v | 4 ++-- basil/firmware/modules/spi/spi.v | 4 ++-- basil/firmware/modules/spi/spi_core.v | 4 ++-- basil/firmware/modules/sram_fifo/sram_fifo.v | 4 ++-- basil/firmware/modules/sram_fifo/sram_fifo_core.v | 4 ++-- basil/firmware/modules/tb/silbusb.v | 4 ++-- basil/firmware/modules/tb/uartlib.v | 4 ++-- basil/firmware/modules/tdc_s3/tdc_s3.v | 4 ++-- basil/firmware/modules/tdc_s3/tdc_s3_core.v | 4 ++-- basil/firmware/modules/tdl_tdc/controller.v | 4 ++-- .../modules/tdl_tdc/counter/slimfast_multioption_counter.v | 4 ++-- .../modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v | 4 ++-- basil/firmware/modules/tdl_tdc/delayline/sample_deser.v | 4 ++-- basil/firmware/modules/tdl_tdc/priority_encoder.v | 4 ++-- basil/firmware/modules/tdl_tdc/sw_interface.v | 4 ++-- basil/firmware/modules/tdl_tdc/tdl_supersampler.v | 4 ++-- basil/firmware/modules/tdl_tdc/tdl_tdc.v | 4 ++-- basil/firmware/modules/tdl_tdc/tdl_tdc_core.v | 4 ++-- basil/firmware/modules/tdl_tdc/utils/delay_n.v | 4 ++-- basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v | 4 ++-- basil/firmware/modules/tdl_tdc/word_broker.v | 4 ++-- basil/firmware/modules/timestamp/timestamp.v | 4 ++-- basil/firmware/modules/timestamp/timestamp_core.v | 4 ++-- basil/firmware/modules/tlu/tlu_controller.v | 4 ++-- basil/firmware/modules/tlu/tlu_controller_core.v | 4 ++-- basil/firmware/modules/tlu/tlu_controller_fsm.v | 4 ++-- basil/firmware/modules/uart/uart.v | 4 ++-- basil/firmware/modules/uart/uart_master.v | 4 ++-- basil/firmware/modules/utils/3_stage_synchronizer.v | 4 ++-- basil/firmware/modules/utils/BUFG.v | 4 ++-- basil/firmware/modules/utils/CG_MOD_neg.v | 4 ++-- basil/firmware/modules/utils/CG_MOD_pos.v | 4 ++-- basil/firmware/modules/utils/DCM.v | 4 ++-- basil/firmware/modules/utils/IBUF.v | 4 ++-- basil/firmware/modules/utils/IBUFDS.v | 4 ++-- basil/firmware/modules/utils/IBUFG.v | 4 ++-- basil/firmware/modules/utils/IBUFGDS.v | 4 ++-- basil/firmware/modules/utils/IDDR.v | 4 ++-- basil/firmware/modules/utils/IDDR_s3.v | 4 ++-- basil/firmware/modules/utils/IDDR_s3_noibuf.v | 4 ++-- basil/firmware/modules/utils/IDDR_s6.v | 4 ++-- basil/firmware/modules/utils/IOBUF.v | 4 ++-- basil/firmware/modules/utils/OBUF.v | 4 ++-- basil/firmware/modules/utils/OBUFDS.v | 4 ++-- basil/firmware/modules/utils/ODDR.v | 4 ++-- basil/firmware/modules/utils/ODDR_s3.v | 4 ++-- basil/firmware/modules/utils/ODDR_s6.v | 4 ++-- basil/firmware/modules/utils/PLLE2_BASE.v | 4 ++-- basil/firmware/modules/utils/RAMB16_S1_S2.v | 4 ++-- basil/firmware/modules/utils/RAMB16_S1_S9.v | 4 ++-- basil/firmware/modules/utils/bus_to_ip.v | 4 ++-- basil/firmware/modules/utils/cdc_pulse_sync.v | 4 ++-- basil/firmware/modules/utils/cdc_pulse_sync_cnt.v | 4 ++-- basil/firmware/modules/utils/cdc_reset_sync.v | 4 ++-- basil/firmware/modules/utils/cdc_syncfifo.v | 4 ++-- basil/firmware/modules/utils/clock_divider.v | 4 ++-- basil/firmware/modules/utils/clock_multiplier.v | 4 ++-- basil/firmware/modules/utils/ddr_des.v | 4 ++-- basil/firmware/modules/utils/fifo_32_to_8.v | 4 ++-- basil/firmware/modules/utils/fifo_64_to_16.v | 4 ++-- basil/firmware/modules/utils/fifo_8_to_32.v | 4 ++-- basil/firmware/modules/utils/fifo_8_to_64.v | 4 ++-- basil/firmware/modules/utils/flag_domain_crossing.v | 4 ++-- basil/firmware/modules/utils/fx2_to_bus.v | 4 ++-- basil/firmware/modules/utils/generic_fifo.v | 4 ++-- basil/firmware/modules/utils/pulse_gen_rising.v | 4 ++-- basil/firmware/modules/utils/ramb_8_to_n.v | 4 ++-- basil/firmware/modules/utils/rbcp_to_bus.v | 4 ++-- basil/firmware/modules/utils/reset_gen.v | 4 ++-- basil/firmware/modules/utils/rgmii_io.v | 4 ++-- basil/firmware/modules/utils/sbus_to_ip.v | 4 ++-- basil/firmware/modules/utils/simple_arbiter.v | 4 ++-- basil/firmware/modules/utils/tcp_to_bus.v | 4 ++-- 107 files changed, 214 insertions(+), 214 deletions(-) diff --git a/basil/firmware/modules/bram_fifo/bram_fifo.v b/basil/firmware/modules/bram_fifo/bram_fifo.v index 4766b14f0..8eec9d4c1 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_BRAM_FIFO_BRAM_FIFO_V -`define BASIL_BRAM_FIFO_BRAM_FIFO_V +`ifndef BRAM_FIFO +`define BRAM_FIFO `include "bram_fifo/bram_fifo_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/bram_fifo/bram_fifo_core.v b/basil/firmware/modules/bram_fifo/bram_fifo_core.v index a9caefece..bc7a0eda4 100644 --- a/basil/firmware/modules/bram_fifo/bram_fifo_core.v +++ b/basil/firmware/modules/bram_fifo/bram_fifo_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_BRAM_FIFO_BRAM_FIFO_CORE_V -`define BASIL_BRAM_FIFO_BRAM_FIFO_CORE_V +`ifndef BRAM_FIFO_CORE +`define BRAM_FIFO_CORE `include "utils/generic_fifo.v" diff --git a/basil/firmware/modules/cmd_seq/cmd_seq.v b/basil/firmware/modules/cmd_seq/cmd_seq.v index dca07d687..1836d499d 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_CMD_SEQ_CMD_SEQ_V -`define BASIL_CMD_SEQ_CMD_SEQ_V +`ifndef CMD_SEQ +`define CMD_SEQ `include "cmd_seq/cmd_seq_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/cmd_seq/cmd_seq_core.v b/basil/firmware/modules/cmd_seq/cmd_seq_core.v index 1900c08b0..6d0992015 100644 --- a/basil/firmware/modules/cmd_seq/cmd_seq_core.v +++ b/basil/firmware/modules/cmd_seq/cmd_seq_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_CMD_SEQ_CMD_SEQ_CORE_V -`define BASIL_CMD_SEQ_CMD_SEQ_CORE_V +`ifndef CMD_SEQ_CORE +`define CMD_SEQ_CORE `include "utils/flag_domain_crossing.v" `include "utils/3_stage_synchronizer.v" diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v index 7025c2bdf..7faf65a5c 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v @@ -5,8 +5,8 @@ * ------------------------------------------------------------ */ -`ifndef BASIL_FAST_SPI_RX_FAST_SPI_RX_V -`define BASIL_FAST_SPI_RX_FAST_SPI_RX_V +`ifndef FAST_SPI_RX +`define FAST_SPI_RX `include "fast_spi_rx/fast_spi_rx_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v index e2a34447d..ebe0f9ae8 100644 --- a/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v +++ b/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FAST_SPI_RX_FAST_SPI_RX_CORE_V -`define BASIL_FAST_SPI_RX_FAST_SPI_RX_CORE_V +`ifndef FAST_SPI_RX_CORE +`define FAST_SPI_RX_CORE `include "utils/cdc_pulse_sync.v" `include "utils/cdc_syncfifo.v" diff --git a/basil/firmware/modules/fei4_rx/decode_8b10b.v b/basil/firmware/modules/fei4_rx/decode_8b10b.v index 797288794..0c33c0892 100644 --- a/basil/firmware/modules/fei4_rx/decode_8b10b.v +++ b/basil/firmware/modules/fei4_rx/decode_8b10b.v @@ -15,8 +15,8 @@ * notice is preserved. * per Widmer and Franaszek */ -`ifndef BASIL_FEI4_RX_DECODE_8B10B_V -`define BASIL_FEI4_RX_DECODE_8B10B_V +`ifndef DECODE_8B10B +`define DECODE_8B10B `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fei4_rx/fei4_rx.v b/basil/firmware/modules/fei4_rx/fei4_rx.v index dfb67d839..8504e5b7a 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FEI4_RX_FEI4_RX_V -`define BASIL_FEI4_RX_FEI4_RX_V +`ifndef FEI4_RX +`define FEI4_RX `include "fei4_rx/fei4_rx_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/fei4_rx/fei4_rx_core.v b/basil/firmware/modules/fei4_rx/fei4_rx_core.v index 50721024f..02b4d897f 100644 --- a/basil/firmware/modules/fei4_rx/fei4_rx_core.v +++ b/basil/firmware/modules/fei4_rx/fei4_rx_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FEI4_RX_FEI4_RX_CORE_V -`define BASIL_FEI4_RX_FEI4_RX_CORE_V +`ifndef FEI4_RX_CORE +`define FEI4_RX_CORE `include "utils/3_stage_synchronizer.v" `include "fei4_rx/receiver_logic.v" diff --git a/basil/firmware/modules/fei4_rx/rec_sync.v b/basil/firmware/modules/fei4_rx/rec_sync.v index d437c4195..cbd674415 100644 --- a/basil/firmware/modules/fei4_rx/rec_sync.v +++ b/basil/firmware/modules/fei4_rx/rec_sync.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FEI4_RX_REC_SYNC_V -`define BASIL_FEI4_RX_REC_SYNC_V +`ifndef REC_SYNC +`define REC_SYNC `include "utils/flag_domain_crossing.v" diff --git a/basil/firmware/modules/fei4_rx/receiver_logic.v b/basil/firmware/modules/fei4_rx/receiver_logic.v index b63bd107e..e12a46292 100644 --- a/basil/firmware/modules/fei4_rx/receiver_logic.v +++ b/basil/firmware/modules/fei4_rx/receiver_logic.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FEI4_RX_RECEIVER_LOGIC_V -`define BASIL_FEI4_RX_RECEIVER_LOGIC_V +`ifndef RECEIVER_LOGIC +`define RECEIVER_LOGIC `include "utils/flag_domain_crossing.v" `include "utils/cdc_syncfifo.v" diff --git a/basil/firmware/modules/fei4_rx/sync_master.v b/basil/firmware/modules/fei4_rx/sync_master.v index 8da6caae8..7ff1b9ea8 100644 --- a/basil/firmware/modules/fei4_rx/sync_master.v +++ b/basil/firmware/modules/fei4_rx/sync_master.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FEI4_RX_SYNC_MASTER_V -`define BASIL_FEI4_RX_SYNC_MASTER_V +`ifndef SYNC_MASTER +`define SYNC_MASTER `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/fx3_if/FX3_IF.v b/basil/firmware/modules/fx3_if/FX3_IF.v index 75dde9a56..62748782d 100644 --- a/basil/firmware/modules/fx3_if/FX3_IF.v +++ b/basil/firmware/modules/fx3_if/FX3_IF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_FX3_IF_FX3_IF_V -`define BASIL_FX3_IF_FX3_IF_V +`ifndef FX3_IF +`define FX3_IF `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v index efc7c6140..158bf7963 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_GPAC_ADC_RX_GPAC_ADC_IOBUF_V -`define BASIL_GPAC_ADC_RX_GPAC_ADC_IOBUF_V +`ifndef GPAC_ADC_IOBUF +`define GPAC_ADC_IOBUF `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v index 88a84036b..e7aa1ddd0 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_GPAC_ADC_RX_GPAC_ADC_RX_V -`define BASIL_GPAC_ADC_RX_GPAC_ADC_RX_V +`ifndef GPAC_ADC_RX +`define GPAC_ADC_RX `include "gpac_adc_rx/gpac_adc_rx_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v index 07ac2015d..4bdf1d67c 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_GPAC_ADC_RX_GPAC_ADC_RX_CORE_V -`define BASIL_GPAC_ADC_RX_GPAC_ADC_RX_CORE_V +`ifndef GPAC_ADC_RX_CORE +`define GPAC_ADC_RX_CORE `include "utils/cdc_reset_sync.v" `include "utils/cdc_pulse_sync.v" diff --git a/basil/firmware/modules/gpio/gpio.v b/basil/firmware/modules/gpio/gpio.v index f2f12e03e..c67e13282 100644 --- a/basil/firmware/modules/gpio/gpio.v +++ b/basil/firmware/modules/gpio/gpio.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_GPIO_GPIO_V -`define BASIL_GPIO_GPIO_V +`ifndef GPIO +`define GPIO `include "gpio/gpio_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/gpio/gpio_core.v b/basil/firmware/modules/gpio/gpio_core.v index 06379318d..1f73db728 100644 --- a/basil/firmware/modules/gpio/gpio_core.v +++ b/basil/firmware/modules/gpio/gpio_core.v @@ -6,8 +6,8 @@ */ -`ifndef BASIL_GPIO_GPIO_CORE_V -`define BASIL_GPIO_GPIO_CORE_V +`ifndef GPIO_CORE +`define GPIO_CORE module gpio_core #( parameter ABUSWIDTH = 16, diff --git a/basil/firmware/modules/gpio/gpio_sbus.v b/basil/firmware/modules/gpio/gpio_sbus.v index fec4c15b6..6f783c394 100644 --- a/basil/firmware/modules/gpio/gpio_sbus.v +++ b/basil/firmware/modules/gpio/gpio_sbus.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_GPIO_GPIO_SBUS_V -`define BASIL_GPIO_GPIO_SBUS_V +`ifndef GPIO_SBUS +`define GPIO_SBUS `include "gpio/gpio_core.v" `include "utils/sbus_to_ip.v" diff --git a/basil/firmware/modules/i2c/i2c.v b/basil/firmware/modules/i2c/i2c.v index fa1ad4af8..c3b7cda25 100644 --- a/basil/firmware/modules/i2c/i2c.v +++ b/basil/firmware/modules/i2c/i2c.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_I2C_I2C_V -`define BASIL_I2C_I2C_V +`ifndef I2C +`define I2C `include "i2c/i2c_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/i2c/i2c_core.v b/basil/firmware/modules/i2c/i2c_core.v index f5d2e0789..4b48173c7 100644 --- a/basil/firmware/modules/i2c/i2c_core.v +++ b/basil/firmware/modules/i2c/i2c_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_I2C_I2C_CORE_V -`define BASIL_I2C_I2C_CORE_V +`ifndef I2C_CORE +`define I2C_CORE `include "utils/cdc_pulse_sync.v" diff --git a/basil/firmware/modules/includes/jtag_tap.v b/basil/firmware/modules/includes/jtag_tap.v index a4ecc18a5..2f676d607 100644 --- a/basil/firmware/modules/includes/jtag_tap.v +++ b/basil/firmware/modules/includes/jtag_tap.v @@ -1,5 +1,5 @@ -`ifndef BASIL_INCLUDES_JTAG_TAP_V -`define BASIL_INCLUDES_JTAG_TAP_V +`ifndef JTAG_TAP +`define JTAG_TAP `timescale 1ps / 1ps diff --git a/basil/firmware/modules/jtag_master/jtag_master.v b/basil/firmware/modules/jtag_master/jtag_master.v index 9cb551af4..9ad1010be 100644 --- a/basil/firmware/modules/jtag_master/jtag_master.v +++ b/basil/firmware/modules/jtag_master/jtag_master.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_JTAG_MASTER_JTAG_MASTER_V -`define BASIL_JTAG_MASTER_JTAG_MASTER_V +`ifndef JTAG_MASTER +`define JTAG_MASTER `include "jtag_master/jtag_master_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/jtag_master/jtag_master_core.v b/basil/firmware/modules/jtag_master/jtag_master_core.v index 91a06a85d..1791cf6a7 100644 --- a/basil/firmware/modules/jtag_master/jtag_master_core.v +++ b/basil/firmware/modules/jtag_master/jtag_master_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_JTAG_MASTER_JTAG_MASTER_CORE_V -`define BASIL_JTAG_MASTER_JTAG_MASTER_CORE_V +`ifndef JTAG_MASTER_CORE +`define JTAG_MASTER_CORE `include "utils/ramb_8_to_n.v" `include "utils/cdc_reset_sync.v" diff --git a/basil/firmware/modules/m26_rx/m26_rx.v b/basil/firmware/modules/m26_rx/m26_rx.v index 430facde2..226d2f36f 100644 --- a/basil/firmware/modules/m26_rx/m26_rx.v +++ b/basil/firmware/modules/m26_rx/m26_rx.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_M26_RX_M26_RX_V -`define BASIL_M26_RX_M26_RX_V +`ifndef M26_RX +`define M26_RX `include "m26_rx/m26_rx_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/m26_rx/m26_rx_ch.v b/basil/firmware/modules/m26_rx/m26_rx_ch.v index 0013ed701..f952c0830 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_ch.v +++ b/basil/firmware/modules/m26_rx/m26_rx_ch.v @@ -6,8 +6,8 @@ */ -`ifndef BASIL_M26_RX_M26_RX_CH_V -`define BASIL_M26_RX_M26_RX_CH_V +`ifndef M26_RX_CH +`define M26_RX_CH module m26_rx_ch ( diff --git a/basil/firmware/modules/m26_rx/m26_rx_core.v b/basil/firmware/modules/m26_rx/m26_rx_core.v index 50c3bc9f5..ac0ca3c9b 100644 --- a/basil/firmware/modules/m26_rx/m26_rx_core.v +++ b/basil/firmware/modules/m26_rx/m26_rx_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_M26_RX_M26_RX_CORE_V -`define BASIL_M26_RX_M26_RX_CORE_V +`ifndef M26_RX_CORE +`define M26_RX_CORE `include "utils/flag_domain_crossing.v" `include "utils/3_stage_synchronizer.v" diff --git a/basil/firmware/modules/pulse_gen/pulse_gen.v b/basil/firmware/modules/pulse_gen/pulse_gen.v index eb9bb81a6..725aa2321 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_PULSE_GEN_PULSE_GEN_V -`define BASIL_PULSE_GEN_PULSE_GEN_V +`ifndef PULSE_GEN +`define PULSE_GEN `include "pulse_gen/pulse_gen_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/pulse_gen/pulse_gen_core.v b/basil/firmware/modules/pulse_gen/pulse_gen_core.v index 616631145..4dd94daaf 100644 --- a/basil/firmware/modules/pulse_gen/pulse_gen_core.v +++ b/basil/firmware/modules/pulse_gen/pulse_gen_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_PULSE_GEN_PULSE_GEN_CORE_V -`define BASIL_PULSE_GEN_PULSE_GEN_CORE_V +`ifndef PULSE_GEN_CORE +`define PULSE_GEN_CORE `include "utils/3_stage_synchronizer.v" `include "utils/cdc_pulse_sync.v" diff --git a/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v b/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v index 7adb02bf7..eed9df538 100644 --- a/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +++ b/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_RRP_ARBITER_RRP_ARBITER_V -`define BASIL_RRP_ARBITER_RRP_ARBITER_V +`ifndef RRP_ARBITER +`define RRP_ARBITER `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/seq_gen/seq_gen.v b/basil/firmware/modules/seq_gen/seq_gen.v index 5058f7869..13e9df463 100644 --- a/basil/firmware/modules/seq_gen/seq_gen.v +++ b/basil/firmware/modules/seq_gen/seq_gen.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SEQ_GEN_SEQ_GEN_V -`define BASIL_SEQ_GEN_SEQ_GEN_V +`ifndef SEQ_GEN +`define SEQ_GEN `include "seq_gen/seq_gen_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index eace2622a..4baecd8ab 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SEQ_GEN_SEQ_GEN_CORE_V -`define BASIL_SEQ_GEN_SEQ_GEN_CORE_V +`ifndef SEQ_GEN_CORE +`define SEQ_GEN_CORE `include "utils/ramb_8_to_n.v" `include "utils/cdc_pulse_sync.v" diff --git a/basil/firmware/modules/seq_rec/seq_rec.v b/basil/firmware/modules/seq_rec/seq_rec.v index 40d04d0be..5142308c7 100644 --- a/basil/firmware/modules/seq_rec/seq_rec.v +++ b/basil/firmware/modules/seq_rec/seq_rec.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SEQ_REC_SEQ_REC_V -`define BASIL_SEQ_REC_SEQ_REC_V +`ifndef SEQ_REC +`define SEQ_REC `include "seq_rec/seq_rec_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/seq_rec/seq_rec_core.v b/basil/firmware/modules/seq_rec/seq_rec_core.v index 398d652d7..f1cff9a77 100644 --- a/basil/firmware/modules/seq_rec/seq_rec_core.v +++ b/basil/firmware/modules/seq_rec/seq_rec_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SEQ_REC_SEQ_REC_CORE_V -`define BASIL_SEQ_REC_SEQ_REC_CORE_V +`ifndef SEQ_REC_CORE +`define SEQ_REC_CORE `include "utils/flag_domain_crossing.v" `include "utils/3_stage_synchronizer.v" diff --git a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v index 5453f2468..93295d91b 100644 --- a/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v +++ b/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v @@ -25,8 +25,8 @@ * Read behaviour: read-first on both ports (consistent with legacy primitive). * ------------------------------------------------------------ */ -`ifndef BASIL_SPI_BLK_MEM_GEN_8_TO_1_2K_V -`define BASIL_SPI_BLK_MEM_GEN_8_TO_1_2K_V +`ifndef BLK_MEM_GEN_8_TO_1_2K +`define BLK_MEM_GEN_8_TO_1_2K `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/spi/spi.v b/basil/firmware/modules/spi/spi.v index a0dc73b7d..0a4411cb7 100644 --- a/basil/firmware/modules/spi/spi.v +++ b/basil/firmware/modules/spi/spi.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SPI_SPI_V -`define BASIL_SPI_SPI_V +`ifndef SPI +`define SPI `include "spi/spi_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/spi/spi_core.v b/basil/firmware/modules/spi/spi_core.v index 849116cf0..8cf45a626 100644 --- a/basil/firmware/modules/spi/spi_core.v +++ b/basil/firmware/modules/spi/spi_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SPI_SPI_CORE_V -`define BASIL_SPI_SPI_CORE_V +`ifndef SPI_CORE +`define SPI_CORE `include "spi/blk_mem_gen_8_to_1_2k.v" `include "utils/cdc_pulse_sync.v" diff --git a/basil/firmware/modules/sram_fifo/sram_fifo.v b/basil/firmware/modules/sram_fifo/sram_fifo.v index 333802309..297b29ac2 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SRAM_FIFO_SRAM_FIFO_V -`define BASIL_SRAM_FIFO_SRAM_FIFO_V +`ifndef SRAM_FIFO +`define SRAM_FIFO `include "sram_fifo/sram_fifo_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/sram_fifo/sram_fifo_core.v b/basil/firmware/modules/sram_fifo/sram_fifo_core.v index 6ec03b6ee..71ae42442 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo_core.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_SRAM_FIFO_SRAM_FIFO_CORE_V -`define BASIL_SRAM_FIFO_SRAM_FIFO_CORE_V +`ifndef SRAM_FIFO_CORE +`define SRAM_FIFO_CORE `include "utils/generic_fifo.v" diff --git a/basil/firmware/modules/tb/silbusb.v b/basil/firmware/modules/tb/silbusb.v index cad833163..7ecaaf059 100644 --- a/basil/firmware/modules/tb/silbusb.v +++ b/basil/firmware/modules/tb/silbusb.v @@ -10,8 +10,8 @@ * $Date:: $: */ -`ifndef BASIL_TB_SILBUSB_V -`define BASIL_TB_SILBUSB_V +`ifndef SILIBUSB +`define SILIBUSB module SiLibUSB (input FCLK); diff --git a/basil/firmware/modules/tb/uartlib.v b/basil/firmware/modules/tb/uartlib.v index 34ea147ab..ff6cf9118 100644 --- a/basil/firmware/modules/tb/uartlib.v +++ b/basil/firmware/modules/tb/uartlib.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TB_UARTLIB_V -`define BASIL_TB_UARTLIB_V +`ifndef UARTLIB +`define UARTLIB `timescale 1ns / 100ps diff --git a/basil/firmware/modules/tdc_s3/tdc_s3.v b/basil/firmware/modules/tdc_s3/tdc_s3.v index 97e2e0d8b..2cba13591 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TDC_S3_TDC_S3_V -`define BASIL_TDC_S3_TDC_S3_V +`ifndef TDC_S3 +`define TDC_S3 `include "tdc_s3/tdc_s3_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/tdc_s3/tdc_s3_core.v b/basil/firmware/modules/tdc_s3/tdc_s3_core.v index 3edadf407..521326884 100644 --- a/basil/firmware/modules/tdc_s3/tdc_s3_core.v +++ b/basil/firmware/modules/tdc_s3/tdc_s3_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TDC_S3_TDC_S3_CORE_V -`define BASIL_TDC_S3_TDC_S3_CORE_V +`ifndef TDC_S3_CORE +`define TDC_S3_CORE `include "utils/flag_domain_crossing.v" `include "utils/3_stage_synchronizer.v" diff --git a/basil/firmware/modules/tdl_tdc/controller.v b/basil/firmware/modules/tdl_tdc/controller.v index 2ca1575dd..54dffefe1 100644 --- a/basil/firmware/modules/tdl_tdc/controller.v +++ b/basil/firmware/modules/tdl_tdc/controller.v @@ -2,8 +2,8 @@ // multiplexer, controling the corse counter, arming, calibration // states and the trigger distance mode. Furthermore counts successful events // and tdl misses. -`ifndef BASIL_TDL_TDC_CONTROLLER_V -`define BASIL_TDL_TDC_CONTROLLER_V +`ifndef CONTROLLER +`define CONTROLLER module controller #( parameter state_bits = 4, diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v index 34963a768..8f6a57132 100644 --- a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v @@ -1,7 +1,7 @@ //`include "tdl_tdc/counter/slimfast_multioption_counter.xdc" //`include "tdl_tdc/counter/signal_clipper.vhdl" -`ifndef BASIL_TDL_TDC_COUNTER_SLIMFAST_MULTIOPTION_COUNTER_V -`define BASIL_TDL_TDC_COUNTER_SLIMFAST_MULTIOPTION_COUNTER_V +`ifndef SLIMFAST_MULTIOPTION_COUNTER +`define SLIMFAST_MULTIOPTION_COUNTER `include "utils/pulse_gen_rising.v" diff --git a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v index 81d8236fa..2b0b2c4d6 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +++ b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v @@ -24,8 +24,8 @@ //-- -- //--------------------------------------------------------------------- -`ifndef BASIL_TDL_TDC_DELAYLINE_CARRYSAMPLER_SPARTAN6_20PS_V -`define BASIL_TDL_TDC_DELAYLINE_CARRYSAMPLER_SPARTAN6_20PS_V +`ifndef CARRYSAMPLER_SPARTAN6_20PS +`define CARRYSAMPLER_SPARTAN6_20PS module CHAIN_CELL (CINIT, CI, CO, DO, CLK); diff --git a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v index ada34826a..739a7e97a 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +++ b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TDL_TDC_DELAYLINE_SAMPLE_DESER_V -`define BASIL_TDL_TDC_DELAYLINE_SAMPLE_DESER_V +`ifndef SAMPLE_DESER +`define SAMPLE_DESER module sample_deser #( parameter dlyline_bits = 96, diff --git a/basil/firmware/modules/tdl_tdc/priority_encoder.v b/basil/firmware/modules/tdl_tdc/priority_encoder.v index e16ff9fc2..f041266e8 100644 --- a/basil/firmware/modules/tdl_tdc/priority_encoder.v +++ b/basil/firmware/modules/tdl_tdc/priority_encoder.v @@ -4,8 +4,8 @@ //* SiLab, Physics Institute, University of Bonn //* ------------------------------------------------------------ //*/ -`ifndef BASIL_TDL_TDC_PRIORITY_ENCODER_V -`define BASIL_TDL_TDC_PRIORITY_ENCODER_V +`ifndef PRIORITY_ENCODER +`define PRIORITY_ENCODER module priority_encoder( input wire CLK, diff --git a/basil/firmware/modules/tdl_tdc/sw_interface.v b/basil/firmware/modules/tdl_tdc/sw_interface.v index 37f247c09..91f015234 100644 --- a/basil/firmware/modules/tdl_tdc/sw_interface.v +++ b/basil/firmware/modules/tdl_tdc/sw_interface.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TDL_TDC_SW_INTERFACE_V -`define BASIL_TDL_TDC_SW_INTERFACE_V +`ifndef TDC_SW_INTERFACE +`define TDC_SW_INTERFACE `include "tdl_tdc/utils/graycode_2stage_cdc.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/tdl_tdc/tdl_supersampler.v b/basil/firmware/modules/tdl_tdc/tdl_supersampler.v index 3837b5fcc..efa224d08 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +++ b/basil/firmware/modules/tdl_tdc/tdl_supersampler.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TDL_TDC_TDL_SUPERSAMPLER_V -`define BASIL_TDL_TDC_TDL_SUPERSAMPLER_V +`ifndef TDL_AND_DETECTOR +`define TDL_AND_DETECTOR `include "tdl_tdc/delayline/carrysampler_spartan6_20ps.v" `include "tdl_tdc/delayline/sample_deser.v" diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc.v b/basil/firmware/modules/tdl_tdc/tdl_tdc.v index 543940be0..fab6f125c 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc.v @@ -5,8 +5,8 @@ * ------------------------------------------------------------ */ -`ifndef BASIL_TDL_TDC_TDL_TDC_V -`define BASIL_TDL_TDC_TDL_TDC_V +`ifndef TDL_TDC +`define TDL_TDC `include "tdl_tdc/sw_interface.v" `include "tdl_tdc/tdl_tdc_core.v" diff --git a/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v b/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v index fe3f339ee..92cffd016 100644 --- a/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v +++ b/basil/firmware/modules/tdl_tdc/tdl_tdc_core.v @@ -5,8 +5,8 @@ * ------------------------------------------------------------ */ -`ifndef BASIL_TDL_TDC_TDL_TDC_CORE_V -`define BASIL_TDL_TDC_TDL_TDC_CORE_V +`ifndef TDC_CORE +`define TDC_CORE `include "tdl_tdc/tdl_supersampler.v" `include "tdl_tdc/counter/slimfast_multioption_counter.v" diff --git a/basil/firmware/modules/tdl_tdc/utils/delay_n.v b/basil/firmware/modules/tdl_tdc/utils/delay_n.v index 0a38a8edf..cbe949af9 100644 --- a/basil/firmware/modules/tdl_tdc/utils/delay_n.v +++ b/basil/firmware/modules/tdl_tdc/utils/delay_n.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TDL_TDC_UTILS_DELAY_N_V -`define BASIL_TDL_TDC_UTILS_DELAY_N_V +`ifndef DELAY_N +`define DELAY_N module delay_n #( parameter n = 3, diff --git a/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v b/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v index c1cca058f..934f4c609 100644 --- a/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +++ b/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TDL_TDC_UTILS_GRAYCODE_2STAGE_CDC_V -`define BASIL_TDL_TDC_UTILS_GRAYCODE_2STAGE_CDC_V +`ifndef GRAYCODE_2STAGE_CDC +`define GRAYCODE_2STAGE_CDC module graycode_2stage_cdc #(DATA_WIDTH = 8) ( input wire IN_CLK, diff --git a/basil/firmware/modules/tdl_tdc/word_broker.v b/basil/firmware/modules/tdl_tdc/word_broker.v index b90cae2f8..84ebb55fc 100644 --- a/basil/firmware/modules/tdl_tdc/word_broker.v +++ b/basil/firmware/modules/tdl_tdc/word_broker.v @@ -1,5 +1,5 @@ -`ifndef BASIL_TDL_TDC_WORD_BROKER_V -`define BASIL_TDL_TDC_WORD_BROKER_V +`ifndef WORD_BROKER +`define WORD_BROKER module word_broker #( parameter DATA_IDENTIFIER = 4'b0100, diff --git a/basil/firmware/modules/timestamp/timestamp.v b/basil/firmware/modules/timestamp/timestamp.v index e9820b281..fa6ba5561 100644 --- a/basil/firmware/modules/timestamp/timestamp.v +++ b/basil/firmware/modules/timestamp/timestamp.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TIMESTAMP_TIMESTAMP_V -`define BASIL_TIMESTAMP_TIMESTAMP_V +`ifndef TIMESTAMP +`define TIMESTAMP `include "timestamp/timestamp_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/timestamp/timestamp_core.v b/basil/firmware/modules/timestamp/timestamp_core.v index cb86cdd84..dc502f528 100644 --- a/basil/firmware/modules/timestamp/timestamp_core.v +++ b/basil/firmware/modules/timestamp/timestamp_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TIMESTAMP_TIMESTAMP_CORE_V -`define BASIL_TIMESTAMP_TIMESTAMP_CORE_V +`ifndef TIMESTAMP_CORE +`define TIMESTAMP_CORE `include "utils/cdc_pulse_sync.v" `include "utils/cdc_syncfifo.v" diff --git a/basil/firmware/modules/tlu/tlu_controller.v b/basil/firmware/modules/tlu/tlu_controller.v index 31eea8b0f..312b273f0 100644 --- a/basil/firmware/modules/tlu/tlu_controller.v +++ b/basil/firmware/modules/tlu/tlu_controller.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TLU_TLU_CONTROLLER_V -`define BASIL_TLU_TLU_CONTROLLER_V +`ifndef TLU_CONTROLLER +`define TLU_CONTROLLER `include "tlu/tlu_controller_core.v" `include "utils/bus_to_ip.v" diff --git a/basil/firmware/modules/tlu/tlu_controller_core.v b/basil/firmware/modules/tlu/tlu_controller_core.v index a503ab150..ef63dcf99 100644 --- a/basil/firmware/modules/tlu/tlu_controller_core.v +++ b/basil/firmware/modules/tlu/tlu_controller_core.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TLU_TLU_CONTROLLER_CORE_V -`define BASIL_TLU_TLU_CONTROLLER_CORE_V +`ifndef TLU_CONTROLLER_CORE +`define TLU_CONTROLLER_CORE `include "utils/flag_domain_crossing.v" `include "utils/3_stage_synchronizer.v" diff --git a/basil/firmware/modules/tlu/tlu_controller_fsm.v b/basil/firmware/modules/tlu/tlu_controller_fsm.v index fea57a478..5c243d822 100644 --- a/basil/firmware/modules/tlu/tlu_controller_fsm.v +++ b/basil/firmware/modules/tlu/tlu_controller_fsm.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_TLU_TLU_CONTROLLER_FSM_V -`define BASIL_TLU_TLU_CONTROLLER_FSM_V +`ifndef TLU_CONTROLLER_FSM +`define TLU_CONTROLLER_FSM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/uart/uart.v b/basil/firmware/modules/uart/uart.v index fed561193..89eae9cb6 100644 --- a/basil/firmware/modules/uart/uart.v +++ b/basil/firmware/modules/uart/uart.v @@ -1,5 +1,5 @@ -`ifndef BASIL_UART_UART_V -`define BASIL_UART_UART_V +`ifndef UART +`define UART `timescale 1ns / 1ps // Documented Verilog UART diff --git a/basil/firmware/modules/uart/uart_master.v b/basil/firmware/modules/uart/uart_master.v index e370ac846..23a25b2c9 100644 --- a/basil/firmware/modules/uart/uart_master.v +++ b/basil/firmware/modules/uart/uart_master.v @@ -12,8 +12,8 @@ * Initial version: M. Lemarenko */ -`ifndef BASIL_UART_UART_MASTER_V -`define BASIL_UART_UART_MASTER_V +`ifndef UART_MASTER +`define UART_MASTER module uart_master( input UART_CLK_X4, diff --git a/basil/firmware/modules/utils/3_stage_synchronizer.v b/basil/firmware/modules/utils/3_stage_synchronizer.v index d15dc3370..ffe065e13 100644 --- a/basil/firmware/modules/utils/3_stage_synchronizer.v +++ b/basil/firmware/modules/utils/3_stage_synchronizer.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_3_STAGE_SYNCHRONIZER_V -`define BASIL_UTILS_3_STAGE_SYNCHRONIZER_V +`ifndef THREE_STAGE_SYNCHRONIZER +`define THREE_STAGE_SYNCHRONIZER `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/BUFG.v b/basil/firmware/modules/utils/BUFG.v index c3bf680f6..4028bf9b0 100644 --- a/basil/firmware/modules/utils/BUFG.v +++ b/basil/firmware/modules/utils/BUFG.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_BUFG_V -`define BASIL_UTILS_BUFG_V +`ifndef BUFG +`define BUFG `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/CG_MOD_neg.v b/basil/firmware/modules/utils/CG_MOD_neg.v index 5c46f3c52..e6fa98234 100644 --- a/basil/firmware/modules/utils/CG_MOD_neg.v +++ b/basil/firmware/modules/utils/CG_MOD_neg.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CG_MOD_NEG_V -`define BASIL_UTILS_CG_MOD_NEG_V +`ifndef CG_MOD_NEG +`define CG_MOD_NEG `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/CG_MOD_pos.v b/basil/firmware/modules/utils/CG_MOD_pos.v index f3f1aa209..e499c65da 100644 --- a/basil/firmware/modules/utils/CG_MOD_pos.v +++ b/basil/firmware/modules/utils/CG_MOD_pos.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CG_MOD_POS_V -`define BASIL_UTILS_CG_MOD_POS_V +`ifndef CG_MOD_POS +`define CG_MOD_POS `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/DCM.v b/basil/firmware/modules/utils/DCM.v index 4f05347ca..fe0e8b154 100644 --- a/basil/firmware/modules/utils/DCM.v +++ b/basil/firmware/modules/utils/DCM.v @@ -1,8 +1,8 @@ /** Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx */ -`ifndef BASIL_UTILS_DCM_V -`define BASIL_UTILS_DCM_V +`ifndef DCM +`define DCM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUF.v b/basil/firmware/modules/utils/IBUF.v index 2e28cfbb1..7901fd317 100644 --- a/basil/firmware/modules/utils/IBUF.v +++ b/basil/firmware/modules/utils/IBUF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IBUF_V -`define BASIL_UTILS_IBUF_V +`ifndef IBUF +`define IBUF `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUFDS.v b/basil/firmware/modules/utils/IBUFDS.v index 464d25f41..b6811c17d 100644 --- a/basil/firmware/modules/utils/IBUFDS.v +++ b/basil/firmware/modules/utils/IBUFDS.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IBUFDS_V -`define BASIL_UTILS_IBUFDS_V +`ifndef IBUFDS +`define IBUFDS `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUFG.v b/basil/firmware/modules/utils/IBUFG.v index c81100aaa..6e88f9e7f 100644 --- a/basil/firmware/modules/utils/IBUFG.v +++ b/basil/firmware/modules/utils/IBUFG.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IBUFG_V -`define BASIL_UTILS_IBUFG_V +`ifndef IBUFG +`define IBUFG `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUFGDS.v b/basil/firmware/modules/utils/IBUFGDS.v index d301f184c..173f442e1 100644 --- a/basil/firmware/modules/utils/IBUFGDS.v +++ b/basil/firmware/modules/utils/IBUFGDS.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IBUFGDS_V -`define BASIL_UTILS_IBUFGDS_V +`ifndef IBUFGDS +`define IBUFGDS `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR.v b/basil/firmware/modules/utils/IDDR.v index dba89a11d..be88f3be2 100644 --- a/basil/firmware/modules/utils/IDDR.v +++ b/basil/firmware/modules/utils/IDDR.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IDDR_V -`define BASIL_UTILS_IDDR_V +`ifndef IDDR +`define IDDR `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR_s3.v b/basil/firmware/modules/utils/IDDR_s3.v index 4ce99c0f6..4a8ad7025 100644 --- a/basil/firmware/modules/utils/IDDR_s3.v +++ b/basil/firmware/modules/utils/IDDR_s3.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IDDR_S3_V -`define BASIL_UTILS_IDDR_S3_V +`ifndef IDDR_S3 +`define IDDR_S3 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR_s3_noibuf.v b/basil/firmware/modules/utils/IDDR_s3_noibuf.v index 8e6bcba43..13a23dda8 100644 --- a/basil/firmware/modules/utils/IDDR_s3_noibuf.v +++ b/basil/firmware/modules/utils/IDDR_s3_noibuf.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IDDR_S3_NOIBUF_V -`define BASIL_UTILS_IDDR_S3_NOIBUF_V +`ifndef IDDR_S3_NOIBUF +`define IDDR_S3_NOIBUF `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR_s6.v b/basil/firmware/modules/utils/IDDR_s6.v index ebf49f25c..d6fbb6867 100644 --- a/basil/firmware/modules/utils/IDDR_s6.v +++ b/basil/firmware/modules/utils/IDDR_s6.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IDDR_S6_V -`define BASIL_UTILS_IDDR_S6_V +`ifndef IDDR_S6 +`define IDDR_S6 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IOBUF.v b/basil/firmware/modules/utils/IOBUF.v index d752a03f2..eaf99c84f 100644 --- a/basil/firmware/modules/utils/IOBUF.v +++ b/basil/firmware/modules/utils/IOBUF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_IOBUF_V -`define BASIL_UTILS_IOBUF_V +`ifndef IOBUF +`define IOBUF `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/OBUF.v b/basil/firmware/modules/utils/OBUF.v index 91c49c849..61557d354 100644 --- a/basil/firmware/modules/utils/OBUF.v +++ b/basil/firmware/modules/utils/OBUF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_OBUF_V -`define BASIL_UTILS_OBUF_V +`ifndef OBUF +`define OBUF `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/OBUFDS.v b/basil/firmware/modules/utils/OBUFDS.v index 655285e4a..831815ca4 100644 --- a/basil/firmware/modules/utils/OBUFDS.v +++ b/basil/firmware/modules/utils/OBUFDS.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_OBUFDS_V -`define BASIL_UTILS_OBUFDS_V +`ifndef OBUFDS +`define OBUFDS `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ODDR.v b/basil/firmware/modules/utils/ODDR.v index af5ece84e..57d52f7fa 100644 --- a/basil/firmware/modules/utils/ODDR.v +++ b/basil/firmware/modules/utils/ODDR.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_ODDR_V -`define BASIL_UTILS_ODDR_V +`ifndef ODDR +`define ODDR `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ODDR_s3.v b/basil/firmware/modules/utils/ODDR_s3.v index 18c8f8e58..f6edcfffe 100644 --- a/basil/firmware/modules/utils/ODDR_s3.v +++ b/basil/firmware/modules/utils/ODDR_s3.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_ODDR_S3_V -`define BASIL_UTILS_ODDR_S3_V +`ifndef ODDR_S3 +`define ODDR_S3 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ODDR_s6.v b/basil/firmware/modules/utils/ODDR_s6.v index 9f1e27368..5e443cb19 100644 --- a/basil/firmware/modules/utils/ODDR_s6.v +++ b/basil/firmware/modules/utils/ODDR_s6.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_ODDR_S6_V -`define BASIL_UTILS_ODDR_S6_V +`ifndef ODDR_S6 +`define ODDR_S6 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/PLLE2_BASE.v b/basil/firmware/modules/utils/PLLE2_BASE.v index d8167c861..8d1cea482 100644 --- a/basil/firmware/modules/utils/PLLE2_BASE.v +++ b/basil/firmware/modules/utils/PLLE2_BASE.v @@ -1,7 +1,7 @@ // Blackbox simulation model for PLLE2_BASE primitive // Xilinx PLL base module -`ifndef BASIL_UTILS_PLLE2_BASE_V -`define BASIL_UTILS_PLLE2_BASE_V +`ifndef PLLE2_BASE +`define PLLE2_BASE (* blackbox *) module PLLE2_BASE #( diff --git a/basil/firmware/modules/utils/RAMB16_S1_S2.v b/basil/firmware/modules/utils/RAMB16_S1_S2.v index c67b1b1e8..c7a269e9e 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S2.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S2.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_RAMB16_S1_S2_V -`define BASIL_UTILS_RAMB16_S1_S2_V +`ifndef RAMB16_S1_S2 +`define RAMB16_S1_S2 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/RAMB16_S1_S9.v b/basil/firmware/modules/utils/RAMB16_S1_S9.v index e0adc17ab..acb320c43 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S9.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S9.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_RAMB16_S1_S9_V -`define BASIL_UTILS_RAMB16_S1_S9_V +`ifndef RAMB16_S1_S9 +`define RAMB16_S1_S9 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/bus_to_ip.v b/basil/firmware/modules/utils/bus_to_ip.v index 632a9cebf..ab1908b98 100644 --- a/basil/firmware/modules/utils/bus_to_ip.v +++ b/basil/firmware/modules/utils/bus_to_ip.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_BUS_TO_IP_V -`define BASIL_UTILS_BUS_TO_IP_V +`ifndef BUS_TO_IP +`define BUS_TO_IP `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/cdc_pulse_sync.v b/basil/firmware/modules/utils/cdc_pulse_sync.v index 15176e443..74c5baed4 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CDC_PULSE_SYNC_V -`define BASIL_UTILS_CDC_PULSE_SYNC_V +`ifndef CDC_PULSE_SYNC +`define CDC_PULSE_SYNC `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v b/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v index 7972ea387..900edb781 100644 --- a/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v +++ b/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CDC_PULSE_SYNC_CNT_V -`define BASIL_UTILS_CDC_PULSE_SYNC_CNT_V +`ifndef CDC_PULSE_SYNC_CNT +`define CDC_PULSE_SYNC_CNT `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/cdc_reset_sync.v b/basil/firmware/modules/utils/cdc_reset_sync.v index 696968352..72e174364 100644 --- a/basil/firmware/modules/utils/cdc_reset_sync.v +++ b/basil/firmware/modules/utils/cdc_reset_sync.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CDC_RESET_SYNC_V -`define BASIL_UTILS_CDC_RESET_SYNC_V +`ifndef CDC_RESET_SYNC +`define CDC_RESET_SYNC `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/cdc_syncfifo.v b/basil/firmware/modules/utils/cdc_syncfifo.v index 5bbff936b..bfc92fdef 100644 --- a/basil/firmware/modules/utils/cdc_syncfifo.v +++ b/basil/firmware/modules/utils/cdc_syncfifo.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CDC_SYNCFIFO_V -`define BASIL_UTILS_CDC_SYNCFIFO_V +`ifndef CDC_SYNCFIFO +`define CDC_SYNCFIFO `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/clock_divider.v b/basil/firmware/modules/utils/clock_divider.v index 96fbe436b..6c6328ae4 100644 --- a/basil/firmware/modules/utils/clock_divider.v +++ b/basil/firmware/modules/utils/clock_divider.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_CLOCK_DIVIDER_V -`define BASIL_UTILS_CLOCK_DIVIDER_V +`ifndef CLOCK_DIVIDER +`define CLOCK_DIVIDER `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/clock_multiplier.v b/basil/firmware/modules/utils/clock_multiplier.v index 67e4ff113..a16fb5c6d 100644 --- a/basil/firmware/modules/utils/clock_multiplier.v +++ b/basil/firmware/modules/utils/clock_multiplier.v @@ -1,5 +1,5 @@ -`ifndef BASIL_UTILS_CLOCK_MULTIPLIER_V -`define BASIL_UTILS_CLOCK_MULTIPLIER_V +`ifndef CLOCK_MULTIPLIER +`define CLOCK_MULTIPLIER `timescale 1ps / 1ps diff --git a/basil/firmware/modules/utils/ddr_des.v b/basil/firmware/modules/utils/ddr_des.v index 2b967d78e..1e909fc46 100644 --- a/basil/firmware/modules/utils/ddr_des.v +++ b/basil/firmware/modules/utils/ddr_des.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_DDR_DES_V -`define BASIL_UTILS_DDR_DES_V +`ifndef DDR_DES +`define DDR_DES `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/fifo_32_to_8.v b/basil/firmware/modules/utils/fifo_32_to_8.v index 73c53279d..bd50a50d6 100644 --- a/basil/firmware/modules/utils/fifo_32_to_8.v +++ b/basil/firmware/modules/utils/fifo_32_to_8.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_FIFO_32_TO_8_V -`define BASIL_UTILS_FIFO_32_TO_8_V +`ifndef FIFO_32_TO_8 +`define FIFO_32_TO_8 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/fifo_64_to_16.v b/basil/firmware/modules/utils/fifo_64_to_16.v index ef3dad691..2aee21855 100644 --- a/basil/firmware/modules/utils/fifo_64_to_16.v +++ b/basil/firmware/modules/utils/fifo_64_to_16.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_FIFO_64_TO_16_V -`define BASIL_UTILS_FIFO_64_TO_16_V +`ifndef FIFO_64_TO_16 +`define FIFO_64_TO_16 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/fifo_8_to_32.v b/basil/firmware/modules/utils/fifo_8_to_32.v index d77e307b0..a87e70f3b 100644 --- a/basil/firmware/modules/utils/fifo_8_to_32.v +++ b/basil/firmware/modules/utils/fifo_8_to_32.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_FIFO_8_TO_32_V -`define BASIL_UTILS_FIFO_8_TO_32_V +`ifndef FIFO_8_TO_32 +`define FIFO_8_TO_32 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/fifo_8_to_64.v b/basil/firmware/modules/utils/fifo_8_to_64.v index 855ea34ca..4a65a8553 100644 --- a/basil/firmware/modules/utils/fifo_8_to_64.v +++ b/basil/firmware/modules/utils/fifo_8_to_64.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_FIFO_8_TO_64_V -`define BASIL_UTILS_FIFO_8_TO_64_V +`ifndef FIFO_8_TO_64 +`define FIFO_8_TO_64 `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/flag_domain_crossing.v b/basil/firmware/modules/utils/flag_domain_crossing.v index b2c621c1f..a3cf71c77 100644 --- a/basil/firmware/modules/utils/flag_domain_crossing.v +++ b/basil/firmware/modules/utils/flag_domain_crossing.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_FLAG_DOMAIN_CROSSING_V -`define BASIL_UTILS_FLAG_DOMAIN_CROSSING_V +`ifndef FLAG_DOMAIN_CROSSING +`define FLAG_DOMAIN_CROSSING `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/fx2_to_bus.v b/basil/firmware/modules/utils/fx2_to_bus.v index 8d6576660..576f670fe 100644 --- a/basil/firmware/modules/utils/fx2_to_bus.v +++ b/basil/firmware/modules/utils/fx2_to_bus.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_FX2_TO_BUS_V -`define BASIL_UTILS_FX2_TO_BUS_V +`ifndef FX2_TO_BUS +`define FX2_TO_BUS `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/generic_fifo.v b/basil/firmware/modules/utils/generic_fifo.v index 74fd24173..9bbfdfacc 100644 --- a/basil/firmware/modules/utils/generic_fifo.v +++ b/basil/firmware/modules/utils/generic_fifo.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_GENERIC_FIFO_V -`define BASIL_UTILS_GENERIC_FIFO_V +`ifndef GENERIC_FIFO +`define GENERIC_FIFO `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/pulse_gen_rising.v b/basil/firmware/modules/utils/pulse_gen_rising.v index c11d16c6e..a43103560 100644 --- a/basil/firmware/modules/utils/pulse_gen_rising.v +++ b/basil/firmware/modules/utils/pulse_gen_rising.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_PULSE_GEN_RISING_V -`define BASIL_UTILS_PULSE_GEN_RISING_V +`ifndef PULSE_GEN_RISING +`define PULSE_GEN_RISING `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ramb_8_to_n.v b/basil/firmware/modules/utils/ramb_8_to_n.v index f50da3b78..61e55ea81 100644 --- a/basil/firmware/modules/utils/ramb_8_to_n.v +++ b/basil/firmware/modules/utils/ramb_8_to_n.v @@ -6,8 +6,8 @@ */ -`ifndef BASIL_UTILS_RAMB_8_TO_N_V -`define BASIL_UTILS_RAMB_8_TO_N_V +`ifndef RAMB_8_TO_N +`define RAMB_8_TO_N module ramb_8_to_n (clkA, clkB, diff --git a/basil/firmware/modules/utils/rbcp_to_bus.v b/basil/firmware/modules/utils/rbcp_to_bus.v index b713ab711..c2587ae5b 100644 --- a/basil/firmware/modules/utils/rbcp_to_bus.v +++ b/basil/firmware/modules/utils/rbcp_to_bus.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_RBCP_TO_BUS_V -`define BASIL_UTILS_RBCP_TO_BUS_V +`ifndef RBCP_TO_BUS +`define RBCP_TO_BUS `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/reset_gen.v b/basil/firmware/modules/utils/reset_gen.v index ce1507538..34faa4531 100644 --- a/basil/firmware/modules/utils/reset_gen.v +++ b/basil/firmware/modules/utils/reset_gen.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_RESET_GEN_V -`define BASIL_UTILS_RESET_GEN_V +`ifndef RESET_GEN +`define RESET_GEN `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/rgmii_io.v b/basil/firmware/modules/utils/rgmii_io.v index 57067f2ab..485c4ee3f 100644 --- a/basil/firmware/modules/utils/rgmii_io.v +++ b/basil/firmware/modules/utils/rgmii_io.v @@ -9,8 +9,8 @@ /////////////////////////////////////////////////////////////////////////////// -`ifndef BASIL_UTILS_RGMII_IO_V -`define BASIL_UTILS_RGMII_IO_V +`ifndef RGMII_IO +`define RGMII_IO module rgmii_io ( //----------------------------------------------------------------------- diff --git a/basil/firmware/modules/utils/sbus_to_ip.v b/basil/firmware/modules/utils/sbus_to_ip.v index d2d1bacd9..507a8fe7b 100644 --- a/basil/firmware/modules/utils/sbus_to_ip.v +++ b/basil/firmware/modules/utils/sbus_to_ip.v @@ -6,8 +6,8 @@ */ -`ifndef BASIL_UTILS_SBUS_TO_IP_V -`define BASIL_UTILS_SBUS_TO_IP_V +`ifndef SBUS_TO_IP +`define SBUS_TO_IP module sbus_to_ip #( diff --git a/basil/firmware/modules/utils/simple_arbiter.v b/basil/firmware/modules/utils/simple_arbiter.v index 1d73d2b6a..1b11f74a1 100644 --- a/basil/firmware/modules/utils/simple_arbiter.v +++ b/basil/firmware/modules/utils/simple_arbiter.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_SIMPLE_ARBITER_V -`define BASIL_UTILS_SIMPLE_ARBITER_V +`ifndef ARBITER +`define ARBITER `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/tcp_to_bus.v b/basil/firmware/modules/utils/tcp_to_bus.v index ce4122eb5..70cdb4f5d 100644 --- a/basil/firmware/modules/utils/tcp_to_bus.v +++ b/basil/firmware/modules/utils/tcp_to_bus.v @@ -5,8 +5,8 @@ * ------------------------------------------------------------ */ -`ifndef BASIL_UTILS_TCP_TO_BUS_V -`define BASIL_UTILS_TCP_TO_BUS_V +`ifndef TCP_TO_BUS +`define TCP_TO_BUS `timescale 1ps / 1ps `default_nettype none From ccd85ea998474873c358cf30d6bdf1f4168f1493 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 27 May 2026 16:46:25 +0200 Subject: [PATCH 42/43] fix(verilog): Update two linting rules, and remove unneeded blackbox for PLL --- basil/firmware/modules/gpio/gpio_core.v | 10 ++--- basil/firmware/modules/includes/jtag_tap.v | 5 ++- basil/firmware/modules/utils/PLLE2_BASE.v | 49 ---------------------- 3 files changed, 9 insertions(+), 55 deletions(-) delete mode 100644 basil/firmware/modules/utils/PLLE2_BASE.v diff --git a/basil/firmware/modules/gpio/gpio_core.v b/basil/firmware/modules/gpio/gpio_core.v index 1f73db728..769382f41 100644 --- a/basil/firmware/modules/gpio/gpio_core.v +++ b/basil/firmware/modules/gpio/gpio_core.v @@ -12,8 +12,8 @@ module gpio_core #( parameter ABUSWIDTH = 16, parameter IO_WIDTH = 8, - parameter [IO_WIDTH-1:0] IO_DIRECTION = 0, - parameter [IO_WIDTH-1:0] IO_TRI = 0 + parameter [IO_WIDTH-1:0] IO_DIRECTION = {0,0,0,0,0,0,0,0,0}, + parameter [IO_WIDTH-1:0] IO_TRI = {0,0,0,0,0,0,0,0,0} ) ( BUS_CLK, BUS_RST, @@ -28,14 +28,14 @@ module gpio_core #( localparam VERSION = 0; -// -------- +// ---- // ORDER: // 0 - RESET // 1*B - INPUT (readback) // 2*B - OUTPUT // 3*B - DIRECTION/OUTPUT_ENABLE // B = IO_WIDTH/8+1 -//---- +// ---- input wire BUS_CLK; input wire BUS_RST; @@ -46,7 +46,7 @@ input wire BUS_RD; input wire BUS_WR; inout wire [IO_WIDTH-1:0] IO; -// CORE // +// CORE wire SOFT_RST; //0 localparam IO_BYTES = ((IO_WIDTH-1)/8)+1; diff --git a/basil/firmware/modules/includes/jtag_tap.v b/basil/firmware/modules/includes/jtag_tap.v index 2f676d607..d979f26f3 100644 --- a/basil/firmware/modules/includes/jtag_tap.v +++ b/basil/firmware/modules/includes/jtag_tap.v @@ -54,7 +54,10 @@ ///////////////////////////// `define UNIQUE `define FINISH_WITH_ERROR_EXIT_CODE -`define ASSERT_FALSE $display( "ERROR: Assertion failed in module %m." ); `FINISH_WITH_ERROR_EXIT_CODE + +// WARNING: __FILE__ and __LINE only available in SystemVerilog 2009 and later +// A Verilog only solution would be: define ASSERT_FALSE $display( "ERROR: Assertion failed in module %m." ); `FINISH_WITH_ERROR_EXIT_CODE +`define ASSERT_FALSE $display("ERROR: Assertion failed at %0s:%0d in module %m.", `__FILE__, `__LINE__ ); `FINISH_WITH_ERROR_EXIT_CODE ///////////////////////////// //`include "tap_defines.v" diff --git a/basil/firmware/modules/utils/PLLE2_BASE.v b/basil/firmware/modules/utils/PLLE2_BASE.v deleted file mode 100644 index 8d1cea482..000000000 --- a/basil/firmware/modules/utils/PLLE2_BASE.v +++ /dev/null @@ -1,49 +0,0 @@ -// Blackbox simulation model for PLLE2_BASE primitive -// Xilinx PLL base module -`ifndef PLLE2_BASE -`define PLLE2_BASE - -(* blackbox *) -module PLLE2_BASE #( - parameter BANDWIDTH = "OPTIMIZED", - parameter CLKFBOUT_MULT = 4, - parameter CLKFBOUT_PHASE = 0.0, - parameter CLKIN1_PERIOD = 0.0, - parameter DIVCLK_DIVIDE = 1, - parameter REF_JITTER1 = 0.0, - parameter STARTUP_WAIT = "FALSE", - parameter CLKOUT0_DIVIDE = 1, - parameter CLKOUT0_DUTY_CYCLE = 50.0, - parameter CLKOUT0_PHASE = 0.0, - parameter CLKOUT1_DIVIDE = 1, - parameter CLKOUT1_DUTY_CYCLE = 50.0, - parameter CLKOUT1_PHASE = 0.0, - parameter CLKOUT2_DIVIDE = 1, - parameter CLKOUT2_DUTY_CYCLE = 50.0, - parameter CLKOUT2_PHASE = 0.0, - parameter CLKOUT3_DIVIDE = 1, - parameter CLKOUT3_DUTY_CYCLE = 50.0, - parameter CLKOUT3_PHASE = 0.0, - parameter CLKOUT4_DIVIDE = 1, - parameter CLKOUT4_DUTY_CYCLE = 50.0, - parameter CLKOUT4_PHASE = 0.0, - parameter CLKOUT5_DIVIDE = 1, - parameter CLKOUT5_DUTY_CYCLE = 50.0, - parameter CLKOUT5_PHASE = 0.0 -)( - output wire CLKFBOUT, - output wire CLKOUT0, - output wire CLKOUT1, - output wire CLKOUT2, - output wire CLKOUT3, - output wire CLKOUT4, - output wire CLKOUT5, - output wire LOCKED, - input wire CLKIN1, - input wire PWRDWN, - input wire RST, - input wire CLKFBIN -); -endmodule - -`endif From 81cffc77ee55351606a6a285726982522248d378 Mon Sep 17 00:00:00 2001 From: Kennedy Caisley Date: Wed, 27 May 2026 17:06:02 +0200 Subject: [PATCH 43/43] fix(verilog): Update include guards on simulation models to include _SIM suffix --- basil/firmware/modules/utils/BUFG.v | 4 ++-- basil/firmware/modules/utils/DCM.v | 4 ++-- basil/firmware/modules/utils/IBUF.v | 4 ++-- basil/firmware/modules/utils/IBUFDS.v | 4 ++-- basil/firmware/modules/utils/IBUFG.v | 4 ++-- basil/firmware/modules/utils/IBUFGDS.v | 4 ++-- basil/firmware/modules/utils/IDDR.v | 4 ++-- basil/firmware/modules/utils/IDDR_s3.v | 4 ++-- basil/firmware/modules/utils/IDDR_s3_noibuf.v | 4 ++-- basil/firmware/modules/utils/IDDR_s6.v | 4 ++-- basil/firmware/modules/utils/IOBUF.v | 4 ++-- basil/firmware/modules/utils/OBUF.v | 4 ++-- basil/firmware/modules/utils/OBUFDS.v | 4 ++-- basil/firmware/modules/utils/ODDR.v | 4 ++-- basil/firmware/modules/utils/ODDR_s3.v | 4 ++-- basil/firmware/modules/utils/ODDR_s6.v | 4 ++-- basil/firmware/modules/utils/RAMB16_S1_S2.v | 4 ++-- basil/firmware/modules/utils/RAMB16_S1_S9.v | 4 ++-- 18 files changed, 36 insertions(+), 36 deletions(-) diff --git a/basil/firmware/modules/utils/BUFG.v b/basil/firmware/modules/utils/BUFG.v index 4028bf9b0..d25320eb7 100644 --- a/basil/firmware/modules/utils/BUFG.v +++ b/basil/firmware/modules/utils/BUFG.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef BUFG -`define BUFG +`ifndef BUFG_SIM +`define BUFG_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/DCM.v b/basil/firmware/modules/utils/DCM.v index fe0e8b154..bd2e070a9 100644 --- a/basil/firmware/modules/utils/DCM.v +++ b/basil/firmware/modules/utils/DCM.v @@ -1,8 +1,8 @@ /** Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx */ -`ifndef DCM -`define DCM +`ifndef DCM_SIM +`define DCM_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUF.v b/basil/firmware/modules/utils/IBUF.v index 7901fd317..5f27a7c62 100644 --- a/basil/firmware/modules/utils/IBUF.v +++ b/basil/firmware/modules/utils/IBUF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IBUF -`define IBUF +`ifndef IBUF_SIM +`define IBUF_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUFDS.v b/basil/firmware/modules/utils/IBUFDS.v index b6811c17d..1ba1de2df 100644 --- a/basil/firmware/modules/utils/IBUFDS.v +++ b/basil/firmware/modules/utils/IBUFDS.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IBUFDS -`define IBUFDS +`ifndef IBUFDS_SIM +`define IBUFDS_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUFG.v b/basil/firmware/modules/utils/IBUFG.v index 6e88f9e7f..a50b38a18 100644 --- a/basil/firmware/modules/utils/IBUFG.v +++ b/basil/firmware/modules/utils/IBUFG.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IBUFG -`define IBUFG +`ifndef IBUFG_SIM +`define IBUFG_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IBUFGDS.v b/basil/firmware/modules/utils/IBUFGDS.v index 173f442e1..a83f6bb20 100644 --- a/basil/firmware/modules/utils/IBUFGDS.v +++ b/basil/firmware/modules/utils/IBUFGDS.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IBUFGDS -`define IBUFGDS +`ifndef IBUFGDS_SIM +`define IBUFGDS_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR.v b/basil/firmware/modules/utils/IDDR.v index be88f3be2..20dde34ea 100644 --- a/basil/firmware/modules/utils/IDDR.v +++ b/basil/firmware/modules/utils/IDDR.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IDDR -`define IDDR +`ifndef IDDR_SIM +`define IDDR_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR_s3.v b/basil/firmware/modules/utils/IDDR_s3.v index 4a8ad7025..89025c792 100644 --- a/basil/firmware/modules/utils/IDDR_s3.v +++ b/basil/firmware/modules/utils/IDDR_s3.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IDDR_S3 -`define IDDR_S3 +`ifndef IDDR_S3_SIM +`define IDDR_S3_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR_s3_noibuf.v b/basil/firmware/modules/utils/IDDR_s3_noibuf.v index 13a23dda8..f82b800de 100644 --- a/basil/firmware/modules/utils/IDDR_s3_noibuf.v +++ b/basil/firmware/modules/utils/IDDR_s3_noibuf.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IDDR_S3_NOIBUF -`define IDDR_S3_NOIBUF +`ifndef IDDR_S3_NOIBUF_SIM +`define IDDR_S3_NOIBUF_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IDDR_s6.v b/basil/firmware/modules/utils/IDDR_s6.v index d6fbb6867..a46dd756d 100644 --- a/basil/firmware/modules/utils/IDDR_s6.v +++ b/basil/firmware/modules/utils/IDDR_s6.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IDDR_S6 -`define IDDR_S6 +`ifndef IDDR_S6_SIM +`define IDDR_S6_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/IOBUF.v b/basil/firmware/modules/utils/IOBUF.v index eaf99c84f..99e057481 100644 --- a/basil/firmware/modules/utils/IOBUF.v +++ b/basil/firmware/modules/utils/IOBUF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef IOBUF -`define IOBUF +`ifndef IOBUF_SIM +`define IOBUF_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/OBUF.v b/basil/firmware/modules/utils/OBUF.v index 61557d354..eb457ecfc 100644 --- a/basil/firmware/modules/utils/OBUF.v +++ b/basil/firmware/modules/utils/OBUF.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef OBUF -`define OBUF +`ifndef OBUF_SIM +`define OBUF_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/OBUFDS.v b/basil/firmware/modules/utils/OBUFDS.v index 831815ca4..65ca9f7b9 100644 --- a/basil/firmware/modules/utils/OBUFDS.v +++ b/basil/firmware/modules/utils/OBUFDS.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef OBUFDS -`define OBUFDS +`ifndef OBUFDS_SIM +`define OBUFDS_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ODDR.v b/basil/firmware/modules/utils/ODDR.v index 57d52f7fa..f35a0e829 100644 --- a/basil/firmware/modules/utils/ODDR.v +++ b/basil/firmware/modules/utils/ODDR.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef ODDR -`define ODDR +`ifndef ODDR_SIM +`define ODDR_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ODDR_s3.v b/basil/firmware/modules/utils/ODDR_s3.v index f6edcfffe..8032682cf 100644 --- a/basil/firmware/modules/utils/ODDR_s3.v +++ b/basil/firmware/modules/utils/ODDR_s3.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef ODDR_S3 -`define ODDR_S3 +`ifndef ODDR_S3_SIM +`define ODDR_S3_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/ODDR_s6.v b/basil/firmware/modules/utils/ODDR_s6.v index 5e443cb19..e10f104a8 100644 --- a/basil/firmware/modules/utils/ODDR_s6.v +++ b/basil/firmware/modules/utils/ODDR_s6.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef ODDR_S6 -`define ODDR_S6 +`ifndef ODDR_S6_SIM +`define ODDR_S6_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/RAMB16_S1_S2.v b/basil/firmware/modules/utils/RAMB16_S1_S2.v index c7a269e9e..0b9a46ad7 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S2.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S2.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef RAMB16_S1_S2 -`define RAMB16_S1_S2 +`ifndef RAMB16_S1_S2_SIM +`define RAMB16_S1_S2_SIM `timescale 1ps/1ps `default_nettype none diff --git a/basil/firmware/modules/utils/RAMB16_S1_S9.v b/basil/firmware/modules/utils/RAMB16_S1_S9.v index acb320c43..cfc679695 100644 --- a/basil/firmware/modules/utils/RAMB16_S1_S9.v +++ b/basil/firmware/modules/utils/RAMB16_S1_S9.v @@ -4,8 +4,8 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`ifndef RAMB16_S1_S9 -`define RAMB16_S1_S9 +`ifndef RAMB16_S1_S9_SIM +`define RAMB16_S1_S9_SIM `timescale 1ps/1ps `default_nettype none