i2c/Makefile at main · The-Chiselers/i2c · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
MAKEFLAGS += --silent

SBT = sbt

.PHONY: clean docs update verilog synth sta test

# The Following Vars are set by the development flake:
# - BUILD_ROOT_RELATIVE
# - BUILD_ROOT
# - PROJECT_ROOT
# - FIRTOOL_REV


# Run everything and scan for errors
# list:
# 	@grep '^[^#[:space:]].*:' Makefile

# all: clean publish docs cov yosys check

# Validates the environment to see if it is possible to run
validate:
	@if [ -z $(BUILD_ROOT) ]; then echo "BUILD_ROOT is not set"; exit 1; fi
	@if [ -z $(PROJECT_ROOT) ]; then echo "PROJECT_ROOT is not set"; exit 1; fi
	@if [ -z $(TOP) ]; then echo "TOP is not set"; exit 1; fi
	@if [ -z $(FIRTOOL_REV) ]; then echo "FIRTOOL_REV is not set"; exit 1; fi

# check:
# 	@echo
# 	@echo Checking for errors
# 	grep error */*.rpt */*/*/*.rpt */*/*/*.log | tee error.rpt
# 	grep Error */*.rpt */*/*/*.rpt */*/*/*.log | tee -a error.rpt
# 	grep fail */*.rpt */*/*/*.rpt */*/*/*.log | grep -v "failed 0" | tee -a error.rpt
# 	@echo;
# 	if [ ! -s error.rpt ]; \
# 	then echo "\e[1;32mALL TESTS PASSED WITH NO ERRORS \e[0m"; \
# 	else echo "\e[1;31mTESTS COMPLETED WITH ERRORS \e[0m"; \
# 	fi;
# 	@echo

# Start with a fresh directory
clean:
	@echo Cleaning
	rm -rf generated target *anno.json ./*.rpt doc/*.rpt syn/*.rpt syn.log out test_run_dir
	rm -rf project/build.properties project/project project/target

	# filter all files with bad extensions:
	find . -type f -name "*.aux" -delete
	find . -type f -name "*.toc" -delete
	find . -type f -name "*.out" -delete
	find . -type f -name "*.log" -delete
	find . -type f -name "*.fdb_latexmk" -delete
	find . -type f -name "*.fls" -delete
	find . -type f -name "*.synctex.gz" -delete
	find . -type f -name "*.pdf" -delete

# Publish the documentation (locally)
# publish:
# 	@echo Publishing local
# 	rm -rf /home/tws/.ivy2/local/tech.rocksavage/$(TOP)_2.13
# 	$(SBT) "publishLocal" | tee doc/publish.rpt

# Generate the documentation
docs:
	@echo Generating docs
	mkdir -p $(PWD)/out/doc
	cd $(PWD)/doc/user-guide && pdflatex -output-directory=$(PWD)/out/doc $(PWD)/doc/user-guide/I2C.tex | tee -a $(PWD)/out/doc/doc.rpt

doc_frags:
	@echo Generating doc fragments
	@$(SBT) "runMain tech.rocksavage.Main docs --module tech.rocksavage.chiselware.I2C.I2C --techlib synth/stdcells.lib --config-class tech.rocksavage.chiselware.I2C.I2cConfig --clock-period 5.0"


# Run the tests
test: validate
	@echo Running tests
	mkdir -p $(BUILD_ROOT)/test
	mkdir -p $(BUILD_ROOT)/cov/verilog
	mkdir -p $(BUILD_ROOT)/cov/scala
	$(SBT) -DtestName="allTests" -DuseVerilator="true" test | tee $(BUILD_ROOT)/test/test.rpt

# Run the tests with Scala code coverage enables
cov: validate
	@echo Running tests with coverage enabled
	mkdir -p $(BUILD_ROOT)/test
	mkdir -p $(BUILD_ROOT)/cov/scala
	mkdir -p $(BUILD_ROOT)/cov/verilog
	$(SBT) clean \
	coverageOn \
	test \
	"runMain tech.rocksavage.chiselware.$(TOP).GenVerilog" \
	"runMain tech.rocksavage.chiselware.$(TOP).Main" \
	coverageReport | tee $(BUILD_ROOT)/cov/scala/test.rpt
	google-chrome --new-window $(BUILD_ROOT)/cov/scala/scoverage-report/index.html &

# Synthesize the design
# synth: verilog
# 	@echo Synthesizing
# 	sh $(PROJECT_ROOT)/synth/synth.sh

# Generate timing analysis
# sta: synth
# 	# Uses a python script to generate the SDC file
# 	mkdir -p $(BUILD_ROOT)/sta
# 	python3 $(PROJECT_ROOT)/synth/sdc.py --top $(TOP) --out $(BUILD_ROOT)/sta/$(TOP).sdc --clock clock=5.0
# 	sh $(PROJECT_ROOT)/synth/sta.sh

verilog:
	@echo Generating Verilog...
	@$(SBT) "runMain tech.rocksavage.Main verilog --mode write --module tech.rocksavage.chiselware.I2C.I2C --config-class tech.rocksavage.chiselware.I2C.I2cConfig"

synth:
	@echo Synthesizing...
	@$(SBT) "runMain tech.rocksavage.Main synth --module tech.rocksavage.chiselware.I2C.I2C --techlib synth/stdcells.lib --config-class tech.rocksavage.chiselware.I2C.I2cConfig"

sta:
	@echo Running Timing Analysis...
	@$(SBT) "runMain tech.rocksavage.Main sta --module tech.rocksavage.chiselware.I2C.I2C --techlib synth/stdcells.lib --config-class tech.rocksavage.chiselware.I2C.I2cConfig --clock-period 5.0"