Merge remote-tracking branch 'origin/main'

# Conflicts:
#	src/main/scala/tech/rocksavage/chiselware/timer/TimerConfig.scala
#	src/test/scala/tech/rocksavage/chiselware/timer/TimerTest.scala

Author: nickrallison

Makefile

@@ -22,6 +22,7 @@ clean:
 	rm -rf generated target *anno.json ./*.rpt doc/*.rpt syn/*.rpt syn.log out test_run_dir target
 	rm -rf project/project project/target
 	rm -rf generated
+	rm -rf ~/.sbt ~/.ivy2
 	# filter all files with bad extensions
 	find . -type f -name "*.aux" -delete
 	find . -type f -name "*.toc" -delete
@@ -46,7 +47,7 @@ sta:
 
 test:
 	@echo Running tests...
-	@$(SBT) test
+	@$(SBT) test -DuseVerilator="true"
 
 cov: 
 	@$(SBT) coverageOn test coverageReport

build.sbt

@@ -8,23 +8,23 @@ ThisBuild / organizationName := "Rocksavage Technology"
 //Test / parallelExecution := false
 
 lazy val chisel_module_runner = RootProject(
-  uri("https://github.com/The-Chiselers/chisel_module_runner.git#main")
+  uri("https://github.com/The-Chiselers/chisel_module_runner.git#main"),
 )
 lazy val stdlib = RootProject(
-  uri("https://github.com/The-Chiselers/stdlib.git#main")
+  uri("https://github.com/The-Chiselers/stdlib.git#main"),
 )
 lazy val synth = RootProject(
-  uri("https://github.com/The-Chiselers/synth.git#main")
+  uri("https://github.com/The-Chiselers/synth.git#main"),
 )
 lazy val addrdecode = RootProject(
-  uri("https://github.com/The-Chiselers/addrdecode.git#main")
+  uri("https://github.com/The-Chiselers/addrdecode.git#main"),
 )
 lazy val apb = RootProject(uri("https://github.com/The-Chiselers/apb.git#main"))
 lazy val registermap = RootProject(
-  uri("https://github.com/The-Chiselers/registermap.git#main")
+  uri("https://github.com/The-Chiselers/registermap.git#main"),
 )
 lazy val test_utils = RootProject(
-  uri("https://github.com/The-Chiselers/test_utils.git#main")
+  uri("https://github.com/The-Chiselers/test_utils.git#main"),
 )
 lazy val root = (project in file("."))
     .settings(
@@ -33,18 +33,18 @@ lazy val root = (project in file("."))
       libraryDependencies ++= Seq(
         "org.chipsalliance" %% "chisel"     % chiselVersion,
         "edu.berkeley.cs"   %% "chiseltest" % "6.0.0",
-        "org.rogach"        %% "scallop"    % "5.2.0"
+        "org.rogach"        %% "scallop"    % "5.2.0",
       ),
       scalacOptions ++= Seq(
         "-language:reflectiveCalls",
         "-deprecation",
         "-feature",
         "-Xcheckinit",
-        "-Ymacro-annotations"
+        "-Ymacro-annotations",
       ),
       addCompilerPlugin(
-        "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full
-      )
+        "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full,
+      ),
     )
     .dependsOn(
       chisel_module_runner,
@@ -53,7 +53,7 @@ lazy val root = (project in file("."))
       addrdecode,
       apb,
       registermap,
-      test_utils
+      test_utils,
     )
 val chiselVersion   = "6.6.0"
 val scalafmtVersion = "2.5.0"

flake.nix

@@ -23,6 +23,7 @@
                     sbt
                     scala-cli
                     scalafmt
+                    scalafix
 
                     # Chisel
                     circt
@@ -108,6 +109,7 @@
                       sbt
                       scala-cli
                       scalafmt
+                      scalafix
 
                       # Chisel
                       circt
@@ -189,6 +191,7 @@
                       sbt
                       scala-cli
                       scalafmt
+                      scalafix
 
                       # Chisel
                       circt

shared-config

@@ -3,21 +3,26 @@
 package tech.rocksavage.chiselware.timer
 
 import chisel3._
-import tech.rocksavage.chiselware.addrdecode.{AddrDecode, AddrDecodeError}
+import tech.rocksavage.chiselware.addrdecode.AddrDecode
+import tech.rocksavage.chiselware.addrdecode.AddrDecodeError
 import tech.rocksavage.chiselware.addressable.RegisterMap
-import tech.rocksavage.chiselware.apb.{ApbBundle, ApbParams}
+import tech.rocksavage.chiselware.apb.ApbBundle
+import tech.rocksavage.chiselware.apb.ApbParams
 import tech.rocksavage.chiselware.timer.bundle.TimerOutputBundle
 import tech.rocksavage.chiselware.timer.param.TimerParams
+import tech.rocksavage.test.TestUtils.coverAll
 
-/** A Timer module that implements a configurable timer with various
-  * functionalities.
+/** A Timer module that implements a configurable timer with various functionalities.
   *
   * @param timerParams
   *   Parameters for configuring the timer.
   * @param formal
   *   A boolean value to enable formal verification.
   */
-class Timer(val timerParams: TimerParams, formal: Boolean) extends Module {
+class Timer(
+    val timerParams: TimerParams,
+    formal: Boolean)
+    extends Module {
 
     /** Data width for the timer */
     val dataWidth = timerParams.dataWidth
@@ -50,55 +55,55 @@ class Timer(val timerParams: TimerParams, formal: Boolean) extends Module {
     registerMap.createAddressableRegister(
       en,
       "en",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     /** Prescaler value register */
     val prescaler: UInt = RegInit(0.U(timerParams.prescalerWidth.W))
     registerMap.createAddressableRegister(
       prescaler,
       "prescaler",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     /** Maximum count value register */
     val maxCount: UInt = RegInit(0.U(timerParams.countWidth.W))
     registerMap.createAddressableRegister(
       maxCount,
       "maxCount",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     /** PWM ceiling value register */
     val pwmCeiling: UInt = RegInit(0.U(timerParams.countWidth.W))
     registerMap.createAddressableRegister(
       pwmCeiling,
       "pwmCeiling",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     /** Value to set the count register */
     val setCountValue: UInt = RegInit(0.U(timerParams.countWidth.W))
     registerMap.createAddressableRegister(
       setCountValue,
       "setCountValue",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     /** Signal to set the count register */
     val setCount: Bool = RegInit(false.B)
     registerMap.createAddressableRegister(
       setCount,
       "setCount",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     /** Enable interrupt for maximum count register */
     val maxCountEnableInterrupt: Bool = RegInit(false.B)
     registerMap.createAddressableRegister(
       maxCountEnableInterrupt,
       "maxCountEnableInterrupt",
-      verbose = timerParams.verbose
+      verbose = timerParams.verbose,
     )
 
     // Generate AddrDecode
@@ -111,37 +116,39 @@ class Timer(val timerParams: TimerParams, formal: Boolean) extends Module {
     addrDecode.io.en       := true.B
     addrDecode.io.selInput := true.B
     io.apb.PREADY          := (io.apb.PENABLE && io.apb.PSEL)
-    io.apb.PSLVERR := addrDecode.io.errorCode === AddrDecodeError.AddressOutOfRange
-    io.apb.PRDATA := 0.U
+    io.apb.PSLVERR         := addrDecode.io.errorCode === AddrDecodeError.AddressOutOfRange
+    io.apb.PRDATA          := 0.U
 
     // Control Register Read/Write
     when(io.apb.PSEL && io.apb.PENABLE) {
         when(io.apb.PWRITE) {
-            for (reg <- registerMap.getRegisters) {
+            for (reg <- registerMap.getRegisters)
                 when(addrDecode.io.sel(reg.id)) {
                     reg.writeCallback(addrDecode.io.addrOut, io.apb.PWDATA)
                 }
-            }
         }.otherwise {
-            for (reg <- registerMap.getRegisters) {
+            for (reg <- registerMap.getRegisters)
                 when(addrDecode.io.sel(reg.id)) {
                     io.apb.PRDATA := reg.readCallback(addrDecode.io.addrOut)
                 }
-            }
         }
     }
 
     // Instantiate the TimerInner module
     /** TimerInner module instance */
     val timerInner = Module(new TimerInner(timerParams, formal))
-    timerInner.io.timerInputBundle.en            := en
-    timerInner.io.timerInputBundle.setCount      := setCount
-    timerInner.io.timerInputBundle.prescaler     := prescaler
-    timerInner.io.timerInputBundle.maxCount      := maxCount
-    timerInner.io.timerInputBundle.pwmCeiling    := pwmCeiling
-    timerInner.io.timerInputBundle.setCountValue := setCountValue
+    timerInner.io.timerInputBundle.en                      := en
+    timerInner.io.timerInputBundle.setCount                := setCount
+    timerInner.io.timerInputBundle.prescaler               := prescaler
+    timerInner.io.timerInputBundle.maxCount                := maxCount
+    timerInner.io.timerInputBundle.pwmCeiling              := pwmCeiling
+    timerInner.io.timerInputBundle.setCountValue           := setCountValue
     timerInner.io.timerInputBundle.maxCountEnableInterrupt := maxCountEnableInterrupt
 
     // Connect the TimerInner outputs to the top-level outputs
     io.timerOutput <> timerInner.io.timerOutputBundle
+
+    if (timerParams.coverage)
+        // Cover the entire IO bundle recursively.
+        coverAll(io, "_io")
 }