fixing makefile

Author: nickrallison

.github/workflows/scalafmt.yml

@@ -2,9 +2,9 @@ name: "Synthesis and Results"
 
 on:
   push:
-    branches: ["main"]
+    branches: [ "main" ]
   pull_request:
-    branches: ["main"]
+    branches: [ "main" ]
 
 jobs:
   synth-and-publish:
@@ -186,6 +186,7 @@ jobs:
         run: |
           mkdir -p artifacts
           cp -r out/results artifacts/
+          cp -r out/verilog artifacts/
           # Copy netlists from out/synth
           find out/synth -name "*.v" -exec cp {} artifacts/ \;
           # Copy any verilog from generated/ if needed

.github/workflows/synth_sta.yml

@@ -34,17 +34,11 @@ clean:
 	find . -type f -name "*.synctex.gz" -delete
 	find . -type f -name "*.pdf" -delete
 
-# Generate verilog from the Chisel code
 # Generate verilog from the Chisel code
 verilog:
 	@echo Generating Verilog...
-	@mkdir -p generated
-	@$(SBT) "runMain tech.rocksavage.Main verilog --mode print --module tech.rocksavage.chiselware.uart.Uart --config-class tech.rocksavage.chiselware.uart.UartConfig" | awk '/^\/\/ Generated by CIRCT/,0' > generated/combined_uart.v
-	@echo "Extracting individual modules..."
-	@cd generated && python3 $(shell pwd)/scripts/split_verilog.py combined_uart.v
-	@echo "Verilog files generated successfully!"
-	@ls -l generated/*.v | wc -l | xargs -I{} echo "Total modules generated: {}"
-	
+	@$(SBT) "runMain tech.rocksavage.Main verilog --mode write --module tech.rocksavage.chiselware.uart.Uart --config-class tech.rocksavage.chiselware.uart.UartConfig"
+
 # Run the tests
 test:
 	@echo Running tests...