diff --git a/.github/workflows/ci-build-sw.yml b/.github/workflows/linker-unit-test.yml similarity index 72% rename from .github/workflows/ci-build-sw.yml rename to .github/workflows/linker-unit-test.yml index 3fd5f6e1..ac280fc2 100644 --- a/.github/workflows/ci-build-sw.yml +++ b/.github/workflows/linker-unit-test.yml @@ -18,30 +18,35 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -name: CI Build SW +name: Linker unit testing on: + push: + branches: + - main + - dev pull_request: jobs: - build: - runs-on: ubuntu-22.04 + linker_unit_tests: + runs-on: ubuntu-24.04 permissions: { contents: read } steps: - name: Checkout code - uses: actions/checkout@v4 + uses: actions/checkout@v6 - - name: Install build tools - run: | - sudo apt-get update -qq - sudo apt-get install -y build-essential linux-headers-$(uname -r) libxml2-dev libzmq3-dev libjsoncpp-dev + - name: Setup python + uses: actions/setup-python@v6 + with: + python-version: "3.10" + cache: "pip" - - name: Build hotplug driver - if: ${{ false }} - run: | - cd ${{ github.workspace }}/submodules/pcie-hotplug-drv/ && make + - name: Install required packages + run: pip install -r requirements.txt - - name: Build linker - run: | - cd ${{ github.workspace }}/submodules/v80-vitis-flow && cmake . && make + - name: Run unit tests + run: cd linker && pytest + + - name: Check formatting + run: cd linker && autopep8 -r --diff --exit-code --exclude 'slashkit/resources/*' slashkit/ test/ diff --git a/.github/workflows/vrt-unit-test.yml b/.github/workflows/vrt-unit-test.yml new file mode 100644 index 00000000..d0031344 --- /dev/null +++ b/.github/workflows/vrt-unit-test.yml @@ -0,0 +1,72 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +name: VRT unit testing + +on: + push: + branches: + - main + - dev + pull_request: + +jobs: + vrt_unit_tests: + runs-on: ubuntu-24.04 + permissions: { contents: read } + + steps: + - name: Checkout code + uses: actions/checkout@v6 + with: + submodules: "true" + + - name: Install dependencies + run: | + sudo apt install -y cmake pkg-config ninja-build \ + libxml2-dev libzmq3-dev libjsoncpp-dev zlib1g-dev \ + libsystemd-dev libinih-dev libcli11-dev lcov python3-zmq + + - name: Build and run VRT unit tests + run: | + mkdir vrt/build + cd vrt/build + cmake -DVRT_INCLUDE_VRTD=1 -DVRTD_INCLUDE_LIBSLASH=1 -DVRT_BUILD_TESTS=1 -DENABLE_COVERAGE=1 .. + make unit_tests -j$(nproc) + cd tests && ctest --output-on-failure + + - name: Generate coverage report + run: | + cd vrt/build + lcov --capture --directory . --output-file coverage.info \ + --ignore-errors mismatch --ignore-errors negative + lcov --remove coverage.info \ + '/usr/*' '*/build/_deps/*' '*/vrtd/*' '*/tests/*' \ + --output-file coverage.filtered.info \ + --ignore-errors unused + genhtml coverage.filtered.info --output-directory coverage-report + lcov --list coverage.filtered.info + + - name: Upload coverage report + uses: actions/upload-artifact@v4 + with: + name: vrt-coverage-report + path: vrt/build/coverage-report/ + \ No newline at end of file diff --git a/.github/workflows/vrtd-unit-test.yml b/.github/workflows/vrtd-unit-test.yml new file mode 100644 index 00000000..5d967b60 --- /dev/null +++ b/.github/workflows/vrtd-unit-test.yml @@ -0,0 +1,72 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +name: VRTD unit testing + +on: + push: + branches: + - main + - dev + pull_request: + +jobs: + vrtd_unit_tests: + runs-on: ubuntu-24.04 + permissions: { contents: read } + + steps: + - name: Checkout code + uses: actions/checkout@v6 + with: + submodules: "true" + + - name: Install dependencies + run: | + sudo apt update + sudo apt install -y cmake pkg-config ninja-build \ + libsystemd-dev libinih-dev lcov + + - name: Build and run VRTD unit tests + run: | + mkdir vrt/vrtd/build + cd vrt/vrtd/build + cmake -DVRTD_BUILD_TESTS=1 -DVRTD_INCLUDE_LIBSLASH=1 -DENABLE_COVERAGE=1 .. + make unit_tests -j$(nproc) + export LD_LIBRARY_PATH=$(pwd)/libslash/src/:$LD_LIBRARY_PATH + cd tests && ctest --output-on-failure + + - name: Generate coverage report + run: | + cd vrt/vrtd/build + lcov --capture --directory . --output-file coverage.info \ + --ignore-errors mismatch --ignore-errors negative + lcov --remove coverage.info \ + '/usr/*' '*/build/_deps/*' '*/tests/*' \ + --output-file coverage.filtered.info \ + --ignore-errors unused + genhtml coverage.filtered.info --output-directory coverage-report + lcov --list coverage.filtered.info + + - name: Upload coverage report + uses: actions/upload-artifact@v4 + with: + name: vrtd-coverage-report + path: vrt/vrtd/build/coverage-report/ diff --git a/.gitignore b/.gitignore index c3fc2a99..07e46f38 100644 --- a/.gitignore +++ b/.gitignore @@ -53,5 +53,34 @@ Thumbs.db *~ *.Xil !build_all.sh +!build_bsp.sh .clang-format +.cache +**/linker_results/ +**/linker_results_*/ + +__pycache__/ +*.pyc +.venv/ + +# Kernel module kcompat probe scratch (driver/kcompat/probe.sh) +driver/kcompat/.scratch/ + +# Build files for package +/pbuild/ +/rpmbuild/ +/debian/ + +# Output files for package +/deb/ +/rpm/ + +# VBIN build directories +*.prj + +# Python virtual environment +.venv + +# Python test coverage +.coverage diff --git a/.gitmodules b/.gitmodules index 07ee074b..4a47bcf5 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ [submodule "submodules/qdma_drv"] path = submodules/qdma_drv url = https://github.com/Xilinx/dma_ip_drivers.git -[submodule "submodules/v80-vitis-flow/submodules/aved"] - path = submodules/v80-vitis-flow/submodules/aved +[submodule "AVED"] + path = submodules/AVED url = https://github.com/Xilinx/AVED.git diff --git a/.readthedocs.yaml b/.readthedocs.yaml index ec397586..7a8c7d06 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -24,9 +24,9 @@ version: 2 build: - os: ubuntu-20.04 + os: ubuntu-24.04 tools: - python: "3.8" + python: "3.12" apt_packages: - graphviz @@ -39,4 +39,4 @@ sphinx: python: install: - - requirements: docs/requirements.txt \ No newline at end of file + - requirements: docs/requirements.txt diff --git a/README.md b/README.md index c860e53d..f8727193 100644 --- a/README.md +++ b/README.md @@ -1,47 +1,303 @@ -# SLASH VRT (V80 RunTime) API +# SLASH — Platform for AMD Alveo V80 -This repository contains SLASH, a SmartNIC platform for Alveo V80. SLASH consists of several components: -- card management functionality that layers on top of [AVED](https://github.com/Xilinx/AVED) -- V80 RunTime (VRT): the VRT API implementation, along with examples. -- (upcoming) 200Gbps MAC implementation for network-attached kernels and SmartNIC applications +SLASH is an open-source platform for AMD Alveo V80 FPGA boards. It provides a +complete runtime and development ecosystem for executing FPGA kernels, managing +devices, and transferring data between host and device memory. -> [!WARNING] -> The project was only tested with AMD Vivado & Vitis tools version 2024.2, on Ubuntu 22.04, kernel version 5.15. Please use same versions of tools/kernel. +Key components: -## Dependencies +- **VRT** (V80 RunTime) — C++17 API for kernel execution, buffer management, and device control +- **v80-smi** — command-line tool for board management, programming, and diagnostics +- **slashkit** — Python-based linker that packages HLS kernels into deployable *vrtbin* archives +- **slash** — Linux kernel module and driver stack -- libxml2 -- ZeroMQ (zmq) for emulation & simulation -- jsoncpp for emulation & simulation +## Architecture -To install the dependencies: +SLASH is organized as a layered stack. Each layer has a single responsibility +and communicates with adjacent layers through well-defined interfaces. + +``` +┌─────────────────────────────────────────────┐ +│ User Application │ C++17 +├─────────────────────────────────────────────┤ +│ VRT (libvrt) │ C++17 ─ MIT +├─────────────────────────────────────────────┤ +│ libvrtd++ (C++ RAII wrapper) │ C++20 ─ MIT +├─────────────────────────────────────────────┤ +│ libvrtd (C wire-protocol) │ C11 ─ MIT +├──────────────── AF_UNIX ────────────────────┤ +│ vrtd (daemon) │ C11 ─ MIT +├─────────────────────────────────────────────┤ +│ libslash (driver wrapper) │ C ─ MIT +├─────────────────────────────────────────────┤ +│ Linux kernel module (slash) │ C ─ GPLv2 +├─────────────────────────────────────────────┤ +│ AMD Alveo V80 Hardware │ +└─────────────────────────────────────────────┘ +``` + +Two additional components sit alongside the stack: + +- **v80-smi** — CLI for listing, programming, resetting, and validating V80 boards. +- **slashkit** — links HLS kernels into *vrtbin* archives for deployment. + +## Repository Layout + +| Directory | Component | Description | +|-----------|-----------|-------------| +| [`vrt/`](vrt/) | VRT | C++17 runtime library — [README](vrt/README.md) | +| [`driver/`](driver/) | Kernel module + libslash | Linux driver and C wrapper — [README](driver/libslash/README.md) | +| [`smi/`](smi/) | v80-smi | CLI management tool — [README](smi/README.md) | +| [`linker/`](linker/) | slashkit | Python-based kernel linker | +| [`cmake/`](cmake/) | CMake modules | Build system integration — [README](cmake/README.md) | +| [`examples/`](examples/) | Examples | Demo projects — [README](examples/README.md) | +| [`docs/`](docs/) | Documentation | Sphinx / ReadTheDocs site | +| [`packaging/`](packaging/) | Packages | Debian and RPM packaging | +| [`scripts/`](scripts/) | Scripts | Build, package, and test helpers | + +## Platform Modes + +VRT supports three execution platforms. The same application source code runs +on all three — the platform is determined by the vrtbin file, not by the +application. + +| Platform | Transport | Build Target | Use Case | +|----------|-----------|-------------|----------| +| **Hardware** | PCIe BAR + QDMA | `hw` | Production runs on a physical V80 board | +| **Emulation** | ZeroMQ IPC to C-model | `emu` | Functional verification without FPGA hardware | +| **Simulation** | Verilog register map | `sim` | Cycle-accurate RTL simulation | + +Each example provides three vrtbin targets via CMake: + +```cmake +add_vbin(TARGET "axilite_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "axilite_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "axilite_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +``` + +## Prerequisites + +**System requirements:** + +- Ubuntu LTS 22.04+; RHEL 9+ or compatible (other distributions may work as well but have not been tested) +- AMD Vivado & Vitis HLS 2025.1 — source the environment before building or + running against emulation/simulation: + + ```bash + source /settings64.sh + source /settings64.sh + ``` + + For `csh`/`tcsh` shells, use `settings64.csh` instead. Using versions other + than 2025.1 may cause breakage. + +**Library dependencies:** ```bash -sudo apt install libxml2-dev libzmq3-dev libjsoncpp-dev xvfb +sudo apt install cmake pkg-config ninja-build \ + libxml2-dev libzmq3-dev libjsoncpp-dev zlib1g-dev \ + libsystemd-dev libinih-dev libcli11-dev \ + linux-headers-$(uname -r) ``` -### Submodules +**Submodules:** + +SLASH depends on [AVED](https://github.com/Xilinx/AVED) and [QDMA](https://github.com/Xilinx/dma_ip_drivers): -SLASH depends on [AVED](https://github.com/Xilinx/AVED) and [QDMA](https://github.com/Xilinx/dma_ip_drivers) which can be pulled from git using: ```bash git submodule update --init --recursive ``` -## Deployment -In order to build and deploy all necessary software for this project to work, follow the steps shown in the [deployment instructions](deploy/README.md). +## Quick Start + +### 1. Build the stack + +Components must be built in dependency order: + +```bash +# Kernel module +cd driver && make && sudo insmod slash.ko && cd .. + +# libslash (kernel module client library) +cd driver/libslash && cmake -S . -B build -G Ninja && cmake --build build && sudo cmake --install build && cd ../.. + +# vrtd (daemon + client libraries) +cd vrt/vrtd && cmake -S . -B build -G Ninja && cmake --build build && sudo cmake --install build && cd ../.. + +# VRT (runtime library) +cd vrt && cmake -S . -B build -G Ninja && cmake --build build && sudo cmake --install build && cd .. + +# v80-smi (CLI tool) +cd smi && cmake -S . -B build -G Ninja && cmake --build build && sudo cmake --install build && cd .. +``` + +### 2. Start the daemon + +```bash +sudo vrtd # manual +sudo systemctl enable --now vrtd # production (systemd) +``` + +### 3. Verify + +```bash +v80-smi list +``` + +All four readiness checks (PF0, PF1, PF2, VRTD) should pass for each board. + +### 4. Build and run an example + +```bash +cd examples/00_axilite +cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON +cmake --build build + +# Build FPGA artefacts (requires Vivado/Vitis) +cmake --build build --target hls # compile HLS kernels +cmake --build build --target axilite_hw # link into a hardware vrtbin + +# Run +./build/00_axilite build/axilite_hw.vbin +``` + +Set these environment variables before running: + +```bash +source /settings64.sh +source /settings64.sh +``` + +## Code Example + +A minimal VRT application: + +```cpp +#include +#include +#include + +int main() { + // Open device and program FPGA + vrt::Device device("03:00", "design.vrtbin"); + + // Get kernel handle + vrt::Kernel increment(device, "increment_0"); + + // Allocate device buffer using the kernel's port configuration + vrt::Buffer buffer(device, 1024, increment.argMemoryConfig("in")); + + // Fill host-side data + for (size_t i = 0; i < 1024; ++i) + buffer[i] = static_cast(i); + + // Transfer host → device + buffer.sync(vrt::SyncType::HOST_TO_DEVICE); + + // Launch kernel + increment.setArg(0, 1024); + increment.setArg(1, buffer); + increment.start(); + increment.wait(); + + // Transfer device → host + buffer.sync(vrt::SyncType::DEVICE_TO_HOST); + + // Read result register + uint32_t result = increment.read(0x18); + + device.cleanup(); + return 0; +} +``` + +## v80-smi Commands + +| Command | Description | +|---------|-------------| +| `v80-smi version` | Print build version | +| `v80-smi list` | Enumerate V80 boards with readiness checks (`-l` long, `-s` sensors, `-j` JSON) | +| `v80-smi inspect ` | Display vrtbin metadata (platform, clock, kernels, memory map) | +| `v80-smi query -d ` | Display metadata of the currently loaded design on a device | +| `v80-smi program -d ` | Program a V80 device with a vrtbin file | +| `v80-smi reset -d ` | Hardware-reset a board (PCIe secondary bus reset) | +| `v80-smi validate -d ` | Run memory integrity and bandwidth tests (HBM and DDR) | + +See the full [v80-smi reference](smi/README.md) for details and examples. + +## Memory Model + +The V80 board has two memory subsystems: + +| Memory | Selection | Capacity | Notes | +|--------|-----------|----------|-------| +| **DDR** | `MemoryRangeType::DDR` | Large, single address space | Bulk storage; referenced as `DDR0` in linker config | +| **HBM** (port) | `MemoryRangeType::HBM` + port | 64 pseudo-channels (HBM0–HBM63) | Explicit channel; high aggregate bandwidth | +| **HBM** (VNOC) | `MemoryRangeType::HBM_VNOC` | Auto-distributed across channels | No manual channel management | + +The recommended approach is to derive memory configuration from the kernel metadata +rather than hardcoding types: + +```cpp +vrt::Buffer buf(device, size, kernel.argMemoryConfig("in")); +``` + +This ensures the buffer allocation always matches the linker configuration. + +## Examples + +| ID | Feature | Notes | +|----|---------|-------| +| 00 | Linking, AXI-Lite control | | +| 01 | Kernels with AXI-MM interfaces | | +| 02 | Freerunning streaming kernels | | +| 03 | Controlling multiple V80s | Uses vrtbin from example 00 | +| 04 | Frequency targets | | +| 05 | Memory performance test | Instantiates maximum number of kernels | + +See the [examples README](examples/README.md) for build and run instructions. + +## Component Documentation + +Each component has its own README with detailed information: + +- **[VRT Runtime](vrt/README.md)** — API overview, classes, building, and platform support +- **[libslash](driver/libslash/README.md)** — driver wrapper, device node API, mock mode +- **[v80-smi](smi/README.md)** — all commands with usage examples +- **[CMake Modules](cmake/README.md)** — BuildHLS, FindVivado, FindVitis, SlashTools reference +- **[VRT API Docs](vrt/doc/README.md)** — Doxygen generation instructions +- **[vrtd Daemon](vrt/vrtd/README.md)** — daemon coding guidelines and standards +- **[Examples](examples/README.md)** — build recipes and run instructions for all examples + +## Full Documentation + +The complete documentation is published at **[slash-fpga.readthedocs.io](https://slash-fpga.readthedocs.io/)** and covers: + +- **Tutorials** — getting started, writing kernels, buffers and memory, emulation/simulation, platform setup, device management, vrtd configuration +- **How-To Guides** — multiple boards, clock frequency, streaming chains, memory benchmarking, building from source, CMake modules, vrtbin inspection, mock mode +- **API Reference** — VRT, libslash, libvrtd, libvrtdpp, vrtd, v80-smi, CMake modules +- **Architecture** — stack overview, memory model, PCIe topology, platform modes, vrtbin format + +## Known Limitations + +- HLS arguments should not be Verilog or VHDL keywords (e.g. `in`, `out`). Some issues may appear in the linker with this configuration. +- In emulation, HLS kernels must include at least one AXI4-Lite interface to work. +- A maximum of 15 kernels can be instantiated in the current version of the linker. This will be fixed in future versions. +- Freerunning streaming kernel chains are not supported in emulation. -## How to build VRT API documentation +## Contributing -Follow the instructions in the [API documentation README](vrt/doc/README.md). +We welcome contributions. Please see [CONTRIBUTING.md](CONTRIBUTING.md) for: -## How to build the examples +- Issue reporting guidelines +- Pull request process (target the `dev` branch) +- Developer Certificate of Origin (DCO) requirements -A [README](examples/README.md) file can be found in the examples directory. Please follow the instruction given there to proceed. +## License -## Known limitations -- HLS arguments should not be Verilog or VHDL keywords (eg. `in`, `out` so on). Some issues may appear in the linker with this configuration. -- In emulation, HLS kernels must include at least one axi4lite interface to work. -- In the current version of the [linker](submodules/v80-vitis-flow), a maximum number of 15 kernels can be instantiated. This will be fixed in future versions. +| Component | License | +|-----------|---------| +| Linux kernel driver | GPLv2 | +| All user-space code | MIT | -## Notes -All the hardware examples are built using the Segmented Configuration flow. +See [LICENSE](LICENSE) for the full text. diff --git a/cmake/BuildHLS.cmake b/cmake/BuildHLS.cmake new file mode 100644 index 00000000..97803e24 --- /dev/null +++ b/cmake/BuildHLS.cmake @@ -0,0 +1,198 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +include_guard(GLOBAL) + +function(build_hls) + set(oneValueArgs TARGET CPP CFG DEVICE OUT_DIR) + cmake_parse_arguments(BHL "" "${oneValueArgs}" "" ${ARGN}) + + if(NOT BHL_TARGET) + message(FATAL_ERROR "build_hls(): TARGET is required") + endif() + if(NOT BHL_CPP OR NOT BHL_CFG) + message(FATAL_ERROR "build_hls(): CPP and CFG are required") + endif() + if(NOT BHL_DEVICE) + message(FATAL_ERROR "build_hls(): DEVICE is required (e.g., xcv80-lsva4737-2MHP-e-S)") + endif() + + get_filename_component(_cpp "${BHL_CPP}" REALPATH) + get_filename_component(_cfg "${BHL_CFG}" REALPATH) + + if(NOT EXISTS "${_cpp}") + message(FATAL_ERROR "build_hls(): CPP not found: '${_cpp}'") + endif() + if(NOT EXISTS "${_cfg}") + message(FATAL_ERROR "build_hls(): CFG not found: '${_cfg}'") + endif() + + if("${BHL_OUT_DIR}" STREQUAL "") + set(BHL_OUT_DIR "${CMAKE_CURRENT_BINARY_DIR}") + endif() + + get_filename_component(_stem "${_cpp}" NAME_WE) + set(_build_dir "${BHL_OUT_DIR}/build_${_stem}.${BHL_DEVICE}") + set(_component_xml "${_build_dir}/hls/impl/ip/component.xml") + # Copy the cfg next to the build outputs so relative paths inside the cfg keep working. + set(_cfg_local "${_build_dir}/${_stem}.cfg") + file(MAKE_DIRECTORY "${_build_dir}") + + find_program(VPP_EXECUTABLE NAMES v++) + if(NOT VPP_EXECUTABLE) + message(FATAL_ERROR "build_hls(): v++ not found. Ensure Vitis is installed and v++ is on PATH.") + endif() + + find_program(VITIS_RUN_EXECUTABLE NAMES vitis-run) + if(NOT VITIS_RUN_EXECUTABLE) + message(FATAL_ERROR "build_hls(): vitis-run not found. Ensure Vitis is installed and vitis-run is on PATH.") + endif() + + add_custom_command( + OUTPUT "${_component_xml}" + COMMAND "${CMAKE_COMMAND}" -E make_directory "${_build_dir}" + COMMAND "${CMAKE_COMMAND}" -E copy_if_different "${_cpp}" "${_build_dir}/${_stem}.cpp" + COMMAND "${CMAKE_COMMAND}" -E copy_if_different "${_cfg}" "${_cfg_local}" + COMMAND "${VPP_EXECUTABLE}" -c --mode hls --config "${_cfg_local}" --work_dir . + COMMAND "${VITIS_RUN_EXECUTABLE}" --mode hls --package --config "${_cfg_local}" --work_dir . + WORKING_DIRECTORY "${_build_dir}" + DEPENDS "${_cpp}" "${_cfg}" + COMMENT "HLS build: ${_stem}" + VERBATIM + ) + + add_custom_target("${BHL_TARGET}" DEPENDS "${_component_xml}") + set_property(TARGET "${BHL_TARGET}" PROPERTY HLS_BUILD_DIR "${_build_dir}") + set_property(TARGET "${BHL_TARGET}" PROPERTY HLS_COMPONENT_XML "${_component_xml}") + set("${BHL_TARGET}_BUILD_DIR" "${_build_dir}" PARENT_SCOPE) + set("${BHL_TARGET}_COMPONENT_XML" "${_component_xml}" PARENT_SCOPE) +endfunction() + +function(build_hls_dir) + set(oneValueArgs TARGET ROOT DEVICE OUT_DIR OUT_IP_REPO OUT_KERNELS) + set(multiValueArgs KERNELS) + cmake_parse_arguments(BHLD "" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + if(NOT BHLD_TARGET) + message(FATAL_ERROR "build_hls_dir(): TARGET is required") + endif() + if(NOT BHLD_ROOT) + message(FATAL_ERROR "build_hls_dir(): ROOT is required") + endif() + if(NOT BHLD_DEVICE) + message(FATAL_ERROR "build_hls_dir(): DEVICE is required") + endif() + if(NOT BHLD_KERNELS) + message(FATAL_ERROR "build_hls_dir(): KERNELS is required (e.g., KERNELS increment accumulate)") + endif() + + get_filename_component(_root "${BHLD_ROOT}" REALPATH) + if(NOT IS_DIRECTORY "${_root}") + message(FATAL_ERROR "build_hls_dir(): ROOT is not a directory: '${_root}'") + endif() + + if("${BHLD_OUT_DIR}" STREQUAL "") + set(BHLD_OUT_DIR "${CMAKE_CURRENT_BINARY_DIR}/${BHLD_TARGET}") + endif() + file(MAKE_DIRECTORY "${BHLD_OUT_DIR}") + + set(_kernel_targets "") + set(_kernel_xmls "") + + foreach(k IN LISTS BHLD_KERNELS) + set(_cpp "${_root}/${k}.cpp") + set(_cfg "${_root}/${k}.cfg") + + if(NOT EXISTS "${_cpp}") + message(FATAL_ERROR "build_hls_dir(): CPP not found for kernel '${k}': '${_cpp}'") + endif() + if(NOT EXISTS "${_cfg}") + message(FATAL_ERROR "build_hls_dir(): CFG not found for kernel '${k}': '${_cfg}'") + endif() + + set(_t "${BHLD_TARGET}_${k}") + string(REGEX REPLACE "[^A-Za-z0-9_]+" "_" _t "${_t}") + + build_hls( + TARGET "${_t}" + CPP "${_cpp}" + CFG "${_cfg}" + DEVICE "${BHLD_DEVICE}" + OUT_DIR "${BHLD_OUT_DIR}" + ) + + list(APPEND _kernel_targets "${_t}") + list(APPEND _kernel_xmls "${${_t}_COMPONENT_XML}") + endforeach() + + add_custom_target("${BHLD_TARGET}" DEPENDS ${_kernel_targets}) + + if(NOT "${BHLD_OUT_IP_REPO}" STREQUAL "") + set("${BHLD_OUT_IP_REPO}" "${BHLD_OUT_DIR}" PARENT_SCOPE) + endif() + if(NOT "${BHLD_OUT_KERNELS}" STREQUAL "") + set("${BHLD_OUT_KERNELS}" "${_kernel_xmls}" PARENT_SCOPE) + endif() +endfunction() + +function(build_hls_clean) + set(oneValueArgs TARGET DEVICE ROOT) + set(multiValueArgs EXTRA_GLOBS) + cmake_parse_arguments(BHLC "" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + if(NOT BHLC_TARGET) + message(FATAL_ERROR "build_hls_clean(): TARGET is required") + endif() + if(NOT BHLC_DEVICE) + message(FATAL_ERROR "build_hls_clean(): DEVICE is required") + endif() + + if("${BHLC_ROOT}" STREQUAL "") + set(BHLC_ROOT "${CMAKE_CURRENT_LIST_DIR}") + endif() + + set(_patterns + "${BHLC_ROOT}/build_*.${BHLC_DEVICE}" + "${BHLC_ROOT}/*.log" + "${BHLC_ROOT}/.Xil" + "${BHLC_ROOT}/CMakeCache.txt" + "${BHLC_ROOT}/CMakeFiles" + "${BHLC_ROOT}/cmake_install.cmake" + "${BHLC_ROOT}/Makefile" + "${BHLC_ROOT}/*_rewrite_cfg.cmake" + "${BHLC_ROOT}/${BHLC_TARGET}.cmake" + ) + if(BHLC_EXTRA_GLOBS) + list(APPEND _patterns ${BHLC_EXTRA_GLOBS}) + endif() + + set(_clean_script "${CMAKE_CURRENT_BINARY_DIR}/${BHLC_TARGET}.cmake") + set(_script "message(STATUS \"Cleaning HLS build outputs\")\n") + foreach(p IN LISTS _patterns) + string(APPEND _script "file(GLOB _matches \"${p}\")\n") + string(APPEND _script "if(_matches)\n file(REMOVE_RECURSE \${_matches})\nendif()\n") + endforeach() + file(WRITE "${_clean_script}" "${_script}") + + add_custom_target("${BHLC_TARGET}" + COMMAND "${CMAKE_COMMAND}" -P "${_clean_script}" + COMMENT "Cleaning HLS build outputs" + ) +endfunction() diff --git a/cmake/CMakeLists.txt b/cmake/CMakeLists.txt new file mode 100644 index 00000000..44d88e16 --- /dev/null +++ b/cmake/CMakeLists.txt @@ -0,0 +1,41 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.16) +project(SlashTools LANGUAGES NONE) + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) + +configure_package_config_file( + "${CMAKE_CURRENT_SOURCE_DIR}/SlashToolsConfig.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/SlashToolsConfig.cmake" + INSTALL_DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/SlashTools" +) + +install(FILES + "${CMAKE_CURRENT_BINARY_DIR}/SlashToolsConfig.cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/SlashTools.cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/BuildHLS.cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/FindVivado.cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/FindVitis.cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/CheckSlashInstall.cmake" + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/SlashTools" +) diff --git a/cmake/CheckSlashInstall.cmake b/cmake/CheckSlashInstall.cmake new file mode 100644 index 00000000..fa1a991b --- /dev/null +++ b/cmake/CheckSlashInstall.cmake @@ -0,0 +1,41 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +if(NOT DEFINED INSTALL_DIR OR "${INSTALL_DIR}" STREQUAL "") + set(INSTALL_DIR "/opt/amd/slash") +endif() + +set(_required_files + "static_shell_service_layer.dcp" + "static_shell_slash.dcp" + "amd_v80_gen5x8_25.1.pdi" + "top_wrapper_routed_bb.dcp" +) + +set(_missing "") +foreach(_f IN LISTS _required_files) + if(NOT EXISTS "${INSTALL_DIR}/${_f}") + list(APPEND _missing "${INSTALL_DIR}/${_f}") + endif() +endforeach() + +if(_missing) + message(FATAL_ERROR "install was not run. ask your admin to run install first") +endif() diff --git a/cmake/FindVitis.cmake b/cmake/FindVitis.cmake new file mode 100644 index 00000000..ee58ba74 --- /dev/null +++ b/cmake/FindVitis.cmake @@ -0,0 +1,40 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +find_program(VITIS_BINARY + NAMES vitis + PATHS ${VITIS_ROOT_DIR} ENV XILINX_VITIS ENV VITIS_HOME ENV VITIS + PATH_SUFFIXES bin +) + +if(NOT VITIS_BINARY) + message(FATAL_ERROR "Vitis not found. Set XILINX_VITIS or VITIS_HOME (or add vitis to PATH).") +endif() + +get_filename_component(_vitis_bin_dir "${VITIS_BINARY}" DIRECTORY) +get_filename_component(VITIS_ROOT_DIR "${_vitis_bin_dir}" DIRECTORY) + +set(VITIS_INCLUDE_DIR "${VITIS_ROOT_DIR}/include") +if(NOT EXISTS "${VITIS_INCLUDE_DIR}") + message(FATAL_ERROR "Vitis include dir not found: ${VITIS_INCLUDE_DIR}") +endif() + +set(VITIS_FOUND TRUE) +message(STATUS "Found Vitis at ${VITIS_ROOT_DIR}.") diff --git a/cmake/FindVivado.cmake b/cmake/FindVivado.cmake new file mode 100644 index 00000000..e1e5366f --- /dev/null +++ b/cmake/FindVivado.cmake @@ -0,0 +1,34 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +find_path(VIVADO_PATH + NAMES vivado + PATHS ${VIVADO_ROOT_DIR} ENV XILINX_VIVADO + PATH_SUFFIXES bin +) + +if(NOT EXISTS ${VIVADO_PATH}) + message(FATAL_ERROR "Vivado not found.") +else() + get_filename_component(VIVADO_ROOT_DIR ${VIVADO_PATH} DIRECTORY) + set(VIVADO_FOUND TRUE) + set(VIVADO_BINARY ${VIVADO_ROOT_DIR}/bin/vivado) + message(STATUS "Found Vivado at ${VIVADO_ROOT_DIR}.") +endif() \ No newline at end of file diff --git a/cmake/README.md b/cmake/README.md new file mode 100644 index 00000000..01b23b3c --- /dev/null +++ b/cmake/README.md @@ -0,0 +1,264 @@ +# SLASH CMake Modules + +Build-system support for HLS kernel compilation, FPGA vbin linking, +and AMD tool discovery. + +| Module | Purpose | +|----------------------------|------------------------------------------------------| +| `SlashTools.cmake` | SLASH linker integration (`add_vbin`) | +| `BuildHLS.cmake` | HLS kernel compilation (`build_hls`, `build_hls_dir`, `build_hls_clean`) | +| `FindVivado.cmake` | Locate AMD Vivado installation | +| `FindVitis.cmake` | Locate AMD Vitis HLS installation | +| `CheckSlashInstall.cmake` | Validate SLASH hardware files are installed | + +## Using the modules + +**Installed mode** (after `cmake --install`): + +```cmake +find_package(SlashTools REQUIRED) +``` + +Modules are installed to `/lib/cmake/SlashTools/`. +`find_package(SlashTools)` automatically brings in `BuildHLS`, +`FindVivado`, and `FindVitis`. + +**Source-tree mode** (development against local repo): + +```cmake +list(APPEND CMAKE_MODULE_PATH "${SLASH_REPO_ROOT}/cmake") +include(SlashTools) +``` + +## Module reference + +### SlashTools — `add_vbin()` + +Links HLS kernel IP into a vbin file using the SLASH linker. + +```cmake +add_vbin( + TARGET + PLATFORM + CFG + KERNELS [kernel2.xml ...] +) +``` + +| Parameter | Required | Description | +|------------|----------|--------------------------------------------| +| `TARGET` | yes | Name of the CMake target to create | +| `PLATFORM` | yes | Target platform: `hw`, `sim`, or `emu` | +| `CFG` | yes | Path to the linker configuration file | +| `KERNELS` | yes | List of kernel component.xml files to link | + +**Output:** `${CMAKE_CURRENT_BINARY_DIR}/.vbin` + +**Linker detection** (two modes, tried in order): + +1. **Installed** — finds `slashkit` on PATH +2. **Source tree** — uses `SLASH_REPO_ROOT` (or auto-detects from + `../linker/src/main.py` relative to this directory). Requires + Python 3. + +Variables set after loading: + +| Variable | Description | +|-----------------------|-------------------------------------------| +| `SLASH_FOUND` | `TRUE` when SlashTools is ready | +| `SLASHKIT_EXECUTABLE` | Path to `slashkit` (installed mode) | +| `SLASH_REPO_ROOT` | Path to SLASH repo root (source mode) | +| `VIVADO_BINARY` | Path to `vivado` (from FindVivado) | +| `VITIS_ROOT_DIR` | Path to Vitis root (from FindVitis) | + +### BuildHLS — `build_hls()`, `build_hls_dir()`, `build_hls_clean()` + +Compiles HLS kernels using `v++` and `vitis-run`. Both executables +must be on PATH. + +#### `build_hls()` — single kernel + +```cmake +build_hls( + TARGET + CPP + CFG + DEVICE + [OUT_DIR ] +) +``` + +| Parameter | Required | Description | +|-----------|----------|------------------------------------------------------| +| `TARGET` | yes | CMake target name | +| `CPP` | yes | HLS C++ source file | +| `CFG` | yes | Vitis HLS configuration file | +| `DEVICE` | yes | FPGA part (e.g. `xcv80-lsva4737-2MHP-e-S`) | +| `OUT_DIR` | no | Output directory (default: `CMAKE_CURRENT_BINARY_DIR`) | + +Sets target properties `HLS_BUILD_DIR` and `HLS_COMPONENT_XML`, and +parent-scope variables `${TARGET}_BUILD_DIR` and +`${TARGET}_COMPONENT_XML`. + +#### `build_hls_dir()` — batch build + +```cmake +build_hls_dir( + TARGET + ROOT + DEVICE + KERNELS [kernel2 ...] + [OUT_DIR ] + [OUT_IP_REPO ] + [OUT_KERNELS ] +) +``` + +For each kernel name `K`, expects `ROOT/K.cpp` and `ROOT/K.cfg`. +Creates individual build targets and a parent target that depends on +all of them. + +| Parameter | Required | Description | +|--------------|----------|--------------------------------------------------| +| `TARGET` | yes | Parent CMake target name | +| `ROOT` | yes | Directory containing `.cpp` and `.cfg` | +| `DEVICE` | yes | FPGA part name | +| `KERNELS` | yes | List of kernel names | +| `OUT_DIR` | no | Output directory | +| `OUT_IP_REPO`| no | Variable to receive the IP repository path | +| `OUT_KERNELS`| no | Variable to receive the list of component.xml files | + +#### `build_hls_clean()` — remove build artifacts + +```cmake +build_hls_clean( + TARGET + DEVICE + [ROOT ] + [EXTRA_GLOBS ...] +) +``` + +Creates a target that removes `build_*.DEVICE` directories, log files, +`.Xil`, and CMake cache artifacts. + +### FindVivado + +Locates the AMD Vivado installation. + +```cmake +find_package(Vivado REQUIRED) +``` + +Search order: + +1. `VIVADO_ROOT_DIR` CMake variable +2. `XILINX_VIVADO` environment variable +3. System `PATH` + +| Variable | Description | +|-------------------|----------------------------------| +| `VIVADO_FOUND` | `TRUE` if Vivado was found | +| `VIVADO_PATH` | Directory containing `vivado` | +| `VIVADO_ROOT_DIR` | Vivado installation root | +| `VIVADO_BINARY` | Full path to `vivado` executable | + +### FindVitis + +Locates the AMD Vitis HLS installation. + +```cmake +find_package(Vitis REQUIRED) +``` + +Search order: + +1. `VITIS_ROOT_DIR` CMake variable +2. `XILINX_VITIS` environment variable +3. `VITIS_HOME` environment variable +4. `VITIS` environment variable +5. System `PATH` + +| Variable | Description | +|---------------------|---------------------------------------------| +| `VITIS_FOUND` | `TRUE` if Vitis was found | +| `VITIS_BINARY` | Full path to `vitis` executable | +| `VITIS_ROOT_DIR` | Vitis installation root | +| `VITIS_INCLUDE_DIR` | `${VITIS_ROOT_DIR}/include` (validated) | + +### CheckSlashInstall + +Validates that SLASH hardware files are installed. + +```cmake +include(CheckSlashInstall) +``` + +Checks for four required files in `INSTALL_DIR` (default +`/opt/amd/slash`): + +- `static_shell_service_layer.dcp` +- `static_shell_slash.dcp` +- `amd_v80_gen5x8_25.1.pdi` +- `top_wrapper_routed_bb.dcp` + +Override the install path: + +```cmake +set(INSTALL_DIR "/custom/path") +include(CheckSlashInstall) +``` + +## Typical integration + +```cmake +cmake_minimum_required(VERSION 3.20) +project(my_v80_project) + +option(SLASH_USE_REPO "Build against local SLASH repo" OFF) + +if(SLASH_USE_REPO) + set(SLASH_REPO_ROOT "/path/to/SLASH") + list(APPEND CMAKE_MODULE_PATH "${SLASH_REPO_ROOT}/cmake") + include(SlashTools) +else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) +endif() + +set(DEVICE "xcv80-lsva4737-2MHP-e-S") + +# Build HLS kernels +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS increment accumulate + OUT_KERNELS _KERNEL_XMLS +) + +# Link into a vbin +add_vbin( + TARGET my_design_hw + PLATFORM hw + CFG "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg" + KERNELS ${_KERNEL_XMLS} +) +``` + +## File listing + +``` +cmake/ + SlashTools.cmake Linker integration (add_vbin) + BuildHLS.cmake HLS kernel build functions + FindVivado.cmake Vivado tool finder + FindVitis.cmake Vitis HLS tool finder + CheckSlashInstall.cmake Installation validator + SlashToolsConfig.cmake.in Package config template + CMakeLists.txt Module installation +``` + +## License + +MIT. See the license header in each `.cmake` file for the full text. diff --git a/cmake/SlashTools.cmake b/cmake/SlashTools.cmake new file mode 100644 index 00000000..2901def5 --- /dev/null +++ b/cmake/SlashTools.cmake @@ -0,0 +1,118 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +include_guard(GLOBAL) + +# Make FindVivado.cmake and FindVitis.cmake discoverable from the same directory +list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}") + +# Include BuildHLS so that find_package(SlashTools) provides everything +include("${CMAKE_CURRENT_LIST_DIR}/BuildHLS.cmake") + +find_package(Vivado REQUIRED) + +# --- Locate the SLASH linker --- +# Two modes: +# 1. Installed: slashkit executable on PATH (preferred) +# 2. Source tree: SLASH_REPO_ROOT points to the repository root +set(_SLASH_TOOLS_USE_INSTALLED FALSE) +set(_SLASH_TOOLS_USE_REPO FALSE) + +find_program(SLASHKIT_EXECUTABLE NAMES slashkit) +if(SLASHKIT_EXECUTABLE) + set(_SLASH_TOOLS_USE_INSTALLED TRUE) + message(STATUS "SlashTools: Found installed slashkit at ${SLASHKIT_EXECUTABLE}") +endif() + +if(NOT DEFINED SLASH_REPO_ROOT) + # Try to detect if we are in the source tree + get_filename_component(_slash_tools_candidate_root "${CMAKE_CURRENT_LIST_DIR}/.." REALPATH) + if(EXISTS "${_slash_tools_candidate_root}/linker/slashkit/__main__.py") + set(SLASH_REPO_ROOT "${_slash_tools_candidate_root}") + endif() +endif() + +if(DEFINED SLASH_REPO_ROOT AND EXISTS "${SLASH_REPO_ROOT}/linker/slashkit/__main__.py") + set(_SLASH_TOOLS_USE_REPO TRUE) + set(SLASH_LINKER_DIR "${SLASH_REPO_ROOT}/linker") + find_package(Python3 REQUIRED COMPONENTS Interpreter) + message(STATUS "SlashTools: Found SLASH repo at ${SLASH_REPO_ROOT}") +endif() + +if(NOT _SLASH_TOOLS_USE_INSTALLED AND NOT _SLASH_TOOLS_USE_REPO) + message(FATAL_ERROR + "SlashTools: Cannot find the SLASH linker. Either:\n" + " - Install the slashkit package (provides /usr/bin/slashkit), or\n" + " - Set SLASH_REPO_ROOT to the SLASH repository root.") +endif() + +set(SLASH_FOUND TRUE) + +function(add_vbin) + set(oneValueArgs TARGET CFG PLATFORM) + set(multiValueArgs KERNELS) + cmake_parse_arguments(SLASH_VBIN "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN}) + + foreach(req TARGET CFG PLATFORM KERNELS) + if("${SLASH_VBIN_${req}}" STREQUAL "") + message(FATAL_ERROR "add_vbin: ${req} is required") + endif() + endforeach() + + set(SLASH_VBIN_FILE "${CMAKE_CURRENT_BINARY_DIR}/${SLASH_VBIN_TARGET}.vbin") + + if(_SLASH_TOOLS_USE_REPO) + # Source-tree mode: invoke the slashkit package as a module from the + # linker directory so that `import slashkit` resolves to ./slashkit/. + if(DEFINED Python3_EXECUTABLE AND NOT "${Python3_EXECUTABLE}" STREQUAL "") + set(_py "${Python3_EXECUTABLE}") + else() + set(_py "python3") + endif() + + add_custom_command( + OUTPUT "${SLASH_VBIN_FILE}" + COMMAND "${_py}" "-m" "slashkit" "link" + "-c" "${SLASH_VBIN_CFG}" + "-p" "${SLASH_VBIN_PLATFORM}" + "-o" "${SLASH_VBIN_FILE}" + "-k" ${SLASH_VBIN_KERNELS} + "--vivado" "${VIVADO_BINARY}" + BYPRODUCTS "${SLASH_VBIN_FILE}.prj" + DEPENDS "${SLASH_VBIN_CFG}" "${SLASH_VBIN_KERNELS}" + WORKING_DIRECTORY "${SLASH_LINKER_DIR}" + ) + else() + # Installed mode: invoke the slashkit wrapper + add_custom_command( + OUTPUT "${SLASH_VBIN_FILE}" + COMMAND "${SLASHKIT_EXECUTABLE}" "link" + "-c" "${SLASH_VBIN_CFG}" + "-p" "${SLASH_VBIN_PLATFORM}" + "-o" "${SLASH_VBIN_FILE}" + "-k" ${SLASH_VBIN_KERNELS} + "--vivado" "${VIVADO_BINARY}" + BYPRODUCTS "${SLASH_VBIN_FILE}.prj" + DEPENDS "${SLASH_VBIN_CFG}" "${SLASH_VBIN_KERNELS}" + ) + endif() + + add_custom_target("${SLASH_VBIN_TARGET}" DEPENDS "${SLASH_VBIN_FILE}") +endfunction() diff --git a/cmake/SlashToolsConfig.cmake.in b/cmake/SlashToolsConfig.cmake.in new file mode 100644 index 00000000..d20d7e99 --- /dev/null +++ b/cmake/SlashToolsConfig.cmake.in @@ -0,0 +1,24 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +@PACKAGE_INIT@ + +list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}") +include("${CMAKE_CURRENT_LIST_DIR}/SlashTools.cmake") diff --git a/deploy/README.md b/deploy/README.md deleted file mode 100644 index f1457728..00000000 --- a/deploy/README.md +++ /dev/null @@ -1,165 +0,0 @@ -# SLASH components deployment - -In order to deploy compute kernels on the SLASH platform, a few steps are necessary. - -- Apply the AVED patch to the repository -- Build the AVED software stack -- Install the AVED software stack -- Build the VRT software stack -- Install the VRT software stack -- Build and install the QDMA driver - -## Apply the AVED patch to the repository - -In order to apply the AVED patch to the repository, run the following commands: - -```bash -cd /submodules/v80-vitis-flow/submodules/aved/ -git apply ../../../../deploy/aved.patch -``` - -## Create the base PDI for segmented configuration - -In order to build the base PDI for segmented configuration, run the following commands: -```bash -cd /deploy/base_pdi -python3 build.py --platform compute -``` -This will take a few hours. - -## Build the AVED software stack -In order to build the AVED software stack, run the following commands: - -```bash -cd /submodules/v80-vitis-flow/submodules/aved/sw/AMI/ -./scripts/gen_package.py -``` - -## Install the AVED software stack - -The previous commands generate a directory, called `output`. Inside of that directory, a new directory is created, with the name `yyyy-mm-dd-hh-mm-ss`. Run the following commands: - -```bash -cd /submodules/v80-vitis-flow/submodules/aved/sw/AMI/output/yyyy-mm-dd-hh-mm-ss -sudo apt install ./ami___.deb -``` -This should install the AVED software stack. To verify the install was correct, run: - -```bash -ami_tool overview - -AMI -------------------------------------------------------------- -Version | 2.3.0 (0) -Branch -Hash | 0bab29e568f64a25f17425c0ffd1c0e89609b6d1 -Hash Date | 20240307 -Driver Version | 2.3.0 (0) - - -BDF | Device | UUID | AMC | State ------------------------------------------------------------------------------------------ -21:00.0 | ALVEO V80 INT | 3907c6f088e5c23471ab99aae09a9928 | 2.3.0 (0) | READY -e2:00.0 | ALVEO V80 INT | 3907c6f088e5c23471ab99aae09a9928 | 2.3.0 (0) | READY -``` - -## Build the VRT software stack - -In order to build the VRT software stack, run the following commands: - -```bash -cd -./deploy/package/package.py -``` - -## Install the VRT software stack - -In the directory `/deploy/output` the previous commands generate a directory called `amd-vrt__` directory. Navigate to that directory and run: - -```bash -cd /deploy/output/amd-vrt__ -sudo apt install ./amd-vrt___.deb -``` -This will install the runtime API and CLI utility function. You can verify the successful installation by running: - -```bash -v80-smi list --------------------------------------------------------------------- -Listing V80 devices --------------------------------------------------------------------- -V80 device found with BDF: 0000:e2:00.0 --------------------------------------------------------------------- -V80 device found with BDF: 0000:21:00.0 --------------------------------------------------------------------- -``` - -## Build and install the QDMA driver -In order to build and install the QDMA driver, a few steps are necessary: - -```bash -cd /submodules/qdma-drv/QDMA/linux-kernel/driver/src -``` -The PCIe identifier for V80 cards needs to be inserted in the file `pci_ids.h`, as follows: - -```bash -lspci -vd 10ee: -21:00.0 Processing accelerators: Xilinx Corporation Device 50b4 - Subsystem: Xilinx Corporation Device 000e - Physical Slot: 2-1 - Flags: bus master, fast devsel, latency 0, NUMA node 2, IOMMU group 27 - Memory at 2bf70000000 (64-bit, prefetchable) [size=256M] - Capabilities: - Kernel driver in use: ami - Kernel modules: ami - -21:00.1 Processing accelerators: Xilinx Corporation Device 50b5 - Subsystem: Xilinx Corporation Device 000e - Physical Slot: 2-1 - Flags: bus master, fast devsel, latency 0, NUMA node 2, IOMMU group 27 - Memory at 2bf80000000 (64-bit, prefetchable) [size=512K] - Capabilities: - Kernel driver in use: qdma-pf - Kernel modules: qdma_pf, ami, qdma_vf - -# At the same line with 21:00.1, you can see the PCIe identifier as 50b5 -# 50b5 should be added to end of src/pci_ids.h in following form -{ PCI_DEVICE(0x10ee, 0x50b5), }, /** V80 */ -``` -Then the driver can be built: - -```bash -cd /submodules/qdma-drv/QDMA/linux-kernel && make -sudo make install -``` - -In order to verify the correct installation of the qdma driver, run the command: - -```bash -lspci -vd 10ee: -21:00.0 Processing accelerators: Xilinx Corporation Device 50b4 - Subsystem: Xilinx Corporation Device 000e - Flags: bus master, fast devsel, latency 0, NUMA node 0, IOMMU group 29 - Memory at 2bf70000000 (64-bit, prefetchable) [size=256M] - Capabilities: - Kernel driver in use: ami - Kernel modules: ami - -21:00.1 Processing accelerators: Xilinx Corporation Device 50b5 - Subsystem: Xilinx Corporation Device 000e - Flags: bus master, fast devsel, latency 0, NUMA node 0, IOMMU group 29 - Memory at 2bf80000000 (64-bit, prefetchable) [size=512K] - Capabilities: - Kernel driver in use: qdma-pf - Kernel modules: qdma_pf, ami, qdma_vf -``` - -## New card preparation - -In order for VRT to work, the [AVED card installation](https://xilinx.github.io/AVED/latest/AVED%2BUpdating%2BFPT%2BImage%2Bin%2BFlash.html) process should be followed to prepare the card. - -After the card installation is complete, partition 1 of the OSPI memory needs to be overwritten with the Segmented Configuration image. The Segmented Configuration image can be found at `/opt/amd/vrt/design.pdi`. In order to program this, run the following command: - -```bash -sudo ami_tool cfgmem_program -d 21:00.0 -i /opt/amd/vrt/design.pdi -t primary -p 1 -``` -Replace `21:00.0` with your card's BDF. \ No newline at end of file diff --git a/deploy/aved.patch b/deploy/aved.patch deleted file mode 100644 index c91c5aed..00000000 --- a/deploy/aved.patch +++ /dev/null @@ -1,2725 +0,0 @@ -diff --git a/fw/AMC/build/amc_version.json b/fw/AMC/build/amc_version.json -deleted file mode 100644 -index d35941a..0000000 ---- a/fw/AMC/build/amc_version.json -+++ /dev/null -@@ -1,11 +0,0 @@ --{ -- "BUILD_BRANCH":"", -- "VERSION_HASH":"37139f62ff1333680cda75c952112a85c01e131d", -- "VERSION_HASH_DATE":"20240725", -- "AMC_VERSION_RELEASE":"2.3.0", -- "AMC_VERSION_MAJOR":2, -- "AMC_VERSION_MINOR":3, -- "AMC_VERSION_PATCH":0, -- "AMC_DEV_COMMITS":0, -- "AMC_DEV_STATUS":0 --} -diff --git a/fw/AMC/src/apps/in_band/in_band_telemetry.c b/fw/AMC/src/apps/in_band/in_band_telemetry.c -index e69615e..3f226d3 100644 ---- a/fw/AMC/src/apps/in_band/in_band_telemetry.c -+++ b/fw/AMC/src/apps/in_band/in_band_telemetry.c -@@ -624,6 +624,7 @@ static int iAmiCallback( EVL_SIGNAL *pxSignal ) - PLL_DBG( IN_BAND_NAME, "PDI last packet : 0x%x\r\n", xDownloadRequest.iLastPacket ); - PLL_DBG( IN_BAND_NAME, "PDI packet number : 0x%hx\r\n", xDownloadRequest.usPacketNum ); - PLL_DBG( IN_BAND_NAME, "PDI packet size (KB) : 0x%hx\r\n", xDownloadRequest.usPacketSize ); -+ PLL_DBG( IN_BAND_NAME, "PDI partial bitstream: 0x%hhx\r\n", xDownloadRequest.usPartial ); - - if( TRUE == xDownloadRequest.iUpdateFpt ) - { -@@ -645,7 +646,9 @@ static int iAmiCallback( EVL_SIGNAL *pxSignal ) - ( uint32_t )HAL_RPU_SHARED_MEMORY_BASE_ADDR, - xDownloadRequest.ulLength, - xDownloadRequest.usPacketNum, -- xDownloadRequest.usPacketSize ); -+ xDownloadRequest.usPacketSize, -+ xDownloadRequest.iLastPacket, -+ xDownloadRequest.usPartial ); - } - - if( OK != iStatus ) -diff --git a/fw/AMC/src/fal/gcq/fw_if_gcq_amc.c b/fw/AMC/src/fal/gcq/fw_if_gcq_amc.c -index f324b86..8a04e8d 100644 ---- a/fw/AMC/src/fal/gcq/fw_if_gcq_amc.c -+++ b/fw/AMC/src/fal/gcq/fw_if_gcq_amc.c -@@ -451,6 +451,7 @@ static uint32_t prvGCQClose( void *pvFWIf ) - */ - pxProfile->xState = FW_IF_GCQ_STATE_CLOSED; - INC_STAT_COUNTER( FW_IF_GCQ_STATS_CLOSE_COUNT ); -+ xGCQDeinit(pxProfile->pxGCQInstance); - } - - return xRet; -diff --git a/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.c b/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.c -index 72b4cdd..62c77f5 100644 ---- a/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.c -+++ b/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.c -@@ -175,6 +175,7 @@ typedef enum AMI_CMD_OPCODE_REQ - AMI_CMD_OPCODE_PDI_DOWNLOAD_REQ = 0xA, - AMI_CMD_OPCODE_SENSOR_REQ = 0xC, - AMI_CMD_OPCODE_PDI_COPY_REQ = 0xD, -+ AMI_CMD_OPCODE_PARTIAL_PDI_DOWNLOAD_REQ = 0xE, - AMI_CMD_OPCODE_IDENTIFY_REQ = 0x202, - - MAX_AMI_CMD_OPCODE -@@ -392,6 +393,7 @@ typedef struct AMI_CMD_DATA_PAYLOAD - uint16_t usPacketNum:15; - uint16_t usPacketSize; /* packet size in KB */ - uint32_t ulPad; -+ uint8_t usPartial; - - } AMI_CMD_DATA_PAYLOAD; - -@@ -558,8 +560,8 @@ static int iHandleDebugVerbosityRequest( AMI_CMD_REQUEST *pxCmdRequest ); - int iAMI_Initialise( uint8_t ucProxyId, FW_IF_CFG *pxFwIf, uint32_t ulFwIfPort, - uint32_t ulTaskPrio, uint32_t ulTaskStack ) - { -- int iStatus = ERROR; - -+ int iStatus = ERROR; - if( ( UPPER_FIREWALL == pxThis->ulUpperFirewall ) && - ( LOWER_FIREWALL == pxThis->ulLowerFirewall ) && - ( FALSE == pxThis->iInitialised ) && -@@ -996,10 +998,33 @@ int iAMI_GetPdiDownloadRequest( EVL_SIGNAL *pxSignal, - pxThis->xRxData[ ucIndex ].xDownloadRequest.iUpdateFpt; - pxDownloadRequest->iLastPacket = - pxThis->xRxData[ ucIndex ].xDownloadRequest.iLastPacket; -+ pxDownloadRequest->usPartial = 0; - iStatus = OK; - } -- else -+ else if( AMI_CHECK_VALID_INDEX( ucIndex ) && -+ ( TRUE == pxThis->xRxData[ ucIndex ].ucInUse ) && -+ AMI_CMD_OPCODE_PARTIAL_PDI_DOWNLOAD_REQ == pxThis->xRxData[ ucIndex ].xOpCode ) - { -+ pxDownloadRequest->iBootDevice = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.iBootDevice; -+ pxDownloadRequest->ullAddress = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.ullAddress; -+ pxDownloadRequest->ulLength = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.ulLength; -+ pxDownloadRequest->ulPartitionSel = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.ulPartitionSel; -+ pxDownloadRequest->usPacketNum = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.usPacketNum; -+ pxDownloadRequest->usPacketSize = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.usPacketSize; -+ pxDownloadRequest->iUpdateFpt = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.iUpdateFpt; -+ pxDownloadRequest->iLastPacket = -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.iLastPacket; -+ pxDownloadRequest->usPartial = 1; -+ iStatus = OK; -+ } -+ else { - PLL_ERR( AMI_NAME, "Error invalid PDI download request for instance\r\n" ); - INC_ERROR_COUNTER_WITH_STATE( AMI_PROXY_ERRORS_PDI_DOWNLOAD_REQUEST ) - } -@@ -1616,6 +1641,72 @@ static void vProxyDriverTask( void *pvArgs ) - } - break; - } -+ case AMI_CMD_OPCODE_PARTIAL_PDI_DOWNLOAD_REQ: -+ { -+ if( OSAL_ERRORS_NONE == iOSAL_Mutex_Take( pxThis->pvOsalMutexHdl, -+ OSAL_TIMEOUT_WAIT_FOREVER ) ) -+ { -+ INC_STAT_COUNTER( AMI_PROXY_STATS_TAKE_MUTEX ) -+ -+ iStatus = iFindNextFreeRxDataIndex( &ucIndex ); -+ if( ERROR != iStatus ) -+ { -+ pxThis->xRxData[ ucIndex ].usCid = xCmdRequest.xHdr.usCid; -+ pxThis->xRxData[ ucIndex ].xOpCode = xCmdRequest.xHdr.ulOpCode; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.iBootDevice = -+ xCmdRequest.xPdiDownloadPayload.ulBootDevice; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.ullAddress = -+ xCmdRequest.xPdiDownloadPayload.ullAddress; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.ulLength = -+ xCmdRequest.xPdiDownloadPayload.ulSize; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.ulPartitionSel = -+ xCmdRequest.xPdiDownloadPayload.ulPartitionSel; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.usPacketNum = -+ xCmdRequest.xPdiDownloadPayload.usPacketNum; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.usPacketSize = -+ xCmdRequest.xPdiDownloadPayload.usPacketSize; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.iUpdateFpt = -+ xCmdRequest.xPdiDownloadPayload.ulUpdateFpt; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.iLastPacket = -+ xCmdRequest.xPdiDownloadPayload.usLastPacket; -+ pxThis->xRxData[ ucIndex ].ucInUse = TRUE; -+ pxThis->xRxData[ ucIndex ].xDownloadRequest.usPartial = 1; -+ } -+ else -+ { -+ INC_ERROR_COUNTER_WITH_STATE( AMI_PROXY_RX_DATA_INDEX_FAILED ) -+ } -+ -+ if( OSAL_ERRORS_NONE != iOSAL_Mutex_Release( pxThis->pvOsalMutexHdl ) ) -+ { -+ INC_ERROR_COUNTER_WITH_STATE( AMI_PROXY_ERRORS_MUTEX_RELEASE_FAILED ) -+ } -+ -+ if( ERROR != iStatus ) -+ { -+ INC_STAT_COUNTER( AMI_PROXY_STATS_RELEASE_MUTEX ) -+ -+ /* Raise event using the index as the method to track the event */ -+ EVL_SIGNAL xNewSignal = { pxThis->ucMyId, -+ AMI_PROXY_DRIVER_E_PDI_DOWNLOAD_START, -+ ucIndex, -+ 0 }; -+ iStatus = iEVL_RaiseEvent( pxThis->pxEvlRecord, &xNewSignal ); -+ if( ERROR == iStatus ) -+ { -+ PLL_ERR( AMI_NAME, "Error attempting to raise event 0x%x\r\n", -+ AMI_PROXY_DRIVER_E_PDI_DOWNLOAD_START ); -+ INC_ERROR_COUNTER_WITH_STATE( AMI_PROXY_RAISE_EVENT_PDI_DOWNLOAD_FAILED ) -+ } -+ } -+ } -+ else -+ { -+ INC_ERROR_COUNTER_WITH_STATE( AMI_PROXY_ERRORS_MUTEX_TAKE_FAILED ) -+ } -+ break; -+ } -+ - case AMI_CMD_OPCODE_PDI_COPY_REQ: - { - if( OSAL_ERRORS_NONE == iOSAL_Mutex_Take( pxThis->pvOsalMutexHdl, -diff --git a/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.h b/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.h -index a77dc6c..126dd85 100644 ---- a/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.h -+++ b/fw/AMC/src/proxy_drivers/ami/ami_proxy_driver.h -@@ -47,6 +47,7 @@ typedef enum AMI_PROXY_DRIVER_EVENTS - AMI_PROXY_DRIVER_E_EEPROM_READ_WRITE, - AMI_PROXY_DRIVER_E_MODULE_READ_WRITE, - AMI_PROXY_DRIVER_E_DEBUG_VERBOSITY, -+ AMI_PROXY_DRIVER_E_PDI_PARTIAL_DOWNLOAD_START, - - MAX_AMI_PROXY_DRIVER_EVENTS - -@@ -152,6 +153,7 @@ typedef struct AMI_PROXY_PDI_DOWNLOAD_REQUEST - uint32_t ulPartitionSel; - uint16_t usPacketNum; - uint16_t usPacketSize; -+ uint8_t usPartial; - - } AMI_PROXY_PDI_DOWNLOAD_REQUEST; - -diff --git a/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.c b/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.c -index 58b16b7..ce0cfcb 100644 ---- a/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.c -+++ b/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.c -@@ -18,6 +18,7 @@ - #include "osal.h" - #include "apc_proxy_driver.h" - #include "profile_hal.h" -+#include "profile_fal.h" - - /******************************************************************************/ - /* Defines */ -@@ -53,6 +54,22 @@ - #define APC_FPT_HDR_MAGIC_NUM ( 0x92F7A516 ) - #endif - -+#define PDI_PARTIAL_ADDR 0x100000 -+#define PDI_PARTIAL_ADDR_HIGH 0x00 -+#define TIMEOUT_PDI_TRIGGER (4 * 1000) -+ -+/* PDI Reload commands */ -+#define PDI_RELOAD_CMD_ADDR 0xFF3F0A40 -+#define PDI_RELOAD_CMD_DDR (PDI_RELOAD_CMD_ADDR + 4) -+#define PDI_RELOAD_ADDR_HIGH (PDI_RELOAD_CMD_ADDR + 8) -+#define PDI_RELOAD_ADDR_LOW (PDI_RELOAD_CMD_ADDR + 12) -+#define PDI_RELOAD_CMD_TRIGGER (0xFF360000) -+#define PDI_RELOAD_POLL_DONE (0xFF360004) -+ -+/* PDI Reload values */ -+#define PDI_LOAD 0x30701 -+#define PDI_LOAD_DDR 0x0F -+#define IPI_RPU 0x02 - /* Stat & Error definitions */ - #define APC_PROXY_STATS( DO ) \ - DO( APC_PROXY_STATS_INIT_OVERALL_COMPLETE ) \ -@@ -164,6 +181,7 @@ typedef enum - APC_MSG_TYPE_COPY_PDI, - APC_MSG_TYPE_PARTITION_SELECT, - APC_MSG_TYPE_ENABLE_HOT_RESET, -+ APC_MSG_TYPE_DOWNLOAD_PARTIAL_PDI, - MAX_APC_MSG_TYPE - - } APC_MSG_TYPES; -@@ -205,9 +223,8 @@ typedef struct APC_PRIVATE_DATA - - uint32_t pulStats[ APC_PROXY_STATS_MAX ]; - uint32_t pulErrors[ APC_PROXY_ERRORS_MAX ]; -- -+ void* pvTimerHandle; - uint32_t ulLowerFirewall; -- - } APC_PRIVATE_DATA; - - /** -@@ -353,6 +370,15 @@ static int iVerifyDownload( APC_MBOX_DOWNLOAD_IMAGE *pxImageData ); - */ - static int iRefreshFptData( APC_BOOT_DEVICES xBootDevice ); - -+/** -+ * @brief Run partial bitstream -+ * -+ * @param pxImageData Pointer to data regarding the image to download -+ * -+ * @return OK if the image was successfully downloaded -+ * ERROR if the image was not successfully downloaded -+ */ -+static int iProgramPartial (APC_MBOX_DOWNLOAD_IMAGE *pxImageData); - - /******************************************************************************/ - /* Local variables */ -@@ -391,10 +417,13 @@ static APC_PRIVATE_DATA xLocalData = - { - 0 - }, /* puErrors */ -+ NULL, /* pvTimerHandle */ - LOWER_FIREWALL /* ulLowerFirewall */ - }; - static APC_PRIVATE_DATA *pxThis = &xLocalData; - -+static void vTimerTriggerCb ( void *pvTimerHandle ); -+ - - /******************************************************************************/ - /* Public Function implementations */ -@@ -428,6 +457,14 @@ int iAPC_Initialise( uint8_t ucProxyId, - /* used for primary boot device only */ - pxThis->ulNextBootAddr = APC_MULTIBOOT_REAL( HAL_IO_READ32( HAL_APC_PMC_BOOT_REG ) ); - -+ /* initialise timer */ -+ if (OSAL_ERRORS_NONE != iOSAL_Timer_Create( &pxThis->pvTimerHandle, -+ OSAL_TIMER_CONFIG_ONE_SHOT, -+ vTimerTriggerCb, -+ "pl_reload_timer")) -+ { -+ PLL_ERR( APC_NAME, "Error: iOSAL_Timer_Create failed\r\n"); -+ } - /* initalise evl record*/ - if( OK != iEVL_CreateRecord( &pxThis->pxEvlRecord ) ) - { -@@ -598,7 +635,9 @@ int iAPC_DownloadImage( EVL_SIGNAL *pxSignal, - uint32_t ulSrcAddr, - uint32_t ulImageSize, - uint16_t usPacketNum, -- uint16_t usPacketSize ) -+ uint16_t usPacketSize, -+ int iLastPacket, -+ uint8_t usPartial ) - { - int iStatus = ERROR; - -@@ -616,7 +655,9 @@ int iAPC_DownloadImage( EVL_SIGNAL *pxSignal, - { - 0 - }; -- xMsg.eMsgType = APC_MSG_TYPE_DOWNLOAD_PDI; -+ xMsg.eMsgType = (usPartial) ? -+ APC_MSG_TYPE_DOWNLOAD_PARTIAL_PDI : -+ APC_MSG_TYPE_DOWNLOAD_PDI; - xMsg.ucRequestId = pxSignal->ucInstance; - xMsg.xDownloadImageData.xBootDevice = xBootDevice; - xMsg.xDownloadImageData.iPartition = iPartition; -@@ -625,6 +666,7 @@ int iAPC_DownloadImage( EVL_SIGNAL *pxSignal, - xMsg.xDownloadImageData.ulSrcAddr = ulSrcAddr; - xMsg.xDownloadImageData.usPacketNum = usPacketNum; - xMsg.xDownloadImageData.usPacketSize = usPacketSize; -+ xMsg.xDownloadImageData.iLastPacket = iLastPacket; - - if( OSAL_ERRORS_NONE == iOSAL_MBox_Post( pxThis->pvOsalMBoxHdl, - ( void* )&xMsg, -@@ -1222,6 +1264,24 @@ static void vProxyDriverTask( void *pArg ) - } - break; - -+ case APC_MSG_TYPE_DOWNLOAD_PARTIAL_PDI: -+ { -+ xSignal.ucEventType = APC_PROXY_DRIVER_E_DOWNLOAD_STARTED; -+ if( OK == iProgramPartial( &xMBoxData.xDownloadImageData)) { -+ INC_STAT_COUNTER( APC_PROXY_STATS_IMAGE_DOWNLOAD_COMPLETE ) -+ xSignal.ucEventType = APC_PROXY_DRIVER_E_DOWNLOAD_COMPLETE; -+ } -+ else -+ { -+ INC_ERROR_COUNTER_WITH_STATE( APC_PROXY_ERRORS_IMAGE_DOWNLOAD_FAILED ) -+ xSignal.ucEventType = APC_PROXY_DRIVER_E_DOWNLOAD_FAILED; -+ } -+ if( OK != iEVL_RaiseEvent( pxThis->pxEvlRecord, &xSignal ) ) -+ { -+ INC_ERROR_COUNTER_WITH_STATE( APC_PROXY_ERRORS_RAISE_EVENT_FAILED ) -+ } -+ } -+ break; - default: - { - INC_ERROR_COUNTER_WITH_STATE( APC_PROXY_ERRORS_MBOX_PEND_FAILED ) -@@ -1875,3 +1935,73 @@ static int iVerifyDownload( APC_MBOX_DOWNLOAD_IMAGE *pxImageData ) - - return iStatus; - } -+ -+/** -+ * @brief Program FPGA with partial image -+ */ -+uint8_t* rsvd_mem_partial_program = ( uint8_t* ) PDI_PARTIAL_ADDR; // base address for PDI download -+static int iProgramPartial (APC_MBOX_DOWNLOAD_IMAGE *pxImageData) -+{ -+ uint32_t ulAddr = pxImageData->ulSrcAddr; -+ uint32_t ulImageSize = pxImageData->ulImageSize; -+ uint8_t usLast = pxImageData->iLastPacket; -+ uint16_t packetSize = pxImageData->usPacketSize; -+ uint16_t packetNum = pxImageData->usPacketNum; -+ uint8_t *pucPdiData = (uint8_t *)(uintptr_t)(pxImageData->ulSrcAddr); -+ HAL_FLUSH_CACHE_DATA( ( uintptr_t )( pxImageData->ulSrcAddr ), ulImageSize ); -+ PLL_DBG(APC_NAME, "Source addr: 0x%x\n\r", ulAddr); -+ PLL_DBG(APC_NAME, "Image size: 0x%x\n\r", ulImageSize); -+ PLL_DBG(APC_NAME, "Last packet: %u\n\r", usLast); -+ PLL_DBG(APC_NAME, "Packet size: %u\n\r", packetSize); -+ PLL_DBG(APC_NAME, "Packet number: %u\n\r", packetNum); -+ uint32_t destAddr = pxImageData->usPacketNum * ( pxImageData->usPacketSize * APC_BASE_PACKET_SIZE ); -+ PLL_DBG(APC_NAME, "Dest addr: 0x%x\n\r", destAddr); -+ if( NULL == pvOSAL_MemCpy(rsvd_mem_partial_program + destAddr, pucPdiData, ulImageSize) ) -+ { -+ PLL_ERR(APC_NAME, "Error: MemCpy"); -+ return ERROR; -+ } -+ -+ if( usLast == 1 ) -+ { -+ if( OSAL_ERRORS_NONE != iOSAL_Timer_Start( pxThis->pvTimerHandle, TIMEOUT_PDI_TRIGGER ) ) -+ { -+ PLL_ERR(APC_NAME, "Error: Timer start"); -+ } -+ } -+ -+ return OK; -+} -+ -+int iTriggerPartial () -+{ -+ if( OSAL_ERRORS_NONE != iOSAL_Mutex_Take( pxThis->pvOsalMutexHdl, OSAL_TIMEOUT_WAIT_FOREVER ) ) -+ { -+ INC_ERROR_COUNTER_WITH_STATE( APC_PROXY_ERRORS_MUTEX_TAKE_FAILED ) -+ } -+ -+ xGcqIf.close(&xGcqIf); -+ HAL_IO_WRITE32(PDI_LOAD, PDI_RELOAD_CMD_ADDR); -+ HAL_IO_WRITE32(PDI_LOAD_DDR, PDI_RELOAD_CMD_DDR); -+ HAL_IO_WRITE32(PDI_PARTIAL_ADDR_HIGH, PDI_RELOAD_ADDR_HIGH); -+ HAL_IO_WRITE32(PDI_PARTIAL_ADDR, PDI_RELOAD_ADDR_LOW); -+ PLL_LOG(APC_NAME, "Triggering IPI...\r\n"); -+ iOSAL_Task_SleepMs( APC_TASK_SLEEP_MS ); -+ HAL_IO_WRITE32(IPI_RPU, PDI_RELOAD_CMD_TRIGGER); -+ while (HAL_IO_READ32(PDI_RELOAD_POLL_DONE) != 0) {} -+ PLL_LOG(APC_NAME, "PDI done...\r\n"); -+ xGcqIf.open(&xGcqIf); -+ if( OSAL_ERRORS_NONE != iOSAL_Mutex_Release( pxThis->pvOsalMutexHdl ) ) -+ { -+ INC_ERROR_COUNTER_WITH_STATE( APC_PROXY_ERRORS_MUTEX_RELEASE_FAILED ) -+ } -+ -+ return OK; -+} -+ -+static void vTimerTriggerCb ( void *pvTimerHandle ) -+{ -+ iTriggerPartial(); -+ iOSAL_Timer_Stop(pvTimerHandle); -+ -+} -\ No newline at end of file -diff --git a/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.h b/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.h -index 757ba56..da92d67 100644 ---- a/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.h -+++ b/fw/AMC/src/proxy_drivers/apc/apc_proxy_driver.h -@@ -41,6 +41,9 @@ typedef enum APC_PROXY_DRIVER_EVENTS - APC_PROXY_DRIVER_E_COPY_FAILED, - APC_PROXY_DRIVER_E_PARTITION_SELECTED, - APC_PROXY_DRIVER_E_PARTITION_SELECTION_FAILED, -+ APC_PROXY_DRIVER_E_PARTIAL_DOWNLOAD_STARTED, -+ APC_PROXY_DRIVER_E_PARTIAL_DOWNLOAD_COMPLETE, -+ APC_PROXY_DRIVER_E_PARTIAL_DOWNLOAD_FAILED, - - MAX_APC_PROXY_DRIVER_EVENTS - -@@ -136,13 +139,14 @@ int iAPC_BindCallback( EVL_CALLBACK *pxCallback ); - * @param ulImageSize Size of image (in bytes) - * @param usPacketNum Image packet number - * @param usPacketSize Size of image packet (in KB) -+ * @param usPartial Flag that indicates if this is a partial PDI - * - * @return OK Image downloaded successfully - * ERROR Image not downloaded successfully - * - */ - int iAPC_DownloadImage( EVL_SIGNAL *pxSignal, APC_BOOT_DEVICES xBootDevice, int iPartition, uint32_t ulSrcAddr, -- uint32_t ulImageSize, uint16_t usPacketNum, uint16_t usPacketSize ); -+ uint32_t ulImageSize, uint16_t usPacketNum, uint16_t usPacketSize, int usLastPacket, uint8_t usPartial ); - - /** - * @brief Download an image with an FPT to a location in NV memory -@@ -254,4 +258,12 @@ int iAPC_ClearStatistics( void ); - */ - int iAPC_GetState( MODULE_STATE *pxState ); - -+/** -+ * @brief Trigger partial programming -+ * -+ * @return OK If successful -+ * ERROR If not successful -+ */ -+int iTriggerPartial (); -+ - #endif -diff --git a/fw/AMC/src/proxy_drivers/apc/debug/apc_proxy_driver_debug.c b/fw/AMC/src/proxy_drivers/apc/debug/apc_proxy_driver_debug.c -index 63efd51..bc26318 100644 ---- a/fw/AMC/src/proxy_drivers/apc/debug/apc_proxy_driver_debug.c -+++ b/fw/AMC/src/proxy_drivers/apc/debug/apc_proxy_driver_debug.c -@@ -104,6 +104,13 @@ static void vGetFptHeader( void ); - */ - static void vGetFptPartition( void ); - -+/** -+ * @brief Debug function to trigger a partial PDI reload -+ * -+ * @return N/A -+ */ -+ static void vTriggerPartial( void ); -+ - /***** Helper functions *****/ - - /** -@@ -152,6 +159,7 @@ void vAPC_DebugInit( DAL_HDL pxParentHandle ) - pxDAL_NewDebugFunction( "set_copy_image", pxSetDir, vSetCopyImage ); - pxDAL_NewDebugFunction( "set_next_partition", pxSetDir, vSetNextPartition ); - pxDAL_NewDebugFunction( "enable_hot_reset", pxSetDir, vSetEnableHotReset ); -+ pxDAL_NewDebugFunction( "trigger_partial", pxSetDir, vTriggerPartial ); - } - if( NULL != pxGetDir ) - { -@@ -213,6 +221,7 @@ static void vSetDownloadImage( void ) - uint32_t ulSrcAddr = 0; - int iPacketNum = 0; - int iPacketSize = 0; -+ int iPartial = 0; - - if( OK != iDAL_GetIntInRange( "Enter request instance:", &iInstance, 0, UTIL_MAX_UINT8 ) ) - { -@@ -242,21 +251,30 @@ static void vSetDownloadImage( void ) - { - PLL_DAL( APC_DBG_NAME, "Error retrieving packet size\r\n" ); - } -- - else - { - EVL_SIGNAL xSignal = { 0 }; - xSignal.ucInstance = iInstance; -- -+ if( iPartial == 1 ) -+ { -+ iTriggerPartial(); -+ } - if( OK != iAPC_DownloadImage( &xSignal, ( APC_BOOT_DEVICES )xBootDevice, iPartition, ulSrcAddr, ( uint32_t )iImageSize, -- ( uint16_t )iPacketNum, ( uint16_t )iPacketSize ) ) -+ ( uint16_t )iPacketNum, ( uint16_t )iPacketSize, 0, ( uint8_t )iPartial ) ) - { - PLL_DAL( APC_DBG_NAME, "Error writing %d bytes to partition %d\r\n", iImageSize, iPartition ); - } - else - { -- PLL_DAL( APC_DBG_NAME, "%d bytes written from 0x%08X to partition %d\r\n", -+ if( iPartial == 0 ) -+ { -+ PLL_DAL( APC_DBG_NAME, "%d bytes written from 0x%08X to partition %d\r\n", - iImageSize, ulSrcAddr, iPartition ); -+ } -+ else -+ { -+ PLL_DAL( APC_DBG_NAME, "Partial PDI starting\r\n"); -+ } - } - } - } -@@ -465,3 +483,13 @@ static int iTestCallback( EVL_SIGNAL *pxSignal ) - return iStatus; - } - -+/** -+ * @brief Trigger a partial PDI reload -+ */ -+static void vTriggerPartial( void ) { -+ if (OK == iTriggerPartial()) { -+ PLL_DAL( APC_DBG_NAME, "Partial PDI triggered\r\n"); -+ } else { -+ PLL_DAL( APC_DBG_NAME, "Error triggering partial PDI\r\n"); -+ } -+} -diff --git a/hw/amd_v80_gen5x8_24.1/src/build_design.tcl b/hw/amd_v80_gen5x8_24.1/src/build_design.tcl -index 1e19be3..e829f18 100644 ---- a/hw/amd_v80_gen5x8_24.1/src/build_design.tcl -+++ b/hw/amd_v80_gen5x8_24.1/src/build_design.tcl -@@ -49,6 +49,7 @@ proc do_aved_build {} { - if {[get_property PROGRESS [get_runs impl_1]] != "100%"} { - common::send_msg_id {BUILD_HW-6} {ERROR} "Implementation failed" - } -+ source "$src_dir/run_post.tcl" - - common::send_msg_id {BUILD_HW-8} {INFO} {Done!} - } -diff --git a/hw/amd_v80_gen5x8_24.1/src/create_design.tcl b/hw/amd_v80_gen5x8_24.1/src/create_design.tcl -index 4ddb58e..e799514 100644 ---- a/hw/amd_v80_gen5x8_24.1/src/create_design.tcl -+++ b/hw/amd_v80_gen5x8_24.1/src/create_design.tcl -@@ -44,6 +44,9 @@ proc do_aved_create_design { } { - source "$src_dir/bd/create_bd_design.tcl" - create_root_design "" - -+ # Add custom logic to AVED block design -+ source "$src_dir/run_pre.tcl" -+ run_pre "" - # Write the block diagram wrapper and set it as design top - add_files -norecurse [make_wrapper -files [get_files "${bd_name}.bd"] -top] - update_compile_order -fileset sources_1 -diff --git a/sw/AMI/api/include/ami_program.h b/sw/AMI/api/include/ami_program.h -index 4195249..3c2a7bb 100644 ---- a/sw/AMI/api/include/ami_program.h -+++ b/sw/AMI/api/include/ami_program.h -@@ -104,6 +104,7 @@ struct ami_pdi_progress { - * @boot_device: Target boot device. - * @partition: Partition number to flash to. - * @progress_handler: An event handler to accept progress notifications. -+ * @partial: Specify whether the PDI is partial or full. - * - * If a progress handler is given, a thread will be started to monitor driver - * events - `ctr` will be equal to the number of bytes successfully written -@@ -112,7 +113,7 @@ struct ami_pdi_progress { - * Return: AMI_STATUS_OK or AMI_STATUS_ERROR. - */ - int ami_prog_download_pdi(ami_device *dev, const char *path, uint8_t boot_device, -- uint32_t partition, ami_event_handler progress_handler); -+ uint32_t partition, ami_event_handler progress_handler, bool partial); - - /** - * ami_prog_update_fpt() - Program a PDI containing an FPT onto a device. -diff --git a/sw/AMI/api/src/ami_ioctl.h b/sw/AMI/api/src/ami_ioctl.h -index 96efb72..61e39ca 100644 ---- a/sw/AMI/api/src/ami_ioctl.h -+++ b/sw/AMI/api/src/ami_ioctl.h -@@ -41,6 +41,7 @@ - * @cap_override: Bypass permission checks. This may not apply to all IOCTL's. - * @efd: File descriptor for event notifications (used for progress reporting when - * performing long running operations like PDI downloads) - optional -+ * @partial: Flag to indicate partial or full PDI - * - * Note that addr can be an address to any arbitrary data type, - * depending on the context. This struct is reused for the boot select -@@ -61,6 +62,7 @@ struct ami_ioc_data_payload { - uint32_t dest_part; - bool cap_override; - int efd; -+ bool partial; - }; - - /** -diff --git a/sw/AMI/api/src/ami_program.c b/sw/AMI/api/src/ami_program.c -index c5b635e..170b638 100644 ---- a/sw/AMI/api/src/ami_program.c -+++ b/sw/AMI/api/src/ami_program.c -@@ -108,11 +108,12 @@ static int read_file(const char *fname, uint8_t **buf, uint32_t *size) - * @boot_device: Target boot device. - * @partition: Partition number to program. - * @progress_handler: Progress handler callback (optional). -+ * @partial: Specify whether the PDI is partial or full. - * - * Return: AMI_STATUS_OK or AMI_STATUS_ERROR - */ - static int do_image_download(ami_device *dev, const char *path, uint8_t boot_device, uint32_t partition, -- ami_event_handler progress_handler) -+ ami_event_handler progress_handler, bool partial) - { - uint8_t *img_data = NULL; - uint32_t img_size = 0; -@@ -136,9 +137,10 @@ static int do_image_download(ami_device *dev, const char *path, uint8_t boot_dev - payload.boot_device = boot_device; - payload.partition = partition; - payload.efd = AMI_INVALID_FD; -+ payload.partial = partial; - - if (progress_handler) { -- progress.bytes_to_write = img_size; -+ progress.bytes_to_write = 2 * img_size; - - if (ami_watch_driver_events(&evt_data, progress_handler, (void*)&progress) == AMI_STATUS_OK) - payload.efd = evt_data.efd; -@@ -172,7 +174,7 @@ static int do_image_download(ami_device *dev, const char *path, uint8_t boot_dev - * Program a pdi bitstream onto a device. - */ - int ami_prog_download_pdi(ami_device *dev, const char *path, uint8_t boot_device, -- uint32_t partition, ami_event_handler progress_handler) -+ uint32_t partition, ami_event_handler progress_handler, bool partial) - { - if (!dev || !path || (partition == AMI_IOC_FPT_UPDATE_MAGIC)) - return AMI_API_ERROR(AMI_ERROR_EINVAL); -@@ -182,7 +184,8 @@ int ami_prog_download_pdi(ami_device *dev, const char *path, uint8_t boot_device - path, - boot_device, - partition, -- progress_handler -+ progress_handler, -+ partial - ); - } - -@@ -200,7 +203,8 @@ int ami_prog_update_fpt(ami_device *dev, const char *path, uint8_t boot_device, - path, - boot_device, - AMI_IOC_FPT_UPDATE_MAGIC, -- progress_handler -+ progress_handler, -+ false - ); - } - -@@ -211,7 +215,6 @@ int ami_prog_device_boot(struct ami_device **dev, uint32_t partition) - { - int ret = AMI_STATUS_ERROR; - struct ami_ioc_data_payload payload = { 0 }; -- - if (!dev || !(*dev)) - return AMI_API_ERROR(AMI_ERROR_EINVAL); - -@@ -219,7 +222,7 @@ int ami_prog_device_boot(struct ami_device **dev, uint32_t partition) - return AMI_STATUS_ERROR; /* last error is set by ami_open_cdev */ - - payload.partition = partition; -- -+ payload.cap_override = (*dev)->cap_override; - if (ioctl((*dev)->cdev, AMI_IOC_DEVICE_BOOT, &payload) == AMI_LINUX_STATUS_ERROR) { - ret = AMI_API_ERROR_M( - AMI_ERROR_EIO, -@@ -230,6 +233,7 @@ int ami_prog_device_boot(struct ami_device **dev, uint32_t partition) - } else { - /* Perform hot reset. This will update the device handle. */ - ret = ami_dev_hot_reset(dev); -+ ret = AMI_STATUS_OK; - } - - return ret; -diff --git a/sw/AMI/app/Makefile b/sw/AMI/app/Makefile -index 91f7598..576fed1 100644 ---- a/sw/AMI/app/Makefile -+++ b/sw/AMI/app/Makefile -@@ -20,7 +20,7 @@ INC_FLAGS := $(addprefix -I,$(INC_DIRS)) - AMI_LIB_DIR := ../api/build - AMI_LIB := ami - --CFLAGS := $(INC_FLAGS) -Wall -Werror -+CFLAGS := $(INC_FLAGS) -Wall - LDFLAGS := -L$(AMI_LIB_DIR) -l$(AMI_LIB) -lm -lpthread - - # -diff --git a/sw/AMI/app/cmd_handlers/cmd_cfgmem_program.c b/sw/AMI/app/cmd_handlers/cmd_cfgmem_program.c -index d1f0e38..f25fa76 100644 ---- a/sw/AMI/app/cmd_handlers/cmd_cfgmem_program.c -+++ b/sw/AMI/app/cmd_handlers/cmd_cfgmem_program.c -@@ -235,7 +235,8 @@ static int do_cmd_cfgmem_program(struct app_option *options, int num_args, char - image->arg, - selected_boot_device, - partition_number, -- progress_handler) == AMI_STATUS_OK) { -+ progress_handler, -+ false) == AMI_STATUS_OK) { - printf("\r\nImage programming complete.\r\n"); - - if ((NULL == find_app_option('q', options)) && -@@ -274,7 +275,7 @@ static int do_cmd_cfgmem_program(struct app_option *options, int num_args, char - ret = EXIT_SUCCESS; - printf("\r\nAborting...\r\n"); - } -- -+ - ami_dev_delete(&dev); - return ret; - } -diff --git a/sw/AMI/app/cmd_handlers/cmd_device_boot.c b/sw/AMI/app/cmd_handlers/cmd_device_boot.c -index 4202ebb..957b771 100644 ---- a/sw/AMI/app/cmd_handlers/cmd_device_boot.c -+++ b/sw/AMI/app/cmd_handlers/cmd_device_boot.c -@@ -122,6 +122,12 @@ static int do_cmd_device_boot(struct app_option *options, int num_args, char **a - - partition_number = (uint32_t)strtoul(partition->arg, NULL, 0); - -+ -+ if(ami_dev_request_access(dev) != AMI_STATUS_OK) { -+ APP_API_ERROR("could not request access to device"); -+ } -+ -+ - printf("Will do a hot reset to boot into partition %d. This may take a minute...\r\n", - partition_number); - -diff --git a/sw/AMI/driver/amc_proxy.c b/sw/AMI/driver/amc_proxy.c -index c68e87e..9e031d0 100644 ---- a/sw/AMI/driver/amc_proxy.c -+++ b/sw/AMI/driver/amc_proxy.c -@@ -57,6 +57,7 @@ enum amc_proxy_cmd_opcode { - AMC_PROXY_CMD_OPCODE_PDI_DOWNLOAD = 0xA, - AMC_PROXY_CMD_OPCODE_SENSOR = 0xC, - AMC_PROXY_CMD_OPCODE_PARTITION_COPY = 0xD, -+ AMC_PROXY_CMD_OPCODE_PARTIAL_PDI_DOWNLOAD = 0xE, - AMC_PROXY_CMD_OPCODE_IDENTIFY = 0x202, - - /* Other commands to be added here */ -@@ -983,7 +984,6 @@ int amc_proxy_request_identity(struct amc_proxy_cmd_struct *cmd) - - amc_ctxt = amc_proxy_find_matching_proxy_instance(cmd->cmd_fw_if_gcq); - if (amc_ctxt && amc_ctxt->inst.initialised) { -- - struct amc_proxy_cmd_request request_cmd_entry = {{{{0}}}}; - struct amc_proxy_cmd_request_hdr *request_hdr = NULL; - request_hdr = &(request_cmd_entry.hdr); -@@ -1076,7 +1076,9 @@ int amc_proxy_request_pdi_download(struct amc_proxy_cmd_struct *cmd, - struct amc_proxy_cmd_request_hdr *request_hdr = NULL; - request_hdr = &(request_cmd_entry.hdr); - request_hdr->state = AMC_PROXY_REQUEST_CMD_NEW; -- request_hdr->opcode = AMC_PROXY_CMD_OPCODE_PDI_DOWNLOAD; -+ request_hdr->opcode = (pdi_download->partial) ? -+ AMC_PROXY_CMD_OPCODE_PARTIAL_PDI_DOWNLOAD : -+ AMC_PROXY_CMD_OPCODE_PDI_DOWNLOAD; - request_hdr->count = sizeof(request_cmd_entry.pdi_payload); - request_hdr->cid = cmd->cmd_cid; - -@@ -1213,7 +1215,6 @@ int amc_proxy_request_heartbeat(struct amc_proxy_cmd_struct *cmd, - - amc_ctxt = amc_proxy_find_matching_proxy_instance(cmd->cmd_fw_if_gcq); - if (amc_ctxt && amc_ctxt->inst.initialised) { -- - struct amc_proxy_cmd_request request_cmd_entry = {{{{0}}}}; - struct amc_proxy_cmd_request_hdr *request_hdr = NULL; - request_hdr = &(request_cmd_entry.hdr); -diff --git a/sw/AMI/driver/amc_proxy.h b/sw/AMI/driver/amc_proxy.h -index 63673a3..09707f9 100644 ---- a/sw/AMI/driver/amc_proxy.h -+++ b/sw/AMI/driver/amc_proxy.h -@@ -156,6 +156,7 @@ struct amc_proxy_pdi_download_request { - uint16_t last_chunk; - uint16_t chunk; - uint16_t chunk_size; -+ bool partial; - }; - - /** -diff --git a/sw/AMI/driver/ami_amc_control.c b/sw/AMI/driver/ami_amc_control.c -index 6bf6b51..e3eb693 100644 ---- a/sw/AMI/driver/ami_amc_control.c -+++ b/sw/AMI/driver/ami_amc_control.c -@@ -795,6 +795,9 @@ static enum amc_cmd_id get_cmd_command_id(enum gcq_submit_cmd_req cmd_req) - id = AMC_CMD_ID_DEBUG_VERBOSITY; - break; - -+ case GCQ_SUBMIT_CMD_DOWNLOAD_PARTIAL_PDI: -+ id = AMC_CMD_ID_DOWNLOAD_PARTIAL_PDI; -+ break; - default: - id = AMC_CMD_ID_UNKNOWN; - break; -@@ -1222,6 +1225,7 @@ int submit_gcq_command(struct amc_control_ctxt *amc_ctrl_ctxt, - switch (cmd_id) { - /* data_buf required */ - case AMC_CMD_ID_DOWNLOAD_PDI: -+ case AMC_CMD_ID_DOWNLOAD_PARTIAL_PDI: - case AMC_CMD_ID_IDENTIFY: - case AMC_CMD_ID_SENSOR: - case AMC_CMD_ID_HEARTBEAT: -@@ -1332,6 +1336,34 @@ int submit_gcq_command(struct amc_control_ctxt *amc_ctrl_ctxt, - } - break; - -+ case AMC_CMD_ID_DOWNLOAD_PARTIAL_PDI: -+ /* Same as AMC_CMD_ID_DOWNLOAD_PDI. Handler changes so the change is seen in AMC */ -+ { -+ if (acquire_gcq_data(amc_ctrl_ctxt, (uint32_t *)&(payload_address), &length)) { -+ ret = -EIO; -+ goto done; -+ } -+ -+ data_page_acquired = true; -+ payload_size = data_size; -+ -+ AMI_VDBG(amc_ctrl_ctxt, -+ "Payload size = %d, page length = %d", -+ payload_size, -+ length); -+ if (length < payload_size) { -+ AMI_WARN(amc_ctrl_ctxt, -+ "Data request length is %d but allocated length is %d", -+ payload_size, -+ length); -+ payload_size = length; -+ } -+ -+ /* Copy payload data to address */ -+ memcpy_gcq_payload_to_device(amc_ctrl_ctxt, payload_address, data_buf, data_size); -+ } -+ break; -+ - case AMC_CMD_ID_SENSOR: - { - if (acquire_gcq_log_page_sema(amc_ctrl_ctxt, -@@ -1475,6 +1507,31 @@ int submit_gcq_command(struct amc_control_ctxt *amc_ctrl_ctxt, - pdi_download_request.length = payload_size; - pdi_download_request.address = payload_address; - pdi_download_request.boot_device = PDI_BOOT_DEVICE(flags); -+ pdi_download_request.partial = false; -+ -+ /* Using the `flags` argument to select the partition. */ -+ if (PDI_PARTITION(flags) != FPT_UPDATE_FLAG) -+ pdi_download_request.partition = PDI_PARTITION(flags); -+ else -+ pdi_download_request.partition = FPT_UPDATE_MAGIC; -+ -+ pdi_download_request.last_chunk = PDI_CHUNK_IS_LAST(flags); -+ pdi_download_request.chunk = PDI_CHUNK(flags); -+ pdi_download_request.chunk_size = PDI_CHUNK_SIZE; -+ /* Set longer timeout for the PDI download */ -+ amc_proxy_cmd->cmd_timeout_jiffies = jiffies + REQUEST_DOWNLOAD_TIMEOUT; -+ ret = amc_proxy_request_pdi_download(amc_proxy_cmd, &pdi_download_request); -+ -+ } -+ break; -+ -+ case AMC_CMD_ID_DOWNLOAD_PARTIAL_PDI: -+ { -+ struct amc_proxy_pdi_download_request pdi_download_request = { 0 }; -+ pdi_download_request.length = payload_size; -+ pdi_download_request.address = payload_address; -+ pdi_download_request.boot_device = PDI_BOOT_DEVICE(flags); -+ pdi_download_request.partial = true; - - /* Using the `flags` argument to select the partition. */ - if (PDI_PARTITION(flags) != FPT_UPDATE_FLAG) -@@ -1674,6 +1731,9 @@ int submit_gcq_command(struct amc_control_ctxt *amc_ctrl_ctxt, - ret = amc_proxy_get_response_debug_verbosity(amc_proxy_cmd); - break; - -+ case AMC_CMD_ID_DOWNLOAD_PARTIAL_PDI: -+ ret = amc_proxy_get_response_pdi_download(amc_proxy_cmd); -+ break; - default: - AMI_ERR(amc_ctrl_ctxt, "Unsupported response %d", cmd_id); - break; -diff --git a/sw/AMI/driver/ami_amc_control.h b/sw/AMI/driver/ami_amc_control.h -index 5828031..75ca259 100644 ---- a/sw/AMI/driver/ami_amc_control.h -+++ b/sw/AMI/driver/ami_amc_control.h -@@ -140,6 +140,7 @@ enum gcq_submit_cmd_req { - GCQ_SUBMIT_CMD_DOWNLOAD_PDI = 0x04, - GCQ_SUBMIT_CMD_DEVICE_BOOT = 0x05, - GCQ_SUBMIT_CMD_COPY_PARTITION = 0x06, -+ GCQ_SUBMIT_CMD_DOWNLOAD_PARTIAL_PDI = 0x07, - GCQ_SUBMIT_CMD_GET_INLET_TEMP_SENSOR = 0x10, - GCQ_SUBMIT_CMD_GET_OUTLET_TEMP_SENSOR = 0x11, - GCQ_SUBMIT_CMD_GET_BOARD_TEMP_SENSOR = 0x12, -@@ -359,6 +360,7 @@ enum amc_cmd_id { - AMC_CMD_ID_EEPROM_READ_WRITE, - AMC_CMD_ID_MODULE_READ_WRITE, - AMC_CMD_ID_DEBUG_VERBOSITY, -+ AMC_CMD_ID_DOWNLOAD_PARTIAL_PDI, - - AMC_CMD_ID_MAX - }; -diff --git a/sw/AMI/driver/ami_cdev.c b/sw/AMI/driver/ami_cdev.c -index a332f7f..63453d1 100644 ---- a/sw/AMI/driver/ami_cdev.c -+++ b/sw/AMI/driver/ami_cdev.c -@@ -5,793 +5,800 @@ - * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. - */ - --#include /* pci_dev */ --#include /* error codes */ --#include /* container_of */ --#include /* kzalloc... */ --#include /* string funcs */ --#include /* file_operations */ --#include --#include --#include -- --#include "ami.h" --#include "ami_hwmon.h" --#include "ami_top.h" --#include "ami_cdev.h" --#include "ami_utils.h" --#include "ami_pcie.h" --#include "ami_program.h" --#include "ami_eeprom.h" --#include "ami_utils.h" --#include "ami_module.h" -- --#define ROOT_USER (0) --#define READ_WRITE (0666) --#define IS_ROOT_USER(uid, euid) (capable(CAP_DAC_OVERRIDE) || (uid == ROOT_USER) || (euid == ROOT_USER)) -- -- --static int dev_major = 0; /* This will be overriden. */ -- -- --/** -- * devnode() - Callback to return device permissions. -- * @dev: Pointer to device struct. -- * @mode: Pointer to store permission bits. -- * -- * Return: NULL. -- */ --static char *devnode(struct device *dev, umode_t *mode) --{ -- if (mode) -- *mode = READ_WRITE; -- -- return NULL; --} -- --/* -- * Open a device file - this increments the pf_dev refcount. -- */ --int dev_open(struct inode *inode, struct file *filp) --{ -- if (!inode || !filp) -- return -EINVAL; -- -- /* This already checks the minor number */ -- filp->private_data = get_pf_dev_entry((void*)inode, PF_DEV_CACHE_INODE); -- -- if (!filp->private_data) -- return -ENODEV; -- -- return 0; --} -- --/* -- * Close a device file - this decrements the pf_dev refcount. -- */ --int dev_close(struct inode *inode, struct file *filp) --{ -- if (!inode || !filp) -- return -EINVAL; -- -- if (filp->private_data) -- put_pf_dev_entry((struct pf_dev_struct*)filp->private_data); -- -- return 0; --} -- --/* -- * This function will be called when we use IOCTL with command on the Device file -- */ --long dev_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) --{ -- int ret = 0; -- struct pf_dev_struct *pf_dev = NULL; -- /* eventfd is used for sending notifications to the user */ -- struct eventfd_ctx *efd_ctx = NULL; -- -- if (!filp) -- return -EINVAL; -- -- /* -- * Extract the type and number bitfields, and don't decode -- * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok( ) -- */ -- if(_IOC_TYPE(cmd) != AMI_IOC_MAGIC) return -ENOTTY; -- if(_IOC_NR(cmd) > AMI_IOC_MAX) return -ENOTTY; -- -- if(!access_ok((void __user*)arg, _IOC_SIZE(cmd))) -- return -ENOTTY; -- -- /* This is is already reference counted */ -- pf_dev = filp->private_data; -- -- /* Check device data */ -- if (!pf_dev) { -- PR_ERR("dev_unlocked_ioctl: unable to find card"); -- return -ENODEV; -- } -- -- /* Check device state */ -- switch (cmd) { -- /* READY, MISSING_INFO or COMPAT only */ -- case AMI_IOC_DOWNLOAD_PDI: -- case AMI_IOC_DEVICE_BOOT: -- switch (pf_dev->state) { -- case PF_DEV_STATE_COMPAT: -- case PF_DEV_STATE_READY: -- case PF_DEV_STATE_MISSING_INFO: -- break; -- -- default: -- return -EPERM; -- } -- break; -- -- /* Any state except INIT and SHUTDOWN */ -- case AMI_IOC_READ_BAR: -- case AMI_IOC_WRITE_BAR: -- case AMI_IOC_APP_SETUP: -- switch (pf_dev->state) { -- case PF_DEV_STATE_INIT: -- case PF_DEV_STATE_SHUTDOWN: -- return -EPERM; -- -- default: -- break; -- } -- break; -- -- /* READY or MISSING_INFO only */ -- case AMI_IOC_GET_SENSOR_VALUE: -- case AMI_IOC_COPY_PARTITION: -- case AMI_IOC_SET_SENSOR_REFRESH: -- case AMI_IOC_GET_FPT_HDR: -- case AMI_IOC_GET_FPT_PARTITION: -- case AMI_IOC_READ_EEPROM: -- case AMI_IOC_WRITE_EEPROM: -- case AMI_IOC_READ_MODULE: -- case AMI_IOC_WRITE_MODULE: -- case AMI_IOC_DEBUG_VERBOSITY: -- switch (pf_dev->state) { -- case PF_DEV_STATE_READY: -- case PF_DEV_STATE_MISSING_INFO: -- break; -- -- default: -- return -EPERM; -- } -- break; -- -- default: -- break; -- } -- -- /* Acquire semaphore */ -- if (down_interruptible(&(pf_dev->ioctl_sema))) -- return -ERESTARTSYS; -- -- if (pf_dev->state == PF_DEV_STATE_COMPAT) -- PR_WARN("Performing IOCTL request in compatibility mode - you may experience issues!"); -- -- /* Handle command */ -- switch (cmd) { -- case AMI_IOC_SET_SENSOR_REFRESH: -- { -- /* -- * This does the same thing as writing to the `update_interval` -- * hwmon file, but we do not require any sudo permissions here. -- */ -- pf_dev->sensor_refresh = (uint16_t)arg; -- break; -- } -- -- case AMI_IOC_DOWNLOAD_PDI: -- { -- /* -- * `arg` is a pointer to the `ami_ioc_data_payload` struct -- * This struct contains the address of the actual data buffer. -- */ -- struct ami_ioc_data_payload data = { 0 }; -- uint8_t *buf = NULL; -- -- /* Check PF - currently only PF0 supported for this command. */ -- if (pf_dev->pcie_function_num != 0) { -- ret = -ENODEV; -- goto done; -- } -- -- /* Read data payload from user. */ -- if (copy_from_user(&data, (struct ami_ioc_data_payload*)arg, sizeof(data))) { -- ret = -EFAULT; /* Bad address */ -- goto done; -- } -- -- /* Check permissions. */ -- if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -- ret = -EPERM; -- goto done; -- } -- -- if ((data.size <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* -- * Using vzalloc because the PDI buffer will be too large -- * for kzalloc (around 4-6MB) -- */ -- buf = vzalloc(data.size); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- if (data.efd >= 0) -- efd_ctx = eventfd_ctx_fdget(data.efd); -- -- /* Read actual data buffer. `addr` is a pointer to uint8_t */ -- if(!copy_from_user(buf, (uint8_t*)data.addr, data.size)) { -- if (data.partition == AMI_IOC_FPT_UPDATE_MAGIC) -- ret = update_fpt( -- pf_dev, -- buf, -- data.size, -- data.boot_device, -- efd_ctx -- ); -- else -- ret = download_pdi( -- pf_dev->amc_ctrl_ctxt, -- buf, -- data.size, -- data.boot_device, -- data.partition, -- efd_ctx -- ); -- } else { -- ret = -EFAULT; -- } -- -- vfree(buf); -- break; -- } -- -- case AMI_IOC_DEVICE_BOOT: -- { -- /* -- * `arg` is a pointer to the `ami_ioc_data_payload` struct. -- * Only the `partition` field should be populated. -- */ -- struct ami_ioc_data_payload data = { 0 }; -- -- /* Check PF - currently only PF0 supported for this command. */ -- if (pf_dev->pcie_function_num != 0) { -- ret = -ENODEV; -- goto done; -- } -- -- /* Read data payload from user. */ -- if (copy_from_user(&data, (struct ami_ioc_data_payload*)arg, sizeof(data))) { -- ret = -EFAULT; /* Bad address */ -- goto done; -- } -- -- /* Check permissions. */ -- if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -- ret = -EPERM; -- goto done; -- } -- -- ret = device_boot(pf_dev, data.partition); -- -- break; -- } -- -- case AMI_IOC_COPY_PARTITION: -- { -- /* -- * `arg` is a pointer to the `ami_ioc_data_payload` struct. -- * Only the `partition` field should be populated. -- */ -- struct ami_ioc_data_payload data = { 0 }; -- -- /* Check PF - currently only PF0 supported for this command. */ -- if (pf_dev->pcie_function_num != 0) { -- ret = -ENODEV; -- goto done; -- } -- -- /* Read data payload from user. */ -- if (copy_from_user(&data, (struct ami_ioc_data_payload*)arg, sizeof(data))) { -- ret = -EFAULT; /* Bad address */ -- goto done; -- } -- -- /* Check permissions. */ -- if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -- ret = -EPERM; -- goto done; -- } -- -- ret = copy_partition(pf_dev, data.src_device, data.src_part, data.dest_device, data.dest_part); -- break; -- } -- -- case AMI_IOC_READ_BAR: -- { -- /* -- * `arg` is a pointer to the `ami_ioc_bar_data` struct. -- */ -- uint32_t *buf = NULL; -- struct ami_ioc_bar_data data = { 0 }; -- -- /* Read data payload. */ -- if (copy_from_user(&data, (struct ami_ioc_bar_data*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- /* Check permissions. */ -- if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -- ret = -EPERM; -- goto done; -- } -- -- if ((data.num <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* Allocate memory for response buffer. */ -- buf = vzalloc(data.num * sizeof(uint32_t)); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- /* We will write the response to the userspace address. */ -- ret = read_pcie_bar(pf_dev->pci, data.bar_idx, -- data.offset, data.num, buf); -- -- if (!ret) -- ret = copy_to_user((uint32_t*)data.addr, buf, -- data.num * sizeof(uint32_t)); -- -- vfree(buf); -- break; -- } -- -- case AMI_IOC_WRITE_BAR: -- { -- /* -- * `arg` is a pointer to the `ami_ioc_bar_data` struct. -- */ -- uint32_t *buf = NULL; -- struct ami_ioc_bar_data data = { 0 }; -- -- /* Read data payload. */ -- if (copy_from_user(&data, (struct ami_ioc_bar_data*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- /* Check permissions. */ -- if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -- ret = -EPERM; -- goto done; -- } -- -- if ((data.num <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* Allocate memory for payload buffer. */ -- buf = vzalloc(data.num * sizeof(uint32_t)); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- /* Copy payload data. */ -- if (!copy_from_user(buf, (uint32_t*)data.addr, data.num * sizeof(uint32_t))) -- ret = write_pcie_bar(pf_dev->pci, data.bar_idx, -- data.offset, data.num, buf); -- else -- ret = -EFAULT; -- -- vfree(buf); -- break; -- } -- -- case AMI_IOC_GET_SENSOR_VALUE: -- { -- /* `arg` is a pointer to `struct ami_ioc_sensor_value` */ -- struct ami_ioc_sensor_value data = { 0 }; -- enum hwmon_sensor_types hwmon_type = 0; -- uint32_t hwmon_attr = 0; -- -- if (copy_from_user(&data, (struct ami_ioc_sensor_value*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- /* Currently, only the instant sensor value is supported with this API. */ -- switch (data.sensor_type) { -- case IOC_SENSOR_TYPE_TEMP: -- hwmon_type = hwmon_temp; -- hwmon_attr = hwmon_temp_input; -- break; -- -- case IOC_SENSOR_TYPE_POWER: -- hwmon_type = hwmon_power; -- hwmon_attr = hwmon_power_input; -- break; -- -- case IOC_SENSOR_TYPE_CURRENT: -- hwmon_type = hwmon_curr; -- hwmon_attr = hwmon_curr_input; -- break; -- -- case IOC_SENSOR_TYPE_VOLTAGE: -- hwmon_type = hwmon_in; -- hwmon_attr = hwmon_in_input; -- break; -- -- default: -- ret = -EINVAL; -- break; -- } -- -- if (ret) -- goto done; -- -- ret = read_sensor_val( -- pf_dev, -- hwmon_type, -- hwmon_attr, -- data.hwmon_channel, -- &data.val, -- data.status, -- &data.fresh -- ); -- -- if (!ret) -- ret = copy_to_user((struct ami_ioc_sensor_value*)arg, -- &data, sizeof(data)); -- -- break; -- } -- -- case AMI_IOC_GET_FPT_HDR: -- { -- /* `arg` is a pointer to `struct ami_ioc_fpt_hdr_value` */ -- struct ami_ioc_fpt_hdr_value data = { 0 }; -- struct fpt_header hdr = { 0 }; -- -- /* Read data payload from user. */ -- if (copy_from_user(&data, (struct ami_ioc_fpt_hdr_value*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- ret = read_fpt_hdr(pf_dev, data.boot_device, &hdr); -- if (!ret) { -- data.version = hdr.version; -- data.hdr_size = hdr.header_size; -- data.entry_size = hdr.entry_size; -- data.num_entries = hdr.num_entries; -- ret = copy_to_user((struct ami_ioc_fpt_hdr_value*)arg, -- &data, sizeof(data)); -- } -- break; -- } -- -- case AMI_IOC_GET_FPT_PARTITION: -- { -- /* `arg` is a pointer to `struct ami_ioc_fpt_partition_value` */ -- struct ami_ioc_fpt_partition_value data = { 0 }; -- struct fpt_partition partition = { 0 }; -- -- if (copy_from_user(&data, (struct ami_ioc_fpt_partition_value*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- ret = read_fpt_partition(pf_dev, -+ #include -+ #include /* pci_dev */ -+ #include /* error codes */ -+ #include /* container_of */ -+ #include /* kzalloc... */ -+ #include /* string funcs */ -+ #include /* file_operations */ -+ #include -+ #include -+ #include -+ -+ #include "ami.h" -+ #include "ami_hwmon.h" -+ #include "ami_top.h" -+ #include "ami_cdev.h" -+ #include "ami_utils.h" -+ #include "ami_pcie.h" -+ #include "ami_program.h" -+ #include "ami_eeprom.h" -+ #include "ami_utils.h" -+ #include "ami_module.h" -+ -+ #define ROOT_USER (0) -+ #define READ_WRITE (0666) -+ #define IS_ROOT_USER(uid, euid) (capable(CAP_DAC_OVERRIDE) || (uid == ROOT_USER) || (euid == ROOT_USER)) -+ -+ -+ static int dev_major = 0; /* This will be overriden. */ -+ -+ -+ /** -+ * devnode() - Callback to return device permissions. -+ * @dev: Pointer to device struct. -+ * @mode: Pointer to store permission bits. -+ * -+ * Return: NULL. -+ */ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(6,2,0) -+ static char *devnode(const struct device *dev, umode_t *mode) -+ #else -+ static char *devnode(struct device *dev, umode_t *mode) -+ #endif -+ { -+ if (mode) -+ *mode = READ_WRITE; -+ -+ return NULL; -+ } -+ -+ /* -+ * Open a device file - this increments the pf_dev refcount. -+ */ -+ int dev_open(struct inode *inode, struct file *filp) -+ { -+ if (!inode || !filp) -+ return -EINVAL; -+ -+ /* This already checks the minor number */ -+ filp->private_data = get_pf_dev_entry((void*)inode, PF_DEV_CACHE_INODE); -+ -+ if (!filp->private_data) -+ return -ENODEV; -+ -+ return 0; -+ } -+ -+ /* -+ * Close a device file - this decrements the pf_dev refcount. -+ */ -+ int dev_close(struct inode *inode, struct file *filp) -+ { -+ if (!inode || !filp) -+ return -EINVAL; -+ -+ if (filp->private_data) -+ put_pf_dev_entry((struct pf_dev_struct*)filp->private_data); -+ -+ return 0; -+ } -+ -+ /* -+ * This function will be called when we use IOCTL with command on the Device file -+ */ -+ long dev_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -+ { -+ int ret = 0; -+ struct pf_dev_struct *pf_dev = NULL; -+ /* eventfd is used for sending notifications to the user */ -+ struct eventfd_ctx *efd_ctx = NULL; -+ -+ if (!filp) -+ return -EINVAL; -+ -+ /* -+ * Extract the type and number bitfields, and don't decode -+ * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok( ) -+ */ -+ if(_IOC_TYPE(cmd) != AMI_IOC_MAGIC) return -ENOTTY; -+ if(_IOC_NR(cmd) > AMI_IOC_MAX) return -ENOTTY; -+ -+ if(!access_ok((void __user*)arg, _IOC_SIZE(cmd))) -+ return -ENOTTY; -+ -+ /* This is is already reference counted */ -+ pf_dev = filp->private_data; -+ -+ /* Check device data */ -+ if (!pf_dev) { -+ PR_ERR("dev_unlocked_ioctl: unable to find card"); -+ return -ENODEV; -+ } -+ -+ /* Check device state */ -+ switch (cmd) { -+ /* READY, MISSING_INFO or COMPAT only */ -+ case AMI_IOC_DOWNLOAD_PDI: -+ case AMI_IOC_DEVICE_BOOT: -+ switch (pf_dev->state) { -+ case PF_DEV_STATE_COMPAT: -+ case PF_DEV_STATE_READY: -+ case PF_DEV_STATE_MISSING_INFO: -+ break; -+ -+ default: -+ return -EPERM; -+ } -+ break; -+ -+ /* Any state except INIT and SHUTDOWN */ -+ case AMI_IOC_READ_BAR: -+ case AMI_IOC_WRITE_BAR: -+ case AMI_IOC_APP_SETUP: -+ switch (pf_dev->state) { -+ case PF_DEV_STATE_INIT: -+ case PF_DEV_STATE_SHUTDOWN: -+ return -EPERM; -+ -+ default: -+ break; -+ } -+ break; -+ -+ /* READY or MISSING_INFO only */ -+ case AMI_IOC_GET_SENSOR_VALUE: -+ case AMI_IOC_COPY_PARTITION: -+ case AMI_IOC_SET_SENSOR_REFRESH: -+ case AMI_IOC_GET_FPT_HDR: -+ case AMI_IOC_GET_FPT_PARTITION: -+ case AMI_IOC_READ_EEPROM: -+ case AMI_IOC_WRITE_EEPROM: -+ case AMI_IOC_READ_MODULE: -+ case AMI_IOC_WRITE_MODULE: -+ case AMI_IOC_DEBUG_VERBOSITY: -+ switch (pf_dev->state) { -+ case PF_DEV_STATE_READY: -+ case PF_DEV_STATE_MISSING_INFO: -+ break; -+ -+ default: -+ return -EPERM; -+ } -+ break; -+ -+ default: -+ break; -+ } -+ -+ /* Acquire semaphore */ -+ if (down_interruptible(&(pf_dev->ioctl_sema))) -+ return -ERESTARTSYS; -+ -+ if (pf_dev->state == PF_DEV_STATE_COMPAT) -+ PR_WARN("Performing IOCTL request in compatibility mode - you may experience issues!"); -+ -+ /* Handle command */ -+ switch (cmd) { -+ case AMI_IOC_SET_SENSOR_REFRESH: -+ { -+ /* -+ * This does the same thing as writing to the `update_interval` -+ * hwmon file, but we do not require any sudo permissions here. -+ */ -+ pf_dev->sensor_refresh = (uint16_t)arg; -+ break; -+ } -+ -+ case AMI_IOC_DOWNLOAD_PDI: -+ { -+ /* -+ * `arg` is a pointer to the `ami_ioc_data_payload` struct -+ * This struct contains the address of the actual data buffer. -+ */ -+ struct ami_ioc_data_payload data = { 0 }; -+ uint8_t *buf = NULL; -+ -+ /* Check PF - currently only PF0 supported for this command. */ -+ if (pf_dev->pcie_function_num != 0) { -+ ret = -ENODEV; -+ goto done; -+ } -+ -+ /* Read data payload from user. */ -+ if (copy_from_user(&data, (struct ami_ioc_data_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; /* Bad address */ -+ goto done; -+ } -+ -+ /* Check permissions. */ -+ if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -+ ret = -EPERM; -+ goto done; -+ } -+ -+ if ((data.size <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* -+ * Using vzalloc because the PDI buffer will be too large -+ * for kzalloc (around 4-6MB) -+ */ -+ buf = vzalloc(data.size); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ if (data.efd >= 0) -+ efd_ctx = eventfd_ctx_fdget(data.efd); -+ -+ /* Read actual data buffer. `addr` is a pointer to uint8_t */ -+ if(!copy_from_user(buf, (uint8_t*)data.addr, data.size)) { -+ if (data.partition == AMI_IOC_FPT_UPDATE_MAGIC) -+ ret = update_fpt( -+ pf_dev, -+ buf, -+ data.size, - data.boot_device, -- data.partition, -- &partition); -- if (!ret) { -- data.type = partition.type; -- data.base_addr = partition.base_addr; -- data.partition_size = partition.partition_size; -- ret = copy_to_user((struct ami_ioc_fpt_partition_value*)arg, -- &data, sizeof(data)); -- } -- break; -- } -- -- case AMI_IOC_READ_EEPROM: -- { -- struct ami_ioc_eeprom_payload data = { 0 }; -- uint8_t *buf = NULL; -- -- /* Read data payload. */ -- if (copy_from_user(&data, (struct ami_ioc_eeprom_payload*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- if ((data.len <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* Allocate memory for response buffer. */ -- buf = vzalloc(data.len * sizeof(uint8_t)); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- ret = eeprom_read(pf_dev->amc_ctrl_ctxt, buf, data.len, data.offset); -- if (!ret) { -- ret = copy_to_user((uint8_t*)data.addr, buf, -- data.len * sizeof(uint8_t)); -- } -- vfree(buf); -- break; -- } -- -- case AMI_IOC_WRITE_EEPROM: -- { -- struct ami_ioc_eeprom_payload data = { 0 }; -- uint8_t *buf = NULL; -- -- /* Read data payload. */ -- if (copy_from_user(&data, (struct ami_ioc_eeprom_payload*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- if ((data.len <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* Allocate memory for payload buffer. */ -- buf = vzalloc(data.len * sizeof(uint8_t)); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- /* Copy payload data. */ -- if (!copy_from_user(buf, (uint8_t*)data.addr, data.len * sizeof(uint8_t))) -- ret = eeprom_write(pf_dev->amc_ctrl_ctxt, buf, data.len, data.offset); -- else -- ret = -EFAULT; -- -- vfree(buf); -- break; -- } -- -- case AMI_IOC_APP_SETUP: -- switch ((enum ami_ioc_app_setup)arg) { -- case IOC_APP_SETUP_REGISTER: -- ret = add_pf_dev_app(pf_dev, get_current()); -- break; -- -- case IOC_APP_SETUP_DEREGISTER: -- ret = delete_pf_dev_app(pf_dev, get_current()); -- break; -- -- default: -- ret = -EINVAL; -- break; -- } -- break; -- -- case AMI_IOC_READ_MODULE: -- { -- struct ami_ioc_module_payload data = { 0 }; -- uint8_t *buf = NULL; -- -- /* Read data payload. */ -- if (copy_from_user(&data, (struct ami_ioc_module_payload*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- if ((data.len <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* Allocate memory for response buffer. */ -- buf = vzalloc(data.len * sizeof(uint8_t)); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- ret = module_read( -- pf_dev->amc_ctrl_ctxt, -- data.device_id, -- data.page, -- data.offset, -- buf, -- data.len -- ); -- -- if (!ret) { -- ret = copy_to_user((uint8_t*)data.addr, buf, -- data.len * sizeof(uint8_t)); -- } -- vfree(buf); -- break; -- } -- -- case AMI_IOC_WRITE_MODULE: -- { -- struct ami_ioc_module_payload data = { 0 }; -- uint8_t *buf = NULL; -- -- /* Read data payload. */ -- if (copy_from_user(&data, (struct ami_ioc_module_payload*)arg, sizeof(data))) { -- ret = -EFAULT; -- goto done; -- } -- -- if ((data.len <= 0) || (data.addr == 0)) { -- ret = -EINVAL; -- goto done; -- } -- -- /* Allocate memory for payload buffer. */ -- buf = vzalloc(data.len * sizeof(uint8_t)); -- -- if (!buf) { -- ret = -ENOMEM; -- goto done; -- } -- -- /* Copy payload data. */ -- if (!copy_from_user(buf, (uint8_t*)data.addr, data.len * sizeof(uint8_t))) -- ret = module_write( -- pf_dev->amc_ctrl_ctxt, -- data.device_id, -- data.page, -- data.offset, -- buf, -- data.len -- ); -- else -- ret = -EFAULT; -- -- vfree(buf); -- break; -- } -- -- case AMI_IOC_DEBUG_VERBOSITY: -- ret = submit_gcq_command( -- pf_dev->amc_ctrl_ctxt, -- GCQ_SUBMIT_CMD_DEBUG_VERBOSITY, -- (uint8_t)arg, -- NULL, -- 0 -- ); -- break; -- -- default: -- PR_ERR("Unknown command, do nothing"); -- ret = -ENOTTY; -- break; -- } -- --done: -- if (efd_ctx) -- eventfd_ctx_put(efd_ctx); -- -- up(&(pf_dev->ioctl_sema)); -- return ret; --} -- --/* -- * Create a character device. -- */ --int create_cdev(unsigned baseminor, struct drv_cdev_struct *drv_cdev, -- struct device *parent, const struct file_operations *fops) --{ -- int ret = 0; -- bool cls_created = false; -- -- /* parent may be NULL */ -- if (!drv_cdev || !fops) { -- return -EINVAL; -- } -- -- /* Allocate chrdev region */ -- drv_cdev->count = DEFAULT_CDEV_COUNT; -- if(dev_major) { -- drv_cdev->cdev_num = MKDEV(dev_major, baseminor); -- ret = register_chrdev_region(drv_cdev->cdev_num, DEFAULT_CDEV_COUNT, -- (const char*)DEFAULT_DEVICE_NAME); -- } else { -- /* This is the first device. */ -- ret = alloc_chrdev_region(&(drv_cdev->cdev_num), baseminor, -- DEFAULT_CDEV_COUNT, (const char*)DEFAULT_DEVICE_NAME); -- dev_major = MAJOR(drv_cdev->cdev_num); -- } -- -- if(ret) -- goto fail; -- -- /* If first device, create class. */ -- strncpy(drv_cdev->drv_cls_str, (const char*)DEFAULT_CLS_NAME, CLS_STR_SIZE); -- -- if(!drv_cdev->dev_class) { -- cls_created = true; -- drv_cdev->dev_class = class_create(THIS_MODULE, drv_cdev->drv_cls_str); -- if (IS_ERR(drv_cdev->dev_class)) { -- ret = PTR_ERR(drv_cdev->dev_class); -- PR_ERR("Failed to create class %s. ret : %d", -- drv_cdev->drv_cls_str, ret); -- goto unreg_cdev_reg; -- } -- drv_cdev->dev_class->devnode = devnode; -- } -- -- /* Create device */ -- snprintf(drv_cdev->dev_name, DEV_NAME_SIZE, "%s%d", DEFAULT_DEVICE_NAME, baseminor); -- drv_cdev->device = device_create(drv_cdev->dev_class, NULL, -- drv_cdev->cdev_num, NULL, drv_cdev->dev_name); -- if (IS_ERR(drv_cdev->device)) { -- ret = PTR_ERR(drv_cdev->device); -- PR_ERR("Failed to create device %s. ret : %d", drv_cdev->dev_name, ret); -- goto del_class; -- } -- -- /* Initialize the cdev structure */ -- cdev_init(&(drv_cdev->cdev), fops); -- drv_cdev->cdev.owner = THIS_MODULE; -- drv_cdev->cdev.ops = fops; -- -- /* -- * Setting the parent is necessary so that the kobject is referenced -- * appropriately and the parent is not freed before the cdev. -- */ -- if (parent) -- cdev_set_parent(&drv_cdev->cdev, &parent->kobj); -- -- /* Register cdev to the kernel */ -- ret = cdev_add(&(drv_cdev->cdev), drv_cdev->cdev_num, drv_cdev->count); -- if (ret) { -- PR_ERR("Failed to register cdev to the kernel, err_code : %d", ret); -- goto del_device; -- } -- -- return SUCCESS; -- --del_device: -- device_destroy(drv_cdev->dev_class, drv_cdev->cdev_num); -- --del_class: -- if(cls_created) -- class_destroy(drv_cdev->dev_class); -- --unreg_cdev_reg: -- unregister_chrdev_region(drv_cdev->cdev_num, DEFAULT_CDEV_COUNT); -- --fail: -- return ret; --} -+ efd_ctx -+ ); -+ else -+ ret = download_pdi( -+ pf_dev->amc_ctrl_ctxt, -+ buf, -+ data.size, -+ data.boot_device, -+ data.partition, -+ efd_ctx, -+ data.partial ? true : false -+ ); -+ } else { -+ ret = -EFAULT; -+ } -+ -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_DEVICE_BOOT: -+ { -+ /* -+ * `arg` is a pointer to the `ami_ioc_data_payload` struct. -+ * Only the `partition` field should be populated. -+ */ -+ struct ami_ioc_data_payload data = { 0 }; -+ -+ /* Check PF - currently only PF0 supported for this command. */ -+ if (pf_dev->pcie_function_num != 0) { -+ ret = -ENODEV; -+ goto done; -+ } -+ -+ /* Read data payload from user. */ -+ if (copy_from_user(&data, (struct ami_ioc_data_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; /* Bad address */ -+ goto done; -+ } -+ -+ /* Check permissions. */ -+ if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -+ ret = -EPERM; -+ goto done; -+ } -+ -+ ret = device_boot(pf_dev, data.partition); -+ -+ break; -+ } -+ -+ case AMI_IOC_COPY_PARTITION: -+ { -+ /* -+ * `arg` is a pointer to the `ami_ioc_data_payload` struct. -+ * Only the `partition` field should be populated. -+ */ -+ struct ami_ioc_data_payload data = { 0 }; -+ -+ /* Check PF - currently only PF0 supported for this command. */ -+ if (pf_dev->pcie_function_num != 0) { -+ ret = -ENODEV; -+ goto done; -+ } -+ -+ /* Read data payload from user. */ -+ if (copy_from_user(&data, (struct ami_ioc_data_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; /* Bad address */ -+ goto done; -+ } -+ -+ /* Check permissions. */ -+ if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -+ ret = -EPERM; -+ goto done; -+ } -+ -+ ret = copy_partition(pf_dev, data.src_device, data.src_part, data.dest_device, data.dest_part); -+ break; -+ } -+ -+ case AMI_IOC_READ_BAR: -+ { -+ /* -+ * `arg` is a pointer to the `ami_ioc_bar_data` struct. -+ */ -+ uint32_t *buf = NULL; -+ struct ami_ioc_bar_data data = { 0 }; -+ -+ /* Read data payload. */ -+ if (copy_from_user(&data, (struct ami_ioc_bar_data*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ /* Check permissions. */ -+ if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -+ ret = -EPERM; -+ goto done; -+ } -+ -+ if ((data.num <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* Allocate memory for response buffer. */ -+ buf = vzalloc(data.num * sizeof(uint32_t)); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ /* We will write the response to the userspace address. */ -+ ret = read_pcie_bar(pf_dev->pci, data.bar_idx, -+ data.offset, data.num, buf); -+ -+ if (!ret) -+ ret = copy_to_user((uint32_t*)data.addr, buf, -+ data.num * sizeof(uint32_t)); -+ -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_WRITE_BAR: -+ { -+ /* -+ * `arg` is a pointer to the `ami_ioc_bar_data` struct. -+ */ -+ uint32_t *buf = NULL; -+ struct ami_ioc_bar_data data = { 0 }; -+ -+ /* Read data payload. */ -+ if (copy_from_user(&data, (struct ami_ioc_bar_data*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ /* Check permissions. */ -+ if (!(data.cap_override || IS_ROOT_USER(current_uid().val, current_euid().val))) { -+ ret = -EPERM; -+ goto done; -+ } -+ -+ if ((data.num <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* Allocate memory for payload buffer. */ -+ buf = vzalloc(data.num * sizeof(uint32_t)); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ /* Copy payload data. */ -+ if (!copy_from_user(buf, (uint32_t*)data.addr, data.num * sizeof(uint32_t))) -+ ret = write_pcie_bar(pf_dev->pci, data.bar_idx, -+ data.offset, data.num, buf); -+ else -+ ret = -EFAULT; -+ -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_GET_SENSOR_VALUE: -+ { -+ /* `arg` is a pointer to `struct ami_ioc_sensor_value` */ -+ struct ami_ioc_sensor_value data = { 0 }; -+ enum hwmon_sensor_types hwmon_type = 0; -+ uint32_t hwmon_attr = 0; -+ -+ if (copy_from_user(&data, (struct ami_ioc_sensor_value*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ /* Currently, only the instant sensor value is supported with this API. */ -+ switch (data.sensor_type) { -+ case IOC_SENSOR_TYPE_TEMP: -+ hwmon_type = hwmon_temp; -+ hwmon_attr = hwmon_temp_input; -+ break; -+ -+ case IOC_SENSOR_TYPE_POWER: -+ hwmon_type = hwmon_power; -+ hwmon_attr = hwmon_power_input; -+ break; -+ -+ case IOC_SENSOR_TYPE_CURRENT: -+ hwmon_type = hwmon_curr; -+ hwmon_attr = hwmon_curr_input; -+ break; -+ -+ case IOC_SENSOR_TYPE_VOLTAGE: -+ hwmon_type = hwmon_in; -+ hwmon_attr = hwmon_in_input; -+ break; -+ -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ -+ if (ret) -+ goto done; -+ -+ ret = read_sensor_val( -+ pf_dev, -+ hwmon_type, -+ hwmon_attr, -+ data.hwmon_channel, -+ &data.val, -+ data.status, -+ &data.fresh -+ ); -+ -+ if (!ret) -+ ret = copy_to_user((struct ami_ioc_sensor_value*)arg, -+ &data, sizeof(data)); -+ -+ break; -+ } -+ -+ case AMI_IOC_GET_FPT_HDR: -+ { -+ /* `arg` is a pointer to `struct ami_ioc_fpt_hdr_value` */ -+ struct ami_ioc_fpt_hdr_value data = { 0 }; -+ struct fpt_header hdr = { 0 }; -+ -+ /* Read data payload from user. */ -+ if (copy_from_user(&data, (struct ami_ioc_fpt_hdr_value*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ ret = read_fpt_hdr(pf_dev, data.boot_device, &hdr); -+ if (!ret) { -+ data.version = hdr.version; -+ data.hdr_size = hdr.header_size; -+ data.entry_size = hdr.entry_size; -+ data.num_entries = hdr.num_entries; -+ ret = copy_to_user((struct ami_ioc_fpt_hdr_value*)arg, -+ &data, sizeof(data)); -+ } -+ break; -+ } -+ -+ case AMI_IOC_GET_FPT_PARTITION: -+ { -+ /* `arg` is a pointer to `struct ami_ioc_fpt_partition_value` */ -+ struct ami_ioc_fpt_partition_value data = { 0 }; -+ struct fpt_partition partition = { 0 }; -+ -+ if (copy_from_user(&data, (struct ami_ioc_fpt_partition_value*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ ret = read_fpt_partition(pf_dev, -+ data.boot_device, -+ data.partition, -+ &partition); -+ if (!ret) { -+ data.type = partition.type; -+ data.base_addr = partition.base_addr; -+ data.partition_size = partition.partition_size; -+ ret = copy_to_user((struct ami_ioc_fpt_partition_value*)arg, -+ &data, sizeof(data)); -+ } -+ break; -+ } -+ -+ case AMI_IOC_READ_EEPROM: -+ { -+ struct ami_ioc_eeprom_payload data = { 0 }; -+ uint8_t *buf = NULL; -+ -+ /* Read data payload. */ -+ if (copy_from_user(&data, (struct ami_ioc_eeprom_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ if ((data.len <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* Allocate memory for response buffer. */ -+ buf = vzalloc(data.len * sizeof(uint8_t)); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ ret = eeprom_read(pf_dev->amc_ctrl_ctxt, buf, data.len, data.offset); -+ if (!ret) { -+ ret = copy_to_user((uint8_t*)data.addr, buf, -+ data.len * sizeof(uint8_t)); -+ } -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_WRITE_EEPROM: -+ { -+ struct ami_ioc_eeprom_payload data = { 0 }; -+ uint8_t *buf = NULL; -+ -+ /* Read data payload. */ -+ if (copy_from_user(&data, (struct ami_ioc_eeprom_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ if ((data.len <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* Allocate memory for payload buffer. */ -+ buf = vzalloc(data.len * sizeof(uint8_t)); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ /* Copy payload data. */ -+ if (!copy_from_user(buf, (uint8_t*)data.addr, data.len * sizeof(uint8_t))) -+ ret = eeprom_write(pf_dev->amc_ctrl_ctxt, buf, data.len, data.offset); -+ else -+ ret = -EFAULT; -+ -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_APP_SETUP: -+ switch ((enum ami_ioc_app_setup)arg) { -+ case IOC_APP_SETUP_REGISTER: -+ ret = add_pf_dev_app(pf_dev, get_current()); -+ break; -+ -+ case IOC_APP_SETUP_DEREGISTER: -+ ret = delete_pf_dev_app(pf_dev, get_current()); -+ break; -+ -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ break; -+ -+ case AMI_IOC_READ_MODULE: -+ { -+ struct ami_ioc_module_payload data = { 0 }; -+ uint8_t *buf = NULL; -+ -+ /* Read data payload. */ -+ if (copy_from_user(&data, (struct ami_ioc_module_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ if ((data.len <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* Allocate memory for response buffer. */ -+ buf = vzalloc(data.len * sizeof(uint8_t)); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ ret = module_read( -+ pf_dev->amc_ctrl_ctxt, -+ data.device_id, -+ data.page, -+ data.offset, -+ buf, -+ data.len -+ ); -+ -+ if (!ret) { -+ ret = copy_to_user((uint8_t*)data.addr, buf, -+ data.len * sizeof(uint8_t)); -+ } -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_WRITE_MODULE: -+ { -+ struct ami_ioc_module_payload data = { 0 }; -+ uint8_t *buf = NULL; -+ -+ /* Read data payload. */ -+ if (copy_from_user(&data, (struct ami_ioc_module_payload*)arg, sizeof(data))) { -+ ret = -EFAULT; -+ goto done; -+ } -+ -+ if ((data.len <= 0) || (data.addr == 0)) { -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ /* Allocate memory for payload buffer. */ -+ buf = vzalloc(data.len * sizeof(uint8_t)); -+ -+ if (!buf) { -+ ret = -ENOMEM; -+ goto done; -+ } -+ -+ /* Copy payload data. */ -+ if (!copy_from_user(buf, (uint8_t*)data.addr, data.len * sizeof(uint8_t))) -+ ret = module_write( -+ pf_dev->amc_ctrl_ctxt, -+ data.device_id, -+ data.page, -+ data.offset, -+ buf, -+ data.len -+ ); -+ else -+ ret = -EFAULT; -+ -+ vfree(buf); -+ break; -+ } -+ -+ case AMI_IOC_DEBUG_VERBOSITY: -+ ret = submit_gcq_command( -+ pf_dev->amc_ctrl_ctxt, -+ GCQ_SUBMIT_CMD_DEBUG_VERBOSITY, -+ (uint8_t)arg, -+ NULL, -+ 0 -+ ); -+ break; -+ -+ default: -+ PR_ERR("Unknown command, do nothing"); -+ ret = -ENOTTY; -+ break; -+ } -+ -+ done: -+ if (efd_ctx) -+ eventfd_ctx_put(efd_ctx); -+ -+ up(&(pf_dev->ioctl_sema)); -+ return ret; -+ } -+ -+ /* -+ * Create a character device. -+ */ -+ int create_cdev(unsigned baseminor, struct drv_cdev_struct *drv_cdev, -+ struct device *parent, const struct file_operations *fops) -+ { -+ int ret = 0; -+ bool cls_created = false; -+ -+ /* parent may be NULL */ -+ if (!drv_cdev || !fops) { -+ return -EINVAL; -+ } -+ -+ /* Allocate chrdev region */ -+ drv_cdev->count = DEFAULT_CDEV_COUNT; -+ if(dev_major) { -+ drv_cdev->cdev_num = MKDEV(dev_major, baseminor); -+ ret = register_chrdev_region(drv_cdev->cdev_num, DEFAULT_CDEV_COUNT, -+ (const char*)DEFAULT_DEVICE_NAME); -+ } else { -+ /* This is the first device. */ -+ ret = alloc_chrdev_region(&(drv_cdev->cdev_num), baseminor, -+ DEFAULT_CDEV_COUNT, (const char*)DEFAULT_DEVICE_NAME); -+ dev_major = MAJOR(drv_cdev->cdev_num); -+ } -+ -+ if(ret) -+ goto fail; -+ -+ /* If first device, create class. */ -+ strncpy(drv_cdev->drv_cls_str, (const char*)DEFAULT_CLS_NAME, CLS_STR_SIZE); -+ -+ if(!drv_cdev->dev_class) { -+ cls_created = true; -+ drv_cdev->dev_class = class_create(THIS_MODULE, drv_cdev->drv_cls_str); -+ if (IS_ERR(drv_cdev->dev_class)) { -+ ret = PTR_ERR(drv_cdev->dev_class); -+ PR_ERR("Failed to create class %s. ret : %d", -+ drv_cdev->drv_cls_str, ret); -+ goto unreg_cdev_reg; -+ } -+ drv_cdev->dev_class->devnode = devnode; -+ } -+ -+ /* Create device */ -+ snprintf(drv_cdev->dev_name, DEV_NAME_SIZE, "%s%d", DEFAULT_DEVICE_NAME, baseminor); -+ drv_cdev->device = device_create(drv_cdev->dev_class, NULL, -+ drv_cdev->cdev_num, NULL, drv_cdev->dev_name); -+ if (IS_ERR(drv_cdev->device)) { -+ ret = PTR_ERR(drv_cdev->device); -+ PR_ERR("Failed to create device %s. ret : %d", drv_cdev->dev_name, ret); -+ goto del_class; -+ } -+ -+ /* Initialize the cdev structure */ -+ cdev_init(&(drv_cdev->cdev), fops); -+ drv_cdev->cdev.owner = THIS_MODULE; -+ drv_cdev->cdev.ops = fops; -+ -+ /* -+ * Setting the parent is necessary so that the kobject is referenced -+ * appropriately and the parent is not freed before the cdev. -+ */ -+ if (parent) -+ cdev_set_parent(&drv_cdev->cdev, &parent->kobj); -+ -+ /* Register cdev to the kernel */ -+ ret = cdev_add(&(drv_cdev->cdev), drv_cdev->cdev_num, drv_cdev->count); -+ if (ret) { -+ PR_ERR("Failed to register cdev to the kernel, err_code : %d", ret); -+ goto del_device; -+ } -+ -+ return SUCCESS; -+ -+ del_device: -+ device_destroy(drv_cdev->dev_class, drv_cdev->cdev_num); -+ -+ del_class: -+ if(cls_created) -+ class_destroy(drv_cdev->dev_class); -+ -+ unreg_cdev_reg: -+ unregister_chrdev_region(drv_cdev->cdev_num, DEFAULT_CDEV_COUNT); -+ -+ fail: -+ return ret; -+ } -+ -\ No newline at end of file -diff --git a/sw/AMI/driver/ami_cdev.h b/sw/AMI/driver/ami_cdev.h -index d58e3e6..39a9b8b 100755 ---- a/sw/AMI/driver/ami_cdev.h -+++ b/sw/AMI/driver/ami_cdev.h -@@ -43,6 +43,7 @@ - * @cap_override: Bypass permission checks. This may not apply to all IOCTL's. - * @efd: File descriptor for event notifications (used for progress reporting when - * performing long running operations like PDI downloads) - optional -+ * @partial: Flag to indicate whether the PDI is partial or full. - * - * Note that addr can be an address to any arbitrary data type, - * depending on the context. This struct is reused for the boot select -@@ -63,6 +64,7 @@ struct ami_ioc_data_payload { - uint32_t dest_part; - bool cap_override; - int efd; -+ bool partial; - }; - - /** -diff --git a/sw/AMI/driver/ami_program.c b/sw/AMI/driver/ami_program.c -index cd0bafc..2951de8 100644 ---- a/sw/AMI/driver/ami_program.c -+++ b/sw/AMI/driver/ami_program.c -@@ -29,6 +29,7 @@ - * @boot_device: Target boot device. - * @partition: Partition number to flash. - * @efd_ctx: eventfd context for reporting progress (optional). -+ * @partial: Flag to indicate partial download. - * - * If `partition` is equal to `FPT_UPDATE_MAGIC` will update the FPT. - * -@@ -71,7 +72,7 @@ static int do_image_download(struct amc_control_ctxt *amc_ctrl_ctxt, uint8_t *bu - bytes_to_write = (size - bytes_written); - else - bytes_to_write = (PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER); -- -+ - /* - * Don't invalidate the boot tag if we're updating the FPT - * or if there is only a single chunk. -@@ -153,23 +154,121 @@ static int do_image_download(struct amc_control_ctxt *amc_ctrl_ctxt, uint8_t *bu - return ret; - } - -+static int do_image_download_partial(struct amc_control_ctxt *amc_ctrl_ctxt, uint8_t *buf, uint32_t size, -+ uint8_t boot_device, uint32_t partition, struct eventfd_ctx *efd_ctx) -+{ -+ int ret = SUCCESS; -+ uint16_t chunk = 0; -+ uint32_t bytes_written = 0; -+ uint32_t bytes_to_write = 0; -+ printk("Size: %d\n", size); -+ uint16_t num_chunks = (size + ((PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER) - 1)) / -+ (PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER); -+ printk("num_chunks = %d\n", num_chunks); -+ if (!size || !amc_ctrl_ctxt || !buf) -+ return -EINVAL; -+ -+ AMI_VDBG( -+ amc_ctrl_ctxt, -+ "Attempting to download partial PDI with image size %d, num_chunks = %d", size, num_chunks -+ ); -+ -+ while (bytes_written < size) { -+ -+ if ((PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER) > (size - bytes_written)) -+ bytes_to_write = (size - bytes_written); -+ else -+ bytes_to_write = (PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER); -+ -+ /* -+ * This will copy the bitstream buffer into shared memory and submit -+ * the GCQ command. Using `flags` to pass in partition and chunk numbers. -+ */ -+ ret = submit_gcq_command(amc_ctrl_ctxt, GCQ_SUBMIT_CMD_DOWNLOAD_PARTIAL_PDI, -+ MK_PDI_FLAGS(boot_device, partition, chunk, false), -+ &buf[bytes_written], bytes_to_write); -+ -+ if (ret) -+ break; -+ -+ if (efd_ctx) -+ eventfd_signal(efd_ctx, bytes_to_write); -+ -+ AMI_VDBG( -+ amc_ctrl_ctxt, -+ "Done with chunk %d", -+ chunk -+ ); -+ chunk++; -+ bytes_written += bytes_to_write; -+ } -+ -+ chunk = 0; -+ bytes_written = 0; -+ bytes_to_write = 0; -+ -+ while (bytes_written < size) { -+ -+ if ((PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER) > (size - bytes_written)) -+ bytes_to_write = (size - bytes_written); -+ else -+ bytes_to_write = (PDI_CHUNK_SIZE * PDI_CHUNK_MULTIPLIER); -+ -+ /* -+ * This will copy the bitstream buffer into shared memory and submit -+ * the GCQ command. Using `flags` to pass in partition and chunk numbers. -+ */ -+ ret = submit_gcq_command(amc_ctrl_ctxt, GCQ_SUBMIT_CMD_DOWNLOAD_PARTIAL_PDI, -+ MK_PDI_FLAGS(boot_device, partition, chunk, (chunk == (num_chunks - 1))), -+ &buf[bytes_written], bytes_to_write); -+ -+ if (ret) -+ break; -+ -+ if (efd_ctx) -+ eventfd_signal(efd_ctx, bytes_to_write); -+ -+ AMI_VDBG( -+ amc_ctrl_ctxt, -+ "Done with chunk %d", -+ chunk -+ ); -+ chunk++; -+ bytes_written += bytes_to_write; -+ } -+ -+ if (ret) -+ AMI_ERR(amc_ctrl_ctxt, "Failed to download partial PDI, ret code: %d", ret); -+ -+ return ret; -+} -+ - /* - * Download a PDI bitstream. - */ - int download_pdi(struct amc_control_ctxt *amc_ctrl_ctxt, uint8_t *buf, uint32_t size, -- uint8_t boot_device, uint32_t partition, struct eventfd_ctx *efd_ctx) -+ uint8_t boot_device, uint32_t partition, struct eventfd_ctx *efd_ctx, uint8_t partial) - { - if (!amc_ctrl_ctxt || !size || !buf || (partition == FPT_UPDATE_MAGIC)) - return -EINVAL; -- -- return do_image_download( -- amc_ctrl_ctxt, -- buf, -- size, -- boot_device, -- partition, -- efd_ctx -- ); -+ if (!partial) -+ return do_image_download( -+ amc_ctrl_ctxt, -+ buf, -+ size, -+ boot_device, -+ partition, -+ efd_ctx -+ ); -+ else -+ return do_image_download_partial( -+ amc_ctrl_ctxt, -+ buf, -+ size, -+ boot_device, -+ partition, -+ efd_ctx -+ ); - } - - /* -diff --git a/sw/AMI/driver/ami_program.h b/sw/AMI/driver/ami_program.h -index 87da637..4bec2d8 100644 ---- a/sw/AMI/driver/ami_program.h -+++ b/sw/AMI/driver/ami_program.h -@@ -66,11 +66,12 @@ - * @boot_device: Target boot device. - * @partition: Partition number to flash. - * @efd_ctx: eventfd context for reporting progress (optional). -+ * @partial: Flag to indicate whether the PDI is partial or full. - * - * Return: 0 or negative error code. - */ - int download_pdi(struct amc_control_ctxt *amc_ctrl_ctxt, uint8_t *buf, uint32_t size, -- uint8_t boot_device, uint32_t partition, struct eventfd_ctx *efd_ctx); -+ uint8_t boot_device, uint32_t partition, struct eventfd_ctx *efd_ctx, uint8_t partial); - - /** - * update_fpt() - Download a PDI containing an FPT onto a device. diff --git a/deploy/base_pdi/build.py b/deploy/base_pdi/build.py deleted file mode 100644 index 37934ce7..00000000 --- a/deploy/base_pdi/build.py +++ /dev/null @@ -1,225 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -import argparse -import glob -import subprocess -import shutil -import os - -ROOT_PATH = os.path.realpath(".") -DESIGN_PDI_PATH = os.path.join(ROOT_PATH, "..") -RESOURCES_PATH = os.path.realpath("../../submodules/v80-vitis-flow/resources/") -COMPUTE_EXAMPLE_DIR = os.path.realpath("../../examples/05_perf/") -DEPLOY_PROJECT_COMPUTE = os.path.join(os.getcwd(), "deploy_project_compute") -HLS_DIR_COMPUTE = os.path.join(DEPLOY_PROJECT_COMPUTE, "hls/") -AVED_ROOT_DIR_COMPUTE = os.path.join(DEPLOY_PROJECT_COMPUTE, "build/v80-vitis-flow/build/aved-fork/hw/amd_v80_gen5x8_24.1/") -AVED_SRC_DIR_COMPUTE = os.path.join(AVED_ROOT_DIR_COMPUTE, "src/") -AVED_IPREPO_DIR_COMPUTE = os.path.join(AVED_SRC_DIR_COMPUTE, "iprepo/") -LINKER_SRC_DIR_COMPUTE = os.path.join(DEPLOY_PROJECT_COMPUTE, "build/v80-vitis-flow/") -LINKER_BUILD_DIR_COMPUTE = os.path.join(LINKER_SRC_DIR_COMPUTE, "build/") -AVED_DIR_SUBMODULE_COMPUTE = os.path.join(DEPLOY_PROJECT_COMPUTE, LINKER_SRC_DIR_COMPUTE, "submodules/aved/") -AVED_DIR_COMPUTE_BUILD = os.path.join(DEPLOY_PROJECT_COMPUTE, LINKER_SRC_DIR_COMPUTE, "build/aved-fork/") -CONFIG_FILE_PATH_COMPUTE = os.path.join(DEPLOY_PROJECT_COMPUTE, "config.cfg") - -TCL_DIR = os.path.realpath("./tcl/") -CREATE_DESIGN_DIR = os.path.join(TCL_DIR, "create_design.tcl") -NOC_SOLUTION_DIR = os.path.join(TCL_DIR, "noc_solution.tcl") -EXPORT_NOC_DIR = os.path.join(TCL_DIR, "export_noc.tcl") -SEGMENTED_IMG_BIF = os.path.join(TCL_DIR, "segmented_img.bif") - - - -def run_linker(CONFIG_PATH, KERNEL_PATHS): - os.chdir(LINKER_BUILD_DIR_COMPUTE) - cmd = [ - "./v80++-linker", - "--cfg", CONFIG_PATH, - "--platform", "hw", - "--segmented" - ] - cmd.append("--kernels") - cmd.extend(KERNEL_PATHS) - - subprocess.run(cmd, check=True) - print("Linker run completed.") - -def run_hw(): - os.chdir(AVED_ROOT_DIR_COMPUTE) - subprocess.run(["./build_all.sh"], check=False) - print("Hardware build completed.") - -def setup_step(platform): - if platform == "compute": - os.chdir(COMPUTE_EXAMPLE_DIR) - subprocess.run(["make", "setup"]) - shutil.copytree(COMPUTE_EXAMPLE_DIR, DEPLOY_PROJECT_COMPUTE, dirs_exist_ok=True) - elif platform == "eth": - print("Eth mode not supported yet.") - else: - raise ValueError("Invalid platform specified.") - -def hls_step(platform): - if platform == "compute": - os.chdir(DEPLOY_PROJECT_COMPUTE) - subprocess.run(["make", "hls"]) - elif platform == "eth": - print("Eth mode not supported yet.") - else: - raise ValueError("Invalid platform specified.") - -def linker_step(platform): - if platform == "compute": - os.chdir(LINKER_SRC_DIR_COMPUTE) - os.makedirs("build", exist_ok=True) - subprocess.run(["cmake", ".."], cwd="build", check=True) - subprocess.run(["make", "-j", "4"], cwd="build", check=True) - shutil.copytree(AVED_DIR_SUBMODULE_COMPUTE, AVED_DIR_COMPUTE_BUILD, dirs_exist_ok=True) - shutil.copy(CREATE_DESIGN_DIR, os.path.join(AVED_SRC_DIR_COMPUTE, "create_design.tcl")) - shutil.copy(NOC_SOLUTION_DIR, os.path.join(AVED_SRC_DIR_COMPUTE, "noc_solution.tcl")) - shutil.copy(EXPORT_NOC_DIR, os.path.join(AVED_SRC_DIR_COMPUTE, "export_noc.tcl")) - shutil.copy(SEGMENTED_IMG_BIF, os.path.join(AVED_ROOT_DIR_COMPUTE, "segmented_img.bif")) - # Copying HLS to iprepo - shutil.copytree(HLS_DIR_COMPUTE, AVED_IPREPO_DIR_COMPUTE, dirs_exist_ok=True) - build_dirs = [d for d in glob.glob(os.path.join(HLS_DIR_COMPUTE, "build_*")) - if os.path.isdir(d)] - sol1_paths = [os.path.join(d, "sol1") for d in build_dirs] - run_linker(CONFIG_FILE_PATH_COMPUTE, sol1_paths) - shutil.copy(os.path.join(LINKER_BUILD_DIR_COMPUTE, "run_pre.tcl"), AVED_SRC_DIR_COMPUTE) - shutil.copy(os.path.join(RESOURCES_PATH, "run_post.tcl"), AVED_SRC_DIR_COMPUTE) - elif platform == "eth": - print("Eth mode not supported yet.") - else: - raise ValueError("Invalid platform specified.") - -def hw_step(platform): - if platform == "compute": - run_hw() - elif platform == "eth": - print("Eth mode not supported yet.") - else: - raise ValueError("Invalid platform specified.") - -def generate_pdi_step(platform): - if platform == "compute": - os.chdir(AVED_ROOT_DIR_COMPUTE) - # No FPT generation for now - subprocess.run(["bootgen", "-arch", "versal", "-image", "segmented_img.bif", "-w", "-o", "design.pdi"], check=True) - shutil.copy(os.path.join(AVED_ROOT_DIR_COMPUTE, "design.pdi"), os.path.join(ROOT_PATH, "../design.pdi")) - elif platform == "eth": - print("Eth mode not supported yet.") - else: - raise ValueError("Invalid platform specified.") - -def generate_noc_solution_step(platform): - if platform == "compute": - os.chdir(AVED_ROOT_DIR_COMPUTE) - # subprocess.run(["vivado", "-mode", "tcl", "-source", "src/export_noc.tcl"], check=True) - # shutil.copy(os.path.join(AVED_ROOT_DIR_COMPUTE, "noc_sol.ncr"), os.path.join(RESOURCES_PATH, "noc_sol_compute.ncr")) - shutil.copy(os.path.join(RESOURCES_PATH, "noc_sol.ncr"), os.path.join(RESOURCES_PATH, "noc_sol_compute.ncr")) - elif platform == "eth": - print("Eth mode not supported yet.") - else: - raise ValueError("Invalid platform specified.") - -STEPS = [ - ("setup_step", setup_step), - ("hls_step", hls_step), - ("linker_step", linker_step), - ("hw_step", hw_step), - ("generate_pdi_step", generate_pdi_step), - ("generate_noc_solution_step", generate_noc_solution_step) -] - -def main(): - parser = argparse.ArgumentParser(description="Platform build driver with step range.") - parser.add_argument("--platform", choices=["compute", "eth"], required=True) - parser.add_argument("--from_step", type=str, default=STEPS[0][0], help="Step name or index to start from.") - parser.add_argument("--to_step", type=str, help="(Optional) Step name or index to end at.") - parser.add_argument("--list_steps", action="store_true", help="List all available steps and exit.") - args = parser.parse_args() - - if args.list_steps: - print("Available steps:") - for i, (name, _) in enumerate(STEPS, 1): - print(f"{i}. {name}") - return - - if args.platform != "compute": - print("Eth mode not supported yet.") - return - - def step_index(step_id): - if step_id.isdigit(): - idx = int(step_id) - 1 - else: - idx = next((i for i, (name, _) in enumerate(STEPS) if name == step_id), -1) - if idx < 0 or idx >= len(STEPS): - raise ValueError(f"Invalid step: {step_id}") - return idx - - from_idx = step_index(args.from_step) - to_idx = step_index(args.to_step) if args.to_step else len(STEPS) - 1 - - if from_idx > to_idx: - raise ValueError("--from_step must come before or equal to --to_step") - - for i in range(from_idx, to_idx + 1): - name, func = STEPS[i] - print(f"\n--- Running Step {i + 1}: {name} ---") - func(args.platform) - - # if args.platform == "compute": - # print("Running in compute mode.") - # os.chdir(COMPUTE_EXAMPLE_DIR) - # subprocess.run(["make", "setup"]) - # shutil.copytree(COMPUTE_EXAMPLE_DIR, DEPLOY_PROJECT_COMPUTE, dirs_exist_ok=True) - # os.chdir(DEPLOY_PROJECT_COMPUTE) - # # Setup the deployment project - # subprocess.run(["make", "hls"]) - # os.chdir(LINKER_SRC_DIR_COMPUTE) - # os.makedirs("build", exist_ok=True) - # subprocess.run(["cmake", ".."], cwd="build", check=True) - # subprocess.run(["make", "-j", "4"], cwd="build", check=True) - # shutil.copytree(AVED_DIR_SUBMODULE_COMPUTE, AVED_DIR_COMPUTE_BUILD, dirs_exist_ok=True) - # shutil.copy(CREATE_DESIGN_DIR, os.path.join(AVED_SRC_DIR_COMPUTE, "create_design.tcl")) - # shutil.copy(NOC_SOLUTION_DIR, os.path.join(AVED_SRC_DIR_COMPUTE, "noc_solution.tcl")) - # shutil.copy(EXPORT_NOC_DIR, os.path.join(AVED_SRC_DIR_COMPUTE, "export_noc.tcl")) - # shutil.copy(SEGMENTED_IMG_BIF, os.path.join(AVED_ROOT_DIR_COMPUTE, "segmented_img.bif")) - # # Copying HLS to iprepo - # shutil.copytree(HLS_DIR_COMPUTE, AVED_IPREPO_DIR_COMPUTE, dirs_exist_ok=True) - # build_dirs = [d for d in glob.glob(os.path.join(HLS_DIR_COMPUTE, "build_*")) - # if os.path.isdir(d)] - # sol1_paths = [os.path.join(d, "sol1") for d in build_dirs] - # run_linker(CONFIG_FILE_PATH_COMPUTE, sol1_paths) - # shutil.copy(os.path.join(LINKER_BUILD_DIR_COMPUTE, "run_pre.tcl"), AVED_SRC_DIR_COMPUTE) - # run_hw() - # os.chdir(AVED_ROOT_DIR_COMPUTE) - # # No FPT generation for now - # subprocess.run(["bootgen", "-arch", "versal", "-image", "segmented_img.bif", "-w", "-o", "design.pdi"], check=True) - # shutil.copy(os.path.join(AVED_ROOT_DIR_COMPUTE, "design.pdi"), os.path.join(ROOT_PATH, "design.pdi")) - # # Generate NoC solution from the vivado project - # subprocess.run(["vivado", "-mode", "batch", "-source", "export_noc.tcl"], check=True) - # shutil.copy(os.path.join(AVED_ROOT_DIR_COMPUTE, "noc_sol.ncr"), os.path.join(RESOURCES_PATH, "noc_sol_compute.ncr")) - # elif args.platform == "eth": - # print("Eth mode not supported yet.") - -if __name__ == "__main__": - main() diff --git a/deploy/base_pdi/tcl/create_design.tcl b/deploy/base_pdi/tcl/create_design.tcl deleted file mode 100644 index be0b86c1..00000000 --- a/deploy/base_pdi/tcl/create_design.tcl +++ /dev/null @@ -1,76 +0,0 @@ -# (c) Copyright 2024, Advanced Micro Devices, Inc. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -############################################################ - -set src_dir [file dirname [file normalize [info script]]] -set cwd [pwd] -set design_name "amd_v80_gen5x8_24.1" -set bd_name "top" - -proc do_aved_create_design { } { - global bd_name - global src_dir - global design_name - # Create the project targeting its part - create_project prj "[pwd]/build" -part xcv80-lsva4737-2MHP-e-S -force - - - # Set project IP repositories - set_property ip_repo_paths "${src_dir}/iprepo" [current_project] - update_ip_catalog - - # Create block diagram - create_bd_design ${bd_name} - current_bd_design ${bd_name} - - # Add base to block diagram - source "$src_dir/bd/create_bd_design.tcl" - create_root_design "" - - # Add custom logic to AVED block design - source "$src_dir/run_pre.tcl" - run_pre "" - - # Add deployment logic to AVED block design - source "$src_dir/noc_solution.tcl" - run_noc_solution "" - - # Write the block diagram wrapper and set it as design top - add_files -norecurse [make_wrapper -files [get_files "${bd_name}.bd"] -top] - update_compile_order -fileset sources_1 - update_compile_order -fileset sim_1 - set_property top top_wrapper [current_fileset] - - # Add constraint and hook files - import_files -fileset constrs_1 -norecurse "$src_dir/constraints/impl.xdc" - import_files -fileset constrs_1 -norecurse "$src_dir/constraints/impl.pins.xdc" - import_files -fileset utils_1 -norecurse "$src_dir/constraints/opt.post.tcl" - import_files -fileset utils_1 -norecurse "$src_dir/constraints/place.pre.tcl" - import_files -fileset utils_1 -norecurse "$src_dir/constraints/write_device_image.pre.tcl" - - set_property -dict { used_in_synthesis false processing_order NORMAL } [get_files *impl.xdc] - set_property -dict { used_in_synthesis false processing_order NORMAL } [get_files *impl.pins.xdc] - - set_property STEPS.OPT_DESIGN.TCL.POST [get_files *opt.post.tcl] [get_runs impl_1] - set_property STEPS.PLACE_DESIGN.TCL.PRE [get_files *place.pre.tcl] [get_runs impl_1] - set_property STEPS.WRITE_DEVICE_IMAGE.TCL.PRE [get_files *write_device_image.pre.tcl] [get_runs impl_1] -} - -do_aved_create_design diff --git a/deploy/base_pdi/tcl/export_noc.tcl b/deploy/base_pdi/tcl/export_noc.tcl deleted file mode 100644 index 76e5feb3..00000000 --- a/deploy/base_pdi/tcl/export_noc.tcl +++ /dev/null @@ -1,27 +0,0 @@ -deploy/base_pdi/build.py# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -set build_dir "build" -open_project $build_dir/prj.xpr -open_run synth_1 -set_property lock true [get_noc_net_routes -of [get_noc_logical_paths -filter {initial_boot == 1}]] -set_property lock true [get_noc_net_routes -of [get_noc_logical_paths -of [get_noc_logical_instances *n?u128*]]] -write_noc_solution -file noc_sol.ncr -exit diff --git a/deploy/base_pdi/tcl/segmented_img.bif b/deploy/base_pdi/tcl/segmented_img.bif deleted file mode 100644 index 9ae9d277..00000000 --- a/deploy/base_pdi/tcl/segmented_img.bif +++ /dev/null @@ -1,13 +0,0 @@ -all: -{ - image { - { type=bootimage, file=./build/prj.runs/impl_1/top_wrapper_boot.pdi } - } - image { - { type=bootimage, file=./build/prj.runs/impl_1/top_wrapper_pld.pdi } - } - image { - id = 0x1c000000, name=rpu_subsystem, delay_handoff - { core=r5-0, file=./build/amc.elf } - } -} diff --git a/deploy/package/package.py b/deploy/package/package.py deleted file mode 100755 index abe2469d..00000000 --- a/deploy/package/package.py +++ /dev/null @@ -1,569 +0,0 @@ -#!/usr/bin/env python3 - -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -import os -import sys -import subprocess -import shutil -import argparse -from datetime import datetime - -PACKAGE_NAME = "amd-vrt" -MAINTAINER = "AMD " -DEB_ARCH = "amd64" -RPM_ARCH = "x86_64" -DESCRIPTION = "AMD V80 Runtime API, SMI and PCIe driver package" - -# Debian-like dependencies (as given) -DEB_DEPENDS = "libxml2, libzmq3-dev, libjsoncpp-dev" - -# Rough RPM equivalents (adjust if needed in your environment) -RPM_REQUIRES = [ - "libxml2", - "czmq", # if you actually use libzmq directly, use 'zeromq' or 'zeromq-libs' - "jsoncpp", -] - -def run_command(cmd, cwd=None, env=None): - try: - result = subprocess.run( - cmd, shell=True, check=True, text=True, - stdout=subprocess.PIPE, stderr=subprocess.PIPE, cwd=cwd, env=env - ) - return result.stdout - except subprocess.CalledProcessError as e: - print(f"Error executing command: {cmd}") - print(f"STDERR:\n{e.stderr}") - sys.exit(1) - -def get_version_from_header(repo_root): - """Extract version from vrt_version.hpp header file""" - version_file = os.path.join(repo_root, "vrt", "include", "api", "vrt_version.hpp") - if not os.path.exists(version_file): - print(f"Warning: Version file not found at {version_file}") - return "1.0.0" - - major = "1"; minor = "0"; patch = "0"; git_tag = "" - try: - with open(version_file, "r") as f: - content = f.read() - import re - m = re.search(r'#define\s+VRT_VERSION_MAJOR\s+(\d+)', content); major = m.group(1) if m else major - m = re.search(r'#define\s+VRT_VERSION_MINOR\s+(\d+)', content); minor = m.group(1) if m else minor - m = re.search(r'#define\s+VRT_VERSION_PATCH\s+(\d+)', content); patch = m.group(1) if m else patch - m = re.search(r'#define\s+GIT_TAG\s+"([^"]+)"', content); git_tag = m.group(1) if m else "" - - version = f"{major}.{minor}.{patch}" - if version == "1.0.0" and git_tag.startswith("v"): - version = git_tag[1:] - print(f"Using version from GIT_TAG: {version}") - else: - print(f"Extracted version from components: {version}") - return version - except Exception as e: - print(f"Error extracting version from header file: {e}") - return "1.0.0" - -def detect_packaging_format(forced=None): - """ - Return 'deb' or 'rpm'. - If --format is provided, honor it. Otherwise detect via /etc/os-release. - """ - if forced: - return forced - os_release = "/etc/os-release" - if os.path.exists(os_release): - data = open(os_release).read().lower() - if any(k in data for k in ["ubuntu", "debian"]): - return "deb" - if any(k in data for k in ["rocky", "rhel", "red hat", "centos", "almalinux", "fedora"]): - return "rpm" - # Fallback: try tools - if shutil.which("dpkg-deb"): - return "deb" - if shutil.which("rpmbuild"): - return "rpm" - print("Could not detect packaging system. Install dpkg-deb or rpmbuild, or pass --format deb|rpm.") - sys.exit(2) - -def create_stage_tree(repo_root): - """Create the staging directory with the final filesystem layout""" - timestamp = datetime.now().strftime("%Y-%m-%d-%H-%M-%S") - out_dir = os.path.join(repo_root, "deploy", "output") - os.makedirs(out_dir, exist_ok=True) - stage_dir = os.path.join(out_dir, f"{PACKAGE_NAME}-stage-{timestamp}") - os.makedirs(stage_dir, exist_ok=True) - - # Create common dirs - for d in [ - "usr/local/bin", - "usr/local/lib", - "usr/local/vrt/include", - "usr/src/pcie-hotplug-drv", - "opt/amd/vrt", - ]: - os.makedirs(os.path.join(stage_dir, d), exist_ok=True) - - return stage_dir - -def copy_design_pdi(repo_root, stage_dir): - pdi_src = os.path.join(repo_root, "deploy", "design.pdi") - pdi_dst = os.path.join(stage_dir, "opt/amd/vrt/design.pdi") - if os.path.exists(pdi_src): - shutil.copy2(pdi_src, pdi_dst) - print("design.pdi copied to package") - else: - print(f"Warning: design.pdi not found at {pdi_src}") - -def build_and_copy_vrt(repo_root, stage_dir): - vrt_dir = os.path.join(repo_root, "vrt") - build_dir = os.path.join(vrt_dir, "build") - if os.path.exists(build_dir): - shutil.rmtree(build_dir) - os.makedirs(build_dir, exist_ok=True) - run_command("cmake ..", cwd=build_dir) - run_command("make -j$(nproc)", cwd=build_dir) - - lib_dir = os.path.join(build_dir, "lib") - if os.path.isdir(lib_dir): - for lib_file in os.listdir(lib_dir): - if lib_file.startswith("libvrt") and (lib_file.endswith(".so") or lib_file.endswith(".a")): - shutil.copy2(os.path.join(lib_dir, lib_file), os.path.join(stage_dir, "usr/local/lib", lib_file)) - - include_src = os.path.join(vrt_dir, "include") - include_dst = os.path.join(stage_dir, "usr/local/vrt/include") - if os.path.exists(include_src): - for root, _, files in os.walk(include_src): - for file in files: - if file.endswith((".h", ".hpp")): - rel = os.path.relpath(root, include_src) - dst_dir = os.path.join(include_dst, rel) - os.makedirs(dst_dir, exist_ok=True) - shutil.copy2(os.path.join(root, file), os.path.join(dst_dir, file)) - - scripts_src = os.path.join(vrt_dir, "scripts") - if os.path.exists(scripts_src): - scripts_dst = os.path.join(stage_dir, "usr/local/vrt") - os.makedirs(scripts_dst, exist_ok=True) - for item in os.listdir(scripts_src): - s = os.path.join(scripts_src, item) - d = os.path.join(scripts_dst, item) - if os.path.isfile(s): - shutil.copy2(s, d) - # make script executable if it looks like one - if s.endswith((".sh", ".py")) or os.access(s, os.X_OK): - os.chmod(d, 0o755) - - print("VRT API built and files copied to stage") - -def build_and_copy_smi(repo_root, stage_dir): - smi_dir = os.path.join(repo_root, "smi") - build_dir = os.path.join(smi_dir, "build") - if os.path.exists(build_dir): - shutil.rmtree(build_dir) - os.makedirs(build_dir, exist_ok=True) - run_command("cmake ..", cwd=build_dir) - run_command("make -j$(nproc)", cwd=build_dir) - - # find -smi binaries (incl. v80-smi) - for root, _, files in os.walk(build_dir): - for f in files: - full = os.path.join(root, f) - if (f == "v80-smi" or f.endswith("-smi")) and os.access(full, os.X_OK): - print(f"Found SMI binary: {f}") - dst = os.path.join(stage_dir, "usr/local/bin", f) - shutil.copy2(full, dst) - os.chmod(dst, 0o755) - - print("SMI CLI built and files copied to stage") - -def copy_pcie_driver(repo_root, stage_dir): - src = os.path.join(repo_root, "submodules/pcie-hotplug-drv") - dst = os.path.join(stage_dir, "usr/src/pcie-hotplug-drv") - if not os.path.exists(src): - print(f"Warning: PCIe driver directory not found at {src}") - return - for item in os.listdir(src): - s = os.path.join(src, item); d = os.path.join(dst, item) - if os.path.isdir(s): - shutil.copytree(s, d, symlinks=True) - else: - shutil.copy2(s, d) - print("PCIe hotplug driver source copied to stage") - -# ----------------------- DEB PACKAGING ----------------------- - -def write_debian_scripts(debian_dir): - os.makedirs(debian_dir, exist_ok=True) - postinst = """#!/bin/bash -set -e -echo "/usr/local/lib" > /etc/ld.so.conf.d/amd-vrt.conf -ldconfig - -if [ -d "/usr/src/pcie-hotplug-drv" ]; then - echo "Building PCIe hotplug driver..." - cd /usr/src/pcie-hotplug-drv - make clean || true - make || true - make install || true - - echo "Configuring pcie_hotplug module to load at boot..." - echo "pcie_hotplug" > /etc/modules-load.d/amd-vrt.conf - - echo "Creating VRT device permission rules..." - cat > /etc/udev/rules.d/99-amd-vrt-permissions.rules << 'EOF' -KERNEL=="pcie_hotplug", MODE="0666", GROUP="users" -KERNEL=="pcie_hotplug*", MODE="0666", GROUP="users" -EOF - udevadm control --reload-rules - - cat > /usr/local/bin/vrt-setup-devices.sh << 'EOF' -#!/bin/bash -if ! lsmod | grep -q "pcie_hotplug"; then - modprobe pcie_hotplug || true - sleep 1 -fi -for dev in /dev/pcie_hotplug*; do - if [ -e "$dev" ]; then - chmod 666 "$dev" || true - chown root:users "$dev" || true - fi -done -EOF - chmod +x /usr/local/bin/vrt-setup-devices.sh - - cat > /etc/systemd/system/vrt-devices.service << 'EOF' -[Unit] -Description=VRT Device Permissions -After=systemd-udev-settle.service -After=systemd-modules-load.service - -[Service] -Type=oneshot -ExecStart=/usr/local/bin/vrt-setup-devices.sh -RemainAfterExit=yes - -[Install] -WantedBy=multi-user.target -EOF - systemctl daemon-reload - systemctl enable vrt-devices.service || true - - if lsmod | grep -q "pcie_hotplug"; then - rmmod pcie_hotplug || true - fi - modprobe pcie_hotplug || true - udevadm trigger || true - sleep 1 - /usr/local/bin/vrt-setup-devices.sh || true -fi -exit 0 -""" - prerm = """#!/bin/bash -set -e -if lsmod | grep -q "pcie_hotplug"; then - rmmod pcie_hotplug || true -fi -exit 0 -""" - postrm = """#!/bin/bash -set -e -rm -f /etc/modules-load.d/amd-vrt.conf || true -if [ -f "/etc/udev/rules.d/99-amd-vrt-permissions.rules" ]; then - rm -f /etc/udev/rules.d/99-amd-vrt-permissions.rules - udevadm control --reload-rules || true -fi -if [ -f "/etc/systemd/system/vrt-devices.service" ]; then - systemctl disable vrt-devices.service || true - systemctl stop vrt-devices.service || true - rm -f /etc/systemd/system/vrt-devices.service - systemctl daemon-reload || true -fi -rm -f /usr/local/bin/vrt-setup-devices.sh || true -if [ -f "/etc/ld.so.conf.d/amd-vrt.conf" ]; then - rm -f /etc/ld.so.conf.d/amd-vrt.conf - ldconfig -fi -exit 0 -""" - with open(os.path.join(debian_dir, "postinst"), "w") as f: f.write(postinst) - with open(os.path.join(debian_dir, "prerm"), "w") as f: f.write(prerm) - with open(os.path.join(debian_dir, "postrm"), "w") as f: f.write(postrm) - os.chmod(os.path.join(debian_dir, "postinst"), 0o755) - os.chmod(os.path.join(debian_dir, "prerm"), 0o755) - os.chmod(os.path.join(debian_dir, "postrm"), 0o755) - -def build_deb(stage_dir, version, repo_root): - timestamp = datetime.now().strftime("%Y-%m-%d-%H-%M-%S") - deb_root = stage_dir # stage already mirrors FS - debian_dir = os.path.join(deb_root, "DEBIAN") - os.makedirs(debian_dir, exist_ok=True) - - control = f"""Package: {PACKAGE_NAME} -Version: {version} -Architecture: {DEB_ARCH} -Maintainer: {MAINTAINER} -Depends: {DEB_DEPENDS} -Section: utils -Priority: optional -Homepage: https://www.amd.com/ -Description: {DESCRIPTION} - This package includes: - * VRT API - Runtime API for AMD V80 acceleration - * SMI CLI - System Management Interface command-line utility - * PCIe hotplug driver - Driver for PCIe hotplug functionality -""" - with open(os.path.join(debian_dir, "control"), "w") as f: - f.write(control) - - write_debian_scripts(debian_dir) - - out_dir = os.path.join(repo_root, "deploy", "output") - os.makedirs(out_dir, exist_ok=True) - deb_name = f"{PACKAGE_NAME}_{version}_{timestamp}_{DEB_ARCH}.deb" - deb_path = os.path.join(out_dir, deb_name) - - run_command(f"dpkg-deb --build --root-owner-group {deb_root} {deb_path}") - print(f"DEB created: {deb_path}") - return deb_path - -# ----------------------- RPM PACKAGING ----------------------- - -def rpm_topdirs(base_out): - top = os.path.join(base_out, "rpmbuild") - dirs = { - "TOP": top, - "BUILD": os.path.join(top, "BUILD"), - "RPMS": os.path.join(top, "RPMS"), - "SOURCES": os.path.join(top, "SOURCES"), - "SPECS": os.path.join(top, "SPECS"), - "SRPMS": os.path.join(top, "SRPMS"), - } - for d in dirs.values(): - os.makedirs(d, exist_ok=True) - return dirs - -def make_rpm_spec(spec_path, version, release, stage_dir): - """ - Create a SPEC that copies pre-built files from stage_dir into %{buildroot}. - Scriptlets mirror the Debian postinst/prerm/postrm. - """ - summary = DESCRIPTION - license_str = "MIT" - url = "https://www.amd.com/" - requires = "\n".join([f"Requires: {r}" for r in RPM_REQUIRES]) - - # Scriptlets (no shebangs) - post = r''' -echo "/usr/local/lib" > /etc/ld.so.conf.d/amd-vrt.conf -/sbin/ldconfig - -if [ -d "/usr/src/pcie-hotplug-drv" ]; then - echo "Building PCIe hotplug driver..." - cd /usr/src/pcie-hotplug-drv - make clean || true - make || true - make install || true - - echo "pcie_hotplug" > /etc/modules-load.d/amd-vrt.conf - - cat > /etc/udev/rules.d/99-amd-vrt-permissions.rules << 'EOF' -KERNEL=="pcie_hotplug", MODE="0666", GROUP="users" -KERNEL=="pcie_hotplug*", MODE="0666", GROUP="users" -EOF - /usr/bin/udevadm control --reload-rules || true - - cat > /usr/local/bin/vrt-setup-devices.sh << 'EOF' -#!/bin/bash -if ! /usr/sbin/lsmod | /usr/bin/grep -q "pcie_hotplug"; then - /usr/sbin/modprobe pcie_hotplug || true - /usr/bin/sleep 1 -fi -for dev in /dev/pcie_hotplug*; do - if [ -e "$dev" ]; then - /usr/bin/chmod 666 "$dev" || true - /usr/bin/chown root:users "$dev" || true - fi -done -EOF - /usr/bin/chmod +x /usr/local/bin/vrt-setup-devices.sh - - cat > /etc/systemd/system/vrt-devices.service << 'EOF' -[Unit] -Description=VRT Device Permissions -After=systemd-udev-settle.service -After=systemd-modules-load.service - -[Service] -Type=oneshot -ExecStart=/usr/local/bin/vrt-setup-devices.sh -RemainAfterExit=yes - -[Install] -WantedBy=multi-user.target -EOF - /usr/bin/systemctl daemon-reload || true - /usr/bin/systemctl enable vrt-devices.service || true - - if /usr/sbin/lsmod | /usr/bin/grep -q "pcie_hotplug"; then - /usr/sbin/rmmod pcie_hotplug || true - fi - /usr/sbin/modprobe pcie_hotplug || true - /usr/bin/udevadm trigger || true - /usr/bin/sleep 1 - /usr/local/bin/vrt-setup-devices.sh || true -fi -''' - - preun = r''' -if /usr/sbin/lsmod | /usr/bin/grep -q "pcie_hotplug"; then - /usr/sbin/rmmod pcie_hotplug || true -fi -''' - - postun = r''' -/usr/bin/rm -f /etc/modules-load.d/amd-vrt.conf || true -if [ -f "/etc/udev/rules.d/99-amd-vrt-permissions.rules" ]; then - /usr/bin/rm -f /etc/udev/rules.d/99-amd-vrt-permissions.rules - /usr/bin/udevadm control --reload-rules || true -fi -if [ -f "/etc/systemd/system/vrt-devices.service" ]; then - /usr/bin/systemctl disable vrt-devices.service || true - /usr/bin/systemctl stop vrt-devices.service || true - /usr/bin/rm -f /etc/systemd/system/vrt-devices.service - /usr/bin/systemctl daemon-reload || true -fi -/usr/bin/rm -f /usr/local/bin/vrt-setup-devices.sh || true -if [ -f "/etc/ld.so.conf.d/amd-vrt.conf" ]; then - /usr/bin/rm -f /etc/ld.so.conf.d/amd-vrt.conf - /sbin/ldconfig -fi -''' - - spec = f'''Name: {PACKAGE_NAME} -Version: {version} -Release: {release}%{{?dist}} -Summary: {summary} -License: {license_str} -URL: {url} -BuildArch: {RPM_ARCH} -{requires} - -%description -{summary} - -%prep -# Nothing to prep - -%build -# Nothing to build (prebuilt binaries) - -%install -rm -rf %{{buildroot}} -mkdir -p %{{buildroot}} -# Copy from staging dir into buildroot -cp -a "{stage_dir}/." %{{buildroot}}/ - -%post -{post} - -%preun -{preun} - -%postun -{postun} - -%files -%defattr(-,root,root,-) -/usr/local/bin/* -/usr/local/lib/* -/usr/local/vrt -/usr/src/pcie-hotplug-drv -/opt/amd/vrt - -%changelog -* {datetime.utcnow().strftime("%a %b %d %Y")} AMD - {version}-{release} -- Initial build -''' - with open(spec_path, "w") as f: - f.write(spec) - -def build_rpm(stage_dir, version, repo_root): - out_dir = os.path.join(repo_root, "deploy", "output") - os.makedirs(out_dir, exist_ok=True) - topdirs = rpm_topdirs(out_dir) - spec_path = os.path.join(topdirs["SPECS"], f"{PACKAGE_NAME}.spec") - release = "1" - - make_rpm_spec(spec_path, version, release, stage_dir) - # rpmbuild uses %_topdir to find BUILD, RPMS, etc. - cmd = f'rpmbuild -bb --define "_topdir {topdirs["TOP"]}" "{spec_path}"' - run_command(cmd) - - # Find the built RPM in RPMS// - rpm_arch = RPM_ARCH - arch_dir = os.path.join(topdirs["RPMS"], rpm_arch) - if not os.path.isdir(arch_dir): - # some dists put noarch if archless; but we have libs, so expect arch - arch_dir = os.path.join(topdirs["RPMS"], "noarch") - rpms = [os.path.join(arch_dir, f) for f in os.listdir(arch_dir) if f.endswith(".rpm")] - if not rpms: - print("Failed to find built RPM.") - sys.exit(1) - for p in rpms: - print(f"RPM created: {p}") - return rpms[0] - -# ----------------------- MAIN ----------------------- - -def main(): - parser = argparse.ArgumentParser(description="Build amd-vrt package as DEB or RPM") - parser.add_argument("--format", choices=["deb", "rpm", "auto"], default="auto", - help="Packaging format (default: auto)") - args = parser.parse_args() - - repo_root = os.path.abspath(os.getcwd()) - print(f"Repository root directory: {repo_root}") - - version = get_version_from_header(repo_root) - pkg_format = detect_packaging_format(None if args.format == "auto" else args.format) - - stage_dir = create_stage_tree(repo_root) - - # Build & stage files - build_and_copy_vrt(repo_root, stage_dir) - build_and_copy_smi(repo_root, stage_dir) - copy_pcie_driver(repo_root, stage_dir) - copy_design_pdi(repo_root, stage_dir) - - # Build packages - if pkg_format == "deb": - deb = build_deb(stage_dir, version, repo_root) - print(f"\nPackage successfully created: {deb}") - print(f"Install with: sudo apt install ./{os.path.basename(deb)}") - else: - rpm = build_rpm(stage_dir, version, repo_root) - print(f"\nPackage successfully created: {rpm}") - print(f"Install with: sudo dnf install {rpm} # or yum") - -if __name__ == "__main__": - main() diff --git a/docs/.gitignore b/docs/.gitignore new file mode 100644 index 00000000..1b3a6e86 --- /dev/null +++ b/docs/.gitignore @@ -0,0 +1 @@ +sphinx \ No newline at end of file diff --git a/docs/conf.py b/docs/conf.py index 8e10fabd..d45a910b 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -43,8 +43,12 @@ copyright = '2025 Advanced Micro Devices, Inc' author = 'Advanced Micro Devices Inc' -breathe_projects = {} -breathe_projects['VRT'] = '../vrt/doc/docs/xml' +breathe_projects = { + 'VRT': '../vrt/doc/docs/xml', + 'libslash': '../driver/libslash/doc/docs/xml', + 'libvrtd': '../vrt/vrtd/libvrtd/doc/docs/xml', + 'libvrtdpp': '../vrt/vrtd/libvrtdpp/doc/docs/xml', +} # Check if we're running on Read the Docs' servers read_the_docs_build = os.environ.get('READTHEDOCS', None) == 'True' @@ -56,7 +60,7 @@ # ones. #... -extensions = [ "breathe", 'sphinxcontrib.tikz'] +extensions = [ "breathe", 'sphinxcontrib.tikz', 'sphinx.ext.todo', 'sphinx_design'] #... @@ -83,8 +87,18 @@ # Breathe Configuration breathe_default_project = "SLASH" +breathe_domain_by_extension = {"h": "c"} + +# -- Doxygen builds (generate XML for Breathe) -------------------------------- subprocess.call('doxygen ./Doxyfile', shell=True, cwd='../vrt/doc') +subprocess.call('doxygen ./Doxyfile', shell=True, cwd='../driver/libslash/doc') +subprocess.call('doxygen ./Doxyfile', shell=True, cwd='../vrt/vrtd/libvrtd/doc') +subprocess.call('doxygen ./Doxyfile', shell=True, cwd='../vrt/vrtd/libvrtdpp/doc') -# Tikz configuration, as indicated in https://github.com/sphinx-contrib/tikz +# -- Tikz configuration ------------------------------------------------------- +# As indicated in https://github.com/sphinx-contrib/tikz tikz_proc_suite = 'GhostScript' + +# -- Todo extension ------------------------------------------------------------ +todo_include_todos = True diff --git a/docs/examples/index.rst b/docs/examples/index.rst new file mode 100644 index 00000000..a987dcde --- /dev/null +++ b/docs/examples/index.rst @@ -0,0 +1,39 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +########## +Examples +########## + +SLASH includes six example projects demonstrating different VRT features. + +.. list-table:: + :header-rows: 1 + :widths: 5 20 40 + + * - ID + - Name + - Feature + * - 00 + - axilite + - AXI-Lite control interfaces and kernel linking + * - 01 + - aximm + - AXI memory-mapped kernel interfaces + * - 02 + - chain + - Freerunning streaming kernel chains + * - 03 + - multiple_boards + - Multi-device control from a single application + * - 04 + - freq + - Custom clock frequency targeting + * - 05 + - perf + - HBM/DDR memory performance benchmarking + +Each example includes a ``CMakeLists.txt`` with targets for hardware (``hw``), emulation (``emu``), +and simulation (``sim``) flows. See ``examples/README.md`` in the repository for build +instructions. diff --git a/docs/explanation/architecture.rst b/docs/explanation/architecture.rst new file mode 100644 index 00000000..b60b56a1 --- /dev/null +++ b/docs/explanation/architecture.rst @@ -0,0 +1,143 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +Architecture +############## + +SLASH is organised as a layered stack. Each layer has a single responsibility +and communicates with adjacent layers through well-defined interfaces. + +Stack Overview +============== + +.. code-block:: text + + ┌─────────────────────────────────────────────┐ + │ User Application │ C++17 + ├─────────────────────────────────────────────┤ + │ VRT (libvrt) │ C++17 ─ MIT + ├─────────────────────────────────────────────┤ + │ libvrtd++ (C++ RAII wrapper) │ C++20 ─ MIT + ├─────────────────────────────────────────────┤ + │ libvrtd (C wire-protocol) │ C11 ─ MIT + ├──────────────── AF_UNIX ────────────────────┤ + │ vrtd (daemon) │ C11 ─ MIT + ├─────────────────────────────────────────────┤ + │ libslash (driver wrapper) │ C ─ MIT + ├─────────────────────────────────────────────┤ + │ Linux kernel module (slash) │ C ─ GPLv2 + ├─────────────────────────────────────────────┤ + │ AMD Alveo V80 Hardware │ + └─────────────────────────────────────────────┘ + +Two additional components sit alongside the stack: + +- **v80-smi** — command-line system management interface for listing, programming, + resetting, and validating V80 boards. +- **slashkit** — Python-based toolchain that links HLS kernels into + *vrtbin* archives for deployment. + +Layer Descriptions +================== + +User Application +---------------- + +Your C++ program. It uses the VRT API to open a device, load a vrtbin, allocate +buffers, launch kernels, and read results. The same source code runs unchanged +on hardware, emulation, and simulation platforms (see :doc:`/explanation/platform-modes`). + +VRT (libvrt) +------------ + +The V80 RunTime library. VRT is the primary API surface: + +- ``vrt::Device`` — opens a board by BDF, loads a vrtbin, exposes kernels and + memory configuration. +- ``vrt::Kernel`` — represents a hardware kernel; supports argument setting, + start, wait, and register read/write. +- ``vrt::Buffer`` — typed device memory with host synchronisation + (``HOST_TO_DEVICE`` / ``DEVICE_TO_HOST``). +- ``vrt::StreamingBuffer`` — QDMA streaming I/O for kernel ports. +- ``vrt::Vrtbin`` — extracts and inspects vrtbin archives. + +VRT transparently selects the correct back-end (PCIe BAR, ZeroMQ, or Verilog +register map) based on the platform encoded in the vrtbin's ``system_map.xml``. + +libvrtd++ and libvrtd +--------------------- + +Client libraries for communicating with the vrtd daemon: + +- **libvrtd** (C) — wire-protocol client over ``AF_UNIX`` / + ``SOCK_SEQPACKET``. Exposes typed request/response helpers and fd passing + via ``SCM_RIGHTS``. +- **libvrtd++** (C++) — RAII/exception wrapper. ``vrtd::Session``, + ``vrtd::Device``, ``vrtd::Bar``, ``vrtd::BarFile`` manage connection + lifetime automatically. + +vrtd (daemon) +------------- + +The V80 Runtime Daemon multiplexes access to FPGA devices and enforces +permission rules for multi-tenancy. It listens on a Unix domain socket and +translates client requests into libslash calls. Configuration is through +``vrtd.conf`` (see :doc:`/reference/vrtd/configuration`). + +libslash +-------- + +A thin C wrapper around the Linux kernel driver's ioctl interface. It exposes +three modules: + +- **Control** (``slash/ctldev.h``) — BAR MMIO access via PF2. +- **QDMA** (``slash/qdma.h``) — queue-based DMA via PF1. +- **Hotplug** (``slash/hotplug.h``) — PCIe secondary bus reset and rescan. + +Linux Kernel Module +------------------- + +The ``slash`` kernel module manages two PCI functions on each V80 board: + +- **PF1** (``slash_qdma``) — queue-based DMA subsystem. +- **PF2** (``slash_ctl``) — BAR MMIO access for register reads and writes. + +PF0 (``ami``) is the AVED management interface, managed by a separate driver. + +Initialisation order: QDMA → Hotplug → PCIe. Teardown is reversed. + +Typical Execution Flow +====================== + +The following sequence shows a minimal hardware run using VRT: + +.. code-block:: text + + 1. vrt::Device device(bdf, vrtbinFile); + │ + ├─ Extract vrtbin archive (gzipped tar) + ├─ Parse system_map.xml → determine platform + ├─ Connect to vrtd → open device → program FPGA + └─ Discover kernels and memory configuration + + 2. vrt::Kernel kernel(device, "kernel_name"); + └─ Look up kernel in the loaded design + + 3. vrt::Buffer buf(device, size, kernel.argMemoryConfig("in")); + └─ Allocate device memory (DDR or HBM) via QDMA + + 4. buf.sync(vrt::SyncType::HOST_TO_DEVICE); + └─ DMA transfer: host → device + + 5. kernel.setArg(0, size); + kernel.setArg(1, buf); + kernel.start(); + └─ Write arguments to AXI-Lite registers, then set AP_START + + 6. kernel.wait(); + └─ Poll AP_DONE / AP_IDLE + + 7. uint32_t result = kernel.read(0x18); + └─ Read result register via BAR MMIO diff --git a/docs/explanation/memory-model.rst b/docs/explanation/memory-model.rst new file mode 100644 index 00000000..d6d6b836 --- /dev/null +++ b/docs/explanation/memory-model.rst @@ -0,0 +1,175 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +Memory Model +############## + +The AMD Alveo V80 board has two distinct memory subsystems — DDR and HBM — +each with different capacity, bandwidth, and access characteristics. This +document explains how SLASH models these subsystems and how the runtime +allocator manages device memory. + +DDR Memory +========== + +The V80 has a single DDR address space, accessed through the QDMA subsystem +(PCIe Physical Function 1). DDR offers large capacity and is suitable for bulk +data storage where bandwidth is not the primary concern. + +In VRT, DDR memory is selected with ``MemoryRangeType::DDR``: + +.. code-block:: cpp + + vrt::Buffer buffer(device, size, vrt::MemoryRangeType::DDR); + +In the linker configuration, DDR is referenced as ``DDR0``: + +.. code-block:: ini + + sp=offset_0.m_axi_gmem0:DDR0 + +HBM (High Bandwidth Memory) +============================ + +The V80 includes HBM organized as 64 pseudo-channels (HBM0–HBM63). Each +channel provides independent bandwidth, and the aggregate bandwidth across all +channels is substantially higher than DDR. + +There are two access modes: + +Port-Based Access +----------------- + +``MemoryRangeType::HBM`` with an explicit port number allocates on a specific +HBM channel. The kernel port must be mapped to the same channel via the +``sp=`` directive in the linker configuration. + +.. code-block:: cpp + + // Allocate on HBM channel 1 + vrt::Buffer buffer(device, size, vrt::MemoryRangeType::HBM, 1); + +.. code-block:: ini + + # Linker config must match + sp=increment_0.m_axi_gmem0:HBM1 + +Internally, the port number maps to an ``HBMRegion`` enum value (``HBM0`` +through ``HBM63``) and the allocation type is set to ``BufferAllocType::Hbm``. + +.. note:: + + Constructing a buffer with ``MemoryRangeType::HBM`` but *without* a port + throws ``std::invalid_argument``. HBM always requires an explicit channel + unless you use VNOC. + +VNOC (Virtual NoC) Access +-------------------------- + +``MemoryRangeType::HBM_VNOC`` allocates across multiple HBM channels using the +on-chip Virtual Network-on-Chip, aggregating bandwidth without requiring the +application to manage individual channels. + +.. code-block:: cpp + + vrt::Buffer buffer(device, size, vrt::MemoryRangeType::HBM_VNOC); + +The allocation type is set to ``BufferAllocType::HbmVnoc`` and no specific +``HBMRegion`` is selected. + +MemoryConfig and Port Mapping +============================== + +Rather than specifying memory types and ports manually, the recommended +approach is to use ``MemoryConfig`` — a struct that carries both the +``MemoryRangeType`` and an optional HBM port number: + +.. code-block:: cpp + + struct MemoryConfig { + MemoryRangeType type; + std::optional hbmPort; + }; + +Obtain a ``MemoryConfig`` from the kernel: + +.. code-block:: cpp + + // By port name + vrt::MemoryConfig config = kernel.portMemoryConfig("m_axi_gmem0"); + + // By argument name + vrt::MemoryConfig config = kernel.argMemoryConfig("in"); + +These methods parse the ``system_map.xml`` inside the vrtbin to determine +which memory type and channel the kernel port is connected to. The returned +config can be passed directly to the ``Buffer`` constructor: + +.. code-block:: cpp + + vrt::Buffer buffer(device, size, kernel.argMemoryConfig("in")); + +This ensures the buffer allocation always matches the linker configuration. + +Buddy Allocator +=============== + +On hardware, VRT uses a three-tier buddy-system allocator to manage device +memory efficiently. Each tier handles a different size range: + +**SmallBlock** (4 KB – 2 MB) + Managed by ``BuddySuperblockBase<12, 21>``. Allocations are carved from a + 2 MB superblock using power-of-two splitting. + +**MediumBlock** (2 MB – 64 MB) + Managed by ``BuddySuperblockBase<21, 26>``. Allocations are carved from a + 64 MB superblock. + +**LargeBlock** (> 64 MB) + Allocated directly from vrtd as a standalone DMA buffer, bypassing the + buddy system. + +When a buffer is allocated: + +1. The size is rounded up to the nearest power of two. +2. The allocator searches for the smallest available block that fits. +3. If the available block is larger than needed, it is split in half + repeatedly until the target size is reached. The unused halves are returned + to the free list. + +When a buffer is freed: + +1. The allocator checks if the freed block's *buddy* (the other half from the + original split) is also free. +2. If so, the two halves are coalesced back into a single larger block. +3. This continues up the hierarchy until no more buddies can be merged. + +This approach minimises fragmentation while keeping allocation and deallocation +fast. + +Platform Differences +==================== + +The memory model is designed to be transparent across all three SLASH +platforms, but the underlying mechanisms differ: + +**Hardware** + Real DMA allocations through the vrtd daemon, libslash, and the kernel + driver. ``sync()`` triggers QDMA transfers between host and device memory. + The buddy allocator manages physical address space. + +**Emulation** + Fake physical addresses are assigned starting at ``0x4000000000`` (HBM) and + ``0x60000000000`` (DDR). Buffer data is exchanged with the C-model via + ZeroMQ IPC. No real DMA occurs. + +**Simulation** + Same fake address scheme as emulation. Buffer data is exchanged with the + Verilog simulation via ZeroMQ. The address windows match the simulation + memory map configured in the linker's ``run_pre.tcl``. + +In all cases, the ``Buffer`` API (construction, ``sync()``, ``operator[]``) +is identical. Application code does not need to change when switching +platforms. diff --git a/docs/explanation/pcie-topology.rst b/docs/explanation/pcie-topology.rst new file mode 100644 index 00000000..cabfd6c4 --- /dev/null +++ b/docs/explanation/pcie-topology.rst @@ -0,0 +1,177 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################# +PCIe Topology +################# + +Each AMD Alveo V80 board exposes three PCIe Physical Functions (PFs). The +SLASH stack assigns each function a dedicated role, driver, and character +device so that management, DMA, and register access can operate independently. + +Physical Functions +================== + +.. code-block:: text + + ┌─────────────── V80 Board ───────────────┐ + │ │ + │ PF0 (.0) PF1 (.1) PF2 (.2) │ + │ ami slash_qdma slash_ctl │ + │ 0x50B4 0x50B5 0x50B6 │ + │ Management DMA BAR MMIO │ + └──────────────────────────────────────────┘ + +.. list-table:: + :header-rows: 1 + :widths: 10 15 15 20 40 + + * - PF + - Device ID + - Driver + - Device path + - Role + * - PF0 + - ``0x50B4`` + - ``ami`` + - (managed by AMI subsystem) + - AVED management interface — sensor readings, board identity, firmware + version. + * - PF1 + - ``0x50B5`` + - ``slash_qdma`` + - ``/dev/slash_qdma_ctl`` + - Queue-based DMA subsystem — H2C and C2H data transfers for buffers and + streaming. + * - PF2 + - ``0x50B6`` + - ``slash_ctl`` + - ``/dev/slash_ctl`` + - BAR MMIO access — kernel register reads and writes via memory-mapped + I/O. + +All three PFs share vendor ID ``0x10EE`` (AMD/Xilinx). + +BDF Addressing +============== + +PCI devices are identified by a **BDF** (Bus:Device.Function) address in the +format ``DDDD:BB:DD.F`` — domain, bus, device, function. The three V80 +functions share the same domain, bus, and device number and differ only in +the function digit: + +.. code-block:: text + + 0000:03:00.0 ← PF0 (ami) + 0000:03:00.1 ← PF1 (slash_qdma) + 0000:03:00.2 ← PF2 (slash_ctl) + +Throughout the SLASH stack, a **board BDF** refers to the common prefix +without the function digit (e.g. ``0000:03:00``). Given a board BDF, each +component derives the full address by appending ``.0``, ``.1``, or ``.2``. + +Device Discovery +================ + +``v80-smi list`` discovers V80 boards by scanning the sysfs PCI bus: + +1. Enumerate ``/sys/bus/pci/devices/`` for entries with vendor ``0x10EE`` and + device ``0x50B4`` (PF0). +2. Extract the board BDF from the matching entry. +3. Verify that companion functions PF1 (``0x50B5``) and PF2 (``0x50B6``) + exist at the same bus and device. +4. Check that the correct kernel driver is bound to each function by + inspecting the ``driver`` symlink in sysfs. +5. Query the ``vrtd`` daemon for device registration via + ``vrtd::Session::getDeviceByBdf()``. + +Readiness Checks +================ + +``v80-smi list`` reports four readiness indicators per board: + +.. list-table:: + :header-rows: 1 + :widths: 20 40 40 + + * - Check + - Validates + - Failure meaning + * - **PF0** + - ``ami`` driver bound to ``0x50B4`` + - AMI management driver not loaded + * - **PF1** + - ``slash_qdma`` driver bound to ``0x50B5`` + - QDMA driver not loaded + * - **PF2** + - ``slash_ctl`` driver bound to ``0x50B6`` + - Control driver not loaded + * - **VRTD** + - Daemon has registered the board + - ``vrtd`` not running or device not configured + +All four must pass before the board can be used by VRT. + +Hotplug Lifecycle +================= + +FPGA reconfiguration requires removing the device from the PCI bus, +performing a Secondary Bus Reset (SBR), and re-enumerating. The ``slash`` +kernel module exposes a hotplug character device at ``/dev/slash_hotplug`` +with four ioctl operations: + +.. list-table:: + :header-rows: 1 + :widths: 25 75 + + * - Operation + - Description + * - ``REMOVE`` + - Remove a device by BDF from the PCI bus. + * - ``TOGGLE_SBR`` + - Assert the Secondary Bus Reset on the root port (2 ms hold), deassert, + then wait 5 s for the link to retrain. + * - ``RESCAN`` + - Rescan the entire PCI bus to re-enumerate devices. + * - ``HOTPLUG`` + - Atomic REMOVE + RESCAN for a single device. + +A typical FPGA programming sequence follows this order: + +.. code-block:: text + + 1. REMOVE PF0, PF1, PF2 ← tear down all three functions + 2. TOGGLE_SBR on root port ← reset the FPGA, reload bitstream + 3. RESCAN ← re-enumerate the bus + 4. HOTPLUG each function ← bind drivers to the new device + +The ``vrtd`` daemon orchestrates this sequence through its +``ResetSequence`` hotplug operation, which is triggered by +``v80-smi reset`` or programmatically via ``vrtd::Device::hotplugOp()``. + +Segmented Configuration +======================= + +Each physical function operates through its own independent character device. +This separation means that the SLASH stack layers interact with different +functions for different purposes: + +- **VRT** uses PF2 (``slash_ctl``) for kernel register access via BAR MMIO, + and PF1 (``slash_qdma``) for buffer DMA transfers. +- **vrtd** uses libslash to manage all three functions and orchestrate device + lifecycle events like hotplug and reset. +- **v80-smi** reads PF0 (``ami``) for sensor data and board identity, and + uses PF1/PF2 for validation and programming. + +There are no cross-function dependencies in userspace — each character device +can be opened, used, and closed independently. + +See Also +======== + +- :doc:`architecture` — full SLASH stack overview. +- :doc:`/tutorials/admin/device-management` — managing V80 boards in + practice. +- :doc:`/reference/vrtd/client-flow` — how VRT connects to ``vrtd`` for + device access. diff --git a/docs/explanation/platform-modes.rst b/docs/explanation/platform-modes.rst new file mode 100644 index 00000000..afb88dc3 --- /dev/null +++ b/docs/explanation/platform-modes.rst @@ -0,0 +1,117 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################# +Platform Modes +################# + +VRT supports three execution platforms. The same application source code runs +on all three — the platform is determined by the vrtbin file, not by the +application. + +.. list-table:: + :header-rows: 1 + :widths: 15 30 25 30 + + * - Platform + - Transport + - Build target + - Use case + * - **Hardware** + - PCIe BAR + QDMA + - ``hw`` + - Production runs on a physical V80 board + * - **Emulation** + - ZeroMQ IPC to C-model + - ``emu`` + - Functional verification without FPGA hardware + * - **Simulation** + - Verilog register map + - ``sim`` + - Cycle-accurate RTL simulation + +Platform Selection +================== + +The platform is encoded inside the vrtbin archive. When VRT extracts the +archive, it reads the ```` element from ``system_map.xml``: + +- ``"Hardware"`` → ``vrt::Platform::HARDWARE`` +- ``"Emulation"`` → ``vrt::Platform::EMULATION`` +- ``"Simulation"`` → ``vrt::Platform::SIMULATION`` + +Your application can query the active platform at runtime: + +.. code-block:: cpp + + if (device.getPlatform() == vrt::Platform::EMULATION) { + // emulation-specific logic + } + +Building for Each Platform +========================== + +Each example provides three vrtbin targets via CMake: + +.. code-block:: cmake + + add_vbin(TARGET "axilite_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "axilite_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "axilite_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +The application executable is the same regardless of platform — only the vrtbin +file passed at runtime differs. + +Hardware +======== + +On hardware, VRT communicates with the V80 board through the full SLASH stack: + +- **Register access** — BAR MMIO via PF2 (kernel arguments, control, status). +- **Data transfer** — QDMA via PF1 (buffer sync between host and device memory). +- **Device management** — vrtd daemon (programming, reset, multi-tenancy). + +This is the only platform that exercises the physical FPGA. It requires: + +- A V80 board installed in the host. +- The ``slash`` kernel module loaded. +- The ``vrtd`` daemon running. + +Emulation +========= + +Emulation replaces the FPGA with a software C-model of the HLS kernels. VRT +communicates with the emulated kernels over ZeroMQ IPC sockets. + +Advantages: + +- No FPGA hardware required. +- Fast iteration — recompile the C-model instead of running synthesis. +- Full functional verification of kernel logic. + +Limitations: + +- Timing is not modelled — performance measurements are not meaningful. +- HLS kernels must include at least one AXI4-Lite interface. +- Freerunning streaming kernel chains (e.g. example ``02_chain``) are not + supported in emulation. + +Simulation +========== + +Simulation runs the kernel RTL in a Verilog simulator. VRT accesses the +simulated design through a register-map interface. + +Advantages: + +- Cycle-accurate behaviour. +- Can catch timing and protocol issues that emulation misses. + +Limitations: + +- Significantly slower than emulation. +- Requires AMD Vivado and a simulator licence. +- Memory roundtrip fidelity may differ from hardware (floating-point + representation in the simulator can introduce NaN artefacts that the + application must handle). diff --git a/docs/explanation/vrtbin-format.rst b/docs/explanation/vrtbin-format.rst new file mode 100644 index 00000000..c1b55830 --- /dev/null +++ b/docs/explanation/vrtbin-format.rst @@ -0,0 +1,196 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +vrtbin Format +################ + +A vrtbin (``.vbin``) file is the deployment artefact in SLASH. It packages +everything needed to program and interact with a V80 design into a single +archive. + +Overview +======== + +A vrtbin is a **gzip-compressed tar archive** produced by the SLASH linker +(``slashkit``) via the ``add_vbin()`` CMake function. VRT extracts the archive +at runtime when you construct a ``vrt::Device``. + +.. code-block:: text + + ┌───────────────────────────────┐ + │ .vbin file │ gzip-compressed tar + ├───────────────────────────────┤ + │ system_map.xml │ always present — design metadata + │ *.pdi │ hardware only — FPGA bitstream(s) + │ vpp_emu │ emulation only — C-model executable + │ emu_manifest.json │ emulation only — argument routing + │ vpp_sim │ simulation only — simulator launcher + │ report_utilization.xml │ optional — FPGA resource usage + └───────────────────────────────┘ + +Archive Contents +================ + +.. list-table:: + :header-rows: 1 + :widths: 25 15 60 + + * - File + - Present + - Purpose + * - ``system_map.xml`` + - Always + - Design metadata: platform, clock frequency, kernel descriptions, + register maps, memory connections, and streaming connections. + * - ``*.pdi`` + - Hardware + - FPGA bitstream file(s). If multiple PDI files exist, VRT prefers + ``design.pdi``. + * - ``vpp_emu`` + - Emulation + - Compiled C-model executable of the HLS kernels. + * - ``emu_manifest.json`` + - Emulation + - Maps kernel arguments to emulation call types (scalar, buffer) and + routing for register read-back. + * - ``vpp_sim`` + - Simulation + - Verilog simulator wrapper executable. + * - ``report_utilization.xml`` + - Optional + - FPGA resource utilisation report (LUTs, FFs, BRAMs, URAMs, DSPs). + +system_map.xml +============== + +The ``system_map.xml`` file is the most important entry in the archive. It +drives VRT's runtime behaviour — kernel discovery, argument routing, memory +port mapping, and platform detection all come from this file. + +Schema +------ + +.. code-block:: xml + + + Hardware + 250000000 + + + + + + + + + + + + increment_0 + 0x20100000000 + 0x1000 + + + + + + + + + + + + + +Key elements: + +```` + One of ``Hardware``, ``Emulation``, or ``Simulation``. VRT maps this to + the ``vrt::Platform`` enum and selects the appropriate back-end. + +```` + Kernel clock frequency in Hz (e.g. ``250000000`` for 250 MHz). + +```` + One block per kernel instance. Contains the instance name, base address, + register definitions, functional argument metadata, and memory port + connections. + +```` + Each ```` describes a kernel argument: index, name, type + (``scalar`` or ``buffer``), register offset, range in bits, read/write + flags, and the associated AXI port name (for buffer arguments). + +```` + Maps an AXI memory-mapped port to a physical memory target (e.g. + ``HBM1``, ``DDR0``). VRT uses this to determine the correct + ``MemoryConfig`` for buffer allocation. + +How VRT Uses the Vrtbin +======================= + +When you construct ``vrt::Device(bdf, vrtbinPath)``: + +1. **Extract** — ``Vrtbin::extract()`` decompresses the gzip archive into a + temporary cache directory. + +2. **Discover** — VRT locates ``system_map.xml``, PDI files, and + emulation/simulation executables within the extracted tree. + +3. **Parse** — the XML parser reads ``system_map.xml`` to build kernel + objects with register maps, argument metadata, and memory configurations. + +4. **Select platform** — the ```` value determines whether VRT + uses PCIe BAR access (hardware), ZeroMQ to ``vpp_emu`` (emulation), or + ZeroMQ to ``vpp_sim`` (simulation). + +5. **Program** — on hardware, VRT programs the FPGA with the PDI + bitstream(s) via the vrtd daemon. On emulation/simulation, it launches + the model executable in a background thread. + +Inspecting a Vrtbin +=================== + +Use ``v80-smi inspect`` to display a vrtbin's metadata without programming +a device: + +.. code-block:: bash + + v80-smi inspect my_design.vbin + +This prints the platform, clock frequency, kernel names, argument lists, +and memory connections parsed from ``system_map.xml``. + +You can also examine the raw archive contents: + +.. code-block:: bash + + tar tzf my_design.vbin + +See :doc:`/reference/smi/commands` for the full ``inspect`` command +reference. + +Creating a Vrtbin +================= + +Vrtbin archives are produced by the SLASH linker (``slashkit``) through the +CMake ``add_vbin()`` function: + +.. code-block:: cmake + + add_vbin(TARGET "my_design_hw" PLATFORM "hw" CFG "config.cfg" KERNELS ${_KERNELS}) + +The linker reads compiled HLS kernel IP (``component.xml`` files) and a +connectivity configuration (``config.cfg``) to produce the archive. One +target is created per platform (``hw``, ``emu``, ``sim``). + +See :doc:`/reference/cmake/slashtools` for the full ``add_vbin()`` +reference and :doc:`/tutorials/user/your-first-kernel` for a worked +example. diff --git a/docs/howto/benchmark-memory.rst b/docs/howto/benchmark-memory.rst new file mode 100644 index 00000000..98aea8ce --- /dev/null +++ b/docs/howto/benchmark-memory.rst @@ -0,0 +1,134 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################## +Benchmark Memory +################## + +This guide shows how to measure HBM and DDR memory bandwidth on a V80 board +using ``v80-smi validate`` and the performance example. + +Prerequisites +============= + +- The SLASH stack is installed, ``vrtd`` is running, and a V80 board is + visible in ``v80-smi list``. +- Root or sufficient permissions for device reset (``v80-smi validate`` + performs a full reset before testing). + +Quick Start — v80-smi validate +================================ + +The fastest way to benchmark memory is with the built-in validate command: + +.. code-block:: bash + + v80-smi validate -d [-j ] + +- ```` — board address from ``v80-smi list`` (e.g. ``0000:03:00``). +- ``[threads]`` — number of parallel buffers (default: 8). Each buffer is + 64 MB (one allocator sub-region). + +Example: + +.. code-block:: bash + + v80-smi validate -d 0000:03:00 + v80-smi validate -d 0000:03:00 -j 4 # 4 parallel buffers + +What validate Measures +======================== + +The command runs three phases: + +1. **Device reset** — performs a full hotplug reset sequence via ``vrtd`` to + bring the board to a clean state. + +2. **HBM test** — allocates *N* buffers in HBM, then: + + - **Integrity check**: fills each buffer with an XOR pattern + (``data[i] = i ^ seed``), syncs host-to-device, clears the host copy, + syncs device-to-host, and verifies every word matches. + - **Bandwidth measurement**: launches *N* threads in parallel. Each thread + performs a full-buffer host-to-device (H2C) transfer, then a + device-to-host (C2H) transfer. Wall-clock time is recorded for each + direction. + +3. **DDR test** — repeats the same integrity and bandwidth measurements using + DDR memory. + +Output includes per-direction bandwidth in MB/s and a pass/fail verdict for +data integrity. + +Using Example 05 (perf) +========================= + +The ``05_perf`` example provides a more configurable benchmark that runs +inside your own application. Build it against the repository: + +.. code-block:: bash + + cd examples/05_perf + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + cmake --build build + cmake --build build --target hls + cmake --build build --target perf_hw # or perf_emu / perf_sim + +Run: + +.. code-block:: bash + + ./05_perf perf_hw.vbin + +This example allocates buffers across HBM and DDR banks and measures +round-trip throughput, giving you a baseline for your own kernel designs. + +Interpreting Results +==================== + +.. list-table:: + :header-rows: 1 + :widths: 25 35 40 + + * - Metric + - Direction + - Description + * - Write bandwidth + - H2C (host-to-device) + - Rate at which data is DMA'd from host memory to the device. + * - Read bandwidth + - C2H (device-to-host) + - Rate at which data is DMA'd from the device back to host memory. + * - Data integrity + - Both + - PASS if every word survives the round-trip; FAIL indicates a + transfer or memory error. + +HBM typically delivers significantly higher aggregate bandwidth than DDR due +to its 32 independent channels. Increasing the thread count can improve +utilisation of these parallel channels. + +.. note:: + + Bandwidth numbers depend on PCIe link width and generation, BIOS + settings, IOMMU configuration, and host CPU/memory speed. Results are + most useful for relative comparisons (e.g. before/after a configuration + change) rather than absolute guarantees. + +Tuning Parameters +================= + +- **Thread count** — more parallel buffers can saturate more HBM channels, + but returns diminish once the PCIe link is the bottleneck. +- **Buffer size** — each buffer is 64 MB by default (one allocator + sub-region). The validate command does not expose a size parameter; use + the VRT API directly if you need different sizes. + +See Also +======== + +- :doc:`/explanation/memory-model` — how HBM and DDR banks are organised. +- :doc:`/tutorials/user/buffers-and-memory` — buffer allocation and + synchronisation in application code. +- :doc:`/reference/smi/commands` — full ``v80-smi`` command reference. diff --git a/docs/howto/build-from-source.rst b/docs/howto/build-from-source.rst new file mode 100644 index 00000000..a9697fae --- /dev/null +++ b/docs/howto/build-from-source.rst @@ -0,0 +1,215 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +#################### +Build from Source +#################### + +This guide covers building all SLASH components from the repository. + +Prerequisites +============= + +- **CMake** 3.20 or later +- **C++ compiler** with C++17 support (GCC 9+, Clang 10+) — v80-smi requires + C++20 +- **C compiler** with C11 support +- **Linux kernel headers** (for the kernel module) +- **pkg-config** + +Library dependencies: + +- **libxml2** — XML parsing (vrtbin ``system_map.xml``) +- **ZeroMQ** (libzmq) — emulation/simulation IPC +- **JsonCpp** — JSON manifest and command handling +- **zlib** — vrtbin archive decompression +- **libsystemd** — vrtd daemon integration +- **inih** — INI configuration parsing (vrtd) + +On Debian/Ubuntu: + +.. code-block:: bash + + sudo apt install cmake pkg-config ninja-build \ + libxml2-dev libzmq3-dev libjsoncpp-dev zlib1g-dev \ + libsystemd-dev libinih-dev libcli11-dev \ + linux-headers-$(uname -r) \ + python3 + +Build Order +=========== + +Components must be built in dependency order: + +.. code-block:: text + + 1. Linux kernel module (slash) + 2. libslash + 3. vrtd (depends on libslash) + 4. VRT (depends on vrtd) + 5. v80-smi (depends on VRT) + +Alternatively, VRT can build vrtd as a CMake subdirectory automatically. + +Linux Kernel Module +=================== + +.. code-block:: bash + + cd driver + make + sudo insmod slash.ko + +Optional module parameters: + +- ``qdma_num_threads=N`` — number of libqdma worker threads (default: 8). +- ``qdma_debugfs_path=/sys/kernel/debug`` — enable QDMA debugfs diagnostics. + +vrtd (Daemon) +============= + +.. code-block:: bash + + cd vrt/vrtd + cmake -B build -S . -G Ninja + cmake --build build + +This produces: + +- ``libvrtd`` — C wire-protocol client library. +- ``libvrtdpp`` — C++ RAII wrapper library. +- ``vrtd`` — the daemon executable. + +Install: + +.. code-block:: bash + + sudo cmake --install build + +VRT (Runtime Library) +===================== + +.. code-block:: bash + + cd vrt + cmake -B build -S . -G Ninja + cmake --build build + +If vrtd is not installed system-wide, VRT will build it as a subdirectory +automatically. To force this behaviour: + +.. code-block:: bash + + cmake -B build -S . -G Ninja -DFETCHCONTENT_FULLY_DISCONNECTED=OFF + +Install: + +.. code-block:: bash + + sudo cmake --install build + +v80-smi +======= + +Requires C++20 and a built VRT library. + +.. code-block:: bash + + cd smi + cmake -B build -S . -G Ninja + cmake --build build + +Install: + +.. code-block:: bash + + sudo cmake --install build + +slashkit — Static Shell +============================== + +After installing ``v80-smi``, the linker's static shell must be built +before hardware vrtbins can be linked. The static shell is the pre-built +FPGA platform base that every hardware vrtbin is linked against. It contains +platform IP — including the SMBus controller used for board management — +that requires a **Vivado Enterprise license** to build. + +Source Vivado **2025.1** and Vitis **2025.1** and ensure a Vivado Enterprise +license is configured for your site: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +For ``csh``/``tcsh`` users: + +.. code-block:: csh + + source /settings64.csh + source /settings64.csh + +.. note:: + + Vivado Enterprise license configuration is site-specific. Contact your + license administrator if you are unsure how licenses are served at your + site. + +The SMBus IP (``xilinx.com:ip:smbus:1.1``) used for board management is +**not included** in this repository and is not bundled with Vivado. It must +be downloaded separately from the AMD member portal and placed into the +local IP repository before building: + +1. Download the SMBus IP from https://www.xilinx.com/member/v80.html + (AMD account required). +2. Copy the downloaded IP directory into ``linker/slashkit/resources/base/iprepo/`` + so that Vivado can locate it during synthesis. + +See the `AVED rebuild guide `_ for +additional details. + +Then run the linker install script from the repository root: + +.. code-block:: bash + + bash scripts/root-design-build.sh + +**This step takes several hours** — it runs full Vivado synthesis and +implementation to produce the static shell artifacts. + +Examples +======== + +Each example is a standalone CMake project. To build against the local +repository tree (without installing SLASH first): + +.. code-block:: bash + + cd examples/00_axilite + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + cmake --build build + +To build against installed SLASH packages: + +.. code-block:: bash + + cmake -B build -S . -G Ninja + cmake --build build + +Building FPGA artefacts (HLS kernels and vrtbin files) requires AMD Vivado +**2025.1** and Vitis HLS **2025.1**. Source the environment before building: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. Using versions +other than 2025.1 may cause breakage. + +The CMake ``SlashTools`` module provides: + +- ``build_hls_dir()`` — compile HLS kernels from a directory. +- ``add_vbin()`` — link kernels into a vrtbin for a target platform + (``hw``, ``emu``, or ``sim``). diff --git a/docs/howto/chain-streaming-kernels.rst b/docs/howto/chain-streaming-kernels.rst new file mode 100644 index 00000000..0bc35ce6 --- /dev/null +++ b/docs/howto/chain-streaming-kernels.rst @@ -0,0 +1,222 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +########################### +Chain Streaming Kernels +########################### + +This guide shows how to connect multiple HLS kernels via AXI-Stream to form a +processing pipeline where data flows kernel-to-kernel without touching device +memory. + +Prerequisites +============= + +- The SLASH stack is installed, ``vrtd`` is running, and a V80 board is visible. +- Familiarity with HLS kernel basics. + See :doc:`/tutorials/user/your-first-kernel`. + +Streaming Pipeline Concept +=========================== + +In a streaming pipeline, kernels are wired together through on-chip AXI-Stream +channels. Data bypasses device memory entirely between stages: + +.. code-block:: text + + Host Memory ──► [dma_in] ──axis──► [passthrough] ──axis──► [dma_out] ──► Host Memory + +- **dma_in** — reads from device memory and writes to a stream. +- **passthrough** — a freerunning kernel that processes each element as it + arrives (in this example, a simple pass-through). +- **dma_out** — reads from a stream and writes to device memory. + +Writing Streaming HLS Kernels +============================== + +DMA-In Kernel (Stream Producer) +--------------------------------- + +The DMA-in kernel reads from a memory-mapped port and pushes each element onto +an AXI-Stream output: + +.. code-block:: cpp + + void dma_in(ap_uint<64>* in, hls::stream>& axis_out, ap_uint<32> size) { + #pragma hls interface mode=s_axilite port=size + #pragma hls interface mode=axis port=axis_out + #pragma hls interface m_axi bundle=gmem0 port=in max_widen_bitwidth=64 + #pragma hls interface mode=s_axilite port=return + + for (ap_uint<32> i = 0; i < size; i++) { + #pragma HLS PIPELINE II=1 + axis_out.write(in[i]); + } + } + +Key pragmas: + +- ``m_axi`` — memory-mapped master for the input buffer. +- ``axis`` — AXI-Stream output port. +- ``s_axilite port=return`` — allows the host to start and poll the kernel. + +Freerunning Kernel (Stream Processor) +--------------------------------------- + +A freerunning kernel has no host control interface. It runs continuously, +processing data whenever the input stream has elements: + +.. code-block:: cpp + + void passthrough(hls::stream>& axis_in, hls::stream>& axis_out) { + #pragma HLS INTERFACE axis port=axis_in + #pragma HLS INTERFACE axis port=axis_out + #pragma HLS INTERFACE ap_ctrl_none port=return + + ap_uint<64> data; + while (true) { + #pragma HLS PIPELINE II=1 + if (!axis_in.empty()) { + data = axis_in.read(); + axis_out.write(data); + } + } + } + +The ``ap_ctrl_none`` pragma is critical — it removes the start/done/idle +control registers, making the kernel autonomous. You do **not** call +``kernel.start()`` or ``kernel.wait()`` for freerunning kernels. + +DMA-Out Kernel (Stream Consumer) +---------------------------------- + +The DMA-out kernel reads from a stream and writes each element to device +memory: + +.. code-block:: cpp + + void dma_out(ap_uint<32> size, hls::stream>& axis_in, ap_uint<64>* out) { + #pragma hls interface mode=s_axilite port=size + #pragma hls interface mode=axis port=axis_in + #pragma hls interface m_axi bundle=gmem0 port=out max_widen_bitwidth=64 + #pragma hls interface mode=s_axilite port=return + + for (ap_uint<32> i = 0; i < size; i++) { + #pragma HLS PIPELINE II=1 + ap_uint<64> val; + axis_in.read(val); + out[i] = val; + } + } + +Linker Configuration +===================== + +Connect the kernels with ``stream_connect`` directives in ``config.cfg``: + +.. code-block:: ini + + [connectivity] + nk=dma_in:1:dma_in_0 + nk=passthrough:1:passthrough_0 + nk=dma_out:1:dma_out_0 + + stream_connect=dma_in_0.axis_out:passthrough_0.axis_in + stream_connect=passthrough_0.axis_out:dma_out_0.axis_in + +- ``nk`` — instantiates each kernel (same syntax as non-streaming designs). +- ``stream_connect`` — wires AXI-Stream ports between kernel instances using + ``.:.`` syntax. + +No ``sp=`` lines are needed for the streaming ports themselves. Only the +memory-mapped ports on ``dma_in`` and ``dma_out`` require memory mapping, which +the linker assigns automatically when no explicit ``sp=`` is given. + +Host Application +================= + +In the host code, only the DMA endpoint kernels need to be controlled. The +freerunning ``passthrough`` kernel is not instantiated: + +.. code-block:: cpp + + vrt::Kernel dma_in(device, "dma_in_0"); + vrt::Kernel dma_out(device, "dma_out_0"); + // passthrough_0 is freerunning — no host handle needed + +Allocate buffers using ``argMemoryConfig()`` so the VRT runtime automatically +selects the correct memory bank for each kernel's memory-mapped argument: + +.. code-block:: cpp + + vrt::Buffer buffer_in(device, size, dma_in.argMemoryConfig("in")); + vrt::Buffer buffer_out(device, size, dma_out.argMemoryConfig("out")); + +Set arguments, start both DMA kernels, and verify the output: + +.. code-block:: cpp + + buffer_in.sync(vrt::SyncType::HOST_TO_DEVICE); + + dma_in.setArg(0, buffer_in); + dma_in.setArg(1, size); + dma_out.setArg(0, size); + dma_out.setArg(1, buffer_out); + + dma_in.start(); + dma_out.start(); + dma_in.wait(); + dma_out.wait(); + + buffer_out.sync(vrt::SyncType::DEVICE_TO_HOST); + +.. note:: + + Both ``dma_in`` and ``dma_out`` must be started. If ``dma_out`` is not + ready to consume data, the pipeline will stall due to back-pressure. + +Build and Run +============== + +Ensure you have sourced Vivado and Vitis HLS before building: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +.. code-block:: bash + + cd examples/02_chain + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + cmake --build build + cmake --build build --target hls + cmake --build build --target chain_hw # or chain_emu / chain_sim + +.. code-block:: bash + + ./02_chain chain_hw.vbin + +Replace ```` with your board's address from ``v80-smi list``. + +Key Design Considerations +=========================== + +- **ap_ctrl_none** kernels cannot be started or stopped from the host. They + run whenever data is available on their input streams. +- **Stream widths must match** between connected ports. In this example all + three kernels use ``ap_uint<64>``. +- **Back-pressure** is handled automatically — if a downstream kernel is not + consuming, upstream stalls. +- For multi-stage pipelines, extend the ``stream_connect`` chain in + ``config.cfg``. + +Next Steps +========== + +- :doc:`/tutorials/user/your-first-kernel` — basic kernel authoring. +- :doc:`/tutorials/user/buffers-and-memory` — buffer management for DMA + endpoints. +- :doc:`/howto/use-cmake-modules` — CMake setup for HLS and vrtbin linking. +- :doc:`/explanation/architecture` — how streaming fits in the SLASH stack. diff --git a/docs/howto/index.rst b/docs/howto/index.rst new file mode 100644 index 00000000..37956b2b --- /dev/null +++ b/docs/howto/index.rst @@ -0,0 +1,24 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +How-To Guides +############## + +Task-oriented recipes for common operations. + +.. toctree:: + :maxdepth: 1 + + install-from-packages + use-multiple-boards + set-clock-frequency + chain-streaming-kernels + benchmark-memory + build-from-source + use-cmake-modules + inspect-vrtbin-metadata + use-mock-mode + migrate-from-xrt + use-rtl-kernels diff --git a/docs/howto/inspect-vrtbin-metadata.rst b/docs/howto/inspect-vrtbin-metadata.rst new file mode 100644 index 00000000..5db61edb --- /dev/null +++ b/docs/howto/inspect-vrtbin-metadata.rst @@ -0,0 +1,148 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +########################## +Inspect vrtbin Metadata +########################## + +This guide shows how to use ``v80-smi inspect`` and ``v80-smi query`` to +examine kernel information, clock frequency, and resource utilisation from a +vrtbin file or a live device. + +Prerequisites +============= + +- ``v80-smi`` is installed and on your ``PATH``. +- You have a vrtbin file to inspect, **or** a V80 board with a loaded design. +- See :doc:`/howto/build-from-source` for installation instructions. + +Inspect a vrtbin File +===================== + +Pass a vrtbin file path to ``v80-smi inspect``: + +.. code-block:: bash + + v80-smi inspect my_design.vbin + +Example output: + +.. code-block:: text + + Vbin my_design.vbin: + Platform: HARDWARE + Clock frequency: 200000000 + Utilization: + slash: LUTs: 42310 (4.81%), FFs: 53792 (3.06%), ... + Kernel: + Name: increment_0 + Physical address: 0x202000000000 + Argument: + Index: 0 + Name: data + Type: int* + Offset: 16 + Range: 64 + Direction: ReadWrite + +The output shows: + +- **Platform** — ``HARDWARE``, ``EMULATION``, or ``SIMULATION``. +- **Clock frequency** — the design clock in Hz. +- **Utilisation** — FPGA resource usage (hardware builds only). +- **Kernels** — each kernel instance with its physical address and arguments. + +JSON Output +----------- + +Use ``-J`` for pretty-printed JSON or ``-j`` for compact JSON (useful for +scripting): + +.. code-block:: bash + + v80-smi inspect my_design.vbin -J + +.. code-block:: json + + { + "clock_frequency": "0xbebc200", + "kernels": { + "increment_0": { + "name": "increment_0", + "address": "0x202000000000", + "args": [ + { + "index": "0x0", + "name": "data", + "type": "int*", + "offset": "0x10", + "range": "0x40", + "direction": "ReadWrite" + } + ] + } + } + } + +.. note:: + + Numeric fields (``clock_frequency``, ``address``, ``offset``, ``range``) + are encoded as hexadecimal strings in the JSON output to avoid integer + precision issues. + +Query a Live Device +=================== + +To read the metadata of the design currently loaded on a device, use +``v80-smi query``: + +.. code-block:: bash + + v80-smi query -d 03:00 + +The output format is identical to ``inspect``, but the data comes from the +device's system map rather than a file on disk. + +.. note:: + + The device must have been programmed with a vrtbin (via ``v80-smi program`` + or the VRT API). If no design is loaded, the command will report an error. + +Use ``v80-smi list`` to discover the BDF addresses of your boards. + +Understanding the Arguments +=========================== + +Each kernel argument entry contains: + +- **Index** — positional index in the HLS function signature. +- **Name** — the C++ parameter name from the HLS source. +- **Type** — the C++ type (e.g. ``int*``, ``unsigned int``). +- **Offset** — register offset within the kernel's AXI-Lite control block. +- **Range** — bit width of the argument register. +- **Direction** — ``Read``, ``Write``, or ``ReadWrite``. + +Understanding Utilisation +========================= + +Hardware vrtbin files include a utilisation report showing how much of the +FPGA fabric the design consumes: + +- **LUTs** — Look-Up Tables (combinational logic). +- **FFs** — Flip-Flops (sequential logic). +- **LUTRAM** — LUT-based distributed RAM. +- **SRL** — Shift Register LUTs. +- **RAMB36 / RAMB18** — Block RAM tiles. +- **URAM** — UltraRAM blocks. +- **DSP** — Digital Signal Processing slices. + +Each metric shows the absolute count and, when available, the percentage of +total resources used. + +Next Steps +========== + +- :doc:`/explanation/vrtbin-format` — understand the vrtbin archive structure. +- :doc:`/reference/smi/commands` — full ``v80-smi`` command reference. +- :doc:`/tutorials/admin/device-management` — device management workflows. diff --git a/docs/howto/install-from-packages.rst b/docs/howto/install-from-packages.rst new file mode 100644 index 00000000..56da412a --- /dev/null +++ b/docs/howto/install-from-packages.rst @@ -0,0 +1,496 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +###################### +Install from Packages +###################### + +This guide covers installing the SLASH stack from pre-built Debian or RPM +packages. This is the recommended installation method for most users. + +For building everything from source (e.g. for development or unsupported +distributions), see :doc:`build-from-source`. + +.. contents:: On this page + :depth: 2 + :local: + +Package Groups +============== + +SLASH is split into focused packages so you install only what you need. + +Runtime packages (required on every host with a V80 board): + +.. list-table:: + :header-rows: 1 + :widths: 25 75 + + * - Package + - Purpose + * - ``slash-dkms`` + - DKMS source for the ``slash`` kernel module. Compiles and installs + ``slash.ko`` for the running kernel automatically. + * - ``libslash`` + - Shared library for interacting with the kernel module over the + driver's character device. + * - ``vrtd`` + - Daemon that multiplexes device access, enforces permissions, and + manages board state. Includes systemd units, udev rules, and + default ``/etc/vrt/vrtd.conf``. + * - ``libvrtd`` + - Client libraries (``libvrtd`` C wire-protocol, ``libvrtdpp`` C++ + RAII wrapper) for applications that communicate with the daemon. + * - ``libvrt`` + - VRT C++ runtime library — the high-level API for kernels, buffers, + and device control. + * - ``v80-smi`` + - Board management CLI: ``list``, ``inspect``, ``program``, + ``query``, ``reset``, ``validate``. + +Development packages (required when building applications or HLS kernels): + +.. list-table:: + :header-rows: 1 + :widths: 25 75 + + * - Package + - Purpose + * - ``libslash-dev`` + - Headers and CMake targets for ``libslash``. + * - ``libvrtd-dev`` + - Headers and CMake targets for ``libvrtd`` / ``libvrtdpp``. + * - ``libvrt-dev`` + - Headers and CMake targets for ``libvrt``. + * - ``slashkit`` + - Python-based kernel linker that packages compiled HLS IP into + ``.vbin`` archives. Provides the ``build_hls_dir()`` and + ``add_vbin()`` CMake functions via the ``SlashTools`` module. + +Convenience metapackages: + +.. list-table:: + :header-rows: 1 + :widths: 25 75 + + * - Package + - Pulls in + * - ``slash`` + - All runtime packages above except ``v80-smi`` (install separately). + * - ``slash-dev`` + - All development packages above. + * - ``slash-sim-emu`` + - Runtime subset for simulation/emulation hosts (no board required). + * - ``slash-sim-emu-dev`` + - Development subset for simulation/emulation. + +Build the Packages +================== + +All packages — including the AMI driver package — are produced by a single +script run from the repository root: + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + .. code-block:: bash + + scripts/package-deb.sh + + Packages are written to ``./deb/``. + + .. tab-item:: RHEL / Rocky / Fedora + + .. code-block:: bash + + scripts/package-rpm.sh + + Packages are written to ``./rpm/``. + +Both scripts call ``scripts/package-ami.sh`` internally, so the AMI package +is built and placed in the same output directory as the SLASH packages. + +Install System Prerequisites +============================= + +Every target machine needs kernel headers so that DKMS can compile the +kernel module: + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + .. code-block:: bash + + sudo apt install linux-headers-$(uname -r) + + .. tab-item:: RHEL / Rocky / Fedora + + .. code-block:: bash + + sudo dnf install kernel-devel-$(uname -r) + +Other install-time dependencies (``dkms``, ``gcc``, libraries, etc.) are +declared by the packages themselves and will be pulled from the system +repositories automatically. + +Install the AMI Driver +======================= + +The V80 board's PF0 function (device ID ``0x50B4``) is managed by the +**AMI** (AVED Management Interface) kernel module. Install it before the +rest of the SLASH stack — ``vrtd`` requires AMI to be bound to PF0 to +manage the board. + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + .. code-block:: bash + + sudo apt install ./deb/ami__amd64.deb + + .. tab-item:: RHEL / Rocky / Fedora + + .. code-block:: bash + + sudo dnf install ./rpm/ami--1..x86_64.rpm + +.. warning:: + + If AMI is already installed on this system — for example, built from + source or installed from a separate vendor package — the generated AMI + package may conflict with the existing installation. Either remove the + existing AMI installation before proceeding, or skip this step and + ensure your installed AMI version is compatible with this SLASH release. + +After installation, verify that ``ami`` is bound to PF0: + +.. code-block:: bash + + lspci -d 10ee:50b4 -k + +You should see ``Kernel driver in use: ami``. + +Install Runtime Packages +========================= + +When installing from local package files, list all packages explicitly so +that the package manager can satisfy the inter-package dependencies in a +single transaction: + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + .. code-block:: bash + + sudo apt install \ + ./deb/slash-dkms__all.deb \ + ./deb/libslash__amd64.deb \ + ./deb/vrtd__amd64.deb \ + ./deb/libvrtd__amd64.deb \ + ./deb/libvrt__amd64.deb \ + ./deb/v80-smi__amd64.deb \ + ./deb/slashkit__amd64.deb + + .. tab-item:: RHEL / Rocky / Fedora + + .. code-block:: bash + + sudo dnf install \ + ./rpm/slash-dkms--1..noarch.rpm \ + ./rpm/libslash--1..x86_64.rpm \ + ./rpm/vrtd--1..x86_64.rpm \ + ./rpm/libvrtd--1..x86_64.rpm \ + ./rpm/libvrt--1..x86_64.rpm \ + ./rpm/v80-smi--1..x86_64.rpm \ + ./rpm/slashkit--1..x86_64.rpm + +.. note:: + + The ``slash`` metapackage and metapackage-based installs + (``sudo apt install slash``) only work when the packages are served + from a configured APT or DNF/YUM repository. Installing a bare + metapackage ``.deb`` or ``.rpm`` from a local file will fail because + the package manager cannot resolve its dependencies against local + files. + +After installation, DKMS automatically compiles and inserts the kernel +module for the running kernel. Verify it loaded: + +.. code-block:: bash + + lsmod | grep slash + +Start and Enable the Daemon +============================ + +The ``vrtd`` package installs a systemd service and socket. Enable it so +that it starts on boot and is running now: + +.. code-block:: bash + + sudo systemctl enable --now vrtd + +Check that the board is reachable through the daemon: + +.. code-block:: bash + + v80-smi list + +You should see one entry per V80 board with all four readiness indicators +passing (PF0, PF1, PF2, VRTD). + +Program the Board +================== + +.. note:: + + This step assumes the AMI driver is already bound to PF0 + (``10ee:50b4``). If your V80 has never been programmed with AVED — for + example, a brand-new board — first complete + :doc:`/tutorials/admin/bootstrap-aved` to install AVED via JTAG. + +After installing the packages, the board's flash memory must be programmed +with the static shell before the system can be used. This step is required: + +- on the **first install** of SLASH, and +- when **upgrading** to a version that changes the static shell (noted in + the release notes). + +It is **not** required after crashes, daemon restarts, or other normal +operations — SLASH reads from flash but never writes to it during regular use. + +Program the primary flash partition (replace ```` with the bus address +from ``v80-smi list``, e.g. ``03:00``): + +.. code-block:: bash + + # For Ubuntu 22.04 + sudo ami_tool cfgmem_program -d -t primary -p 0 \ + -i /usr/lib/python3.10/dist-packages/slashkit/resources/static_shell/amd_v80_gen5x8_25.1.pdi + + # For Rocky 9 + sudo ami_tool cfgmem_program -d -t primary -p 0 \ + -i /usr/lib/python3.9/site-packages/slashkit/resources/static_shell/amd_v80_gen5x8_25.1.pdi + +After programming completes, reboot the system for the new flash contents +to take effect: + +.. code-block:: bash + + sudo reboot + +Install Development Packages +============================== + +If you are writing applications against the VRT API or compiling HLS +kernels, install the development metapackage: + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + .. code-block:: bash + + sudo apt install \ + ./deb/libslash-dev__amd64.deb \ + ./deb/libvrtd-dev__amd64.deb \ + ./deb/libvrt-dev__amd64.deb \ + ./deb/slashkit__amd64.deb + + .. tab-item:: RHEL / Rocky / Fedora + + .. code-block:: bash + + sudo dnf install \ + ./rpm/libslash-devel--1..x86_64.rpm \ + ./rpm/libvrtd-devel--1..x86_64.rpm \ + ./rpm/libvrt-devel--1..x86_64.rpm \ + ./rpm/slashkit--1..x86_64.rpm + +This installs: + +- C++ headers under ``/usr/include/vrt/``, ``/usr/include/vrtd/``, and + ``/usr/include/slash/`` +- CMake package files under ``/usr/lib/cmake/`` +- The ``slashkit`` linker and the ``SlashTools`` CMake module + +CMake projects can then discover VRT with: + +.. code-block:: cmake + + find_package(vrt REQUIRED CONFIG) + target_link_libraries(my_app PRIVATE vrt::vrt) + +Before building HLS kernels or vrtbin files, source the Vivado and Vitis HLS +environment in your shell: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. SLASH has been +built and tested against **Vivado/Vitis 2025.1**; using other versions may +cause breakage. + +See :doc:`use-cmake-modules` for details on using the CMake integration. + +Install Emulation / Simulation Packages +======================================== + +To develop or run kernels in emulation or simulation without a physical +V80 board, install the ``slash-sim-emu`` subset: + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + .. code-block:: bash + + sudo apt install \ + ./deb/libslash__amd64.deb \ + ./deb/libvrtd__amd64.deb \ + ./deb/libvrt__amd64.deb + + For building emu/sim kernels, also install: + + .. code-block:: bash + + sudo apt install \ + ./deb/libslash-dev__amd64.deb \ + ./deb/libvrtd-dev__amd64.deb \ + ./deb/libvrt-dev__amd64.deb \ + ./deb/slashkit__amd64.deb + + .. tab-item:: RHEL / Rocky / Fedora + + .. code-block:: bash + + sudo dnf install \ + ./rpm/libslash--1..x86_64.rpm \ + ./rpm/libvrtd--1..x86_64.rpm \ + ./rpm/libvrt--1..x86_64.rpm + + For building emu/sim kernels, also install: + + .. code-block:: bash + + sudo dnf install \ + ./rpm/libslash-devel--1..x86_64.rpm \ + ./rpm/libvrtd-devel--1..x86_64.rpm \ + ./rpm/libvrt-devel--1..x86_64.rpm \ + ./rpm/slashkit--1..x86_64.rpm + +No board and no kernel module are required on emulation/simulation hosts. +The daemon is still needed if any component connects to ``vrtd``, but you +can point applications at the emulation platform directly. + +See :doc:`/tutorials/user/emulation-and-simulation` for a walkthrough. + +Upgrade and Removal +==================== + +.. note:: + + If the new version changes the static shell, re-program the board flash + after upgrading the packages. See `Program the Board`_ above. + +.. tab-set:: + + .. tab-item:: Debian / Ubuntu + + Re-run ``scripts/package-deb.sh`` to produce the new packages, then + reinstall with ``apt install`` — apt handles upgrades transparently + when given local ``.deb`` files: + + .. code-block:: bash + + sudo apt install \ + ./deb/ami__amd64.deb \ + ./deb/slash-dkms__all.deb \ + ./deb/libslash__amd64.deb \ + ./deb/vrtd__amd64.deb \ + ./deb/libvrtd__amd64.deb \ + ./deb/libvrt__amd64.deb \ + ./deb/v80-smi__amd64.deb \ + ./deb/slashkit__amd64.deb + + To remove all SLASH and AMI packages: + + .. code-block:: bash + + sudo apt remove ami slash-dkms libslash libvrtd libvrt \ + v80-smi slashkit vrtd + sudo apt autoremove + + .. tab-item:: RHEL / Rocky / Fedora + + Re-run ``scripts/package-rpm.sh``, then upgrade: + + .. code-block:: bash + + sudo dnf upgrade \ + ./rpm/ami--1..x86_64.rpm \ + ./rpm/slash-dkms--1..noarch.rpm \ + ./rpm/libslash--1..x86_64.rpm \ + ./rpm/vrtd--1..x86_64.rpm \ + ./rpm/libvrtd--1..x86_64.rpm \ + ./rpm/libvrt--1..x86_64.rpm \ + ./rpm/v80-smi--1..x86_64.rpm \ + ./rpm/slashkit--1..x86_64.rpm + + To remove: + + .. code-block:: bash + + sudo dnf remove ami slash-dkms libslash libvrtd libvrt v80-smi slashkit vrtd + +.. note:: + + Removing ``slash-dkms`` automatically removes the kernel module from + DKMS management and unloads it if currently loaded. + +Troubleshooting +=============== + +**Kernel module did not load after install** + + DKMS compiles during package installation. If headers were missing at + that point, install them and rebuild: + + .. code-block:: bash + + sudo apt install linux-headers-$(uname -r) # Debian/Ubuntu + sudo dkms build slash/0.1 + sudo dkms install slash/0.1 + +**vrtd fails to start** + + Check the journal for errors: + + .. code-block:: bash + + sudo journalctl -u vrtd --no-pager + + Common causes: kernel module not loaded, or board not detected by the + OS (check ``lspci -d 10ee:``). + +**v80-smi list shows no boards** + + Verify the module is loaded (``lsmod | grep slash``) and that the + daemon is running (``systemctl status vrtd``). + +**Permission denied** + + The user must be in the ``vrtadmin`` group: + + .. code-block:: bash + + sudo usermod -aG vrtadmin + + Log out and back in for the change to take effect. diff --git a/docs/howto/migrate-from-xrt.rst b/docs/howto/migrate-from-xrt.rst new file mode 100644 index 00000000..498a7576 --- /dev/null +++ b/docs/howto/migrate-from-xrt.rst @@ -0,0 +1,652 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2026 Advanced Micro Devices, Inc + +######################### +Migrate from XRT to VRT +######################### + +This guide maps XRT (Xilinx Runtime) concepts to their VRT (V80 Runtime) +equivalents. It is intended for developers familiar with host code written +against XRT for Alveo U200/U250/U280/U55C boards, and provides the +reference needed to become productive on the Alveo V80 with VRT. + +.. note:: + + VRT targets the AMD Alveo V80 exclusively. The API surface is smaller + and more opinionated than XRT, so there is less to learn. + +Quick Reference +=============== + +.. list-table:: + :header-rows: 1 + :widths: 30 40 30 + + * - XRT + - VRT + - Header + * - ``xrt::device`` + - ``vrt::Device`` + - ```` + * - ``xrt::kernel`` + - ``vrt::Kernel`` + - ```` + * - ``xrt::bo`` + - ``vrt::Buffer`` + - ```` + * - ``xrt::run`` + - (integrated into ``vrt::Kernel``) + - ```` + * - xclbin + - vbin + - ```` + * - ``xrt::run::set_arg`` + - ``vrt::Kernel::setArg`` + - ```` + * - ``xrt::bo::sync`` + - ``vrt::Buffer::sync`` + - ```` + * - ``xrt::bo::map`` + - ``vrt::Buffer::operator[]`` / ``get()`` + - ```` + * - xbutil + - v80-smi + - CLI tool + * - ``XCL_EMULATION_MODE`` + - Built into vbin (platform auto-detected) + - -- + * - ``xrt::kernel::group_id`` + - ``vrt::Kernel::argMemoryConfig`` + - ```` + * - N/A + - ``vrt::Device::setFrequency`` + - ```` + +Architecture: What Changed +========================== + +XRT talks to the kernel driver directly via ioctls. VRT is one component +of the broader **SLASH** platform, which inserts a **daemon** (``vrtd``) +between the application and the driver: + +.. code-block:: text + + XRT: App --> libxrt_core --> xocl/xclmgmt (kernel driver) --> FPGA + + SLASH: App --> libvrt --> vrtd (daemon) --> slash (kernel driver) --> FPGA + +The daemon multiplexes device access across processes, manages DMA buffer +lifetimes, and handles FPGA programming. From the user's perspective, +this layering is transparent: the application code interacts with the +same style of Device/Kernel/Buffer objects regardless of how requests are +dispatched underneath. + +**What this means in practice:** + +* The ``vrtd`` daemon must be running before the application starts (it + is a systemd service). +* Multi-process access to the same device works without coordination + from the user side. +* There is no equivalent of ``xbmgmt`` -- management operations go + through ``vrtd`` or ``v80-smi``. + +Includes +======== + +XRT: + +.. code-block:: cpp + + #include + #include + #include + +VRT: + +.. code-block:: cpp + + #include + #include + #include + +Device Management +================= + +Opening a Device +---------------- + +XRT opens a device by index and loads an xclbin: + +.. code-block:: cpp + + auto device = xrt::device(0); + auto uuid = device.load_xclbin("design.xclbin"); + +VRT opens a device by PCIe BDF and programs a vbin in one step: + +.. code-block:: cpp + + vrt::Device device("d8:00", "design.vbin"); + +The constructor extracts the vbin archive, programs the FPGA, and parses +kernel metadata. To skip programming (when the device is already loaded): + +.. code-block:: cpp + + vrt::Device device("d8:00", "design.vbin", false); + +.. note:: + + **BDF format:** VRT uses board-level ``BB:DD`` or ``DDDD:BB:DD`` -- + no function suffix. Copy the address directly from ``v80-smi list`` + output. + +Binary Format: xclbin vs vbin +============================= + +.. list-table:: + :header-rows: 1 + :widths: 25 35 40 + + * - + - xclbin + - vbin + * - Format + - Custom Xilinx container + - tar archive + * - Contents + - Bitstream, metadata, clock info + - PDI, system_map.xml, (optional) emu/sim executables + * - Kernel metadata + - Embedded XML sections + - ``system_map.xml`` (auto-parsed) + * - Platform variants + - Separate files or ``--target`` flag + - Single file; platform (hw/emu/sim) embedded in metadata + +VRT auto-detects whether a vbin targets hardware, emulation, or +simulation. There is no ``XCL_EMULATION_MODE`` environment variable -- +the platform is a property of the vbin itself. + +You can inspect a vbin without a device: + +.. code-block:: bash + + v80-smi inspect design.vbin + +Kernel Execution +================ + +Getting a Kernel Handle +----------------------- + +XRT: + +.. code-block:: cpp + + auto kernel = xrt::kernel(device, uuid, "my_kernel"); + +VRT: + +.. code-block:: cpp + + vrt::Kernel kernel(device, "my_kernel_0"); + +.. note:: + + **Naming convention:** VRT kernel names include the instance suffix + from the design (e.g., ``"vadd_0"``), matching what appears in + ``system_map.xml``. + +Setting Arguments and Launching +------------------------------- + +XRT exposes two launch styles: a one-call form that takes the arguments +inline, and a staged form that sets arguments individually before +starting. VRT mirrors the same two styles directly on the ``Kernel`` +object. + +XRT -- one call, blocking: + +.. code-block:: cpp + + auto run = kernel(bo_in, bo_out, size); // set args + start + run.wait(); + +XRT -- staged: + +.. code-block:: cpp + + auto run = xrt::run(kernel); + run.set_arg(0, bo_in); + run.set_arg(1, bo_out); + run.set_arg(2, size); + run.start(); + run.wait(); + +VRT -- one call, blocking (``call`` sets the args, starts the kernel, +and waits for completion): + +.. code-block:: cpp + + kernel.call(buffer_in, buffer_out, size); + +VRT -- one call, non-blocking (``start`` with arguments sets them and +starts execution without blocking): + +.. code-block:: cpp + + kernel.start(buffer_in, buffer_out, size); + // ... do other work ... + kernel.wait(); + +VRT -- staged with ``setArg`` + ``start`` / ``call``: + +.. code-block:: cpp + + kernel.setArg(0, buffer_in); + kernel.setArg(1, buffer_out); + kernel.setArg(2, size); + kernel.start(); // non-blocking; pair with kernel.wait() + // or + kernel.call(); // blocking equivalent of start() + wait() + +Arguments can also be set by name: + +.. code-block:: cpp + + kernel.setArg("input", buffer_in); + kernel.setArg("output", buffer_out); + kernel.setArg("size", 1024); + kernel.call(); + +.. list-table:: + :header-rows: 1 + :widths: 40 20 20 20 + + * - Style + - Sets args + - Starts + - Waits + * - ``kernel.call(args...)`` + - yes + - yes + - yes + * - ``kernel.start(args...)`` + - yes + - yes + - no + * - ``setArg(...)`` + ``kernel.call()`` + - yes + - yes + - yes + * - ``setArg(...)`` + ``kernel.start()`` + - yes + - yes + - no + +.. note:: + + **Buffer arguments are resolved automatically.** When you pass a + ``vrt::Buffer`` to ``call``, ``start``, or ``setArg``, VRT extracts + the physical address. No need to call ``.address()`` or similar. + +Reading Output Registers +------------------------ + +XRT: Read kernel outputs via ``xrt::bo`` or register access. + +VRT: Read directly from kernel registers by offset: + +.. code-block:: cpp + + uint32_t result = kernel.read(0x18); + +Buffer Management +================= + +Creating Buffers +---------------- + +XRT allocates buffer objects with a memory group: + +.. code-block:: cpp + + auto bo = xrt::bo(device, size_bytes, kernel.group_id(0)); + +VRT uses typed, element-counted buffers. Memory placement comes from +kernel metadata: + +.. code-block:: cpp + + vrt::Buffer buf(device, num_elements, kernel.argMemoryConfig("input")); + +``argMemoryConfig()`` returns a ``MemoryConfig`` that encodes the correct +memory type (DDR, HBM, or HBM_VNOC) and HBM port for that kernel +argument -- the VRT equivalent of XRT's ``group_id()``. + +.. list-table:: + :header-rows: 1 + :widths: 50 50 + + * - XRT + - VRT + * - ``xrt::bo(device, size_bytes, group_id)`` + - ``vrt::Buffer(device, num_elements, kernel.argMemoryConfig("arg"))`` + * - Size in **bytes** + - Size in **elements** (byte size = ``num_elements * sizeof(T)``) + * - Untyped (``void*``) + - Typed (``T*``) + +Writing Data to a Buffer +------------------------ + +XRT: + +.. code-block:: cpp + + auto host_ptr = bo.map(); + for (int i = 0; i < n; i++) host_ptr[i] = i; + +VRT buffers are directly subscriptable: + +.. code-block:: cpp + + for (int i = 0; i < n; i++) buf[i] = static_cast(i); + +You can also get a raw pointer if needed: + +.. code-block:: cpp + + float* ptr = buf.get(); + +Synchronizing Buffers +--------------------- + +XRT: + +.. code-block:: cpp + + bo.sync(XCL_BO_SYNC_BO_TO_DEVICE); + // ... run kernel ... + bo.sync(XCL_BO_SYNC_BO_FROM_DEVICE); + +VRT: + +.. code-block:: cpp + + buf.sync(vrt::SyncType::HOST_TO_DEVICE); + // ... run kernel ... + buf.sync(vrt::SyncType::DEVICE_TO_HOST); + +Memory Types +------------ + +VRT exposes three memory types through ``MemoryRangeType``: + +.. list-table:: + :header-rows: 1 + :widths: 35 65 + + * - VRT Memory Type + - Description + * - ``MemoryRangeType::DDR`` + - DDR memory + * - ``MemoryRangeType::HBM`` + - HBM with explicit port (0-63) + * - ``MemoryRangeType::HBM_VNOC`` + - HBM via Virtual Network-on-Chip (auto-distributed) + +When using ``kernel.argMemoryConfig()``, the correct type and port are +selected automatically from the design metadata. This is the recommended +approach. + +CLI: xbutil vs v80-smi +====================== + +.. list-table:: + :header-rows: 1 + :widths: 25 35 40 + + * - Task + - XRT (xbutil) + - VRT (v80-smi) + * - List devices + - ``xbutil examine`` + - ``v80-smi list`` + * - Detailed device info + - ``xbutil examine -d `` + - ``v80-smi list -l`` + * - Program device + - ``xbutil program -d -u `` + - ``v80-smi program -d `` + * - Reset device + - ``xbutil reset -d `` + - ``v80-smi reset -d `` + * - Validate device + - ``xbutil validate`` + - ``v80-smi validate -d `` + * - Inspect binary + - ``xclbinutil --info -i `` + - ``v80-smi inspect `` + * - Query loaded design + - -- + - ``v80-smi query -d `` + * - JSON output + - -- + - Add ``-j`` or ``-J`` to most commands + * - Version + - ``xbutil --version`` + - ``v80-smi version`` + +CMake Integration +================= + +XRT: + +.. code-block:: cmake + + find_package(XRT REQUIRED) + target_link_libraries(myapp PRIVATE XRT::xrt_coreutil) + +VRT: + +.. code-block:: cmake + + find_package(vrt REQUIRED CONFIG) + target_link_libraries(myapp PRIVATE vrt::vrt) + +Full example: + +.. code-block:: cmake + + cmake_minimum_required(VERSION 3.20) + project(my_v80_app LANGUAGES CXX) + + set(CMAKE_CXX_STANDARD 20) + set(CMAKE_CXX_STANDARD_REQUIRED ON) + + find_package(vrt REQUIRED CONFIG) + + add_executable(my_app main.cpp) + target_link_libraries(my_app PRIVATE vrt::vrt) + +See :doc:`use-cmake-modules` for the full CMake module reference. + +Multi-Device +============ + +XRT: + +.. code-block:: cpp + + auto dev0 = xrt::device(0); + auto dev1 = xrt::device(1); + +VRT uses BDF strings instead of indices: + +.. code-block:: cpp + + vrt::Device fpga0("e2:00", "design.vbin"); + vrt::Device fpga1("21:00", "design.vbin"); + +Each device is fully independent -- separate kernels, buffers, and +frequencies: + +.. code-block:: cpp + + vrt::Kernel k0(fpga0, "vadd_0"); + vrt::Kernel k1(fpga1, "vadd_0"); + + vrt::Buffer buf0(fpga0, 1024, k0.argMemoryConfig("in")); + vrt::Buffer buf1(fpga1, 1024, k1.argMemoryConfig("in")); + +Use ``v80-smi list`` to discover available board addresses. The format +is ``BB:DD`` (no function suffix) -- copy the address directly from the +command output. See :doc:`use-multiple-boards` for more detail. + +Clock Frequency Control +======================= + +VRT exposes runtime clock frequency control, which has no direct XRT +equivalent: + +.. code-block:: cpp + + std::cout << "Current: " << device.getFrequency() << " Hz\n"; + std::cout << "Max: " << device.getMaxFrequency() << " Hz\n"; + + device.setFrequency(300000000); // 300 MHz + +See :doc:`set-clock-frequency` for more detail. + +Emulation and Simulation +======================== + +XRT: Set ``XCL_EMULATION_MODE=hw_emu`` or ``sw_emu`` and run with an +emulation xclbin. + +VRT: Build the design for the target platform (hw, emu, or sim) and use +the corresponding vbin. The platform is auto-detected -- no environment +variable needed: + +.. code-block:: cpp + + // Same host code for all three. The vbin determines the platform. + vrt::Device device(bdf, "design_emu.vbin"); + + // Check which platform is active: + if (device.getPlatform() == vrt::Platform::EMULATION) { + std::cout << "Running in emulation mode\n"; + } + +Platform values: ``vrt::Platform::HARDWARE``, ``vrt::Platform::EMULATION``, +``vrt::Platform::SIMULATION``. + +See :doc:`/explanation/platform-modes` for further background. + +Logging +======= + +VRT has a built-in logger with configurable verbosity: + +.. code-block:: cpp + + #include + + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::DEBUG); + +Log levels: ``NONE``, ``WARN``, ``ERROR``, ``INFO``, ``DEBUG``. + +Complete Example: Vector Add +============================ + +Here is a minimal vadd host program showing the full XRT-to-VRT +translation. + +XRT version: + +.. code-block:: cpp + + #include + #include + #include + + int main() { + auto device = xrt::device(0); + auto uuid = device.load_xclbin("vadd.xclbin"); + auto kernel = xrt::kernel(device, uuid, "vadd"); + + auto bo_a = xrt::bo(device, 1024 * sizeof(int), kernel.group_id(0)); + auto bo_b = xrt::bo(device, 1024 * sizeof(int), kernel.group_id(1)); + auto bo_c = xrt::bo(device, 1024 * sizeof(int), kernel.group_id(2)); + + auto a = bo_a.map(); + auto b = bo_b.map(); + for (int i = 0; i < 1024; i++) { a[i] = i; b[i] = i; } + + bo_a.sync(XCL_BO_SYNC_BO_TO_DEVICE); + bo_b.sync(XCL_BO_SYNC_BO_TO_DEVICE); + + auto run = xrt::run(kernel); + run.set_arg(0, bo_a); + run.set_arg(1, bo_b); + run.set_arg(2, bo_c); + run.set_arg(3, 1024); + run.start(); + run.wait(); + + bo_c.sync(XCL_BO_SYNC_BO_FROM_DEVICE); + auto c = bo_c.map(); + // verify c[i] == 2*i + } + +VRT version: + +.. code-block:: cpp + + #include + #include + #include + + int main() { + vrt::Device device("d8:00", "vadd.vbin"); + vrt::Kernel vadd(device, "vadd_0"); + + vrt::Buffer a(device, 1024, vadd.argMemoryConfig("a")); + vrt::Buffer b(device, 1024, vadd.argMemoryConfig("b")); + vrt::Buffer c(device, 1024, vadd.argMemoryConfig("c")); + + for (int i = 0; i < 1024; i++) { a[i] = i; b[i] = i; } + + a.sync(vrt::SyncType::HOST_TO_DEVICE); + b.sync(vrt::SyncType::HOST_TO_DEVICE); + + // One-call blocking form (set args + start + wait): + vadd.call(a, b, c, 1024); + + // Equivalent staged form: + // vadd.setArg("a", a); + // vadd.setArg("b", b); + // vadd.setArg("c", c); + // vadd.setArg("size", 1024); + // vadd.start(); // non-blocking + // vadd.wait(); + + c.sync(vrt::SyncType::DEVICE_TO_HOST); + // verify c[i] == 2*i + } + +**Key differences at a glance:** + +* Device by BDF, not index. Programming and xclbin-loading combined into + the constructor. +* No UUID. Kernel lookup by name only. +* No separate ``xrt::run`` object. ``call``/``start``/``setArg``/``wait`` + live on ``Kernel`` directly. +* Buffers are typed and element-counted. Memory placement via + ``argMemoryConfig()``. +* Explicit ``sync()`` with enum direction instead of ``XCL_BO_SYNC_*`` + macros. +* Device and buffer cleanup is automatic via RAII, same as XRT. diff --git a/docs/howto/set-clock-frequency.rst b/docs/howto/set-clock-frequency.rst new file mode 100644 index 00000000..07900c52 --- /dev/null +++ b/docs/howto/set-clock-frequency.rst @@ -0,0 +1,111 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +###################### +Set Clock Frequency +###################### + +This guide explains how to configure the kernel clock frequency at build time +and adjust it at runtime using the VRT Device API. + +Prerequisites +============= + +- The SLASH stack is installed. +- A V80 board is visible (``v80-smi list``) and ``vrtd`` is running. +- Familiarity with building a SLASH application. + See :doc:`/tutorials/user/your-first-kernel`. + +Where Clock Frequency Is Set +============================= + +Clock frequency can be specified at three levels. Each level overrides the +previous one at its respective stage. + +Build-Time: HLS Configuration +------------------------------ + +The HLS ``.cfg`` file sets the synthesis target clock period: + +.. code-block:: ini + + clock=2ns + +A period of ``2ns`` targets 500 MHz; ``4ns`` targets 250 MHz. This value +drives the timing constraints during HLS compilation. + +Build-Time: Linker Configuration +--------------------------------- + +The ``config.cfg`` ``[clock]`` section sets the frequency recorded in the +vrtbin's ``system_map.xml``: + +.. code-block:: ini + + [clock] + krnl=vadd_0 + freqhz=400000000 + +This value (in Hz) is what the design reports as its clock frequency when +inspected with ``v80-smi inspect``. + +Runtime: VRT Device API +------------------------ + +After opening a device, you can read and change the frequency from your host +application: + +.. code-block:: cpp + + std::cout << "Current frequency: " << device.getFrequency() << " Hz\n"; + std::cout << "Max frequency: " << device.getMaxFrequency() << " Hz\n"; + + device.setFrequency(300000000); // 300 MHz + + std::cout << "New frequency: " << device.getFrequency() << " Hz\n"; + +Build and Run the Example +========================== + +Ensure you have sourced Vivado and Vitis HLS before building: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +Example ``04_freq`` demonstrates all three levels: + +.. code-block:: bash + + cd examples/04_freq + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + cmake --build build + cmake --build build --target hls + cmake --build build --target freq_hw # or freq_emu / freq_sim + +Run: + +.. code-block:: bash + + ./04_freq freq_hw.vbin + +Replace ```` with your board's address from ``v80-smi list``. + +Frequency Guidelines +===================== + +- Frequencies are always specified in **Hz** (e.g. ``300000000`` for 300 MHz). +- Do not exceed the value returned by ``getMaxFrequency()``. +- Lower frequencies can improve timing closure for complex designs. +- Higher frequencies increase throughput but may cause timing violations. +- The user's ``vrtd`` role must include the ``clock`` permission. + See :doc:`/reference/vrtd/configuration`. + +Next Steps +========== + +- :doc:`/reference/vrt-api/device` — full Device API reference. +- :doc:`/howto/use-cmake-modules` — CMake project setup. +- :doc:`/reference/vrtd/configuration` — permission keys including ``clock``. diff --git a/docs/howto/use-cmake-modules.rst b/docs/howto/use-cmake-modules.rst new file mode 100644 index 00000000..f0859761 --- /dev/null +++ b/docs/howto/use-cmake-modules.rst @@ -0,0 +1,154 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +##################### +Use CMake Modules +##################### + +This guide shows how to set up a new CMake project that compiles HLS +kernels and links vrtbin archives using the SLASH CMake modules. + +Installed SLASH (Recommended) +============================= + +If SLASH is installed system-wide (via ``sudo make install``), use +``find_package`` to import the modules and the VRT library: + +.. code-block:: cmake + + cmake_minimum_required(VERSION 3.20) + project(my_project LANGUAGES CXX) + set(CMAKE_CXX_STANDARD 20) + + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + + # Your application + add_executable(my_app main.cpp) + target_link_libraries(my_app PRIVATE vrt::vrt) + +``find_package(SlashTools)`` makes ``build_hls()``, ``build_hls_dir()``, +and ``add_vbin()`` available. It also includes ``FindVivado`` automatically. + +Source-Tree SLASH +================= + +When developing against the SLASH repository without installing, add the +CMake module path and VRT as a subdirectory: + +.. code-block:: cmake + + option(SLASH_USE_REPO "Build against local repo tree" OFF) + + if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_LIBS vrt) + else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + set(_VRT_LIBS vrt::vrt) + endif() + + add_executable(my_app main.cpp) + target_link_libraries(my_app PRIVATE ${_VRT_LIBS}) + +Configure with: + +.. code-block:: bash + + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + +HLS Kernel Directory +==================== + +``build_hls_dir()`` expects a directory containing matched pairs of +``.cpp`` and ``.cfg`` files: + +.. code-block:: text + + hls/ + ├── my_kernel.cpp + ├── my_kernel.cfg + ├── other_kernel.cpp + └── other_kernel.cfg + +Add this to your ``CMakeLists.txt``: + +.. code-block:: cmake + + set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") + + build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS my_kernel other_kernel + OUT_KERNELS _KERNELS + ) + +The ``_KERNELS`` variable receives the list of compiled kernel IP paths, +which you pass to ``add_vbin()`` below. + +See :doc:`/reference/cmake/buildhls` for the full ``build_hls_dir()`` and +``build_hls()`` reference. + +Linking Vrtbin Archives +======================= + +Create a linker configuration file (``config.cfg``): + +.. code-block:: ini + + [connectivity] + nk=my_kernel:1:my_kernel_0 + nk=other_kernel:1:other_kernel_0 + sp=my_kernel_0.m_axi_gmem0:HBM1 + +Then add vrtbin targets for each platform: + +.. code-block:: cmake + + set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + + add_vbin(TARGET "design_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "design_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "design_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +See :doc:`/reference/cmake/slashtools` for the full ``add_vbin()`` +reference. + +Locating Vivado and Vitis +========================= + +Before configuring or building, source the Vivado and Vitis HLS environment in +your shell: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. SLASH has been +built and tested against **Vivado/Vitis 2025.1**; using other versions may +cause breakage. + +The SLASH CMake modules will then automatically find Vivado and Vitis on +``PATH``. + +Build Sequence +============== + +.. code-block:: bash + + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON # or without flag if SLASH is installed + cmake --build build # build the host application + cmake --build build --target hls # compile HLS kernels (requires Vitis HLS) + cmake --build build --target design_hw # link hardware vrtbin + cmake --build build --target design_emu # link emulation vrtbin + +The host application and HLS compilation are independent — you can build +them in either order. The vrtbin targets depend on the HLS kernels. diff --git a/docs/howto/use-mock-mode.rst b/docs/howto/use-mock-mode.rst new file mode 100644 index 00000000..a55b6abb --- /dev/null +++ b/docs/howto/use-mock-mode.rst @@ -0,0 +1,140 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +Use Mock Mode +################ + +This guide shows how to use the libslash mock mode to test BAR access code +without a physical V80 board. + +Prerequisites +============= + +- libslash built and installed (or available in the build tree). +- No V80 hardware required. + +What is Mock Mode? +================== + +Mock mode provides an in-memory substitute for a V80 control device. When +you open a device with the special path ``"@mock"``, libslash creates a +temporary backing file instead of talking to the kernel driver. This lets +you develop and test BAR read/write logic on any Linux machine — including +CI runners with no FPGA hardware. + +Opening a Mock Device +===================== + +Pass the sentinel string ``"@mock"`` to ``slash_ctldev_open()``: + +.. code-block:: c + + #include + + struct slash_ctldev *ctldev = slash_ctldev_open("@mock"); + if (!ctldev) { + perror("mock open failed"); + return -1; + } + +The returned handle behaves like a real control device for BAR operations. + +What Mock Mode Provides +======================= + +- **BAR 0** is usable with a size of 64 MB. +- A temporary backing file is created in ``$XDG_RUNTIME_DIR`` (or ``/tmp`` + as fallback) and memory-mapped with ``MAP_SHARED``. +- Full 32-bit and 64-bit read/write through the mapped pointer. +- ``slash_device_info_read()`` returns a zeroed BDF (``0000:00:00.0``). +- ``slash_bar_info_read(ctldev, 0)`` reports BAR 0 as usable with + ``length = 64 * 1024 * 1024``. + +What Mock Mode Does Not Provide +================================ + +- **BARs 1–5** are reported as unusable (zero length). +- **QDMA** queue pairs — no DMA transfers. +- **Hotplug** operations — no PCIe reset or rescan. +- **Real PCIe enumeration** — no sysfs interaction. +- **Sensor readings** — no AMI management interface. +- **DMA-buf sync** — ``slash_bar_file_start_write()`` and + ``slash_bar_file_end_write()`` are no-ops on mock devices. + +Example: Read and Write BAR Registers +======================================== + +.. code-block:: c + + #include + #include + #include + #include + + int main(void) { + /* Open mock device */ + struct slash_ctldev *ctldev = slash_ctldev_open("@mock"); + assert(ctldev); + + /* Query BAR 0 properties */ + struct slash_ioctl_bar_info *info = slash_bar_info_read(ctldev, 0); + assert(info->usable); + assert(info->length == 64 * 1024 * 1024); + free(info); + + /* Map BAR 0 for read/write */ + struct slash_bar_file *bar = slash_bar_file_open(ctldev, 0, O_RDWR); + assert(bar); + + /* Write and read back through the mapped region */ + uint32_t *regs = (uint32_t *)bar->map; + regs[0] = 0xDEADBEEF; + assert(regs[0] == 0xDEADBEEF); + + regs[4] = 0xA5A5A5A5; + assert(regs[4] == 0xA5A5A5A5); + + /* Clean up — backing file is deleted automatically */ + slash_bar_file_close(bar); + slash_ctldev_close(ctldev); + return 0; + } + +Using Mock Mode in Tests +======================== + +The libslash test suite in ``driver/libslash/tests/`` uses mock mode for all +its unit tests. This pattern works well for CI pipelines: + +1. Open the device with ``"@mock"`` — no hardware detection needed. +2. Exercise BAR read/write logic against the 64 MB mapped region. +3. Verify register values, offsets, and access patterns. +4. Clean up — the temporary file is unlinked when the device is closed. + +Since mock devices require no kernel module or daemon, tests can run in +unprivileged containers and in any CI environment. + +Backing File Internals +====================== + +When a mock device is opened, libslash: + +1. Generates a random filename (``slash.mock.`` in + ``$XDG_RUNTIME_DIR`` or ``/tmp``). +2. Creates the file with ``O_RDWR | O_CREAT | O_EXCL`` and mode ``0600``. +3. Truncates to 64 MB. +4. Maps with ``mmap(PROT_READ | PROT_WRITE, MAP_SHARED)``. + +On close, the file is ``munmap``'d and ``unlink``'d. If the process +terminates abnormally, the file remains in the temp directory but occupies +only as much disk space as was actually written (sparse file). + +See Also +======== + +- :doc:`/explanation/architecture` — how libslash fits in the SLASH stack. +- :doc:`/reference/libslash-api/ctldev` — full control device API reference. +- :doc:`/explanation/pcie-topology` — the real PCIe functions that mock mode + replaces. diff --git a/docs/howto/use-multiple-boards.rst b/docs/howto/use-multiple-boards.rst new file mode 100644 index 00000000..d35848c2 --- /dev/null +++ b/docs/howto/use-multiple-boards.rst @@ -0,0 +1,146 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +###################### +Use Multiple Boards +###################### + +This guide shows how to control multiple V80 boards from a single application +using separate ``vrt::Device`` instances. + +Prerequisites +============= + +- Two or more V80 boards installed and visible via ``v80-smi list``. +- The SLASH stack is installed and ``vrtd`` is running. +- A vrtbin file built for the target design. +- See :doc:`/tutorials/user/getting-started` for an introduction to the VRT + workflow. + +Identifying Your Boards +======================== + +Run ``v80-smi list`` to discover the BDF address of each board: + +.. code-block:: bash + + v80-smi list + +Each board is listed with a unique BDF (Bus:Device.Function). Note the BDF for +every board you intend to use. + +Opening Multiple Devices +======================== + +Create a separate ``vrt::Device`` for each board. Both can load the same +vrtbin: + +.. code-block:: cpp + + vrt::Device fpga0("e2:00.0", "my_design.vrtbin", false, vrt::ProgramType::FLASH); + vrt::Device fpga1("21:00.0", "my_design.vrtbin", false, vrt::ProgramType::FLASH); + +.. note:: + + Replace the BDF strings with the addresses reported by ``v80-smi list`` on + your system. The addresses above are examples. + +Each ``Device`` manages its own connection to the ``vrtd`` daemon and its own +FPGA state. + +Per-Device Kernels and Buffers +=============================== + +Kernels and buffers are scoped to the device that created them. Create +separate instances for each board: + +.. code-block:: cpp + + // Kernels on fpga0 + vrt::Kernel increment0(fpga0, "increment_0"); + vrt::Kernel accumulate0(fpga0, "accumulate_0"); + + // Same kernel names, but on fpga1 + vrt::Kernel increment1(fpga1, "increment_0"); + vrt::Kernel accumulate1(fpga1, "accumulate_0"); + + // Buffers — one per device + vrt::Buffer buffer0(fpga0, size, increment0.argMemoryConfig("in")); + vrt::Buffer buffer1(fpga1, size, increment1.argMemoryConfig("in")); + +You cannot pass a buffer allocated on one device to a kernel on another. + +Running Kernels Independently +=============================== + +Each device operates independently. You can run kernels on different boards +sequentially or concurrently: + +.. code-block:: cpp + + buffer0.sync(vrt::SyncType::HOST_TO_DEVICE); + buffer1.sync(vrt::SyncType::HOST_TO_DEVICE); + + // Run on fpga0 + increment0.start(size, buffer0.getPhysAddr()); + accumulate0.start(size); + increment0.wait(); + accumulate0.wait(); + + // Run on fpga1 + increment1.start(size, buffer1.getPhysAddr()); + accumulate1.start(size); + increment1.wait(); + accumulate1.wait(); + +To maximise throughput, start kernels on both boards before waiting: + +.. code-block:: cpp + + increment0.start(size, buffer0.getPhysAddr()); + increment1.start(size, buffer1.getPhysAddr()); + // Both boards are now running in parallel + increment0.wait(); + increment1.wait(); + +Each device can also have its own clock frequency: + +.. code-block:: cpp + + fpga0.setFrequency(200000000); + fpga1.setFrequency(200000000); + +Cleanup +======= + +Call ``cleanup()`` on each device when done: + +.. code-block:: cpp + + fpga0.cleanup(); + fpga1.cleanup(); + +Complete Example +================ + +Example ``03_multiple_boards`` demonstrates this pattern using the +``increment`` and ``accumulate`` kernels from example ``00_axilite``. + +.. code-block:: bash + + cd examples/03_multiple_boards + cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + cmake --build build + +.. note:: + + This example reuses the vrtbin from example ``00_axilite``. Build that + example first to produce the vrtbin file. + +Next Steps +========== + +- :doc:`/reference/vrt-api/device` — full Device API reference. +- :doc:`/tutorials/user/buffers-and-memory` — buffer management in depth. +- :doc:`set-clock-frequency` — frequency tuning per device. diff --git a/docs/howto/use-rtl-kernels.rst b/docs/howto/use-rtl-kernels.rst new file mode 100644 index 00000000..3d5d56be --- /dev/null +++ b/docs/howto/use-rtl-kernels.rst @@ -0,0 +1,234 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2026 Advanced Micro Devices, Inc + +################## +Using RTL Kernels +################## + +RTL IP following the IP-XACT standard can be used directly as kernels in SLASH. +No intermediate compiled-object container is needed — the SLASH linker consumes +IP-XACT directories as produced by the Vivado IP Integrator. This guide is a +re-synthesis of the Vitis/XRT guide "Packaging RTL Kernels" (UG1393) adapted for +SLASH. Readers familiar with Vitis/XRT should consult the +`Differences from Vitis/XRT`_ section below for a concise summary of what has +changed. + +.. note:: + + The interface requirements for RTL kernels in SLASH are not yet formally + enforced. Treat the requirements stated here as strong guidelines that are + expected to hold in practice. + +Differences from Vitis/XRT +=========================== + +The general requirements for RTL kernels in SLASH are similar to those in Vitis/XRT +(UG1393, "Packaging RTL Kernels"), but the following terminology and concept changes +apply throughout. + +.. list-table:: + :header-rows: 1 + :widths: 35 35 30 + + * - Vitis/XRT + - SLASH + - Notes + * - Software emulation + - Emulation + - Behavioural C-model-based execution + * - Hardware emulation + - Simulation + - RTL Verilog simulation + * - ``.xclbin`` device binary + - ``.vbin`` device binary + - See :doc:`/explanation/vrtbin-format` + * - Compiled object file (``.xo``) + - Raw IP-XACT directory + - Vivado IP Integrator output; no additional packaging step needed + * - XRT-managed vs user-managed kernel + - No hard distinction + - See below + +**XRT-managed vs user-managed kernels** + +In Vitis/XRT there is a formal distinction between XRT-managed kernels — which must +implement the ``ap_ctrl_hs`` or ``ap_ctrl_chain`` control protocol — and user-managed +kernels, which can implement any control scheme. SLASH does not enforce this distinction +as a formal category. + +The VRT Kernel API provides two levels of use that can be applied to the same kernel: + +- **Direct register access** via ``kernel.read(offset)`` and + ``kernel.write(offset, value)``: works with any RTL kernel regardless of its + control scheme. +- **High-level launch API** — ``kernel.setArg(...)``, ``kernel.call(...)``, + ``kernel.start()``, ``kernel.wait()``: these implement the ``ap_ctrl_hs`` handshake + protocol on top of ``read`` and ``write``. A kernel intended to be used with this + API must expose the control register map described in + `Control Interface Register Map`_. + +There is no hard boundary between the two. A kernel may expose a control register and +be used with ``call()``/``wait()`` for convenience, or it may implement a completely +custom scheme driven entirely through ``read()``/``write()``. + +Kernel Interface Requirements +============================== + +To allow the SLASH linker to connect the kernel to the platform and to other kernels, +the RTL IP is expected to expose the following interfaces. All ports must be associated +with a bus interface in the IP-XACT packaging. + +.. list-table:: + :header-rows: 1 + :widths: 20 25 55 + + * - Port / Interface + - Description + - Notes + * - Clock + - One or more clock inputs + - At least one clock is required. The clock can be named anything. + * - Reset + - Active-Low reset input + - Optional. Should be associated with a clock via the + ``ASSOCIATED_RESET`` property. Internally pipeline the reset to + improve timing. The signal should be driven by a synchronous reset in + the associated clock domain. + * - ``interrupt`` + - Active-High interrupt + - Optional. When used, the port name must be exactly ``interrupt``. + * - ``s_axi_control`` + - AXI4-Lite slave control interface + - Optional for purely data-driven kernels. When present, the interface + name must be exactly ``s_axi_control`` (case-sensitive). + * - ``m_axi_*`` + - AXI4 memory-mapped master + - Optional. Must use 64-bit addresses. Must not use WRAP or FIXED burst + types; ``AxSIZE`` should match the AXI data bus width. Memory offsets + for each partition are supplied by the host through a register in the + ``s_axi_control`` interface. Non-conforming logic must be wrapped or + bridged to satisfy these requirements. + * - ``axis`` + - AXI4-Stream + - Optional. One-way only — bidirectional ports are not supported. + +.. note:: + + AMD recommends packaging AXI4 memory-mapped interfaces with + ``HAS_BURST=0`` and ``SUPPORTS_NARROW_BURST=0`` set in the IP-level + ``bd.tcl`` file, indicating that wrap/fixed burst types and narrow bursts + are not used. + +Control Interface Register Map +================================ + +The control register map is only required if the kernel is intended to be used with +the high-level VRT launch API (``setArg``, ``call``, ``start``, ``wait``). Kernels +driven exclusively through ``kernel.read()``/``kernel.write()`` may implement any +register scheme. + +When the high-level API is used, the VRT runtime communicates with the kernel through +the ``ap_ctrl_hs`` protocol over the ``s_axi_control`` interface. The expected register +layout matches the XRT-managed kernel layout from UG1393: + +.. list-table:: + :header-rows: 1 + :widths: 10 25 65 + + * - Offset + - Name + - Description + * - ``0x00`` + - Control + - Bit 0 (``ap_start``): write 1 to begin execution. Bit 1 + (``ap_done``): reads 1 when execution is complete. + * - ``0x04`` + - Global Interrupt Enable + - Optional; only required if the kernel signals an interrupt to the host. + * - ``0x08`` + - IP Interrupt Enable + - Optional. + * - ``0x0C`` + - IP Interrupt Status + - Optional. + * - ``0x10``\ + + - Kernel arguments + - Scalar arguments are 32 bits wide; ``m_axi`` and ``axis`` pointer + arguments are 64 bits wide. All user-defined registers must begin at + offset ``0x10``; offsets below this are reserved. + +Kernels driven through ``read()``/``write()`` only are free to place registers at any +offset, including below ``0x10``. + +Build Targets +============= + +RTL kernels support the **hardware** and **simulation** build targets. + +.. list-table:: + :header-rows: 1 + :widths: 20 15 65 + + * - Target + - Supported + - Notes + * - Hardware + - Yes + - Full Vivado implementation producing a ``.vbin`` device binary + * - Simulation + - Yes + - RTL simulated via the Verilog register model + * - Emulation + - No + - RTL kernels do not support the emulation build target + +See :doc:`/explanation/platform-modes` and +:doc:`/tutorials/user/emulation-and-simulation` for further background on build +targets. + +Design Recommendations +======================= + +Memory Performance +------------------ + +The AXI4 memory-mapped interfaces connect to the DDR and HBM memory controllers on +the platform. For best performance: + +- Match the AXI data width to the native memory controller width (typically 512 bits + on the V80). +- Do not use WRAP, FIXED, or sub-sized bursts. +- Use burst transfers as large as possible (up to the 4 KB AXI4 protocol limit). +- Avoid deasserted write strobes; these can cause ECC logic in the DDR memory + controller to perform read-modify-write operations. +- Use pipelined AXI transactions. +- Avoid generating write address commands if the kernel cannot deliver the full write + transaction, and avoid generating read address commands if the kernel cannot accept + all read data without back pressure. + +Quality of Results +------------------ + +- Pipeline all reset inputs and internally distribute resets, avoiding high-fanout nets. +- Reset only essential control-logic flip-flops. +- Consider registering input and output signals where possible. +- Account for the resource footprint of the kernel relative to the V80's capacity, + especially if multiple kernels are instantiated. + +Debug and Verification +---------------------- + +- Verify the RTL in a standalone testbench before integration. The AXI Verification + IP (VIP), available in the Vivado IP catalog, can help verify AXI interfaces. +- Use simulation builds to test host-side software integration and to observe + interactions between multiple kernels. +- ILA cores can be embedded inside RTL kernels for on-hardware debug. + +Next Steps +========== + +- :doc:`/tutorials/user/your-first-kernel` — HLS kernel walkthrough for comparison +- :doc:`/tutorials/user/emulation-and-simulation` — emulation and simulation builds +- :doc:`/explanation/platform-modes` — hardware, simulation, and emulation explained +- :doc:`/reference/cmake/slashtools` — ``add_vbin()`` reference diff --git a/docs/index.rst b/docs/index.rst index 1f23eb6a..3a87dd7a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -6,10 +6,53 @@ SLASH: An Open-Source Research Shell for Alveo V80 ################################################### -Documentation coming soon! +SLASH is an open-source platform for AMD Alveo V80 FPGA boards. It provides +a complete runtime and development ecosystem for FPGA kernel execution, device +management, and memory operations. + +.. toctree:: + :maxdepth: 2 + :caption: Tutorials + + tutorials/user/getting-started + tutorials/user/your-first-kernel + tutorials/user/buffers-and-memory + tutorials/user/emulation-and-simulation + tutorials/admin/platform-setup + tutorials/admin/bootstrap-aved + tutorials/admin/device-management + tutorials/admin/vrtd-configuration + +.. toctree:: + :maxdepth: 2 + :caption: How-To Guides + + howto/index + +.. toctree:: + :maxdepth: 2 + :caption: Reference + + reference/vrt-api/index + reference/libslash-api/index + reference/libvrtd-api/index + reference/libvrtdpp-api/index + reference/vrtd/index + reference/smi/index + reference/cmake/index + +.. toctree:: + :maxdepth: 2 + :caption: Explanation + + explanation/architecture + explanation/memory-model + explanation/vrtbin-format + explanation/pcie-topology + explanation/platform-modes .. toctree:: :maxdepth: 1 - :caption: Contents - - runtime \ No newline at end of file + :caption: Examples + + examples/index diff --git a/docs/reference/cmake/buildhls.rst b/docs/reference/cmake/buildhls.rst new file mode 100644 index 00000000..dcdd4dfe --- /dev/null +++ b/docs/reference/cmake/buildhls.rst @@ -0,0 +1,206 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############ +BuildHLS +############ + +``BuildHLS.cmake`` provides CMake functions for compiling HLS C++ kernels using +Vitis HLS. It is automatically included by :doc:`slashtools`, so you do not +need to include it separately. + +build_hls() +=========== + +Compiles a single HLS kernel from a C++ source file and configuration. + +.. code-block:: cmake + + build_hls( + TARGET + CPP + CFG + DEVICE + [OUT_DIR ] + ) + +Parameters +---------- + +``TARGET`` *(required)* + CMake target name for this kernel build. + +``CPP`` *(required)* + Path to the HLS C++ source file. + +``CFG`` *(required)* + Path to the Vitis HLS configuration file (``.cfg``). + +``DEVICE`` *(required)* + FPGA part string, e.g. ``xcv80-lsva4737-2MHP-e-S``. + +``OUT_DIR`` *(optional)* + Output directory. Defaults to ``CMAKE_CURRENT_BINARY_DIR``. + +Output Properties +----------------- + +After the target is created, two properties are set on it: + +``HLS_BUILD_DIR`` + The build directory containing HLS outputs. + +``HLS_COMPONENT_XML`` + Path to the generated ``component.xml`` file. This is the input for + ``add_vbin()``. + +The same values are also exported as ``${TARGET}_BUILD_DIR`` and +``${TARGET}_COMPONENT_XML`` in the calling scope. + +build_hls_dir() +=============== + +Compiles multiple HLS kernels from a directory containing paired +``.cpp`` and ``.cfg`` files. + +.. code-block:: cmake + + build_hls_dir( + TARGET + ROOT + DEVICE + KERNELS + [OUT_DIR ] + [OUT_IP_REPO ] + [OUT_KERNELS ] + ) + +Parameters +---------- + +``TARGET`` *(required)* + Umbrella CMake target name. Individual kernel targets are created as + ``${TARGET}_${kernel_name}``. + +``ROOT`` *(required)* + Directory containing kernel source files. For each name listed in + ``KERNELS``, the directory must contain ``.cpp`` and ``.cfg``. + +``DEVICE`` *(required)* + FPGA part string. + +``KERNELS`` *(required)* + List of kernel names to compile (without file extensions). + +``OUT_DIR`` *(optional)* + Output directory. Defaults to ``${CMAKE_CURRENT_BINARY_DIR}/${TARGET}``. + +``OUT_IP_REPO`` *(optional)* + Variable name to receive the IP repository output path. + +``OUT_KERNELS`` *(optional)* + Variable name to receive the list of ``component.xml`` paths for all + compiled kernels. Pass this to ``add_vbin(KERNELS ...)``. + +build_hls_clean() +================= + +Creates a CMake target that removes HLS build artefacts. + +.. code-block:: cmake + + build_hls_clean( + TARGET + DEVICE + [ROOT ] + [EXTRA_GLOBS ] + ) + +Parameters +---------- + +``TARGET`` *(required)* + Name for the clean target. + +``DEVICE`` *(required)* + Part string, used to match ``build_*.${DEVICE}`` directories. + +``ROOT`` *(optional)* + Directory to clean. Defaults to ``CMAKE_CURRENT_LIST_DIR``. + +``EXTRA_GLOBS`` *(optional)* + Additional glob patterns to remove. + +The generated clean target removes: build directories, log files, ``.Xil`` +directories, CMake cache files, and any patterns specified via +``EXTRA_GLOBS``. + +HLS Configuration File Format +============================== + +Each kernel requires a ``.cfg`` file for Vitis HLS. Example +(``increment.cfg``): + +.. code-block:: ini + + part=xcv80-lsva4737-2MHP-e-S + + [hls] + flow_target=vivado + + syn.top=increment + syn.file=increment.cpp + clock=4ns + + package.output.format=ip_catalog + package.output.syn=false + +``part`` + The FPGA part string for the V80 board. + +``syn.top`` + Top-level function name in the C++ source. + +``syn.file`` + Source file to compile. + +``clock`` + Target clock period (e.g. ``4ns`` = 250 MHz). + +``package.output.format`` + Must be ``ip_catalog`` for the SLASH linker. + +``package.output.syn`` + Set to ``false`` to defer RTL synthesis to the linker. + +Example +======= + +A complete CMakeLists.txt using all three functions: + +.. code-block:: cmake + + set(DEVICE "xcv80-lsva4737-2MHP-e-S") + + build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS increment accumulate + OUT_KERNELS _KERNELS + ) + + add_vbin(TARGET "my_design_hw" PLATFORM "hw" + CFG "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg" + KERNELS ${_KERNELS}) + + build_hls_clean(TARGET hls_clean DEVICE "${DEVICE}") + +Build with: + +.. code-block:: bash + + cmake --build build --target hls # compile all HLS kernels + cmake --build build --target my_design_hw # link into a hardware vrtbin + cmake --build build --target hls_clean # remove HLS build artefacts diff --git a/docs/reference/cmake/findtools.rst b/docs/reference/cmake/findtools.rst new file mode 100644 index 00000000..a6b98891 --- /dev/null +++ b/docs/reference/cmake/findtools.rst @@ -0,0 +1,123 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############################## +FindVivado and FindVitis +############################## + +SLASH provides two CMake find modules for locating AMD Vivado and Vitis HLS +installations. ``FindVivado`` is used internally by ``SlashTools.cmake``. +Both modules can also be included directly. + +FindVivado +========== + +Locates an AMD Vivado installation for FPGA synthesis and implementation. + +Search Order +------------ + +1. ``VIVADO_ROOT_DIR`` CMake variable. +2. ``XILINX_VIVADO`` environment variable. +3. System ``PATH`` (searches for ``vivado`` in ``bin/`` subdirectories). + +Variables Set +------------- + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Variable + - Description + * - ``VIVADO_FOUND`` + - ``TRUE`` if Vivado was located. + * - ``VIVADO_ROOT_DIR`` + - Root directory of the Vivado installation. + * - ``VIVADO_BINARY`` + - Full path to the ``vivado`` executable. + * - ``VIVADO_PATH`` + - Path to the ``bin/`` directory containing the Vivado binary. + +Usage +----- + +``FindVivado`` is included automatically by ``SlashTools.cmake`` — no +manual ``include()`` is needed in most projects. + +Source the Vivado environment before running CMake so that ``vivado`` is on +``PATH``: + +.. code-block:: bash + + source /settings64.sh + +For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. SLASH has been +built and tested against **Vivado 2025.1**; using other versions may cause +breakage. + +Error Behaviour +--------------- + +``FindVivado`` issues a ``FATAL_ERROR`` if the ``vivado`` binary cannot be +found. + +FindVitis +========= + +Locates an AMD Vitis HLS installation for kernel compilation. + +Search Order +------------ + +1. ``VITIS_ROOT_DIR`` CMake variable. +2. ``XILINX_VITIS`` environment variable. +3. ``VITIS_HOME`` environment variable. +4. ``VITIS`` environment variable. +5. System ``PATH`` (searches for ``vitis`` in ``bin/`` subdirectories). + +Variables Set +------------- + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Variable + - Description + * - ``VITIS_FOUND`` + - ``TRUE`` if Vitis was located. + * - ``VITIS_BINARY`` + - Full path to the ``vitis`` executable. + * - ``VITIS_ROOT_DIR`` + - Root directory of the Vitis installation. + * - ``VITIS_INCLUDE_DIR`` + - Path to the Vitis include directory (e.g. for ``ap_fixed.h``, + ``hls_stream.h``). Validated to exist. + +Usage +----- + +``FindVitis`` can be included manually if your project needs the Vitis root +or include directories. ``BuildHLS.cmake`` locates the ``v++`` and +``vitis-run`` executables directly and does not require this module. + +Source the Vitis HLS environment before running CMake so that ``vitis`` is +on ``PATH``: + +.. code-block:: bash + + source /settings64.sh + +For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. SLASH has been +built and tested against **Vitis HLS 2025.1**; using other versions may +cause breakage. + +Error Behaviour +--------------- + +``FindVitis`` issues a ``FATAL_ERROR`` if: + +- The ``vitis`` binary cannot be found. +- The include directory (``${VITIS_ROOT_DIR}/include``) does not exist. diff --git a/docs/reference/cmake/index.rst b/docs/reference/cmake/index.rst new file mode 100644 index 00000000..7c48caf9 --- /dev/null +++ b/docs/reference/cmake/index.rst @@ -0,0 +1,17 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +CMake Modules +################ + +SLASH provides CMake modules for integrating HLS compilation and FPGA design +linking into your build system. + +.. toctree:: + :maxdepth: 1 + + slashtools + buildhls + findtools diff --git a/docs/reference/cmake/slashtools.rst b/docs/reference/cmake/slashtools.rst new file mode 100644 index 00000000..f8a7f11a --- /dev/null +++ b/docs/reference/cmake/slashtools.rst @@ -0,0 +1,119 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +SlashTools +############## + +``SlashTools.cmake`` is the primary CMake module for building SLASH projects. +It provides the ``add_vbin()`` function for linking HLS kernels into vrtbin +archives, and automatically includes :doc:`buildhls` for HLS kernel +compilation. + +Including SlashTools +==================== + +When SLASH is installed system-wide: + +.. code-block:: cmake + + find_package(SlashTools REQUIRED) + +When building from the SLASH source tree: + +.. code-block:: cmake + + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + +``SlashTools`` automatically includes ``BuildHLS.cmake`` and locates Vivado via +``FindVivado.cmake``. + +add_vbin() +========== + +Links compiled HLS kernels into a ``.vbin`` archive for a given platform. + +.. code-block:: cmake + + add_vbin( + TARGET + PLATFORM + CFG + KERNELS + ) + +Parameters +---------- + +``TARGET`` *(required)* + Name of the CMake custom target. The output file will be + ``${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.vbin``. + +``PLATFORM`` *(required)* + Target platform. One of: + + - ``hw`` — hardware (real V80 board) + - ``emu`` — emulation (C-model, no FPGA required) + - ``sim`` — simulation (Verilog register map) + +``CFG`` *(required)* + Path to the linker configuration file containing ``[connectivity]`` + directives (``nk=``, ``stream_connect=``, ``sp=``). + +``KERNELS`` *(required)* + List of HLS component XML paths. These are typically produced by + ``build_hls_dir()`` via the ``OUT_KERNELS`` parameter. + +Operating Modes +---------------- + +``add_vbin()`` supports two modes for locating the SLASH linker: + +**Installed mode** (preferred) + If ``slashkit`` is found on ``PATH``, the function invokes it directly. + +**Source-tree mode** + If ``SLASH_REPO_ROOT`` is set (or auto-detected from the module's location), + the function invokes ``linker/src/main.py`` via Python 3. + +If neither mode is available, CMake emits a ``FATAL_ERROR``. + +Configuration Variables +======================== + +``SLASH_REPO_ROOT`` + Path to the SLASH repository root. Auto-detected when the CMake module is + located inside the repository tree. + +``SLASHKIT_EXECUTABLE`` + Path to the installed ``slashkit`` linker. Auto-detected via ``find_program()``. + +Example +======= + +From ``examples/00_axilite/CMakeLists.txt``: + +.. code-block:: cmake + + build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS increment accumulate + OUT_KERNELS _KERNELS + ) + + set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + add_vbin(TARGET "axilite_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "axilite_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "axilite_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +Build with: + +.. code-block:: bash + + cmake --build build --target hls # compile HLS kernels + cmake --build build --target axilite_hw # link hardware vrtbin + cmake --build build --target axilite_emu # link emulation vrtbin diff --git a/docs/reference/libslash-api/ctldev.rst b/docs/reference/libslash-api/ctldev.rst new file mode 100644 index 00000000..bfded94f --- /dev/null +++ b/docs/reference/libslash-api/ctldev.rst @@ -0,0 +1,10 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +######################## +Control Device (ctldev) +######################## + +.. doxygenfile:: slash/ctldev.h + :project: libslash diff --git a/docs/reference/libslash-api/hotplug.rst b/docs/reference/libslash-api/hotplug.rst new file mode 100644 index 00000000..cd2649dd --- /dev/null +++ b/docs/reference/libslash-api/hotplug.rst @@ -0,0 +1,10 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +######### +Hotplug +######### + +.. doxygenfile:: slash/hotplug.h + :project: libslash diff --git a/docs/reference/libslash-api/index.rst b/docs/reference/libslash-api/index.rst new file mode 100644 index 00000000..8f87eae0 --- /dev/null +++ b/docs/reference/libslash-api/index.rst @@ -0,0 +1,17 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +libslash C API +################ + +libslash is a userspace C library wrapping the SLASH kernel driver. It provides +three modules: Control (BAR access), QDMA (DMA transfers), and Hotplug (PCIe lifecycle). + +.. toctree:: + :maxdepth: 1 + + ctldev + qdma + hotplug diff --git a/docs/reference/libslash-api/qdma.rst b/docs/reference/libslash-api/qdma.rst new file mode 100644 index 00000000..d273c401 --- /dev/null +++ b/docs/reference/libslash-api/qdma.rst @@ -0,0 +1,10 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +###### +QDMA +###### + +.. doxygenfile:: slash/qdma.h + :project: libslash diff --git a/docs/reference/libvrtd-api/index.rst b/docs/reference/libvrtd-api/index.rst new file mode 100644 index 00000000..21ce7e11 --- /dev/null +++ b/docs/reference/libvrtd-api/index.rst @@ -0,0 +1,17 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############################ +libvrtd C Client API +############################ + +libvrtd is a C client library for communicating with the vrtd daemon over +a UNIX domain socket. It provides functions for device enumeration, BAR access, +QDMA queue management, buffer allocation, and more. + +.. toctree:: + :maxdepth: 1 + + vrtd + wire diff --git a/docs/reference/libvrtd-api/vrtd.rst b/docs/reference/libvrtd-api/vrtd.rst new file mode 100644 index 00000000..94a3124c --- /dev/null +++ b/docs/reference/libvrtd-api/vrtd.rst @@ -0,0 +1,10 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +##################### +vrtd Client Functions +##################### + +.. doxygenfile:: vrtd/vrtd.h + :project: libvrtd diff --git a/docs/reference/libvrtd-api/wire.rst b/docs/reference/libvrtd-api/wire.rst new file mode 100644 index 00000000..42b54939 --- /dev/null +++ b/docs/reference/libvrtd-api/wire.rst @@ -0,0 +1,12 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +Wire Protocol +################ + +On-wire protocol definitions shared between the vrtd daemon and its clients. + +.. doxygenfile:: vrtd/wire.h + :project: libvrtd diff --git a/docs/reference/libvrtdpp-api/bar-file.rst b/docs/reference/libvrtdpp-api/bar-file.rst new file mode 100644 index 00000000..93378574 --- /dev/null +++ b/docs/reference/libvrtdpp-api/bar-file.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +vrtd::BarFile +################ + +.. doxygenclass:: vrtd::BarFile + :project: libvrtdpp + :members: diff --git a/docs/reference/libvrtdpp-api/bar.rst b/docs/reference/libvrtdpp-api/bar.rst new file mode 100644 index 00000000..c4476002 --- /dev/null +++ b/docs/reference/libvrtdpp-api/bar.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############ +vrtd::Bar +############ + +.. doxygenclass:: vrtd::Bar + :project: libvrtdpp + :members: diff --git a/docs/reference/libvrtdpp-api/buffer.rst b/docs/reference/libvrtdpp-api/buffer.rst new file mode 100644 index 00000000..aacfcde3 --- /dev/null +++ b/docs/reference/libvrtdpp-api/buffer.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############### +vrtd::Buffer +############### + +.. doxygenclass:: vrtd::Buffer + :project: libvrtdpp + :members: diff --git a/docs/reference/libvrtdpp-api/device.rst b/docs/reference/libvrtdpp-api/device.rst new file mode 100644 index 00000000..651316cd --- /dev/null +++ b/docs/reference/libvrtdpp-api/device.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############### +vrtd::Device +############### + +.. doxygenclass:: vrtd::Device + :project: libvrtdpp + :members: diff --git a/docs/reference/libvrtdpp-api/index.rst b/docs/reference/libvrtdpp-api/index.rst new file mode 100644 index 00000000..a51a5d22 --- /dev/null +++ b/docs/reference/libvrtdpp-api/index.rst @@ -0,0 +1,20 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############################## +libvrtdpp C++ Client API +############################## + +libvrtdpp is a C++ wrapper around libvrtd, providing RAII-based classes for +interacting with the vrtd daemon. + +.. toctree:: + :maxdepth: 1 + + session + device + bar + bar-file + buffer + qdma-qpair diff --git a/docs/reference/libvrtdpp-api/qdma-qpair.rst b/docs/reference/libvrtdpp-api/qdma-qpair.rst new file mode 100644 index 00000000..9c24188f --- /dev/null +++ b/docs/reference/libvrtdpp-api/qdma-qpair.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################## +vrtd::QdmaQpair +################## + +.. doxygenclass:: vrtd::QdmaQpair + :project: libvrtdpp + :members: diff --git a/docs/reference/libvrtdpp-api/session.rst b/docs/reference/libvrtdpp-api/session.rst new file mode 100644 index 00000000..f20f9424 --- /dev/null +++ b/docs/reference/libvrtdpp-api/session.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +vrtd::Session +################ + +.. doxygenclass:: vrtd::Session + :project: libvrtdpp + :members: diff --git a/docs/reference/smi/commands.rst b/docs/reference/smi/commands.rst new file mode 100644 index 00000000..563a81b5 --- /dev/null +++ b/docs/reference/smi/commands.rst @@ -0,0 +1,309 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +##################### +Command Reference +##################### + +``v80-smi`` is the command-line system management interface for AMD Alveo V80 +boards. Running ``v80-smi`` with no subcommand prints usage help. + +Device Addressing +================= + +Several commands accept a ``-d/--device`` option that takes a **BDF** +(Bus:Device.Function) address. The following formats are supported: + +.. list-table:: + :header-rows: 1 + :widths: 30 30 + + * - Format + - Example + * - ``BB:DD`` (short) + - ``03:00`` + * - ``BB:DD.F`` (short with function) + - ``03:00.0`` + * - ``DDDD:BB:DD`` (domain:bus:device) + - ``0000:03:00`` + * - ``DDDD:BB:DD.F`` (full) + - ``0000:03:00.0`` + +Commands +======== + +version +------- + +Print the v80-smi version and exit. + +.. code-block:: text + + v80-smi version [-p|--plain] + +.. option:: -p, --plain + + Print only the version in ``x.y.z`` format with no prefix. Useful for + scripting. + +list +---- + +Enumerate V80 boards visible on the system and report their readiness status. + +.. code-block:: text + + v80-smi list [-j|--json] [-J|--pretty-json] [-l|--long] [-s|--sensors] + +.. option:: -j, --json + + Output as compact JSON. + +.. option:: -J, --pretty-json + + Output as indented JSON. + +.. option:: -l, --long + + Include additional information (PCI IDs, driver status). + +.. option:: -s, --sensors + + Include sensor readings (temperature, power). Requires the vrtd daemon to be + running. + +inspect +------- + +Display metadata from a vrtbin file on disk without programming it onto a +device. + +.. code-block:: text + + v80-smi inspect [-j|--json] [-J|--pretty-json] + +.. option:: vbin + + Path to the vrtbin file. **Required.** + +.. option:: -j, --json + + Output as compact JSON. + +.. option:: -J, --pretty-json + + Output as indented JSON. + +query +----- + +Display the metadata of the vrtbin currently loaded on a device. + +.. code-block:: text + + v80-smi query -d [-j|--json] [-J|--pretty-json] + +.. option:: -d, --device + + Board address. **Required.** + +.. option:: -j, --json + + Output as compact JSON. + +.. option:: -J, --pretty-json + + Output as indented JSON. + +program +------- + +Load a vrtbin file onto a device, programming the FPGA. + +.. code-block:: text + + v80-smi program -d + +.. option:: vbin + + Path to the vrtbin file. **Required.** + +.. option:: -d, --device + + Board address. **Required.** + +reset +----- + +Perform a hardware reset of a V80 board. This executes a full PCIe secondary +bus reset and rescan (hotplug) sequence. + +.. code-block:: text + + v80-smi reset -d + +.. option:: -d, --device + + Board address. **Required.** + +validate +-------- + +Run memory integrity and bandwidth tests against a board's HBM and DDR +subsystems. + +.. code-block:: text + + v80-smi validate -d [-j|--threads ] + +.. option:: -d, --device + + Board address. **Required.** + +.. option:: -j, --threads + + Number of parallel buffers/threads for the validation test (1–64, default 8). + +debug +----- + +Low-level troubleshooting commands. + +debug bar-poke +^^^^^^^^^^^^^^ + +Read or write BAR words. + +.. code-block:: text + + v80-smi debug bar-poke -d -b (-r|--read | -w|--write) [-x|--hex] [-W|--word-size ] [-c|--count ]
[value] + +.. option:: -d, --device + + Board address. **Required.** + +.. option:: -b, --bar + + BAR number (0-5). **Required.** + +.. option:: -r, --read + + Read mode. + +.. option:: -w, --write + + Write mode. + +.. option:: -x, --hex + + Print read output in hexadecimal. + +.. option:: -W, --word-size + + Access width in bytes: 1, 2, 4, or 8 (default 4). + +.. option:: -c, --count + + Number of words to read (default 1; must be 1 for write). + +Rules: + +- Exactly one of ``--read`` or ``--write`` must be provided. +- ``value`` is required for write and forbidden for read. +- ``address`` is a BAR-relative byte offset. + +debug mem-poke +^^^^^^^^^^^^^^ + +Read or write device memory at a raw physical address. This bypasses the +allocator and requires raw-mem-access permission in vrtd. + +.. code-block:: text + + v80-smi debug mem-poke -d (-r|--read | -w|--write) [-x|--hex] [-W|--word-size ] [-c|--count ]
[value] [-f|--file ] + +.. option:: -d, --device + + Board address. **Required.** + +.. option:: -r, --read + + Read mode. + +.. option:: -w, --write + + Write mode. + +.. option:: -x, --hex + + Hex mode. + + - Read-to-stdout: prints values in hexadecimal. + - With ``--file``: treats file payload as hex text/hexdump format. + +.. option:: -W, --word-size + + Access width in bytes: 1, 2, 4, or 8 (default 4). + +.. option:: -c, --count + + Number of words to transfer (default 1). + +.. option:: -f, --file + + File mode transfer path. + + - In read mode: destination file. + - In write mode: source file. + +Rules: + +- Exactly one of ``--read`` or ``--write`` must be provided. +- ``address`` is a device physical address. +- ``word-size`` must be 1, 2, 4, or 8. +- ``count`` must be greater than zero. +- Scalar mode (no ``--file``): + - write requires ``value`` and forces ``count == 1`` + - read forbids ``value`` + - address must be aligned to word-size +- File mode (``--file`` present): + - ``value`` is forbidden + - transfer size is exactly ``word-size * count`` bytes + - with ``--hex`` file is text hex/hexdump; without ``--hex`` file is raw binary + +debug clockwiz +^^^^^^^^^^^^^^ + +Read or set clock rate for a device clock region using vrtd clock-op. + +.. code-block:: text + + v80-smi debug clockwiz -d (--get | --set ) [--region ] [-x|--hex] + +.. option:: -d, --device + + Board address. **Required.** + +.. option:: --get + + Read current clock rate for selected region. + +.. option:: --set + + Set requested clock rate in Hz for selected region. + +.. option:: --region + + Clock region selector (default: ``user``). + +.. option:: -x, --hex + + Print ``--get`` output in hexadecimal. + +Rules: + +- Exactly one of ``--get`` or ``--set`` must be provided. +- ``--set`` value is in Hz and must be greater than zero. +- ``--hex`` is valid only with ``--get``. +- ``--set`` prints requested and achieved frequencies. diff --git a/docs/reference/smi/index.rst b/docs/reference/smi/index.rst new file mode 100644 index 00000000..b0565790 --- /dev/null +++ b/docs/reference/smi/index.rst @@ -0,0 +1,14 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +######### +v80-smi +######### + +v80-smi is the command-line system management interface for V80 devices. + +.. toctree:: + :maxdepth: 1 + + commands diff --git a/docs/reference/vrt-api/buffer.rst b/docs/reference/vrt-api/buffer.rst new file mode 100644 index 00000000..e3128727 --- /dev/null +++ b/docs/reference/vrt-api/buffer.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +vrt::Buffer +############## + +.. doxygenclass:: vrt::Buffer + :project: VRT + :members: diff --git a/docs/reference/vrt-api/device.rst b/docs/reference/vrt-api/device.rst new file mode 100644 index 00000000..d86dba49 --- /dev/null +++ b/docs/reference/vrt-api/device.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +vrt::Device +############## + +.. doxygenclass:: vrt::Device + :project: VRT + :members: diff --git a/docs/reference/vrt-api/enums.rst b/docs/reference/vrt-api/enums.rst new file mode 100644 index 00000000..f6261813 --- /dev/null +++ b/docs/reference/vrt-api/enums.rst @@ -0,0 +1,182 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################## +VRT Enumerations +################## + +This page documents the public enumerations and supporting types in the VRT +API. + +Platform +======== + +Defined in ``vrt/utils/platform.hpp``. + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Value + - Description + * - ``Platform::HARDWARE`` + - Physical FPGA device via PCIe. + * - ``Platform::EMULATION`` + - Software C-model via ZeroMQ IPC. + * - ``Platform::SIMULATION`` + - Cycle-accurate Verilog simulation. + * - ``Platform::UNKNOWN`` + - Unspecified or invalid platform. + +.. code-block:: cpp + + if (device.getPlatform() == vrt::Platform::EMULATION) { + // emulation-specific logic + } + +See :doc:`/explanation/platform-modes` for a full description of each mode. + +SyncType +======== + +Defined in ``vrt/buffer.hpp``. + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Value + - Description + * - ``SyncType::HOST_TO_DEVICE`` + - DMA write — transfer data from host memory to device memory (H2C). + * - ``SyncType::DEVICE_TO_HOST`` + - DMA read — transfer data from device memory to host memory (C2H). + +.. code-block:: cpp + + buf.sync(vrt::SyncType::HOST_TO_DEVICE); // write to device + kernel.start(); + kernel.wait(); + buf.sync(vrt::SyncType::DEVICE_TO_HOST); // read results back + +MemoryRangeType +=============== + +Defined in ``vrt/allocator/allocator.hpp``. + +.. list-table:: + :header-rows: 1 + :widths: 20 80 + + * - Value + - Description + * - ``MemoryRangeType::HBM`` + - High Bandwidth Memory. Requires an explicit port number (0–63) in the + ``Buffer`` constructor or a ``MemoryConfig`` with ``hbmPort`` set. + * - ``MemoryRangeType::DDR`` + - DDR system memory. Single address space, no port required. + * - ``MemoryRangeType::HBM_VNOC`` + - HBM via the Virtual Network-on-Chip. The allocator automatically + places the buffer across HBM channels — no explicit port required. + +.. code-block:: cpp + + // DDR buffer — no port needed + vrt::Buffer ddr(device, 1024, vrt::MemoryRangeType::DDR); + + // HBM buffer — explicit port required + vrt::Buffer hbm(device, 1024, vrt::MemoryRangeType::HBM, 3); + + // HBM VNOC — auto-placed, no port + vrt::Buffer vnoc(device, 1024, vrt::MemoryRangeType::HBM_VNOC); + +See :doc:`/explanation/memory-model` for details on memory types and +allocation strategies. + +HBMRegion +========= + +Defined in ``vrt/allocator/allocator.hpp``. + +Underlying type: ``uint64_t``. + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Value + - Description + * - ``HBM0`` – ``HBM63`` + - Individual HBM pseudo-channels. ``HBM0 = 0``, ``HBM1 = 1``, …, + ``HBM63 = 63``. + * - ``NON_HBM`` + - Sentinel value (``UINT64_MAX``) indicating no specific HBM region. + +Users typically do not reference ``HBMRegion`` directly. Pass a port number +to the ``Buffer`` constructor instead. + +ProgramType +=========== + +Defined in ``vrt/device.hpp``. + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Value + - Description + * - ``ProgramType::FLASH`` + - Program the device via flash memory (default). + * - ``ProgramType::JTAG`` + - Program the device via JTAG interface. + +.. code-block:: cpp + + vrt::Device device(bdf, vrtbinPath, true, vrt::ProgramType::FLASH); + +StreamDirection +=============== + +Defined in ``vrt/qdma/qdma_connection.hpp``. + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Value + - Description + * - ``StreamDirection::HOST_TO_DEVICE`` + - Streaming data flow from host to device (H2C). + * - ``StreamDirection::DEVICE_TO_HOST`` + - Streaming data flow from device to host (C2H). + +Used internally by ``QdmaConnection`` and ``StreamingBuffer``. Most users +interact with streaming via ``vrt::StreamingBuffer`` rather than +referencing ``StreamDirection`` directly. + +MemoryConfig +============ + +Defined in ``vrt/allocator/allocator.hpp``. + +A plain struct describing the memory type and optional HBM port for a +buffer. Obtain it from kernel metadata rather than constructing it manually: + +.. code-block:: cpp + + vrt::Kernel kernel(device, "my_kernel"); + vrt::MemoryConfig config = kernel.portMemoryConfig("m_axi_gmem0"); + vrt::Buffer buf(device, 1024, config); + +.. list-table:: + :header-rows: 1 + :widths: 30 70 + + * - Field + - Description + * - ``MemoryRangeType type`` + - ``DDR``, ``HBM``, or ``HBM_VNOC``. + * - ``std::optional hbmPort`` + - Set only when ``type == HBM``. Contains the HBM port number (0–63). diff --git a/docs/reference/vrt-api/index.rst b/docs/reference/vrt-api/index.rst new file mode 100644 index 00000000..db4cafdc --- /dev/null +++ b/docs/reference/vrt-api/index.rst @@ -0,0 +1,20 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############# +VRT C++ API +############# + +The V80 RunTime (VRT) is a C++17 library for deploying and executing FPGA kernels +on Alveo V80 cards. + +.. toctree:: + :maxdepth: 1 + + device + kernel + buffer + streaming-buffer + vrtbin + enums diff --git a/docs/reference/vrt-api/kernel.rst b/docs/reference/vrt-api/kernel.rst new file mode 100644 index 00000000..60e5c773 --- /dev/null +++ b/docs/reference/vrt-api/kernel.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +vrt::Kernel +############## + +.. doxygenclass:: vrt::Kernel + :project: VRT + :members: diff --git a/docs/reference/vrt-api/streaming-buffer.rst b/docs/reference/vrt-api/streaming-buffer.rst new file mode 100644 index 00000000..b2096b6f --- /dev/null +++ b/docs/reference/vrt-api/streaming-buffer.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +####################### +vrt::StreamingBuffer +####################### + +.. doxygenclass:: vrt::StreamingBuffer + :project: VRT + :members: diff --git a/docs/reference/vrt-api/vrtbin.rst b/docs/reference/vrt-api/vrtbin.rst new file mode 100644 index 00000000..82342def --- /dev/null +++ b/docs/reference/vrt-api/vrtbin.rst @@ -0,0 +1,11 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +vrt::Vrtbin +############## + +.. doxygenclass:: vrt::Vrtbin + :project: VRT + :members: diff --git a/docs/reference/vrtd/client-flow.rst b/docs/reference/vrtd/client-flow.rst new file mode 100644 index 00000000..13f1e14e --- /dev/null +++ b/docs/reference/vrtd/client-flow.rst @@ -0,0 +1,257 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############# +Client Flow +############# + +``vrtd`` (the *V80 Runtime Daemon*) multiplexes access to SLASH-managed FPGA +devices and enforces permission rules for multi-tenancy. Applications talk to +``vrtd`` over a Unix domain socket via: + +- **C API**: *libvrtd* (````) +- **C++ wrapper**: *libvrtd++* (``vrtd::Session``, ``vrtd::Device``, ``vrtd::Bar``, + ``vrtd::BarFile``) + +Pipeline +======== + +.. code-block:: text + + +-----------+ +----------+ +-----------+ +---------+ +--------+ + | libvrt | <-- | libvrtd++| <-- | libvrtd | <-- | vrtd | <-- |libslash| + +-----------+ +----------+ +-----------+ +---------+ +--------+ + AF_UNIX / SOCK_SEQPACKET + sendmsg/recvmsg (+SCM_RIGHTS) + +Roles +----- + +- **SLASH kernel module / libslash**: low-level device control. +- **vrtd**: daemon that arbitrates access and permissions (multi-tenant). +- **libvrtd (C)**: wire protocol client; exposes typed requests/responses. +- **libvrtd++ (C++)**: safer RAII/exception wrapper on top of libvrtd. + +Quick Start (C++) +================= + +Minimal program that opens a session, grabs device 0, opens BAR 0, and reads a +``uint32_t`` via RAII: + +.. code-block:: cpp + + #include + #include + #include + #include + #include + #include + + int main() { + try { + vrtd::Session s; // connects to the standard socket path + + auto n = s.getNumDevices(); + if (n == 0) { + std::cout << "No devices\n"; + return 0; + } + + vrtd::Device d = s.getDevice(0); + vrtd::Bar b = d.getBar(0); + + vrtd::BarFile bf = b.openBarFile(); + + auto p = bf.getPtr(vrtd::BarFile::Direction::Read, /*address=*/0); + std::uint32_t value = *p; // read via volatile + (void)value; + + bf.close(); + } catch (const vrtd::Error& e) { + std::cerr << "vrtd error: " << e.what() << "\n"; + return 1; + } + return 0; + } + +Quick Start (C) +=============== + +Same operation using the C API with explicit bracketing for memory access: + +.. code-block:: c + + #include + #include + #include + #include + #include + + int main() { + int fd = vrtd_connect(VRTD_STANDARD_PATH); + if (fd < 0) { perror("vrtd_connect"); return 1; } + + uint32_t num = 0; + if (vrtd_get_num_devices(fd, &num) != VRTD_RET_OK || num == 0) { + fprintf(stderr, "no devices or error\n"); close(fd); return 1; + } + + struct slash_bar_file bf = {0}; + enum vrtd_ret r = vrtd_open_bar_file(fd, /*dev=*/0, /*bar=*/0, &bf); + if (r != VRTD_RET_OK) { + fprintf(stderr, "open bar failed: %d\n", (int)r); close(fd); return 1; + } + + slash_bar_file_start_read(&bf); + volatile uint32_t *p = (volatile uint32_t*)((volatile uint8_t*)bf.map + 0); + uint32_t value = *p; + slash_bar_file_end_read(&bf); + (void)value; + + vrtd_close_bar_file(&bf); + close(fd); + return 0; + } + +End-to-End Flow +=============== + +This section walks the common path from connection to BAR memory access, +showing the C and C++ entry points side-by-side. + +1) Connect +---------- + +- **C**: ``int fd = vrtd_connect(VRTD_STANDARD_PATH);`` + Returns ``fd >= 0`` on success (caller owns and must ``close(fd)``), + or ``-1`` with ``errno`` set on failure. + +- **C++**: ``vrtd::Session s;`` or ``vrtd::Session s{"/run/vrtd.sock"};`` + Throws ``vrtd::Error(VRTD_RET_BAD_CONN)`` on failure. + RAII — destructor calls ``close()``. Thread-safe (internal mutex). + +2) Discover Devices +------------------- + +- **C**: + + - ``vrtd_get_num_devices(fd, &count)`` — returns ``VRTD_RET_OK`` on success. + - ``vrtd_get_device_info(fd, dev_index, &info)`` — fills + ``struct vrtd_device_info`` (name + PCI BDF/IDs). + - ``vrtd_get_device_by_bdf(fd, "0000:65:00.0", &dev_index)`` — lookup by BDF. + +- **C++**: + + - ``uint32_t n = s.getNumDevices();`` + - ``vrtd::Device d = s.getDevice(i);`` — throws ``vrtd::Error(VRTD_RET_NOEXIST)`` + if out of range. + - Accessors: ``d.getNum()``, ``d.getName()``, ``d.getBdf()``. + - Any ``Device`` becomes invalid if its originating ``Session`` is closed or moved. + +3) BAR Metadata +--------------- + +- **C**: ``vrtd_get_bar_info(fd, dev, bar, &info)`` fills + ``struct slash_ioctl_bar_info`` with usability flag, start address, and + length (bytes). + +- **C++**: ``vrtd::Bar b = d.getBar(bar_index);`` + Query: ``b.isUsable()``, ``b.isInUse()``, ``b.getStartAddress()``, + ``b.getLength()`` (bytes, physical). + +4) Obtain BAR FD +---------------- + +- **C**: ``vrtd_get_bar_fd(fd, dev, bar, &bar_fd, &len)`` receives ``bar_fd`` + via ``SCM_RIGHTS``. Caller owns and must ``close(bar_fd)``. + +- **C++**: Not called directly — ``Bar::openBarFile()`` handles this internally. + +5) Map the BAR +-------------- + +- **C**: ``vrtd_open_bar_file(fd, dev, bar, &bf)`` fills ``struct slash_bar_file`` + with ``bf.fd``, ``bf.map``, and ``bf.len``. Unmap with ``vrtd_close_bar_file(&bf)``. + +- **C++**: ``vrtd::BarFile bf = b.openBarFile();`` — RAII; owns FD + mapping. + ``bf.close()`` or destructor releases resources. + +6) Access BAR Memory +-------------------- + +- **C**: + + - Read: ``slash_bar_file_start_read(&bf);`` … access via ``volatile`` pointer + into ``bf.map`` … ``slash_bar_file_end_read(&bf);`` + - Write: ``slash_bar_file_start_write(&bf);`` … access … + ``slash_bar_file_end_write(&bf);`` + - Use ``(volatile uint8_t*)bf.map + offset`` to compute addresses. + +- **C++**: + + - ``auto p = bf.getPtr(vrtd::BarFile::Direction::Read, offset);`` + Returns a move-only ``vrtd::BarFilePtr`` that brackets the operation and + ends it on destruction. + - Only one operation (read or write) may be active at a time per ``BarFile``. + - Raw pointer: ``bf.getRawPtr(offset)`` — caller must manually bracket with + ``slash_bar_file_start_*`` / ``_end_*``. + +Error Model +=========== + +- **C** functions return ``vrtd_ret``. Check for ``VRTD_RET_OK`` before using + outputs. +- **C++** methods throw ``vrtd::Error``; transport failures map to + ``VRTD_RET_BAD_CONN``. ``vrtd::Error::what()`` returns a static, + human-readable string. +- Local misuse in ``BarFile`` / ``BarFilePtr`` throws ``std::runtime_error``. + +Common return codes: + +- ``VRTD_RET_OK`` — success. +- ``VRTD_RET_BAD_LIB_CALL`` — bad library usage (e.g. null out-pointer). +- ``VRTD_RET_BAD_CONN`` — broken transport (socket errors, daemon not running). +- ``VRTD_RET_BAD_REQUEST`` — malformed request. +- ``VRTD_RET_INVALID_ARGUMENT`` — invalid argument. +- ``VRTD_RET_NOEXIST`` — resource does not exist (e.g. out-of-range index). +- ``VRTD_RET_INTERNAL_ERROR`` — daemon-side failure; check vrtd logs. +- ``VRTD_RET_AUTH_ERROR`` — permission denied by role configuration. + +Thread Safety +============= + +- **Session / Device / Bar (C++)**: public methods are thread-safe (internal + mutex). Object validity is tied to the originating session — closing or + moving a session invalidates previously obtained ``Device`` / ``Bar`` values. +- **BarFile / BarFilePtr (C++)**: not thread-safe. Only one read or write + operation may be active at a time. Re-entrant ``getPtr()`` calls throw. + +Lifetime and Moves (C++) +========================= + +- Moving or closing a ``Session`` invalidates all ``Device`` and ``Bar`` objects + obtained from it (subsequent calls throw). +- ``BarFile`` is move-only. Ensure all ``BarFilePtr`` instances have been + destroyed before calling ``bf.close()`` or letting the destructor run, + otherwise an exception is thrown. + +Wire Protocol +============= + +- Transport: ``AF_UNIX`` + ``SOCK_SEQPACKET``. +- Messages: request/response headers (size, opcode, seqno) + body. +- FD passing: responses may carry a file descriptor via ``SCM_RIGHTS`` + (e.g. for BAR file access). +- Size limits: request body must not exceed ``VRTD_MSG_MAX_SIZE`` minus headers. +- Generic escape hatch: ``vrtd_raw_request`` sends arbitrary opcodes; prefer + typed helpers for normal use. + +Troubleshooting +=============== + +- **Out-of-range device index** → ``VRTD_RET_NOEXIST`` (C) or ``vrtd::Error`` (C++). +- **Session closed/moved, then using Device/Bar** → throws (invalid lifetime). +- **Two concurrent ``getPtr()`` calls on the same BarFile** → throws re-entrancy error. +- **Transport errors** (socket down, daemon not running) → map to + ``VRTD_RET_BAD_CONN`` / ``vrtd::Error`` with "connection" message. diff --git a/docs/reference/vrtd/configuration.rst b/docs/reference/vrtd/configuration.rst new file mode 100644 index 00000000..3dcdaa80 --- /dev/null +++ b/docs/reference/vrtd/configuration.rst @@ -0,0 +1,128 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################ +Configuration +################ + +The ``vrtd`` daemon reads its configuration from ``vrtd.conf`` at startup. +The file uses an INI-style format with sections for roles, users, and groups. + +File Location +============= + +The default configuration file is installed alongside the ``vrtd`` binary. +Additional configuration fragments can be included via the ``include-glob`` +directive at the top of the file: + +.. code-block:: ini + + include-glob = vrtd.conf.d/*.conf + +This loads all ``.conf`` files in the ``vrtd.conf.d/`` directory, allowing +drop-in configuration without editing the main file. + +Roles +===== + +A role defines a set of permissions. Roles are declared with +``[role:]`` sections for global permissions and +``[role::]`` sub-sections for per-device permissions. + +The ```` specifier can be a BDF address or the ``any`` wildcard to +match all devices. + +Built-in Roles +-------------- + +The default configuration defines two roles: + +**fullaccess** — grants all permissions on all devices: + +.. code-block:: ini + + [role:fullaccess] + query-devices = yes + + [role:fullaccess:any] + bar-access = full + qdma = yes + buffer = yes + design-write = yes + clock = yes + pcie-hotplug = yes + +**info** — can enumerate and query devices but not access them: + +.. code-block:: ini + + [role:info] + query-devices = yes + +Permission Keys +--------------- + +The following permission keys are available in per-device sub-sections: + +.. list-table:: + :header-rows: 1 + :widths: 25 50 + + * - Key + - Description + * - ``query-devices`` + - Enumerate devices and read device info (global, not per-device). + * - ``bar-access`` + - BAR MMIO access level. Values: ``full``, or omit to deny. + * - ``qdma`` + - Allow QDMA (DMA transfer) operations. + * - ``buffer`` + - Allow device buffer allocation. + * - ``design-write`` + - Allow programming (loading vrtbin onto device). + * - ``clock`` + - Allow clock frequency configuration. + * - ``pcie-hotplug`` + - Allow PCIe hotplug operations (reset, remove, rescan). + +User and Group Mappings +======================= + +Users and groups are assigned roles with ``[user:]`` and +``[group:]`` sections. The wildcard ``*`` matches any user or group. + +Default mappings: + +.. code-block:: ini + + [user:root] + role = fullaccess + + [group:vrtadmin] + role = fullaccess + + [user:*] + role = info + +This gives ``root`` and members of the ``vrtadmin`` group full access, while +all other users get read-only device enumeration. + +Custom Roles +============ + +You can define custom roles to grant fine-grained access. For example, to allow +a role that can run kernels but not reprogram the FPGA: + +.. code-block:: ini + + [role:runner] + query-devices = yes + + [role:runner:any] + bar-access = full + qdma = yes + buffer = yes + + [group:fpga-users] + role = runner diff --git a/docs/reference/vrtd/index.rst b/docs/reference/vrtd/index.rst new file mode 100644 index 00000000..e52bd7dc --- /dev/null +++ b/docs/reference/vrtd/index.rst @@ -0,0 +1,16 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############## +vrtd Daemon +############## + +The V80 Runtime Daemon (vrtd) provides low-level device access via a UNIX domain +socket. It runs as a systemd service and mediates access to V80 hardware. + +.. toctree:: + :maxdepth: 1 + + client-flow + configuration diff --git a/docs/requirements.txt b/docs/requirements.txt index a9fa3567..783580b7 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,3 +1,4 @@ breathe sphinxcontrib-tikz sphinx-rtd-theme +sphinx-design diff --git a/docs/runtime.rst b/docs/runtime.rst deleted file mode 100644 index 5849ceab..00000000 --- a/docs/runtime.rst +++ /dev/null @@ -1,16 +0,0 @@ -.. - comment:: SPDX-License-Identifier: MIT - comment:: Copyright (C) 2025 Advanced Micro Devices, Inc - -################################################### -SLASH V80 Run-Time (VRT) -################################################### - -********************************** -vrt::Device -********************************** - -.. doxygenclass:: vrt::Device - :project: VRT - :members: - diff --git a/docs/tutorials/admin/bootstrap-aved.rst b/docs/tutorials/admin/bootstrap-aved.rst new file mode 100644 index 00000000..1e49cc48 --- /dev/null +++ b/docs/tutorials/admin/bootstrap-aved.rst @@ -0,0 +1,170 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +######################### +Bootstrapping with AVED +######################### + +This tutorial walks an administrator through the one-time JTAG step +required to install **AVED** (the Alveo Versal Example Design) on an +AMD Alveo V80 board. AVED provides the AMC firmware and the PCIe +management function (PF0, device ID ``0x50B4``) that the SLASH stack +binds to via the ``ami`` kernel driver. + +When you need this tutorial +=========================== + +The rest of the SLASH platform-setup flow — including +``ami_tool cfgmem_program`` for writing the SLASH static shell — +requires that ``ami`` is already bound to PF0. That, in turn, requires +a valid AVED image in the V80's OSPI flash. Follow this tutorial when: + +- the V80 is **brand new** and has never had AVED programmed, or +- the V80's OSPI flash has been corrupted or wiped and PF0 no longer + enumerates over PCIe, or ami repports errors (such as ``NO_AMC```) + +Boards that already enumerate PF0 (visible as ``10ee:50b4`` in +``lspci``) can skip this tutorial and go directly to +:doc:`platform-setup`. + +Prerequisites +============= + +**Hardware:** + +- AMD Alveo V80 installed in a PCIe slot. +- USB cable from the host to the V80's onboard USB-JTAG. + +**Software:** + +- AMD Vivado 2025.1. + +Download the AVED Deployment Archive +===================================== + +AVED is published by AMD as a prebuilt deployment archive. Download +the archive for the V80 from the AVED documentation portal: + +- AVED documentation: https://xilinx.github.io/AVED/ +- V80 member-portal page: https://www.xilinx.com/member/v80.html + +Extract the archive on the host. The relevant files for this tutorial +are located under ``flash_setup/``: + +.. list-table:: + :header-rows: 1 + :widths: 40 60 + + * - File + - Purpose + * - ``flash_setup/versal_change_boot_mode.tcl`` + - XSDB script that switches the Versal device to JTAG boot mode. + * - ``flash_setup/v80_initialization.pdi`` + - Initialization PDI loaded over JTAG before flashing OSPI. + * - ``flash_setup/fpt_setup__.pdi`` + - Flash Partition Table setup PDI written to OSPI. + +Switch the V80 to JTAG Boot Mode +================================ + +By default the V80 boots from OSPI. To program a fresh board over +JTAG, the Versal device must first be switched to JTAG boot mode. +Source the Vivado settings, then launch ``xsdb`` and source the +``versal_change_boot_mode.tcl`` script shipped with the archive: + +.. code-block:: bash + + source /settings64.sh + xsdb + +At the ``xsdb%`` prompt: + +.. code-block:: tcl + + connect + targets -set -filter {name =~ "Versal*"} + source flash_setup/versal_change_boot_mode.tcl + +The script reconfigures the boot-mode register on the Versal device +so that subsequent JTAG operations from Hardware Manager will be +accepted. + +See `AVED JTAG Boot Recovery +`_ +for the upstream reference. + +Program OSPI Flash via Vivado Hardware Manager +============================================== + +With the V80 in JTAG boot mode, launch Vivado Hardware Manager and +program the OSPI flash: + +1. Launch Vivado and open Hardware Manager + (*Flow* → *Open Hardware Manager*). +2. *Open Target* → *Auto Connect*. The V80 should appear as + ``xcv80_1``. +3. Right-click ``xcv80_1`` → *Add Configuration Memory Device*. +4. Select the ``cfgmem-2048-ospi-x8-single`` part.` +5. Program the configuration memory using + ``flash_setup/fpt_setup__.pdi`` together with + ``flash_setup/v80_initialization.pdi``. For the address range + select **Entire Configuration Memory Device**. +6. Wait for Hardware Manager to report **Flash Programming + Completed Successfully**. + +For the upstream step-by-step reference, see `AVED Updating FPT Image +in Flash `_ +and `AVED Device Programming +`_. + +Cold-Reboot the Host +==================== + +A full power cycle is required after flashing — a soft ``reboot`` +will not re-read the Versal boot-mode pins. Shut the host down +completely, then power it back on: + +.. code-block:: bash + + sudo shutdown -h now + +After the host powers back on, the V80 boots from OSPI and AVED +becomes active. + +Verify +====== + +Confirm that PF0 enumerates on the PCIe bus: + +.. code-block:: bash + + lspci -d 10ee:50b4 + +You should see one entry per V80 board. If the ``ami`` driver is +already installed on this host, ``ami_tool`` will also report the +card: + +.. code-block:: bash + + sudo ami_tool overview + +The reported ``logic_uuid`` should match the UUID listed in the +AVED archive's ``version.json``. + +.. note:: + + If you are following the package build flow on a fresh board, you + will not have the ``ami`` driver or ``ami_tool`` installed yet. That + is expected at this stage — confirming that the board enumerates on + PCIe via ``lspci`` is sufficient. Continue on to :doc:`platform-setup` + to install the SLASH stack, which brings in ``ami`` and ``ami_tool``. + +Next Steps +========== + +With AVED bootstrapped and PF0 visible, continue with the regular +platform-setup flow: + +- :doc:`platform-setup` — install the SLASH stack and program the + SLASH static shell over PCIe with ``ami_tool cfgmem_program``. diff --git a/docs/tutorials/admin/device-management.rst b/docs/tutorials/admin/device-management.rst new file mode 100644 index 00000000..6e40dbda --- /dev/null +++ b/docs/tutorials/admin/device-management.rst @@ -0,0 +1,155 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################### +Device Management +################### + +This tutorial covers day-to-day V80 board management using ``v80-smi``. +For the full command syntax, see :doc:`/reference/smi/commands`. + +Prerequisites +============= + +- SLASH platform is set up (kernel module loaded, vrtd running). + See :doc:`platform-setup` if starting from scratch. +- ``v80-smi`` is installed and on ``PATH``. + +Listing Devices +=============== + +Enumerate all V80 boards on the system: + +.. code-block:: bash + + v80-smi list + +The output shows each board's BDF address and readiness status. A board is +ready when all four checks pass: + +- **PF0** (``ami``) — management interface driver loaded. +- **PF1** (``slash_qdma``) — QDMA driver loaded. +- **PF2** (``slash_ctl``) — control driver loaded. +- **VRTD** — daemon is running and the device is registered. + +For detailed information including PCI IDs and driver names: + +.. code-block:: bash + + v80-smi list -l + +For machine-readable output: + +.. code-block:: bash + + v80-smi list -j # compact JSON + v80-smi list -J # pretty-printed JSON + +To include sensor readings (temperature, power): + +.. code-block:: bash + + v80-smi list -s + +Inspecting a Vrtbin +=================== + +Before programming a device, inspect a vrtbin file to verify its contents: + +.. code-block:: bash + + v80-smi inspect my_design.vbin + +This displays the platform (Hardware/Emulation/Simulation), clock +frequency, kernel names, argument lists, and memory port connections — +all parsed from the ``system_map.xml`` inside the archive. + +See :doc:`/explanation/vrtbin-format` for details on the archive structure. + +Programming a Device +==================== + +Load a vrtbin onto a board: + +.. code-block:: bash + + v80-smi program my_design.vbin -d 03:00 + +This extracts the PDI bitstream from the vrtbin and programs the FPGA. +The device BDF (``03:00``) can be found from ``v80-smi list``. + +Programming can also be done using VRT: + +.. code-block:: cpp + + vrt::Device device("03:00", "my_design.vbin"); // programs automatically + +Querying the Active Design +========================== + +To see what was last programmed on a device: + +.. code-block:: bash + + v80-smi query -d 03:00 + +This shows the same metadata as ``inspect`` but reads it from the device +rather than from a file on disk. + +.. warning:: + + ``query`` only reports what **you** (the current user) last wrote to the + board at the given BDF — not what is physically loaded on the device right + now. Querying the actual on-board design is not currently possible. Treat + the output as a guide, not absolute truth. + +Resetting a Device +================== + +Perform a hardware reset (PCIe secondary bus reset and rescan): + +.. code-block:: bash + + v80-smi reset -d 03:00 + +Use this when: + +- A kernel is stuck and not responding to ``AP_DONE`` polling. +- You need to clear the device state before reprogramming. +- Debugging hardware issues. + +After a reset, the board returns to an unprogrammed state and must be +reprogrammed before use. + +Validating Memory +================= + +Run memory integrity and bandwidth tests: + +.. code-block:: bash + + v80-smi validate -d 03:00 + +This tests both HBM and DDR subsystems: + +- **Integrity** — fills each memory region with a deterministic pattern + (``i ^ seed``), reads it back, and compares. +- **Bandwidth** — measures host-to-device (H2C) and device-to-host (C2H) + throughput. + +Control the number of parallel test threads: + +.. code-block:: bash + + v80-smi validate -d 03:00 -j 16 # 16 threads (default: 8, max: 64) + +A passing result confirms the hardware, drivers, and memory subsystems are +functioning correctly. + +Next Steps +========== + +- :doc:`/reference/smi/commands` — full ``v80-smi`` command reference. +- :doc:`vrtd-configuration` — customise daemon permissions and roles. +- :doc:`/tutorials/user/getting-started` — run your first user application. diff --git a/docs/tutorials/admin/platform-setup.rst b/docs/tutorials/admin/platform-setup.rst new file mode 100644 index 00000000..61e9a88f --- /dev/null +++ b/docs/tutorials/admin/platform-setup.rst @@ -0,0 +1,475 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############### +Platform Setup +############### + +This tutorial walks a system administrator through installing the SLASH +stack on a machine with an AMD Alveo V80 board — from package installation +to a validated, running system. + +The recommended installation method is via pre-built packages (Debian or +RPM). If you need to build from source instead, see +:doc:`/howto/build-from-source`. + +Prerequisites +============= + +**Hardware:** + +- AMD Alveo V80 board installed in a PCIe x8 (or wider) slot. + +**Software:** + +- Linux (Ubuntu LTS 22.04+, RHEL 9+ or compatible recommended). + +Target-machine prerequisites +---------------------------- + +Every machine that will run the SLASH packages needs kernel headers +installed so that DKMS can compile the kernel module: + +.. tab-set:: + + .. tab-item:: Ubuntu + + .. code-block:: bash + + sudo apt install linux-headers-$(uname -r) + + .. tab-item:: RHEL / Rocky Linux / AlmaLinux + + .. code-block:: bash + + sudo dnf install kernel-devel-$(uname -r) + +Other install-time dependencies (``dkms``, ``gcc``, libraries, etc.) are +declared by the packages themselves and will be pulled from the system +repositories automatically. + +Build-machine prerequisites +--------------------------- + +The machine used to run the packaging scripts needs a C/C++ toolchain, +library development headers, and the packaging tools. These are only +required on the build machine, not on every target: + +.. tab-set:: + + .. tab-item:: Ubuntu + + .. code-block:: bash + + sudo apt install \ + build-essential cmake ninja-build pkg-config rsync \ + debhelper dpkg-dev apt-utils \ + python3 python3-pip \ + libcli11-dev libinih-dev libjsoncpp-dev \ + libsystemd-dev libxml2-dev libzmq3-dev zlib1g-dev + + .. tab-item:: RHEL 9 / Rocky Linux 9 / AlmaLinux 9 + + .. code-block:: bash + + sudo dnf install \ + gcc gcc-c++ cmake make ninja-build pkg-config rsync \ + rpm-build createrepo_c systemd-rpm-macros \ + python3.11 python3.11-pip \ + cli11-devel cppzmq-devel inih-devel jsoncpp-devel \ + libxml2-devel systemd-devel \ + zeromq-devel zlib-devel + + .. tab-item:: RHEL 10 / Rocky Linux 10 / AlmaLinux 10 + + .. code-block:: bash + + sudo dnf install \ + gcc gcc-c++ cmake make ninja-build pkg-config rsync \ + rpm-build createrepo_c systemd-rpm-macros \ + python3 python3-pip \ + cli11-devel cppzmq-devel inih-devel jsoncpp-devel \ + libxml2-devel systemd-devel \ + zeromq-devel zlib-devel + +.. note:: + + **How package dependencies work.** Each SLASH package declares its + dependencies — both on system packages (e.g. ``slash-dkms`` depends on + ``dkms``, ``gcc``, ``make``) and on other SLASH packages (e.g. ``vrtd`` + depends on ``libslash``). System-repository dependencies are resolved + automatically by ``apt`` / ``dnf``. + + However, ``apt`` and ``dnf`` cannot resolve dependencies between local + ``.deb`` / ``.rpm`` files unless they are hosted in a repository. When + installing from the command line, you must pass **all** required SLASH + packages in a single command so the package manager can satisfy them + together. The packaging scripts generate repository metadata + (``Packages`` / ``repodata/``) so that hosting the output directory as a + repository avoids this limitation. + +Static Shell +============ + +The *static shell* is the pre-built FPGA platform base that ships inside +the ``slashkit`` package. It contains the fixed platform infrastructure — +including the SMBus controller IP used for board management — that every +hardware vrtbin is linked against. + +Building it requires **Vivado 2025.1** and **Vitis 2025.1**, plus a +**Vivado Enterprise license** (the SMBus IP is not available under the +standard tier). Source both tools before running the package build: + +.. code-block:: bash + + source /settings64.sh + source /settings64.sh + +For ``csh``/``tcsh`` users: + +.. code-block:: csh + + source /settings64.csh + source /settings64.csh + +.. note:: + + Vivado Enterprise license configuration is site-specific. Contact your + license administrator if you are unsure how licenses are served at your + site. + +The SMBus IP (``xilinx.com:ip:smbus:1.1``) used for board management is +**not included** in this repository and is not bundled with Vivado. It must +be downloaded separately from the AMD member portal and placed into the +local IP repository before building: + +1. Download the SMBus IP from https://www.xilinx.com/member/v80.html + (AMD account required). +2. Copy the downloaded IP directory into ``linker/slashkit/resources/base/iprepo/`` + so that Vivado can locate it during synthesis. + +See the `AVED rebuild guide `_ for +additional details. + +Build the Packages +================== + +All packages — including the AMI driver package — are produced by a single +script run from the repository root. The static shell is built +automatically as part of this step. **Expect the build to take several +hours** while Vivado synthesises and implements the platform design. + +.. tab-set:: + + .. tab-item:: Ubuntu + + .. code-block:: bash + + ./scripts/package-deb.sh + + Packages are written to ``./deb/``. + + .. tab-item:: RHEL / Rocky Linux / AlmaLinux + + .. code-block:: bash + + ./scripts/package-rpm.sh + + Packages are written to ``./rpm/``. + +Both scripts call ``scripts/package-ami.sh`` internally, so the AMI package +is built and placed in the same output directory automatically. + +Install the AMI Driver +====================== + +The V80 board's PF0 function (device ID ``0x50B4``) is managed by the +**AMI** (AVED Management Interface) kernel module. AMI should be installed +along with the rest of the SLASH stack. + +.. tab-set:: + + .. tab-item:: Ubuntu + + .. code-block:: bash + + sudo apt install ./deb/ami__amd64.deb + + .. tab-item:: RHEL / Rocky Linux / AlmaLinux + + .. code-block:: bash + + sudo dnf install ./rpm/ami--1..x86_64.rpm + +.. warning:: + + If AMI is already installed on this system — for example, built from + source or installed from a separate vendor package — the generated AMI + package may conflict with the existing installation. Either remove the + existing AMI installation before proceeding, or skip this step and + ensure your installed AMI version is compatible with this SLASH release. + +Verify that the ``ami`` driver is bound to PF0 after installation: + +.. code-block:: bash + + lspci -d 10ee:50b4 -k + +The output should show ``Kernel driver in use: ami``. + +Install SLASH Packages +====================== + +Install the full runtime stack in one command by listing all packages: + +.. tab-set:: + + .. tab-item:: Ubuntu (.deb) + + .. code-block:: bash + + sudo apt install \ + ./deb/slash-dkms__all.deb \ + ./deb/libslash__amd64.deb \ + ./deb/vrtd__amd64.deb \ + ./deb/libvrtd__amd64.deb \ + ./deb/libvrt__amd64.deb \ + ./deb/v80-smi__amd64.deb \ + ./deb/slashkit__amd64.deb + + .. tab-item:: RHEL / Rocky Linux / AlmaLinux (.rpm) + + .. code-block:: bash + + sudo dnf install \ + ./rpm/slash-dkms--1..noarch.rpm \ + ./rpm/libslash--1..x86_64.rpm \ + ./rpm/vrtd--1..x86_64.rpm \ + ./rpm/libvrtd--1..x86_64.rpm \ + ./rpm/libvrt--1..x86_64.rpm \ + ./rpm/v80-smi--1..x86_64.rpm \ + ./rpm/slashkit--1..x86_64.rpm + +.. note:: + + If you also need to write or compile kernels (HLS development), + install the development packages as well: + + .. tab-set:: + + .. tab-item:: Ubuntu + + .. code-block:: bash + + sudo apt install \ + ./deb/libslash-dev__amd64.deb \ + ./deb/libvrtd-dev__amd64.deb \ + ./deb/libvrt-dev__amd64.deb + + .. tab-item:: RHEL / Rocky Linux / AlmaLinux + + .. code-block:: bash + + sudo dnf install \ + ./rpm/libslash-devel--1..x86_64.rpm \ + ./rpm/libvrtd-devel--1..x86_64.rpm \ + ./rpm/libvrt-devel--1..x86_64.rpm + + This installs ``slashkit`` (the kernel linker) and development headers. + +Package Overview +---------------- + +The following table summarises what each package provides: + +.. list-table:: + :header-rows: 1 + :widths: 25 75 + + * - Package + - Contents + * - ``slash-dkms`` + - Kernel module source + DKMS configuration. Compiles and installs + ``slash.ko`` for the running kernel automatically. + * - ``libslash`` + - Shared library for interacting with the kernel module. + * - ``libslash-dev`` + - Development headers and CMake modules for ``libslash``. + * - ``vrtd`` + - The ``vrtd`` daemon, systemd units, udev rules, and default + configuration. Multiplexes device access and enforces permissions. + * - ``libvrtd`` + - Wire-protocol client libraries (``libvrtd``, ``libvrtdpp``) for + communicating with the daemon. + * - ``libvrtd-dev`` + - Development headers and CMake modules for ``libvrtd``. + * - ``libvrt`` + - The VRT C++ runtime library (``libvrt``). + * - ``libvrt-dev`` + - Development headers and CMake modules for ``libvrt``. + * - ``v80-smi`` + - Board management CLI tool. + * - ``slashkit`` + - Python-based kernel linker for producing ``.vbin`` artefacts. + * - ``slash`` + - Metapackage: pulls in all runtime packages. + * - ``slash-dev`` + - Metapackage: pulls in all development headers and CMake modules. + * - ``slash-sim-emu`` + - Metapackage: pulls in runtime packages for simulation and emulation + (no kernel module or daemon). + * - ``slash-sim-emu-dev`` + - Metapackage: pulls in development packages for simulation and + emulation. + +Program the Board +================= + +.. note:: + + This step assumes the AMI driver is already bound to PF0 + (``10ee:50b4``). If your V80 has never been programmed with AVED — for + example, a brand-new board — first complete :doc:`bootstrap-aved` to + install AVED via JTAG. + +After installing the packages, the board's flash memory must be programmed +with the static shell before the system can be used. This step is required: + +- on the **first install** of SLASH, and +- when **upgrading** to a version that changes the static shell (noted in + the release notes). + +It is **not** required after crashes, daemon restarts, or other normal +operations — SLASH reads from flash but never writes to it during regular use. + +Program the primary flash partition (replace ```` with the bus address +from ``lspci -d 10ee:``, e.g. ``03:00``): + +.. tab-set:: + + .. tab-item:: Ubuntu + + .. code-block:: bash + + sudo ami_tool cfgmem_program -d -t primary -p 0 \ + -i /usr/lib/python3.10/dist-packages/slashkit/resources/static_shell/amd_v80_gen5x8_25.1.pdi + + .. tab-item:: RHEL 9 / Rocky Linux 9 / AlmaLinux 9 + + .. code-block:: bash + + sudo ami_tool cfgmem_program -d -t primary -p 0 \ + -i /usr/lib/python3.9/site-packages/slashkit/resources/static_shell/amd_v80_gen5x8_25.1.pdi + + .. tab-item:: RHEL 10 / Rocky Linux 10 / AlmaLinux 10 + + .. code-block:: bash + + sudo ami_tool cfgmem_program -d -t primary -p 0 \ + -i /usr/lib/python3.12/site-packages/slashkit/resources/static_shell/amd_v80_gen5x8_25.1.pdi + +After programming completes, reboot the system for the new flash contents +to take effect: + +.. code-block:: bash + + sudo reboot + +Verify the Kernel Module +======================== + +DKMS compiles and loads ``slash.ko`` automatically on package install. +To confirm the module is loaded: + +.. code-block:: bash + + lsmod | grep slash + dmesg | grep slash + +You should see one line in ``lsmod`` and, in ``dmesg``, messages for each +V80 PCI function discovered. + +Each V80 board exposes three PCI functions: + +.. list-table:: + :header-rows: 1 + :widths: 15 20 25 40 + + * - Function + - Device ID + - Driver + - Purpose + * - PF0 + - ``0x50B4`` + - ``ami`` + - AVED management interface + * - PF1 + - ``0x50B5`` + - ``slash_qdma`` + - Queue-based DMA subsystem + * - PF2 + - ``0x50B6`` + - ``slash_ctl`` + - BAR MMIO access (register reads/writes) + +Check that all three appear with their drivers bound: + +.. code-block:: bash + + lspci -d 10ee: -k + +Start the vrtd Daemon +===================== + +The ``vrtd`` package installs a systemd service and socket. Enable it so +that it starts on boot and is running now: + +.. code-block:: bash + + sudo systemctl enable --now vrtd + +Verify the daemon is reachable: + +.. code-block:: bash + + v80-smi list + +Each board should show all four readiness checks passing (PF0, PF1, PF2, +VRTD). + +Validate the Board +================== + +Run the built-in memory integrity and bandwidth test: + +.. code-block:: bash + + v80-smi validate -d + +Replace ```` with the bus address shown by ``v80-smi list`` +(e.g. ``03:00``). This tests both HBM and DDR subsystems. A passing result +confirms the hardware, drivers, and daemon are all working correctly. + +User Access +=========== + +By default, only ``root`` and members of the ``vrtadmin`` group have full +device access. To grant a user access: + +.. code-block:: bash + + sudo usermod -aG vrtadmin + +The user must log out and back in for the group change to take effect. + +For fine-grained permission control (per-device, per-operation), edit +``/etc/vrt/vrtd.conf``. See :doc:`/reference/vrtd/configuration` for the +full configuration reference. + +Next Steps +========== + +- :doc:`device-management` — list, program, reset, and validate devices. +- :doc:`vrtd-configuration` — customise daemon permissions and roles. +- :doc:`/tutorials/user/getting-started` — run your first application. diff --git a/docs/tutorials/admin/vrtd-configuration.rst b/docs/tutorials/admin/vrtd-configuration.rst new file mode 100644 index 00000000..4d963286 --- /dev/null +++ b/docs/tutorials/admin/vrtd-configuration.rst @@ -0,0 +1,301 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +###################### +vrtd Configuration +###################### + +This tutorial walks through configuring the ``vrtd`` daemon — the V80 Runtime +Daemon that multiplexes access to FPGA devices and enforces role-based +permissions. By the end you will know how to manage roles, assign users, and +integrate with systemd. + +Prerequisites +============= + +- The SLASH platform is set up (kernel module, libraries, ``vrtd`` installed). + See :doc:`platform-setup`. +- Root or ``sudo`` access for editing configuration and restarting the daemon. + +How vrtd Manages Access +======================== + +All VRT operations — programming a device, allocating buffers, launching +kernels — go through ``vrtd`` via a Unix domain socket at +``/run/vrtd.sock``. The daemon authenticates the connecting user and checks +their role before allowing each operation. + +This makes multi-tenant deployments possible: several users or applications can +share the same FPGA boards, each with different privilege levels. + +Configuration File +=================== + +``vrtd`` reads its configuration at startup from ``vrtd.conf``, located +alongside the ``vrtd`` binary (typically ``/etc/vrt/vrtd.conf``). The file +uses an INI-style format. + +The first line enables drop-in fragments: + +.. code-block:: ini + + include-glob = vrtd.conf.d/*.conf + +Any ``.conf`` file placed in the ``vrtd.conf.d/`` directory is loaded +automatically. This lets you add custom roles and user mappings without +editing the main configuration. + +Understanding Roles +==================== + +A **role** defines a set of permissions. The default configuration ships with +two roles. + +fullaccess +---------- + +Grants all permissions on all devices: + +.. code-block:: ini + + [role:fullaccess] + query-devices = yes + + [role:fullaccess:any] + bar-access = full + qdma = yes + buffer = yes + design-write = yes + clock = yes + pcie-hotplug = yes + +info +---- + +Can enumerate and query devices but not access them: + +.. code-block:: ini + + [role:info] + query-devices = yes + +Permission Keys +--------------- + +.. list-table:: + :header-rows: 1 + :widths: 25 50 + + * - Key + - Description + * - ``query-devices`` + - Enumerate devices and read device info. Set in the ``[role:]`` + section (global, not per-device). + * - ``bar-access`` + - BAR MMIO access level. Values: ``full`` or omit to deny. + * - ``qdma`` + - Allow QDMA (DMA transfer) operations. + * - ``buffer`` + - Allow device buffer allocation. + * - ``design-write`` + - Allow programming (loading a vrtbin onto a device). + * - ``clock`` + - Allow clock frequency changes. + * - ``pcie-hotplug`` + - Allow PCIe hotplug operations (reset, remove, rescan). + +Per-device permissions go in ``[role::]`` sub-sections, where +```` is a BDF address or the ``any`` wildcard. + +User and Group Mappings +======================== + +Users and groups are assigned roles with ``[user:]`` and +``[group:]`` sections. The default mappings are: + +.. code-block:: ini + + [user:root] + role = fullaccess + + [group:vrtadmin] + role = fullaccess + + [user:*] + role = info + +This gives ``root`` and members of the ``vrtadmin`` group full access, while +all other users receive read-only enumeration. + +To grant a user full access, add them to the ``vrtadmin`` group: + +.. code-block:: bash + + sudo usermod -aG vrtadmin + +The user must log out and back in for the new group membership to take effect. + +Creating a Custom Role +======================== + +Suppose you want a **runner** role that can execute kernels but cannot +reprogram the FPGA or change the clock. Create a drop-in file +``vrtd.conf.d/runner.conf``: + +.. code-block:: ini + + [role:runner] + query-devices = yes + + [role:runner:any] + bar-access = full + qdma = yes + buffer = yes + + [group:fpga-users] + role = runner + +Members of the ``fpga-users`` group can now allocate buffers and run kernels, +but ``design-write``, ``clock``, and ``pcie-hotplug`` are denied. + +Per-Device Permissions +======================== + +You can restrict a user to a specific board by using a BDF instead of ``any``: + +.. code-block:: ini + + [role:lab-board1] + query-devices = yes + + [role:lab-board1:03:00] + bar-access = full + qdma = yes + buffer = yes + design-write = yes + clock = yes + + [user:labuser] + role = lab-board1 + +The user ``labuser`` can only access device ``03:00``. Operations targeting any +other board will be denied. + +Systemd Integration +==================== + +``vrtd`` is managed by two systemd units: a socket unit that creates the +listening socket and a service unit that runs the daemon. + +Socket Unit +----------- + +The socket unit (``vrtd.socket``) creates the Unix socket before ``vrtd`` +starts: + +.. code-block:: ini + + [Socket] + ListenSequentialPacket=/run/vrtd.sock + FileDescriptorName=api + SocketMode=0666 + SocketGroup=vrt + RemoveOnStop=yes + +``SocketMode=0666`` allows any local user to connect. Access control is then +enforced by ``vrtd``'s role system after authentication. + +Service Unit +------------ + +The service unit (``vrtd.service``) runs the daemon under a dedicated +``vrtd`` user with security hardening: + +.. code-block:: ini + + [Service] + Type=notify + ExecStart=/usr/lib/vrt/vrtd + User=vrtd + Group=vrtd + WatchdogSec=60s + Restart=on-failure + RestartSec=2s + + # Hardening + NoNewPrivileges=true + ProtectSystem=full + ProtectHome=true + PrivateTmp=true + +The daemon uses ``sd_notify`` to signal readiness and integrates with the +systemd watchdog for automatic restart on failure. + +Enabling the Service +--------------------- + +.. code-block:: bash + + sudo systemctl enable --now vrtd.socket + sudo systemctl enable --now vrtd + +Verify that the daemon is running and boards are visible: + +.. code-block:: bash + + v80-smi list + +Reloading Configuration +------------------------- + +Configuration is read at startup. After editing ``vrtd.conf`` or adding +drop-in files, restart the daemon: + +.. code-block:: bash + + sudo systemctl restart vrtd + +Multi-Tenancy +============== + +With roles and per-device permissions in place, ``vrtd`` enables multiple users +and applications to share FPGA devices safely: + +- Roles control which operations each user can perform. +- Per-device permissions allow partitioning boards across teams. +- The ``vrtadmin`` group provides a convenient way to grant full access to + administrators without editing configuration files. + +Troubleshooting +================ + +Check daemon status: + +.. code-block:: bash + + systemctl status vrtd + +View logs: + +.. code-block:: bash + + journalctl -u vrtd + +Common issues: + +- **VRTD_RET_AUTH_ERROR** in application output — the user's role lacks a + required permission. Check their role assignment and group membership. +- **vrtd not running** — ensure ``vrtd.socket`` is enabled and start ``vrtd`` + manually with ``sudo systemctl start vrtd``. +- **Group membership not taking effect** — the user must log out and back in + after being added to a group. Verify with ``groups ``. + +Next Steps +========== + +- :doc:`/reference/vrtd/configuration` — full configuration reference. +- :doc:`/reference/vrtd/client-flow` — how applications communicate with + ``vrtd``. +- :doc:`platform-setup` — initial platform installation. +- :doc:`device-management` — day-to-day device management. diff --git a/docs/tutorials/user/buffers-and-memory.rst b/docs/tutorials/user/buffers-and-memory.rst new file mode 100644 index 00000000..11e9af68 --- /dev/null +++ b/docs/tutorials/user/buffers-and-memory.rst @@ -0,0 +1,209 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +#################### +Buffers and Memory +#################### + +This tutorial explains how to allocate device memory, transfer data between +host and device, and choose the right memory type for your workload. + +Memory Types on the V80 +======================== + +The AMD Alveo V80 board has two distinct memory subsystems: + +**DDR** + A single, large-capacity address space. Suitable for bulk data that does not + require high bandwidth. Selected with ``MemoryRangeType::DDR``. + +**HBM (High Bandwidth Memory)** + 64 pseudo-channels (HBM0–HBM63) offering very high aggregate bandwidth. + Each channel is accessed independently. There are two ways to use HBM: + + - **Port-based** — ``MemoryRangeType::HBM`` with an explicit port number. + The buffer is allocated on a specific HBM channel and the kernel accesses + that channel directly. This gives the full bandwidth of the channel, but + restricts access to that HBM region only — the kernel cannot reach other + HBM channels through this port. The kernel's ``sp=`` directive in the + linker configuration must map the port to the same channel. + - **VNOC (Virtual NoC)** — ``MemoryRangeType::HBM_VNOC``. The buffer is + allocated across multiple HBM channels and accessed through the on-chip + VNOC interconnect. This allows the kernel to reach the entire HBM memory + space regardless of which channel holds the data, but is bottlenecked by + the lower bandwidth of the VNOC compared to a direct HBM port connection. + +The linker configuration determines which memory each kernel port is connected +to. For example, ``sp=increment_0.m_axi_gmem0:HBM1`` maps the +``m_axi_gmem0`` port of ``increment_0`` to HBM channel 1. + +Creating Buffers +================ + +``Buffer`` is a typed, host-accessible buffer backed by device memory. There +are three ways to construct one. + +From a MemoryConfig (recommended) +---------------------------------- + +.. code-block:: cpp + + // By kernel argument name (recommended) + vrt::Buffer buffer(device, size, increment.argMemoryConfig("in")); + + // By AXI port name + vrt::Buffer buffer(device, size, increment.portMemoryConfig("m_axi_gmem0")); + +Both methods read the vrtbin metadata and return a ``MemoryConfig`` struct with +the correct memory type and HBM port (if applicable), ensuring the buffer +automatically matches the kernel's linker configuration. + +``Kernel::argMemoryConfig()`` is recommended because argument names are part of +the kernel's public interface. +``Kernel::portMemoryConfig()`` requires knowing the internal AXI port name (e.g. +``m_axi_gmem0``), which is an implementation detail of the HLS pragma. + +With explicit HBM port +----------------------- + +.. code-block:: cpp + + vrt::Buffer buffer(device, size, vrt::MemoryRangeType::HBM, 1); + +Allocates on HBM channel 1 specifically. Use this when you need to control +placement directly. The port number must match the ``sp=`` mapping in the linker +configuration. + +With DDR +-------- + +.. code-block:: cpp + + vrt::Buffer buffer(device, size, vrt::MemoryRangeType::DDR); + +Allocates in the DDR address space. + +.. note:: + + Constructing a buffer with ``MemoryRangeType::HBM`` but *without* a port + number throws ``std::invalid_argument``. If you want aggregated HBM + bandwidth without specifying a channel, use ``MemoryRangeType::HBM_VNOC`` + instead. + +Host-Device Data Transfer +========================= + +Data moves between host and device memory with ``sync()``: + +.. code-block:: cpp + + // Fill the buffer on the host side + for (uint32_t i = 0; i < size; i++) { + buffer[i] = static_cast(i); + } + + // Transfer host -> device + buffer.sync(vrt::SyncType::HOST_TO_DEVICE); + + // ... run kernels ... + + // Transfer device -> host + buffer.sync(vrt::SyncType::DEVICE_TO_HOST); + + // Read results + float result = buffer[0]; + +On hardware, ``sync()`` triggers a DMA transfer through the QDMA subsystem. In +emulation and simulation, buffer data is exchanged over ZeroMQ — the same API +works transparently on all platforms. + +Accessing Buffer Data +===================== + +``Buffer`` provides array-style access on the host side: + +.. code-block:: cpp + + buffer[i] = 42.0f; // write element i + float val = buffer[i]; // read element i + float* raw = buffer.get(); // raw pointer to the host buffer + +``operator[]`` performs bounds checking and throws ``std::out_of_range`` if the +index exceeds the buffer size. + +The host-side array is only a local copy. Changes are not visible on the device +until you call ``sync(HOST_TO_DEVICE)``, and device-side results are not visible +on the host until you call ``sync(DEVICE_TO_HOST)``. + +Complete Example +================ + +Putting it all together — the typical buffer workflow: + +.. code-block:: cpp + + #include + #include + #include + + vrt::Device device(bdf, vrtbinFile); + vrt::Kernel increment(device, "increment_0"); + + // Allocate using the kernel's port configuration + uint32_t size = 1024; + vrt::Buffer buffer(device, size, increment.argMemoryConfig("in")); + + // Fill data + for (uint32_t i = 0; i < size; i++) { + buffer[i] = static_cast(i); + } + + // Transfer to device + buffer.sync(vrt::SyncType::HOST_TO_DEVICE); + + // Launch kernel + increment.setArg(0, size); + increment.setArg(1, buffer); + increment.start(); + increment.wait(); + + // Transfer results back + buffer.sync(vrt::SyncType::DEVICE_TO_HOST); + + // Read results + for (uint32_t i = 0; i < size; i++) { + std::cout << buffer[i] << std::endl; + } + + device.cleanup(); + +Common Patterns +=============== + +**Buffer is move-only.** + ``Buffer`` cannot be copied — only moved. This prevents accidental + double-free of device memory. + + .. code-block:: cpp + + vrt::Buffer a(device, size, vrt::MemoryRangeType::DDR); + vrt::Buffer b = std::move(a); // OK + // vrt::Buffer c = b; // compile error + +**Call cleanup() after you are done with buffers.** + ``device.cleanup()`` releases all device resources. Buffers should not be + used after cleanup. + +**HBM port mismatches throw at construction.** + If you create a buffer on HBM channel 3 but the kernel port is mapped to + channel 1 in the linker configuration, the transfer will target the wrong + memory region. Use ``portMemoryConfig()`` to avoid this. + +Next Steps +========== + +- :doc:`/explanation/memory-model` — deeper look at the DDR/HBM memory + subsystems and the buddy allocator. +- :doc:`your-first-kernel` — write your own HLS kernel from scratch. +- :doc:`/explanation/architecture` — understand the full SLASH stack. diff --git a/docs/tutorials/user/emulation-and-simulation.rst b/docs/tutorials/user/emulation-and-simulation.rst new file mode 100644 index 00000000..8948c4ad --- /dev/null +++ b/docs/tutorials/user/emulation-and-simulation.rst @@ -0,0 +1,174 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############################ +Emulation and Simulation +############################ + +This tutorial walks through building and running a SLASH application in +emulation and simulation modes. Neither mode requires FPGA hardware — your +application runs against a software model of the kernels instead. + +For a conceptual overview of the three platforms see +:doc:`/explanation/platform-modes`. + +Prerequisites +============= + +- The SLASH stack is installed (at minimum VRT and the CMake modules). + See :doc:`/howto/build-from-source` if building from source. +- AMD Vivado **2025.1** and Vitis HLS **2025.1** are installed and sourced in + your shell: + + .. code-block:: bash + + source /settings64.sh + source /settings64.sh + + For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. Using versions + other than 2025.1 may cause breakage. + +- For simulation: a Vivado-supported Verilog simulator licence. +- No V80 board is required. + +When to Use Each Mode +===================== + +.. list-table:: + :header-rows: 1 + :widths: 15 25 25 35 + + * - Mode + - Speed + - Accuracy + - Best for + * - **Emulation** + - Fast + - Functional only + - Rapid iteration on kernel logic + * - **Simulation** + - Slow + - Cycle-accurate RTL + - Catching timing and protocol bugs + +Use emulation first to verify functional correctness, then simulation when +you need cycle-accurate behaviour. + +Build an Emulation Vrtbin +========================= + +Ensure you have sourced Vivado and Vitis HLS before building (see +`Prerequisites`_). + +Using the ``00_axilite`` example: + +.. code-block:: bash + + cd examples/00_axilite + cmake -B build -S . -G Ninja + cmake --build build # build the host application + cmake --build build --target hls # compile HLS kernels (requires Vitis HLS) + cmake --build build --target axilite_emu # link into an emulation vrtbin + +The ``axilite_emu`` target invokes the SLASH linker (``slashkit``) with +``PLATFORM "emu"``. The resulting ``.vbin`` file contains: + +- ``system_map.xml`` with ``Emulation`` +- ``vpp_emu`` — a compiled C-model executable of the HLS kernels +- ``emu_manifest.json`` — argument routing metadata + +Run in Emulation +================ + +Run the same application binary, passing the emulation vrtbin: + +.. code-block:: bash + + ./00_axilite 03:00 axilite_emu.vbin + +The BDF argument (``03:00``) is still required for API compatibility but no +hardware is accessed. Under the hood VRT: + +1. Extracts the vrtbin and reads ``system_map.xml``. +2. Detects ``Platform::EMULATION``. +3. Launches the ``vpp_emu`` process in a background thread. +4. Connects to the C-model via ZeroMQ on ``tcp://localhost:5555``. +5. Translates ``setArg()``, ``start()``, ``wait()``, and ``sync()`` calls + into JSON commands sent over ZeroMQ. + +The application output should match hardware results exactly. + +Build and Run in Simulation +=========================== + +.. code-block:: bash + + cmake --build build --target axilite_sim # link into a simulation vrtbin + ./00_axilite 03:00 axilite_sim.vbin + +The simulation vrtbin contains a ``vpp_sim`` executable (a Verilog +simulator wrapper) and a ``system_map.xml`` with +``Simulation``. + +VRT launches the simulator and communicates via ZeroMQ in the same way as +emulation. Simulation is significantly slower — expect minutes rather than +seconds for even simple designs. + +Querying the Platform at Runtime +================================ + +Your application can check the active platform and adjust behaviour: + +.. code-block:: cpp + + vrt::Device device(bdf, vrtbinPath); + + if (device.getPlatform() == vrt::Platform::EMULATION) { + std::cout << "Running in emulation mode" << std::endl; + } + + if (device.getPlatform() == vrt::Platform::SIMULATION) { + std::cout << "Running in simulation mode" << std::endl; + } + +See :doc:`/reference/vrt-api/enums` for all ``vrt::Platform`` values. + +How Buffers Work in Emulation and Simulation +============================================ + +In emulation and simulation, ``vrt::Buffer`` allocates host memory +instead of device memory. Fake physical addresses are assigned automatically +so that kernel argument routing works transparently: + +- **Emulation** — ``sync(HOST_TO_DEVICE)`` sends the buffer contents over + ZeroMQ to the C-model. ``sync(DEVICE_TO_HOST)`` fetches the results + back. +- **Simulation** — the same pattern applies, using the simulator's memory + model. + +No changes to your buffer code are needed. The same ``sync()`` calls work +on all three platforms. + +Known Limitations +================= + +**Emulation:** + +- Timing is not modelled — performance measurements are not meaningful. +- HLS kernels must include at least one AXI4-Lite interface. + +**Simulation:** + +- Significantly slower than emulation. +- Requires AMD Vivado and a simulator licence. +- Floating-point representation in the simulator can introduce NaN artefacts. + Your application should handle these with relaxed comparison tolerances. + +Next Steps +========== + +- :doc:`/explanation/platform-modes` — conceptual overview of all three + platforms. +- :doc:`/explanation/vrtbin-format` — what is inside a vrtbin archive. +- :doc:`your-first-kernel` — write and build your own HLS kernel. diff --git a/docs/tutorials/user/getting-started.rst b/docs/tutorials/user/getting-started.rst new file mode 100644 index 00000000..49b0a0c0 --- /dev/null +++ b/docs/tutorials/user/getting-started.rst @@ -0,0 +1,182 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +############### +Getting Started +############### + +This tutorial walks through building and running your first SLASH application +using example ``00_axilite``. + +Prerequisites +============= + +Before you begin, ensure: + +- The SLASH stack is installed (kernel module, libslash, vrtd, VRT, v80-smi). + The recommended way is to install pre-built packages — see + :doc:`/tutorials/admin/platform-setup`. To build from source instead, see + :doc:`/howto/build-from-source`. +- A V80 board is installed and visible (run ``v80-smi list`` to check). +- The ``vrtd`` daemon is running (``sudo systemctl enable --now vrtd``). +- AMD Vivado **2025.1** and Vitis HLS **2025.1** are installed and sourced in + your shell (for building FPGA artefacts). Source the environment before + building: + + .. code-block:: bash + + source /settings64.sh + source /settings64.sh + + For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. Using versions + other than 2025.1 may cause breakage. + +What the Example Does +===================== + +Example ``00_axilite`` demonstrates AXI-Lite control interfaces. It deploys two +HLS kernels onto a V80 board: + +- **increment** — reads a buffer of floats from device memory, adds 1.0 to each + element, and writes the result back. +- **accumulate** — sums all elements and returns the total via an AXI-Lite + output register. + +The host application generates random data, sends it to the device, runs both +kernels, and verifies the result against a golden model. + +Build the Example +================= + +.. code-block:: bash + + cd examples/00_axilite + cmake -B build -S . -G Ninja + cmake --build build + +This builds the host application. To also build the FPGA artefacts (HLS kernels +and hardware vrtbin), ensure you have sourced Vivado and Vitis HLS first (see +`Prerequisites`_): + +.. code-block:: bash + + cmake --build build --target hls # compile HLS kernels + cmake --build build --target axilite_hw # link into a hardware vrtbin + +For emulation (no FPGA required): + +.. code-block:: bash + + cmake --build build --target axilite_emu # link into an emulation vrtbin + +Run the Example +=============== + +Identify your board's BDF address: + +.. code-block:: bash + + v80-smi list + +Run the application with the BDF and the vrtbin file: + +.. code-block:: bash + + ./00_axilite + +For example: + +.. code-block:: bash + + ./00_axilite 03:00 axilite_hw.vbin + +Expected output: + +.. code-block:: text + + VRT Version: 0.1.0 + Generating data... + Time taken for waits: us + Expected: + Got: + Absolute error: (effective tolerance ...) + Test passed! + +Understanding the Code +====================== + +The key VRT calls in ``00_axilite.cpp``: + +**1. Open a device and load the vrtbin:** + +.. code-block:: cpp + + vrt::Device device(bdf, vrtbinFile); + +This connects to vrtd, opens the board at the given BDF, and programs the FPGA +with the design from the vrtbin file. The platform (hardware, emulation, or +simulation) is determined automatically from the vrtbin contents. + +**2. Create kernel handles:** + +.. code-block:: cpp + + vrt::Kernel accumulate(device, "accumulate_0"); + vrt::Kernel increment(device, "increment_0"); + +Each kernel is looked up by name from the loaded design. + +**3. Allocate a device buffer:** + +.. code-block:: cpp + + vrt::Buffer buffer(device, size, increment.argMemoryConfig("in")); + +This allocates ``size`` floats in device memory. The memory configuration +(DDR vs HBM, address range) is taken from the kernel argument named ``"in"``. + +**4. Transfer data to the device:** + +.. code-block:: cpp + + buffer.sync(vrt::SyncType::HOST_TO_DEVICE); + +DMA transfers the host-side buffer contents to device memory. + +**5. Set arguments and launch kernels:** + +.. code-block:: cpp + + increment.setArg(0, size); + increment.setArg(1, buffer); + increment.start(); + +Arguments are written to the kernel's AXI-Lite registers. ``start()`` sets the +AP_START bit. ``wait()`` polls until the kernel signals completion. + +**6. Read a result register:** + +.. code-block:: cpp + + uint32_t val = accumulate.read(0x18); + +Reads a 32-bit value from the kernel's AXI-Lite register space at offset +``0x18``. + +**7. Clean up:** + +.. code-block:: cpp + + device.cleanup(); + +Releases device resources. + +Next Steps +========== + +- :doc:`your-first-kernel` — write your own HLS kernel from scratch. +- :doc:`buffers-and-memory` — learn about DDR vs HBM and streaming buffers. +- :doc:`/explanation/architecture` — understand the full SLASH stack. +- :doc:`/explanation/platform-modes` — run the same code in emulation or + simulation. diff --git a/docs/tutorials/user/your-first-kernel.rst b/docs/tutorials/user/your-first-kernel.rst new file mode 100644 index 00000000..d4a7c7db --- /dev/null +++ b/docs/tutorials/user/your-first-kernel.rst @@ -0,0 +1,300 @@ +.. + comment:: SPDX-License-Identifier: MIT + comment:: Copyright (C) 2025 Advanced Micro Devices, Inc + +################## +Your First Kernel +################## + +This tutorial walks through writing an HLS kernel from scratch, compiling it +with Vitis HLS, linking it into a vrtbin, and running it on a V80 board. By the +end you will understand every file in a minimal SLASH project. + +Prerequisites +============= + +- The SLASH stack is installed (kernel module, libslash, vrtd, VRT, v80-smi). + See :doc:`/howto/build-from-source` if building from source. +- AMD Vivado **2025.1** and Vitis HLS **2025.1** are installed and sourced in + your shell: + + .. code-block:: bash + + source /settings64.sh + source /settings64.sh + + For ``csh``/``tcsh`` shells, use ``settings64.csh`` instead. Using versions + other than 2025.1 may cause breakage. + +- A V80 board is installed and visible (``v80-smi list``), or you plan to use + simulation/emulation. + +Anatomy of an HLS Kernel +========================= + +An HLS kernel is a C/C++ function with interface pragmas that tell Vitis HLS +how to map arguments to hardware ports. Here is the ``increment`` kernel from +``examples/00_axilite/hls/increment.cpp``: + +.. code-block:: cpp + + #include + #include + + void increment(ap_uint<32> size, float* in, hls::stream& axis_out) { + #pragma hls interface mode=s_axilite port=size + #pragma hls interface m_axi bundle=gmem0 port=in max_widen_bitwidth=64 + #pragma hls interface axis port=axis_out + #pragma hls interface mode=s_axilite port=return + + for(ap_uint<32> i = 0; i < size; i++) { + #pragma hls pipeline II=1 + float data = in[i] + 1; + axis_out.write(data); + } + } + +Each pragma controls a different aspect of the hardware interface: + +``s_axilite`` + Exposes the argument as a memory-mapped register on the AXI-Lite control + bus. The host sets these via ``Kernel::setArg()`` before launching the + kernel. + +``m_axi`` + Maps a pointer argument to an AXI memory-mapped master port. The + ``bundle=gmem0`` name becomes the port name visible in the linker + configuration (prefixed with ``m_axi_``). ``max_widen_bitwidth=64`` + limits data-path widening for this port. + +``axis`` + Maps an ``hls::stream`` argument to an AXI-Stream port. Streams connect + kernels directly without going through device memory. + +``s_axilite port=return`` + Required on every SLASH kernel. It creates the AP_START / AP_DONE / AP_IDLE + control registers that VRT uses to start and poll the kernel. + +``pipeline II=1`` + Instructs HLS to pipeline the loop body with an initiation interval of one + clock cycle — one new iteration begins every cycle. + +HLS Configuration File +======================= + +Each kernel needs a ``.cfg`` file that tells Vitis HLS how to compile it. +Here is ``increment.cfg``: + +.. code-block:: ini + + part=xcv80-lsva4737-2MHP-e-S + + [hls] + flow_target=vivado + + syn.top=increment + syn.file=increment.cpp + clock=4ns + + package.output.format=ip_catalog + package.output.syn=false + +``part`` + The FPGA part string for the V80 board. + +``syn.top`` + The top-level function name in the C++ source. + +``syn.file`` + The source file to compile. + +``clock`` + The target clock period. ``4ns`` corresponds to 250 MHz. + +``package.output.format`` + Must be ``ip_catalog`` so the output can be consumed by the SLASH linker. + +``package.output.syn`` + Set to ``false`` to skip RTL synthesis during HLS (the linker handles it). + +Linker Configuration +==================== + +The linker configuration file (``config.cfg``) describes how kernels are +instantiated, connected, and mapped to memory. Here is +``examples/00_axilite/config.cfg``: + +.. code-block:: ini + + [connectivity] + nk=accumulate:1:accumulate_0 + nk=increment:1:increment_0 + stream_connect=increment_0.axis_out:accumulate_0.axis_in + sp=increment_0.m_axi_gmem0:HBM1 + +``nk`` + Instantiates a kernel. Format: ``::``. + The instance name is what you pass to ``vrt::Kernel(device, "increment_0")``. + +``stream_connect`` + Wires an AXI-Stream output port on one kernel instance to an input port on + another. Format: ``.:.``. + +``sp`` + Maps an AXI memory-mapped port to a physical memory resource. Format: + ``.:``. Valid memories include ``HBM0``–``HBM63``, + ``DDR0``–``DDR3``, and ``MEM``. + +CMake Build Setup +================= + +SLASH provides CMake modules for compiling HLS kernels and linking vrtbins. +With SLASH installed, use ``find_package`` to import them: + +.. code-block:: cmake + + cmake_minimum_required(VERSION 3.20) + project(my_project LANGUAGES CXX) + set(CMAKE_CXX_STANDARD 20) + + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + + # --- HLS kernels --- + set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") + + build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS increment accumulate + OUT_KERNELS _KERNELS + ) + + # --- VBIN targets --- + set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + add_vbin(TARGET "my_design_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "my_design_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "my_design_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + + # --- Executable --- + add_executable(my_app main.cpp) + target_link_libraries(my_app PRIVATE vrt::vrt) + +``find_package(SlashTools)`` makes ``build_hls_dir()`` and ``add_vbin()`` +available, and also locates Vivado and Vitis automatically. + +``build_hls_dir()`` compiles every kernel in the ``hls/`` directory. It +expects ``.cpp`` and ``.cfg`` file pairs for each kernel listed in +``KERNELS``. The compiled IP paths are stored in ``_KERNELS``. + +``add_vbin()`` invokes the SLASH linker (``slashkit``) to produce a ``.vbin`` +archive from the compiled kernels and the connectivity configuration. One +target is created per platform (``hw``, ``emu``, ``sim``). + +See :doc:`/reference/cmake/slashtools` and :doc:`/reference/cmake/buildhls` +for full function reference. + +Build and Run +============= + +Ensure you have sourced Vivado and Vitis HLS before building (see +`Prerequisites`_). + +.. code-block:: bash + + cmake -B build -S . -G Ninja + cmake --build build # build the host application + cmake --build build --target hls # compile HLS kernels (requires Vitis HLS) + cmake --build build --target my_design_hw # link into a hardware vrtbin + +Run the application: + +.. code-block:: bash + + v80-smi list # find your board's BDF + ./my_app 03:00 my_design_hw.vbin # run with BDF and vrtbin + +For emulation (no FPGA required): + +.. code-block:: bash + + cmake --build build --target my_design_emu + ./my_app 03:00 my_design_emu.vbin + +Creating Your Own Project +========================= + +To start a project outside the SLASH repository, create a directory with the +following layout: + +.. code-block:: text + + my_project/ + ├── CMakeLists.txt + ├── config.cfg + ├── main.cpp + └── hls/ + ├── my_kernel.cpp + └── my_kernel.cfg + +**CMakeLists.txt** — use ``find_package`` to locate the installed SLASH modules: + +.. code-block:: cmake + + cmake_minimum_required(VERSION 3.20) + project(my_project LANGUAGES CXX) + set(CMAKE_CXX_STANDARD 20) + + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + + set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") + + build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS my_kernel + OUT_KERNELS _KERNELS + ) + + set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + add_vbin(TARGET "my_design_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "my_design_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + add_vbin(TARGET "my_design_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + + add_executable(my_app main.cpp) + target_link_libraries(my_app PRIVATE vrt::vrt) + +**config.cfg** — a minimal connectivity configuration: + +.. code-block:: ini + + [connectivity] + nk=my_kernel:1:my_kernel_0 + sp=my_kernel_0.m_axi_gmem0:HBM1 + +**Build sequence:** + +.. code-block:: bash + + cmake -B build -S . -G Ninja + cmake --build build # build the host application + cmake --build build --target hls # compile HLS kernels + cmake --build build --target my_design_hw # hardware vrtbin + cmake --build build --target my_design_emu # emulation vrtbin + cmake --build build --target my_design_sim # simulation vrtbin + +See :doc:`/howto/use-cmake-modules` for the full CMake setup reference. + +Next Steps +========== + +- :doc:`buffers-and-memory` — learn about DDR vs HBM memory and buffer + management. +- :doc:`/reference/cmake/slashtools` — full ``add_vbin()`` reference. +- :doc:`/reference/cmake/buildhls` — full ``build_hls()`` and + ``build_hls_dir()`` reference. +- :doc:`/explanation/platform-modes` — run the same code in emulation or + simulation. diff --git a/driver/.gitignore b/driver/.gitignore new file mode 100644 index 00000000..d1963bd4 --- /dev/null +++ b/driver/.gitignore @@ -0,0 +1,15 @@ +# Kernel module build artifacts +*.o +*.ko +*.mod +*.mod.c +*.mod.o +*.cmd +*.gcno +Module.symvers +modules.order +compile_commands_driver.json + +# LCov coverage outputs +coverage.info +coverage diff --git a/driver/Makefile b/driver/Makefile new file mode 100644 index 00000000..98a56815 --- /dev/null +++ b/driver/Makefile @@ -0,0 +1,137 @@ +#/** +# * Copyright (C) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# * This program is free software; you can redistribute it and/or modify it under the terms of the +# * GNU General Public License as published by the Free Software Foundation; version 2. +# * +# * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without +# * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# * General Public License for more details. +# * +# * You should have received a copy of the GNU General Public License along with this program; if +# * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# * 02110-1301, USA. +# */ + + +MODULE := slash + +ifneq ($(KERNELDIR),) +KDIR ?= $(KERNELDIR) +else +KDIR ?= /lib/modules/$(shell uname -r)/build +endif +PWD := $(shell pwd) + +# Driver version. Priority: +# 1. SLASH_VERSION passed in (e.g. from DKMS MAKE[0]). +# 2. packaging/version file (in-tree builds). +# 3. "unknown" fallback (DKMS install tree has no packaging/version). +SLASH_VERSION ?= $(strip $(shell cat $(src)/../packaging/version 2>/dev/null)) +ifeq ($(SLASH_VERSION),) +SLASH_VERSION := unknown +endif + +# This exists when installed for dkms +LIBQDMA_LOCAL_DIR := ./libqdma +# This exists when building from tree +LIBQDMA_FALLBACK := ../submodules/qdma_drv/QDMA/linux-kernel/driver/libqdma + +ifneq (,$(wildcard $(src)/$(LIBQDMA_LOCAL_DIR)/.)) + LIBQDMA_PATH := $(LIBQDMA_LOCAL_DIR) +else + LIBQDMA_PATH := $(LIBQDMA_FALLBACK) +endif + +SLASH_QDMA_OP_DEBUG ?= 0 + +# Kcompat feature flags. Defaults are "n"; the all: recipe runs +# driver/kcompat/probe.sh against $(KDIR) to detect the actual values +# and passes them into the kbuild recursion. Each pair (modern API + +# legacy fallback) is covered by one probe — if the modern form is +# absent, the legacy form is the unconditional fallback in slash_compat.h. +SLASH_HAVE_VM_FLAGS_SET ?= n +SLASH_HAVE_MODULE_IMPORT_NS_TOKEN ?= n + +# Set GCOV=1 to instrument the module for kernel gcov coverage. +# Not set by default — never enable this in production builds. +ifdef GCOV +GCOV_PROFILE := y +endif + +obj-m := $(MODULE).o +$(MODULE)-objs := $(MODULE)_main.o $(MODULE)_ctldev.o $(MODULE)_pcie.o $(MODULE)_dmabuf.o $(MODULE)_hotplug.o $(MODULE)_qdma.o +ccflags-y += \ + -I$(src)/libslash/include \ + -I$(src)/libslash/include/slash/uapi \ + -I$(src)/$(LIBQDMA_PATH) \ + -I$(src)/$(LIBQDMA_PATH)/qdma_access \ + -I$(src)/$(LIBQDMA_PATH)/qdma_access/eqdma_cpm5_access \ + -I$(src)/$(LIBQDMA_PATH)/qdma_access/eqdma_soft_access \ + -I$(src)/$(LIBQDMA_PATH)/qdma_access/qdma_cpm4_access \ + -I$(src)/$(LIBQDMA_PATH)/qdma_access/qdma_soft_access \ + \ + -DTANDEM_BOOT_SUPPORTED=1 \ + -DSLASH_QDMA_OP_DEBUG=$(SLASH_QDMA_OP_DEBUG) \ + -DSLASH_VERSION_STR=\"$(SLASH_VERSION)\" + +ifeq ($(SLASH_HAVE_VM_FLAGS_SET),y) +ccflags-y += -DSLASH_HAVE_VM_FLAGS_SET +endif + +ifeq ($(SLASH_HAVE_MODULE_IMPORT_NS_TOKEN),y) +ccflags-y += -DSLASH_HAVE_MODULE_IMPORT_NS_TOKEN +endif + + +LIBQDMA_OBJS := \ + $(LIBQDMA_PATH)/qdma_mbox.o \ + $(LIBQDMA_PATH)/qdma_intr.o \ + $(LIBQDMA_PATH)/qdma_st_c2h.o \ + $(LIBQDMA_PATH)/qdma_thread.o \ + $(LIBQDMA_PATH)/libqdma_export.o \ + $(LIBQDMA_PATH)/qdma_context.o \ + $(LIBQDMA_PATH)/qdma_sriov.o \ + $(LIBQDMA_PATH)/qdma_platform.o \ + $(LIBQDMA_PATH)/qdma_descq.o \ + $(LIBQDMA_PATH)/qdma_regs.o \ + $(LIBQDMA_PATH)/qdma_debugfs.o \ + $(LIBQDMA_PATH)/qdma_debugfs_dev.o \ + $(LIBQDMA_PATH)/qdma_debugfs_queue.o \ + $(LIBQDMA_PATH)/libqdma_config.o \ + $(LIBQDMA_PATH)/qdma_device.o \ + $(LIBQDMA_PATH)/xdev.o \ + $(LIBQDMA_PATH)/thread.o + +QDMA_ACCESS_OBJS := \ + $(LIBQDMA_PATH)/qdma_access/qdma_mbox_protocol.o \ + $(LIBQDMA_PATH)/qdma_access/qdma_list.o \ + $(LIBQDMA_PATH)/qdma_access/qdma_access_common.o \ + $(LIBQDMA_PATH)/qdma_access/qdma_resource_mgmt.o \ + $(LIBQDMA_PATH)/qdma_access/qdma_cpm4_access/qdma_cpm4_access.o \ + $(LIBQDMA_PATH)/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.o \ + $(LIBQDMA_PATH)/qdma_access/qdma_soft_access/qdma_soft_access.o \ + $(LIBQDMA_PATH)/qdma_access/eqdma_soft_access/eqdma_soft_access.o \ + $(LIBQDMA_PATH)/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.o \ + $(LIBQDMA_PATH)/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.o \ + $(LIBQDMA_PATH)/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.o + +$(MODULE)-objs += $(LIBQDMA_OBJS) $(QDMA_ACCESS_OBJS) + + +KCOMPAT := "$(SHELL)" "$(PWD)/kcompat/probe.sh" + +all: + @flags="$$($(KCOMPAT) "$(KDIR)" | tr '\n' ' ')"; \ + echo "slash: kcompat: $$flags"; \ + $(MAKE) -C "$(KDIR)" M="$(PWD)" $$flags modules + +clean: + $(MAKE) -C "$(KDIR)" M="$(PWD)" clean + rm -rf "$(PWD)/kcompat/.scratch" + +install: all + sudo install -d -m 755 /lib/modules/$(shell uname -r)/extra + sudo install -m 644 $(MODULE).ko /lib/modules/$(shell uname -r)/extra + sudo depmod -a + +.PHONY: all clean install diff --git a/driver/README.md b/driver/README.md new file mode 100644 index 00000000..65cd911a --- /dev/null +++ b/driver/README.md @@ -0,0 +1,71 @@ +# SLASH kernel module + +## Testing + +The test suite requires a physical V80 to be present and the module to be +loaded into a running kernel. + +### Prerequisites + +- A kernel built with `CONFIG_GCOV_KERNEL=y` (only needed for coverage runs). +- `lcov` and `genhtml` installed (only needed for coverage runs). +- The BDF identifier of the V80 card (e.g. `0000:03:00`). + - You may be able to retrieve the BDF identifier by running `v80-smi list` + +### Running the tests manually + +Build the module and the test suite: + +```sh +make # builds slash.ko +make -C tests/ all +``` + +Load the module and rescan the PCI bus so the device nodes appear: + +```sh +sudo insmod ./slash.ko +echo 1 | sudo tee /sys/bus/pci/rescan > /dev/null +``` + +Run the kselftest suite (must be run as root): + +```sh +sudo make -C tests/ run +``` + +The suite produces TAP output. Each test fixture automatically tears down +queue pairs on failure, so a failing test does not leave the device in a +broken state. + +#### Optional: override the DMA target address + +The `write_read_verify` test defaults to DMA address `0x0`. Set +`SLASH_TEST_DMA_ADDR` to use a different address: + +```sh +sudo SLASH_TEST_DMA_ADDR=0x100000000 make -C tests/ run +``` + +### Running with code-coverage instrumentation + +`test_module.sh` automates the full build → load → test → coverage cycle: + +```sh +./test_module.sh +``` + +Replace `` with the BDF of the V80 (e.g. `0000:03:00`). + +The script: +1. Checks that the running kernel has `CONFIG_GCOV_KERNEL=y`. +2. Builds `slash.ko` with gcov instrumentation (`make GCOV=1`). +3. Builds the test suite. +4. Removes any currently-loaded `slash` module. +5. Resets the gcov counters. +6. Inserts the module and rescans the PCI bus. +7. Runs the full kselftest suite. +8. Removes the module. +9. Captures coverage with `lcov` and generates an HTML report in `coverage/`. + +Open `coverage/index.html` in a browser to browse line-level coverage. diff --git a/driver/kcompat/module_import_ns_token.c b/driver/kcompat/module_import_ns_token.c new file mode 100644 index 00000000..fa58d976 --- /dev/null +++ b/driver/kcompat/module_import_ns_token.c @@ -0,0 +1,44 @@ +/** + * Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/* + * Token-form MODULE_IMPORT_NS probe. + * + * Pre-6.13: MODULE_IMPORT_NS(ns) = MODULE_INFO(import_ns, __stringify(ns)) + * -> token form is the documented usage. + * 6.13+: MODULE_IMPORT_NS(ns) = MODULE_INFO(import_ns, ns) + * -> token form fails to compile (DMA_BUF undefined). + * + * So this probe succeeds iff the token form is the right one to use. + * Compile success on a pre-6.13 kernel that still accepts the string + * form silently produces the wrong namespace string at runtime, which + * is why we probe the token form (precise) instead of the string form + * (ambiguous on older kernels). + */ +#include +#include + +static int __init conftest_init(void) +{ + return 0; +} + +static void __exit conftest_exit(void) +{ +} + +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(DMA_BUF); +module_init(conftest_init); +module_exit(conftest_exit); diff --git a/driver/kcompat/probe.sh b/driver/kcompat/probe.sh new file mode 100755 index 00000000..a8245e9a --- /dev/null +++ b/driver/kcompat/probe.sh @@ -0,0 +1,67 @@ +#!/bin/sh +#/** +# * Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. +# * This program is free software; you can redistribute it and/or modify it under the terms of the +# * GNU General Public License as published by the Free Software Foundation; version 2. +# * +# * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without +# * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# * General Public License for more details. +# * +# * You should have received a copy of the GNU General Public License along with this program; if +# * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# * 02110-1301, USA. +# */ + +# Probe the kernel build at $1 for SLASH API compatibility features. +# +# Each *.c file in this directory is built as a tiny standalone module +# against the target kernel headers; a successful build means the +# feature is available. One make-style assignment per feature is +# printed to stdout, e.g.: +# +# SLASH_HAVE_VM_FLAGS_SET=y +# SLASH_HAVE_MODULE_IMPORT_NS_STRING=n +# +# To add a new probe, drop another conftest .c file into this directory. +# The macro name is derived from the file basename (uppercased). + +set -eu + +if [ "$#" -ne 1 ]; then + echo "Usage: $0 " >&2 + exit 2 +fi + +kdir="$1" +here="$(cd "$(dirname "$0")" && pwd)" + +if [ ! -d "$kdir" ]; then + echo "$0: kernel build dir '$kdir' not found" >&2 + exit 1 +fi + +scratch="$here/.scratch" +cleanup() { rm -rf "$scratch"; } +trap cleanup EXIT HUP INT TERM + +# Conftest builds must actually compile to be meaningful. Drop any +# flags the parent make may have set (notably -n / --dry-run, which +# would make every probe look successful but produce no real result). +unset MAKEFLAGS MFLAGS MAKEOVERRIDES + +rm -rf "$scratch" +mkdir -p "$scratch" +printf 'obj-m := conftest.o\n' > "$scratch/Makefile" + +for src in "$here"/*.c; do + [ -f "$src" ] || continue + feat=$(basename "$src" .c) + cp "$src" "$scratch/conftest.c" + if "${MAKE:-make}" -s -C "$kdir" M="$scratch" modules >/dev/null 2>&1; then + ans=y + else + ans=n + fi + printf 'SLASH_HAVE_%s=%s\n' "$(printf '%s' "$feat" | tr '[:lower:]' '[:upper:]')" "$ans" +done diff --git a/driver/kcompat/vm_flags_set.c b/driver/kcompat/vm_flags_set.c new file mode 100644 index 00000000..dcc4edac --- /dev/null +++ b/driver/kcompat/vm_flags_set.c @@ -0,0 +1,33 @@ +/** + * Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include + +static int __init conftest_init(void) +{ + struct vm_area_struct *vma = NULL; + + vm_flags_set(vma, (vm_flags_t)0); + return 0; +} + +static void __exit conftest_exit(void) +{ +} + +MODULE_LICENSE("GPL"); +module_init(conftest_init); +module_exit(conftest_exit); diff --git a/driver/libslash/.gitignore b/driver/libslash/.gitignore new file mode 100644 index 00000000..cc786a97 --- /dev/null +++ b/driver/libslash/.gitignore @@ -0,0 +1 @@ +doc/ \ No newline at end of file diff --git a/driver/libslash/CMakeLists.txt b/driver/libslash/CMakeLists.txt new file mode 100644 index 00000000..7ecc1f6b --- /dev/null +++ b/driver/libslash/CMakeLists.txt @@ -0,0 +1,120 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.16) + +# Read version from packaging/version +file(READ "${CMAKE_CURRENT_SOURCE_DIR}/../../packaging/version" LIBSLASH_VERSION) +string(STRIP "${LIBSLASH_VERSION}" LIBSLASH_VERSION) + +# Parse into components +string(REPLACE "." ";" VERSION_LIST "${LIBSLASH_VERSION}") +list(GET VERSION_LIST 0 LIBSLASH_VERSION_MAJOR) +list(GET VERSION_LIST 1 LIBSLASH_VERSION_MINOR) +list(GET VERSION_LIST 2 LIBSLASH_VERSION_PATCH) + +message(STATUS "LIBSLASH version: ${LIBSLASH_VERSION} (${LIBSLASH_VERSION_MAJOR}.${LIBSLASH_VERSION_MINOR}.${LIBSLASH_VERSION_PATCH})") + +project(libslash + VERSION ${LIBSLASH_VERSION} + LANGUAGES C CXX +) + +# Allow user to choose shared vs static (standard CMake variable) +option(BUILD_SHARED_LIBS "Build shared libraries" ON) +option(LIBSLASH_BUILD_TESTS "Build unit tests" OFF) + +option(ENABLE_SANITIZERS "Build with AddressSanitizer and UBSan" OFF) +if(ENABLE_SANITIZERS) + add_compile_options(-fsanitize=address,undefined -fno-omit-frame-pointer) + add_link_options(-fsanitize=address,undefined) +endif() + +option(ENABLE_COVERAGE "Build with gcov coverage instrumentation" OFF) +if(ENABLE_COVERAGE) + if(ENABLE_SANITIZERS) + message(FATAL_ERROR "ENABLE_COVERAGE and ENABLE_SANITIZERS cannot be used together") + endif() + add_compile_options(--coverage -fno-inline) + add_link_options(--coverage) +endif() + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) + +add_subdirectory(src) + +if(LIBSLASH_BUILD_TESTS) + add_subdirectory(tests) +endif() + +# -------- Installation: headers and library -------- +# Public headers are under include/ (layout: include/slash/*.h) +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + TARGETS slash + EXPORT slashTargets + ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}" + LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}" + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" + INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +# -------- CMake package configuration -------- +# Generate the version file +write_basic_package_version_file( + "${CMAKE_CURRENT_BINARY_DIR}/slashConfigVersion.cmake" + VERSION ${PROJECT_VERSION} + COMPATIBILITY SameMinorVersion +) + +# Configure the main package config from template +configure_package_config_file( + "${PROJECT_SOURCE_DIR}/cmake/slashConfig.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/slashConfig.cmake" + INSTALL_DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/slash" +) + +# Export targets for *install* tree +install( + EXPORT slashTargets + NAMESPACE slash:: + FILE slashTargets.cmake + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/slash" +) + +# Install the config + version files +install( + FILES + "${CMAKE_CURRENT_BINARY_DIR}/slashConfig.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/slashConfigVersion.cmake" + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/slash" +) + +# Export targets for *build* tree so a project can use this directory directly +export( + EXPORT slashTargets + NAMESPACE slash:: + FILE "${CMAKE_CURRENT_BINARY_DIR}/slashTargets.cmake" +) diff --git a/driver/libslash/README.md b/driver/libslash/README.md new file mode 100644 index 00000000..9e04813a --- /dev/null +++ b/driver/libslash/README.md @@ -0,0 +1,203 @@ +# libslash + +Userspace C library for the SLASH kernel driver. libslash provides a +thin, type-safe wrapper around the driver's ioctl interface, covering +three areas of functionality: + +| Module | Header | Device node | PCI function | +|----------|-------------------|--------------------------|--------------| +| Control | `slash/ctldev.h` | `/dev/slash_ctl` | PF2 | +| QDMA | `slash/qdma.h` | `/dev/slash_qdma_ctl` | PF1 | +| Hotplug | `slash/hotplug.h` | `/dev/slash_hotplug` | — | + +## Building + +```sh +cmake -B build -S . -G Ninja +cmake --build build +``` + +CMake options: + +| Option | Default | Description | +|-----------------------|---------|--------------------------------| +| `BUILD_SHARED_LIBS` | `ON` | Build a shared library | +| `SLASH_BUILD_EXAMPLES` | `ON` | Build example programs | +| `SLASH_BUILD_TESTS` | `ON` | Build unit tests | + +## Installing + +```sh +sudo cmake --install build --prefix /usr/local +``` + +This installs: + +- Headers to `/include/slash/` +- Library to `/lib/libslash.so` (or `.a`) +- CMake package config to `/lib/cmake/slash/` + +Downstream projects can then use: + +```cmake +find_package(slash REQUIRED) +target_link_libraries(myapp PRIVATE slash::slash) +``` + +## API overview + +All functions follow POSIX conventions: pointer-returning functions +return `NULL` on failure, int-returning functions return `-1`. `errno` +is set in both cases. + +### Control device — BAR info and memory-mapped access + +```c +#include + +/* Open the control device (or "@mock" for testing without hardware) */ +struct slash_ctldev *dev = slash_ctldev_open("/dev/slash_ctl0"); + +/* Query PCI identity */ +struct slash_ioctl_device_info *info = slash_device_info_read(dev); +printf("BDF: %s vendor: 0x%04x\n", info->bdf, info->vendor_id); +slash_device_info_free(info); + +/* Query and map a BAR */ +struct slash_ioctl_bar_info *bi = slash_bar_info_read(dev, 0); +if (bi->usable) { + struct slash_bar_file *bar = slash_bar_file_open(dev, 0, O_CLOEXEC); + volatile uint32_t *regs = bar->map; + + /* Bracket MMIO accesses with dma-buf sync calls */ + slash_bar_file_start_write(bar); + regs[0] = 0x1; + slash_bar_file_end_write(bar); + + slash_bar_file_start_read(bar); + uint32_t val = regs[0]; + slash_bar_file_end_read(bar); + + slash_bar_file_close(bar); +} +slash_bar_info_free(bi); + +slash_ctldev_close(dev); +``` + +### QDMA — queue-based DMA transfers + +Queue pair lifecycle: **add → start → I/O → stop → del**. + +```c +#include + +struct slash_qdma *qdma = slash_qdma_open("/dev/slash_qdma_ctl0"); + +/* Create a queue pair (MM mode, H2C + C2H directions) */ +struct slash_qdma_qpair_add req = { + .size = sizeof(req), + .mode = 0, /* QDMA_Q_MODE_MM */ + .dir_mask = 0x3, /* H2C | C2H */ + .h2c_ring_sz = 4, /* CSR table index */ + .c2h_ring_sz = 4, + .cmpt_ring_sz = 4, +}; +slash_qdma_qpair_add(qdma, &req); +uint32_t qid = req.qid; + +slash_qdma_qpair_start(qdma, qid); + +/* Get an fd for data transfer — read() = C2H, write() = H2C */ +int fd = slash_qdma_qpair_get_fd(qdma, qid, O_CLOEXEC); +write(fd, buf, len); /* H2C */ +read(fd, buf, len); /* C2H */ +close(fd); + +slash_qdma_qpair_stop(qdma, qid); +slash_qdma_qpair_del(qdma, qid); +slash_qdma_close(qdma); +``` + +### Hotplug — PCIe device lifecycle + +Typical FPGA reconfiguration flow: +**remove → SBR → sleep → rescan → hotplug**. + +```c +#include + +struct slash_hotplug *hp = slash_hotplug_open(NULL); /* /dev/slash_hotplug */ + +slash_hotplug_remove(hp, "0000:03:00.0"); +slash_hotplug_remove(hp, "0000:03:00.1"); +slash_hotplug_remove(hp, "0000:03:00.2"); + +slash_hotplug_toggle_sbr(hp, "0000:03:00.0"); /* assert 2 ms, settle 5 s */ + +usleep(5000000); /* wait for device re-init */ + +slash_hotplug_rescan(hp); + +slash_hotplug_hotplug(hp, "0000:03:00.0"); /* remove + rescan in one step */ +slash_hotplug_hotplug(hp, "0000:03:00.1"); +slash_hotplug_hotplug(hp, "0000:03:00.2"); + +slash_hotplug_close(hp); +``` + +For single-device systems, pass `NULL` instead of a BDF string. + +## Mock mode + +The control device API supports a mock mode for testing without +hardware. Pass `"@mock"` as the device path: + +```c +struct slash_ctldev *dev = slash_ctldev_open("@mock"); +``` + +Mock mode creates temporary backing files (in `$XDG_RUNTIME_DIR` or +`/tmp`) that simulate 64 MB BARs. All BAR reads and writes operate +on these files instead of real MMIO. + +## Tests + +```sh +cmake --build build +cd build && ctest +``` + +Tests run in mock mode and do not require hardware or the kernel module +to be loaded. + +## Project layout + +``` +libslash/ + include/slash/ + ctldev.h Public API — control device + qdma.h Public API — QDMA + hotplug.h Public API — hotplug + uapi/ + slash_interface.h User-kernel ABI (ctldev + QDMA ioctls) + slash_hotplug.h User-kernel ABI (hotplug ioctls) + src/ + ctldev.c Control device implementation + ctldev_mock.c Mock-mode BAR backing + qdma.c QDMA implementation + hotplug.c Hotplug implementation + examples/ + 01_bar/print_bar.c Enumerate and read/write BARs + 02_test/some_tb.c Multi-core HBM transfer testbench + tests/ + slash_mock_tests.c Unit tests (mock mode) +``` + +## License + +MIT. See the license header in `CMakeLists.txt` for the full text. + +The UAPI headers under `include/slash/uapi/` are dual-licensed +`GPL-2.0-only OR MIT` so they can be included by both the GPL kernel +module and the MIT userspace library without ambiguity. diff --git a/vrt/scripts/jtag_program.sh b/driver/libslash/cmake/slashConfig.cmake.in old mode 100755 new mode 100644 similarity index 86% rename from vrt/scripts/jtag_program.sh rename to driver/libslash/cmake/slashConfig.cmake.in index 066e5697..53bf2ed5 --- a/vrt/scripts/jtag_program.sh +++ b/driver/libslash/cmake/slashConfig.cmake.in @@ -1,5 +1,3 @@ -#!/bin/bash - # ################################################################################################## # The MIT License (MIT) # Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. @@ -20,12 +18,9 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## +@PACKAGE_INIT@ -if [ "$#" -ne 1 ]; then - echo "Usage: $0 " - exit 1 -fi - -program_file=$1 +# If you have dependencies, call find_dependency() here. +# e.g.: find_dependency(Threads) -vivado -nolog -nojournal -mode batch -source /usr/local/vrt/program.tcl -tclargs "$program_file" +include("${CMAKE_CURRENT_LIST_DIR}/slashTargets.cmake") diff --git a/examples/00_axilite/hls/Makefile b/driver/libslash/doc/Doxyfile similarity index 68% rename from examples/00_axilite/hls/Makefile rename to driver/libslash/doc/Doxyfile index 08aa7983..1e7291aa 100644 --- a/examples/00_axilite/hls/Makefile +++ b/driver/libslash/doc/Doxyfile @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) # Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,23 +18,26 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -TARGET=ip -DEVICE=xcv80-lsva4737-2MHP-e-S +# Doxyfile for libslash — generates XML for Sphinx/Breathe integration. -INCREMENT_BUILD_DIR=build_increment.$(DEVICE) -ACCUMULATE_BUILD_DIR=build_accumulate.$(DEVICE) +PROJECT_NAME = "libslash" +PROJECT_BRIEF = "Userspace C library for the SLASH kernel driver" -all: $(INCREMENT_BUILD_DIR) $(ACCUMULATE_BUILD_DIR) +OUTPUT_DIRECTORY = ./docs -$(INCREMENT_BUILD_DIR): - if [ ! -d "$(INCREMENT_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) increment; \ - fi +INPUT = ../include +RECURSIVE = YES +FILE_PATTERNS = *.h -$(ACCUMULATE_BUILD_DIR): - if [ ! -d "$(ACCUMULATE_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) accumulate; \ - fi +EXTRACT_ALL = YES +EXTRACT_STATIC = YES +OPTIMIZE_OUTPUT_FOR_C = YES -clean: - rm -rf $(INCREMENT_BUILD_DIR) $(ACCUMULATE_BUILD_DIR) vitis_hls.log \ No newline at end of file +MACRO_EXPANSION = YES +PREDEFINED = __inline__=inline \ + __attribute__(x)= + +GENERATE_HTML = NO +GENERATE_LATEX = NO +GENERATE_XML = YES +XML_OUTPUT = xml diff --git a/driver/libslash/include/slash/ctldev.h b/driver/libslash/include/slash/ctldev.h new file mode 100644 index 00000000..fbeaf7eb --- /dev/null +++ b/driver/libslash/include/slash/ctldev.h @@ -0,0 +1,212 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file ctldev.h + * + * Userspace API for the slash control device — device info, BAR info, + * and memory-mapped BAR access. + * + * A slash control device is a misc character device created for each + * FPGA PCI function (specifically PF2). Device nodes appear at + * /dev/slash_ctl0, /dev/slash_ctl1, etc. + * + * Three groups of functionality: + * 1. Device info — PCI identity (slash_device_info_read) + * 2. BAR info — BAR properties (slash_bar_info_read) + * 3. BAR file — mmap'd BAR access via dma-buf (slash_bar_file_open) + * + * BAR file access uses the kernel dma-buf framework. Callers must + * bracket MMIO accesses with the start/end sync helpers for cache + * coherency. + * + * Mock mode: passing "\@mock" as the path to slash_ctldev_open() creates + * a device backed by files on disk for testing without hardware. + * + * All functions follow POSIX conventions: pointer-returning functions + * return NULL on failure; int-returning functions return -1. errno is + * set in both cases. + */ + +#ifndef LIBSLASH_CTLDEV_H +#define LIBSLASH_CTLDEV_H + +#include "uapi/slash_interface.h" + +#include +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Handle to an open slash control device. + */ +struct slash_ctldev { + int fd; /**< File descriptor for the control character device. */ + bool mock; /**< True if this is a mock device (no real hardware). */ +}; + +/** + * @brief A memory-mapped BAR region. + * + * Obtained via slash_bar_file_open(). Callers access MMIO registers + * through \@map, bracketing accesses with the start/end sync helpers. + */ +struct slash_bar_file { + void *map; /**< Pointer to the mmap'd BAR region. */ + size_t len; /**< Size of the mapping in bytes. */ + int fd; /**< The dma-buf file descriptor backing the mapping. */ + bool mock; /**< True if backed by a mock file instead of real hardware. */ + /** + * Path to the backing file (mock mode only); NULL otherwise. + * Allocated by slash_bar_file_open() (mock path) and freed + * by slash_bar_file_close(). NULL in non-mock mode. + */ + char *mock_path; +}; + +/** + * @brief Open a slash control device. + * + * @param path Path to the character device node, or "\@mock" for mock mode. + * + * @return A heap-allocated handle on success, NULL on failure. + */ +struct slash_ctldev *slash_ctldev_open(const char *path); + +/** + * @brief Close the control device and free the handle. + * + * @param ctldev Handle from slash_ctldev_open(). NULL returns -1 / EINVAL. + * Must not be used after this call. + * + * @return 0 on success, -1 on failure. + */ +int slash_ctldev_close(struct slash_ctldev *ctldev); + + +/** + * @brief Read PCI identity information. + * + * @param ctldev Open control device handle. + * + * @return A heap-allocated slash_ioctl_device_info on success (caller + * frees with slash_device_info_free()), or NULL on failure. + */ +struct slash_ioctl_device_info *slash_device_info_read(struct slash_ctldev *ctldev); + +/** @brief Free a device info struct returned by slash_device_info_read(). */ +void slash_device_info_free(struct slash_ioctl_device_info *info); + +/** + * @brief Read BAR information for a specific BAR. + * + * @param ctldev Open control device handle. + * @param bar_number Which BAR to query (0–5). + * + * @return A heap-allocated slash_ioctl_bar_info on success (caller + * frees with slash_bar_info_free()), or NULL on failure. + */ +struct slash_ioctl_bar_info *slash_bar_info_read(struct slash_ctldev *ctldev, int bar_number); + +/** @brief Free a BAR info struct returned by slash_bar_info_read(). */ +void slash_bar_info_free(struct slash_ioctl_bar_info *ctldev); + +/** + * @brief Open and mmap a BAR region. + * + * @param ctldev Open control device handle. + * @param bar_number Which BAR to map (0–5). + * @param flags Only O_CLOEXEC is accepted. + * + * On success returns a handle whose \@map field points to the BAR + * (PROT_READ|PROT_WRITE, MAP_SHARED). The underlying fd is a dma-buf; + * callers must use the sync helpers to bracket accesses. + * + * @return NULL on failure. + */ +struct slash_bar_file *slash_bar_file_open(struct slash_ctldev *ctldev, int bar_number, int flags); + +/** + * @brief Unmap and close a BAR file. + * + * @param bar_file Handle from slash_bar_file_open(). NULL returns -1 / EINVAL. + * + * @return 0 on success, -1 if munmap or close fails. + * The handle is freed regardless. + */ +int slash_bar_file_close(struct slash_bar_file *bar_file); + +/** + * @brief Issue a DMA_BUF_IOCTL_SYNC on the BAR fd. + * + * @param bar_file Open BAR file handle. + * @param flags DMA_BUF_SYNC_* flags (START/END combined with READ/WRITE). + * + * Must be called to bracket MMIO accesses for cache coherency. + * No-op in mock mode. + * + * @return 0 on success, -1 on failure. + */ +static __inline__ int slash_bar_file_sync(struct slash_bar_file *bar_file, unsigned int flags) +{ + struct dma_buf_sync sync = { .flags = flags }; + + if (bar_file->mock) { + return 0; + } + + int ret = ioctl(bar_file->fd, DMA_BUF_IOCTL_SYNC, &sync); + if (ret == -1) { + fprintf(stderr, "slash_bar_file_sync: DMA_BUF_IOCTL_SYNC failed (flags=0x%x, fd=%d, errno=%d)\n", + flags, bar_file->fd, errno); + } + return ret; +} + +/** Acquire write access to the BAR mapping. Equivalent to slash_bar_file_sync(bar_file, DMA_BUF_SYNC_START | DMA_BUF_SYNC_WRITE). */ +static __inline__ int slash_bar_file_start_write(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_START | DMA_BUF_SYNC_WRITE); +} + +/** Release write access to the BAR mapping. Equivalent to slash_bar_file_sync(bar_file, DMA_BUF_SYNC_END | DMA_BUF_SYNC_WRITE). */ +static __inline__ int slash_bar_file_end_write(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_END | DMA_BUF_SYNC_WRITE); +} + +/** Acquire read access to the BAR mapping. Equivalent to slash_bar_file_sync(bar_file, DMA_BUF_SYNC_START | DMA_BUF_SYNC_READ). */ +static __inline__ int slash_bar_file_start_read(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_START | DMA_BUF_SYNC_READ); +} + +/** Release read access to the BAR mapping. Equivalent to slash_bar_file_sync(bar_file, DMA_BUF_SYNC_END | DMA_BUF_SYNC_READ). */ +static __inline__ int slash_bar_file_end_read(struct slash_bar_file *bar_file) +{ + return slash_bar_file_sync(bar_file, DMA_BUF_SYNC_END | DMA_BUF_SYNC_READ); +} + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#endif /* LIBSLASH_CTLDEV_H */ diff --git a/driver/libslash/include/slash/hotplug.h b/driver/libslash/include/slash/hotplug.h new file mode 100644 index 00000000..dae7f9f2 --- /dev/null +++ b/driver/libslash/include/slash/hotplug.h @@ -0,0 +1,122 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file hotplug.h + * + * Userspace API for managing PCIe hot-plug operations on slash devices. + * + * This module provides a thin wrapper around the slash hotplug character + * device (/dev/slash_hotplug). It handles opening/closing the device + * node and issuing the four hotplug ioctls defined in the UAPI header: + * rescan, remove, toggle SBR, and full hot-plug. + * + * All functions follow POSIX conventions: return 0 on success, -1 on + * failure with errno set. slash_hotplug_open() returns NULL on failure. + */ + +#ifndef LIBSLASH_HOTPLUG_H +#define LIBSLASH_HOTPLUG_H + +#include "uapi/slash_hotplug.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** Default path to the hotplug character device. */ +#define SLASH_HOTPLUG_DEFAULT_PATH "/dev/" SLASH_HOTPLUG_DEVICE_NAME + +/** + * @brief Opaque handle to the hotplug control device. + */ +struct slash_hotplug { + int fd; /**< File descriptor for the opened hotplug character device. */ +}; + +/** + * @brief Open the hotplug control device. + * + * @param path Path to the character device, or NULL to use + * SLASH_HOTPLUG_DEFAULT_PATH ("/dev/slash_hotplug"). + * + * @return A heap-allocated handle on success, or NULL on failure + * (errno is set by open() or calloc()). + */ +struct slash_hotplug *slash_hotplug_open(const char *path); /* NULL means SLASH_HOTPLUG_DEFAULT_PATH */ + +/** + * @brief Close the hotplug device and free the handle. + * + * @param hotplug Handle returned by slash_hotplug_open(). Must not be used + * after this call. Passing NULL sets errno to EINVAL and + * returns -1. + * + * @return 0 on success, -1 if close() fails (errno is preserved). + * The handle is freed regardless of whether close() succeeds. + */ +int slash_hotplug_close(struct slash_hotplug *hotplug); + +/** + * @brief Trigger a PCI bus rescan. + * + * @param hotplug Open hotplug handle. + * + * No device BDF is required; the kernel rescans the entire bus. + * + * @return 0 on success, -1 on failure. + */ +int slash_hotplug_rescan(struct slash_hotplug *hotplug); + +/** + * @brief Remove a device from the PCI bus. + * + * @param hotplug Open hotplug handle. + * @param bdf PCI BDF string (e.g. "0000:03:00.0"). Required. + * + * @return 0 on success, -1 on failure. + */ +int slash_hotplug_remove(struct slash_hotplug *hotplug, const char *bdf); + +/** + * @brief Assert and deassert a Secondary Bus Reset. + * + * @param hotplug Open hotplug handle. + * @param bdf PCI BDF string identifying the device (or its former + * location if already removed). Required. + * + * Toggles the SBR bit on the device's immediate upstream bridge + * (assert, 2 ms hold, deassert) and returns. The caller is + * responsible for waiting for the device to re-initialize before + * rescanning the bus. + * + * @return 0 on success, -1 on failure. + */ +int slash_hotplug_toggle_sbr(struct slash_hotplug *hotplug, const char *bdf); + +/** + * @brief Perform a full hot-plug cycle (remove + rescan). + * + * @param hotplug Open hotplug handle. + * @param bdf PCI BDF string. Required. + * + * @return 0 on success, -1 on failure. + */ +int slash_hotplug_hotplug(struct slash_hotplug *hotplug, const char *bdf); + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#endif /* LIBSLASH_HOTPLUG_H */ diff --git a/driver/libslash/include/slash/qdma.h b/driver/libslash/include/slash/qdma.h new file mode 100644 index 00000000..8d726544 --- /dev/null +++ b/driver/libslash/include/slash/qdma.h @@ -0,0 +1,159 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file qdma.h + * + * Userspace API for slash QDMA (Queue-based DMA) devices. + * + * A QDMA device is a separate misc character device created for PF1, + * while the control device (ctldev) is created for PF2. Each PCI + * function gets at most one of each. Device nodes appear at + * /dev/slash_qdma_ctl0, /dev/slash_qdma_ctl1, etc. + * + * Queue pair lifecycle: + * 1. slash_qdma_open() — open the QDMA device + * 2. slash_qdma_qpair_add() — create a queue pair (returns assigned qid) + * 3. slash_qdma_qpair_start() — activate for transfers + * 4. slash_qdma_qpair_get_fd() — obtain fd for data transfer + * 5. slash_qdma_qpair_stop() — deactivate + * 6. slash_qdma_qpair_del() — destroy + * 7. slash_qdma_close() — close the device + * + * The fd from qpair_get_fd() supports read() for C2H (card-to-host) + * and write() for H2C (host-to-card) DMA transfers. Positional I/O + * via lseek()/pread()/pwrite() is also supported. splice(), mmap(), + * and poll() are not available. + * + * Error conventions: int-returning functions return -1 with errno set. + * Pointer-returning functions return NULL with errno set. + */ + +#ifndef LIBSLASH_QDMA_H +#define LIBSLASH_QDMA_H + +#include "uapi/slash_interface.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Handle to an open QDMA device. + * + * \@priv is NULL for real hardware handles. When slash_qdma_open() is + * called with "\@mock", it points to an internal slash_qdma_mock context; + * callers should treat it as opaque. + */ +struct slash_qdma { + int fd; /**< File descriptor for the QDMA character device (-1 in mock mode). */ + void *priv; /**< Opaque mock context, or NULL for real hardware. */ +}; + +/** + * @brief Open a QDMA device. + * + * @param path Path to the character device node. NULL returns NULL/EINVAL. + * + * @return Heap-allocated handle on success, NULL on failure. + */ +struct slash_qdma *slash_qdma_open(const char *path); + +/** + * @brief Close a QDMA device and free the handle. + * + * @param qdma Handle from slash_qdma_open(), or NULL (returns -1/EINVAL). + * + * @return 0 on success, -1 on failure. + */ +int slash_qdma_close(struct slash_qdma *qdma); + +/** + * @brief Read QDMA device capabilities. + * + * @param qdma Open QDMA handle. + * @param info Caller-allocated struct, filled in on success. + * + * @return 0 on success, -1 on failure. + */ +int slash_qdma_info_read(struct slash_qdma *qdma, struct slash_qdma_info *info); + +/** + * @brief Create a new queue pair. + * + * @param qdma Open QDMA handle. + * @param req In/out — caller sets configuration fields, kernel fills in + * the assigned queue id (and possibly other output fields). + * + * @return 0 on success, -1 on failure. + */ +int slash_qdma_qpair_add(struct slash_qdma *qdma, + struct slash_qdma_qpair_add *req); + +/** + * @brief Activate a queue pair for transfers. + * + * @param qdma Open QDMA handle. + * @param qid Queue pair id from slash_qdma_qpair_add(). + * + * @return 0 on success, -1 on failure. + */ +int slash_qdma_qpair_start(struct slash_qdma *qdma, uint32_t qid); + +/** + * @brief Deactivate a queue pair. + * + * @param qdma Open QDMA handle. + * @param qid Queue pair id. + * + * @return 0 on success, -1 on failure. + */ +int slash_qdma_qpair_stop(struct slash_qdma *qdma, uint32_t qid); + +/** + * @brief Destroy a queue pair. + * + * @param qdma Open QDMA handle. + * @param qid Queue pair id. + * + * The kernel implicitly stops the queue if it is still running, so a + * separate stop call is not required before del. + * + * @return 0 on success, -1 on failure. + */ +int slash_qdma_qpair_del(struct slash_qdma *qdma, uint32_t qid); + +/** + * @brief Obtain a file descriptor for data transfer. + * + * @param qdma Open QDMA handle. + * @param qid Queue pair id (must be started). + * @param flags Only O_CLOEXEC is accepted; the kernel returns -EINVAL for + * any other bits. + * + * The returned fd supports read() (C2H) and write() (H2C). Positional + * I/O via lseek()/pread()/pwrite() is also available. + * + * @return Non-negative fd on success, -1 on failure. + */ +int slash_qdma_qpair_get_fd(struct slash_qdma *qdma, uint32_t qid, int flags); + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#endif /* LIBSLASH_QDMA_H */ + diff --git a/driver/libslash/include/slash/uapi/slash_hotplug.h b/driver/libslash/include/slash/uapi/slash_hotplug.h new file mode 100644 index 00000000..2d79f616 --- /dev/null +++ b/driver/libslash/include/slash/uapi/slash_hotplug.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * This file is dual-licensed: you may select either the GNU General Public + * License version 2 (GPL-2.0-only) or the MIT License. See the LICENSE + * files in the repository root for the full text of each license. + */ + +/** + * @file slash_hotplug.h + * + * User-kernel ABI for the slash hotplug control device. + * + * The slash hotplug subsystem manages the PCIe-level lifecycle of FPGA + * devices: removing them from the PCI bus, triggering Secondary Bus + * Resets (SBR), rescanning, and performing full hot-plug sequences. + * + * This is essential for FPGA reconfiguration workflows where the device + * identity or BAR layout may change after loading a new bitstream, and + * the kernel must re-enumerate the device. + * + * All communication goes through a dedicated character device named + * SLASH_HOTPLUG_DEVICE_NAME ("/dev/slash_hotplug"). + * + * A typical FPGA reconfiguration flow uses these operations in order: + * + * 1. REMOVE all PCI functions (PF0, PF1, PF2 …) from the bus. + * 2. TOGGLE_SBR on the root-port to reset the device. + * 3. Sleep (~5 s) to let the device re-initialise. + * 4. RESCAN the PCI bus to discover the new configuration. + * 5. HOTPLUG each function to complete re-enumeration. + * + * For a simple device teardown/re-add (no reset or bitstream change), + * REMOVE → RESCAN is sufficient. + */ + +#ifndef SLASH_HOTPLUG_UAPI_H +#define SLASH_HOTPLUG_UAPI_H + +#include + +#ifdef __KERNEL__ +#include +#else +#include +#endif /* __KERNEL__ */ + +/** Name of the hotplug control character device (appears under /dev/). */ +#define SLASH_HOTPLUG_DEVICE_NAME "slash_hotplug" + +/** Maximum length (including NUL) of a PCI BDF string in hotplug requests. */ +#define SLASH_HOTPLUG_BDF_LEN 32 + +/** + * @brief Identify a device for a hotplug operation. + * + * If \@bdf is empty and multiple devices are tracked, the kernel + * returns -EOPNOTSUPP; the caller must specify the BDF explicitly. + * -ENODEV is returned if no devices are tracked at all. + */ +struct slash_hotplug_device_request { + __u32 size; /**< Struct size for ABI versioning. */ + /** + * PCI Bus/Device/Function string (e.g. "0000:03:00.0"), NUL-terminated. + * If the string is empty, the kernel targets the only currently + * tracked device (convenient for single-device systems). + */ + char bdf[SLASH_HOTPLUG_BDF_LEN]; +}; + +/** ioctl magic number for hotplug commands (uses 'w', distinct from 'v'). */ +#define SLASH_HOTPLUG_IOCTL_MAGIC 'w' + +/** + * Rescan the PCI bus to discover new or reconfigured devices. + * Takes no per-device argument. + */ +#define SLASH_HOTPLUG_IOCTL_RESCAN _IO(SLASH_HOTPLUG_IOCTL_MAGIC, 0x30) + +/** + * Remove a device from the PCI bus. + * The device is identified by the \@bdf in the request struct. + */ +#define SLASH_HOTPLUG_IOCTL_REMOVE _IOW(SLASH_HOTPLUG_IOCTL_MAGIC, 0x31, struct slash_hotplug_device_request) + +/** + * Toggle a Secondary Bus Reset (SBR) on the device's upstream port. + * + * A single ioctl call performs the full SBR sequence on the upstream + * bridge. The kernel first attempts pci_bridge_secondary_bus_reset() + * (which saves/restores bridge config space), falling back to a manual + * PCI_BRIDGE_CONTROL register toggle if the kernel API is unavailable. + * A 1000 ms post-SBR link training delay is included before the ioctl + * returns. The caller should wait an additional ~10 s for full FPGA + * re-initialisation before rescanning. + */ +#define SLASH_HOTPLUG_IOCTL_TOGGLE_SBR _IOW(SLASH_HOTPLUG_IOCTL_MAGIC, 0x32, struct slash_hotplug_device_request) + +/** + * Perform a full hot-plug cycle on the device. + * + * A "full hot-plug" performs REMOVE then RESCAN in one atomic step: + * the kernel calls pci_stop_and_remove_bus_device() followed by + * pci_rescan_bus() on the root-port's subordinate bus. It does + * **not** include a Secondary Bus Reset; use TOGGLE_SBR separately + * before HOTPLUG if a reset is required. + */ +#define SLASH_HOTPLUG_IOCTL_HOTPLUG _IOW(SLASH_HOTPLUG_IOCTL_MAGIC, 0x33, struct slash_hotplug_device_request) + +#endif /* SLASH_HOTPLUG_UAPI_H */ diff --git a/driver/libslash/include/slash/uapi/slash_interface.h b/driver/libslash/include/slash/uapi/slash_interface.h new file mode 100644 index 00000000..588aed04 --- /dev/null +++ b/driver/libslash/include/slash/uapi/slash_interface.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * Copyright (C) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * This file is dual-licensed: you may select either the GNU General Public + * License version 2 (GPL-2.0-only) or the MIT License. See the LICENSE + * files in the repository root for the full text of each license. + */ + +/** + * @file slash_interface.h + * + * User-kernel ABI for the slash control device and QDMA subsystem. + * + * This header defines the ioctl structures and command numbers used by + * libslash to communicate with the slash kernel module. It covers two + * areas of functionality: + * + * 1. **Control device operations** — querying PCIe BAR information, + * obtaining file descriptors for BAR mappings, and retrieving + * device identity (BDF, vendor/device IDs). + * + * 2. **QDMA operations** — querying QDMA capabilities, adding/ + * starting/stopping/deleting queue pairs, and obtaining file + * descriptors for queue pair I/O. + * + * All ioctl structs carry a leading `size` field for versioning: the + * caller sets `size = sizeof(struct ...)` so the kernel can detect + * older or newer userspace and handle compatibility. + * + * This file is shared between kernel and userspace (UAPI) and must + * remain compatible with both build environments. + */ + + +#ifndef SLASH_UAPI_INTERFACE_H +#define SLASH_UAPI_INTERFACE_H + +#include + +#ifdef __KERNEL__ +#include +#else +#include +#endif /* __KERNEL__ */ + +/** + * ioctl number allocation + * + * Numbers are chosen per the kernel's ioctl registry: + * https://www.kernel.org/doc/Documentation/userspace-api/ioctl/ioctl-number.rst + * + * The following codes are currently free: + * Code: 'v' + * Seq#: 30-BF + * + * We will aim to be good citizens and use a small range like 'v' 30-4F, + * which is 32 ioctls. However, both these codes and the range used is + * subject to change for future versions of the driver. + */ + +/* ───────────────────────────────────────────────────────────────────── + * Control device ioctls — BAR and device info + * ───────────────────────────────────────────────────────────────────── */ + +/** + * @brief Query information about a single PCIe BAR. + */ +struct slash_ioctl_bar_info { + /** + * Struct size for ABI versioning. Caller must set to + * sizeof(struct slash_ioctl_bar_info). + */ + __u32 size; + + /* Userspace to kernel */ + __u8 bar_number; /**< [in] Which BAR to query (0–5). */ + + /* Kernel to userspace */ + __u8 usable; /**< [out] Non-zero if the BAR is present and usable. */ + __u8 in_use; /**< [out] Non-zero if the BAR is currently mapped / claimed. */ + __u8 pad0; /**< Padding for natural alignment. */ + + __u64 start_address; /**< [out] Physical / bus start address of the BAR. */ + __u64 length; /**< [out] Size of the BAR region in bytes. */ +}; + +/** + * @brief Obtain a file descriptor for a BAR. + * + * Userspace sends the desired \@bar_number and \@flags; the kernel returns + * a new fd (via ioctl return convention) and fills in \@length. + * + * The actual fd is returned as the return value to the ioctl. + */ +struct slash_ioctl_bar_fd_request { + __u32 size; /**< Struct size for ABI versioning. */ + + /* Userspace to kernel */ + __u8 bar_number; /**< [in] Which BAR to open. */ + __u8 pad0; /**< Padding. */ + __u16 pad1; /**< Padding. */ + + __u32 flags; /**< [in] File descriptor flags. Only O_CLOEXEC is honoured. */ + + /* Kernel to userspace */ + __u64 length; /**< [out] Size of the BAR region backing the returned fd. */ +}; + +/** Maximum length (including NUL) of a PCI BDF string ("DDDD:BB:DD.F"). */ +#define SLASH_PCI_BDF_LEN 32 + +/** + * @brief Retrieve PCI identity of the device. + */ +struct slash_ioctl_device_info { + __u32 size; /**< Struct size for ABI versioning. */ + + /* Kernel to userspace */ + char bdf[SLASH_PCI_BDF_LEN]; /**< [out] PCI Bus/Device/Function string, NUL-terminated. */ + __u16 vendor_id; /**< [out] PCI vendor ID. */ + __u16 device_id; /**< [out] PCI device ID. */ + __u16 subsystem_vendor_id; /**< [out] PCI subsystem vendor ID. */ + __u16 subsystem_device_id; /**< [out] PCI subsystem device ID. */ +}; + +/** Query BAR properties. Fills the kernel-to-userspace fields of slash_ioctl_bar_info. */ +#define SLASH_CTLDEV_IOCTL_GET_BAR_INFO _IOWR('v', 0x30, struct slash_ioctl_bar_info) + +/** Obtain a mappable fd for a BAR region. */ +#define SLASH_CTLDEV_IOCTL_GET_BAR_FD _IOWR('v', 0x31, struct slash_ioctl_bar_fd_request) + +/** Retrieve PCI identity strings and IDs for the device. */ +#define SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO _IOWR('v', 0x32, struct slash_ioctl_device_info) + + +/* ───────────────────────────────────────────────────────────────────── + * QDMA ioctls — DMA queue management + * ───────────────────────────────────────────────────────────────────── */ + +/** + * @brief Query QDMA subsystem capabilities. + * + * \@caps is reserved for future use; the kernel currently sets it to 0. + */ +struct slash_qdma_info { + __u32 size; /**< Struct size for ABI versioning. */ + + /* Kernel to userspace */ + __u32 qsets_max; /**< [out] Maximum number of queue sets the hardware supports. */ + __u32 msix_qvecs; /**< [out] Number of MSI-X vectors available for queues. */ + __u32 vf_max; /**< [out] Maximum number of virtual functions. */ + __u32 caps; /**< [out] Capability bitmask. */ +}; + +/** + * @brief Add (allocate) a new QDMA queue pair. + * + * \@mode must be one of: + * - QDMA_Q_MODE_MM (0) — AXI Memory Mapped mode. + * - QDMA_Q_MODE_ST (1) — AXI Streaming mode. + * + * \@dir_mask selects which directions to enable: + * - bit 0 (0x1) — H2C (Host-to-Card). + * - bit 1 (0x2) — C2H (Card-to-Host). + * - bit 2 (0x4) — CMPT (Completion queue). + * + * The ring size fields are hardware CSR table indices (valid range + * 0–15), not byte or descriptor counts. Each index selects a + * pre-configured descriptor-ring depth from the global CSR ring-size + * table (e.g. index 0 → 2049 descriptors, index 15 → 16385). + */ +struct slash_qdma_qpair_add { + __u32 size; /**< Struct size for ABI versioning. */ + + /* Userspace to kernel */ + __u32 mode; /**< [in] Queue operating mode. */ + __u32 dir_mask; /**< [in] Direction bitmask — which directions to enable. */ + + __u32 h2c_ring_sz; /**< [in] Host-to-card descriptor ring size. */ + __u32 c2h_ring_sz; /**< [in] Card-to-host descriptor ring size. */ + __u32 cmpt_ring_sz; /**< [in] Completion ring size. */ + + /* Kernel to userspace */ + __u32 qid; /**< [out] Kernel-assigned queue pair ID. */ +}; + +/** + * Queue pair lifecycle operations, used in slash_qdma_qpair_op::op. + * + * The expected lifecycle of a queue pair is: + * ADD → START → (I/O) → STOP → DEL + */ +enum { + SLASH_QDMA_QUEUE_OP_START, /**< Start (activate) the queue pair. */ + SLASH_QDMA_QUEUE_OP_STOP, /**< Stop (quiesce) the queue pair. */ + SLASH_QDMA_QUEUE_OP_DEL, /**< Delete (free) the queue pair. */ +}; + +/** + * @brief Perform a lifecycle operation on a queue pair. + */ +struct slash_qdma_qpair_op { + __u32 size; /**< Struct size for ABI versioning. */ + + /* Userspace to kernel */ + __u32 qid; /**< [in] Queue pair ID (as returned by slash_qdma_qpair_add). */ + __u32 op; /**< [in] One of the SLASH_QDMA_QUEUE_OP_* constants. */ +}; + +/** + * @brief Obtain a file descriptor for queue I/O. + * + * The returned fd can be used for read/write (or mmap) to transfer data + * through the queue pair. + * + * The fd is returned as the ioctl return value (same convention as + * the BAR fd ioctl). A single fd is returned per queue pair; + * read() on the fd performs C2H transfers and write() performs H2C + * transfers, using whichever directions were enabled in \@dir_mask + * when the queue pair was added. + */ +struct slash_qdma_qpair_fd_request { + __u32 size; /**< Struct size for ABI versioning. */ + + /* Userspace to kernel */ + __u32 qid; /**< [in] Queue pair ID. */ + __u32 flags; /**< [in] File descriptor flags. Only O_CLOEXEC is honoured. */ +}; + +/** Query QDMA subsystem capabilities. */ +#define SLASH_QDMA_IOCTL_INFO _IOWR('v', 0x50, struct slash_qdma_info) + +/** Allocate a new queue pair; returns assigned qid. */ +#define SLASH_QDMA_IOCTL_QPAIR_ADD _IOWR('v', 0x51, struct slash_qdma_qpair_add) + +/** Start, stop, or delete an existing queue pair. */ +#define SLASH_QDMA_IOCTL_Q_OP _IOWR('v', 0x52, struct slash_qdma_qpair_op) + +/** Obtain an I/O file descriptor for a queue pair. */ +#define SLASH_QDMA_IOCTL_QPAIR_GET_FD _IOWR('v', 0x53, struct slash_qdma_qpair_fd_request) + +#endif diff --git a/submodules/v80-vitis-flow/CMakeLists.txt b/driver/libslash/src/CMakeLists.txt similarity index 61% rename from submodules/v80-vitis-flow/CMakeLists.txt rename to driver/libslash/src/CMakeLists.txt index 562c0d70..5c8abf5b 100644 --- a/submodules/v80-vitis-flow/CMakeLists.txt +++ b/driver/libslash/src/CMakeLists.txt @@ -18,17 +18,32 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(v80++-linker) +# Library sources (list explicitly; avoid GLOB for reproducible builds) +add_library(slash + ${CMAKE_CURRENT_SOURCE_DIR}/ctldev.c + ${CMAKE_CURRENT_SOURCE_DIR}/ctldev_mock.c + ${CMAKE_CURRENT_SOURCE_DIR}/hotplug.c + ${CMAKE_CURRENT_SOURCE_DIR}/qdma.c + ${CMAKE_CURRENT_SOURCE_DIR}/qdma_mock.c +) -set(CMAKE_CXX_STANDARD 20) -set(CMAKE_CXX_STANDARD_REQUIRED ON) - -include_directories(${CMAKE_SOURCE_DIR}/include/xml_parser /usr/include/libxml2 /usr/include/jsoncpp ${CMAKE_SOURCE_DIR}/include/bd_builder/ ${CMAKE_SOURCE_DIR}/include/arg_parser/ ${CMAKE_SOURCE_DIR}/include/ ${CMAKE_SOURCE_DIR}/include/utils/ ${CMAKE_SOURCE_DIR}/include/sw_emu/) - -file(GLOB SOURCES ${CMAKE_SOURCE_DIR}/src/*.cpp ${CMAKE_SOURCE_DIR}/src/xml_parser/*.cpp ${CMAKE_SOURCE_DIR}/src/arg_parser/*.cpp ${CMAKE_SOURCE_DIR}/src/bd_builder/*.cpp ${CMAKE_SOURCE_DIR}/src/utils/*.cpp ${CMAKE_SOURCE_DIR}/src/sw_emu/*.cpp) - -add_executable(${PROJECT_NAME} ${SOURCES}) -target_link_libraries(${PROJECT_NAME} xml2 jsoncpp zmq) +# Provide an alias target with namespace (nice for internal use too) +add_library(slash::slash ALIAS slash) +# C standard / properties +set_target_properties(slash PROPERTIES + C_STANDARD 90 + C_STANDARD_REQUIRED YES + C_EXTENSIONS NO + VERSION ${PROJECT_VERSION} + SOVERSION ${PROJECT_VERSION_MAJOR} +) +# Public include dir (for consumers) and private include dir (for .c / private headers) +target_include_directories(slash + PUBLIC + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/driver/libslash/src/ctldev.c b/driver/libslash/src/ctldev.c new file mode 100644 index 00000000..536ba2ab --- /dev/null +++ b/driver/libslash/src/ctldev.c @@ -0,0 +1,269 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file ctldev.c + * + * Implementation of the slash control device wrapper. + * + * Each public function either delegates to the mock implementation + * (ctldev_mock.h) or issues a single ioctl/syscall against the real + * character device. No caching or retry logic. + * + * Error handling follows POSIX conventions: -1 or NULL on failure + * with errno set. + */ + + +#define _GNU_SOURCE + +#include + +#include "ctldev_mock.h" + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +struct slash_ctldev *slash_ctldev_open(const char *path) +{ + struct slash_ctldev *ctldev; + + if (path == NULL) { + errno = EINVAL; + return NULL; + } + + if (strcmp(path, "@mock") == 0) { + return slash_ctldev_mock_open(); + } + + ctldev = calloc(1, sizeof(*ctldev)); + if (ctldev == NULL) { + return NULL; + } + + ctldev->fd = open(path, O_RDWR); + if (ctldev->fd < 0) { + goto err_free_ctldev; + } + + ctldev->mock = false; + + return ctldev; + +err_free_ctldev: + free(ctldev); + + return NULL; +} + +int slash_ctldev_close(struct slash_ctldev *ctldev) +{ + int ret; + + if (ctldev == NULL) { + errno = EINVAL; + return -1; + } + + if (ctldev->mock) { + return slash_ctldev_mock_close(ctldev); + } + + ret = 0; + if (ctldev->fd >= 0 && close(ctldev->fd) != 0) { + ret = -1; + } + + /* Free unconditionally — the handle is invalid after this call. */ + free(ctldev); + + return ret; +} + +struct slash_ioctl_device_info *slash_device_info_read(struct slash_ctldev *ctldev) +{ + int ret; + struct slash_ioctl_device_info *info; + + if (ctldev == NULL) { + errno = EINVAL; + return NULL; + } + + if (ctldev->mock) { + return slash_device_info_mock_read(ctldev); + } + + info = calloc(1, sizeof(*info)); + if (info == NULL) { + return NULL; + } + + /* Set size so the kernel can version-check the struct. */ + info->size = sizeof(*info); + + ret = ioctl(ctldev->fd, SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO, info); + if (ret < 0) { + goto err_free_info; + } + + return info; + +err_free_info: + free(info); + + return NULL; +} + +void slash_device_info_free(struct slash_ioctl_device_info *info) +{ + free(info); +} + +struct slash_ioctl_bar_info *slash_bar_info_read(struct slash_ctldev *ctldev, int bar_number) +{ + int ret; + struct slash_ioctl_bar_info *bar_info; + + if (ctldev == NULL) { + errno = EINVAL; + return NULL; + } + + if (ctldev->mock) { + return slash_bar_info_mock_read(ctldev, bar_number); + } + + bar_info = calloc(1, sizeof(*bar_info)); + if (bar_info == NULL) { + return NULL; + } + + bar_info->size = sizeof(*bar_info); + bar_info->bar_number = bar_number; + + ret = ioctl(ctldev->fd, SLASH_CTLDEV_IOCTL_GET_BAR_INFO, bar_info); + if (ret < 0) { + goto err_free_bar_info; + } + + return bar_info; + +err_free_bar_info: + free(bar_info); + + return NULL; +} + +struct slash_bar_file *slash_bar_file_open(struct slash_ctldev *ctldev, int bar_number, int flags) +{ + struct slash_ioctl_bar_fd_request req = { + .size = sizeof(req), + + .bar_number = bar_number, + .flags = flags, + }; + + struct slash_bar_file *bar_file; + + if (ctldev == NULL) { + errno = EINVAL; + return NULL; + } + + if (ctldev->mock) { + return slash_bar_file_mock_open(ctldev, bar_number, flags); + } + + bar_file = calloc(1, sizeof(*bar_file)); + if (bar_file == NULL) { + return NULL; + } + + /* The ioctl returns the dma-buf fd directly as its return value. */ + bar_file->fd = ioctl(ctldev->fd, SLASH_CTLDEV_IOCTL_GET_BAR_FD, &req); + if (bar_file->fd < 0) { + goto err_free_bar_file; + } + + /* The kernel filled in req.length with the BAR size. */ + bar_file->len = (size_t) req.length; + + /* + * Map the entire BAR into our address space. The dma-buf fd + * backs this mapping — the kernel's slash_bar_dmabuf_mmap() + * installs a fault handler that maps BAR pages via + * vmf_insert_pfn() on first access. Callers must bracket + * accesses with the DMA_BUF_IOCTL_SYNC start/end helpers + * (see the inline functions in ctldev.h). + */ + bar_file->map = mmap(NULL, bar_file->len, PROT_READ | PROT_WRITE, MAP_SHARED, bar_file->fd, 0); + if (bar_file->map == MAP_FAILED) { + goto err_close_fd; + } + + bar_file->mock = false; + + return bar_file; + +err_close_fd: + (void) close(bar_file->fd); + +err_free_bar_file: + free(bar_file); + + return NULL; +} + +int slash_bar_file_close(struct slash_bar_file *bar_file) +{ + int ret = 0; + + if (bar_file == NULL) { + errno = EINVAL; + return -1; + } + + if (bar_file->mock) { + return slash_bar_file_mock_close(bar_file); + } + + if (munmap(bar_file->map, bar_file->len) != 0) { + ret = -1; + } + + if (close(bar_file->fd) != 0) { + ret = -1; + } + + /* Free unconditionally — the handle is invalid after this call. */ + free(bar_file); + + return ret; +} + +void slash_bar_info_free(struct slash_ioctl_bar_info *bar_info) +{ + free(bar_info); +} diff --git a/driver/libslash/src/ctldev_mock.c b/driver/libslash/src/ctldev_mock.c new file mode 100644 index 00000000..12158b67 --- /dev/null +++ b/driver/libslash/src/ctldev_mock.c @@ -0,0 +1,303 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file ctldev_mock.c + * @brief Mock control-device implementation backed by temporary files. + */ + +#define _GNU_SOURCE + +#include "ctldev_mock.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLASH_MOCK_BAR_SIZE (64ULL * 1024ULL * 1024ULL) + +/** @brief Generate a random 64-bit value, falling back to time/pid XOR. */ +static uint64_t slash_mock_random(void) +{ + uint64_t value; + ssize_t ret; + ret = getrandom(&value, sizeof(value), 0); + + if (ret != (ssize_t) sizeof(value)) { + struct timespec ts; + + if (clock_gettime(CLOCK_REALTIME, &ts) == 0) { + value = ((uint64_t) ts.tv_sec << 32) ^ (uint64_t) ts.tv_nsec; + } else { + value = (uint64_t) time(NULL); + } + + value ^= (uint64_t) (uintptr_t) &value; + value ^= (uint64_t) getpid(); + } + + return value; +} + +/** @brief Create a temporary file for mock BAR storage in XDG_RUNTIME_DIR or /tmp. */ +static int slash_mock_create_backing_file(char **path_out) +{ + const char *env_dir = getenv("XDG_RUNTIME_DIR"); + const char *dir_path = {0}; + int last_errno = EIO; + size_t i; + int attempt; + + if (env_dir != NULL && env_dir[0] != '\0') { + dir_path = env_dir; + } else { + dir_path = "/tmp"; + } + + for (attempt = 0; attempt < 32; ++attempt) { + uint64_t rnd; + int needed; + size_t buf_len; + char *path; + int fd; + + rnd = slash_mock_random(); + needed = snprintf(NULL, 0, "%s/%s%llu", dir_path, "slash.mock.", (unsigned long long) rnd); + if (needed < 0) { + last_errno = EINVAL; + continue; + } + + if ((size_t) needed >= PATH_MAX) { + last_errno = ENAMETOOLONG; + continue; + } + + buf_len = (size_t) needed + 1; + path = malloc(buf_len); + if (path == NULL) { + last_errno = ENOMEM; + errno = ENOMEM; + return -1; + } + + (void) snprintf(path, buf_len, "%s/slash.mock.%llu", dir_path, (unsigned long long) rnd); + + fd = open(path, O_RDWR | O_CREAT | O_EXCL | O_CLOEXEC, 0600); + if (fd >= 0) { + *path_out = path; + return fd; + } + + last_errno = errno; + free(path); + + if (errno == EEXIST) { + continue; + } + + if (errno == ENOENT || errno == EACCES) { + break; + } + + return -1; + } + + errno = last_errno; + return -1; +} + +struct slash_ctldev *slash_ctldev_mock_open(void) +{ + struct slash_ctldev *ctldev; + + ctldev = calloc(1, sizeof(*ctldev)); + if (ctldev == NULL) { + return NULL; + } + + ctldev->fd = -1; + ctldev->mock = true; + + return ctldev; +} + +int slash_ctldev_mock_close(struct slash_ctldev *ctldev) +{ + if (ctldev == NULL) { + errno = EINVAL; + return -1; + } + + free(ctldev); + + return 0; +} + +struct slash_ioctl_device_info *slash_device_info_mock_read(struct slash_ctldev *ctldev) +{ + struct slash_ioctl_device_info *info; + + if (ctldev == NULL || !ctldev->mock) { + errno = EINVAL; + return NULL; + } + + info = calloc(1, sizeof(*info)); + if (info == NULL) { + return NULL; + } + + info->size = sizeof(*info); + (void) snprintf(info->bdf, sizeof(info->bdf), "0000:00:00.0"); + + return info; +} + +struct slash_ioctl_bar_info *slash_bar_info_mock_read(struct slash_ctldev *ctldev, int bar_number) +{ + struct slash_ioctl_bar_info *bar_info; + + if (ctldev == NULL || !ctldev->mock) { + errno = EINVAL; + return NULL; + } + + bar_info = calloc(1, sizeof(*bar_info)); + if (bar_info == NULL) { + return NULL; + } + + bar_info->size = sizeof(*bar_info); + bar_info->bar_number = (uint8_t) bar_number; + + if (bar_number == 0) { + bar_info->usable = 1; + bar_info->in_use = 0; + bar_info->start_address = 0; + bar_info->length = SLASH_MOCK_BAR_SIZE; + } else { + bar_info->usable = 0; + bar_info->in_use = 0; + bar_info->start_address = 0; + bar_info->length = 0; + } + + return bar_info; +} + +void slash_bar_info_mock_free(struct slash_ioctl_bar_info *bar_info) +{ + free(bar_info); +} + +struct slash_bar_file *slash_bar_file_mock_open(struct slash_ctldev *ctldev, int bar_number, int flags) +{ + (void) flags; + + struct slash_bar_file *bar_file; + char *path; + int fd; + void *map; + + if (ctldev == NULL || !ctldev->mock) { + errno = EINVAL; + return NULL; + } + + if (bar_number != 0) { + errno = ENODEV; + return NULL; + } + + bar_file = calloc(1, sizeof(*bar_file)); + if (bar_file == NULL) { + return NULL; + } + + path = NULL; + fd = slash_mock_create_backing_file(&path); + if (fd < 0) { + free(bar_file); + return NULL; + } + + if (ftruncate(fd, (off_t) SLASH_MOCK_BAR_SIZE) != 0) { + (void) unlink(path); + free(path); + (void) close(fd); + free(bar_file); + return NULL; + } + + map = mmap(NULL, (size_t) SLASH_MOCK_BAR_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if (map == MAP_FAILED) { + (void) unlink(path); + free(path); + (void) close(fd); + free(bar_file); + return NULL; + } + + bar_file->fd = fd; + bar_file->len = (size_t) SLASH_MOCK_BAR_SIZE; + bar_file->map = map; + bar_file->mock = true; + bar_file->mock_path = path; + + return bar_file; +} + +int slash_bar_file_mock_close(struct slash_bar_file *bar_file) +{ + int ret = 0; + + if (bar_file == NULL) { + errno = EINVAL; + return -1; + } + + if (bar_file->map != NULL && bar_file->len != 0) { + if (munmap(bar_file->map, bar_file->len) != 0) { + ret = -1; + } + } + + if (bar_file->fd >= 0) { + if (close(bar_file->fd) != 0) { + ret = -1; + } + } + + if (bar_file->mock_path != NULL) { + if (unlink(bar_file->mock_path) != 0 && errno != ENOENT) { + ret = -1; + } + free(bar_file->mock_path); + } + + free(bar_file); + + return ret; +} diff --git a/driver/libslash/src/ctldev_mock.h b/driver/libslash/src/ctldev_mock.h new file mode 100644 index 00000000..48acd056 --- /dev/null +++ b/driver/libslash/src/ctldev_mock.h @@ -0,0 +1,75 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file ctldev_mock.h + * @brief Mock control-device implementation for testing without hardware. + */ + +#ifndef LIBSLASH_CTLDEV_MOCK_H +#define LIBSLASH_CTLDEV_MOCK_H + +#include + +/** + * @brief Open a mock control device (no hardware required). + * @return Allocated mock handle, or NULL on failure. + */ +struct slash_ctldev *slash_ctldev_mock_open(void); + +/** + * @brief Close a mock control device and free its handle. + * @param ctldev Handle returned by slash_ctldev_mock_open(). + * @return 0 on success, -1 on failure. + */ +int slash_ctldev_mock_close(struct slash_ctldev *ctldev); + +/** + * @brief Return mock device info with BDF 0000:00:00.0. + * @param ctldev Mock control device handle. + * @return Allocated device info, or NULL on failure. Free with slash_device_info_free(). + */ +struct slash_ioctl_device_info *slash_device_info_mock_read(struct slash_ctldev *ctldev); + +/** + * @brief Return mock BAR info. BAR 0 is usable (64 MB); others are unusable. + * @param ctldev Mock control device handle. + * @param bar_number BAR index (0-5). + * @return Allocated BAR info, or NULL on failure. Free with slash_bar_info_mock_free(). + */ +struct slash_ioctl_bar_info *slash_bar_info_mock_read(struct slash_ctldev *ctldev, int bar_number); + +/** + * @brief Free a BAR info struct returned by slash_bar_info_mock_read(). + * @param ctldev BAR info to free. + */ +void slash_bar_info_mock_free(struct slash_ioctl_bar_info *ctldev); + +/** + * @brief Open mock BAR 0 backed by a temporary file (64 MB mmap). + * @param ctldev Mock control device handle. + * @param bar_number BAR index (only 0 is supported). + * @param flags Open flags (e.g. O_CLOEXEC). + * @return Allocated BAR file with mmap, or NULL on failure. + */ +struct slash_bar_file *slash_bar_file_mock_open(struct slash_ctldev *ctldev, int bar_number, int flags); + +/** + * @brief Close mock BAR file, unmap memory, and unlink the backing file. + * @param bar_file BAR file returned by slash_bar_file_mock_open(). + * @return 0 on success, -1 on failure. + */ +int slash_bar_file_mock_close(struct slash_bar_file *bar_file); + +#endif /* LIBSLASH_CTLDEV_MOCK_H */ diff --git a/driver/libslash/src/hotplug.c b/driver/libslash/src/hotplug.c new file mode 100644 index 00000000..03495477 --- /dev/null +++ b/driver/libslash/src/hotplug.c @@ -0,0 +1,184 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file hotplug.c + * + * Implementation of the libslash hotplug wrapper. + * + * This file provides the userspace side of the slash hotplug interface. + * Each public function maps directly to a single ioctl on the hotplug + * character device — there is no caching, batching, or retry logic. + * + * Error handling follows POSIX conventions throughout: functions return + * -1 and set errno. errno values originate either from this library + * (EINVAL for NULL handles or oversized BDF strings) or from the + * underlying syscalls (open, close, ioctl). + */ + +#define _GNU_SOURCE + +#include + +#include +#include +#include +#include +#include + +#include + +/** + * slash_hotplug_ioctl_without_request() — Issue an ioctl that takes no + * argument struct (used by RESCAN). + * + * @hotplug: Open hotplug handle. Must not be NULL. + * @op: ioctl request number. + * + * Returns 0 on success, -1 on failure (errno set by ioctl or EINVAL). + */ +static int slash_hotplug_ioctl_without_request(struct slash_hotplug *hotplug, unsigned long op) +{ + int ret; + + if (hotplug == NULL) { + errno = EINVAL; + return -1; + } + + ret = ioctl(hotplug->fd, op); + if (ret < 0) { + return -1; + } + + return 0; +} + +/** + * slash_hotplug_ioctl_with_request() — Issue an ioctl that carries a + * slash_hotplug_device_request identifying a device by BDF. + * + * @hotplug: Open hotplug handle. Must not be NULL. + * @op: ioctl request number. + * @bdf: PCI BDF string, or NULL / empty string to let the kernel + * pick the only tracked device. Must be shorter than + * SLASH_HOTPLUG_BDF_LEN bytes (including NUL); otherwise + * EINVAL is returned. + * + * Returns 0 on success, -1 on failure. + */ +static int slash_hotplug_ioctl_with_request( + struct slash_hotplug *hotplug, + unsigned long op, + const char *bdf +) +{ + struct slash_hotplug_device_request req; + size_t len; + int ret; + + if (hotplug == NULL) { + errno = EINVAL; + return -1; + } + + memset(&req, 0, sizeof(req)); + req.size = sizeof(req); + + if (bdf != NULL && bdf[0] != '\0') { + len = strlen(bdf); + if (len >= sizeof(req.bdf)) { + errno = EINVAL; + return -1; + } + + memcpy(req.bdf, bdf, len + 1); + } + + ret = ioctl(hotplug->fd, op, &req); + if (ret < 0) { + return -1; + } + + return 0; +} + +struct slash_hotplug *slash_hotplug_open(const char *path) +{ + const char *open_path; + struct slash_hotplug *hotplug; + + open_path = path; + if (open_path == NULL) { + open_path = SLASH_HOTPLUG_DEFAULT_PATH; + } + + hotplug = calloc(1, sizeof(*hotplug)); + if (hotplug == NULL) { + return NULL; + } + + hotplug->fd = open(open_path, O_RDWR | O_CLOEXEC); + if (hotplug->fd < 0) { + free(hotplug); + return NULL; + } + + return hotplug; +} + +int slash_hotplug_close(struct slash_hotplug *hotplug) +{ + int ret; + + if (hotplug == NULL) { + errno = EINVAL; + return -1; + } + + ret = 0; + if (hotplug->fd >= 0 && close(hotplug->fd) != 0) { + ret = -1; + } + + /* Free unconditionally — the handle is invalid after this call + * regardless of whether close() succeeded. */ + free(hotplug); + + return ret; +} + +/* ───────────────────────────────────────────────────────────────────── + * Public hotplug operations — each is a thin wrapper over an ioctl. + * ───────────────────────────────────────────────────────────────────── */ + +int slash_hotplug_rescan(struct slash_hotplug *hotplug) +{ + return slash_hotplug_ioctl_without_request(hotplug, SLASH_HOTPLUG_IOCTL_RESCAN); +} + +int slash_hotplug_remove(struct slash_hotplug *hotplug, const char *bdf) +{ + return slash_hotplug_ioctl_with_request(hotplug, SLASH_HOTPLUG_IOCTL_REMOVE, bdf); +} + +int slash_hotplug_toggle_sbr(struct slash_hotplug *hotplug, const char *bdf) +{ + return slash_hotplug_ioctl_with_request(hotplug, SLASH_HOTPLUG_IOCTL_TOGGLE_SBR, bdf); +} + +int slash_hotplug_hotplug(struct slash_hotplug *hotplug, const char *bdf) +{ + return slash_hotplug_ioctl_with_request(hotplug, SLASH_HOTPLUG_IOCTL_HOTPLUG, bdf); +} diff --git a/driver/libslash/src/qdma.c b/driver/libslash/src/qdma.c new file mode 100644 index 00000000..68c38b6d --- /dev/null +++ b/driver/libslash/src/qdma.c @@ -0,0 +1,250 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file qdma.c + * + * Implementation of the slash QDMA userspace wrapper. + * + * Each public function validates its arguments, then issues a single + * ioctl against the QDMA character device. No mock path exists yet. + * + * The ioctl structs use a size field for kernel-side version + * negotiation: userspace sets size = sizeof(struct), and the kernel + * can handle older/newer struct layouts accordingly. + */ + +#define _GNU_SOURCE + +#include + +#include "qdma_mock.h" + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct slash_qdma *slash_qdma_open(const char *path) +{ + struct slash_qdma *qdma; + + if (path == NULL) { + errno = EINVAL; + return NULL; + } + + if (strcmp(path, "@mock") == 0) { + return slash_qdma_mock_open(); + } + + qdma = calloc(1, sizeof(*qdma)); + if (qdma == NULL) { + return NULL; + } + + qdma->fd = open(path, O_RDWR); + if (qdma->fd < 0) { + free(qdma); + return NULL; + } + + return qdma; +} + +int slash_qdma_close(struct slash_qdma *qdma) +{ + int ret; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + if (qdma->priv) { + return slash_qdma_mock_close(qdma); + } + + ret = 0; + if (qdma->fd >= 0 && close(qdma->fd) != 0) { + ret = -1; + } + + /* Free unconditionally — handle is invalid after this call. */ + free(qdma); + + return ret; +} + +int slash_qdma_info_read(struct slash_qdma *qdma, struct slash_qdma_info *info) +{ + struct slash_qdma_info tmp; + int ret; + + if (qdma == NULL || info == NULL) { + errno = EINVAL; + return -1; + } + + if (qdma->priv) { + return slash_qdma_mock_info_read(qdma, info); + } + + memset(&tmp, 0, sizeof(tmp)); + tmp.size = sizeof(tmp); + + ret = ioctl(qdma->fd, SLASH_QDMA_IOCTL_INFO, &tmp); + if (ret < 0) { + return -1; + } + + /* Copy the kernel-filled result back to the caller. */ + *info = tmp; + + return 0; +} + +/** + * slash_qdma_qpair_add() — Create a new queue pair. + * + * Copies caller-provided configuration into a zeroed temporary to + * ensure no stale fields leak to the kernel, then copies the full + * kernel response (including assigned qid) back into @req. + */ +int slash_qdma_qpair_add(struct slash_qdma *qdma, + struct slash_qdma_qpair_add *req) +{ + struct slash_qdma_qpair_add tmp; + int ret; + + if (qdma == NULL || req == NULL) { + errno = EINVAL; + return -1; + } + + if (qdma->priv) { + return slash_qdma_mock_qpair_add(qdma, req); + } + + memset(&tmp, 0, sizeof(tmp)); + tmp.size = sizeof(tmp); + tmp.mode = req->mode; + tmp.dir_mask = req->dir_mask; + tmp.h2c_ring_sz = req->h2c_ring_sz; + tmp.c2h_ring_sz = req->c2h_ring_sz; + tmp.cmpt_ring_sz = req->cmpt_ring_sz; + + ret = ioctl(qdma->fd, SLASH_QDMA_IOCTL_QPAIR_ADD, &tmp); + if (ret < 0) { + return -1; + } + + /* Write back — kernel will have filled in qid and other fields. */ + *req = tmp; + + return 0; +} + +/** + * slash_qdma_qpair_op() — Issue a queue pair lifecycle operation. + * + * Internal helper shared by start/stop/del. The @op parameter selects + * which operation the kernel performs. + */ +static int slash_qdma_qpair_op(struct slash_qdma *qdma, + uint32_t qid, + uint32_t op) +{ + struct slash_qdma_qpair_op req; + int ret; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + if (qdma->priv) { + switch (op) { + case SLASH_QDMA_QUEUE_OP_START: + return slash_qdma_mock_qpair_start(qdma, qid); + case SLASH_QDMA_QUEUE_OP_STOP: + return slash_qdma_mock_qpair_stop(qdma, qid); + case SLASH_QDMA_QUEUE_OP_DEL: + return slash_qdma_mock_qpair_del(qdma, qid); + default: + errno = EINVAL; + return -1; + } + } + + memset(&req, 0, sizeof(req)); + req.size = sizeof(req); + req.qid = qid; + req.op = op; + + ret = ioctl(qdma->fd, SLASH_QDMA_IOCTL_Q_OP, &req); + if (ret < 0) { + return -1; + } + + return 0; +} + +int slash_qdma_qpair_start(struct slash_qdma *qdma, uint32_t qid) +{ + return slash_qdma_qpair_op(qdma, qid, SLASH_QDMA_QUEUE_OP_START); +} + +int slash_qdma_qpair_stop(struct slash_qdma *qdma, uint32_t qid) +{ + return slash_qdma_qpair_op(qdma, qid, SLASH_QDMA_QUEUE_OP_STOP); +} + +int slash_qdma_qpair_del(struct slash_qdma *qdma, uint32_t qid) +{ + return slash_qdma_qpair_op(qdma, qid, SLASH_QDMA_QUEUE_OP_DEL); +} + +int slash_qdma_qpair_get_fd(struct slash_qdma *qdma, uint32_t qid, int flags) +{ + struct slash_qdma_qpair_fd_request req; + int fd; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + if (qdma->priv) { + return slash_qdma_mock_qpair_get_fd(qdma, qid, flags); + } + + memset(&req, 0, sizeof(req)); + req.size = sizeof(req); + req.qid = qid; + req.flags = flags; + + fd = ioctl(qdma->fd, SLASH_QDMA_IOCTL_QPAIR_GET_FD, &req); + if (fd < 0) { + return -1; + } + + return fd; +} + diff --git a/driver/libslash/src/qdma_mock.c b/driver/libslash/src/qdma_mock.c new file mode 100644 index 00000000..92a24c6c --- /dev/null +++ b/driver/libslash/src/qdma_mock.c @@ -0,0 +1,259 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file qdma_mock.c + * @brief Mock QDMA implementation backed by memfd files. + * + * Each queue pair's I/O fd is a memfd_create() anonymous file. The kernel + * supports pread()/pwrite() at arbitrary offsets on memfds (tmpfs), so the + * test's DDR_BASE_ADDRESS offset is handled transparently via sparse pages. + * + * Queue state is tracked in a fixed-size table (QDMA_MOCK_MAX_QUEUES slots) + * stored in the slash_qdma_mock struct pointed to by qdma->priv. + */ + +#define _GNU_SOURCE + +#include "qdma_mock.h" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define QDMA_MOCK_MAX_QUEUES 64 + +struct slash_qdma_mock_qpair { + bool in_use; + bool started; + int fd; /* backing memfd; -1 when slot is free */ +}; + +struct slash_qdma_mock { + struct slash_qdma_mock_qpair queues[QDMA_MOCK_MAX_QUEUES]; +}; + +static struct slash_qdma_mock *mock_ctx(struct slash_qdma *qdma) +{ + return (struct slash_qdma_mock *) qdma->priv; +} + +struct slash_qdma *slash_qdma_mock_open(void) +{ + struct slash_qdma *qdma; + struct slash_qdma_mock *ctx; + size_t i; + + qdma = calloc(1, sizeof(*qdma)); + if (qdma == NULL) { + return NULL; + } + + ctx = calloc(1, sizeof(*ctx)); + if (ctx == NULL) { + free(qdma); + return NULL; + } + + for (i = 0; i < QDMA_MOCK_MAX_QUEUES; ++i) { + ctx->queues[i].fd = -1; + } + + qdma->fd = -1; + qdma->priv = ctx; + + return qdma; +} + +int slash_qdma_mock_close(struct slash_qdma *qdma) +{ + struct slash_qdma_mock *ctx; + size_t i; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + ctx = mock_ctx(qdma); + + for (i = 0; i < QDMA_MOCK_MAX_QUEUES; ++i) { + if (ctx->queues[i].in_use && ctx->queues[i].fd >= 0) { + (void) close(ctx->queues[i].fd); + } + } + + free(ctx); + free(qdma); + + return 0; +} + +int slash_qdma_mock_info_read(struct slash_qdma *qdma, struct slash_qdma_info *info) +{ + if (qdma == NULL || info == NULL) { + errno = EINVAL; + return -1; + } + + memset(info, 0, sizeof(*info)); + info->size = sizeof(*info); + info->qsets_max = QDMA_MOCK_MAX_QUEUES; + info->msix_qvecs = 1; + + return 0; +} + +int slash_qdma_mock_qpair_add(struct slash_qdma *qdma, struct slash_qdma_qpair_add *req) +{ + struct slash_qdma_mock *ctx; + size_t i; + int fd; + + if (qdma == NULL || req == NULL) { + errno = EINVAL; + return -1; + } + + ctx = mock_ctx(qdma); + + for (i = 0; i < QDMA_MOCK_MAX_QUEUES; ++i) { + if (!ctx->queues[i].in_use) { + break; + } + } + + if (i == QDMA_MOCK_MAX_QUEUES) { + errno = ENOSPC; + return -1; + } + + fd = memfd_create("slash_qdma_mock", MFD_CLOEXEC); + if (fd < 0) { + return -1; + } + + ctx->queues[i].in_use = true; + ctx->queues[i].started = false; + ctx->queues[i].fd = fd; + + req->qid = (uint32_t) i; + + return 0; +} + +static int mock_qpair_op(struct slash_qdma *qdma, uint32_t qid, bool start) +{ + struct slash_qdma_mock *ctx; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + if (qid >= QDMA_MOCK_MAX_QUEUES) { + errno = EINVAL; + return -1; + } + + ctx = mock_ctx(qdma); + + if (!ctx->queues[qid].in_use) { + errno = EINVAL; + return -1; + } + + ctx->queues[qid].started = start; + + return 0; +} + +int slash_qdma_mock_qpair_start(struct slash_qdma *qdma, uint32_t qid) +{ + return mock_qpair_op(qdma, qid, true); +} + +int slash_qdma_mock_qpair_stop(struct slash_qdma *qdma, uint32_t qid) +{ + return mock_qpair_op(qdma, qid, false); +} + +int slash_qdma_mock_qpair_del(struct slash_qdma *qdma, uint32_t qid) +{ + struct slash_qdma_mock *ctx; + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + if (qid >= QDMA_MOCK_MAX_QUEUES) { + errno = EINVAL; + return -1; + } + + ctx = mock_ctx(qdma); + + if (!ctx->queues[qid].in_use) { + errno = EINVAL; + return -1; + } + + if (ctx->queues[qid].fd >= 0) { + (void) close(ctx->queues[qid].fd); + } + + memset(&ctx->queues[qid], 0, sizeof(ctx->queues[qid])); + ctx->queues[qid].fd = -1; + + return 0; +} + +int slash_qdma_mock_qpair_get_fd(struct slash_qdma *qdma, uint32_t qid, int flags) +{ + struct slash_qdma_mock *ctx; + int new_fd; + (void) flags; /* O_CLOEXEC already set on the memfd */ + + if (qdma == NULL) { + errno = EINVAL; + return -1; + } + + if (qid >= QDMA_MOCK_MAX_QUEUES) { + errno = EINVAL; + return -1; + } + + ctx = mock_ctx(qdma); + + if (!ctx->queues[qid].in_use || !ctx->queues[qid].started) { + errno = EINVAL; + return -1; + } + + /* dup so the caller owns a separate fd they can close independently */ + new_fd = dup(ctx->queues[qid].fd); + if (new_fd < 0) { + return -1; + } + + return new_fd; +} diff --git a/driver/libslash/src/qdma_mock.h b/driver/libslash/src/qdma_mock.h new file mode 100644 index 00000000..36f3d596 --- /dev/null +++ b/driver/libslash/src/qdma_mock.h @@ -0,0 +1,37 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file qdma_mock.h + * @brief Mock QDMA implementation for testing without hardware. + */ + +#ifndef LIBSLASH_QDMA_MOCK_H +#define LIBSLASH_QDMA_MOCK_H + +#include +#include + +#include + +struct slash_qdma *slash_qdma_mock_open(void); +int slash_qdma_mock_close(struct slash_qdma *qdma); +int slash_qdma_mock_info_read(struct slash_qdma *qdma, struct slash_qdma_info *info); +int slash_qdma_mock_qpair_add(struct slash_qdma *qdma, struct slash_qdma_qpair_add *req); +int slash_qdma_mock_qpair_start(struct slash_qdma *qdma, uint32_t qid); +int slash_qdma_mock_qpair_stop(struct slash_qdma *qdma, uint32_t qid); +int slash_qdma_mock_qpair_del(struct slash_qdma *qdma, uint32_t qid); +int slash_qdma_mock_qpair_get_fd(struct slash_qdma *qdma, uint32_t qid, int flags); + +#endif /* LIBSLASH_QDMA_MOCK_H */ diff --git a/driver/libslash/tests/CMakeLists.txt b/driver/libslash/tests/CMakeLists.txt new file mode 100644 index 00000000..d37fb072 --- /dev/null +++ b/driver/libslash/tests/CMakeLists.txt @@ -0,0 +1,47 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +include(FetchContent) +FetchContent_Declare( + googletest + URL https://github.com/google/googletest/archive/refs/tags/v1.17.0.zip +) +FetchContent_MakeAvailable(googletest) + +enable_testing() + +include(GoogleTest) + +add_custom_target(unit_tests) + +macro(add_slash_test test_name test_source) + add_executable(${test_name} ${test_source}) + target_link_libraries(${test_name} PRIVATE GTest::gtest_main GTest::gmock slash::slash) + set_target_properties(${test_name} PROPERTIES + CXX_STANDARD 20 + CXX_STANDARD_REQUIRED YES + ) + gtest_discover_tests(${test_name}) + add_dependencies(unit_tests ${test_name}) +endmacro() + +add_slash_test(ctldev_test ctldev_test.cpp) +add_slash_test(hotplug_test hotplug_test.cpp) +add_slash_test(qdma_test qdma_test.cpp) diff --git a/driver/libslash/tests/ctldev_test.cpp b/driver/libslash/tests/ctldev_test.cpp new file mode 100644 index 00000000..c18cbbef --- /dev/null +++ b/driver/libslash/tests/ctldev_test.cpp @@ -0,0 +1,219 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include + +extern "C" { +#include +} + +static constexpr uint64_t MOCK_BAR_SIZE = 64ULL * 1024ULL * 1024ULL; +static constexpr const char *REAL_CTLDEV_PATH = "/dev/slash_ctl0"; + +// ─── Null / invalid argument tests (no hardware needed) ────────────────────── + +TEST(CtldevOpenTest, NullPath) { + errno = 0; + struct slash_ctldev *dev = slash_ctldev_open(nullptr); + EXPECT_EQ(dev, nullptr); + EXPECT_EQ(errno, EFAULT); +} + +TEST(CtldevCloseTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_ctldev_close(nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(CtldevBarFileCloseTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_bar_file_close(nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +// ─── Mock-mode tests (no hardware needed) ──────────────────────────────────── + +class MockCtldevTest : public ::testing::Test { + protected: + void SetUp() override { + dev_ = slash_ctldev_open("@mock"); + ASSERT_NE(dev_, nullptr); + ASSERT_TRUE(dev_->mock); + } + + void TearDown() override { + if (dev_) { + slash_ctldev_close(dev_); + dev_ = nullptr; + } + } + + struct slash_ctldev *dev_ = nullptr; +}; + +TEST_F(MockCtldevTest, OpenReturnsMockHandle) { + EXPECT_TRUE(dev_->mock); + EXPECT_EQ(dev_->fd, -1); +} + +TEST_F(MockCtldevTest, CloseSucceeds) { + EXPECT_EQ(slash_ctldev_close(dev_), 0); + dev_ = nullptr; +} + +TEST_F(MockCtldevTest, DeviceInfoRead) { + struct slash_ioctl_device_info *info = slash_device_info_read(dev_); + ASSERT_NE(info, nullptr); + EXPECT_STREQ(info->bdf, "0000:00:00.0"); + slash_device_info_free(info); +} + +TEST_F(MockCtldevTest, DeviceInfoReadNullHandle) { + errno = 0; + EXPECT_EQ(slash_device_info_read(nullptr), nullptr); + EXPECT_EQ(errno, EINVAL); +} + +TEST_F(MockCtldevTest, BarInfoReadBar0Usable) { + struct slash_ioctl_bar_info *info = slash_bar_info_read(dev_, 0); + ASSERT_NE(info, nullptr); + EXPECT_NE(info->usable, 0); + EXPECT_EQ(info->length, MOCK_BAR_SIZE); + EXPECT_EQ(info->bar_number, 0); + slash_bar_info_free(info); +} + +TEST_F(MockCtldevTest, BarInfoReadNonZeroBarsNotUsable) { + for (int bar = 1; bar <= 5; ++bar) { + struct slash_ioctl_bar_info *info = slash_bar_info_read(dev_, bar); + ASSERT_NE(info, nullptr) << "bar=" << bar; + EXPECT_EQ(info->usable, 0) << "bar=" << bar; + slash_bar_info_free(info); + } +} + +TEST_F(MockCtldevTest, BarInfoReadNullHandle) { + errno = 0; + EXPECT_EQ(slash_bar_info_read(nullptr, 0), nullptr); + EXPECT_EQ(errno, EINVAL); +} + +TEST_F(MockCtldevTest, BarFileOpenBar0) { + struct slash_bar_file *bar = slash_bar_file_open(dev_, 0, 0); + ASSERT_NE(bar, nullptr); + EXPECT_NE(bar->map, nullptr); + EXPECT_EQ(bar->len, MOCK_BAR_SIZE); + EXPECT_TRUE(bar->mock); + EXPECT_EQ(slash_bar_file_close(bar), 0); +} + +TEST_F(MockCtldevTest, BarFileOpenNonZeroBarFails) { + errno = 0; + struct slash_bar_file *bar = slash_bar_file_open(dev_, 1, 0); + EXPECT_EQ(bar, nullptr); + EXPECT_EQ(errno, ENODEV); +} + +TEST_F(MockCtldevTest, BarFileOpenNullHandle) { + errno = 0; + EXPECT_EQ(slash_bar_file_open(nullptr, 0, 0), nullptr); + EXPECT_EQ(errno, EINVAL); +} + +TEST_F(MockCtldevTest, BarFileSyncIsNoopInMockMode) { + struct slash_bar_file *bar = slash_bar_file_open(dev_, 0, 0); + ASSERT_NE(bar, nullptr); + + EXPECT_EQ(slash_bar_file_start_write(bar), 0); + EXPECT_EQ(slash_bar_file_end_write(bar), 0); + EXPECT_EQ(slash_bar_file_start_read(bar), 0); + EXPECT_EQ(slash_bar_file_end_read(bar), 0); + + EXPECT_EQ(slash_bar_file_close(bar), 0); +} + +TEST_F(MockCtldevTest, BarFileMapIsReadWrite) { + struct slash_bar_file *bar = slash_bar_file_open(dev_, 0, 0); + ASSERT_NE(bar, nullptr); + + auto *p = static_cast(bar->map); + p[0] = 0xDEADBEEFu; + EXPECT_EQ(p[0], 0xDEADBEEFu); + + EXPECT_EQ(slash_bar_file_close(bar), 0); +} + +// ─── Real device tests (requires /dev/slash_ctl0) ──────────────────────────── + +class RealCtldevTest : public ::testing::Test { + protected: + void SetUp() override { + dev_ = slash_ctldev_open(REAL_CTLDEV_PATH); + if (!dev_) { + GTEST_SKIP() << REAL_CTLDEV_PATH << " not available (errno=" << errno << ")"; + } + } + + void TearDown() override { + if (dev_) { + slash_ctldev_close(dev_); + dev_ = nullptr; + } + } + + struct slash_ctldev *dev_ = nullptr; +}; + +TEST_F(RealCtldevTest, OpenSucceeds) { + EXPECT_FALSE(dev_->mock); + EXPECT_GE(dev_->fd, 0); +} + +TEST_F(RealCtldevTest, DeviceInfoBdfNonEmpty) { + struct slash_ioctl_device_info *info = slash_device_info_read(dev_); + ASSERT_NE(info, nullptr); + EXPECT_GT(strlen(info->bdf), 0u); + slash_device_info_free(info); +} + +TEST_F(RealCtldevTest, Bar0InfoUsable) { + struct slash_ioctl_bar_info *info = slash_bar_info_read(dev_, 0); + ASSERT_NE(info, nullptr); + EXPECT_NE(info->usable, 0); + EXPECT_GT(info->length, 0u); + slash_bar_info_free(info); +} + +TEST_F(RealCtldevTest, Bar0FileOpenAndSync) { + struct slash_bar_file *bar = slash_bar_file_open(dev_, 0, 0); + ASSERT_NE(bar, nullptr); + EXPECT_NE(bar->map, nullptr); + EXPECT_GT(bar->len, 0u); + EXPECT_FALSE(bar->mock); + + EXPECT_EQ(slash_bar_file_start_write(bar), 0); + EXPECT_EQ(slash_bar_file_end_write(bar), 0); + + EXPECT_EQ(slash_bar_file_close(bar), 0); +} diff --git a/driver/libslash/tests/hotplug_test.cpp b/driver/libslash/tests/hotplug_test.cpp new file mode 100644 index 00000000..6229b08e --- /dev/null +++ b/driver/libslash/tests/hotplug_test.cpp @@ -0,0 +1,104 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include + +extern "C" { +#include +} + +// ─── Null / invalid argument tests (no hardware needed) ────────────────────── + +TEST(HotplugOpenTest, NonexistentPathFails) { + errno = 0; + struct slash_hotplug *hp = slash_hotplug_open("/nonexistent/slash_hotplug"); + EXPECT_EQ(hp, nullptr); + EXPECT_EQ(errno, ENOENT); +} + +TEST(HotplugCloseTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_hotplug_close(nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(HotplugRescanTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_hotplug_rescan(nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(HotplugRemoveTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_hotplug_remove(nullptr, "0000:00:00.0"), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(HotplugToggleSbrTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_hotplug_toggle_sbr(nullptr, "0000:00:00.0"), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(HotplugHotplugTest, NullHandle) { + errno = 0; + EXPECT_EQ(slash_hotplug_hotplug(nullptr, "0000:00:00.0"), -1); + EXPECT_EQ(errno, EINVAL); +} + +// ─── Real device tests (requires /dev/slash_hotplug) ───────────────────────── + +class RealHotplugTest : public ::testing::Test { + protected: + void SetUp() override { + hp_ = slash_hotplug_open(SLASH_HOTPLUG_DEFAULT_PATH); + if (!hp_) { + GTEST_SKIP() << SLASH_HOTPLUG_DEFAULT_PATH + << " not available (errno=" << errno << ")"; + } + } + + void TearDown() override { + if (hp_) { + slash_hotplug_close(hp_); + hp_ = nullptr; + } + } + + struct slash_hotplug *hp_ = nullptr; +}; + +TEST_F(RealHotplugTest, OpenDefaultPathSucceeds) { + EXPECT_GE(hp_->fd, 0); +} + +TEST_F(RealHotplugTest, OpenExplicitPathSucceeds) { + struct slash_hotplug *hp2 = slash_hotplug_open("/dev/slash_hotplug"); + ASSERT_NE(hp2, nullptr); + EXPECT_GE(hp2->fd, 0); + EXPECT_EQ(slash_hotplug_close(hp2), 0); +} + +TEST_F(RealHotplugTest, CloseSucceeds) { + EXPECT_EQ(slash_hotplug_close(hp_), 0); + hp_ = nullptr; +} diff --git a/driver/libslash/tests/qdma_test.cpp b/driver/libslash/tests/qdma_test.cpp new file mode 100644 index 00000000..5b024111 --- /dev/null +++ b/driver/libslash/tests/qdma_test.cpp @@ -0,0 +1,186 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include + +extern "C" { +#include +} + +static constexpr const char *REAL_QDMA_PATH = "/dev/slash_qdma_ctl0"; +static constexpr uint64_t DDR_BASE_ADDRESS = 0x60000000000ULL; + +// ─── Null / invalid argument tests (no hardware needed) ────────────────────── + +TEST(QdmaNullTest, Open) { + errno = 0; + EXPECT_EQ(slash_qdma_open(nullptr), nullptr); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, Close) { + errno = 0; + EXPECT_EQ(slash_qdma_close(nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, NullInfoRead) { + struct slash_qdma_info info{}; + errno = 0; + EXPECT_EQ(slash_qdma_info_read(nullptr, &info), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, FakeInfoRead) { + /* Construct a minimal fake handle — we only need errno set by the NULL info check. */ + struct slash_qdma fake{}; + fake.fd = -1; + errno = 0; + EXPECT_EQ(slash_qdma_info_read(&fake, nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, NullQpairAdd) { + struct slash_qdma_qpair_add req{}; + errno = 0; + EXPECT_EQ(slash_qdma_qpair_add(nullptr, &req), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, FakeQpairAdd) { + struct slash_qdma fake{}; + fake.fd = -1; + errno = 0; + EXPECT_EQ(slash_qdma_qpair_add(&fake, nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, QpairStart) { + errno = 0; + EXPECT_EQ(slash_qdma_qpair_start(nullptr, 0), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, QpairStop) { + errno = 0; + EXPECT_EQ(slash_qdma_qpair_stop(nullptr, 0), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, QpairDel) { + errno = 0; + EXPECT_EQ(slash_qdma_qpair_del(nullptr, 0), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(QdmaNullTest, QpaiGetFd) { + errno = 0; + EXPECT_EQ(slash_qdma_qpair_get_fd(nullptr, 0, 0), -1); + EXPECT_EQ(errno, EINVAL); +} + +// ─── Real device tests (requires /dev/slash_qdma_ctl0) ─────────────────────── + +class ParametrizedQdmaTest : public ::testing::TestWithParam { + protected: + bool mock; + + void SetUp() override { + mock = GetParam(); + if (mock) { + qdma_ = slash_qdma_open("@mock"); + EXPECT_NE(qdma_, nullptr); + } else { + qdma_ = slash_qdma_open(REAL_QDMA_PATH); + if (!qdma_) { + GTEST_SKIP() << REAL_QDMA_PATH << " not available (errno=" << errno << ")"; + } + } + } + + void TearDown() override { + if (qdma_) { + slash_qdma_close(qdma_); + qdma_ = nullptr; + } + } + + struct slash_qdma *qdma_ = nullptr; +}; + +TEST_P(ParametrizedQdmaTest, OpenSucceeds) { + EXPECT_GE(qdma_->fd, mock ? -1 : 0); + EXPECT_EQ(qdma_->priv != nullptr, mock); +} + +TEST_P(ParametrizedQdmaTest, InfoRead) { + struct slash_qdma_info info{}; + EXPECT_EQ(slash_qdma_info_read(qdma_, &info), 0); +} + +TEST_P(ParametrizedQdmaTest, QueueDmaTransfer) { + static constexpr size_t XFER_SIZE = 4096; + + // Add a Memory-Mapped queue pair with both H2C and C2H enabled. + struct slash_qdma_qpair_add req{}; + req.mode = 0; /* QDMA_Q_MODE_MM */ + req.dir_mask = 0x3; /* H2C | C2H */ + req.h2c_ring_sz = 0; + req.c2h_ring_sz = 0; + req.cmpt_ring_sz = 0; + + ASSERT_EQ(slash_qdma_qpair_add(qdma_, &req), 0); + uint32_t qid = req.qid; + + ASSERT_EQ(slash_qdma_qpair_start(qdma_, qid), 0); + + int queue_fd = slash_qdma_qpair_get_fd(qdma_, qid, 0); + ASSERT_GE(queue_fd, 0); + + // Write a known pattern to DDR (H2C). + uint8_t src[XFER_SIZE]; + for (size_t i = 0; i < XFER_SIZE; ++i) { + src[i] = static_cast(i & 0xFF); + } + ssize_t written = pwrite(queue_fd, src, XFER_SIZE, static_cast(DDR_BASE_ADDRESS)); + EXPECT_EQ(written, static_cast(XFER_SIZE)); + + // Read back from DDR (C2H) and verify. + uint8_t dst[XFER_SIZE]{}; + ssize_t read_bytes = pread(queue_fd, dst, XFER_SIZE, static_cast(DDR_BASE_ADDRESS)); + EXPECT_EQ(read_bytes, static_cast(XFER_SIZE)); + EXPECT_EQ(std::memcmp(src, dst, XFER_SIZE), 0); + + EXPECT_EQ(close(queue_fd), 0); + + EXPECT_EQ(slash_qdma_qpair_stop(qdma_, qid), 0); + EXPECT_EQ(slash_qdma_qpair_del(qdma_, qid), 0); +} + +TEST_P(ParametrizedQdmaTest, CloseSucceeds) { + EXPECT_EQ(slash_qdma_close(qdma_), 0); + qdma_ = nullptr; +} + +INSTANTIATE_TEST_SUITE_P(QdmaTest, ParametrizedQdmaTest, testing::Values(true, false)); \ No newline at end of file diff --git a/driver/slash.h b/driver/slash.h new file mode 100644 index 00000000..9c4ecb67 --- /dev/null +++ b/driver/slash.h @@ -0,0 +1,32 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash.h + * + * Umbrella include for the SLASH kernel module. + * + * Pulls in the build-time configuration (PCI IDs, naming, log format) + * and the user-kernel ABI definitions (ioctl structs and command + * numbers) so that every driver source file can include a single + * header for the common definitions. + */ + +#ifndef SLASH_H +#define SLASH_H + +#include "slash_config.h" +#include "slash_interface.h" + +#endif /* SLASH_H */ diff --git a/driver/slash_compat.h b/driver/slash_compat.h new file mode 100644 index 00000000..5b3a50c2 --- /dev/null +++ b/driver/slash_compat.h @@ -0,0 +1,56 @@ +/** + * Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef SLASH_COMPAT_H +#define SLASH_COMPAT_H + +#include +#include + +/* + * Compat shims selected by the kcompat probes in driver/kcompat/. + * If the modern form is detected (SLASH_HAVE_*), use it; otherwise + * fall back to the legacy form. The probes are exhaustive, so no + * #error path is needed. + */ + +static inline void slash_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags) +{ +#if defined(SLASH_HAVE_VM_FLAGS_SET) + vm_flags_set(vma, flags); +#else + vma->vm_flags |= flags; +#endif +} + +/* + * MODULE_IMPORT_NS argument form. + * + * Pre-6.13: bare token, e.g. MODULE_IMPORT_NS(DMA_BUF). The kernel + * macro internally __stringify()s the argument, so passing a + * string literal would produce a runtime namespace mismatch. + * 6.13+: string literal, e.g. MODULE_IMPORT_NS("DMA_BUF"). The + * kernel macro stopped stringifying, so passing a bare token + * fails to compile. + * + * We probe the token form (precise cutover at 6.13) and stringify here + * when it's no longer accepted. + */ +#if defined(SLASH_HAVE_MODULE_IMPORT_NS_TOKEN) +#define SLASH_MODULE_IMPORT_NS(ns) MODULE_IMPORT_NS(ns) +#else +#define SLASH_MODULE_IMPORT_NS(ns) MODULE_IMPORT_NS(#ns) +#endif + +#endif /* SLASH_COMPAT_H */ diff --git a/driver/slash_config.h b/driver/slash_config.h new file mode 100644 index 00000000..c06c5962 --- /dev/null +++ b/driver/slash_config.h @@ -0,0 +1,98 @@ +/** + * Copyright (C) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_config.h + * + * Build-time constants for the SLASH kernel module. + * + * Defines PCI identity, physical-function assignments, character-device + * naming conventions, and the kernel log prefix used throughout the + * driver. + * + * The SLASH design exposes two PCI physical functions per card: + * + * - **PF1** (device 0x50B5) — QDMA function. Hosts the Xilinx QDMA + * IP used for high-throughput DMA transfers between host memory and + * the FPGA fabric. + * + * - **PF2** (device 0x50B6) — Control function. Exposes PCI BARs + * that the host can mmap for register-level MMIO access to the + * FPGA design. + * + * Both functions share vendor ID 0x10EE (AMD/Xilinx). + */ + +#ifndef SLASH_CONFIG_H +#define SLASH_CONFIG_H + +/* --- PCI identity for the control function (PF2) --- */ + +/** AMD/Xilinx PCI vendor ID. */ +#define SLASH_PCIE_VENDOR_ID 0x10EE +/** PCI device ID for the V80 SLASH control function. */ +#define SLASH_PCIE_DEVICE_ID 0x50B6 +/** Physical function number for the control/BAR-access interface. */ +#define SLASH_PCIE_PF 2 + +/* --- PCI identity for the QDMA function (PF1) --- */ + +/** AMD/Xilinx PCI vendor ID (same as control function). */ +#define SLASH_QDMA_PCI_VENDOR_ID 0x10EE +/** PCI device ID for the V80 SLASH QDMA function. */ +#define SLASH_QDMA_PCI_DEVICE_ID 0x50B5 +/** Physical function number for the QDMA DMA engine. */ +#define SLASH_QDMA_PF 1 + +/* --- Driver name and character-device naming --- */ + +/** Short driver name used in log prefixes and sysfs entries. */ +#define SLASH_NAME "slash" +/** PCI driver name for the PF2 control function. */ +#define SLASH_PCIE_DRV_NAME SLASH_NAME "_ctl" +/** PCI driver name for the PF1 QDMA function. */ +#define SLASH_QDMA_DRV_NAME SLASH_NAME "_qdma" + +/** + * Name format for control misc devices. + * Uses pci_name() (e.g. "0000:03:00.2") — appears in /sys/class/misc. + */ +#define SLASH_CTLDEV_NAME_FMT "slash_ctl_%s" +/** + * Node name format for control misc devices. + * Uses an incrementing counter — appears as /dev/slash_ctl0, etc. + */ +#define SLASH_CTLDEV_NODENAME_FMT "slash_ctl%d" + +/** Name format for QDMA control misc devices (/sys/class/misc). */ +#define SLASH_QDMA_CTLDEV_NAME_FMT "slash_qdma_ctl_%s" +/** Node name format for QDMA control misc devices (/dev/). */ +#define SLASH_QDMA_CTLDEV_NODENAME_FMT "slash_qdma_ctl%d" + +/* + * Default /dev node permissions (owner read/write only). + * For production, prefer a udev rule to set permissions instead of + * changing these constants. + */ +#define SLASH_CTLDEV_MODE 0600 +#define SLASH_CTLDEV_QDMA_MODE 0600 + +/* + * Override the kernel's pr_fmt to prefix every pr_info/pr_err/pr_dbg + * message with "slash:: ". + */ +#undef pr_fmt +#define pr_fmt(fmt) "%s:%s: " fmt, SLASH_NAME, __func__ + +#endif /* SLASH_CONFIG_H */ diff --git a/driver/slash_ctldev.c b/driver/slash_ctldev.c new file mode 100644 index 00000000..dc69b137 --- /dev/null +++ b/driver/slash_ctldev.c @@ -0,0 +1,678 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_ctldev.c + * + * Control device implementation for the SLASH kernel module. + * + * Creates a per-device misc character device (/dev/slash_ctl) that + * exposes device identity, BAR properties, and dma-buf-backed BAR + * mappings to userspace via ioctl. This is an ioctl-only interface — + * no read/write/mmap file operations are provided on the control + * device itself. + * + * The ioctl interface uses **size-versioned structs** for ABI + * compatibility: every ioctl struct has a leading @size field that the + * caller sets to sizeof(struct ...). The kernel reads the minimum + * required fields (MIN_SIZE), copies min(user_size, kernel_size) + * bytes, and zero-fills any trailing space when a newer userspace sends + * a larger struct than the kernel knows about. This allows the driver + * and userspace library to evolve independently. + */ + +#include "slash_ctldev.h" + +#include +#include +#include +#include +#include +#include +#include + +#include "slash.h" +#include "slash_dmabuf.h" + +/** Compute the size of a struct member without needing an instance. */ +#define SLASH_FIELD_SIZE(_type, _member) (sizeof(((_type *)0)->_member)) + +/* + * Minimum struct sizes needed to read the input fields, and minimum + * sizes needed to write back the output fields, for each ioctl. + * These define the ABI backward-compatibility boundary: any userspace + * that provides at least MIN_SIZE bytes is accepted. + */ + +#define SLASH_IOCTL_BAR_INFO_MIN_SIZE \ + (offsetof(struct slash_ioctl_bar_info, bar_number) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_info, bar_number)) +#define SLASH_IOCTL_BAR_INFO_RESPONSE_SIZE \ + (offsetof(struct slash_ioctl_bar_info, length) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_info, length)) + +#define SLASH_IOCTL_BAR_FD_MIN_SIZE \ + (offsetof(struct slash_ioctl_bar_fd_request, flags) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_fd_request, flags)) +#define SLASH_IOCTL_BAR_FD_RESPONSE_SIZE \ + (offsetof(struct slash_ioctl_bar_fd_request, length) + SLASH_FIELD_SIZE(struct slash_ioctl_bar_fd_request, length)) + +static int slash_ctldev_set_bar_info(struct pci_dev *pdev, struct slash_ctldev *ctldev); +static int slash_ctldev_create_bar_dmabufs(struct slash_ctldev *ctldev); +static int slash_ctldev_create_misc(struct slash_ctldev *ctldev); + +static void slash_ctldev_destroy_misc(struct slash_ctldev *ctldev); +static void slash_ctldev_destroy_dmabufs(struct slash_ctldev *ctldev); + +static long slash_ctldev_fop_ioctl(struct file *, unsigned int, unsigned long); + +/** + * struct slash_ctldev_id_entry - Stable BDF-to-number mapping entry. + * @node: Intrusive list linkage for @slash_ctldev_id_map. + * @bdf: Full PCI BDF string including function (e.g. "0000:61:00.2"). + * @number: The /dev/slash_ctl suffix permanently assigned to this BDF. + * @in_use: True while the device is bound to the driver. Cleared on remove, + * set on probe. A probe that finds @in_use already true indicates + * the kernel handed us a device that was never properly unbound — + * this should never happen under normal operation. + * + * Entries are allocated in probe and intentionally never freed. They survive + * hotplug remove+rescan cycles so that a device always gets back the same N. + */ +struct slash_ctldev_id_entry { + struct list_head node; + char bdf[32]; /* "DDDD:BB:SS.F\0" fits comfortably in 32 bytes */ + int number; + bool in_use; +}; + +/** Persistent BDF-to-number map; entries live for the module's lifetime. */ +static LIST_HEAD(slash_ctldev_id_map); +/** Serialises all accesses to @slash_ctldev_id_map and @in_use fields. */ +static DEFINE_MUTEX(slash_ctldev_id_map_lock); +/** Source of new numbers; only incremented when a BDF is seen for the first time. */ +static atomic_t slash_ctldev_devcount = ATOMIC_INIT(0); + +static struct file_operations slash_ctldev_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = slash_ctldev_fop_ioctl, +}; + +/** + * slash_ctldev_create() - Create a control device for a PCI function. + * @pdev: PCI device to create the control device for. + * + * Allocates the control device state, probes all PCI BARs, creates + * dma-buf exporters for MMIO BARs, and registers a misc device. + * The state is stored as PCI driver data on @pdev. + * + * Return: 0 on success, negative errno on failure. + */ +int slash_ctldev_create(struct pci_dev *pdev) +{ + int err; + + struct slash_ctldev *ctldev = kzalloc(sizeof(*ctldev), GFP_KERNEL); + if (!ctldev) { + dev_err(&pdev->dev, "ctldev: kzalloc failed\n"); + return -ENOMEM; + } + ctldev->pdev = pdev; + + dev_info(&pdev->dev, "ctldev: creating control device\n"); + + /* Store early so that the ioctl handler can find us via pci_get_drvdata(). */ + pci_set_drvdata(pdev, ctldev); + + err = slash_ctldev_set_bar_info(pdev, ctldev); + if (err) { + dev_err(&pdev->dev, "ctldev: set_bar_info failed: %d\n", err); + goto err_free_ctldev; + } + + err = slash_ctldev_create_bar_dmabufs(ctldev); + if (err) { + dev_err(&pdev->dev, "ctldev: creating BAR dma-bufs failed: %d\n", err); + /* + * Some dmabufs may have been created before the failure, + * so we must destroy whatever was successfully created. + */ + goto err_destroy_dmabufs; + } + + err = slash_ctldev_create_misc(ctldev); + if (err) { + dev_err(&pdev->dev, "ctldev: creating misc ctldev failed: %d\n", err); + goto err_destroy_dmabufs; + } + + dev_info(&pdev->dev, "ctldev: device created successfully\n"); + + return 0; + +err_destroy_dmabufs: + slash_ctldev_destroy_dmabufs(ctldev); + +err_free_ctldev: + kfree(ctldev); + + return err; +} + +/** + * slash_ctldev_set_bar_info() - Probe and cache BAR metadata. + * @pdev: PCI device to read BAR info from. + * @ctldev: Control device state to populate. + * + * Iterates over all 6 standard PCI BARs and records their start + * address, size, and type (MMIO vs I/O port). BARs with a zero + * start address are considered unused and skipped. + * + * Return: Always 0 (BAR discovery cannot fail). + */ +static int slash_ctldev_set_bar_info(struct pci_dev *pdev, struct slash_ctldev *ctldev) +{ + int i; + + dev_dbg(&pdev->dev, "ctldev: probing PCI BARs\n"); + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + unsigned long flags; + + if (!pci_resource_start(pdev, i)) { + dev_dbg(&pdev->dev, "ctldev: BAR%d unused\n", i); + continue; /* Unused BAR */ + } + + ctldev->bars[i].active = 1; + ctldev->bars[i].start = pci_resource_start(pdev, i); + ctldev->bars[i].end = pci_resource_end(pdev, i); + ctldev->bars[i].len = pci_resource_len(pdev, i); + flags = pci_resource_flags(pdev, i); + ctldev->bars[i].mmio = ((flags & IORESOURCE_MEM) != 0); + + + dev_info(&pdev->dev, + "Found BAR%d: 0x%pa - 0x%pa (size: %pa) %s\n", + i, &ctldev->bars[i].start, &ctldev->bars[i].end, &ctldev->bars[i].len, + (flags & IORESOURCE_MEM) ? "MMIO" : + (flags & IORESOURCE_IO) ? "IO" : "UNKNOWN"); + } + + return 0; +} + +/** + * slash_ctldev_create_bar_dmabufs() - Create dma-buf exporters for MMIO BARs. + * @ctldev: Control device whose BARs to export. + * + * Only active MMIO BARs get a dma-buf; I/O-port BARs are skipped. + * The dma-buf lets userspace mmap the BAR for direct register access. + * + * Return: 0 on success, negative errno on first failure (some dmabufs + * may already have been created and must be cleaned up by the caller). + */ +static int slash_ctldev_create_bar_dmabufs(struct slash_ctldev *ctldev) +{ + int i; + struct dma_buf *dmabuf; + + dev_dbg(&ctldev->pdev->dev, "ctldev: creating dma-bufs for MMIO BARs\n"); + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + if (!ctldev->bars[i].active || !ctldev->bars[i].mmio) { + continue; + } + + dmabuf = slash_bar_dmabuf_create(ctldev->pdev, i); + if (IS_ERR(dmabuf)) { + dev_err(&ctldev->pdev->dev, "ctldev: BAR%d dmabuf create failed: %ld\n", i, PTR_ERR(dmabuf)); + return PTR_ERR(dmabuf); + } + + ctldev->bars[i].dmabuf = dmabuf; + dev_dbg(&ctldev->pdev->dev, "ctldev: BAR%d dmabuf created\n", i); + } + + return 0; +} + +/** + * slash_ctldev_id_get() - Look up or allocate a stable number for a BDF. + * @bdf: Full PCI BDF string (e.g. "0000:61:00.2") from pci_name(). + * + * Called from probe. Returns the number permanently associated with @bdf, + * allocating a new one if this BDF is seen for the first time. Also marks + * the entry as in_use = true. + * + * If an existing entry is found with in_use already set, the device was + * never properly unbound before probe was called again — this indicates a + * kernel PCI driver bug. The function logs a loud error and returns + * -EBUSY so that probe aborts without touching the device. + * + * Return: non-negative stable device number on success, negative errno on + * failure (-ENOMEM if allocation fails, -EBUSY if already in use). + */ +static int slash_ctldev_id_get(const char *bdf) +{ + struct slash_ctldev_id_entry *entry; + int number; + + mutex_lock(&slash_ctldev_id_map_lock); + + list_for_each_entry(entry, &slash_ctldev_id_map, node) { + if (strcmp(entry->bdf, bdf) != 0) + continue; + + if (entry->in_use) { + /* + * This BDF is already marked in_use. The kernel should + * never call probe for a device that is still bound — + * if this fires, something has gone badly wrong in the + * PCI driver infrastructure. + */ + pr_err("slash_ctldev: BUG: probe called for %s but entry is already in_use " + "(number=%d); refusing to bind\n", bdf, entry->number); + mutex_unlock(&slash_ctldev_id_map_lock); + return -EBUSY; + } + + entry->in_use = true; + number = entry->number; + mutex_unlock(&slash_ctldev_id_map_lock); + pr_info("slash_ctldev: reusing number %d for %s\n", number, bdf); + return number; + } + + /* First time we've seen this BDF — allocate a fresh entry. */ + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) { + mutex_unlock(&slash_ctldev_id_map_lock); + return -ENOMEM; + } + + strscpy(entry->bdf, bdf, sizeof(entry->bdf)); + entry->number = atomic_inc_return(&slash_ctldev_devcount) - 1; + entry->in_use = true; + list_add_tail(&entry->node, &slash_ctldev_id_map); + + number = entry->number; + mutex_unlock(&slash_ctldev_id_map_lock); + + pr_info("slash_ctldev: assigned number %d to %s\n", number, bdf); + return number; +} + +/** + * slash_ctldev_id_release() - Mark a BDF's entry as no longer in use. + * @bdf: Full PCI BDF string passed to the matching slash_ctldev_id_get() call. + * + * Called from remove. Clears in_use so that the next probe for the same + * BDF can reuse the stored number. The entry itself is not freed — it must + * persist so the number remains stable across hotplug cycles. + * + * If no entry exists for @bdf (should never happen after a successful probe), + * the call is a no-op and a warning is logged. + */ +static void slash_ctldev_id_release(const char *bdf) +{ + struct slash_ctldev_id_entry *entry; + + mutex_lock(&slash_ctldev_id_map_lock); + + list_for_each_entry(entry, &slash_ctldev_id_map, node) { + if (strcmp(entry->bdf, bdf) != 0) + continue; + + entry->in_use = false; + mutex_unlock(&slash_ctldev_id_map_lock); + pr_info("slash_ctldev: released number %d for %s\n", entry->number, bdf); + return; + } + + /* Should be unreachable: remove without a prior successful probe. */ + pr_warn("slash_ctldev: WARNING: release called for %s but no entry found\n", bdf); + mutex_unlock(&slash_ctldev_id_map_lock); +} + +/** + * slash_ctldev_create_misc() - Register the misc character device. + * @ctldev: Control device to register. + * + * Creates /dev/slash_ctl with a stable index derived from the BDF-to-number + * map. The sysfs name includes the PCI BDF for identification; the /dev node + * uses a numeric suffix that is stable across hotplug remove+rescan cycles. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_ctldev_create_misc(struct slash_ctldev *ctldev) +{ + int err, id; + const char *name, *nodename; + + /* sysfs name: includes PCI BDF (e.g. "slash_ctl_0000:03:00.2"). */ + name = kasprintf(GFP_KERNEL, SLASH_CTLDEV_NAME_FMT, pci_name(ctldev->pdev)); + if (!name) { + dev_err(&ctldev->pdev->dev, "ctldev: kasprintf(name) failed\n"); + return -ENOMEM; + } + + /* /dev node name: stable numeric index from BDF-to-number map. */ + id = slash_ctldev_id_get(pci_name(ctldev->pdev)); + if (id < 0) { + dev_err(&ctldev->pdev->dev, "ctldev: id_get failed: %d\n", id); + err = id; + goto err_free_name; + } + + nodename = kasprintf(GFP_KERNEL, SLASH_CTLDEV_NODENAME_FMT, id); + if (!nodename) { + dev_err(&ctldev->pdev->dev, "ctldev: kasprintf(nodename) failed\n"); + err = -ENOMEM; + goto err_release_id; + } + + ctldev->misc.minor = MISC_DYNAMIC_MINOR; + ctldev->misc.name = name; + ctldev->misc.fops = &slash_ctldev_fops; + ctldev->misc.parent = &ctldev->pdev->dev; + ctldev->misc.nodename = nodename; + ctldev->misc.mode = SLASH_CTLDEV_MODE; + + err = misc_register(&ctldev->misc); + if (err) { + dev_err(&ctldev->pdev->dev, "ctldev: misc_register failed: %d\n", err); + goto err_free_nodename; + } + + return 0; + +err_free_nodename: + kfree(nodename); + +err_release_id: + /* id_get succeeded and set in_use; undo that. */ + slash_ctldev_id_release(pci_name(ctldev->pdev)); + +err_free_name: + kfree(name); + + return err; +} + +void slash_ctldev_destroy(struct pci_dev *pdev) +{ + struct slash_ctldev *ctldev = pci_get_drvdata(pdev); + + dev_info(&pdev->dev, "ctldev: destroying control device\n"); + slash_ctldev_destroy_misc(ctldev); + slash_ctldev_destroy_dmabufs(ctldev); + + kfree(ctldev); +} + +static void slash_ctldev_destroy_misc(struct slash_ctldev *ctldev) +{ + dev_dbg(&ctldev->pdev->dev, "ctldev: deregistering misc device\n"); + misc_deregister(&ctldev->misc); + slash_ctldev_id_release(pci_name(ctldev->pdev)); + kfree(ctldev->misc.name); + kfree(ctldev->misc.nodename); + ctldev->misc.name = NULL; + ctldev->misc.nodename = NULL; +} + +static void slash_ctldev_destroy_dmabufs(struct slash_ctldev *ctldev) +{ + int i; + + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + if (ctldev->bars[i].dmabuf) { + dev_dbg(&ctldev->pdev->dev, "ctldev: destroying BAR%d dmabuf\n", i); + slash_bar_dmabuf_destroy(ctldev->bars[i].dmabuf); + } + } +} + +/** + * slash_ctldev_fop_ioctl() - Handle control device ioctls. + * @file: Open file for the misc device. + * @op: ioctl command number. + * @arg: Pointer to the user-space ioctl struct. + * + * Dispatches to one of: + * - GET_BAR_INFO: Return BAR properties (start, size, usability). + * - GET_BAR_FD: Return a dma-buf fd for mmap'ing a BAR. + * - GET_DEVICE_INFO: Return PCI identity (BDF, vendor/device IDs). + * + * All ioctls use the size-versioning pattern described in the file + * header. + * + * Return: 0 (or positive fd for GET_BAR_FD) on success, negative errno on failure. + */ +static long slash_ctldev_fop_ioctl(struct file *file, unsigned int op, unsigned long arg) +{ + struct miscdevice *misc = file->private_data; + struct pci_dev *pdev = to_pci_dev(misc->parent); + struct slash_ctldev *ctldev = pci_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "ctldev: ioctl op=0x%x\n", op); + switch(op) { + case SLASH_CTLDEV_IOCTL_GET_BAR_INFO: { + struct slash_ioctl_bar_info bar_info = {0}; + struct slash_ctldev_bar *bar = NULL; + u32 bar_info_alleged_size; + size_t copy_size; + + /* + * Size-versioning: read the leading size field first to + * determine how much data the caller provided. + */ + if (copy_from_user(&bar_info_alleged_size, (void __user *)arg, sizeof(bar_info_alleged_size))) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO copy_from_user failed\n"); + return -EFAULT; + } + + if (bar_info_alleged_size < SLASH_IOCTL_BAR_INFO_MIN_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO size too small (%u)\n", bar_info_alleged_size); + return -EINVAL; + } + + /* + * Copy the smaller of (user struct, kernel struct), then + * zero-fill any kernel fields that the user struct doesn't + * cover. This handles older userspace gracefully. + */ + copy_size = min_t(size_t, bar_info_alleged_size, sizeof(bar_info)); + if (copy_from_user(&bar_info, (void __user *)arg, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO copy_from_user failed\n"); + return -EFAULT; + } + if (copy_size < sizeof(bar_info)) { + memset((u8 *)&bar_info + copy_size, 0, sizeof(bar_info) - copy_size); + } + + if (bar_info.bar_number < 0 || bar_info.bar_number >= PCI_STD_NUM_BARS) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO invalid BAR %d\n", bar_info.bar_number); + return -EINVAL; + } + + bar = &ctldev->bars[bar_info.bar_number]; + + /* Populate output fields. */ + bar_info.usable = bar->active && bar->mmio; + bar_info.in_use = 0; + bar_info.start_address = bar->start; + bar_info.length = bar->len; + + /* Tell userspace the kernel's struct size for version negotiation. */ + bar_info.size = sizeof(bar_info); + + if (bar_info_alleged_size < SLASH_IOCTL_BAR_INFO_RESPONSE_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO response size too small (%u)\n", bar_info_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, bar_info_alleged_size, sizeof(bar_info)); + if (copy_to_user((void __user *)arg, &bar_info, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO copy_to_user failed\n"); + return -EFAULT; + } + /* + * If the user struct is larger than what we know, zero-fill + * the tail. This ensures newer userspace sees zeroed fields + * when talking to an older kernel (forward compatibility). + */ + if (bar_info_alleged_size > sizeof(bar_info)) { + size_t extra = bar_info_alleged_size - sizeof(bar_info); + void __user *dst = (void __user *)((unsigned long)arg + sizeof(bar_info)); + + if (clear_user(dst, extra)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_INFO clear_user failed\n"); + return -EFAULT; + } + } + + return 0; + } + + case SLASH_CTLDEV_IOCTL_GET_BAR_FD: { + struct slash_ioctl_bar_fd_request fd_request = {0}; + struct slash_ctldev_bar *bar = NULL; + int ret; + u32 fd_request_alleged_size; + size_t copy_size; + + /* + * Access control is enforced by device-node permissions + * (udev: slash_ctl* is 0600, owned by vrtd:vrtd). + * No capability check is needed here or at mmap() time — + * the dma-buf mmap handler uses fault-based vmf_insert_pfn() + * which does not require CAP_SYS_RAWIO. + */ + + /* Size-versioning: same pattern as GET_BAR_INFO above. */ + if (copy_from_user(&fd_request_alleged_size, (void __user *)arg, sizeof(fd_request_alleged_size))) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD copy_from_user failed\n"); + return -EFAULT; + } + + if (fd_request_alleged_size < SLASH_IOCTL_BAR_FD_MIN_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD size too small (%u)\n", fd_request_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, fd_request_alleged_size, sizeof(fd_request)); + if (copy_from_user(&fd_request, (void __user *)arg, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD copy_from_user failed\n"); + return -EFAULT; + } + if (copy_size < sizeof(fd_request)) { + memset((u8 *)&fd_request + copy_size, 0, sizeof(fd_request) - copy_size); + } + + if (fd_request.bar_number < 0 || fd_request.bar_number >= PCI_STD_NUM_BARS) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD invalid BAR %d\n", fd_request.bar_number); + return -EINVAL; + } + if (fd_request.flags & ~O_CLOEXEC) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD invalid flags 0x%x\n", fd_request.flags); + return -EINVAL; + } + + bar = &ctldev->bars[fd_request.bar_number]; + + if (!bar->dmabuf) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD BAR%d has no dmabuf\n", fd_request.bar_number); + return -ENODEV; + } + + fd_request.length = bar->len; + fd_request.size = sizeof(fd_request); + + if (fd_request_alleged_size < SLASH_IOCTL_BAR_FD_RESPONSE_SIZE) { + dev_warn(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD response size too small (%u)\n", fd_request_alleged_size); + return -EINVAL; + } + + copy_size = min_t(size_t, fd_request_alleged_size, sizeof(fd_request)); + if (copy_to_user((void __user *)arg, &fd_request, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD copy_to_user failed\n"); + return -EFAULT; + } + if (fd_request_alleged_size > sizeof(fd_request)) { + size_t extra = fd_request_alleged_size - sizeof(fd_request); + void __user *dst = (void __user *)((unsigned long)arg + sizeof(fd_request)); + + if (clear_user(dst, extra)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_BAR_FD clear_user failed\n"); + return -EFAULT; + } + } + + /* + * Take an extra reference on the dma-buf before creating the + * fd. The fd will hold this reference; if dma_buf_fd() fails + * we must drop it ourselves. + */ + get_dma_buf(bar->dmabuf); + ret = dma_buf_fd(bar->dmabuf, fd_request.flags); + if (ret < 0) { + dev_err(&pdev->dev, "ctldev: GET_BAR_FD dma_buf_fd failed: %d\n", ret); + dma_buf_put(bar->dmabuf); + return ret; + } + + /* The fd number is returned as the ioctl return value. */ + dev_dbg(&pdev->dev, "ctldev: GET_BAR_FD BAR%d -> fd %d\n", fd_request.bar_number, ret); + return ret; + } + + case SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO: { + struct slash_ioctl_device_info info; + u32 user_size = 0; + size_t copy_size; + + if (copy_from_user(&user_size, (void __user *)arg, sizeof(user_size))) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO copy_from_user failed\n"); + return -EFAULT; + } + + memset(&info, 0, sizeof(info)); + info.size = sizeof(info); + + strscpy(info.bdf, pci_name(pdev), sizeof(info.bdf)); + info.vendor_id = pdev->vendor; + info.device_id = pdev->device; + info.subsystem_vendor_id = pdev->subsystem_vendor; + info.subsystem_device_id = pdev->subsystem_device; + + copy_size = min_t(size_t, user_size, sizeof(info)); + if (copy_to_user((void __user *)arg, &info, copy_size)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO copy_to_user failed\n"); + return -EFAULT; + } + if (user_size > sizeof(info)) { + size_t extra = user_size - sizeof(info); + void __user *dst = (void __user *)((unsigned long)arg + sizeof(info)); + + if (clear_user(dst, extra)) { + dev_err(&pdev->dev, "ctldev: SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO clear_user failed\n"); + return -EFAULT; + } + } + + return 0; + } + + default: + dev_warn(&pdev->dev, "ctldev: unknown ioctl op=0x%x\n", op); + return -ENOTTY; + } +} diff --git a/driver/slash_ctldev.h b/driver/slash_ctldev.h new file mode 100644 index 00000000..efa72579 --- /dev/null +++ b/driver/slash_ctldev.h @@ -0,0 +1,89 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_ctldev.h + * + * Control device interface for the SLASH kernel module. + * + * Each probed PF2 device gets a control misc device (/dev/slash_ctl) + * that exposes device identity, BAR properties, and dma-buf-backed BAR + * mappings to userspace via ioctl. + */ + +#ifndef SLASH_CTLDEV_H +#define SLASH_CTLDEV_H + +#include +#include +#include + +/** + * struct slash_ctldev_bar - Per-BAR metadata cached during probe. + * @active: 1 if the BAR is present (has a non-zero start address). + * @mmio: 1 if the BAR is a memory-mapped I/O region (IORESOURCE_MEM). + * I/O-port BARs are tracked but not exported to userspace. + * @start: Physical/bus start address of the BAR. + * @end: Physical/bus end address of the BAR (inclusive). + * @len: Size of the BAR in bytes. + * @dmabuf: dma-buf exporter for this BAR, or NULL if the BAR is not + * MMIO. Created during probe, destroyed during remove. + */ +struct slash_ctldev_bar { + unsigned int active : 1; + unsigned int mmio : 1; + resource_size_t start; + resource_size_t end; + resource_size_t len; + + struct dma_buf *dmabuf; +}; + +/** + * struct slash_ctldev - Per-device control device state. + * @pdev: Back-pointer to the PCI device this control device manages. + * @misc: Kernel misc device registered as /dev/slash_ctl. + * @bars: Cached BAR metadata for all standard PCI BARs (0-5). + * + * Allocated during probe, stored via pci_set_drvdata(), and freed + * during remove. + */ +struct slash_ctldev { + struct pci_dev *pdev; + struct miscdevice misc; + struct slash_ctldev_bar bars[PCI_STD_NUM_BARS]; +}; + +/** + * slash_ctldev_create() - Create a control device for a PCI function. + * @pdev: PCI device to create the control device for. + * + * Probes BARs, creates dma-buf exporters for MMIO BARs, and registers + * a misc device. The control device state is stored as PCI driver + * data on @pdev. + * + * Return: 0 on success, negative errno on failure. + */ +int slash_ctldev_create(struct pci_dev *pdev); + +/** + * slash_ctldev_destroy() - Destroy a control device. + * @pdev: PCI device whose control device should be torn down. + * + * Deregisters the misc device, destroys dma-buf exporters, and frees + * the control device state. + */ +void slash_ctldev_destroy(struct pci_dev *pdev); + +#endif /* SLASH_CTLDEV_H */ diff --git a/driver/slash_dmabuf.c b/driver/slash_dmabuf.c new file mode 100644 index 00000000..36f3ed53 --- /dev/null +++ b/driver/slash_dmabuf.c @@ -0,0 +1,309 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_dmabuf.c + * + * DMA-buf exporter for PCI BAR regions. + * + * This file implements a dma-buf wrapper around a PCI BAR, allowing + * userspace to obtain a file descriptor (via the control device ioctl) + * and mmap the BAR for direct MMIO register access. + * + * Only userspace mmap is supported. Kernel-side device attachments + * (the normal dma-buf import path) are intentionally rejected because + * a PCI BAR is I/O memory, not DMA-able system RAM. The dma-buf + * framework is used here solely for its fd-based lifetime management + * and mmap infrastructure. + * + * Cache attribute selection: + * - **Prefetchable BARs** → write-combine mapping (pgprot_writecombine). + * Suitable for frame buffers or bulk data regions where write + * coalescing improves throughput. + * - **Non-prefetchable BARs** → device/uncached mapping (pgprot_device). + * Required for control registers where every write must hit the + * device immediately and in order. + */ + +#include "slash_dmabuf.h" + +#include "slash.h" +#include "slash_compat.h" + +#include +#include +#include +#include +#include + +/** + * struct slash_bar_dmabuf_data - Private data attached to each BAR dma-buf. + * @bar_number: Which PCI BAR (0-5) this dma-buf represents. + * @len: Size of the BAR region in bytes. + * @pdev: PCI device owning the BAR. Held via pci_dev_get() + * for the lifetime of this struct. + */ +struct slash_bar_dmabuf_data { + int bar_number; + resource_size_t len; + + struct pci_dev *pdev; +}; + +/* + * We only support userspace mmaps of the BAR; importing into other + * devices is intentionally rejected because a PCI BAR is not system + * memory — it cannot be scatter-gathered or DMA-mapped by another + * device. + */ +static int slash_bar_dmabuf_attach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) +{ + dev_warn(attach->dev, "%s: device attachments are not supported for BAR dmabuf", SLASH_NAME); + return -EOPNOTSUPP; +} + +static void slash_bar_dmabuf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) +{ + dev_dbg(attach->dev, "slash: dmabuf detach (noop)\n"); +} + +static struct sg_table *slash_bar_dmabuf_map(struct dma_buf_attachment *attach, + enum dma_data_direction dir) +{ + dev_dbg(attach->dev, "slash: dmabuf map requested -> not supported\n"); + return ERR_PTR(-EOPNOTSUPP); +} + +static void slash_bar_dmabuf_unmap(struct dma_buf_attachment *attach, + struct sg_table *sgl, enum dma_data_direction dir) +{ + dev_dbg(attach->dev, "slash: dmabuf unmap (noop)\n"); +} + +/** + * slash_bar_dmabuf_fault() - Page-fault handler for BAR mappings. + * @vmf: Fault information provided by the kernel. + * + * Called on the first access to each page in the VMA. Computes the + * physical page frame number (PFN) for the faulting address within + * the PCI BAR and inserts it into the page tables via vmf_insert_pfn(). + * + * This avoids io_remap_pfn_range(), whose remap_pfn_range() security + * path requires CAP_SYS_RAWIO. The fault-based approach (VM_PFNMAP + + * vmf_insert_pfn) is the standard pattern used by DRM/GPU and VFIO + * drivers for mapping device I/O memory to unprivileged userspace. + * + * Lifetime safety: priv->pdev is held via pci_dev_get() for the lifetime + * of the dma-buf. The VMA holds a file reference on the dma-buf, so priv + * and priv->pdev remain valid for any fault during the VMA's lifetime. + * After device removal pci_resource_start() returns stale-but-valid cached + * values from the pci_dev struct; MMIO reads will return 0xFFFFFFFF (PCIe + * completion timeout) which is the expected degraded behavior. + * + * Return: VM_FAULT_NOPAGE on success, VM_FAULT_SIGBUS on out-of-range + * access or insertion failure. + */ +static vm_fault_t slash_bar_dmabuf_fault(struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; + struct slash_bar_dmabuf_data *priv = vma->vm_private_data; + unsigned long page_index; + unsigned long obj_pgoff; + resource_size_t bar_start; + unsigned long pfn; + + /* Page offset within the VMA (0 for the first page of the mapping). */ + page_index = (vmf->address - vma->vm_start) >> PAGE_SHIFT; + + /* BAR-relative page offset: mmap offset + position within mapping. */ + obj_pgoff = vma->vm_pgoff + page_index; + + /* Bounds check: do not map beyond the physical BAR. */ + if ((obj_pgoff << PAGE_SHIFT) >= priv->len) + return VM_FAULT_SIGBUS; + + bar_start = pci_resource_start(priv->pdev, priv->bar_number); + pfn = (bar_start >> PAGE_SHIFT) + obj_pgoff; + + return vmf_insert_pfn(vma, vmf->address, pfn); +} + +static const struct vm_operations_struct slash_bar_dmabuf_vm_ops = { + .fault = slash_bar_dmabuf_fault, +}; + +/** + * slash_bar_dmabuf_mmap() - Set up a BAR region for fault-based mapping. + * @dmabuf: The BAR dma-buf being mapped. + * @vma: The VMA describing the mapping request. + * + * Configures the VMA with appropriate flags, cache attributes, and a + * custom vm_operations_struct whose .fault handler uses vmf_insert_pfn() + * to lazily insert PFNs on first access. This avoids + * io_remap_pfn_range() and its CAP_SYS_RAWIO requirement, allowing + * unprivileged userspace to mmap BAR regions. + * + * Cache attribute selection: + * - Prefetchable BAR → write-combine (pgprot_writecombine): allows + * the CPU to coalesce writes for better throughput on bulk data BARs. + * - Non-prefetchable BAR → device/uncached (pgprot_device): strict + * ordering for control registers. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_bar_dmabuf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) +{ + struct slash_bar_dmabuf_data *priv = dmabuf->priv; + unsigned long size = vma->vm_end - vma->vm_start; + u64 offset = (u64)vma->vm_pgoff << PAGE_SHIFT; + bool wc; + + /* Ensure the requested range lies fully within the BAR. */ + if (offset > priv->len || size > priv->len - offset) + return -EINVAL; + + /* + * VM_PFNMAP — raw PFN mapping, required for vmf_insert_pfn(). + * VM_IO — I/O memory (blocks /proc/pid/mem, core dump). + * VM_DONTDUMP — explicit core-dump exclusion (redundant w/ VM_IO). + * VM_DONTEXPAND — prevents mremap beyond BAR boundary. + * VM_DONTCOPY — do not inherit across fork(); BAR register + * mappings should not be silently shared with children. + */ + slash_vm_flags_set(vma, VM_PFNMAP | VM_IO | VM_DONTDUMP | + VM_DONTEXPAND | VM_DONTCOPY); + + wc = !!(pci_resource_flags(priv->pdev, priv->bar_number) & IORESOURCE_PREFETCH); + vma->vm_page_prot = wc ? pgprot_writecombine(vma->vm_page_prot) + : pgprot_device(vma->vm_page_prot); + + vma->vm_ops = &slash_bar_dmabuf_vm_ops; + vma->vm_private_data = priv; + + dev_dbg(&priv->pdev->dev, + "slash: mmap BAR%d wc=%d pgoff=0x%lx len=0x%lx (fault-based)\n", + priv->bar_number, wc, vma->vm_pgoff, size); + + return 0; +} + +/** + * slash_bar_dmabuf_release() - Free resources when all references are dropped. + * @dmabuf: The BAR dma-buf being released. + * + * Drops the PCI device reference taken in slash_bar_dmabuf_create() + * and frees the private data. + */ +static void slash_bar_dmabuf_release(struct dma_buf *dmabuf) +{ + struct slash_bar_dmabuf_data *priv = dmabuf->priv; + + dev_dbg(&priv->pdev->dev, "slash: dmabuf release (BAR%d)\n", priv->bar_number); + + pci_dev_put(priv->pdev); + kfree(priv); +} + +static const struct dma_buf_ops slash_bar_dmabuf_ops = { + .attach = slash_bar_dmabuf_attach, + .detach = slash_bar_dmabuf_detach, + .map_dma_buf = slash_bar_dmabuf_map, + .unmap_dma_buf = slash_bar_dmabuf_unmap, + .mmap = slash_bar_dmabuf_mmap, + .release = slash_bar_dmabuf_release, +}; + +/** + * slash_bar_dmabuf_create() - Export a PCI BAR as a dma-buf. + * @pdev: PCI device owning the BAR. + * @bar_number: BAR index (0-5). Must be present and MMIO. + * + * Allocates private state, takes a reference on @pdev, and registers a + * dma-buf exporter. The DEFINE_DMA_BUF_EXPORT_INFO macro initializes + * the export info struct with sensible defaults; we override ops, size, + * flags, priv, and exp_name. + * + * Return: Pointer to the new dma_buf on success, ERR_PTR on failure. + */ +struct dma_buf *slash_bar_dmabuf_create(struct pci_dev *pdev, int bar_number) +{ + long err; + resource_size_t len; + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct dma_buf *dmabuf; + struct slash_bar_dmabuf_data *priv; + + if (bar_number < 0 || bar_number >= PCI_STD_NUM_BARS) { + dev_err(&pdev->dev, "slash: invalid BAR %d\n", bar_number); + return ERR_PTR(-EINVAL); + } + if (!pci_resource_start(pdev, bar_number)) { + dev_err(&pdev->dev, "slash: BAR%d not present\n", bar_number); + return ERR_PTR(-ENODEV); + } + if ((pci_resource_flags(pdev, bar_number) & IORESOURCE_MEM) == 0) { + dev_err(&pdev->dev, "slash: BAR%d is not MMIO\n", bar_number); + return ERR_PTR(-ENODEV); + } + + len = pci_resource_len(pdev, bar_number); + + dev_dbg(&pdev->dev, "slash: exporting BAR%d as dma-buf (size=%pa)\n", bar_number, &len); + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "slash: kzalloc(priv) failed\n"); + return ERR_PTR(-ENOMEM); + } + + priv->bar_number = bar_number; + priv->len = len; + /* Hold a PCI device reference for the lifetime of the dma-buf. */ + priv->pdev = pci_dev_get(pdev); + + exp_info.ops = &slash_bar_dmabuf_ops; + exp_info.size = len; + exp_info.flags = O_RDWR; + exp_info.priv = priv; + exp_info.exp_name = SLASH_NAME; + + dmabuf = dma_buf_export(&exp_info); + if (IS_ERR(dmabuf)) { + err = PTR_ERR(dmabuf); + dev_err(&pdev->dev, "slash: dma_buf_export failed: %ld\n", err); + goto err_free_priv; + } + + dev_info(&pdev->dev, "slash: BAR%d exported as dma-buf (size=%pa)\n", bar_number, &len); + return dmabuf; + +err_free_priv: + pci_dev_put(priv->pdev); + kfree(priv); + + return ERR_PTR(err); +} + +/** + * slash_bar_dmabuf_destroy() - Release the driver's reference on a BAR dma-buf. + * @dmabuf: dma-buf returned by slash_bar_dmabuf_create(). + * + * Drops one reference. The dma-buf (and its private data) are actually + * freed only when the last holder — including any userspace fd — closes. + */ +void slash_bar_dmabuf_destroy(struct dma_buf *dmabuf) +{ + pr_debug("slash: dmabuf_destroy()\n"); + dma_buf_put(dmabuf); +} diff --git a/driver/slash_dmabuf.h b/driver/slash_dmabuf.h new file mode 100644 index 00000000..18bac8f2 --- /dev/null +++ b/driver/slash_dmabuf.h @@ -0,0 +1,56 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_dmabuf.h + * + * DMA-buf exporter for PCI BAR regions. + * + * Provides a dma-buf wrapper around a PCI BAR so that userspace can + * obtain a file descriptor and mmap the BAR for direct MMIO access. + * Only userspace mmap is supported; kernel-side device attachment is + * intentionally rejected because a PCI BAR is device I/O memory, not + * system RAM. + */ + +#ifndef SLASH_DMABUF_H +#define SLASH_DMABUF_H + +#include +#include + +/** + * slash_bar_dmabuf_create() - Export a PCI BAR as a dma-buf. + * @pdev: PCI device owning the BAR. + * @bar_number: BAR index (0-5). Must be a valid MMIO BAR. + * + * Creates a dma-buf exporter backed by the physical address range of + * the specified BAR. Takes a reference on @pdev (via pci_dev_get()) + * that is released when the dma-buf is freed. + * + * Return: Pointer to the new dma_buf on success, ERR_PTR on failure. + */ +struct dma_buf *slash_bar_dmabuf_create(struct pci_dev *pdev, int bar_number); + +/** + * slash_bar_dmabuf_destroy() - Release a BAR dma-buf. + * @dmabuf: dma-buf returned by slash_bar_dmabuf_create(). + * + * Drops the driver's reference on the dma-buf. The underlying + * resources (PCI device reference, private data) are freed when the + * last user closes their fd / drops their reference. + */ +void slash_bar_dmabuf_destroy(struct dma_buf *dmabuf); + +#endif /* SLASH_DMABUF_H */ diff --git a/driver/slash_hotplug.c b/driver/slash_hotplug.c new file mode 100644 index 00000000..2d0d0051 --- /dev/null +++ b/driver/slash_hotplug.c @@ -0,0 +1,498 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_hotplug.c + * + * PCIe hot-plug and reset subsystem for the SLASH kernel module. + * + * This file manages the PCIe-level lifecycle of SLASH FPGA devices, + * providing four operations via /dev/slash_hotplug: + * + * - **RESCAN** — rescan all PCI root buses to discover new devices. + * - **REMOVE** — remove a specific device from the PCI bus. + * - **TOGGLE_SBR** — assert and deassert a Secondary Bus Reset on + * the device's immediate upstream bridge. + * - **HOTPLUG** — atomic remove + rescan cycle on the device's + * immediate parent bus. + * + * These operations are essential for FPGA reconfiguration workflows. + * When a new bitstream is loaded, the FPGA's PCI identity and BAR + * layout may change, requiring the device to be removed from the bus, + * reset via SBR, and re-enumerated. + * + * A typical reconfiguration flow: + * 1. REMOVE each PCI function (PF0, PF1, PF2 ...) + * 2. TOGGLE_SBR to reset the device + * 3. Wait in userspace for the FPGA to re-initialize + * 4. RESCAN to discover the new configuration + * + * All ioctls that operate on a specific device require an explicit + * BDF string in the request. + */ + +#include "slash_hotplug_driver.h" + +#include "slash.h" + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLASH_HOTPLUG_MODE 0600 + +/** + * slash_hotplug_copy_request() - Copy and sanitize a hotplug request from userspace. + * @arg: Userspace pointer to the request struct. + * @req: Kernel-side buffer to populate. + * + * NUL-terminates and trims whitespace from the BDF string. + * + * Return: 0 on success, -EFAULT or -EINVAL on failure. + */ +static int slash_hotplug_copy_request(unsigned long arg, struct slash_hotplug_device_request *req) +{ + pr_debug("slash_hotplug: copy_request: copying %zu bytes from userspace\n", sizeof(*req)); + + if (copy_from_user(req, (void __user *)arg, sizeof(*req))) { + pr_err("slash_hotplug: copy_request: copy_from_user failed\n"); + return -EFAULT; + } + + pr_debug("slash_hotplug: copy_request: size=%u bdf='%.*s'\n", + req->size, (int)(SLASH_HOTPLUG_BDF_LEN - 1), req->bdf); + + if (req->size && req->size < sizeof(*req)) { + pr_err("slash_hotplug: request size %u too small (expected %zu)\n", + req->size, sizeof(*req)); + return -EINVAL; + } + + if (!req->size) + req->size = sizeof(*req); + + /* Defend against unterminated strings from userspace. */ + req->bdf[SLASH_HOTPLUG_BDF_LEN - 1] = '\0'; + strim(req->bdf); + + if (!req->bdf[0]) { + pr_err("slash_hotplug: empty BDF in request\n"); + return -EINVAL; + } + + pr_debug("slash_hotplug: copy_request: sanitized BDF='%s'\n", req->bdf); + return 0; +} + +/** + * slash_hotplug_get_pci_dev() - Look up a PCI device by BDF string. + * @bdf: BDF string in "DDDD:BB:SS.F" hex format. + * @pdev_out: On success, receives a reference-counted pci_dev pointer. + * Caller must call pci_dev_put() when done. + * + * Return: 0 on success, -EINVAL if the BDF is malformed, -ENODEV if + * the device is not present. + */ +static int slash_hotplug_get_pci_dev(const char *bdf, struct pci_dev **pdev_out) +{ + int domain, bus, slot, func; + struct pci_dev *pdev; + + if (sscanf(bdf, "%x:%x:%x.%x", &domain, &bus, &slot, &func) != 4) { + pr_err("slash_hotplug: malformed BDF '%s' (expected DDDD:BB:SS.F)\n", bdf); + return -EINVAL; + } + + pr_info("slash_hotplug: get_pci_dev: looking up %s (domain=%04x bus=%02x slot=%02x func=%x)\n", + bdf, domain, bus, slot, func); + + pdev = pci_get_domain_bus_and_slot(domain, bus, PCI_DEVFN(slot, func)); + if (!pdev) { + pr_err("slash_hotplug: device %s not present in PCI subsystem\n", bdf); + return -ENODEV; + } + + pr_info("slash_hotplug: get_pci_dev: found %s\n", pci_name(pdev)); + *pdev_out = pdev; + return 0; +} + +/** + * slash_hotplug_handle_rescan() - Rescan all PCI root buses. + * + * Discovers any new or reconfigured devices on every root bus. + * + * Return: Always 0. + */ +static int slash_hotplug_handle_rescan(void) +{ + struct pci_bus *bus; + int bus_count = 0; + + pr_info("slash_hotplug: rescan: acquiring pci_lock_rescan_remove\n"); + pci_lock_rescan_remove(); + + list_for_each_entry(bus, &pci_root_buses, node) { + pr_info("slash_hotplug: rescan: scanning root bus %04x:%02x\n", + pci_domain_nr(bus), bus->number); + pci_rescan_bus(bus); + bus_count++; + } + + pci_unlock_rescan_remove(); + pr_info("slash_hotplug: rescan: complete (%d root bus(es) scanned)\n", bus_count); + + return 0; +} + +/** + * slash_hotplug_handle_remove() - Remove a device from the PCI bus. + * @bdf: BDF string identifying the device to remove. + * + * Stops the device, tears down its driver bindings, and removes it + * from the PCI hierarchy. The device can be re-discovered later via + * a bus rescan. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_hotplug_handle_remove(const char *bdf) +{ + struct pci_dev *pdev; + int ret; + + pr_info("slash_hotplug: remove: starting for BDF %s\n", bdf); + + ret = slash_hotplug_get_pci_dev(bdf, &pdev); + if (ret) { + pr_err("slash_hotplug: remove: BDF %s unavailable (%d)\n", bdf, ret); + return ret; + } + + if (pdev->bus && pdev->bus->self) { + u16 bridge_ctrl; + pci_read_config_word(pdev->bus->self, PCI_BRIDGE_CONTROL, &bridge_ctrl); + pr_info("slash_hotplug: remove: %s upstream bridge=%s bridge_ctrl=0x%04x before remove\n", + pci_name(pdev), pci_name(pdev->bus->self), bridge_ctrl); + } + + pr_info("slash_hotplug: remove: acquiring pci_lock_rescan_remove\n"); + pci_lock_rescan_remove(); + + pr_info("slash_hotplug: remove: clearing bus master for %s\n", pci_name(pdev)); + pci_clear_master(pdev); + + pr_info("slash_hotplug: remove: calling pci_stop_and_remove_bus_device for %s\n", pci_name(pdev)); + pci_stop_and_remove_bus_device(pdev); + + pci_unlock_rescan_remove(); + pr_info("slash_hotplug: remove: released pci_lock_rescan_remove\n"); + + pci_dev_put(pdev); + pr_info("slash_hotplug: remove: %s complete\n", bdf); + + return 0; +} + +/** + * slash_hotplug_handle_toggle_sbr() - Perform a Secondary Bus Reset. + * @bdf: BDF string identifying the device (or its former location). + * + * Locates the immediate upstream bridge for the given BDF and toggles + * the PCI_BRIDGE_CTL_BUS_RESET bit in the bridge's PCI_BRIDGE_CONTROL + * register. The sequence is: + * + * 1. Read the current bridge control register. + * 2. Assert SBR (set the BUS_RESET bit). + * 3. Wait 2 ms — the PCIe spec minimum reset hold time. + * 4. Deassert SBR (clear the BUS_RESET bit). + * + * The caller is responsible for waiting an appropriate settle time + * after this ioctl returns before rescanning the bus. + * + * Bridge resolution: + * The endpoint is typically removed before SBR is toggled, so we + * resolve the bridge via pci_find_bus() using the bus number from + * the BDF. Bus structures survive endpoint removal. The bridge + * is always the immediate parent (bus->self), never the root port. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_hotplug_handle_toggle_sbr(const char *bdf) +{ + struct pci_bus *ep_bus; + struct pci_dev *bridge; + int domain, bus_nr, slot, func; + int ret; + + pr_info("slash_hotplug: toggle_sbr: starting for BDF %s\n", bdf); + + if (sscanf(bdf, "%x:%x:%x.%x", &domain, &bus_nr, &slot, &func) != 4) { + pr_err("slash_hotplug: toggle_sbr: malformed BDF '%s'\n", bdf); + return -EINVAL; + } + + /* + * Hold pci_lock_rescan_remove() across the pci_find_bus() + pci_dev_get() + * pair. pci_find_bus() does not pin the returned pci_bus; without the + * lock, a concurrent bus removal could free ep_bus between the lookup and + * the dev_get, turning ep_bus->self into a use-after-free. The lock is + * dropped before pci_bridge_secondary_bus_reset() to avoid deadlocking + * with the PCI slot lock that the reset function acquires internally. + */ + pr_info("slash_hotplug: toggle_sbr: looking up bus (domain=%04x bus=%02x)\n", + domain, bus_nr); + pci_lock_rescan_remove(); + ep_bus = pci_find_bus(domain, bus_nr); + if (!ep_bus || !ep_bus->self) { + pci_unlock_rescan_remove(); + pr_err("slash_hotplug: toggle_sbr: no upstream bridge for %s\n", bdf); + return -ENODEV; + } + bridge = pci_dev_get(ep_bus->self); + pci_unlock_rescan_remove(); + + pr_info("slash_hotplug: toggle_sbr: bridge=%s bus=%02x\n", + pci_name(bridge), bus_nr); + + /* + * pci_bridge_secondary_bus_reset() saves and restores bridge config + * space (memory windows, bus numbers, ACS, ARI) and holds the proper + * PCI slot lock. This is essential for root ports whose memory-window + * configuration would otherwise be lost after an SBR. + * + * Available since kernel 5.9; guaranteed present on our minimum targets + * (RHEL 9 / Ubuntu 22.04, both ship kernel >= 5.14). + */ + ret = pci_bridge_secondary_bus_reset(bridge); + if (ret) { + pr_err("slash_hotplug: toggle_sbr: pci_bridge_secondary_bus_reset failed (%d)\n", ret); + goto out_put; + } + pr_info("slash_hotplug: toggle_sbr: pci_bridge_secondary_bus_reset OK\n"); + + /* + * Post-SBR link training delay. The PCIe spec requires at minimum + * 100 ms for link training after SBR deassertion; real FPGA hardware + * can take longer. 1000 ms provides margin for link instability seen + * on repeated resets where 300 ms was insufficient. + * Without this delay, config-space reads on root ports return 0xFFFF + * because the link is not yet trained. + * + * Userspace adds its own ~5 s wait for full FPGA re-initialisation; + * this 1000 ms covers the kernel-internal window between SBR + * deassertion and ioctl return. + */ + pr_info("slash_hotplug: toggle_sbr: waiting 1000 ms for PCIe link training\n"); + msleep(1000); + pr_info("slash_hotplug: toggle_sbr: post-SBR settle complete (1000 ms)\n"); + +out_put: + pci_dev_put(bridge); + if (!ret) + pr_info("slash_hotplug: toggle_sbr: %s complete\n", bdf); + return ret; +} + +/** + * slash_hotplug_handle_hotplug() - Perform a full hot-plug cycle. + * @bdf: BDF string identifying the device. + * + * Removes the device from the bus, then rescans the device's parent + * bus to re-enumerate it. This is an atomic remove-then-rescan, + * useful when the device identity hasn't changed but the kernel needs + * to rebind drivers. + * + * Note: this does **not** include an SBR. If the FPGA bitstream has + * changed and a reset is needed, call TOGGLE_SBR separately before + * HOTPLUG. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_hotplug_handle_hotplug(const char *bdf) +{ + struct pci_dev *pdev; + struct pci_bus *bus; + int ret; + + pr_info("slash_hotplug: hotplug: starting for BDF %s\n", bdf); + + ret = slash_hotplug_get_pci_dev(bdf, &pdev); + if (ret) { + pr_err("slash_hotplug: hotplug: BDF %s unavailable (%d)\n", bdf, ret); + return ret; + } + + bus = pdev->bus; + if (!bus) { + pr_err("slash_hotplug: hotplug: no parent bus for %s\n", pci_name(pdev)); + pci_dev_put(pdev); + return -ENODEV; + } + + pr_info("slash_hotplug: hotplug: parent bus %04x:%02x\n", + pci_domain_nr(bus), bus->number); + + pr_info("slash_hotplug: hotplug: acquiring pci_lock_rescan_remove\n"); + pci_lock_rescan_remove(); + + pr_info("slash_hotplug: hotplug: clearing bus master for %s\n", pci_name(pdev)); + pci_clear_master(pdev); + + pr_info("slash_hotplug: hotplug: calling pci_stop_and_remove_bus_device for %s\n", pci_name(pdev)); + pci_stop_and_remove_bus_device(pdev); + pci_dev_put(pdev); + + pr_info("slash_hotplug: hotplug: device removed, rescanning bus %04x:%02x\n", + pci_domain_nr(bus), bus->number); + pci_rescan_bus(bus); + + pci_unlock_rescan_remove(); + pr_info("slash_hotplug: hotplug: released pci_lock_rescan_remove\n"); + pr_info("slash_hotplug: hotplug: %s complete\n", bdf); + + return 0; +} + +/** + * slash_hotplug_ioctl() - Dispatch hotplug ioctl commands. + * @file: Open file for the hotplug misc device. + * @cmd: ioctl command number. + * @arg: Userspace pointer to the request struct (for commands that need one). + * + * Return: 0 on success, negative errno on failure. + */ +static long slash_hotplug_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct slash_hotplug_device_request req = {0}; + int ret; + + pr_info("slash_hotplug: ioctl: received cmd=0x%x\n", cmd); + + switch (cmd) { + case SLASH_HOTPLUG_IOCTL_RESCAN: + pr_info("slash_hotplug: ioctl: dispatching RESCAN\n"); + ret = slash_hotplug_handle_rescan(); + if (!ret) + pr_info("slash_hotplug: ioctl: RESCAN succeeded\n"); + break; + case SLASH_HOTPLUG_IOCTL_REMOVE: + pr_info("slash_hotplug: ioctl: dispatching REMOVE\n"); + ret = slash_hotplug_copy_request(arg, &req); + if (ret) { + pr_err("slash_hotplug: remove: copy_request failed (%d)\n", ret); + break; + } + pr_info("slash_hotplug: remove: BDF %s\n", req.bdf); + ret = slash_hotplug_handle_remove(req.bdf); + if (!ret) + pr_info("slash_hotplug: ioctl: REMOVE succeeded\n"); + break; + case SLASH_HOTPLUG_IOCTL_TOGGLE_SBR: + pr_info("slash_hotplug: ioctl: dispatching TOGGLE_SBR\n"); + ret = slash_hotplug_copy_request(arg, &req); + if (ret) { + pr_err("slash_hotplug: toggle_sbr: copy_request failed (%d)\n", ret); + break; + } + pr_info("slash_hotplug: toggle_sbr: BDF %s\n", req.bdf); + ret = slash_hotplug_handle_toggle_sbr(req.bdf); + if (!ret) + pr_info("slash_hotplug: ioctl: TOGGLE_SBR succeeded\n"); + break; + case SLASH_HOTPLUG_IOCTL_HOTPLUG: + pr_info("slash_hotplug: ioctl: dispatching HOTPLUG\n"); + ret = slash_hotplug_copy_request(arg, &req); + if (ret) { + pr_err("slash_hotplug: hotplug: copy_request failed (%d)\n", ret); + break; + } + pr_info("slash_hotplug: hotplug: BDF %s\n", req.bdf); + ret = slash_hotplug_handle_hotplug(req.bdf); + if (!ret) + pr_info("slash_hotplug: ioctl: HOTPLUG succeeded\n"); + break; + default: + pr_err("slash_hotplug: unknown ioctl cmd 0x%x\n", cmd); + ret = -ENOTTY; + break; + } + + if (ret) + pr_err("slash_hotplug: ioctl 0x%x returning %d\n", cmd, ret); + + return ret; +} + +#ifdef CONFIG_COMPAT +/** + * slash_hotplug_compat_ioctl() - Handle 32-bit compat ioctls. + * + * Converts the 32-bit userspace pointer to a native pointer and + * delegates to the standard ioctl handler. The request struct is + * the same size on 32-bit and 64-bit, so no field translation is + * needed. + */ +static long slash_hotplug_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + pr_info("slash_hotplug: compat_ioctl: cmd=0x%x (32-bit userspace)\n", cmd); + return slash_hotplug_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +#endif + +static const struct file_operations slash_hotplug_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = slash_hotplug_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = slash_hotplug_compat_ioctl, +#endif +}; + +static struct miscdevice slash_hotplug_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = SLASH_HOTPLUG_DEVICE_NAME, + .fops = &slash_hotplug_fops, + .mode = SLASH_HOTPLUG_MODE, +}; + +int slash_hotplug_init(void) +{ + int ret; + + pr_info("slash_hotplug: registering misc device\n"); + + ret = misc_register(&slash_hotplug_misc); + if (ret) { + pr_err("slash_hotplug: misc_register failed: %d\n", ret); + return ret; + } + + pr_info("slash_hotplug: misc device registered as /dev/%s (minor %d)\n", + slash_hotplug_misc.name, slash_hotplug_misc.minor); + return 0; +} + +void slash_hotplug_exit(void) +{ + pr_info("slash_hotplug: deregistering misc device\n"); + misc_deregister(&slash_hotplug_misc); + pr_info("slash_hotplug: misc device unregistered\n"); +} diff --git a/driver/slash_hotplug_driver.h b/driver/slash_hotplug_driver.h new file mode 100644 index 00000000..fe3cf0d4 --- /dev/null +++ b/driver/slash_hotplug_driver.h @@ -0,0 +1,46 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_hotplug_driver.h + * + * Kernel-internal interface for the SLASH hotplug subsystem. + * + * The hotplug subsystem manages the PCIe-level lifecycle of SLASH FPGA + * devices: removing them from the bus, performing Secondary Bus Resets, + * and rescanning. This is essential for FPGA reconfiguration workflows + * where loading a new bitstream requires re-enumerating the device. + * + * A single misc device (/dev/slash_hotplug) handles ioctls. All + * operations that target a specific device require an explicit BDF. + */ + +#ifndef SLASH_HOTPLUG_DRIVER_H +#define SLASH_HOTPLUG_DRIVER_H + +/** + * slash_hotplug_init() - Register the hotplug misc device. + * + * Creates /dev/slash_hotplug. + * + * Return: 0 on success, negative errno on failure. + */ +int slash_hotplug_init(void); + +/** + * slash_hotplug_exit() - Unregister the hotplug misc device. + */ +void slash_hotplug_exit(void); + +#endif /* SLASH_HOTPLUG_DRIVER_H */ diff --git a/driver/slash_main.c b/driver/slash_main.c new file mode 100644 index 00000000..5296e0e3 --- /dev/null +++ b/driver/slash_main.c @@ -0,0 +1,134 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_main.c + * + * Module entry point for the SLASH kernel driver. + * + * SLASH is a partial-reconfiguration design for AMD Alveo V80 FPGAs. + * This module manages two PCI physical functions exposed by the design: + * + * - PF1 (QDMA) — queue-based DMA for bulk data transfer. + * - PF2 (Control) — BAR access for register-level MMIO. + * + * It also provides a hotplug subsystem for removing, resetting (SBR), + * and rescanning PCI devices — needed when the FPGA bitstream changes + * and the device must be re-enumerated. + * + * Initialization order matters: + * + * 1. **QDMA** — libqdma must be initialized and its PCI driver + * registered before any PCI probe runs, because PF1 and PF2 + * may probe concurrently once drivers are registered. + * + * 2. **Hotplug** — the /dev/slash_hotplug misc device must exist + * before PCI probe registers devices into the tracking list. + * + * 3. **PCIe** — registering the PF2 PCI driver triggers probe for + * any devices already present on the bus. + * + * Teardown is the reverse: PCIe first (unbinds devices), then hotplug + * (frees tracking list), then QDMA (shuts down libqdma). + */ + +#include "slash.h" +#include "slash_compat.h" + +#include +#include +#include +#include + +#include "slash_pcie.h" +#include "slash_hotplug_driver.h" +#include "slash_qdma.h" + +#ifndef SLASH_VERSION_STR +#define SLASH_VERSION_STR "unknown" +#endif + +/** Number of worker threads for libqdma's internal processing. */ +static unsigned int qdma_num_threads = 8; +/** Optional debugfs mount path for libqdma diagnostics (unused). */ +static char *qdma_debugfs_path = NULL; + +/** + * slash_init() - Module initialization. + * + * Brings up the three subsystems in dependency order. + * On failure, tears down any subsystems that were already initialized. + * + * Return: 0 on success, negative errno on failure. + */ +static int __init slash_init(void) +{ + int err; + + pr_info("slash: module init\n"); + + /* 1. QDMA first — libqdma + PF1 PCI driver. */ + err = slash_qdma_init(qdma_num_threads, NULL); + if (err) { + pr_err("slash: libqdma init failed: %d\n", err); + return err; + } + + /* 2. Hotplug — /dev/slash_hotplug misc device. */ + err = slash_hotplug_init(); + if (err) { + pr_err("slash: hotplug init failed: %d\n", err); + slash_qdma_exit(); + return err; + } + + /* 3. PCIe — PF2 PCI driver (triggers probe for present devices). */ + err = slash_pcie_init(); + if (err) { + pr_err("slash: PCIe init failed: %d\n", err); + slash_hotplug_exit(); + return err; + } + + pr_info("slash: module init complete\n"); + return 0; +} + +/** + * slash_exit() - Module cleanup. + * + * Tears down subsystems in reverse initialization order. + */ +static void __exit slash_exit(void) +{ + pr_info("slash: module exit\n"); + slash_pcie_exit(); + slash_hotplug_exit(); + slash_qdma_exit(); + pr_info("slash: module exit complete\n"); +} + +module_init(slash_init); +module_exit(slash_exit); + +module_param(qdma_num_threads, uint, 0644); +MODULE_PARM_DESC(qdma_num_threads, "Number of libqdma worker threads (default: 8)"); +module_param(qdma_debugfs_path, charp, 0644); +MODULE_PARM_DESC(qdma_debugfs_path, "debugfs mount path for libqdma (default: disabled)"); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("AMD Inc."); +MODULE_DESCRIPTION("SLASH/VRT module"); +MODULE_VERSION(SLASH_VERSION_STR); +SLASH_MODULE_IMPORT_NS(DMA_BUF); diff --git a/driver/slash_pcie.c b/driver/slash_pcie.c new file mode 100644 index 00000000..cc707cf9 --- /dev/null +++ b/driver/slash_pcie.c @@ -0,0 +1,162 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_pcie.c + * + * PCI driver for the SLASH control function (PF2). + * + * This driver binds to PCI device 10EE:50B6 (the V80 SLASH control + * function). On probe it creates a control device (slash_ctldev) that + * exposes BAR information and dma-buf-backed BAR mappings to userspace, + * and registers the device with the hotplug subsystem so that it can + * be removed/reset/rescanned during FPGA reconfiguration. + * + * PF1 (the QDMA function, device 10EE:50B5) is handled by a separate + * PCI driver registered in slash_qdma.c. + */ + +#include "slash_pcie.h" + +#include +#include + +#include "slash.h" +#include "slash_ctldev.h" +#include "slash_hotplug_driver.h" + +static int slash_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id); +static void slash_pcie_remove(struct pci_dev *pdev); + +/* Match only the SLASH control function (PF2, device 0x50B6). */ +static const struct pci_device_id slash_pcie_ids[] = { + {PCI_DEVICE(SLASH_PCIE_VENDOR_ID, SLASH_PCIE_DEVICE_ID)}, + {0,} +}; +MODULE_DEVICE_TABLE(pci, slash_pcie_ids); + +static struct pci_driver slash_pcie_driver = { + .name = SLASH_PCIE_DRV_NAME, + .id_table = slash_pcie_ids, + .probe = slash_pcie_probe, + .remove = slash_pcie_remove, +}; + +/** + * slash_pcie_probe() - Bind to a SLASH control function. + * @pdev: PCI device being probed. + * @id: Matching device ID entry (unused). + * + * Verifies that this is the expected physical function (PF2), enables + * the PCI device, creates the control character device, and registers + * with the hotplug subsystem. + * + * Takes an extra reference on @pdev (pci_dev_get) because the control + * device and hotplug subsystem hold pointers to it beyond this function. + * The reference is released in slash_pcie_remove(). + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int err; + + (void) id; /* Unused */ + + dev_info(&pdev->dev, "slash: probe start for %s\n", pci_name(pdev)); + dev_dbg(&pdev->dev, "slash: vendor=0x%04x device=0x%04x fn=%u\n", pdev->vendor, pdev->device, PCI_FUNC(pdev->devfn)); + + /* + * The SLASH design places the control interface on PF2. Reject + * any other function — this guards against unexpected device ID + * collisions or misconfigured FPGA designs. + */ + if (PCI_FUNC(pdev->devfn) != SLASH_PCIE_PF) { + dev_err(&pdev->dev, "slash: expected PF %u, got %u\n", SLASH_PCIE_PF, PCI_FUNC(pdev->devfn)); + return -EINVAL; + } + + /* Hold a reference for the lifetime of the driver binding. */ + pci_dev_get(pdev); + + err = pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "slash: pci_enable_device() failed: %d\n", err); + goto err_put_device; + } + + /* Bus mastering is required for the device to perform DMA. */ + pci_set_master(pdev); + dev_dbg(&pdev->dev, "slash: bus mastering enabled\n"); + + err = slash_ctldev_create(pdev); + if (err) { + dev_err(&pdev->dev, "slash: control device create failed: %d\n", err); + goto err_disable_device; + } + + dev_info(&pdev->dev, "slash: probe successful\n"); + return 0; + +err_disable_device: + pci_clear_master(pdev); + pci_disable_device(pdev); + +err_put_device: + pci_dev_put(pdev); + + return err; +} + +/** + * slash_pcie_remove() - Unbind from a SLASH control function. + * @pdev: PCI device being removed. + * + * Tears down resources in reverse probe order: hotplug unregister, + * control device destroy, then PCI cleanup. + */ +static void slash_pcie_remove(struct pci_dev *pdev) +{ + dev_info(&pdev->dev, "slash: remove start for %s\n", pci_name(pdev)); + + slash_ctldev_destroy(pdev); + pci_clear_master(pdev); + pci_disable_device(pdev); + pci_dev_put(pdev); + + dev_info(&pdev->dev, "slash: remove complete\n"); +} + +int __init slash_pcie_init(void) +{ + int err; + + pr_info("slash: registering PCIe driver '%s'\n", SLASH_NAME); + err = pci_register_driver(&slash_pcie_driver); + + if (err) { + pr_err("slash: pci_register_driver failed: %d\n", err); + return err; + } + + pr_info("slash: driver '%s' registered\n", SLASH_NAME); + return 0; +} + +void __exit slash_pcie_exit(void) +{ + pr_info("slash: unregistering PCIe driver '%s'\n", SLASH_NAME); + pci_unregister_driver(&slash_pcie_driver); + pr_info("slash: driver '%s' unregistered\n", SLASH_NAME); +} diff --git a/driver/slash_pcie.h b/driver/slash_pcie.h new file mode 100644 index 00000000..4206c620 --- /dev/null +++ b/driver/slash_pcie.h @@ -0,0 +1,48 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_pcie.h + * + * PCI driver registration interface for the SLASH control function (PF2). + * + * The PCI driver handles probe/remove callbacks for each V80 SLASH + * control function discovered on the bus. It is registered during + * module init and unregistered during module exit. + */ + +#ifndef SLASH_PCIE_H +#define SLASH_PCIE_H + +#include + +/** + * slash_pcie_init() - Register the SLASH PCI driver with the kernel. + * + * Called from module init. Triggers probe callbacks for any SLASH + * devices already present on the bus. + * + * Return: 0 on success, negative errno on failure. + */ +int __init slash_pcie_init(void); + +/** + * slash_pcie_exit() - Unregister the SLASH PCI driver. + * + * Called from module exit. Triggers remove callbacks for all + * currently bound devices. + */ +void __exit slash_pcie_exit(void); + +#endif /* SLASH_PCIE_H */ diff --git a/driver/slash_qdma.c b/driver/slash_qdma.c new file mode 100644 index 00000000..8e8d9d52 --- /dev/null +++ b/driver/slash_qdma.c @@ -0,0 +1,2496 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_qdma.c + * + * QDMA (Queue-based DMA) subsystem for the SLASH FPGA driver. + * + * This file implements the QDMA data-plane for SLASH, an AMD Alveo V80 + * partial-reconfiguration FPGA design. It wraps the Xilinx libqdma + * library (from submodules/qdma_drv/QDMA/linux-kernel/driver/libqdma/) + * to provide queue-pair-based DMA transfers between host memory and the + * FPGA fabric. + * + * The QDMA subsystem binds to PF1 (PCI device ID 0x50B5), while the + * control device (slash_ctldev) binds to PF2 (device ID 0x50B6). + * + * Queue pair lifecycle: + * add -> start -> I/O (via anon_inode fd) -> stop -> del + * + * Key design decisions: + * - **Poll mode** (no interrupts): avoids interrupt overhead for + * streaming workloads; the host polls HW-written completion status. + * - **Synchronous transfers**: qdma_request_submit() blocks until the + * DMA completes or times out (10 s default). + * - **XArray for qpair tracking**: provides dynamic ID allocation, + * built-in locking, and automatic index management for up to 256 + * concurrent queue pairs. + * - **Reference counting**: kref on both the device and each qpair + * entry; the anon_inode fd holds a ref, preventing premature + * destruction while userspace still has the fd open. + */ + +#include "slash_qdma.h" + +#include "libqdma_export.h" + +#include "slash.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Direction bitmask constants. + * + * These map 1:1 with the libqdma queue_type_t enum values (Q_H2C, + * Q_C2H, Q_CMPT) but expressed as bit positions so they can be + * OR'd together in a single dir_mask field. + * + * SLASH_QDMA_DIR_H2C — Host-to-Card (write path) + * SLASH_QDMA_DIR_C2H — Card-to-Host (read path) + * SLASH_QDMA_DIR_CMPT — Completion queue (status/metadata from card) + */ +#define SLASH_QDMA_DIR_H2C BIT(0) +#define SLASH_QDMA_DIR_C2H BIT(1) +#define SLASH_QDMA_DIR_CMPT BIT(2) +#define SLASH_QDMA_DIR_MASK (SLASH_QDMA_DIR_H2C | SLASH_QDMA_DIR_C2H | \ + SLASH_QDMA_DIR_CMPT) + +/** + * SLASH_QDMA_QTYPE_COUNT - Number of queue types tracked per queue pair. + * + * Equals Q_CMPT + 1 (i.e., 3): one slot each for H2C, C2H, and CMPT. + * Used to size the per-qpair qhndl[] array. + */ +#define SLASH_QDMA_QTYPE_COUNT (Q_CMPT + 1) + +/** + * SLASH_QDMA_MAX_QPAIRS - Maximum number of simultaneous queue pairs. + * + * This matches the conf.qsets_max value passed to qdma_device_open() + * in slash_qdma_conf_options(), keeping the xarray ID space and the + * HW queue-set limit in sync. + */ +#define SLASH_QDMA_MAX_QPAIRS 256 + +/** + * SLASH_QDMA_QPAIR_ID_RANGE - XArray allocation range for qpair IDs. + * + * Constrains xa_alloc() to assign IDs in [0, 255]. The xarray handles + * thread-safe allocation and lookup of queue pair entries within this + * range. + */ +#define SLASH_QDMA_QPAIR_ID_RANGE XA_LIMIT(0, SLASH_QDMA_MAX_QPAIRS - 1) + +/* + * Debug logging infrastructure. + * + * When SLASH_QDMA_OP_DEBUG is non-zero (compile-time flag), every + * libqdma call and state transition is logged via pr_info / dev_info. + * In production builds the macros expand to nothing to avoid log spam. + */ +#ifndef SLASH_QDMA_OP_DEBUG +#define SLASH_QDMA_OP_DEBUG 0 +#endif + +#if SLASH_QDMA_OP_DEBUG +#define SLASH_QDMA_OP_LOG(fmt, ...) \ + pr_info("slash: qdma: " fmt, ##__VA_ARGS__) +#define SLASH_QDMA_OP_DEV_LOG(dev, fmt, ...) \ + dev_info((dev), "slash: qdma: " fmt, ##__VA_ARGS__) +#else +#define SLASH_QDMA_OP_LOG(fmt, ...) \ + do { \ + } while (0) +#define SLASH_QDMA_OP_DEV_LOG(dev, fmt, ...) \ + do { \ + } while (0) +#endif + +/* Forward declaration; full definition follows. */ +struct slash_qdma_dev; + +/** + * struct slash_qdma_qpair_entry - Per-queue-pair state. + * @ref: Reference count. Starts at 1 (held by the xarray slot); + * an additional ref is taken when an anon_inode fd is handed + * to userspace, so the entry outlives the xarray removal if + * the fd is still open. + * @qhndl: Array of libqdma queue handles, one per queue type + * (Q_H2C, Q_C2H, Q_CMPT). Entries that are not in use + * hold the sentinel QDMA_QUEUE_IDX_INVALID. + * @dir_mask: Bitmask of active directions (SLASH_QDMA_DIR_H2C, etc.). + * Updated as individual queues are added or removed. + * @mode: Queue operating mode (QDMA_Q_MODE_MM or QDMA_Q_MODE_ST). + * @irq_mode: Interrupt mode. Currently always 0 (poll mode). + * @irq_vector: MSI-X vector assignment. Currently unused (poll mode). + */ +struct slash_qdma_qpair_entry { + struct kref ref; + unsigned long qhndl[SLASH_QDMA_QTYPE_COUNT]; + u32 dir_mask; + enum qdma_q_mode mode; + u32 irq_mode; + u32 irq_vector; +}; + +/** + * struct slash_qdma_dev - Per-PCI-device QDMA state. + * @pdev: The PCI device (PF1) this instance is bound to. + * @qdma_handle: Opaque handle returned by qdma_device_open(); + * passed to every subsequent libqdma call. + * @misc: Miscdevice registered under /dev/slash_qdma_ctlN. + * Userspace opens this to issue queue management ioctls. + * @ref: Device-level reference count. The miscdevice open + * path and each anon_inode fd hold a ref; the device + * structure is freed when the last ref drops. + * @lock: Serialises ioctl paths and protects @qpairs, + * @hw_shutdown, and @have_qdma_handle. + * @qpairs: XArray mapping qpair IDs (u32) to + * &struct slash_qdma_qpair_entry pointers. Using an + * xarray gives us O(1) lookup, thread-safe auto-ID + * allocation, and safe concurrent iteration during + * teardown. + * @have_qdma_handle: True once qdma_device_open() succeeds; false after + * qdma_device_close(). Guards against use-after-close. + * @is_misc_registered: True while the miscdevice is live. Prevents double + * deregistration on error paths. + * @hw_shutdown: Set to true during destroy to signal that the HW is + * going away. Any ioctl arriving after this flag is + * set returns -ENODEV immediately. + * + * The three booleans (@have_qdma_handle, @is_misc_registered, + * @hw_shutdown) track partially-constructed state during probe/remove + * error paths; outside of create/destroy they should always reflect a + * fully initialised device. + */ +struct slash_qdma_dev { + struct pci_dev *pdev; + unsigned long qdma_handle; + + struct miscdevice misc; + struct kref ref; + struct mutex lock; + struct xarray qpairs; + + /* + * Initialization booleans. + * Assume these are always true outside of create/destroy. + */ + bool have_qdma_handle; + bool is_misc_registered; + bool hw_shutdown; +}; + +/** + * typedef slash_qdma_queue_cmd_fn - Function pointer for queue lifecycle ops. + * + * Matches the signature of qdma_queue_start(), qdma_queue_stop(), and + * slash_qdma_queue_remove_safe(), allowing slash_qdma_ioctl_qpair_op_apply() + * to iterate over all directions in a queue pair and apply the same + * operation generically. + */ +typedef int (*slash_qdma_queue_cmd_fn)(unsigned long qdma_handle, + unsigned long qhndl, + char *errbuf, + int errbuf_sz); + +/* Forward declaration — defined below after its helper functions. */ +static int slash_qdma_queue_remove_safe(unsigned long qdma_handle, + unsigned long qhndl, + char *errbuf, + int errbuf_sz); + +/* ───────────────────────────────────────────────────────────────────── + * Direction / queue-type conversion helpers + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_dir_to_qtype() - Convert a direction bitmask bit to a queue type. + * @dir_bit: Exactly one of SLASH_QDMA_DIR_H2C, _C2H, or _CMPT. + * + * Return: The corresponding libqdma queue_type_t value. + * + * Note: currently unused (hence __attribute__((unused))), but kept as + * the inverse of slash_qdma_qtype_to_dir() for completeness. + */ +__attribute__((unused)) +static enum queue_type_t slash_qdma_dir_to_qtype(u32 dir_bit) +{ + switch (dir_bit) { + case SLASH_QDMA_DIR_H2C: + return Q_H2C; + case SLASH_QDMA_DIR_C2H: + return Q_C2H; + case SLASH_QDMA_DIR_CMPT: + return Q_CMPT; + default: + return Q_H2C; /* should never reach */ + } +} + +/** + * slash_qdma_qtype_to_dir() - Convert a queue type to its direction bitmask bit. + * @qtype: One of Q_H2C, Q_C2H, or Q_CMPT. + * + * Return: The corresponding SLASH_QDMA_DIR_* bitmask value, or 0 for + * an unrecognised queue type. + */ +static u32 slash_qdma_qtype_to_dir(enum queue_type_t qtype) +{ + switch (qtype) { + case Q_H2C: + return SLASH_QDMA_DIR_H2C; + case Q_C2H: + return SLASH_QDMA_DIR_C2H; + case Q_CMPT: + return SLASH_QDMA_DIR_CMPT; + default: + return 0; + } +} + +/** + * slash_qdma_qhndl_is_valid() - Check if a queue handle is valid. + * @qhndl: Queue handle from libqdma. + * + * Return: true if @qhndl is not the sentinel QDMA_QUEUE_IDX_INVALID, + * meaning the queue has been successfully added to the HW. + */ +static inline bool slash_qdma_qhndl_is_valid(unsigned long qhndl) +{ + return qhndl != QDMA_QUEUE_IDX_INVALID; +} + +/* ───────────────────────────────────────────────────────────────────── + * Queue removal with state-machine safety + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_queue_remove_safe() - Stop-then-remove a queue, handling any state. + * @qdma_handle: Device handle from qdma_device_open(). + * @qhndl: Queue handle to remove. + * @errbuf: Buffer for libqdma error messages. + * @errbuf_sz: Size of @errbuf. + * + * The QDMA HW queue state machine requires that an ONLINE queue be + * stopped before it can be removed. This helper queries the current + * state and performs the correct transitions: + * + * - Q_STATE_ONLINE -> stop, then remove + * - Q_STATE_ENABLED -> remove directly (already stopped) + * - Q_STATE_DISABLED -> no-op (already removed) + * - anything else -> return -EINVAL + * + * This "check-before-stop" pattern prevents errors from trying to stop + * an already-stopped queue or remove an already-removed one, which is + * important during teardown where we may not know the current state. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_queue_remove_safe(unsigned long qdma_handle, + unsigned long qhndl, + char *errbuf, + int errbuf_sz) +{ + struct qdma_q_state qstate = {0}; + int err; + + if (!errbuf || errbuf_sz <= 0) + return -EINVAL; + + errbuf[0] = '\0'; + + /* Query the current HW queue state */ + SLASH_QDMA_OP_LOG("qdma_get_queue_state start: handle=%lu qhndl=%lu\n", + qdma_handle, qhndl); + err = qdma_get_queue_state(qdma_handle, qhndl, &qstate, errbuf, errbuf_sz); + if (err) { + SLASH_QDMA_OP_LOG("qdma_get_queue_state failed: qhndl=%lu err=%d (%s)\n", + qhndl, err, errbuf); + return err; + } + SLASH_QDMA_OP_LOG("qdma_get_queue_state done: qhndl=%lu state=%u\n", + qhndl, qstate.qstate); + + switch (qstate.qstate) { + case Q_STATE_ONLINE: + /* Queue is active — must stop before removing. */ + SLASH_QDMA_OP_LOG("qdma_queue_stop start: qhndl=%lu\n", qhndl); + err = qdma_queue_stop(qdma_handle, qhndl, errbuf, errbuf_sz); + if (err) { + SLASH_QDMA_OP_LOG("qdma_queue_stop failed: qhndl=%lu err=%d (%s)\n", + qhndl, err, errbuf); + return err; + } + SLASH_QDMA_OP_LOG("qdma_queue_stop done: qhndl=%lu\n", qhndl); + break; + case Q_STATE_ENABLED: + /* Queue is added but not started — can remove directly. */ + break; + case Q_STATE_DISABLED: + /* Queue is already removed. */ + SLASH_QDMA_OP_LOG("queue already disabled, skip remove: qhndl=%lu\n", + qhndl); + return 0; + default: + snprintf(errbuf, errbuf_sz, "queue in unexpected state %u", + qstate.qstate); + SLASH_QDMA_OP_LOG("qdma_get_queue_state unexpected state: qhndl=%lu state=%u\n", + qhndl, qstate.qstate); + return -EINVAL; + } + + /* State is now ENABLED — safe to remove. */ + SLASH_QDMA_OP_LOG("qdma_queue_remove start: qhndl=%lu\n", qhndl); + err = qdma_queue_remove(qdma_handle, qhndl, errbuf, errbuf_sz); + if (err) { + SLASH_QDMA_OP_LOG("qdma_queue_remove failed: qhndl=%lu err=%d (%s)\n", + qhndl, err, errbuf); + return err; + } + SLASH_QDMA_OP_LOG("qdma_queue_remove done: qhndl=%lu\n", qhndl); + + return 0; +} + +/* ───────────────────────────────────────────────────────────────────── + * Queue pair xarray helpers (lookup, refcount, insert, remove) + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_qpair_lookup() - Find a qpair entry by ID. + * @qdma_dev: QDMA device whose xarray to search. + * @qid: Queue pair ID. + * + * Return: Pointer to the entry, or NULL if @qid is not allocated. + * + * Note: the caller must hold @qdma_dev->lock or otherwise guarantee + * that the entry will not be freed during use (e.g., by holding a ref). + */ +static inline struct slash_qdma_qpair_entry * +slash_qdma_qpair_lookup(struct slash_qdma_dev *qdma_dev, u32 qid) +{ + return xa_load(&qdma_dev->qpairs, qid); +} + +/** + * slash_qdma_qpair_entry_release() - kref release callback for qpair entries. + * @ref: kref embedded in the slash_qdma_qpair_entry being released. + * + * Called when the last reference to a qpair entry is dropped. Frees + * the entry structure. By this point, all associated HW queues must + * already have been removed. + */ +static void slash_qdma_qpair_entry_release(struct kref *ref) +{ + struct slash_qdma_qpair_entry *entry = + container_of(ref, struct slash_qdma_qpair_entry, ref); + + kfree(entry); +} + +/** + * slash_qdma_qpair_get() - Acquire a reference on a qpair entry. + * @entry: The entry to reference. + * + * Used when handing out an anon_inode fd so the entry survives until + * the fd is closed, even if the qpair is deleted from the xarray. + */ +static inline void slash_qdma_qpair_get(struct slash_qdma_qpair_entry *entry) +{ + kref_get(&entry->ref); +} + +/** + * slash_qdma_qpair_put() - Release a reference on a qpair entry. + * @entry: The entry to dereference. + * + * When the last reference drops, the entry is freed via + * slash_qdma_qpair_entry_release(). + */ +static inline void slash_qdma_qpair_put(struct slash_qdma_qpair_entry *entry) +{ + kref_put(&entry->ref, slash_qdma_qpair_entry_release); +} + +/** + * slash_qdma_qpair_insert() - Allocate a new qpair ID and insert the entry. + * @qdma_dev: QDMA device whose xarray receives the entry. + * @entry: The new entry to insert. Its kref is initialised here. + * @id: [out] The auto-assigned queue pair ID. + * + * Uses xa_alloc() to atomically pick the lowest available ID in + * [0, SLASH_QDMA_MAX_QPAIRS-1] and store @entry at that index. + * + * Return: 0 on success, -EBUSY if all 256 IDs are in use, or other + * negative errno. + */ +static inline int +slash_qdma_qpair_insert(struct slash_qdma_dev *qdma_dev, struct slash_qdma_qpair_entry *entry, u32 *id) +{ + kref_init(&entry->ref); + return xa_alloc(&qdma_dev->qpairs, id, entry, SLASH_QDMA_QPAIR_ID_RANGE, GFP_KERNEL); +} + +/** + * slash_qdma_qpair_remove() - Erase a qpair from the xarray and drop its ref. + * @qdma_dev: QDMA device. + * @qid: Queue pair ID to remove. + * + * After this call, the ID is available for reuse. The entry itself is + * only freed when all references (including any held by open fds) are + * released. + */ +static inline void +slash_qdma_qpair_remove(struct slash_qdma_dev *qdma_dev, u32 qid) +{ + struct slash_qdma_qpair_entry *entry; + + entry = xa_erase(&qdma_dev->qpairs, qid); + if (entry) + slash_qdma_qpair_put(entry); +} + +/* ───────────────────────────────────────────────────────────────────── + * Anon-inode file context and I/O control block + * ───────────────────────────────────────────────────────────────────── */ + +/** + * struct slash_qdma_qpair_file_ctx - Private data for an anon_inode qpair fd. + * @qdma_dev: Back-pointer to the owning QDMA device (ref held). + * @entry: The queue pair entry this fd operates on (ref held). + * @qid: Queue pair ID, cached for debug logging. + * + * Allocated in slash_qdma_ioctl_qpair_get_fd_w() and freed in + * slash_qdma_qpair_release(). Both @qdma_dev and @entry have their + * reference counts incremented when the ctx is created, and decremented + * when the fd is closed. + */ +struct slash_qdma_qpair_file_ctx { + struct slash_qdma_dev *qdma_dev; + struct slash_qdma_qpair_entry *entry; + u32 qid; +}; + +/** + * struct slash_qdma_io_cb - I/O control block for a single DMA transfer. + * @buf: User-space buffer address (source for H2C, destination for C2H). + * @len: Transfer length in bytes. + * @pages_nr: Number of user pages pinned by get_user_pages_fast(). + * @sgl: Scatter-gather list of qdma_sw_sg entries, one per pinned page. + * Allocated as a single contiguous block together with @pages. + * @pages: Array of struct page pointers for the pinned user pages. + * Points into the same allocation as @sgl (immediately after it). + * @req: The libqdma request structure submitted to qdma_request_submit(). + * + * This is a stack-local structure (allocated in slash_qdma_qpair_read_write) + * that bundles all per-transfer state. The SGL and page array are heap- + * allocated in slash_qdma_map_user_buf_to_sgl() and freed in + * slash_qdma_iocb_release(). + */ +struct slash_qdma_io_cb { + void __user *buf; + size_t len; + unsigned int pages_nr; + struct qdma_sw_sg *sgl; + struct page **pages; + struct qdma_request req; +}; + +/* ───────────────────────────────────────────────────────────────────── + * Forward declarations + * ───────────────────────────────────────────────────────────────────── */ + +static int slash_qdma_probe(struct pci_dev *pdev, const struct pci_device_id *id); +static void slash_qdma_remove(struct pci_dev *pdev); +static int slash_qdma_create_qdma_device(struct pci_dev *pdev, struct slash_qdma_dev **pdevice); +static void slash_qdma_destroy_qdma_device(struct slash_qdma_dev *device); +static void slash_qdma_dev_release(struct kref *ref); +static void slash_qdma_conf_options(struct qdma_dev_conf *conf, struct pci_dev *pdev); +static int slash_qdma_ioctl_info_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); +static int slash_qdma_ioctl_qpair_add_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); +static int slash_qdma_ioctl_qpair_add(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req); +static int slash_qdma_ioctl_qpair_add_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype); +static void slash_qdma_ioctl_qpair_rm_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype); +static int slash_qdma_ioctl_qpair_op_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); +static int slash_qdma_ioctl_qpair_op(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_op *req); +static int slash_qdma_ioctl_qpair_op_apply(struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + struct slash_qdma_qpair_op *req, + slash_qdma_queue_cmd_fn fn, + const char *op_name, + bool stop_on_err); +static int slash_qdma_ioctl_qpair_get_fd_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg); + +static ssize_t slash_qdma_qpair_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos); +static ssize_t slash_qdma_qpair_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos); +static int slash_qdma_qpair_release(struct inode *inode, struct file *file); +static long slash_qdma_qpair_ioctl(struct file *file, + unsigned int cmd, unsigned long arg); + +/** + * slash_qdma_qpair_fops - File operations for per-qpair anon_inode fds. + * + * read() performs a C2H (card-to-host) DMA transfer. + * write() performs an H2C (host-to-card) DMA transfer. + * llseek uses default_llseek so that pread/pwrite can set the + * device-side address via the file position. + * ioctl is a stub that returns -ENOTTY (no per-fd ioctls defined yet). + * release drops the refs on the qpair entry and device. + */ +static const struct file_operations slash_qdma_qpair_fops = { + .owner = THIS_MODULE, + .read = slash_qdma_qpair_read, + .write = slash_qdma_qpair_write, + .unlocked_ioctl = slash_qdma_qpair_ioctl, + .release = slash_qdma_qpair_release, + .llseek = default_llseek, +}; + + +static int slash_qdma_fop_open(struct inode *inode, struct file *file); +static int slash_qdma_fop_release(struct inode *inode, struct file *file); +static long slash_qdma_fop_ioctl(struct file *file, unsigned int op, unsigned long arg); +static void slash_qdma_ioctl_info(struct miscdevice *misc, struct slash_qdma_dev *qdma_dev, struct slash_qdma_info *qdma_info); + + + +/** + * slash_qdma_ids - PCI device ID table for the QDMA PF. + * + * Matches only PF1 (device ID 0x50B5) on AMD/Xilinx V80 cards. + */ +static const struct pci_device_id slash_qdma_ids[] = { + {PCI_DEVICE(SLASH_QDMA_PCI_VENDOR_ID, SLASH_QDMA_PCI_DEVICE_ID)}, + {0,} +}; +MODULE_DEVICE_TABLE(pci, slash_qdma_ids); + +/** + * slash_qdma_driver - PCI driver structure for the QDMA subsystem. + * + * Registered in slash_qdma_init(); triggers slash_qdma_probe() for each + * matching PF1 device discovered during PCI enumeration. + */ +static struct pci_driver slash_qdma_driver = { + .name = SLASH_QDMA_DRV_NAME, + .id_table = slash_qdma_ids, + .probe = slash_qdma_probe, + .remove = slash_qdma_remove, +}; + +/** + * slash_qdma_fops - File operations for the QDMA control miscdevice. + * + * The miscdevice (/dev/slash_qdma_ctlN) is the management interface: + * userspace opens it and issues ioctls to add/start/stop/delete queue + * pairs and to obtain per-qpair I/O fds. + */ +static struct file_operations slash_qdma_fops = { + .owner = THIS_MODULE, + .open = slash_qdma_fop_open, + .release = slash_qdma_fop_release, + .unlocked_ioctl = slash_qdma_fop_ioctl, +}; + +/* ───────────────────────────────────────────────────────────────────── + * BDF-to-device-number map (stable /dev/slash_qdma_ctlN across hotplug) + * ───────────────────────────────────────────────────────────────────── */ + +/** + * struct slash_qdma_id_entry - Stable BDF-to-number mapping entry. + * @node: Intrusive list linkage for @slash_qdma_id_map. + * @bdf: Full PCI BDF string including function (e.g. "0000:61:00.1"). + * @number: The /dev/slash_qdma_ctl suffix permanently assigned to this BDF. + * @in_use: True while the device is bound to the driver. Cleared on remove, + * set on probe. A probe that finds @in_use already true indicates + * the kernel handed us a device that was never properly unbound — + * this should never happen under normal operation. + * + * Entries are allocated in probe and intentionally never freed. They survive + * hotplug remove+rescan cycles so that a device always gets back the same N. + */ +struct slash_qdma_id_entry { + struct list_head node; + char bdf[32]; /* "DDDD:BB:SS.F\0" fits comfortably in 32 bytes */ + int number; + bool in_use; +}; + +/** Persistent BDF-to-number map; entries live for the module's lifetime. */ +static LIST_HEAD(slash_qdma_id_map); +/** Serialises all accesses to @slash_qdma_id_map and @in_use fields. */ +static DEFINE_MUTEX(slash_qdma_id_map_lock); +/** Source of new numbers; only incremented when a BDF is seen for the first time. */ +static atomic_t slash_qdma_devcount = ATOMIC_INIT(0); + +/** + * slash_qdma_id_get() - Look up or allocate a stable number for a BDF. + * @bdf: Full PCI BDF string (e.g. "0000:61:00.1") from pci_name(). + * + * Called from probe. Returns the number permanently associated with @bdf, + * allocating a new one if this BDF is seen for the first time. Also marks + * the entry as in_use = true. + * + * If an existing entry is found with in_use already set, the device was + * never properly unbound before probe was called again — this indicates a + * kernel PCI driver bug. The function logs a loud error and returns + * -EBUSY so that probe aborts without touching the device. + * + * Return: non-negative stable device number on success, negative errno on + * failure (-ENOMEM if allocation fails, -EBUSY if already in use). + */ +static int slash_qdma_id_get(const char *bdf) +{ + struct slash_qdma_id_entry *entry; + int number; + + mutex_lock(&slash_qdma_id_map_lock); + + list_for_each_entry(entry, &slash_qdma_id_map, node) { + if (strcmp(entry->bdf, bdf) != 0) + continue; + + if (entry->in_use) { + pr_err("slash_qdma: BUG: probe called for %s but entry is already in_use " + "(number=%d); refusing to bind\n", bdf, entry->number); + mutex_unlock(&slash_qdma_id_map_lock); + return -EBUSY; + } + + entry->in_use = true; + number = entry->number; + mutex_unlock(&slash_qdma_id_map_lock); + pr_info("slash_qdma: reusing number %d for %s\n", number, bdf); + return number; + } + + /* First time we've seen this BDF — allocate a fresh entry. */ + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) { + mutex_unlock(&slash_qdma_id_map_lock); + return -ENOMEM; + } + + strscpy(entry->bdf, bdf, sizeof(entry->bdf)); + entry->number = atomic_inc_return(&slash_qdma_devcount) - 1; + entry->in_use = true; + list_add_tail(&entry->node, &slash_qdma_id_map); + + number = entry->number; + mutex_unlock(&slash_qdma_id_map_lock); + + pr_info("slash_qdma: assigned number %d to %s\n", number, bdf); + return number; +} + +/** + * slash_qdma_id_release() - Mark a BDF's entry as no longer in use. + * @bdf: Full PCI BDF string passed to the matching slash_qdma_id_get() call. + * + * Called when the misc device is deregistered (remove path, or probe error + * unwind after misc_register succeeds). Clears in_use so that the next probe + * for the same BDF can reuse the stored number. The entry itself is not freed. + * + * If no entry exists for @bdf (should never happen after a successful probe), + * the call is a no-op and a warning is logged. + */ +static void slash_qdma_id_release(const char *bdf) +{ + struct slash_qdma_id_entry *entry; + + mutex_lock(&slash_qdma_id_map_lock); + + list_for_each_entry(entry, &slash_qdma_id_map, node) { + if (strcmp(entry->bdf, bdf) != 0) + continue; + + entry->in_use = false; + mutex_unlock(&slash_qdma_id_map_lock); + pr_info("slash_qdma: released number %d for %s\n", entry->number, bdf); + return; + } + + /* Should be unreachable: release without a prior successful id_get. */ + pr_warn("slash_qdma: WARNING: release called for %s but no entry found\n", bdf); + mutex_unlock(&slash_qdma_id_map_lock); +} + +/* ───────────────────────────────────────────────────────────────────── + * Module init / exit + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_init() - Initialise the QDMA subsystem. + * @num_threads: Worker thread count for libqdma's internal processing. + * @debugfs: Optional debugfs mount path, or NULL to disable. + * + * Called from the top-level module init. Initialises the libqdma + * library first (which sets up internal data structures and worker + * threads), then registers the PCI driver so that slash_qdma_probe() + * fires for each PF1 device. + * + * Return: 0 on success, negative errno on failure. + */ +int __init slash_qdma_init(unsigned int num_threads, char *debugfs) +{ + int err; + + SLASH_QDMA_OP_LOG("init start: num_threads=%u debugfs=%s\n", + num_threads, debugfs ? debugfs : "(null)"); + + err = libqdma_init(num_threads, debugfs); + if (err) { + SLASH_QDMA_OP_LOG("libqdma_init failed: err=%d\n", err); + pr_err("slash: libqdma_init failed: %d\n", err); + return err; + } + SLASH_QDMA_OP_LOG("libqdma_init done\n"); + + err = pci_register_driver(&slash_qdma_driver); + if (err) { + SLASH_QDMA_OP_LOG("pci_register_driver failed: err=%d\n", err); + pr_err("slash: register qdma driver failed: %d\n", err); + goto err_exit_libqdma; + } + SLASH_QDMA_OP_LOG("pci_register_driver done\n"); + + return 0; + +err_exit_libqdma: + SLASH_QDMA_OP_LOG("libqdma_exit start (init rollback)\n"); + libqdma_exit(); + SLASH_QDMA_OP_LOG("libqdma_exit done (init rollback)\n"); + + return err; +} + +/** + * slash_qdma_exit() - Tear down the QDMA subsystem. + * + * Called from the top-level module exit. Unregisters the PCI driver + * (which triggers slash_qdma_remove() for each probed device) and then + * shuts down the libqdma library. + */ +void slash_qdma_exit(void) +{ + SLASH_QDMA_OP_LOG("exit start\n"); + + pci_unregister_driver(&slash_qdma_driver); + SLASH_QDMA_OP_LOG("pci_unregister_driver done\n"); + + libqdma_exit(); + SLASH_QDMA_OP_LOG("libqdma_exit done\n"); +} + +/* ───────────────────────────────────────────────────────────────────── + * PCI probe / remove + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_probe() - PCI probe callback for QDMA devices. + * @pdev: The PCI device being probed. + * @id: Matching entry from slash_qdma_ids[]. + * + * Verifies that the device is PF1 (the QDMA IP is only on PF1; PF2 is + * the control function handled by slash_ctldev). Then: + * 1. Allocates and initialises a slash_qdma_dev structure. + * 2. Configures and opens the libqdma device via qdma_device_open(). + * 3. Registers the management miscdevice (/dev/slash_qdma_ctlN). + * + * On any failure, the partially-constructed device is torn down and + * the probe returns the error. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int err; + struct qdma_dev_conf conf; + struct slash_qdma_dev *device = NULL; + + memset(&conf, 0, sizeof(conf)); + + dev_info(&pdev->dev, "slash: qdma: probe start for %s\n", pci_name(pdev)); + SLASH_QDMA_OP_DEV_LOG(&pdev->dev, + "probe details: vendor=0x%04x device=0x%04x fn=%u\n", + pdev->vendor, pdev->device, PCI_FUNC(pdev->devfn)); + + /* Reject anything that is not PF1 — the QDMA IP lives only on PF1. */ + if (PCI_FUNC(pdev->devfn) != SLASH_QDMA_PF) { + dev_err(&pdev->dev, "slash: expected PF %u, got %u\n", SLASH_QDMA_PF, PCI_FUNC(pdev->devfn)); + return -EINVAL; + } + + /* Allocate and initialise the per-device structure. */ + err = slash_qdma_create_qdma_device(pdev, &device); + if (err) { + goto err_free; + } + + /* Configure and open the libqdma device. */ + slash_qdma_conf_options(&conf, pdev); + SLASH_QDMA_OP_DEV_LOG(&pdev->dev, + "qdma_device_open start: name=%s qsets_max=%d qsets_base=%d\n", + SLASH_NAME, conf.qsets_max, conf.qsets_base); + err = qdma_device_open(SLASH_NAME, &conf, &device->qdma_handle); + if (err) { + SLASH_QDMA_OP_DEV_LOG(&pdev->dev, "qdma_device_open failed: err=%d\n", + err); + dev_err(&pdev->dev, "slash: qdma: could not open qdma device %d", err); + goto err_free; + } + SLASH_QDMA_OP_DEV_LOG(&pdev->dev, + "qdma_device_open done: handle=%lu\n", + device->qdma_handle); + device->have_qdma_handle = true; + + /* Register the management miscdevice so userspace can issue ioctls. */ + err = misc_register(&device->misc); + if (err) { + dev_err(&pdev->dev, "slash: qdma: could not register misc device: %d", err); + /* + * is_misc_registered is still false here, so slash_qdma_destroy_qdma_device + * will not call misc_deregister or id_release. Release the id explicitly. + */ + slash_qdma_id_release(pci_name(pdev)); + goto err_free; + } + device->is_misc_registered = true; + + return 0; + +err_free: + if (device) { + slash_qdma_destroy_qdma_device(device); + kref_put(&device->ref, slash_qdma_dev_release); + } + + return err; +} + +/** + * slash_qdma_remove() - PCI remove callback for QDMA devices. + * @pdev: The PCI device being removed. + * + * Tears down all HW queues, closes the libqdma device, deregisters the + * miscdevice, and drops the device reference. + */ +static void slash_qdma_remove(struct pci_dev *pdev) +{ + struct slash_qdma_dev *device = pci_get_drvdata(pdev); + + if (!device) + return; + + slash_qdma_destroy_qdma_device(device); + kref_put(&device->ref, slash_qdma_dev_release); +} + +/* ───────────────────────────────────────────────────────────────────── + * Device allocation and teardown + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_create_qdma_device() - Allocate and initialise a QDMA device. + * @pdev: PCI device to bind to. + * @pdevice: [out] Receives a pointer to the new device on success. + * + * Allocates the slash_qdma_dev, initialises its mutex, xarray, kref, + * and miscdevice fields, and stores it in the PCI drvdata. A static + * atomic counter provides unique /dev node numbering across devices. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_create_qdma_device(struct pci_dev *pdev, struct slash_qdma_dev **pdevice) +{ + int err; + struct slash_qdma_dev *device; + int id; + + device = kzalloc(sizeof(*device), GFP_KERNEL); + if (!device) { + return -ENOMEM; + } + device->pdev = pdev; + kref_init(&device->ref); + mutex_init(&device->lock); + xa_init_flags(&device->qpairs, XA_FLAGS_ALLOC); + device->hw_shutdown = false; + pci_set_drvdata(pdev, device); + + { /* Miscdevice setup */ + device->misc.minor = MISC_DYNAMIC_MINOR; + device->misc.fops = &slash_qdma_fops; + device->misc.parent = &pdev->dev; + device->misc.mode = SLASH_CTLDEV_QDMA_MODE; + + /* Name visible in /sys/class/misc, includes PCI BDF for uniqueness. */ + device->misc.name = kasprintf(GFP_KERNEL, SLASH_QDMA_CTLDEV_NAME_FMT, pci_name(device->pdev)); + if (!device->misc.name) { + dev_err(&device->pdev->dev, "qdma: kasprintf(name) failed\n"); + err = -ENOMEM; + goto err_free; + } + + /* /dev node name: stable numeric index from BDF-to-number map. */ + id = slash_qdma_id_get(pci_name(device->pdev)); + if (id < 0) { + dev_err(&device->pdev->dev, "qdma: id_get failed: %d\n", id); + err = id; + goto err_free_name; + } + + device->misc.nodename = kasprintf(GFP_KERNEL, SLASH_QDMA_CTLDEV_NODENAME_FMT, id); + if (!device->misc.nodename) { + dev_err(&device->pdev->dev, "qdma: kasprintf(nodename) failed\n"); + err = -ENOMEM; + goto err_release_id; + } + } + + *pdevice = device; + return 0; + +err_release_id: + slash_qdma_id_release(pci_name(device->pdev)); + +err_free_name: + kfree(device->misc.name); + device->misc.name = NULL; + +err_free: + slash_qdma_destroy_qdma_device(device); + *pdevice = NULL; + + return err; +} + +/** + * slash_qdma_destroy_qdma_device() - Tear down a QDMA device. + * @device: The device to destroy. + * + * Idempotent: uses @hw_shutdown to ensure the teardown sequence runs + * only once even if called from multiple paths (e.g., probe error + + * remove). + * + * Teardown order: + * 1. Set @hw_shutdown = true (prevents new ioctls). + * 2. Deregister the miscdevice (prevents new opens). + * 3. Iterate all queue pairs: stop, remove each HW queue, erase from + * xarray, and drop the xarray's ref. + * 4. Destroy the xarray. + * 5. Close the libqdma device handle. + * + * Note: the device structure itself is freed later by the kref callback + * (slash_qdma_dev_release) when the last reference drops. + */ +static void slash_qdma_destroy_qdma_device(struct slash_qdma_dev *device) +{ + int err; + + if (!device) { + return; + } + + mutex_lock(&device->lock); + if (device->hw_shutdown) { + mutex_unlock(&device->lock); + return; + } + device->hw_shutdown = true; + mutex_unlock(&device->lock); + + /* Detach from PCI drvdata so no new lookups can find us. */ + pci_set_drvdata(device->pdev, NULL); + + /* Deregister miscdevice to prevent new file opens. */ + if (device->is_misc_registered) { + misc_deregister(&device->misc); + slash_qdma_id_release(pci_name(device->pdev)); + device->is_misc_registered = false; + } + + mutex_lock(&device->lock); + + { + /* + * Tear down all remaining queue pairs. This handles the case + * where userspace did not cleanly delete its queues before the + * device is removed (e.g., surprise removal or unclean exit). + */ + struct slash_qdma_qpair_entry *entry; + unsigned long index; + unsigned int idx; + + xa_for_each(&device->qpairs, index, entry) { + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + + if (!(entry->dir_mask & dir_bit)) + continue; + + slash_qdma_ioctl_qpair_rm_q(&device->misc, device, entry, qtype); + } + xa_erase(&device->qpairs, index); + slash_qdma_qpair_put(entry); + } + xa_destroy(&device->qpairs); + } + + /* Close the libqdma device handle, releasing HW resources. */ + if (device->have_qdma_handle) { + SLASH_QDMA_OP_DEV_LOG(&device->pdev->dev, + "qdma_device_close start: handle=%lu\n", + device->qdma_handle); + err = qdma_device_close(device->pdev, device->qdma_handle); + if (err) { + SLASH_QDMA_OP_DEV_LOG(&device->pdev->dev, + "qdma_device_close failed: err=%d\n", err); + dev_err(&device->pdev->dev, "Error in qdma_device_close: %d\n", err); + } else { + SLASH_QDMA_OP_DEV_LOG(&device->pdev->dev, + "qdma_device_close done\n"); + } + device->have_qdma_handle = false; + } + + mutex_unlock(&device->lock); +} + +/** + * slash_qdma_dev_release() - kref release callback for the QDMA device. + * @ref: kref embedded in the slash_qdma_dev being released. + * + * Called when the last reference drops (after both the miscdevice is + * closed and all anon_inode fds are released). Frees the dynamically + * allocated miscdevice name/nodename strings and the device structure. + */ +static void slash_qdma_dev_release(struct kref *ref) +{ + struct slash_qdma_dev *device = + container_of(ref, struct slash_qdma_dev, ref); + + mutex_destroy(&device->lock); + + if (device->misc.name) { + kfree(device->misc.name); + } + + if (device->misc.nodename) { + kfree(device->misc.nodename); + } + + kfree(device); +} + +/* ───────────────────────────────────────────────────────────────────── + * libqdma device configuration + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_conf_options() - Populate the qdma_dev_conf for device open. + * @conf: Configuration structure to fill in. + * @pdev: PCI device being opened. + * + * Sets up the libqdma device configuration with parameters tuned for + * the V80 SLASH design: + * + * - qsets_max = 256: maximum number of queue pairs (matches + * SLASH_QDMA_MAX_QPAIRS). + * - zerolen_dma = 0: zero-length transfers are disallowed. + * - master_pf = 1: this is the master physical function. + * - qdma_drv_mode = POLL_MODE: avoids interrupt overhead for + * streaming workloads. The host polls HW-written completion + * status in memory instead of waiting for MSI-X interrupts. + * - msix_qvec_max = 32: Versal-specific MSI-X vector limit for + * queues. Even though we use poll mode, libqdma still needs + * a non-zero value here for internal setup. + * - intr_rngsz = INTR_RING_SZ_4KB: interrupt ring size from the + * reference driver defaults. + * - bar_num_config = 0: BAR 0 is the configuration BAR. + * - bar_num_user / bar_num_bypass = -1: not used in this design. + * - qsets_base = -1: let libqdma auto-assign the queue set base. + * - All optional callbacks (ISR handlers, FLR resource free) are + * set to NULL since we operate in poll mode. + */ +static void slash_qdma_conf_options(struct qdma_dev_conf *conf, struct pci_dev *pdev) +{ + conf->pdev = pdev; + conf->qsets_max = 256; /* Maximum number of queue paris. Might be lowered. TODO: tune */ + conf->zerolen_dma = 0; /* Disallow 0-length transfers */ + conf->master_pf = 1; /* This is the master PF */ + conf->intr_moderation = 1; + conf->vf_max = 8; + conf->intr_rngsz = INTR_RING_SZ_4KB; // TODO: tune + + // Ask for as many queue MSI-X vectors as you'd like to dedicate to queues + conf->msix_qvec_max = 32; // For Versal + conf->user_msix_qvec_max = 1; + conf->data_msix_qvec_max = 5; + + conf->qdma_drv_mode = POLL_MODE; // TODO: experiment with this + conf->uld = 0; + + conf->bar_num_config = 0; + conf->bar_num_user = -1; + conf->bar_num_bypass = -1; + conf->qsets_base = -1; + + // Optional callbacks + conf->fp_user_isr_handler = NULL; + conf->fp_q_isr_top_dev = NULL; + conf->fp_flr_free_resource= NULL; + conf->debugfs_dev_root = NULL; +} + +/* ───────────────────────────────────────────────────────────────────── + * Miscdevice file operations (management interface) + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_fop_ioctl() - Dispatch ioctls on the QDMA control miscdevice. + * @file: Open file for the miscdevice. + * @op: Ioctl command number. + * @arg: User-space argument pointer. + * + * Routes incoming ioctls to the appropriate handler: + * - SLASH_QDMA_IOCTL_INFO: query QDMA capabilities + * - SLASH_QDMA_IOCTL_QPAIR_ADD: allocate a new queue pair + * - SLASH_QDMA_IOCTL_Q_OP: start/stop/delete a queue pair + * - SLASH_QDMA_IOCTL_QPAIR_GET_FD: obtain an I/O fd for a queue pair + * + * All paths check @hw_shutdown before proceeding to reject ioctls + * that arrive during or after device teardown. + * + * Return: 0 or positive fd on success, negative errno on failure. + */ +static long slash_qdma_fop_ioctl(struct file *file, unsigned int op, unsigned long arg) +{ + struct slash_qdma_dev *qdma_dev = file->private_data; + struct miscdevice *misc = &qdma_dev->misc; + void __user *uarg = (void __user *)arg; + long ret = 0; + + if (!qdma_dev) + return -ENODEV; + + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, "ioctl op=0x%x\n", op); + + /* Early rejection if the device is shutting down. */ + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + mutex_unlock(&qdma_dev->lock); + + switch (op) { + case SLASH_QDMA_IOCTL_INFO: + ret = slash_qdma_ioctl_info_w(misc, qdma_dev, uarg); + break; + + case SLASH_QDMA_IOCTL_QPAIR_ADD: + ret = slash_qdma_ioctl_qpair_add_w(misc, qdma_dev, uarg); + break; + + case SLASH_QDMA_IOCTL_Q_OP: + ret = slash_qdma_ioctl_qpair_op_w(misc, qdma_dev, uarg); + break; + + case SLASH_QDMA_IOCTL_QPAIR_GET_FD: + ret = slash_qdma_ioctl_qpair_get_fd_w(misc, qdma_dev, uarg); + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/** + * slash_qdma_fop_open() - Open handler for the QDMA control miscdevice. + * @inode: Inode of the device node. + * @file: File being opened. + * + * The misc framework sets file->private_data to the miscdevice before + * calling open. We use container_of to recover the slash_qdma_dev, + * take a device reference, and stash the device pointer in private_data + * so that subsequent ioctl/release calls can find it directly. + * + * Return: 0 on success, -ENODEV if the device is shutting down. + */ +static int slash_qdma_fop_open(struct inode *inode, struct file *file) +{ + struct miscdevice *misc = file->private_data; + struct slash_qdma_dev *qdma_dev = + container_of(misc, struct slash_qdma_dev, misc); + int ret = 0; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + ret = -ENODEV; + } else { + kref_get(&qdma_dev->ref); + file->private_data = qdma_dev; + } + mutex_unlock(&qdma_dev->lock); + + return ret; +} + +/** + * slash_qdma_fop_release() - Release handler for the QDMA control miscdevice. + * @inode: Inode of the device node. + * @file: File being closed. + * + * Drops the device reference acquired in open. If this is the last + * reference, the device structure is freed. + * + * Return: Always 0. + */ +static int slash_qdma_fop_release(struct inode *inode, struct file *file) +{ + struct slash_qdma_dev *qdma_dev = file->private_data; + + if (qdma_dev) + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + + return 0; +} + +/* ───────────────────────────────────────────────────────────────────── + * IOCTL: info + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_ioctl_info_w() - Wrapper for the QDMA info ioctl. + * @misc: Miscdevice handle. + * @qdma_dev: QDMA device. + * @uarg: User-space pointer to a slash_qdma_info struct. + * + * Implements the versioned copy-in / copy-out pattern: + * 1. Read the leading @size field to learn how large the caller's + * struct is (ABI forward/backward compatibility). + * 2. Fill the kernel-side struct via slash_qdma_ioctl_info(). + * 3. Copy back only min(user_size, kernel_size) bytes. + * + * Return: 0 on success, -EFAULT on copy failure, -ENODEV if shutting down. + */ +static int slash_qdma_ioctl_info_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_info info; + u32 user_size = 0; + size_t copy_size; + + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + memset(&info, 0, sizeof(info)); + info.size = sizeof(info); + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + slash_qdma_ioctl_info(misc, qdma_dev, &info); + mutex_unlock(&qdma_dev->lock); + + copy_size = min_t(size_t, user_size, sizeof(info)); + if (copy_to_user(uarg, &info, copy_size)) + return -EFAULT; + if (user_size > sizeof(info)) { + if (clear_user((void __user *)((unsigned long)uarg + sizeof(info)), + user_size - sizeof(info))) + return -EFAULT; + } + + return 0; +} + +/** + * slash_qdma_ioctl_info() - Populate QDMA capability information. + * @misc: Miscdevice handle (unused). + * @qdma_dev: QDMA device (unused for now). + * @qdma_info: [out] Structure to fill with capability data. + * + * Currently returns zeroes for all fields. This is a placeholder for + * future capability reporting (e.g., querying qdma_device_capabilities). + */ +static void slash_qdma_ioctl_info(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_info *qdma_info) +{ + (void) misc; + (void) qdma_dev; + + qdma_info->qsets_max = 0; + qdma_info->msix_qvecs = 0; + qdma_info->vf_max = 0; + qdma_info->caps = 0; +} + +/* ───────────────────────────────────────────────────────────────────── + * IOCTL: qpair add + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_ioctl_qpair_add_w() - Wrapper for the qpair-add ioctl. + * @misc: Miscdevice handle. + * @qdma_dev: QDMA device. + * @uarg: User-space pointer to a slash_qdma_qpair_add struct. + * + * Validates userspace inputs: + * - @dir_mask must contain only valid direction bits and be non-zero. + * - @mode must be MM or ST. + * - Ring size indices must be in [0, 15] (CSR table range). + * + * On success, the kernel-assigned @qid is written back to userspace. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_ioctl_qpair_add_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_qpair_add req; + __u32 user_size = 0; + size_t copy_size; + u32 dir_mask; + int err; + + /* + * First, fetch the size field from userspace so we can + * safely handle callers built against older or newer + * versions of the struct. + */ + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + memset(&req, 0, sizeof(req)); + + if (copy_from_user(&req, uarg, min_t(size_t, user_size, sizeof(req)))) + return -EFAULT; + + /* Validate direction mask: must be non-zero and contain only known bits. */ + dir_mask = req.dir_mask & SLASH_QDMA_DIR_MASK; + if (!dir_mask || dir_mask != req.dir_mask) + return -EINVAL; + + /* Only memory-mapped and streaming modes are supported. */ + if (req.mode != QDMA_Q_MODE_MM && req.mode != QDMA_Q_MODE_ST) + return -EINVAL; + + /* + * Ring size fields are CSR table indices (0-15), not raw descriptor + * counts. Each index selects a pre-programmed ring depth from the + * global CSR ring-size table. + */ + if (req.h2c_ring_sz >= 16 || req.c2h_ring_sz >= 16 || req.cmpt_ring_sz >= 16) + return -EINVAL; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + err = slash_qdma_ioctl_qpair_add(misc, qdma_dev, &req); + mutex_unlock(&qdma_dev->lock); + + if (err) + return err; + + /* + * On success, update the size field to reflect the + * kernel's view of the struct and copy back only as + * many bytes as the caller originally provided. + */ + req.size = sizeof(req); + copy_size = min_t(size_t, user_size, sizeof(req)); + if (copy_to_user(uarg, &req, copy_size)) + return -EFAULT; + if (user_size > sizeof(req)) { + if (clear_user((void __user *)((unsigned long)uarg + sizeof(req)), + user_size - sizeof(req))) + return -EFAULT; + } + + return err; +} + +/** + * slash_qdma_ioctl_qpair_add() - Allocate a qpair and add its constituent queues. + * @misc: Miscdevice handle. + * @qdma_dev: QDMA device. + * @req: Add request (dir_mask, mode, ring sizes); @qid is set on success. + * + * Allocates a slash_qdma_qpair_entry, inserts it into the xarray (which + * auto-assigns the qpair ID), and then iterates over the requested + * directions to add each individual HW queue. If any queue addition + * fails, all previously-added queues are rolled back and the xarray + * entry is removed. + * + * The xarray-assigned ID is used as the QDMA queue index for all queues + * in the pair, so H2C queue N and C2H queue N share the same index. + * Any qid value provided by userspace in the request is ignored. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_ioctl_qpair_add(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req) +{ + struct slash_qdma_qpair_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); + unsigned int idx; + bool added[SLASH_QDMA_QTYPE_COUNT] = {0}; + int ret = 0; + + if (!entry) + return -ENOMEM; + + entry->mode = req->mode; + entry->irq_mode = 0; + entry->irq_vector = 0; + + /* Initialise all queue handles to invalid (not yet added). */ + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) + entry->qhndl[idx] = QDMA_QUEUE_IDX_INVALID; + + /* + * Allocate a new qpair ID in the xarray and use it as the + * QDMA queue index for all queues in this pair. Any qid + * value provided by userspace is ignored. + */ + ret = slash_qdma_qpair_insert(qdma_dev, entry, &req->qid); + if (ret) { + dev_err(&qdma_dev->pdev->dev, + "qdma: qpair insert failed: %d\n", ret); + kfree(entry); + return ret; + } + + /* Add each requested direction's HW queue. */ + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + + if (!(req->dir_mask & dir_bit)) + continue; + + ret = slash_qdma_ioctl_qpair_add_q(misc, qdma_dev, req, entry, qtype); + if (ret) + goto rollback; + + added[idx] = true; + } + + return 0; + +rollback: + /* Undo any queues that were successfully added before the failure. */ + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + if (added[idx]) + slash_qdma_ioctl_qpair_rm_q(misc, qdma_dev, entry, idx); + } + + slash_qdma_qpair_remove(qdma_dev, req->qid); + + return ret; +} + +/** + * slash_qdma_ioctl_qpair_add_q() - Add a single HW queue to a queue pair. + * @misc: Miscdevice handle (for error logging context). + * @qdma_dev: QDMA device. + * @req: The add request (provides queue index, mode, and ring sizes). + * @entry: The qpair entry to attach the new queue to. + * @qtype: Which queue type to add (Q_H2C, Q_C2H, or Q_CMPT). + * + * Fills a qdma_queue_conf structure and calls qdma_queue_add(). The + * configuration fields deserve detailed explanation: + * + * - qconf.qidx: set to the xarray-assigned qpair ID so all queues + * in a pair share the same HW queue index. + * - qconf.st: 1 for streaming mode (QDMA_Q_MODE_ST), 0 for memory- + * mapped (QDMA_Q_MODE_MM). Streaming uses AXI-Stream for data + * transfer; MM uses AXI Memory Mapped. + * - qconf.irq_en = 0: interrupts disabled — we use poll mode. + * - qconf.cmpl_en_intr = 0: no completion interrupts — poll mode. + * - qconf.cmpl_trig_mode = TRIG_MODE_DISABLE: no automatic completion + * trigger; the host explicitly polls for completion status. + * - qconf.wb_status_en = 1: enables HW write-back of completion status + * to host memory, which is how the poll-mode driver detects transfer + * completion. + * - qconf.cmpl_status_acc_en = 1: accumulate completion status entries + * (required for poll-mode operation per the reference driver). + * - qconf.cmpl_status_pend_chk = 1: check for pending completions + * (required for poll-mode operation per the reference driver). + * - qconf.cmpl_stat_en = 1: enable completion status generation + * (required for poll-mode operation per the reference driver). + * - qconf.aperture_size = 4096: page-granularity (4 KB) for descriptor + * addressing. Each descriptor addresses one page-sized chunk. + * - qconf.desc_rng_sz_idx: CSR table index (0-15) selecting the + * descriptor ring depth. Not a raw descriptor count — the actual + * count is looked up from the global CSR ring-size table. + * - qconf.cmpl_rng_sz_idx: same as desc_rng_sz_idx but for the + * completion ring (C2H and CMPT queues only). + * - qconf.cmpl_desc_sz = CMPT_DESC_SZ_16B: 16-byte completion + * descriptors (C2H and CMPT queues only). + * + * For CMPT-type queues, streaming mode is forced off (qconf.st = 0) + * because the completion queue is always memory-mapped regardless of + * the data queue mode. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_ioctl_qpair_add_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_add *req, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype) +{ + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + struct qdma_queue_conf qconf = {0}; + char errbuf[128] = {0}; + u32 dir_mask = req->dir_mask; + int err; + unsigned long qhndl = QDMA_QUEUE_IDX_INVALID; + + if (!(dir_mask & dir_bit)) + return -EINVAL; + + /* --- Common queue configuration (all directions) --- */ + qconf.qidx = req->qid; /* Use xarray-assigned ID as HW queue index */ + qconf.q_type = qtype; + qconf.st = (req->mode == QDMA_Q_MODE_ST); /* Streaming vs memory-mapped */ + qconf.irq_en = 0; /* Poll mode: no interrupts */ + qconf.cmpl_en_intr = 0; /* Poll mode: no completion interrupts */ + qconf.cmpl_trig_mode = TRIG_MODE_DISABLE; /* No auto-trigger; we poll explicitly */ + + qconf.wb_status_en = 1; /* HW writes completion status to host memory */ + qconf.cmpl_status_acc_en = 1; /* Accumulate completion status (poll-mode req) */ + qconf.cmpl_status_pend_chk = 1; /* Check pending completions (poll-mode req) */ + qconf.cmpl_stat_en = 1; /* Enable completion status generation */ + + qconf.aperture_size = 4096; /* Page-granularity descriptor addressing */ + + /* --- Per-direction ring configuration --- */ + switch (qtype) { + case Q_H2C: + qconf.desc_rng_sz_idx = req->h2c_ring_sz; /* CSR table index for H2C descriptor ring */ + break; + case Q_C2H: + qconf.desc_rng_sz_idx = req->c2h_ring_sz; /* CSR table index for C2H descriptor ring */ + qconf.cmpl_rng_sz_idx = req->cmpt_ring_sz; /* CSR table index for C2H completion ring */ + qconf.cmpl_desc_sz = CMPT_DESC_SZ_16B; /* 16-byte completion descriptors */ + break; + case Q_CMPT: + qconf.st = 0; /* CMPT queue is always memory-mapped */ + qconf.desc_rng_sz_idx = req->cmpt_ring_sz; + qconf.cmpl_rng_sz_idx = req->cmpt_ring_sz; + qconf.cmpl_desc_sz = CMPT_DESC_SZ_16B; /* 16-byte completion descriptors */ + qconf.cmpl_en_intr = 0; /* Redundant but explicit: no CMPT interrupts */ + break; + default: + break; + } + + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_queue_add start: qid=%u type=%u mode=%u\n", + req->qid, qtype, req->mode); + err = qdma_queue_add(qdma_dev->qdma_handle, &qconf, &qhndl, + errbuf, sizeof(errbuf)); + if (err) { + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_queue_add failed: qid=%u type=%u err=%d (%s)\n", + req->qid, qtype, err, errbuf); + dev_err(&qdma_dev->pdev->dev, + "qdma: queue add failed (qid=%u, type=%u): %d (%s)\n", + req->qid, qtype, err, errbuf); + return err; + } + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_queue_add done: qid=%u type=%u qhndl=%lu\n", + req->qid, qtype, qhndl); + + /* Record the handle and mark this direction as active. */ + entry->qhndl[qtype] = qhndl; + entry->dir_mask |= dir_bit; + + return 0; +} + +/** + * slash_qdma_ioctl_qpair_rm_q() - Remove a single HW queue from a queue pair. + * @misc: Miscdevice handle (for logging context). + * @qdma_dev: QDMA device. + * @entry: The qpair entry to remove the queue from. + * @qtype: Which queue type to remove (Q_H2C, Q_C2H, or Q_CMPT). + * + * Uses slash_qdma_queue_remove_safe() to handle all possible HW queue + * states (online, enabled, or already disabled). On completion, the + * queue handle is set to QDMA_QUEUE_IDX_INVALID and the direction bit + * is cleared from the entry's dir_mask. + * + * Errors are logged but not propagated — this is best-effort cleanup + * used during teardown. + */ +static void slash_qdma_ioctl_qpair_rm_q(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + enum queue_type_t qtype) +{ + unsigned long qhndl = entry->qhndl[qtype]; + char errbuf[128] = {0}; + int err; + + /* If the handle is already invalid, just clear state and return. */ + if (!slash_qdma_qhndl_is_valid(qhndl)) { + entry->qhndl[qtype] = QDMA_QUEUE_IDX_INVALID; + entry->dir_mask &= ~slash_qdma_qtype_to_dir(qtype); + return; + } + + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "queue_remove_safe start: type=%u qhndl=%lu\n", + qtype, qhndl); + err = slash_qdma_queue_remove_safe(qdma_dev->qdma_handle, qhndl, + errbuf, sizeof(errbuf)); + + if (err) { + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "queue_remove_safe failed: type=%u qhndl=%lu err=%d (%s)\n", + qtype, qhndl, err, errbuf); + dev_err(&qdma_dev->pdev->dev, + "qdma: queue remove failed (type=%u): %d (%s)\n", + qtype, err, errbuf); + return; + } + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "queue_remove_safe done: type=%u qhndl=%lu\n", + qtype, qhndl); + + entry->qhndl[qtype] = QDMA_QUEUE_IDX_INVALID; + entry->dir_mask &= ~slash_qdma_qtype_to_dir(qtype); +} + +/* ───────────────────────────────────────────────────────────────────── + * IOCTL: qpair op (start / stop / delete) + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_ioctl_qpair_op_w() - Wrapper for the qpair operation ioctl. + * @misc: Miscdevice handle. + * @qdma_dev: QDMA device. + * @uarg: User-space pointer to a slash_qdma_qpair_op struct. + * + * Handles the versioned copy-in / copy-out pattern and validates that + * the requested operation is within the known range. + * + * Return: 0 on success, negative errno on failure. + */ +static int slash_qdma_ioctl_qpair_op_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_qpair_op req; + __u32 user_size = 0; + size_t copy_size; + int ret; + + /* + * First, fetch the size field from userspace so we can + * safely handle callers built against older or newer + * versions of the struct. + */ + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + memset(&req, 0, sizeof(req)); + + if (copy_from_user(&req, uarg, min_t(size_t, user_size, sizeof(req)))) + return -EFAULT; + + if (req.op > SLASH_QDMA_QUEUE_OP_DEL) + return -EINVAL; + + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + ret = slash_qdma_ioctl_qpair_op(misc, qdma_dev, &req); + mutex_unlock(&qdma_dev->lock); + + if (ret) + return ret; + + /* + * On success, update the size field to reflect the + * kernel's view of the struct and copy back only as + * many bytes as the caller originally provided. + */ + req.size = sizeof(req); + copy_size = min_t(size_t, user_size, sizeof(req)); + if (copy_to_user(uarg, &req, copy_size)) + return -EFAULT; + if (user_size > sizeof(req)) { + if (clear_user((void __user *)((unsigned long)uarg + sizeof(req)), + user_size - sizeof(req))) + return -EFAULT; + } + + return ret; +} + +/** + * slash_qdma_ioctl_qpair_op() - Dispatch a lifecycle operation on a queue pair. + * @misc: Miscdevice handle (unused, present for API consistency). + * @qdma_dev: QDMA device. + * @req: Operation request (@qid identifies the target, @op selects + * the action). + * + * Looks up the qpair entry and dispatches to slash_qdma_ioctl_qpair_op_apply() + * with the appropriate libqdma function pointer: + * + * - START: qdma_queue_start (stop_on_err=true — fail fast) + * - STOP: qdma_queue_stop (stop_on_err=true — fail fast) + * - DEL: slash_qdma_queue_remove_safe (stop_on_err=false — best effort, + * try to remove as many queues as possible even if one fails); + * on success, also removes the entry from the xarray. + * + * Return: 0 on success, -ENOENT if qpair not found, other negative errno + * from the underlying libqdma call. + */ +static int slash_qdma_ioctl_qpair_op(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_op *req) +{ + struct slash_qdma_qpair_entry *entry; + int ret = 0; + + (void) misc; + + if (!qdma_dev->have_qdma_handle) + return -ENODEV; + + entry = slash_qdma_qpair_lookup(qdma_dev, req->qid); + if (!entry) + return -ENOENT; + + switch (req->op) { + case SLASH_QDMA_QUEUE_OP_START: + ret = slash_qdma_ioctl_qpair_op_apply(qdma_dev, entry, req, + qdma_queue_start, + "start", true); + break; + case SLASH_QDMA_QUEUE_OP_STOP: + ret = slash_qdma_ioctl_qpair_op_apply(qdma_dev, entry, req, + qdma_queue_stop, + "stop", true); + break; + case SLASH_QDMA_QUEUE_OP_DEL: + /* + * For delete, use stop_on_err=false to attempt removal of all + * directions even if one fails, then remove from the xarray. + */ + ret = slash_qdma_ioctl_qpair_op_apply(qdma_dev, entry, req, + slash_qdma_queue_remove_safe, + "remove", false); + if (!ret) + slash_qdma_qpair_remove(qdma_dev, req->qid); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +/** + * slash_qdma_ioctl_qpair_op_apply() - Apply a lifecycle operation to all queues in a pair. + * @qdma_dev: QDMA device. + * @entry: Queue pair entry. + * @req: Operation request (used for @qid in log messages). + * @fn: The libqdma function to call per queue (e.g., qdma_queue_start). + * @op_name: Human-readable operation name for log messages. + * @stop_on_err: If true, return immediately on the first error. + * If false, continue through all directions and return + * the first error encountered. + * + * Iterates over all queue types (H2C, C2H, CMPT). For each direction + * that is active in the entry's dir_mask, calls @fn with the corresponding + * queue handle. + * + * Return: 0 if all calls succeed, otherwise the first negative errno. + */ +static int slash_qdma_ioctl_qpair_op_apply(struct slash_qdma_dev *qdma_dev, + struct slash_qdma_qpair_entry *entry, + struct slash_qdma_qpair_op *req, + slash_qdma_queue_cmd_fn fn, + const char *op_name, + bool stop_on_err) +{ + int idx; + int first_err = 0; + + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + u32 dir_bit = slash_qdma_qtype_to_dir(qtype); + char errbuf[128] = {0}; + int err; + + /* Skip directions not present in this queue pair. */ + if (!(entry->dir_mask & dir_bit) || + !slash_qdma_qhndl_is_valid(entry->qhndl[qtype])) + continue; + + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_queue_%s start: qid=%u type=%u qhndl=%lu\n", + op_name, req->qid, qtype, entry->qhndl[qtype]); + err = fn(qdma_dev->qdma_handle, entry->qhndl[qtype], + errbuf, (int)sizeof(errbuf)); + if (err) { + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_queue_%s failed: qid=%u type=%u qhndl=%lu err=%d (%s)\n", + op_name, req->qid, qtype, entry->qhndl[qtype], err, errbuf); + dev_err(&qdma_dev->pdev->dev, + "qdma: queue %s failed (qid=%u, type=%u): %d (%s)\n", + op_name, req->qid, qtype, err, errbuf); + + if (stop_on_err) + return err; + + if (!first_err) + first_err = err; + } else { + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_queue_%s done: qid=%u type=%u qhndl=%lu\n", + op_name, req->qid, qtype, entry->qhndl[qtype]); + } + } + + return first_err; +} + +/* ───────────────────────────────────────────────────────────────────── + * DMA I/O: user buffer mapping, SGL construction, and transfer + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_iocb_release() - Free resources in an I/O control block. + * @iocb: The IOCB to clean up. + * + * Frees the combined SGL + page-pointer allocation and clears the + * pointers. Does not unpin pages — that must be done separately via + * slash_qdma_unmap_user_buf() before calling this. + */ +static inline void slash_qdma_iocb_release(struct slash_qdma_io_cb *iocb) +{ + if (iocb->pages) + iocb->pages = NULL; + + kfree(iocb->sgl); + iocb->sgl = NULL; + iocb->buf = NULL; +} + +/** + * slash_qdma_unmap_user_buf() - Unpin user pages after a DMA transfer. + * @iocb: I/O control block with pinned pages. + * @write: Transfer direction from the device's perspective. If false + * (i.e., a C2H/read transfer), the pages were written to by the + * device and must be marked dirty so the VM knows the page + * contents have changed. + * + * Iterates over pinned pages, marks them dirty if this was a read (C2H) + * transfer (because the device wrote data into those user pages), and + * releases each page reference acquired by get_user_pages_fast(). + */ +static void slash_qdma_unmap_user_buf(struct slash_qdma_io_cb *iocb, bool write) +{ + int i; + + if (!iocb->pages || !iocb->pages_nr) + return; + + for (i = 0; i < iocb->pages_nr; i++) { + if (iocb->pages[i]) { + /* + * For C2H (read) transfers (!write), the device wrote into + * these user pages, so mark them dirty to inform the VM. + */ + if (!write) + set_page_dirty(iocb->pages[i]); + put_page(iocb->pages[i]); + } else { + break; + } + } + + if (i != iocb->pages_nr) + pr_err("slash: qdma: sgl pages %d/%u.\n", i, iocb->pages_nr); + + iocb->pages_nr = 0; +} + +/** + * slash_qdma_map_user_buf_to_sgl() - Pin user pages and build a scatter-gather list. + * @iocb: I/O control block. @iocb->buf and @iocb->len must be set + * before calling. On success, @iocb->sgl, @iocb->pages, and + * @iocb->pages_nr are populated. + * @write: Transfer direction (true = H2C write, false = C2H read). + * + * Steps: + * 1. Compute the number of pages spanned by the user buffer (accounting + * for the offset within the first page). + * 2. Allocate a single contiguous block for the SGL entries and the + * page pointer array (avoids two allocations). + * 3. Pin user pages via get_user_pages_fast() with write=1 (even for + * H2C, because libqdma may write status back). + * 4. Build the qdma_sw_sg linked list: one entry per page, with the + * first entry's offset reflecting the sub-page position of the + * user buffer, and the last entry's length truncated to the + * remaining byte count. + * 5. Flush the data cache for each page to ensure coherency between + * the CPU cache and the DMA engine's view of memory. + * + * Return: 0 on success, negative errno on failure (pages are unpinned + * and the SGL is freed on error). + */ +static int slash_qdma_map_user_buf_to_sgl(struct slash_qdma_io_cb *iocb, + bool write) +{ + unsigned long len = iocb->len; + char *buf = (char *)iocb->buf; + struct qdma_sw_sg *sg; + unsigned int pg_off = offset_in_page(buf); + unsigned int pages_nr = (len + pg_off + PAGE_SIZE - 1) >> PAGE_SHIFT; + int i; + int rv; + + if (len == 0) + pages_nr = 1; + if (pages_nr == 0) + return -EINVAL; + + iocb->pages_nr = 0; + + /* + * Single allocation for both the SGL array and the page pointer + * array. The page pointers are placed immediately after the SGL + * entries in memory. + */ + sg = kmalloc(pages_nr * (sizeof(struct qdma_sw_sg) + + sizeof(struct page *)), GFP_KERNEL); + if (!sg) { + pr_err("slash: qdma: sgl allocation failed for %u pages\n", + pages_nr); + return -ENOMEM; + } + memset(sg, 0, pages_nr * (sizeof(struct qdma_sw_sg) + + sizeof(struct page *))); + iocb->sgl = sg; + + /* Page pointer array lives right after the SGL entries. */ + iocb->pages = (struct page **)(sg + pages_nr); + + /* + * Pin the user pages into physical memory. The write=1 flag tells + * the kernel these pages may be written to (needed for C2H, but we + * always request write permission for simplicity). + */ + rv = get_user_pages_fast((unsigned long)buf, pages_nr, + 1 /* write */, iocb->pages); + if (rv < 0) { + pr_err("slash: qdma: unable to pin down %u user pages, %d\n", + pages_nr, rv); + goto err_out; + } + if (rv != pages_nr) { + pr_err("slash: qdma: unable to pin down all %u user pages, %d\n", + pages_nr, rv); + iocb->pages_nr = rv; + rv = -EFAULT; + goto err_out; + } + + /* + * Build the scatter-gather list. Each entry describes one page's + * worth of data. The first page may have a non-zero offset, and + * the last page may have fewer than PAGE_SIZE bytes. + */ + sg = iocb->sgl; + for (i = 0; i < pages_nr; i++, sg++) { + unsigned int offset = offset_in_page(buf); + unsigned int nbytes = min_t(unsigned int, + PAGE_SIZE - offset, len); + struct page *pg = iocb->pages[i]; + + /* Ensure CPU cache is flushed so the DMA engine sees fresh data. */ + flush_dcache_page(pg); + + sg->next = sg + 1; + sg->pg = pg; + sg->offset = offset; + sg->len = nbytes; + sg->dma_addr = 0UL; + + buf += nbytes; + len -= nbytes; + } + + /* Terminate the linked list. */ + iocb->sgl[pages_nr - 1].next = NULL; + iocb->pages_nr = pages_nr; + return 0; + +err_out: + slash_qdma_unmap_user_buf(iocb, write); + slash_qdma_iocb_release(iocb); + + return rv; +} + +/** + * slash_qdma_qpair_read_write() - Perform a DMA transfer via a qpair fd. + * @file: The anon_inode file for this queue pair. + * @buf: User-space buffer (source for write/H2C, destination for read/C2H). + * @count: Number of bytes to transfer. + * @ppos: File position — used as the device-side (endpoint) address. + * Updated on success to reflect the bytes transferred, enabling + * sequential positional I/O. + * @write: true for H2C (host-to-card write), false for C2H (card-to-host read). + * + * Transfer flow: + * 1. Validate context and check that the required direction (H2C or C2H) + * is enabled on this queue pair. + * 2. Pin user pages and build a scatter-gather list. + * 3. Populate a qdma_request: + * - ep_addr = *ppos: the device-side address (FPGA memory offset). + * - h2c_eot = 1: signals end-of-transfer to the FPGA, allowing it to + * process the complete data packet. + * - timeout_ms = 10000 (10 seconds): if the transfer doesn't complete + * in this time, qdma_request_submit returns an error. + * - fp_done = NULL: synchronous mode — the call blocks until completion. + * If fp_done were set, libqdma would call it asynchronously. + * - dma_mapped = 0: libqdma handles the DMA mapping internally. + * 4. Submit to libqdma via qdma_request_submit(). + * 5. On success, advance *ppos by the number of bytes transferred. + * 6. Unpin pages and free the SGL. + * + * Return: Number of bytes transferred (>= 0) on success, negative errno + * on failure. + */ +static ssize_t slash_qdma_qpair_read_write(struct file *file, char __user *buf, + size_t count, loff_t *ppos, + bool write) +{ + struct slash_qdma_qpair_file_ctx *ctx = file->private_data; + struct slash_qdma_dev *qdma_dev; + struct slash_qdma_qpair_entry *entry; + struct slash_qdma_io_cb iocb; + struct qdma_request *req; + unsigned long qhndl; + ssize_t res; + int rv; + + if (!ctx) + return -EINVAL; + + qdma_dev = ctx->qdma_dev; + entry = ctx->entry; + + if (!qdma_dev || !entry) + return -ENODEV; + + /* Check device liveness and resolve the queue handle for the direction. */ + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + + if (write) { + /* H2C: writing data from host to card */ + if (!(entry->dir_mask & SLASH_QDMA_DIR_H2C) || + !slash_qdma_qhndl_is_valid(entry->qhndl[Q_H2C])) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + qhndl = entry->qhndl[Q_H2C]; + } else { + /* C2H: reading data from card to host */ + if (!(entry->dir_mask & SLASH_QDMA_DIR_C2H) || + !slash_qdma_qhndl_is_valid(entry->qhndl[Q_C2H])) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + qhndl = entry->qhndl[Q_C2H]; + } + mutex_unlock(&qdma_dev->lock); + + /* Pin user pages and build the scatter-gather list. */ + memset(&iocb, 0, sizeof(iocb)); + iocb.buf = buf; + iocb.len = count; + rv = slash_qdma_map_user_buf_to_sgl(&iocb, write); + if (rv < 0) + return rv; + + /* Populate the libqdma request structure. */ + req = &iocb.req; + req->sgcnt = iocb.pages_nr; /* Number of SGL entries */ + req->sgl = iocb.sgl; /* Scatter-gather list */ + req->write = write ? 1 : 0; /* Direction flag for libqdma */ + req->dma_mapped = 0; /* Let libqdma handle DMA mapping */ + req->udd_len = 0; /* No user-defined data */ + req->ep_addr = (u64)*ppos; /* Device-side (endpoint) address */ + req->count = count; /* Total byte count */ + req->timeout_ms = 10 * 1000; /* 10-second timeout */ + req->fp_done = NULL; /* Synchronous: block until complete */ + req->h2c_eot = 1; /* End-of-transfer marker for FPGA */ + + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_request_submit start: qid=%u qhndl=%lu write=%d count=%zu ep_addr=0x%llx\n", + ctx->qid, qhndl, req->write, req->count, + (unsigned long long)req->ep_addr); + res = qdma_request_submit(qdma_dev->qdma_handle, qhndl, req); + SLASH_QDMA_OP_DEV_LOG(&qdma_dev->pdev->dev, + "qdma_request_submit done: qid=%u qhndl=%lu res=%zd\n", + ctx->qid, qhndl, res); + + /* Advance the file position by the number of bytes transferred. */ + if (res > 0) + *ppos += res; + + /* Unpin pages (marking dirty for C2H reads) and free the SGL. */ + slash_qdma_unmap_user_buf(&iocb, write); + slash_qdma_iocb_release(&iocb); + + return res; +} + +/** + * slash_qdma_qpair_read() - Read (C2H) file operation for a qpair fd. + * @file: Anon_inode file for the queue pair. + * @buf: User-space destination buffer. + * @count: Number of bytes to read. + * @ppos: Device-side address to read from. + * + * Thin wrapper that delegates to slash_qdma_qpair_read_write() with + * write=false (C2H direction). + * + * Return: Bytes transferred or negative errno. + */ +static ssize_t slash_qdma_qpair_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + return slash_qdma_qpair_read_write(file, buf, count, ppos, false); +} + +/** + * slash_qdma_qpair_write() - Write (H2C) file operation for a qpair fd. + * @file: Anon_inode file for the queue pair. + * @buf: User-space source buffer. + * @count: Number of bytes to write. + * @ppos: Device-side address to write to. + * + * Thin wrapper that delegates to slash_qdma_qpair_read_write() with + * write=true (H2C direction). + * + * Return: Bytes transferred or negative errno. + */ +static ssize_t slash_qdma_qpair_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + return slash_qdma_qpair_read_write(file, (char __user *)buf, + count, ppos, true); +} + +/** + * slash_qdma_qpair_ioctl() - Ioctl handler for per-qpair anon_inode fds. + * @file: Anon_inode file. + * @cmd: Ioctl command number. + * @arg: User-space argument. + * + * Currently a stub — no per-fd ioctls are defined. Returns -ENOTTY + * for all commands. + * + * Return: -ENOTTY (no valid ioctl). + */ +static long slash_qdma_qpair_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + (void)file; + (void)cmd; + (void)arg; + + return -ENOTTY; +} + +/** + * slash_qdma_qpair_release() - Release handler for per-qpair anon_inode fds. + * @inode: Inode (unused for anon_inodes). + * @file: The file being closed. + * + * Drops the references acquired in slash_qdma_ioctl_qpair_get_fd_w(): + * - One ref on the qpair entry (may free the entry if the qpair has + * already been deleted from the xarray). + * - One ref on the QDMA device (may free the device if it has already + * been removed from PCI). + * + * Also frees the file context structure. + * + * Return: Always 0. + */ +static int slash_qdma_qpair_release(struct inode *inode, struct file *file) +{ + struct slash_qdma_qpair_file_ctx *ctx = file->private_data; + + (void)inode; + + if (ctx) { + if (ctx->entry) + slash_qdma_qpair_put(ctx->entry); + if (ctx->qdma_dev) + kref_put(&ctx->qdma_dev->ref, slash_qdma_dev_release); + kfree(ctx); + file->private_data = NULL; + } + + return 0; +} + +/* ───────────────────────────────────────────────────────────────────── + * IOCTL: qpair get fd + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_ioctl_qpair_get_fd_w() - Create an anon_inode fd for a queue pair. + * @misc: Miscdevice handle (unused). + * @qdma_dev: QDMA device. + * @uarg: User-space pointer to a slash_qdma_qpair_fd_request struct. + * + * Creates an anonymous inode file descriptor that userspace can use + * for read() (C2H) and write() (H2C) DMA transfers on the specified + * queue pair. The fd holds references to both the qpair entry and the + * device, preventing either from being freed while the fd is open. + * + * The only supported flag is O_CLOEXEC (close-on-exec). + * + * The file is created with FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE + * enabled, allowing pread/pwrite and lseek to set the device-side + * address for DMA transfers. + * + * Error handling: on any failure after resources are acquired, all + * refs and allocations are cleaned up before returning. + * + * Return: The new fd (>= 0) on success, negative errno on failure. + */ +static int slash_qdma_ioctl_qpair_get_fd_w(struct miscdevice *misc, + struct slash_qdma_dev *qdma_dev, + void __user *uarg) +{ + struct slash_qdma_qpair_fd_request req; + __u32 user_size = 0; + size_t copy_size; + struct slash_qdma_qpair_entry *entry; + struct slash_qdma_qpair_file_ctx *ctx; + struct file *file; + int fd; + int err; + + (void)misc; + + if (copy_from_user(&user_size, uarg, sizeof(user_size))) + return -EFAULT; + + memset(&req, 0, sizeof(req)); + + if (copy_from_user(&req, uarg, min_t(size_t, user_size, sizeof(req)))) + return -EFAULT; + + /* Only O_CLOEXEC is a valid flag. */ + if (req.flags & ~O_CLOEXEC) + return -EINVAL; + + /* Look up the qpair entry and take refs while holding the lock. */ + mutex_lock(&qdma_dev->lock); + if (qdma_dev->hw_shutdown || !qdma_dev->have_qdma_handle) { + mutex_unlock(&qdma_dev->lock); + return -ENODEV; + } + + entry = slash_qdma_qpair_lookup(qdma_dev, req.qid); + if (!entry || !entry->dir_mask) { + mutex_unlock(&qdma_dev->lock); + return -ENOENT; + } + + /* + * Take a ref on the entry and the device. These refs are held by + * the file context and released when the fd is closed, ensuring + * neither the entry nor the device can be freed prematurely. + */ + slash_qdma_qpair_get(entry); + kref_get(&qdma_dev->ref); + mutex_unlock(&qdma_dev->lock); + + /* Allocate the per-fd context. */ + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + slash_qdma_qpair_put(entry); + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + return -ENOMEM; + } + + ctx->qdma_dev = qdma_dev; + ctx->entry = entry; + ctx->qid = req.qid; + + /* Create the anonymous inode file with read/write access. */ + file = anon_inode_getfile("slash_qdma_qpair", &slash_qdma_qpair_fops, + ctx, O_RDWR | (req.flags & O_CLOEXEC)); + if (IS_ERR(file)) { + err = PTR_ERR(file); + slash_qdma_qpair_put(entry); + kref_put(&qdma_dev->ref, slash_qdma_dev_release); + kfree(ctx); + return err; + } + + /* Enable seek and positional read/write for device-address control. */ + file->f_mode |= FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE; + + + /* Allocate a file descriptor number. */ + fd = get_unused_fd_flags(req.flags & O_CLOEXEC); + if (fd < 0) { + fput(file); /* triggers slash_qdma_qpair_release -> drops entry/dev refs, frees ctx */ + return fd; + } + + /* Copy the response back to userspace before installing the fd. */ + req.size = sizeof(req); + copy_size = min_t(size_t, user_size, sizeof(req)); + if (copy_to_user(uarg, &req, copy_size)) { + put_unused_fd(fd); + fput(file); /* triggers slash_qdma_qpair_release -> drops entry/dev refs, frees ctx */ + return -EFAULT; + } + if (user_size > sizeof(req)) { + if (clear_user((void __user *)((unsigned long)uarg + sizeof(req)), + user_size - sizeof(req))) { + put_unused_fd(fd); + fput(file); + return -EFAULT; + } + } + + /* + * Install the fd. After this point the fd is visible to userspace + * and the file's release callback will handle cleanup. + */ + fd_install(fd, file); + + return fd; +} + +/* ───────────────────────────────────────────────────────────────────── + * Queue pair teardown helper + * ───────────────────────────────────────────────────────────────────── */ + +/** + * slash_qdma_qpair_teardown() - Fully remove a queue pair and its HW queues. + * @qdma_dev: QDMA device. + * @qid: Queue pair ID. + * @entry: Queue pair entry to tear down. + * + * Must be called with @qdma_dev->lock held. + * + * Stops and removes all HW queues in the pair, invalidates all handles, + * erases the entry from the xarray, and drops the xarray's ref on the + * entry. The entry itself is freed only when all references (including + * any held by open anon_inode fds) have been released. + */ +/* Must be called with qdma_dev->lock held */ +static void slash_qdma_qpair_teardown(struct slash_qdma_dev *qdma_dev, u32 qid, + struct slash_qdma_qpair_entry *entry) +{ + unsigned int idx; + + if (!entry) + return; + + /* Remove any queues that still exist */ + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) { + enum queue_type_t qtype = idx; + + if (entry->dir_mask & slash_qdma_qtype_to_dir(qtype)) + slash_qdma_ioctl_qpair_rm_q(&qdma_dev->misc, qdma_dev, entry, qtype); + } + + /* Mark entry dead for any stale FDs */ + for (idx = 0; idx < SLASH_QDMA_QTYPE_COUNT; idx++) + entry->qhndl[idx] = QDMA_QUEUE_IDX_INVALID; + entry->dir_mask = 0; + + /* Drop from xarray and release ref */ + xa_erase(&qdma_dev->qpairs, qid); + slash_qdma_qpair_put(entry); +} diff --git a/driver/slash_qdma.h b/driver/slash_qdma.h new file mode 100644 index 00000000..1c873939 --- /dev/null +++ b/driver/slash_qdma.h @@ -0,0 +1,64 @@ +/** + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * This program is free software; you can redistribute it and/or modify it under the terms of the + * GNU General Public License as published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without + * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with this program; if + * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +/** + * @file slash_qdma.h + * + * QDMA subsystem init/exit interface for the SLASH kernel module. + * + * The QDMA subsystem manages the Xilinx QDMA IP on PF1, providing + * queue-pair-based DMA transfers between host memory and the FPGA + * fabric. It wraps the libqdma library from the Xilinx reference + * driver (submodules/qdma_drv). + * + * Initialization is split from PCI probe: slash_qdma_init() sets up + * the libqdma library and registers a separate PCI driver for PF1, + * while the per-device work happens in the PCI probe callback + * (internal to slash_qdma.c). + */ + +#ifndef SLASH_QDMA_H +#define SLASH_QDMA_H + +#include + +/** + * slash_qdma_init() - Initialize the QDMA subsystem. + * @num_threads: Number of worker threads for libqdma's internal + * processing (passed to libqdma_init()). + * @debugfs: Optional debugfs mount path for libqdma diagnostics. + * Pass NULL to disable debugfs integration. + * + * Initializes the libqdma library and registers a PCI driver that + * will probe QDMA-capable functions (PF1) on SLASH devices. + * + * Must be called before slash_pcie_init(), because PCI probe for PF2 + * may trigger activity that depends on the QDMA subsystem being ready. + * + * Return: 0 on success, negative errno on failure. + */ +int __init slash_qdma_init(unsigned int num_threads, char *debugfs); + +/** + * slash_qdma_exit() - Tear down the QDMA subsystem. + * + * Unregisters the QDMA PCI driver, closes all open QDMA devices, + * removes all queue pairs, and shuts down the libqdma library. + * + * Must be called after slash_pcie_exit() to ensure the control + * function is cleaned up before the QDMA function. + */ +void slash_qdma_exit(void); + +#endif /* SLASH_QDMA_H */ diff --git a/driver/tests/.gitignore b/driver/tests/.gitignore new file mode 100644 index 00000000..b5e865bb --- /dev/null +++ b/driver/tests/.gitignore @@ -0,0 +1,3 @@ +test_* +!test_*.c +!test_module.sh \ No newline at end of file diff --git a/driver/tests/Makefile b/driver/tests/Makefile new file mode 100644 index 00000000..731e01fd --- /dev/null +++ b/driver/tests/Makefile @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only OR MIT +# +# Userspace test suite for the SLASH kernel module. +# Uses the kselftest harness for TAP output. + +CC ?= gcc +CFLAGS ?= -Wall -Werror -O2 +CFLAGS += -I../libslash/include + +TESTS := test_slash_qdma + +all: $(TESTS) + +%: %.c kselftest.h kselftest_harness.h ../libslash/include/slash/uapi/slash_interface.h + $(CC) $(CFLAGS) -o $@ $< + +run: $(TESTS) + @fail=0; \ + for t in $(TESTS); do \ + echo "# Running $$t"; \ + ./$$t || fail=1; \ + echo; \ + done; \ + exit $$fail + +clean: + rm -f $(TESTS) + +.PHONY: all run clean diff --git a/driver/tests/kselftest.h b/driver/tests/kselftest.h new file mode 100644 index 00000000..898d7b2f --- /dev/null +++ b/driver/tests/kselftest.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * kselftest.h: low-level kselftest framework to include from + * selftest programs. When possible, please use + * kselftest_harness.h instead. + * + * Copyright (c) 2014 Shuah Khan + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Using this API consists of first counting how many tests your code + * has to run, and then starting up the reporting: + * + * ksft_print_header(); + * ksft_set_plan(total_number_of_tests); + * + * For each test, report any progress, debugging, etc with: + * + * ksft_print_msg(fmt, ...); + * + * and finally report the pass/fail/skip/xfail state of the test with one of: + * + * ksft_test_result(condition, fmt, ...); + * ksft_test_result_pass(fmt, ...); + * ksft_test_result_fail(fmt, ...); + * ksft_test_result_skip(fmt, ...); + * ksft_test_result_xfail(fmt, ...); + * ksft_test_result_error(fmt, ...); + * + * When all tests are finished, clean up and exit the program with one of: + * + * ksft_exit(condition); + * ksft_exit_pass(); + * ksft_exit_fail(); + * + * If the program wants to report details on why the entire program has + * failed, it can instead exit with a message (this is usually done when + * the program is aborting before finishing all tests): + * + * ksft_exit_fail_msg(fmt, ...); + * + */ +#ifndef __KSELFTEST_H +#define __KSELFTEST_H + +#include +#include +#include +#include +#include + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + +/* + * gcc cpuid.h provides __cpuid_count() since v4.4. + * Clang/LLVM cpuid.h provides __cpuid_count() since v3.4.0. + * + * Provide local define for tests needing __cpuid_count() because + * selftests need to work in older environments that do not yet + * have __cpuid_count(). + */ +#ifndef __cpuid_count +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ __volatile__ ("cpuid\n\t" \ + : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) +#endif + +/* define kselftest exit codes */ +#define KSFT_PASS 0 +#define KSFT_FAIL 1 +#define KSFT_XFAIL 2 +#define KSFT_XPASS 3 +#define KSFT_SKIP 4 + +/* counters */ +struct ksft_count { + unsigned int ksft_pass; + unsigned int ksft_fail; + unsigned int ksft_xfail; + unsigned int ksft_xpass; + unsigned int ksft_xskip; + unsigned int ksft_error; +}; + +static struct ksft_count ksft_cnt; +static unsigned int ksft_plan; + +static inline unsigned int ksft_test_num(void) +{ + return ksft_cnt.ksft_pass + ksft_cnt.ksft_fail + + ksft_cnt.ksft_xfail + ksft_cnt.ksft_xpass + + ksft_cnt.ksft_xskip + ksft_cnt.ksft_error; +} + +static inline void ksft_inc_pass_cnt(void) { ksft_cnt.ksft_pass++; } +static inline void ksft_inc_fail_cnt(void) { ksft_cnt.ksft_fail++; } +static inline void ksft_inc_xfail_cnt(void) { ksft_cnt.ksft_xfail++; } +static inline void ksft_inc_xpass_cnt(void) { ksft_cnt.ksft_xpass++; } +static inline void ksft_inc_xskip_cnt(void) { ksft_cnt.ksft_xskip++; } +static inline void ksft_inc_error_cnt(void) { ksft_cnt.ksft_error++; } + +static inline int ksft_get_pass_cnt(void) { return ksft_cnt.ksft_pass; } +static inline int ksft_get_fail_cnt(void) { return ksft_cnt.ksft_fail; } +static inline int ksft_get_xfail_cnt(void) { return ksft_cnt.ksft_xfail; } +static inline int ksft_get_xpass_cnt(void) { return ksft_cnt.ksft_xpass; } +static inline int ksft_get_xskip_cnt(void) { return ksft_cnt.ksft_xskip; } +static inline int ksft_get_error_cnt(void) { return ksft_cnt.ksft_error; } + +static inline void ksft_print_header(void) +{ + if (!(getenv("KSFT_TAP_LEVEL"))) + printf("TAP version 13\n"); +} + +static inline void ksft_set_plan(unsigned int plan) +{ + ksft_plan = plan; + printf("1..%d\n", ksft_plan); +} + +static inline void ksft_print_cnts(void) +{ + if (ksft_plan != ksft_test_num()) + printf("# Planned tests != run tests (%u != %u)\n", + ksft_plan, ksft_test_num()); + printf("# Totals: pass:%d fail:%d xfail:%d xpass:%d skip:%d error:%d\n", + ksft_cnt.ksft_pass, ksft_cnt.ksft_fail, + ksft_cnt.ksft_xfail, ksft_cnt.ksft_xpass, + ksft_cnt.ksft_xskip, ksft_cnt.ksft_error); +} + +static inline void ksft_print_msg(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + va_start(args, msg); + printf("# "); + errno = saved_errno; + vprintf(msg, args); + va_end(args); +} + +static inline void ksft_test_result_pass(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + ksft_cnt.ksft_pass++; + + va_start(args, msg); + printf("ok %d ", ksft_test_num()); + errno = saved_errno; + vprintf(msg, args); + va_end(args); +} + +static inline void ksft_test_result_fail(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + ksft_cnt.ksft_fail++; + + va_start(args, msg); + printf("not ok %d ", ksft_test_num()); + errno = saved_errno; + vprintf(msg, args); + va_end(args); +} + +/** + * ksft_test_result() - Report test success based on truth of condition + * + * @condition: if true, report test success, otherwise failure. + */ +#define ksft_test_result(condition, fmt, ...) do { \ + if (!!(condition)) \ + ksft_test_result_pass(fmt, ##__VA_ARGS__);\ + else \ + ksft_test_result_fail(fmt, ##__VA_ARGS__);\ + } while (0) + +static inline void ksft_test_result_xfail(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + ksft_cnt.ksft_xfail++; + + va_start(args, msg); + printf("ok %d # XFAIL ", ksft_test_num()); + errno = saved_errno; + vprintf(msg, args); + va_end(args); +} + +static inline void ksft_test_result_skip(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + ksft_cnt.ksft_xskip++; + + va_start(args, msg); + printf("ok %d # SKIP ", ksft_test_num()); + errno = saved_errno; + vprintf(msg, args); + va_end(args); +} + +/* TODO: how does "error" differ from "fail" or "skip"? */ +static inline void ksft_test_result_error(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + ksft_cnt.ksft_error++; + + va_start(args, msg); + printf("not ok %d # error ", ksft_test_num()); + errno = saved_errno; + vprintf(msg, args); + va_end(args); +} + +static inline int ksft_exit_pass(void) +{ + ksft_print_cnts(); + exit(KSFT_PASS); +} + +static inline int ksft_exit_fail(void) +{ + ksft_print_cnts(); + exit(KSFT_FAIL); +} + +/** + * ksft_exit() - Exit selftest based on truth of condition + * + * @condition: if true, exit self test with success, otherwise fail. + */ +#define ksft_exit(condition) do { \ + if (!!(condition)) \ + ksft_exit_pass(); \ + else \ + ksft_exit_fail(); \ + } while (0) + +static inline int ksft_exit_fail_msg(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + va_start(args, msg); + printf("Bail out! "); + errno = saved_errno; + vprintf(msg, args); + va_end(args); + + ksft_print_cnts(); + exit(KSFT_FAIL); +} + +static inline int ksft_exit_xfail(void) +{ + ksft_print_cnts(); + exit(KSFT_XFAIL); +} + +static inline int ksft_exit_xpass(void) +{ + ksft_print_cnts(); + exit(KSFT_XPASS); +} + +static inline int ksft_exit_skip(const char *msg, ...) +{ + int saved_errno = errno; + va_list args; + + va_start(args, msg); + + /* + * FIXME: several tests misuse ksft_exit_skip so produce + * something sensible if some tests have already been run + * or a plan has been printed. Those tests should use + * ksft_test_result_skip or ksft_exit_fail_msg instead. + */ + if (ksft_plan || ksft_test_num()) { + ksft_cnt.ksft_xskip++; + printf("ok %d # SKIP ", 1 + ksft_test_num()); + } else { + printf("1..0 # SKIP "); + } + if (msg) { + errno = saved_errno; + vprintf(msg, args); + va_end(args); + } + if (ksft_test_num()) + ksft_print_cnts(); + exit(KSFT_SKIP); +} + +#endif /* __KSELFTEST_H */ diff --git a/driver/tests/kselftest_harness.h b/driver/tests/kselftest_harness.h new file mode 100644 index 00000000..870f3727 --- /dev/null +++ b/driver/tests/kselftest_harness.h @@ -0,0 +1,1071 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * + * kselftest_harness.h: simple C unit test helper. + * + * See documentation in Documentation/dev-tools/kselftest.rst + * + * API inspired by code.google.com/p/googletest + */ + +/** + * DOC: example + * + * .. code-block:: c + * + * #include "../kselftest_harness.h" + * + * TEST(standalone_test) { + * do_some_stuff; + * EXPECT_GT(10, stuff) { + * stuff_state_t state; + * enumerate_stuff_state(&state); + * TH_LOG("expectation failed with state: %s", state.msg); + * } + * more_stuff; + * ASSERT_NE(some_stuff, NULL) TH_LOG("how did it happen?!"); + * last_stuff; + * EXPECT_EQ(0, last_stuff); + * } + * + * FIXTURE(my_fixture) { + * mytype_t *data; + * int awesomeness_level; + * }; + * FIXTURE_SETUP(my_fixture) { + * self->data = mytype_new(); + * ASSERT_NE(NULL, self->data); + * } + * FIXTURE_TEARDOWN(my_fixture) { + * mytype_free(self->data); + * } + * TEST_F(my_fixture, data_is_good) { + * EXPECT_EQ(1, is_my_data_good(self->data)); + * } + * + * TEST_HARNESS_MAIN + */ + +#ifndef __KSELFTEST_HARNESS_H +#define __KSELFTEST_HARNESS_H + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kselftest.h" + +#define TEST_TIMEOUT_DEFAULT 30 + +/* Utilities exposed to the test definitions */ +#ifndef TH_LOG_STREAM +# define TH_LOG_STREAM stderr +#endif + +#ifndef TH_LOG_ENABLED +# define TH_LOG_ENABLED 1 +#endif + +/** + * TH_LOG() + * + * @fmt: format string + * @...: optional arguments + * + * .. code-block:: c + * + * TH_LOG(format, ...) + * + * Optional debug logging function available for use in tests. + * Logging may be enabled or disabled by defining TH_LOG_ENABLED. + * E.g., #define TH_LOG_ENABLED 1 + * + * If no definition is provided, logging is enabled by default. + * + * If there is no way to print an error message for the process running the + * test (e.g. not allowed to write to stderr), it is still possible to get the + * ASSERT_* number for which the test failed. This behavior can be enabled by + * writing `_metadata->no_print = true;` before the check sequence that is + * unable to print. When an error occur, instead of printing an error message + * and calling `abort(3)`, the test process call `_exit(2)` with the assert + * number as argument, which is then printed by the parent process. + */ +#define TH_LOG(fmt, ...) do { \ + if (TH_LOG_ENABLED) \ + __TH_LOG(fmt, ##__VA_ARGS__); \ +} while (0) + +/* Unconditional logger for internal use. */ +#define __TH_LOG(fmt, ...) \ + fprintf(TH_LOG_STREAM, "# %s:%d:%s:" fmt "\n", \ + __FILE__, __LINE__, _metadata->name, ##__VA_ARGS__) + +/** + * SKIP() + * + * @statement: statement to run after reporting SKIP + * @fmt: format string + * @...: optional arguments + * + * .. code-block:: c + * + * SKIP(statement, fmt, ...); + * + * This forces a "pass" after reporting why something is being skipped + * and runs "statement", which is usually "return" or "goto skip". + */ +#define SKIP(statement, fmt, ...) do { \ + snprintf(_metadata->results->reason, \ + sizeof(_metadata->results->reason), fmt, ##__VA_ARGS__); \ + if (TH_LOG_ENABLED) { \ + fprintf(TH_LOG_STREAM, "# SKIP %s\n", \ + _metadata->results->reason); \ + } \ + _metadata->passed = 1; \ + _metadata->skip = 1; \ + _metadata->trigger = 0; \ + statement; \ +} while (0) + +/** + * TEST() - Defines the test function and creates the registration + * stub + * + * @test_name: test name + * + * .. code-block:: c + * + * TEST(name) { implementation } + * + * Defines a test by name. + * Names must be unique and tests must not be run in parallel. The + * implementation containing block is a function and scoping should be treated + * as such. Returning early may be performed with a bare "return;" statement. + * + * EXPECT_* and ASSERT_* are valid in a TEST() { } context. + */ +#define TEST(test_name) __TEST_IMPL(test_name, -1) + +/** + * TEST_SIGNAL() + * + * @test_name: test name + * @signal: signal number + * + * .. code-block:: c + * + * TEST_SIGNAL(name, signal) { implementation } + * + * Defines a test by name and the expected term signal. + * Names must be unique and tests must not be run in parallel. The + * implementation containing block is a function and scoping should be treated + * as such. Returning early may be performed with a bare "return;" statement. + * + * EXPECT_* and ASSERT_* are valid in a TEST() { } context. + */ +#define TEST_SIGNAL(test_name, signal) __TEST_IMPL(test_name, signal) + +#define __TEST_IMPL(test_name, _signal) \ + static void test_name(struct __test_metadata *_metadata); \ + static inline void wrapper_##test_name( \ + struct __test_metadata *_metadata, \ + struct __fixture_variant_metadata *variant) \ + { \ + test_name(_metadata); \ + } \ + static struct __test_metadata _##test_name##_object = \ + { .name = #test_name, \ + .fn = &wrapper_##test_name, \ + .fixture = &_fixture_global, \ + .termsig = _signal, \ + .timeout = TEST_TIMEOUT_DEFAULT, }; \ + static void __attribute__((constructor)) _register_##test_name(void) \ + { \ + __register_test(&_##test_name##_object); \ + } \ + static void test_name( \ + struct __test_metadata __attribute__((unused)) *_metadata) + +/** + * FIXTURE_DATA() - Wraps the struct name so we have one less + * argument to pass around + * + * @datatype_name: datatype name + * + * .. code-block:: c + * + * FIXTURE_DATA(datatype_name) + * + * Almost always, you want just FIXTURE() instead (see below). + * This call may be used when the type of the fixture data + * is needed. In general, this should not be needed unless + * the *self* is being passed to a helper directly. + */ +#define FIXTURE_DATA(datatype_name) struct _test_data_##datatype_name + +/** + * FIXTURE() - Called once per fixture to setup the data and + * register + * + * @fixture_name: fixture name + * + * .. code-block:: c + * + * FIXTURE(fixture_name) { + * type property1; + * ... + * }; + * + * Defines the data provided to TEST_F()-defined tests as *self*. It should be + * populated and cleaned up using FIXTURE_SETUP() and FIXTURE_TEARDOWN(). + */ +#define FIXTURE(fixture_name) \ + FIXTURE_VARIANT(fixture_name); \ + static struct __fixture_metadata _##fixture_name##_fixture_object = \ + { .name = #fixture_name, }; \ + static void __attribute__((constructor)) \ + _register_##fixture_name##_data(void) \ + { \ + __register_fixture(&_##fixture_name##_fixture_object); \ + } \ + FIXTURE_DATA(fixture_name) + +/** + * FIXTURE_SETUP() - Prepares the setup function for the fixture. + * *_metadata* is included so that EXPECT_*, ASSERT_* etc. work correctly. + * + * @fixture_name: fixture name + * + * .. code-block:: c + * + * FIXTURE_SETUP(fixture_name) { implementation } + * + * Populates the required "setup" function for a fixture. An instance of the + * datatype defined with FIXTURE_DATA() will be exposed as *self* for the + * implementation. + * + * ASSERT_* are valid for use in this context and will prempt the execution + * of any dependent fixture tests. + * + * A bare "return;" statement may be used to return early. + */ +#define FIXTURE_SETUP(fixture_name) \ + void fixture_name##_setup( \ + struct __test_metadata __attribute__((unused)) *_metadata, \ + FIXTURE_DATA(fixture_name) __attribute__((unused)) *self, \ + const FIXTURE_VARIANT(fixture_name) \ + __attribute__((unused)) *variant) + +/** + * FIXTURE_TEARDOWN() + * *_metadata* is included so that EXPECT_*, ASSERT_* etc. work correctly. + * + * @fixture_name: fixture name + * + * .. code-block:: c + * + * FIXTURE_TEARDOWN(fixture_name) { implementation } + * + * Populates the required "teardown" function for a fixture. An instance of the + * datatype defined with FIXTURE_DATA() will be exposed as *self* for the + * implementation to clean up. + * + * A bare "return;" statement may be used to return early. + */ +#define FIXTURE_TEARDOWN(fixture_name) \ + void fixture_name##_teardown( \ + struct __test_metadata __attribute__((unused)) *_metadata, \ + FIXTURE_DATA(fixture_name) __attribute__((unused)) *self) + +/** + * FIXTURE_VARIANT() - Optionally called once per fixture + * to declare fixture variant + * + * @fixture_name: fixture name + * + * .. code-block:: c + * + * FIXTURE_VARIANT(fixture_name) { + * type property1; + * ... + * }; + * + * Defines type of constant parameters provided to FIXTURE_SETUP() and TEST_F() + * as *variant*. Variants allow the same tests to be run with different + * arguments. + */ +#define FIXTURE_VARIANT(fixture_name) struct _fixture_variant_##fixture_name + +/** + * FIXTURE_VARIANT_ADD() - Called once per fixture + * variant to setup and register the data + * + * @fixture_name: fixture name + * @variant_name: name of the parameter set + * + * .. code-block:: c + * + * FIXTURE_VARIANT_ADD(fixture_name, variant_name) { + * .property1 = val1, + * ... + * }; + * + * Defines a variant of the test fixture, provided to FIXTURE_SETUP() and + * TEST_F() as *variant*. Tests of each fixture will be run once for each + * variant. + */ +#define FIXTURE_VARIANT_ADD(fixture_name, variant_name) \ + extern FIXTURE_VARIANT(fixture_name) \ + _##fixture_name##_##variant_name##_variant; \ + static struct __fixture_variant_metadata \ + _##fixture_name##_##variant_name##_object = \ + { .name = #variant_name, \ + .data = &_##fixture_name##_##variant_name##_variant}; \ + static void __attribute__((constructor)) \ + _register_##fixture_name##_##variant_name(void) \ + { \ + __register_fixture_variant(&_##fixture_name##_fixture_object, \ + &_##fixture_name##_##variant_name##_object); \ + } \ + FIXTURE_VARIANT(fixture_name) \ + _##fixture_name##_##variant_name##_variant = + +/** + * TEST_F() - Emits test registration and helpers for + * fixture-based test cases + * + * @fixture_name: fixture name + * @test_name: test name + * + * .. code-block:: c + * + * TEST_F(fixture, name) { implementation } + * + * Defines a test that depends on a fixture (e.g., is part of a test case). + * Very similar to TEST() except that *self* is the setup instance of fixture's + * datatype exposed for use by the implementation. + * + * Warning: use of ASSERT_* here will skip TEARDOWN. + */ +/* TODO(wad) register fixtures on dedicated test lists. */ +#define TEST_F(fixture_name, test_name) \ + __TEST_F_IMPL(fixture_name, test_name, -1, TEST_TIMEOUT_DEFAULT) + +#define TEST_F_SIGNAL(fixture_name, test_name, signal) \ + __TEST_F_IMPL(fixture_name, test_name, signal, TEST_TIMEOUT_DEFAULT) + +#define TEST_F_TIMEOUT(fixture_name, test_name, timeout) \ + __TEST_F_IMPL(fixture_name, test_name, -1, timeout) + +#define __TEST_F_IMPL(fixture_name, test_name, signal, tmout) \ + static void fixture_name##_##test_name( \ + struct __test_metadata *_metadata, \ + FIXTURE_DATA(fixture_name) *self, \ + const FIXTURE_VARIANT(fixture_name) *variant); \ + static inline void wrapper_##fixture_name##_##test_name( \ + struct __test_metadata *_metadata, \ + struct __fixture_variant_metadata *variant) \ + { \ + /* fixture data is alloced, setup, and torn down per call. */ \ + FIXTURE_DATA(fixture_name) self; \ + memset(&self, 0, sizeof(FIXTURE_DATA(fixture_name))); \ + fixture_name##_setup(_metadata, &self, variant->data); \ + /* Let setup failure terminate early. */ \ + if (!_metadata->passed || _metadata->skip) \ + return; \ + fixture_name##_##test_name(_metadata, &self, variant->data); \ + fixture_name##_teardown(_metadata, &self); \ + } \ + static struct __test_metadata \ + _##fixture_name##_##test_name##_object = { \ + .name = #test_name, \ + .fn = &wrapper_##fixture_name##_##test_name, \ + .fixture = &_##fixture_name##_fixture_object, \ + .termsig = signal, \ + .timeout = tmout, \ + }; \ + static void __attribute__((constructor)) \ + _register_##fixture_name##_##test_name(void) \ + { \ + __register_test(&_##fixture_name##_##test_name##_object); \ + } \ + static void fixture_name##_##test_name( \ + struct __test_metadata __attribute__((unused)) *_metadata, \ + FIXTURE_DATA(fixture_name) __attribute__((unused)) *self, \ + const FIXTURE_VARIANT(fixture_name) \ + __attribute__((unused)) *variant) + +/** + * TEST_HARNESS_MAIN - Simple wrapper to run the test harness + * + * .. code-block:: c + * + * TEST_HARNESS_MAIN + * + * Use once to append a main() to the test file. + */ +#define TEST_HARNESS_MAIN \ + static void __attribute__((constructor)) \ + __constructor_order_last(void) \ + { \ + if (!__constructor_order) \ + __constructor_order = _CONSTRUCTOR_ORDER_BACKWARD; \ + } \ + int main(int argc, char **argv) { \ + return test_harness_run(argc, argv); \ + } + +/** + * DOC: operators + * + * Operators for use in TEST() and TEST_F(). + * ASSERT_* calls will stop test execution immediately. + * EXPECT_* calls will emit a failure warning, note it, and continue. + */ + +/** + * ASSERT_EQ() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_EQ(expected, measured): expected == measured + */ +#define ASSERT_EQ(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, ==, 1) + +/** + * ASSERT_NE() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_NE(expected, measured): expected != measured + */ +#define ASSERT_NE(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, !=, 1) + +/** + * ASSERT_LT() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_LT(expected, measured): expected < measured + */ +#define ASSERT_LT(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, <, 1) + +/** + * ASSERT_LE() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_LE(expected, measured): expected <= measured + */ +#define ASSERT_LE(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, <=, 1) + +/** + * ASSERT_GT() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_GT(expected, measured): expected > measured + */ +#define ASSERT_GT(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, >, 1) + +/** + * ASSERT_GE() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_GE(expected, measured): expected >= measured + */ +#define ASSERT_GE(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, >=, 1) + +/** + * ASSERT_NULL() + * + * @seen: measured value + * + * ASSERT_NULL(measured): NULL == measured + */ +#define ASSERT_NULL(seen) \ + __EXPECT(NULL, "NULL", seen, #seen, ==, 1) + +/** + * ASSERT_TRUE() + * + * @seen: measured value + * + * ASSERT_TRUE(measured): measured != 0 + */ +#define ASSERT_TRUE(seen) \ + __EXPECT(0, "0", seen, #seen, !=, 1) + +/** + * ASSERT_FALSE() + * + * @seen: measured value + * + * ASSERT_FALSE(measured): measured == 0 + */ +#define ASSERT_FALSE(seen) \ + __EXPECT(0, "0", seen, #seen, ==, 1) + +/** + * ASSERT_STREQ() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_STREQ(expected, measured): !strcmp(expected, measured) + */ +#define ASSERT_STREQ(expected, seen) \ + __EXPECT_STR(expected, seen, ==, 1) + +/** + * ASSERT_STRNE() + * + * @expected: expected value + * @seen: measured value + * + * ASSERT_STRNE(expected, measured): strcmp(expected, measured) + */ +#define ASSERT_STRNE(expected, seen) \ + __EXPECT_STR(expected, seen, !=, 1) + +/** + * EXPECT_EQ() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_EQ(expected, measured): expected == measured + */ +#define EXPECT_EQ(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, ==, 0) + +/** + * EXPECT_NE() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_NE(expected, measured): expected != measured + */ +#define EXPECT_NE(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, !=, 0) + +/** + * EXPECT_LT() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_LT(expected, measured): expected < measured + */ +#define EXPECT_LT(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, <, 0) + +/** + * EXPECT_LE() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_LE(expected, measured): expected <= measured + */ +#define EXPECT_LE(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, <=, 0) + +/** + * EXPECT_GT() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_GT(expected, measured): expected > measured + */ +#define EXPECT_GT(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, >, 0) + +/** + * EXPECT_GE() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_GE(expected, measured): expected >= measured + */ +#define EXPECT_GE(expected, seen) \ + __EXPECT(expected, #expected, seen, #seen, >=, 0) + +/** + * EXPECT_NULL() + * + * @seen: measured value + * + * EXPECT_NULL(measured): NULL == measured + */ +#define EXPECT_NULL(seen) \ + __EXPECT(NULL, "NULL", seen, #seen, ==, 0) + +/** + * EXPECT_TRUE() + * + * @seen: measured value + * + * EXPECT_TRUE(measured): 0 != measured + */ +#define EXPECT_TRUE(seen) \ + __EXPECT(0, "0", seen, #seen, !=, 0) + +/** + * EXPECT_FALSE() + * + * @seen: measured value + * + * EXPECT_FALSE(measured): 0 == measured + */ +#define EXPECT_FALSE(seen) \ + __EXPECT(0, "0", seen, #seen, ==, 0) + +/** + * EXPECT_STREQ() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_STREQ(expected, measured): !strcmp(expected, measured) + */ +#define EXPECT_STREQ(expected, seen) \ + __EXPECT_STR(expected, seen, ==, 0) + +/** + * EXPECT_STRNE() + * + * @expected: expected value + * @seen: measured value + * + * EXPECT_STRNE(expected, measured): strcmp(expected, measured) + */ +#define EXPECT_STRNE(expected, seen) \ + __EXPECT_STR(expected, seen, !=, 0) + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) +#endif + +/* Support an optional handler after and ASSERT_* or EXPECT_*. The approach is + * not thread-safe, but it should be fine in most sane test scenarios. + * + * Using __bail(), which optionally abort()s, is the easiest way to early + * return while still providing an optional block to the API consumer. + */ +#define OPTIONAL_HANDLER(_assert) \ + for (; _metadata->trigger; _metadata->trigger = \ + __bail(_assert, _metadata->no_print, _metadata->step)) + +#define __INC_STEP(_metadata) \ + /* Keep "step" below 255 (which is used for "SKIP" reporting). */ \ + if (_metadata->passed && _metadata->step < 253) \ + _metadata->step++; + +#define is_signed_type(var) (!!(((__typeof__(var))(-1)) < (__typeof__(var))1)) + +#define __EXPECT(_expected, _expected_str, _seen, _seen_str, _t, _assert) do { \ + /* Avoid multiple evaluation of the cases */ \ + __typeof__(_expected) __exp = (_expected); \ + __typeof__(_seen) __seen = (_seen); \ + if (_assert) __INC_STEP(_metadata); \ + if (!(__exp _t __seen)) { \ + /* Report with actual signedness to avoid weird output. */ \ + switch (is_signed_type(__exp) * 2 + is_signed_type(__seen)) { \ + case 0: { \ + uintmax_t __exp_print = (uintmax_t)__exp; \ + uintmax_t __seen_print = (uintmax_t)__seen; \ + __TH_LOG("Expected %s (%ju) %s %s (%ju)", \ + _expected_str, __exp_print, #_t, \ + _seen_str, __seen_print); \ + break; \ + } \ + case 1: { \ + uintmax_t __exp_print = (uintmax_t)__exp; \ + intmax_t __seen_print = (intmax_t)__seen; \ + __TH_LOG("Expected %s (%ju) %s %s (%jd)", \ + _expected_str, __exp_print, #_t, \ + _seen_str, __seen_print); \ + break; \ + } \ + case 2: { \ + intmax_t __exp_print = (intmax_t)__exp; \ + uintmax_t __seen_print = (uintmax_t)__seen; \ + __TH_LOG("Expected %s (%jd) %s %s (%ju)", \ + _expected_str, __exp_print, #_t, \ + _seen_str, __seen_print); \ + break; \ + } \ + case 3: { \ + intmax_t __exp_print = (intmax_t)__exp; \ + intmax_t __seen_print = (intmax_t)__seen; \ + __TH_LOG("Expected %s (%jd) %s %s (%jd)", \ + _expected_str, __exp_print, #_t, \ + _seen_str, __seen_print); \ + break; \ + } \ + } \ + _metadata->passed = 0; \ + /* Ensure the optional handler is triggered */ \ + _metadata->trigger = 1; \ + } \ +} while (0); OPTIONAL_HANDLER(_assert) + +#define __EXPECT_STR(_expected, _seen, _t, _assert) do { \ + const char *__exp = (_expected); \ + const char *__seen = (_seen); \ + if (_assert) __INC_STEP(_metadata); \ + if (!(strcmp(__exp, __seen) _t 0)) { \ + __TH_LOG("Expected '%s' %s '%s'.", __exp, #_t, __seen); \ + _metadata->passed = 0; \ + _metadata->trigger = 1; \ + } \ +} while (0); OPTIONAL_HANDLER(_assert) + +/* List helpers */ +#define __LIST_APPEND(head, item) \ +{ \ + /* Circular linked list where only prev is circular. */ \ + if (head == NULL) { \ + head = item; \ + item->next = NULL; \ + item->prev = item; \ + return; \ + } \ + if (__constructor_order == _CONSTRUCTOR_ORDER_FORWARD) { \ + item->next = NULL; \ + item->prev = head->prev; \ + item->prev->next = item; \ + head->prev = item; \ + } else { \ + item->next = head; \ + item->next->prev = item; \ + item->prev = item; \ + head = item; \ + } \ +} + +struct __test_results { + char reason[1024]; /* Reason for test result */ +}; + +struct __test_metadata; +struct __fixture_variant_metadata; + +/* Contains all the information about a fixture. */ +struct __fixture_metadata { + const char *name; + struct __test_metadata *tests; + struct __fixture_variant_metadata *variant; + struct __fixture_metadata *prev, *next; +} _fixture_global __attribute__((unused)) = { + .name = "global", + .prev = &_fixture_global, +}; + +static struct __fixture_metadata *__fixture_list = &_fixture_global; +static int __constructor_order; + +#define _CONSTRUCTOR_ORDER_FORWARD 1 +#define _CONSTRUCTOR_ORDER_BACKWARD -1 + +static inline void __register_fixture(struct __fixture_metadata *f) +{ + __LIST_APPEND(__fixture_list, f); +} + +struct __fixture_variant_metadata { + const char *name; + const void *data; + struct __fixture_variant_metadata *prev, *next; +}; + +static inline void +__register_fixture_variant(struct __fixture_metadata *f, + struct __fixture_variant_metadata *variant) +{ + __LIST_APPEND(f->variant, variant); +} + +/* Contains all the information for test execution and status checking. */ +struct __test_metadata { + const char *name; + void (*fn)(struct __test_metadata *, + struct __fixture_variant_metadata *); + pid_t pid; /* pid of test when being run */ + struct __fixture_metadata *fixture; + int termsig; + int passed; + int skip; /* did SKIP get used? */ + int trigger; /* extra handler after the evaluation */ + int timeout; /* seconds to wait for test timeout */ + bool timed_out; /* did this test timeout instead of exiting? */ + __u8 step; + bool no_print; /* manual trigger when TH_LOG_STREAM is not available */ + struct __test_results *results; + struct __test_metadata *prev, *next; +}; + +/* + * Since constructors are called in reverse order, reverse the test + * list so tests are run in source declaration order. + * https://gcc.gnu.org/onlinedocs/gccint/Initialization.html + * However, it seems not all toolchains do this correctly, so use + * __constructor_order to detect which direction is called first + * and adjust list building logic to get things running in the right + * direction. + */ +static inline void __register_test(struct __test_metadata *t) +{ + __LIST_APPEND(t->fixture->tests, t); +} + +static inline int __bail(int for_realz, bool no_print, __u8 step) +{ + if (for_realz) { + if (no_print) + _exit(step); + abort(); + } + return 0; +} + +struct __test_metadata *__active_test; +static void __timeout_handler(int sig, siginfo_t *info, void *ucontext) +{ + struct __test_metadata *t = __active_test; + + /* Sanity check handler execution environment. */ + if (!t) { + fprintf(TH_LOG_STREAM, + "# no active test in SIGALRM handler!?\n"); + abort(); + } + if (sig != SIGALRM || sig != info->si_signo) { + fprintf(TH_LOG_STREAM, + "# %s: SIGALRM handler caught signal %d!?\n", + t->name, sig != SIGALRM ? sig : info->si_signo); + abort(); + } + + t->timed_out = true; + // signal process group + kill(-(t->pid), SIGKILL); +} + +void __wait_for_test(struct __test_metadata *t) +{ + struct sigaction action = { + .sa_sigaction = __timeout_handler, + .sa_flags = SA_SIGINFO, + }; + struct sigaction saved_action; + int status; + + if (sigaction(SIGALRM, &action, &saved_action)) { + t->passed = 0; + fprintf(TH_LOG_STREAM, + "# %s: unable to install SIGALRM handler\n", + t->name); + return; + } + __active_test = t; + t->timed_out = false; + alarm(t->timeout); + waitpid(t->pid, &status, 0); + alarm(0); + if (sigaction(SIGALRM, &saved_action, NULL)) { + t->passed = 0; + fprintf(TH_LOG_STREAM, + "# %s: unable to uninstall SIGALRM handler\n", + t->name); + return; + } + __active_test = NULL; + + if (t->timed_out) { + t->passed = 0; + fprintf(TH_LOG_STREAM, + "# %s: Test terminated by timeout\n", t->name); + } else if (WIFEXITED(status)) { + if (WEXITSTATUS(status) == 255) { + /* SKIP */ + t->passed = 1; + t->skip = 1; + } else if (t->termsig != -1) { + t->passed = 0; + fprintf(TH_LOG_STREAM, + "# %s: Test exited normally instead of by signal (code: %d)\n", + t->name, + WEXITSTATUS(status)); + } else { + switch (WEXITSTATUS(status)) { + /* Success */ + case 0: + t->passed = 1; + break; + /* Other failure, assume step report. */ + default: + t->passed = 0; + fprintf(TH_LOG_STREAM, + "# %s: Test failed at step #%d\n", + t->name, + WEXITSTATUS(status)); + } + } + } else if (WIFSIGNALED(status)) { + t->passed = 0; + if (WTERMSIG(status) == SIGABRT) { + fprintf(TH_LOG_STREAM, + "# %s: Test terminated by assertion\n", + t->name); + } else if (WTERMSIG(status) == t->termsig) { + t->passed = 1; + } else { + fprintf(TH_LOG_STREAM, + "# %s: Test terminated unexpectedly by signal %d\n", + t->name, + WTERMSIG(status)); + } + } else { + fprintf(TH_LOG_STREAM, + "# %s: Test ended in some other way [%u]\n", + t->name, + status); + } +} + +void __run_test(struct __fixture_metadata *f, + struct __fixture_variant_metadata *variant, + struct __test_metadata *t) +{ + /* reset test struct */ + t->passed = 1; + t->skip = 0; + t->trigger = 0; + t->step = 1; + t->no_print = 0; + memset(t->results->reason, 0, sizeof(t->results->reason)); + + ksft_print_msg(" RUN %s%s%s.%s ...\n", + f->name, variant->name[0] ? "." : "", variant->name, t->name); + + /* Make sure output buffers are flushed before fork */ + fflush(stdout); + fflush(stderr); + + t->pid = fork(); + if (t->pid < 0) { + ksft_print_msg("ERROR SPAWNING TEST CHILD\n"); + t->passed = 0; + } else if (t->pid == 0) { + setpgrp(); + t->fn(t, variant); + if (t->skip) + _exit(255); + /* Pass is exit 0 */ + if (t->passed) + _exit(0); + /* Something else happened, report the step. */ + _exit(t->step); + } else { + __wait_for_test(t); + } + ksft_print_msg(" %4s %s%s%s.%s\n", t->passed ? "OK" : "FAIL", + f->name, variant->name[0] ? "." : "", variant->name, t->name); + + if (t->skip) + ksft_test_result_skip("%s\n", t->results->reason[0] ? + t->results->reason : "unknown"); + else + ksft_test_result(t->passed, "%s%s%s.%s\n", + f->name, variant->name[0] ? "." : "", variant->name, t->name); +} + +static int test_harness_run(int __attribute__((unused)) argc, + char __attribute__((unused)) **argv) +{ + struct __fixture_variant_metadata no_variant = { .name = "", }; + struct __fixture_variant_metadata *v; + struct __fixture_metadata *f; + struct __test_results *results; + struct __test_metadata *t; + int ret = 0; + unsigned int case_count = 0, test_count = 0; + unsigned int count = 0; + unsigned int pass_count = 0; + + for (f = __fixture_list; f; f = f->next) { + for (v = f->variant ?: &no_variant; v; v = v->next) { + case_count++; + for (t = f->tests; t; t = t->next) + test_count++; + } + } + + results = mmap(NULL, sizeof(*results), PROT_READ | PROT_WRITE, + MAP_SHARED | MAP_ANONYMOUS, -1, 0); + + ksft_print_header(); + ksft_set_plan(test_count); + ksft_print_msg("Starting %u tests from %u test cases.\n", + test_count, case_count); + for (f = __fixture_list; f; f = f->next) { + for (v = f->variant ?: &no_variant; v; v = v->next) { + for (t = f->tests; t; t = t->next) { + count++; + t->results = results; + __run_test(f, v, t); + t->results = NULL; + if (t->passed) + pass_count++; + else + ret = 1; + } + } + } + munmap(results, sizeof(*results)); + + ksft_print_msg("%s: %u / %u tests passed.\n", ret ? "FAILED" : "PASSED", + pass_count, count); + ksft_exit(ret == 0); + + /* unreachable */ + return KSFT_FAIL; +} + +static void __attribute__((constructor)) __constructor_order_first(void) +{ + if (!__constructor_order) + __constructor_order = _CONSTRUCTOR_ORDER_FORWARD; +} + +#endif /* __KSELFTEST_HARNESS_H */ diff --git a/driver/tests/test_module.sh b/driver/tests/test_module.sh new file mode 100755 index 00000000..b6a6b043 --- /dev/null +++ b/driver/tests/test_module.sh @@ -0,0 +1,61 @@ +#!/usr/bin/env bash + +set -e + +function remove_slash_module() { + if [ -z "$(lsmod | grep slash)" ]; then + return 0 + fi + + echo 1 | sudo tee /sys/bus/pci/devices/${bdf}.0/remove > /dev/null + echo 1 | sudo tee /sys/bus/pci/devices/${bdf}.1/remove > /dev/null + echo 1 | sudo tee /sys/bus/pci/devices/${bdf}.2/remove > /dev/null + sudo rmmod slash +} + +if [ $# -ne 1 ]; then + echo "Usage: $! " 1>&2 + echo 1>&2 + echo "A script that builds the SLASH kernel module with code coverage instrumentation," 1>&2 + echo "Inserts it into the running kernel, runs the kselftests suite, and exports the coverage statistics." 1>&2 + echo 1>&2 + echo "Testing the kernel module requires a physical V80 to be present." 1>&2 + echo "The singular argument of this script is the BDF identifier of this V80." 1>&2 + echo 1>&2 + echo "The kernel has to be built for gcov enabled, which is checked by the script." 1>&2 + exit 1 +fi + +bdf=$1 + +if [ -z "$(cat /boot/config-$(uname -r) | grep CONFIG_GCOV_KERNEL=y)" ]; then + echo "The kernel appears to not be configured with gcov enabled." 1>&2 + echo "Please rebuild the kernel with gcov enabled and boot it." 1>&2 + exit 1 +fi + +# Build the module with gcov enabled +make -C .. GCOV=1 + +# Build the test suite +make all + +# Remove the current kernel module (if currently running) +remove_slash_module + +# Reset the gcov counters +echo 1 | sudo tee /sys/kernel/debug/gcov/reset > /dev/null + +# Load the module +sudo insmod ../slash.ko +echo 1 | sudo tee /sys/bus/pci/rescan > /dev/null + +# Run the tests +sudo make run + +# Remove the module again +remove_slash_module + +# Collect the coverage statistics +sudo lcov --capture --directory /sys/kernel/debug/gcov$(realpath .) --output-file coverage.info +genhtml coverage.info --output-directory coverage diff --git a/driver/tests/test_slash_qdma.c b/driver/tests/test_slash_qdma.c new file mode 100644 index 00000000..6a9eaa41 --- /dev/null +++ b/driver/tests/test_slash_qdma.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Basic QDMA queue-pair lifecycle test. + * + * Uses a kselftest FIXTURE to manage the control device and queue pair, + * with FIXTURE_TEARDOWN guaranteeing cleanup even if assertions fail. + * + * The DMA target address defaults to 0x0 and can be overridden via the + * SLASH_TEST_DMA_ADDR environment variable. + */ + +#include "kselftest_harness.h" + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define QDMA_CTL_DEV "/dev/slash_qdma_ctl0" +#define TRANSFER_SIZE 4096 +#define DDR_BASE_ADDRESS 0x60000000000ULL + +/* ---------- helpers ---------- */ + +static uint64_t get_dma_addr(void) +{ + const char *val = getenv("SLASH_TEST_DMA_ADDR"); + + if (val) + return strtoull(val, NULL, DDR_BASE_ADDRESS); + return 0; +} + +static int qpair_op(int fd, uint32_t qid, uint32_t op) +{ + struct slash_qdma_qpair_op req; + + memset(&req, 0, sizeof(req)); + req.size = sizeof(req); + req.qid = qid; + req.op = op; + + return ioctl(fd, SLASH_QDMA_IOCTL_Q_OP, &req); +} + +static void fill_pattern(uint8_t *buf, size_t len) +{ + size_t i; + + for (i = 0; i < len; i++) + buf[i] = (uint8_t)(i & 0xff); +} + +/* ---------- fixture ---------- */ + +FIXTURE(qdma) +{ + int ctl_fd; + uint32_t qid; + int io_fd; + int qpair_added; + int qpair_started; +}; + +FIXTURE_SETUP(qdma) +{ + self->ctl_fd = -1; + self->io_fd = -1; + self->qpair_added = 0; + self->qpair_started = 0; + + if (access(QDMA_CTL_DEV, F_OK) != 0) + SKIP(return, "QDMA device not found (%s)", QDMA_CTL_DEV); + + self->ctl_fd = open(QDMA_CTL_DEV, O_RDWR); + ASSERT_GE(self->ctl_fd, 0); +} + +FIXTURE_TEARDOWN(qdma) +{ + if (self->io_fd >= 0) + close(self->io_fd); + + if (self->qpair_started) + qpair_op(self->ctl_fd, self->qid, SLASH_QDMA_QUEUE_OP_STOP); + + if (self->qpair_added) + qpair_op(self->ctl_fd, self->qid, SLASH_QDMA_QUEUE_OP_DEL); + + if (self->ctl_fd >= 0) + close(self->ctl_fd); +} + +/* ---------- tests ---------- */ + +TEST_F(qdma, query_info) +{ + struct slash_qdma_info info; + + memset(&info, 0, sizeof(info)); + info.size = sizeof(info); + + EXPECT_GE(ioctl(self->ctl_fd, SLASH_QDMA_IOCTL_INFO, &info), 0); +} + +TEST_F(qdma, qpair_lifecycle) +{ + struct slash_qdma_qpair_add add; + struct slash_qdma_qpair_fd_request fd_req; + + /* Add queue pair */ + memset(&add, 0, sizeof(add)); + add.size = sizeof(add); + add.mode = 0; /* MM mode */ + add.dir_mask = 0x3; /* H2C | C2H */ + + ASSERT_GE(ioctl(self->ctl_fd, SLASH_QDMA_IOCTL_QPAIR_ADD, &add), 0); + self->qid = add.qid; + self->qpair_added = 1; + + /* Start queue pair */ + ASSERT_GE(qpair_op(self->ctl_fd, self->qid, SLASH_QDMA_QUEUE_OP_START), 0); + self->qpair_started = 1; + + /* Get I/O fd */ + memset(&fd_req, 0, sizeof(fd_req)); + fd_req.size = sizeof(fd_req); + fd_req.qid = self->qid; + fd_req.flags = O_CLOEXEC; + + self->io_fd = ioctl(self->ctl_fd, SLASH_QDMA_IOCTL_QPAIR_GET_FD, &fd_req); + ASSERT_GE(self->io_fd, 0); + + /* Stop queue pair */ + ASSERT_GE(qpair_op(self->ctl_fd, self->qid, SLASH_QDMA_QUEUE_OP_STOP), 0); + self->qpair_started = 0; + + /* Delete queue pair */ + ASSERT_GE(qpair_op(self->ctl_fd, self->qid, SLASH_QDMA_QUEUE_OP_DEL), 0); + self->qpair_added = 0; +} + +TEST_F(qdma, write_read_verify) +{ + struct slash_qdma_qpair_add add; + struct slash_qdma_qpair_fd_request fd_req; + uint8_t *write_buf, *read_buf; + uint64_t dma_addr = get_dma_addr(); + ssize_t ret; + + /* Add + start queue pair */ + memset(&add, 0, sizeof(add)); + add.size = sizeof(add); + add.mode = 0; + add.dir_mask = 0x3; + + ASSERT_GE(ioctl(self->ctl_fd, SLASH_QDMA_IOCTL_QPAIR_ADD, &add), 0); + self->qid = add.qid; + self->qpair_added = 1; + + ASSERT_GE(qpair_op(self->ctl_fd, self->qid, SLASH_QDMA_QUEUE_OP_START), 0); + self->qpair_started = 1; + + /* Get I/O fd */ + memset(&fd_req, 0, sizeof(fd_req)); + fd_req.size = sizeof(fd_req); + fd_req.qid = self->qid; + fd_req.flags = O_CLOEXEC; + + self->io_fd = ioctl(self->ctl_fd, SLASH_QDMA_IOCTL_QPAIR_GET_FD, &fd_req); + ASSERT_GE(self->io_fd, 0); + + /* Allocate page-aligned DMA buffers */ + write_buf = aligned_alloc(4096, TRANSFER_SIZE); + ASSERT_NE(NULL, write_buf); + read_buf = aligned_alloc(4096, TRANSFER_SIZE); + ASSERT_NE(NULL, read_buf); + + fill_pattern(write_buf, TRANSFER_SIZE); + memset(read_buf, 0, TRANSFER_SIZE); + + /* Write (H2C) */ + ret = pwrite(self->io_fd, write_buf, TRANSFER_SIZE, (off_t)dma_addr); + ASSERT_EQ(TRANSFER_SIZE, ret); + + /* Read (C2H) */ + ret = pread(self->io_fd, read_buf, TRANSFER_SIZE, (off_t)dma_addr); + ASSERT_EQ(TRANSFER_SIZE, ret); + + /* Verify */ + EXPECT_EQ(0, memcmp(write_buf, read_buf, TRANSFER_SIZE)); + + free(write_buf); + free(read_buf); +} + +TEST_HARNESS_MAIN diff --git a/examples/00_axilite/00_axilite.cpp b/examples/00_axilite/00_axilite.cpp index a917f738..87b2bda0 100644 --- a/examples/00_axilite/00_axilite.cpp +++ b/examples/00_axilite/00_axilite.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -19,14 +19,18 @@ */ #include +#include +#include #include // for std::memcpy +#include #include #include +#include -#include -#include -#include -#include +#include +#include +#include +#include int main(int argc, char* argv[]) { try { @@ -43,21 +47,43 @@ int main(int argc, char* argv[]) { vrt::Kernel accumulate(device, "accumulate_0"); vrt::Kernel increment(device, "increment_0"); - vrt::Buffer buffer(device, size, vrt::MemoryRangeType::HBM); + vrt::Buffer buffer(device, size, increment.argMemoryConfig("in")); std::random_device rd; std::mt19937 gen(rd()); std::uniform_real_distribution<> dis(0.0, 1.0); float goldenModel = 0; + std::vector hostInput(size); std::cout << "Generating data...\n"; for(uint32_t i = 0; i < size; i++) { buffer[i] = static_cast(dis(gen)); + hostInput[i] = buffer[i]; goldenModel += buffer[i] + 1; } buffer.sync(vrt::SyncType::HOST_TO_DEVICE); - increment.start(size, buffer.getPhysAddr()); - accumulate.start(size); + if (device.getPlatform() == vrt::Platform::SIMULATION) { + buffer.sync(vrt::SyncType::DEVICE_TO_HOST); + uint32_t mismatchCount = 0; + uint32_t nanCount = 0; + for (uint32_t i = 0; i < size; i++) { + if (!std::isfinite(buffer[i])) { + nanCount++; + } + if (std::memcmp(&buffer[i], &hostInput[i], sizeof(float)) != 0) { + mismatchCount++; + } + } + std::cout << "SIM pre-kernel memory roundtrip mismatches: " << mismatchCount + << ", NaNs: " << nanCount << std::endl; + std::memcpy(buffer.get(), hostInput.data(), size * sizeof(float)); + buffer.sync(vrt::SyncType::HOST_TO_DEVICE); + } + increment.setArg(0, size); + increment.setArg(1, buffer); + increment.start(); + accumulate.setArg(0, size); + accumulate.start(); auto start = std::chrono::high_resolution_clock::now(); increment.wait(); accumulate.wait(); @@ -66,18 +92,57 @@ int main(int argc, char* argv[]) { auto duration = std::chrono::duration_cast(end - start).count(); std::cout << "Time taken for waits: " << duration << " us" << std::endl; + uint32_t outCtrl = accumulate.read(0x1c); uint32_t val = accumulate.read(0x18); float floatVal; std::memcpy(&floatVal, &val, sizeof(float)); - if(std::fabs(goldenModel - floatVal) > 0.0001) { + const float absError = std::fabs(goldenModel - floatVal); + constexpr float kAbsTolerance = 1e-3f; + constexpr float kRelTolerance = 1e-6f; + const float effectiveTolerance = + std::max(kAbsTolerance, kRelTolerance * std::fabs(goldenModel)); + if ((outCtrl & 0x1u) == 0u) { std::cerr << "Test failed!" << std::endl; + std::cout << "Output valid bit is not set (out_r_ctrl=0x" << std::hex << outCtrl + << ")" << std::dec << std::endl; + std::cout << std::setprecision(10); std::cout << "Expected: " << goldenModel << std::endl; std::cout << "Got: " << floatVal << std::endl; + std::cout << "Raw register value: 0x" << std::hex << val << std::dec << std::endl; device.cleanup(); return 1; + } + if(!std::isfinite(floatVal)) { + std::cerr << "Test failed! (NaN/Inf)" << std::endl; + std::cout << "out_r_ctrl: 0x" << std::hex << outCtrl << std::dec << std::endl; + std::cout << std::setprecision(10); + std::cout << "Expected: " << goldenModel << std::endl; + std::cout << "Got: " << floatVal << std::endl; + std::cout << "Raw register value: 0x" << std::hex << val << std::dec << std::endl; + device.cleanup(); + return 1; + } else if(absError > effectiveTolerance) { + std::cerr << "Test failed! (accuracy)" << std::endl; + std::cout << "out_r_ctrl: 0x" << std::hex << outCtrl << std::dec << std::endl; + std::cout << std::setprecision(10); + std::cout << "Expected: " << goldenModel << std::endl; + std::cout << "Got: " << floatVal << std::endl; + std::cout << "Absolute error: " << absError + << " (effective tolerance " << effectiveTolerance + << ", abs " << kAbsTolerance + << ", rel " << kRelTolerance << ")" + << std::endl; + device.cleanup(); + return 2; } else { + std::cout << std::setprecision(10); std::cout << "Expected: " << goldenModel << std::endl; std::cout << "Got: " << floatVal << std::endl; + std::cout << "Absolute error: " << absError + << " (effective tolerance " << effectiveTolerance + << ", abs " << kAbsTolerance + << ", rel " << kRelTolerance << ")" + << std::endl; std::cout << "Test passed!" << std::endl; } diff --git a/examples/00_axilite/CMakeLists.txt b/examples/00_axilite/CMakeLists.txt index 916b8cf2..3a6bf888 100644 --- a/examples/00_axilite/CMakeLists.txt +++ b/examples/00_axilite/CMakeLists.txt @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,24 +18,47 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(00_axilite) +cmake_minimum_required(VERSION 3.20) +project(00_axilite LANGUAGES CXX) set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) -set(CMAKE_CXX_FLAGS "-O3") -# Include directories -include_directories(/usr/local/vrt/include - /usr/include/ami - /usr/include/libxml2 - /usr/include/jsoncpp) +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) -# Define sources for the executable -set(EXE_SOURCES 00_axilite.cpp) +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt) +else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt) +endif() -# Create the executable -add_executable(${PROJECT_NAME} ${EXE_SOURCES}) +# --- HLS kernels --- +set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") -# Link the library to the executable -target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS increment accumulate + OUT_KERNELS _KERNELS +) + +# --- VBIN targets --- +set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + +add_vbin(TARGET "axilite_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "axilite_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "axilite_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +# --- Executable --- +add_executable(${PROJECT_NAME} 00_axilite.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/00_axilite/Makefile b/examples/00_axilite/Makefile deleted file mode 100644 index 986f0a17..00000000 --- a/examples/00_axilite/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -HLS_BUILD_DIR_ACCUMULATE=build_accumulate.xcv80-lsva4737-2MHP-e-S -HLS_BUILD_DIR_INCREMENT=build_increment.xcv80-lsva4737-2MHP-e-S -DESIGN_NAME=00_axilite -HOME_DIR=$(shell realpath .) -BUILD_DIR=$(shell realpath ./build) -HLS_DIR=$(shell realpath ./hls) -V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) -VPP_DIR=$(BUILD_DIR)/v80-vitis-flow - -.PHONY: all setup hls hw emu sim app clean - -all: setup hls hw app - -emu_all: setup hls emu app - -sim_all: setup hls sim app - -hw_all: setup hls hw app - -setup: - mkdir -p $(BUILD_DIR) - cp -r $(V80PP_PATH) $(BUILD_DIR) - -hls: - @echo "Running HLS step" - $(MAKE) -C $(HLS_DIR) - -hw: setup hls - @echo "Running HW step" - cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_ACCUMULATE)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_INCREMENT)/sol1 && \ - cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR) - -emu: setup hls - @echo "Running HW step" - cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform emu --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_ACCUMULATE)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_INCREMENT)/sol1 && \ - cp build/$(DESIGN_NAME)_emu.vrtbin $(BUILD_DIR) - -sim: setup hls - @echo "Running HW step" - cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform sim --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_ACCUMULATE)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_INCREMENT)/sol1 && \ - cp build/$(DESIGN_NAME)_sim.vrtbin $(BUILD_DIR) - -app: setup - @echo "Running user app build step" - mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ - cmake .. && \ - make -j9 - @echo "Setting LD_LIBRARY_PATH" - export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH - @echo "Setting PATH" - export PATH=$$PATH:/usr/local/sbin - -clean: - rm -rf $(BUILD_DIR) - make -C $(HLS_DIR) clean \ No newline at end of file diff --git a/examples/00_axilite/config.cfg b/examples/00_axilite/config.cfg index 2de6db12..46bb790a 100644 --- a/examples/00_axilite/config.cfg +++ b/examples/00_axilite/config.cfg @@ -22,3 +22,4 @@ nk=accumulate:1:accumulate_0 nk=increment:1:increment_0 stream_connect=increment_0.axis_out:accumulate_0.axis_in +sp=increment_0.m_axi_gmem0:HBM1 \ No newline at end of file diff --git a/examples/00_axilite/hls/accumulate.cfg b/examples/00_axilite/hls/accumulate.cfg new file mode 100644 index 00000000..60dd1cf2 --- /dev/null +++ b/examples/00_axilite/hls/accumulate.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=accumulate +syn.file=accumulate.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/00_axilite/hls/increment.cfg b/examples/00_axilite/hls/increment.cfg new file mode 100644 index 00000000..30adcafb --- /dev/null +++ b/examples/00_axilite/hls/increment.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=increment +syn.file=increment.cpp +clock=4ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/01_aximm/01_example.cpp b/examples/01_aximm/01_aximm.cpp similarity index 77% rename from examples/01_aximm/01_example.cpp rename to examples/01_aximm/01_aximm.cpp index 66f23920..b63127a7 100644 --- a/examples/01_aximm/01_example.cpp +++ b/examples/01_aximm/01_aximm.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -28,9 +28,9 @@ #include -#include -#include -#include +#include +#include +#include int main(int argc, char* argv[]) { if (argc < 3) { @@ -47,23 +47,29 @@ int main(int argc, char* argv[]) { vrt::Kernel dma(device, "dma_0"); vrt::Kernel offset(device, "offset_0"); - vrt::Buffer in_buff(device, size, vrt::MemoryRangeType::HBM); - vrt::Buffer out_buff(device, size, vrt::MemoryRangeType::HBM); + vrt::Buffer in_buff(device, size, offset.argMemoryConfig("input")); + vrt::Buffer out_buff(device, size, dma.argMemoryConfig("out")); for(uint32_t i = 0; i < size; i++) { - in_buff[i] = 1; + in_buff[i] = i; } in_buff.sync(vrt::SyncType::HOST_TO_DEVICE); - offset.start(size, in_buff.getPhysAddr(), m, n); - dma.start(size, out_buff.getPhysAddr()); + offset.setArg(0, size); + offset.setArg(1, in_buff); + offset.setArg(2, m); + offset.setArg(3, n); + dma.setArg(0, size); + dma.setArg(1, out_buff); + offset.start(); + dma.start(); offset.wait(); dma.wait(); out_buff.sync(vrt::SyncType::DEVICE_TO_HOST); for(uint32_t i = 0; i < size; i++) { if(out_buff[i] != in_buff[i] * m + n) { - std::cerr << "Test failed" << std::endl; + std::cerr << "Test failed (accuracy)" << std::endl; std::cerr << "Error: " << i << " " << out_buff[i] << " " << in_buff[i] << std::endl; device.cleanup(); - return 1; + return 2; } } std::cout << "Test passed" << std::endl; diff --git a/examples/01_aximm/CMakeLists.txt b/examples/01_aximm/CMakeLists.txt index 179bc437..b9f14bb3 100644 --- a/examples/01_aximm/CMakeLists.txt +++ b/examples/01_aximm/CMakeLists.txt @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,23 +18,47 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(01_example) +cmake_minimum_required(VERSION 3.20) +project(01_aximm LANGUAGES CXX) set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) -# Include directories -include_directories(/usr/local/vrt/include - /usr/include/ami - /usr/include/libxml2 - /usr/include/jsoncpp) +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) -# Define sources for the executable -set(EXE_SOURCES 01_example.cpp) +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt) +else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt) +endif() -# Create the executable -add_executable(${PROJECT_NAME} ${EXE_SOURCES}) +# --- HLS kernels --- +set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") -# Link the library to the executable -target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS dma offset + OUT_KERNELS _KERNELS +) + +# --- VBIN targets --- +set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + +add_vbin(TARGET "aximm_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "aximm_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "aximm_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +# --- Executable --- +add_executable(${PROJECT_NAME} 01_aximm.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/01_aximm/Makefile b/examples/01_aximm/Makefile deleted file mode 100644 index 3c728a83..00000000 --- a/examples/01_aximm/Makefile +++ /dev/null @@ -1,76 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -HLS_BUILD_DIR_OFFSET=build_offset.xcv80-lsva4737-2MHP-e-S -HLS_BUILD_DIR_DMA=build_dma.xcv80-lsva4737-2MHP-e-S -DESIGN_NAME=01_example -HOME_DIR=$(shell realpath .) -BUILD_DIR=$(shell realpath ./build) -HLS_DIR=$(shell realpath ./hls) -V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) -VPP_DIR=$(BUILD_DIR)/v80-vitis-flow - -.PHONY: all setup hls hw emu sim app clean - -all: setup hls hw app - -emu_all: setup hls emu app - -sim_all: setup hls sim app - -hw_all: setup hls hw app - -setup: - mkdir -p $(BUILD_DIR) - cp -r $(V80PP_PATH) $(BUILD_DIR) - -hls: - @echo "Running HLS step" - $(MAKE) -C $(HLS_DIR) - -hw: setup hls - @echo "Running HW step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_OFFSET)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_DMA)/sol1 && \ - cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR)) - -emu: setup hls - @echo "Running EMU step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform emu --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_OFFSET)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_DMA)/sol1 && \ - cp build/$(DESIGN_NAME)_emu.vrtbin $(BUILD_DIR)) - -sim: setup hls - @echo "Running SIM step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform sim --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_OFFSET)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_DMA)/sol1 && \ - cp build/$(DESIGN_NAME)_sim.vrtbin $(BUILD_DIR)) - -app: setup - @echo "Running user app build step" - mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ - cmake .. && \ - make -j9 - @echo "Setting LD_LIBRARY_PATH" - export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH - @echo "Setting PATH" - export PATH=$$PATH:/usr/local/sbin -clean: - rm -rf $(BUILD_DIR) \ No newline at end of file diff --git a/examples/01_aximm/config.cfg b/examples/01_aximm/config.cfg index e9cbd673..78a1c9ac 100644 --- a/examples/01_aximm/config.cfg +++ b/examples/01_aximm/config.cfg @@ -20,5 +20,8 @@ [connectivity] nk=dma:1:dma_0 -nk=offset:1:offset_0 +nk=offset:1:offset_0 stream_connect=offset_0.axis_out:dma_0.axis_in +sp=dma_0.m_axi_gmem0:HBM0 +sp=offset_0.m_axi_gmem0:DDR0 + diff --git a/examples/01_aximm/hls/dma.cfg b/examples/01_aximm/hls/dma.cfg new file mode 100644 index 00000000..6fd7334a --- /dev/null +++ b/examples/01_aximm/hls/dma.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=dma +syn.file=dma.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/01_aximm/hls/offset.cfg b/examples/01_aximm/hls/offset.cfg new file mode 100644 index 00000000..acff55bf --- /dev/null +++ b/examples/01_aximm/hls/offset.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=offset +syn.file=offset.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/02_chain/02_example.cpp b/examples/02_chain/02_example.cpp index b7510969..b33f5481 100644 --- a/examples/02_chain/02_example.cpp +++ b/examples/02_chain/02_example.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -20,10 +20,10 @@ #include #include -#include -#include -#include -#include +#include +#include +#include +#include int main(int argc, char* argv[]) { try { @@ -33,34 +33,39 @@ int main(int argc, char* argv[]) { } std::string bdf = argv[1]; std::string vrtbinFile = argv[2]; - uint32_t size = 512 * 1024 * 1024; + uint32_t size = 1024*4; vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::DEBUG); vrt::Device device(bdf, vrtbinFile); vrt::Kernel dma_in(device, "dma_in_0"); vrt::Kernel dma_out(device, "dma_out_0"); - vrt::Buffer buffer_in(device, size, vrt::MemoryRangeType::HBM); - vrt::Buffer buffer_out(device, size, vrt::MemoryRangeType::HBM); + vrt::Buffer buffer_in(device, size, dma_in.argMemoryConfig("in")); + vrt::Buffer buffer_out(device, size, dma_out.argMemoryConfig("out")); for(uint32_t i = 0; i < size; i++) { buffer_in[i] = static_cast(i); } buffer_in.sync(vrt::SyncType::HOST_TO_DEVICE); - dma_in.start(buffer_in.getPhysAddr(), size); - dma_out.start(size, buffer_out.getPhysAddr()); + dma_in.setArg(0, buffer_in); + dma_in.setArg(1, size); + dma_out.setArg(0, size); + dma_out.setArg(1, buffer_out); + dma_in.start(); + dma_out.start(); dma_in.wait(); dma_out.wait(); buffer_out.sync(vrt::SyncType::DEVICE_TO_HOST); for(uint32_t i = 0; i < size; i++) { if(buffer_in[i] != buffer_out[i]) { - vrt::utils::Logger::log(vrt::utils::LogLevel::ERROR, __PRETTY_FUNCTION__, "Test failed"); + vrt::utils::Logger::log(vrt::utils::LogLevel::ERROR, __PRETTY_FUNCTION__, "Test failed (accuracy)"); device.cleanup(); - return 0; + return 2; } } vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Test passed"); device.cleanup(); } catch (const std::exception& e) { std::cerr << e.what() << std::endl; + return 1; } return 0; } diff --git a/examples/02_chain/CMakeLists.txt b/examples/02_chain/CMakeLists.txt index cf0e8e2b..d5aaa4f8 100644 --- a/examples/02_chain/CMakeLists.txt +++ b/examples/02_chain/CMakeLists.txt @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,22 +18,47 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(02_example) +cmake_minimum_required(VERSION 3.20) +project(02_chain LANGUAGES CXX) set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) -include_directories(/usr/local/vrt/include - /usr/include/ami - /usr/include/libxml2 - /usr/include/jsoncpp) +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) -# Define sources for the executable -set(EXE_SOURCES 02_example.cpp) +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt) +else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt) +endif() -# Create the executable -add_executable(${PROJECT_NAME} ${EXE_SOURCES}) +# --- HLS kernels --- +set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") -# Link the library to the executable -target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS dma_in dma_out passthrough + OUT_KERNELS _KERNELS +) + +# --- VBIN targets --- +set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + +add_vbin(TARGET "chain_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "chain_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "chain_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +# --- Executable --- +add_executable(${PROJECT_NAME} 02_example.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/02_chain/Makefile b/examples/02_chain/Makefile deleted file mode 100644 index a11cbb6a..00000000 --- a/examples/02_chain/Makefile +++ /dev/null @@ -1,69 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -HLS_BUILD_DIR_DMA_IN=build_dma_in.xcv80-lsva4737-2MHP-e-S -HLS_BUILD_DIR_PASSTHROUGH=build_passthrough.xcv80-lsva4737-2MHP-e-S -HLS_BUILD_DIR_DMA_OUT=build_dma_out.xcv80-lsva4737-2MHP-e-S -DESIGN_NAME=02_example -HOME_DIR=$(shell realpath .) -BUILD_DIR=$(shell realpath ./build) -HLS_DIR=$(shell realpath ./hls) -V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) -VPP_DIR=$(BUILD_DIR)/v80-vitis-flow - -.PHONY: all setup hls hw emu sim app clean - -all: setup hls hw app - -sim_all: setup hls sim app - -hw_all: setup hls hw app - -setup: - mkdir -p $(BUILD_DIR) - cp -r $(V80PP_PATH) $(BUILD_DIR) - -hls: - @echo "Running HLS step" - $(MAKE) -C $(HLS_DIR) - -hw: setup hls - @echo "Running HW step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_DMA_IN)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_PASSTHROUGH)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_DMA_OUT)/sol1 && \ - cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR)) - -sim: setup hls - @echo "Running SIM step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform sim --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_DMA_IN)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_PASSTHROUGH)/sol1 $(HLS_DIR)/$(HLS_BUILD_DIR_DMA_OUT)/sol1 && \ - cp build/$(DESIGN_NAME)_sim.vrtbin $(BUILD_DIR)) - -app: setup - @echo "Running user app build step" - mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ - cmake .. && \ - make -j9 - @echo "Setting LD_LIBRARY_PATH" - export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH - @echo "Setting PATH" - export PATH=$$PATH:/usr/local/sbin -clean: - rm -rf $(BUILD_DIR) \ No newline at end of file diff --git a/examples/02_chain/hls/Makefile b/examples/02_chain/hls/Makefile deleted file mode 100644 index 2b6bed82..00000000 --- a/examples/02_chain/hls/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -TARGET=ip -DEVICE=xcv80-lsva4737-2MHP-e-S - -DMA_IN_BUILD_DIR=build_dma_in.$(DEVICE) -PASSTHROUGH_BUILD_DIR=build_passthrough.$(DEVICE) -DMA_OUT_BUILD_DIR=build_dma_out.$(DEVICE) - -all: $(DMA_IN_BUILD_DIR) $(PASSTHROUGH_BUILD_DIR) $(DMA_OUT_BUILD_DIR) - -$(DMA_IN_BUILD_DIR): - if [ ! -d "$(DMA_IN_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) dma_in; \ - fi - -$(PASSTHROUGH_BUILD_DIR): - if [ ! -d "$(PASSTHROUGH_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) passthrough; \ - fi - -$(DMA_OUT_BUILD_DIR): - if [ ! -d "$(DMA_OUT_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) dma_out; \ - fi - -clean: - rm -rf $(DMA_IN_BUILD_DIR) $(PASSTHROUGH_BUILD_DIR) $(DMA_OUT_BUILD_DIR) vitis_hls.log \ No newline at end of file diff --git a/examples/02_chain/hls/dma_in.cfg b/examples/02_chain/hls/dma_in.cfg new file mode 100644 index 00000000..48f8c263 --- /dev/null +++ b/examples/02_chain/hls/dma_in.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=dma_in +syn.file=dma_in.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/02_chain/hls/dma_out.cfg b/examples/02_chain/hls/dma_out.cfg new file mode 100644 index 00000000..72a3fb2f --- /dev/null +++ b/examples/02_chain/hls/dma_out.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=dma_out +syn.file=dma_out.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/02_chain/hls/passthrough.cfg b/examples/02_chain/hls/passthrough.cfg new file mode 100644 index 00000000..8e653fc2 --- /dev/null +++ b/examples/02_chain/hls/passthrough.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=passthrough +syn.file=passthrough.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/03_multiple_boards/03_example.cpp b/examples/03_multiple_boards/03_example.cpp index eae64c5f..038acf1d 100644 --- a/examples/03_multiple_boards/03_example.cpp +++ b/examples/03_multiple_boards/03_example.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -22,10 +22,10 @@ #include #include -#include -#include -#include -#include +#include +#include +#include +#include int main() { try { diff --git a/examples/03_multiple_boards/CMakeLists.txt b/examples/03_multiple_boards/CMakeLists.txt index 96ab658c..c85bde0e 100644 --- a/examples/03_multiple_boards/CMakeLists.txt +++ b/examples/03_multiple_boards/CMakeLists.txt @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) # Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,19 +18,25 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(03_example) +cmake_minimum_required(VERSION 3.20) +project(03_example LANGUAGES CXX) set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) -include_directories(/usr/local/vrt/include - /usr/include/ami - /usr/include/libxml2 - /usr/include/jsoncpp) +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) -set(EXE_SOURCES 03_example.cpp) +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt) +else() + find_package(vrt REQUIRED CONFIG) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt) +endif() -add_executable(${PROJECT_NAME} ${EXE_SOURCES}) - -target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file +add_executable(${PROJECT_NAME} 03_example.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/04_freq/04_freq.cpp b/examples/04_freq/04_freq.cpp index a45bb640..6ecf4b5a 100644 --- a/examples/04_freq/04_freq.cpp +++ b/examples/04_freq/04_freq.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -21,9 +21,9 @@ #include #include -#include -#include -#include +#include +#include +#include int main(int argc, char* argv[]) { try { @@ -41,12 +41,13 @@ int main(int argc, char* argv[]) { std::cout << "Current set frequency: "<< device.getFrequency() << " Hz" << std::endl; std::cout << "Max frequency: "<< device.getMaxFrequency() << " Hz" << std::endl; - device.setFrequency(500000000); + + device.setFrequency(300000000); std::cout << "Current set frequency: "<< device.getFrequency() << " Hz" << std::endl; - vrt::Buffer a(device, size, vrt::MemoryRangeType::HBM); - vrt::Buffer b(device, size, vrt::MemoryRangeType::HBM); - vrt::Buffer c(device, size, vrt::MemoryRangeType::HBM); + vrt::Buffer a(device, size, vrt::MemoryRangeType::HBM, 0); + vrt::Buffer b(device, size, vrt::MemoryRangeType::HBM, 1); + vrt::Buffer c(device, size, vrt::MemoryRangeType::HBM, 2); for (int i = 0; i < size; i++) { a[i] = i; @@ -54,14 +55,20 @@ int main(int argc, char* argv[]) { } a.sync(vrt::SyncType::HOST_TO_DEVICE); b.sync(vrt::SyncType::HOST_TO_DEVICE); - vadd_0.start(a.getPhysAddr(), b.getPhysAddr(), c.getPhysAddr(), size); + vadd_0.setArg(0, a); + vadd_0.setArg(1, b); + vadd_0.setArg(2, c); + vadd_0.setArg(3, size); + vadd_0.start(); + //vadd_0.start(a, b, c, size); vadd_0.wait(); c.sync(vrt::SyncType::DEVICE_TO_HOST); for (int i = 0; i < size; i++) { if (c[i] != a[i] + b[i]) { + std::cerr << "Test failed (accuracy)" << std::endl; std::cerr << "Error: " << c[i] << " != " << a[i] << " + " << b[i] << std::endl; device.cleanup(); - return 1; + return 2; } } std::cout << "Test passed" << std::endl; @@ -70,4 +77,4 @@ int main(int argc, char* argv[]) { std::cerr << "Exception: " << e.what() << std::endl; return 1; } -} \ No newline at end of file +} diff --git a/examples/04_freq/CMakeLists.txt b/examples/04_freq/CMakeLists.txt index e5060d4f..127f9866 100644 --- a/examples/04_freq/CMakeLists.txt +++ b/examples/04_freq/CMakeLists.txt @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,23 +18,47 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(04_freq) +cmake_minimum_required(VERSION 3.20) +project(04_freq LANGUAGES CXX) set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) -# Include directories -include_directories(/usr/local/vrt/include - /usr/include/ami - /usr/include/libxml2 - /usr/include/jsoncpp) +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) -# Define sources for the executable -set(EXE_SOURCES 04_freq.cpp) +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt) +else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt) +endif() -# Create the executable -add_executable(${PROJECT_NAME} ${EXE_SOURCES}) +# --- HLS kernels --- +set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") -# Link the library to the executable -target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS vadd + OUT_KERNELS _KERNELS +) + +# --- VBIN targets --- +set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + +add_vbin(TARGET "freq_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "freq_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "freq_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +# --- Executable --- +add_executable(${PROJECT_NAME} 04_freq.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/04_freq/Makefile b/examples/04_freq/Makefile deleted file mode 100644 index d6798e1d..00000000 --- a/examples/04_freq/Makefile +++ /dev/null @@ -1,76 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -HLS_BUILD_DIR_VADD = build_vadd.xcv80-lsva4737-2MHP-e-S -DESIGN_NAME = 04_freq - -HOME_DIR=$(shell realpath .) -BUILD_DIR=$(shell realpath ./build) -HLS_DIR=$(shell realpath ./hls) -V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) -VPP_DIR=$(BUILD_DIR)/v80-vitis-flow - -.PHONY: all setup hls hw emu sim app clean - -all: setup hls hw app - -emu_all: setup hls emu app - -sim_all: setup hls sim app - -hw_all: setup hls hw app - -setup: - mkdir -p $(BUILD_DIR) - cp -r $(V80PP_PATH) $(BUILD_DIR) - -hls: - @echo "Running HLS step" - $(MAKE) -C $(HLS_DIR) - -hw: setup hls - @echo "Running HW step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_VADD)/sol1 && \ - cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR)) - -emu: setup hls - @echo "Running EMU step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform emu --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_VADD)/sol1 && \ - cp build/$(DESIGN_NAME)_emu.vrtbin $(BUILD_DIR)) - -sim: setup hls - @echo "Running SIM step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform sim --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_VADD)/sol1 && \ - cp build/$(DESIGN_NAME)_sim.vrtbin $(BUILD_DIR)) - -app: setup - @echo "Running user app build step" - mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ - cmake .. && \ - make -j9 - @echo "Setting LD_LIBRARY_PATH" - export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH - @echo "Setting PATH" - export PATH=$$PATH:/usr/local/sbin -clean: - rm -rf $(BUILD_DIR) \ No newline at end of file diff --git a/examples/04_freq/config.cfg b/examples/04_freq/config.cfg index 08ba16cd..4e317882 100644 --- a/examples/04_freq/config.cfg +++ b/examples/04_freq/config.cfg @@ -23,4 +23,9 @@ nk=vadd:1:vadd_0 [clock] -freqhz=500000000 \ No newline at end of file +krnl=vadd_0 +freqhz=400000000 + +sp=vadd_0.m_axi_gmem0:HBM0 +sp=vadd_0.m_axi_gmem1:HBM1 +sp=vadd_0.m_axi_gmem2:HBM2 diff --git a/examples/04_freq/hls/vadd.cfg b/examples/04_freq/hls/vadd.cfg new file mode 100644 index 00000000..a496003c --- /dev/null +++ b/examples/04_freq/hls/vadd.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=vadd +syn.file=vadd.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/05_perf/05_perf.cpp b/examples/05_perf/05_perf.cpp index f7f4dfe0..651a00d0 100644 --- a/examples/05_perf/05_perf.cpp +++ b/examples/05_perf/05_perf.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,82 +18,226 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ +#include +#include +#include #include -#include +#include +#include #include -#include -#include -#include -#include +#include +#include +#include +#include + +namespace { + +constexpr std::size_t kTotalKernels = 76; +constexpr std::size_t kDefaultKernels = 2; +constexpr std::size_t kHbmKernels = 64; +constexpr std::size_t kMemKernels = 8; +constexpr std::size_t kDdrKernels = 4; +static_assert(kHbmKernels + kMemKernels + kDdrKernels == kTotalKernels, + "Kernel group counts must match config.cfg"); + +constexpr std::uint32_t kPerfLength = 0x1000000u; +constexpr std::uint32_t kWriteMode = 0u; +constexpr std::uint32_t kReadMode = 1u; + +constexpr std::uint32_t kOutAccDataOffset = 0x24u; +constexpr std::uint32_t kOutAccCtrlOffset = 0x28u; + +struct alignas(32) Word256 { + std::uint32_t lane[8]; +}; + +static_assert(sizeof(Word256) == 32, "Word256 must match 256-bit kernel data width"); + +std::uint32_t xorZeroToN(std::uint32_t n) { + switch (n & 0x3u) { + case 0u: + return n; + case 1u: + return 1u; + case 2u: + return n + 1u; + default: + return 0u; + } +} + +double gibPerSecond(std::uint64_t bytes, std::chrono::nanoseconds elapsed) { + if (elapsed.count() == 0) { + return 0.0; + } + constexpr double kGiB = 1024.0 * 1024.0 * 1024.0; + return (static_cast(bytes) / kGiB) / + (static_cast(elapsed.count()) / 1'000'000'000.0); +} + +vrt::Buffer makePerfBuffer(vrt::Device& device, std::size_t kernelIdx) { + if (kernelIdx < kHbmKernels) { + return vrt::Buffer(device, kPerfLength, vrt::MemoryRangeType::HBM, + static_cast(kernelIdx)); + } + if (kernelIdx < (kHbmKernels + kMemKernels)) { + return vrt::Buffer(device, kPerfLength, vrt::MemoryRangeType::HBM_VNOC); + } + return vrt::Buffer(device, kPerfLength, vrt::MemoryRangeType::DDR); +} + +const char* memoryGroupName(std::size_t kernelIdx) { + if (kernelIdx < kHbmKernels) { + return "HBM"; + } + if (kernelIdx < (kHbmKernels + kMemKernels)) { + return "MEM"; + } + return "DDR"; +} + +} // namespace int main(int argc, char* argv[]) { - try { - if (argc < 3) { - std::cerr << "Usage: " << argv[0] << " " << std::endl; + if (argc < 3 || argc > 4) { + std::cerr << "Usage: " << argv[0] << " [kernel_count<=76]" + << std::endl; + return 1; + } + + const std::string bdf = argv[1]; + const std::string vrtbinFile = argv[2]; + + std::size_t kernelCount = kDefaultKernels; + if (argc == 4) { + try { + kernelCount = static_cast(std::stoul(argv[3])); + } catch (const std::exception&) { + std::cerr << "Invalid kernel_count: " << argv[3] << std::endl; + return 1; + } + if (kernelCount == 0 || kernelCount > kTotalKernels) { + std::cerr << "kernel_count must be in [1, " << kTotalKernels << "]" << std::endl; return 1; } - std::string bdf = argv[1]; - std::string vrtbinFile = argv[2]; - vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::DEBUG); - vrt::Device device("21:00.0", "05_perf_emu.vrtbin"); - uint32_t size = 1024; - device.setFrequency(400000000); + } + + try { + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::INFO); + + const std::uint64_t bytesPerKernel = static_cast(kPerfLength) * sizeof(Word256); + const double bufferFootprintGiB = + (static_cast(bytesPerKernel) * static_cast(kernelCount)) / + (1024.0 * 1024.0 * 1024.0); + + std::cout << "VRT Version: " << vrt::getVersion() << std::endl; + std::cout << "Launching " << kernelCount << " perf kernels" << std::endl; + std::cout << "Per-kernel buffer size: " << (bytesPerKernel >> 20) << " MiB" << std::endl; + std::cout << std::fixed << std::setprecision(2) + << "Aggregate buffer footprint: " << bufferFootprintGiB << " GiB" << std::endl; + + vrt::Device device(bdf, vrtbinFile); + const bool isEmu = (device.getPlatform() == vrt::Platform::EMULATION); std::vector kernels; - kernels.reserve(15); - for(int i = 0; i < 15; i++) { - kernels.push_back(std::move(vrt::Kernel(device, "perf_" + std::to_string(i)))); + kernels.reserve(kernelCount); + for (std::size_t i = 0; i < kernelCount; ++i) { + kernels.emplace_back(device, "perf_" + std::to_string(i)); } - std::vector> buffers; - buffers.reserve(15); - for(int i = 0; i < 15; i++) { - vrt::Buffer buffer(device, size, vrt::MemoryRangeType::HBM); - buffers.emplace_back(std::move(buffer)); + std::vector> buffers; + buffers.reserve(kernelCount); + for (std::size_t i = 0; i < kernelCount; ++i) { + buffers.emplace_back(makePerfBuffer(device, i)); } - for (int i = 0; i < 15; i++) { - uint64_t addr = buffers[i].getPhysAddr(); - kernels[i].start(size * sizeof(uint32_t) / 64, buffers[i].getPhysAddr()); + if (isEmu) { + std::cout << "EMU pre-populating " << kernelCount + << " buffer(s) so tb.cpp has buffer mappings..." << std::endl; + for (std::size_t i = 0; i < kernelCount; ++i) { + if (kernelCount <= 4) { + std::cout << " populate perf_" << i << " (" << memoryGroupName(i) << ")" + << std::endl; + } + buffers[i].sync(vrt::SyncType::HOST_TO_DEVICE); + } + std::cout << "EMU buffer pre-population complete" << std::endl; } - auto start_time = std::chrono::high_resolution_clock::now(); - - // The line you want to measure - kernels[14].wait(); - - // Add timing code after wait call - auto end_time = std::chrono::high_resolution_clock::now(); - auto duration = std::chrono::duration_cast(end_time - start_time); - - // Print the time taken - std::cout << "Time taken for kernels[14].wait(): " << duration.count() << " milliseconds" << std::endl; + auto runPhase = [&](std::uint32_t wr, const char* label) { + std::cout << label << " phase: launching " << kernelCount << " kernel(s)" << std::endl; + const auto tStart = std::chrono::high_resolution_clock::now(); + for (std::size_t i = 0; i < kernelCount; ++i) { + if (isEmu && kernelCount <= 4) { + std::cout << " " << label << " start perf_" << i << "..." << std::endl; + } + kernels[i].setArg(0, buffers[i]); + kernels[i].setArg(1, wr); + kernels[i].start(); + if (isEmu && kernelCount <= 4) { + std::cout << " " << label << " start perf_" << i << " returned" << std::endl; + } + } + for (std::size_t i = 0; i < kernelCount; ++i) { + kernels[i].wait(); + } + const auto tEnd = std::chrono::high_resolution_clock::now(); + const auto elapsed = + std::chrono::duration_cast(tEnd - tStart); + + const std::uint64_t totalBytes = bytesPerKernel * static_cast(kernelCount); + std::cout << label << " phase time: " + << std::chrono::duration_cast(elapsed).count() + << " ms"; + std::cout << " (" << std::fixed << std::setprecision(2) + << gibPerSecond(totalBytes, elapsed) << " GiB/s aggregate)" << std::endl; + return elapsed; + }; + const auto writeElapsed = runPhase(kWriteMode, "Write"); + const auto readElapsed = runPhase(kReadMode, "Read"); + + const std::uint32_t expectedAcc = xorZeroToN(kPerfLength - 1u); + std::size_t failures = 0; + for (std::size_t i = 0; i < kernelCount; ++i) { + const std::uint32_t outAcc = kernels[i].read(kOutAccDataOffset); + const std::uint32_t outAccCtrl = kernels[i].read(kOutAccCtrlOffset); + const bool valid = (outAccCtrl & 0x1u) != 0u; + + if (!valid || outAcc != expectedAcc) { + if (failures < 8) { + std::cerr << "Kernel perf_" << i << " (" << memoryGroupName(i) + << ") failed: out_acc=0x" << std::hex << outAcc + << ", out_acc_ctrl=0x" << outAccCtrl + << ", expected=0x" << expectedAcc << std::dec << std::endl; + } + ++failures; + } + } + + const auto totalElapsed = writeElapsed + readElapsed; + const std::uint64_t totalBytes = 2ull * bytesPerKernel * static_cast(kernelCount); + std::cout << std::fixed << std::setprecision(2) + << "Combined read+write throughput: " << gibPerSecond(totalBytes, totalElapsed) + << " GiB/s aggregate" << std::endl; + + if (failures != 0) { + std::cerr << failures << " kernel(s) produced invalid output" << std::endl; + device.cleanup(); + return 1; + } + + std::cout << "Test passed" << std::endl; device.cleanup(); + return 0; + } catch (const std::bad_alloc& e) { + std::cerr << "Allocation failed: " << e.what() << std::endl; + std::cerr << "Try a smaller optional kernel_count (1-" << kTotalKernels + << ") to reduce host/device memory usage." << std::endl; + return 1; } catch (const std::exception& e) { - // std::cerr << e.what() << std::endl; - // device.cleanup(); + std::cerr << "Exception: " << e.what() << std::endl; + return 1; } - - // vrt::Device device("21:00.0", "05_perf_emu.vrtbin"); - // try { - // uint32_t size = 1000; - // vrt::Kernel perf_0(device, "perf_0"); - // vrt::Buffer buffer(device, size, vrt::MemoryRangeType::HBM); - // for(int j = 0; j < size; j++) { - // buffer[j] = j; - // } - // buffer.sync(vrt::SyncType::HOST_TO_DEVICE); - // perf_0.call(size, buffer.getPhysAddr()); - // buffer.sync(vrt::SyncType::DEVICE_TO_HOST); - // for(int j = 0; j < size; j++) { - // std::cout << buffer[j] << " "; - // } - // device.cleanup(); - // } catch (const std::exception& e) { - // std::cerr << e.what() << std::endl; - // device.cleanup(); - // } - // return 0; -} \ No newline at end of file +} diff --git a/examples/05_perf/CMakeLists.txt b/examples/05_perf/CMakeLists.txt index 47156f08..4290ad1c 100644 --- a/examples/05_perf/CMakeLists.txt +++ b/examples/05_perf/CMakeLists.txt @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,19 +18,47 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -cmake_minimum_required(VERSION 3.10) -project(05_perf) +cmake_minimum_required(VERSION 3.20) +project(05_perf LANGUAGES CXX) set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) -include_directories(/usr/local/vrt/include - /usr/include/ami - /usr/include/libxml2 - /usr/include/jsoncpp) +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) -set(EXE_SOURCES 05_perf.cpp) +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES /usr/include/ami) + set(_VRT_LIBS vrt ami) +else() + find_package(vrt REQUIRED CONFIG) + find_package(SlashTools REQUIRED) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt ami) +endif() -add_executable(${PROJECT_NAME} ${EXE_SOURCES}) +# --- HLS kernels --- +set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") -target_link_libraries(${PROJECT_NAME} vrt ami xml2 zmq jsoncpp) \ No newline at end of file +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS perf + OUT_KERNELS _KERNELS +) + +# --- VBIN targets --- +set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + +add_vbin(TARGET "perf_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "perf_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "perf_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +# --- Executable --- +add_executable(${PROJECT_NAME} 05_perf.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/05_perf/Makefile b/examples/05_perf/Makefile deleted file mode 100644 index 8a080dbf..00000000 --- a/examples/05_perf/Makefile +++ /dev/null @@ -1,76 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -HLS_BUILD_DIR_PERF = build_perf.xcv80-lsva4737-2MHP-e-S -DESIGN_NAME = 05_perf - -HOME_DIR=$(shell realpath .) -BUILD_DIR=$(shell realpath ./build) -HLS_DIR=$(shell realpath ./hls) -V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) -VPP_DIR=$(BUILD_DIR)/v80-vitis-flow - -.PHONY: all setup hls hw emu sim app clean - -all: setup hls hw app - -emu_all: setup hls emu app - -sim_all: setup hls sim app - -hw_all: setup hls hw app - -setup: - mkdir -p $(BUILD_DIR) - cp -r $(V80PP_PATH) $(BUILD_DIR) - -hls: - @echo "Running HLS step" - $(MAKE) -C $(HLS_DIR) - -hw: setup hls - @echo "Running HW step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform hw --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_PERF)/sol1 && \ - cp build/$(DESIGN_NAME)_hw.vrtbin $(BUILD_DIR)) - -emu: setup hls - @echo "Running EMU step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform emu --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_PERF)/sol1 && \ - cp build/$(DESIGN_NAME)_emu.vrtbin $(BUILD_DIR)) - -sim: setup hls - @echo "Running SIM step" - (cd $(VPP_DIR) && \ - ./scripts/v80++ --design-name $(DESIGN_NAME) --cfg $(HOME_DIR)/config.cfg --platform sim --segmented --kernels $(HLS_DIR)/$(HLS_BUILD_DIR_PERF)/sol1 && \ - cp build/$(DESIGN_NAME)_sim.vrtbin $(BUILD_DIR)) - -app: setup - @echo "Running user app build step" - mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ - cmake .. && \ - make -j9 - @echo "Setting LD_LIBRARY_PATH" - export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH - @echo "Setting PATH" - export PATH=$$PATH:/usr/local/sbin -clean: - rm -rf $(BUILD_DIR) \ No newline at end of file diff --git a/examples/05_perf/config.cfg b/examples/05_perf/config.cfg index 0d5889da..98763ce0 100644 --- a/examples/05_perf/config.cfg +++ b/examples/05_perf/config.cfg @@ -20,7 +20,83 @@ [connectivity] -nk=perf:15:perf_0.perf_1.perf_2.perf_3.perf_4.perf_5.perf_6.perf_7.perf_8.perf_9.perf_10.perf_11.perf_12.perf_13.perf_14 +nk=perf:76 -[clock] -freqhz=300000000 \ No newline at end of file +sp=perf_0.m_axi_gmem0:HBM0 +sp=perf_1.m_axi_gmem0:HBM1 +sp=perf_2.m_axi_gmem0:HBM2 +sp=perf_3.m_axi_gmem0:HBM3 +sp=perf_4.m_axi_gmem0:HBM4 +sp=perf_5.m_axi_gmem0:HBM5 +sp=perf_6.m_axi_gmem0:HBM6 +sp=perf_7.m_axi_gmem0:HBM7 +sp=perf_8.m_axi_gmem0:HBM8 +sp=perf_9.m_axi_gmem0:HBM9 +sp=perf_10.m_axi_gmem0:HBM10 +sp=perf_11.m_axi_gmem0:HBM11 +sp=perf_12.m_axi_gmem0:HBM12 +sp=perf_13.m_axi_gmem0:HBM13 +sp=perf_14.m_axi_gmem0:HBM14 +sp=perf_15.m_axi_gmem0:HBM15 +sp=perf_16.m_axi_gmem0:HBM16 +sp=perf_17.m_axi_gmem0:HBM17 +sp=perf_18.m_axi_gmem0:HBM18 +sp=perf_19.m_axi_gmem0:HBM19 +sp=perf_20.m_axi_gmem0:HBM20 +sp=perf_21.m_axi_gmem0:HBM21 +sp=perf_22.m_axi_gmem0:HBM22 +sp=perf_23.m_axi_gmem0:HBM23 +sp=perf_24.m_axi_gmem0:HBM24 +sp=perf_25.m_axi_gmem0:HBM25 +sp=perf_26.m_axi_gmem0:HBM26 +sp=perf_27.m_axi_gmem0:HBM27 +sp=perf_28.m_axi_gmem0:HBM28 +sp=perf_29.m_axi_gmem0:HBM29 +sp=perf_30.m_axi_gmem0:HBM30 +sp=perf_31.m_axi_gmem0:HBM31 +sp=perf_32.m_axi_gmem0:HBM32 +sp=perf_33.m_axi_gmem0:HBM33 +sp=perf_34.m_axi_gmem0:HBM34 +sp=perf_35.m_axi_gmem0:HBM35 +sp=perf_36.m_axi_gmem0:HBM36 +sp=perf_37.m_axi_gmem0:HBM37 +sp=perf_38.m_axi_gmem0:HBM38 +sp=perf_39.m_axi_gmem0:HBM39 +sp=perf_40.m_axi_gmem0:HBM40 +sp=perf_41.m_axi_gmem0:HBM41 +sp=perf_42.m_axi_gmem0:HBM42 +sp=perf_43.m_axi_gmem0:HBM43 +sp=perf_44.m_axi_gmem0:HBM44 +sp=perf_45.m_axi_gmem0:HBM45 +sp=perf_46.m_axi_gmem0:HBM46 +sp=perf_47.m_axi_gmem0:HBM47 +sp=perf_48.m_axi_gmem0:HBM48 +sp=perf_49.m_axi_gmem0:HBM49 +sp=perf_50.m_axi_gmem0:HBM50 +sp=perf_51.m_axi_gmem0:HBM51 +sp=perf_52.m_axi_gmem0:HBM52 +sp=perf_53.m_axi_gmem0:HBM53 +sp=perf_54.m_axi_gmem0:HBM54 +sp=perf_55.m_axi_gmem0:HBM55 +sp=perf_56.m_axi_gmem0:HBM56 +sp=perf_57.m_axi_gmem0:HBM57 +sp=perf_58.m_axi_gmem0:HBM58 +sp=perf_59.m_axi_gmem0:HBM59 +sp=perf_60.m_axi_gmem0:HBM60 +sp=perf_61.m_axi_gmem0:HBM61 +sp=perf_62.m_axi_gmem0:HBM62 +sp=perf_63.m_axi_gmem0:HBM63 + +sp=perf_64.m_axi_gmem0:MEM +sp=perf_65.m_axi_gmem0:MEM +sp=perf_66.m_axi_gmem0:MEM +sp=perf_67.m_axi_gmem0:MEM +sp=perf_68.m_axi_gmem0:MEM +sp=perf_69.m_axi_gmem0:MEM +sp=perf_70.m_axi_gmem0:MEM +sp=perf_71.m_axi_gmem0:MEM + +sp=perf_72.m_axi_gmem0:DDR0 +sp=perf_73.m_axi_gmem0:DDR1 +sp=perf_74.m_axi_gmem0:DDR2 +sp=perf_75.m_axi_gmem0:DDR3 diff --git a/examples/05_perf/hls/build.tcl b/examples/05_perf/hls/build.tcl deleted file mode 100644 index e418e72b..00000000 --- a/examples/05_perf/hls/build.tcl +++ /dev/null @@ -1,78 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -set command [lindex $argv 0] -set device [lindex $argv 1] -set ipname [lindex $argv 2] - -set do_sim 0 -set do_syn 0 -set do_export 0 -set do_cosim 0 - -switch $command { - "sim" { - set do_sim 1 - } - "syn" { - set do_syn 1 - } - "ip" { - set do_syn 1 - set do_export 1 - } - "cosim" { - set do_syn 1 - set do_cosim 1 - } - "all" { - set do_sim 1 - set do_syn 1 - set do_export 1 - set do_cosim 1 - } - default { - puts "Unrecognized command" - exit - } -} - - -open_project build_${ipname}.${device} -file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp -add_files $ipname.cpp -cflags "-std=c++14" - -set_top $ipname - -open_solution sol1 - -if {$do_syn} { - set_part $device - create_clock -period 3.33 -name default - config_interface -m_axi_addr64=true - csynth_design -} - -if {$do_export} { - config_export -format ip_catalog - export_design -} - -exit \ No newline at end of file diff --git a/examples/05_perf/hls/perf.cfg b/examples/05_perf/hls/perf.cfg new file mode 100644 index 00000000..71b86b13 --- /dev/null +++ b/examples/05_perf/hls/perf.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=perf +syn.file=perf.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/05_perf/hls/perf.cpp b/examples/05_perf/hls/perf.cpp index dcf2cc93..f9e06f70 100644 --- a/examples/05_perf/hls/perf.cpp +++ b/examples/05_perf/hls/perf.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -19,14 +19,36 @@ */ #include +#include -void perf(ap_uint<32> n, ap_uint<512>* out_mem) { - #pragma hls interface mode=s_axilite port=n - #pragma hls interface mode=s_axilite port=return - #pragma hls interface m_axi bundle=gmem0 port=out_mem max_widen_bitwidth=64 - for (int i = 0; i < n; i++) { - #pragma HLS unroll factor=2 - #pragma HLS pipeline - out_mem[i] = i; +#define DATA_WIDTH 256 +typedef ap_uint uint256_t; +#define LENGTH 0x1000000 + +extern "C" void perf( + uint256_t* hbm_ptr, + ap_uint<32> wr, + ap_uint<32>& out_acc +) { +#pragma HLS INTERFACE m_axi port=hbm_ptr offset=slave bundle=gmem0 max_read_burst_length=64 max_write_burst_length=64 depth=536870912 +#pragma HLS INTERFACE s_axilite port=hbm_ptr bundle=control +#pragma HLS INTERFACE s_axilite port=wr bundle=control +#pragma HLS INTERFACE s_axilite port=out_acc bundle=control +#pragma HLS INTERFACE s_axilite port=return bundle=control + + ap_uint<32> acc = 0; + if (wr == 0) { + for (uint32_t i = 0; i < LENGTH; i++) { + #pragma HLS PIPELINE II=1 + hbm_ptr[i] = i; + } + } else { + for (uint32_t i = 0; i < LENGTH; i++) { + #pragma HLS PIPELINE II=1 + uint256_t val = hbm_ptr[i]; + acc ^= val.range(31, 0); + } + out_acc = acc; } -} \ No newline at end of file +} + diff --git a/submodules/v80-vitis-flow/src/main.cpp b/examples/06_dcmac/06_dcmac.cpp similarity index 53% rename from submodules/v80-vitis-flow/src/main.cpp rename to examples/06_dcmac/06_dcmac.cpp index 39cf851c..3f3ae0f2 100644 --- a/submodules/v80-vitis-flow/src/main.cpp +++ b/examples/06_dcmac/06_dcmac.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -19,29 +19,33 @@ */ #include +#include -#include "arg_parser.hpp" -#include "bd_builder.hpp" -#include "emulator.hpp" -#include "xml_parser.hpp" -int main(int argc, char** argv) { - try { - utils::Logger::setOutput("v80++-linker.log"); - ArgParser parser(argc, argv); - auto plat = parser.getPlatform(); - - BdBuilder builder(parser.getKernels(), parser.getConnections(), parser.getFreqHz(), - parser.isSegmented(), plat, parser.getTclInjections()); - builder.buildBlockDesign(); +#include +#include +#include - if (plat == Platform::EMULATOR) { - Emulator emulator(parser.getKernelPaths(), parser.getKernels(), - parser.getConnections()); - emulator.print(); +int main(int argc, char* argv[]) { + try { + if (argc < 3) { + std::cerr << "Usage: " << argv[0] << " " << std::endl; + return 1; } + std::string bdf = argv[1]; + std::string vrtbinFile = argv[2]; + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::DEBUG); + uint32_t size = 1024; - } catch (std::exception& e) { - std::cout << "Exception: " << e.what() << std::endl; + vrt::Device device(bdf, vrtbinFile); + vrt::Kernel traffic_producer_0(device, "traffic_producer_0"); + vrt::Kernel traffic_producer_1(device, "traffic_producer_1"); + traffic_producer_0.start(100, 0); + traffic_producer_0.wait(); + traffic_producer_1.start(100, 1); + traffic_producer_1.wait(); + device.cleanup(); + } catch (std::exception const& e) { + std::cerr << "Exception: " << e.what() << std::endl; + return 1; } - return 0; } \ No newline at end of file diff --git a/examples/06_dcmac/CMakeLists.txt b/examples/06_dcmac/CMakeLists.txt new file mode 100644 index 00000000..8d145e95 --- /dev/null +++ b/examples/06_dcmac/CMakeLists.txt @@ -0,0 +1,64 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.20) +project(06_dcmac LANGUAGES CXX) + +set(CMAKE_CXX_STANDARD 20) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +option(SLASH_USE_REPO "Build against the local repo tree instead of installed packages" OFF) + +if(SLASH_USE_REPO) + get_filename_component(REPO_ROOT "${CMAKE_CURRENT_LIST_DIR}/../.." REALPATH) + list(APPEND CMAKE_MODULE_PATH "${REPO_ROOT}/cmake") + include(SlashTools) + add_subdirectory(${REPO_ROOT}/vrt ${CMAKE_CURRENT_BINARY_DIR}/vrt) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt) +else() + find_package(SlashTools REQUIRED) + find_package(vrt REQUIRED CONFIG) + set(_VRT_INCLUDES "") + set(_VRT_LIBS vrt::vrt) +endif() + +# --- HLS kernels --- +set(DEVICE "xcv80-lsva4737-2MHP-e-S" CACHE STRING "Target device") + +build_hls_dir( + TARGET hls + ROOT "${CMAKE_CURRENT_SOURCE_DIR}/hls" + DEVICE "${DEVICE}" + KERNELS traffic_producer traffic_consumer + OUT_KERNELS _KERNELS +) + +# --- VBIN targets --- +set(CFG_FILE "${CMAKE_CURRENT_SOURCE_DIR}/config.cfg") + +add_vbin(TARGET "dcmac_hw" PLATFORM "hw" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "dcmac_sim" PLATFORM "sim" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) +add_vbin(TARGET "dcmac_emu" PLATFORM "emu" CFG "${CFG_FILE}" KERNELS ${_KERNELS}) + +# --- Executable --- +add_executable(${PROJECT_NAME} 06_dcmac.cpp) +target_include_directories(${PROJECT_NAME} PRIVATE ${_VRT_INCLUDES}) +target_link_libraries(${PROJECT_NAME} PRIVATE ${_VRT_LIBS}) diff --git a/examples/01_aximm/hls/Makefile b/examples/06_dcmac/config.cfg similarity index 74% rename from examples/01_aximm/hls/Makefile rename to examples/06_dcmac/config.cfg index c6c72c4f..bb6d90df 100644 --- a/examples/01_aximm/hls/Makefile +++ b/examples/06_dcmac/config.cfg @@ -18,23 +18,16 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -TARGET=ip -DEVICE=xcv80-lsva4737-2MHP-e-S +[network] +eth_0=1 +eth_2=1 -DMA_BUILD_DIR=build_dma.$(DEVICE) -OFFSET_BUILD_DIR=build_offset.$(DEVICE) +[connectivity] +nk=traffic_producer:2:traffic_producer_0.traffic_producer_1 +nk=traffic_consumer:2:traffic_consumer_0.traffic_consumer_1 -all: $(DMA_BUILD_DIR) $(OFFSET_BUILD_DIR) +stream_connect=traffic_producer_0.axis_out:eth_0.tx0 +stream_connect=traffic_producer_1.axis_out:eth_2.tx0 -$(DMA_BUILD_DIR): - if [ ! -d "$(DMA_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) dma; \ - fi - -$(OFFSET_BUILD_DIR): - if [ ! -d "$(OFFSET_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) offset; \ - fi - -clean: - rm -rf $(DMA_BUILD_DIR) $(OFFSET_BUILD_DIR) vitis_hls.log \ No newline at end of file +stream_connect=eth_0.rx0:traffic_consumer_0.axis_in +stream_connect=eth_2.rx0:traffic_consumer_1.axis_in \ No newline at end of file diff --git a/examples/06_dcmac/hls/traffic_consumer.cfg b/examples/06_dcmac/hls/traffic_consumer.cfg new file mode 100644 index 00000000..a4a04e1e --- /dev/null +++ b/examples/06_dcmac/hls/traffic_consumer.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=traffic_consumer +syn.file=traffic_consumer.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/submodules/v80-vitis-flow/src/sw_emu/zmq_client.cpp b/examples/06_dcmac/hls/traffic_consumer.cpp similarity index 59% rename from submodules/v80-vitis-flow/src/sw_emu/zmq_client.cpp rename to examples/06_dcmac/hls/traffic_consumer.cpp index e6e0b27e..706a1a02 100644 --- a/submodules/v80-vitis-flow/src/sw_emu/zmq_client.cpp +++ b/examples/06_dcmac/hls/traffic_consumer.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,25 +18,31 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "zmq_client.hpp" +#include "ap_axi_sdata.h" +#include "ap_int.h" +#include "hls_stream.h" -ZmqClient::ZmqClient() : context(1), socket(context, ZMQ_PAIR) {} +#define DWIDTH 512 +#define TDWIDTH 3 -ZmqClient::~ZmqClient() { - socket.close(); - context.close(); -} +typedef ap_axiu pkt; -void ZmqClient::connect(const std::string& address) { socket.connect(address); } +void traffic_consumer(hls::stream &axis_in, + ap_uint<32> &rx_flits) +{ +#pragma HLS INTERFACE mode=axis port=axis_in depth=16 +#pragma HLS INTERFACE mode=s_axilite port=rx_flits bundle=control +#pragma HLS INTERFACE ap_ctrl_none port=return -std::string ZmqClient::recv() { - zmq::message_t message; - socket.recv(message, zmq::recv_flags::none); - return std::string(static_cast(message.data()), message.size()); -} + ap_uint<32> rx = 0; + rx_flits = 0; -void ZmqClient::ack(const std::string& ackMessage) { - zmq::message_t message(ackMessage.size()); - memcpy(message.data(), ackMessage.data(), ackMessage.size()); - socket.send(message, zmq::send_flags::none); -} \ No newline at end of file + while (1) { +#pragma HLS PIPELINE II=1 + if (!axis_in.empty()) { + (void)axis_in.read(); // consume one beat + rx++; + rx_flits = rx; // readable via AXI-Lite + } + } +} diff --git a/examples/06_dcmac/hls/traffic_producer.cfg b/examples/06_dcmac/hls/traffic_producer.cfg new file mode 100644 index 00000000..52b0a43d --- /dev/null +++ b/examples/06_dcmac/hls/traffic_producer.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=traffic_producer +syn.file=traffic_producer.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/examples/06_dcmac/hls/traffic_producer.cpp b/examples/06_dcmac/hls/traffic_producer.cpp new file mode 100644 index 00000000..2f81dd8d --- /dev/null +++ b/examples/06_dcmac/hls/traffic_producer.cpp @@ -0,0 +1,35 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +#include "ap_axi_sdata.h" +#include "ap_int.h" +#include "hls_stream.h" + +#define DWIDTH 512 +#define TDWIDTH 3 + +typedef ap_axiu pkt; + +void traffic_producer(hls::stream &axis_out, + ap_uint<32> flits, + ap_uint dest){ + +#pragma HLS INTERFACE mode=axis port=axis_out depth=16 +#pragma HLS INTERFACE mode=s_axilite port=dest bundle=control +#pragma HLS INTERFACE mode=s_axilite port=flits bundle=control +#pragma HLS INTERFACE mode=s_axilite port=return bundle=control + + pkt axi_word; +generator: + for(unsigned int i=0; i< flits; i++){ + #pragma HLS PIPELINE II=1 + for(unsigned int j=0; j_hw`: Link a hardware vrtbin for the specified project. +- `_emu`: Link an emulation vrtbin for the specified project. +- `_sim`: Link a simulation vrtbin for the specified project. +- ``: Build the runtime application (e.g. `00_axilite`). ### Example usage +```bash +cd examples/00_axilite + +# Configure (use -DSLASH_USE_REPO=ON when building against the local repo tree) +cmake -B build -S . -G Ninja -DSLASH_USE_REPO=ON + +# Build the application +cmake --build build + +# Build FPGA artefacts (requires Vivado/Vitis) +cmake --build build --target hls # compile HLS kernels +cmake --build build --target axilite_hw # link hardware vrtbin +cmake --build build --target axilite_emu # link emulation vrtbin +cmake --build build --target axilite_sim # link simulation vrtbin ``` -cd 0x_/ -make _all -``` -where recipe can be `hw`, `emu` or `sim`. -In order to run an example, navigate to the build directory and an executable named `0x_` will be found. +The vrtbin files and the application executable are placed in the `build/` directory. ## How to run -The following environment variable needs to be set prior to running any examples: +The following environment variables need to be set prior to building or running any examples: +```bash +source /settings64.sh +source /settings64.sh ``` -mkdir -p /home//.ami -export AMI_HOME="/home//.ami" -source -source -``` -To make the changes persistent, add the commands to .bashrc. Sourcing the Vivado scripts are needed for the hardware builds, whereas vitis is needed for emulation. -In order to run one of the built examples, one must identify the BDF for the V80 and input it into the code. +To make the changes persistent, add the commands to `.bashrc`. Sourcing the Vivado scripts is needed for the hardware builds, whereas Vitis HLS is needed for emulation. + +In order to run one of the built examples, one must identify the BDF for the V80: ``` v80-smi list -------------------------------------------------------------------- -Listing V80 devices +Listing V80 devices -------------------------------------------------------------------- V80 device found with BDF: 0000:e2:00.0 -------------------------------------------------------------------- @@ -67,4 +69,4 @@ V80 device found with BDF: 0000:21:00.0 -------------------------------------------------------------------- ``` -To run the example, navigate to the `build` directory, and you will find an executable, called `0x_`. The format for running is `0x_ `. +To run the example, navigate to the `build` directory. The format for running is `0x_ `. diff --git a/linker/.gitignore b/linker/.gitignore new file mode 100644 index 00000000..28d1e7e6 --- /dev/null +++ b/linker/.gitignore @@ -0,0 +1,4 @@ +__pycache__/ +*.egg-info/ +dist/ +build/ diff --git a/linker/pyproject.toml b/linker/pyproject.toml new file mode 100644 index 00000000..1eb0d940 --- /dev/null +++ b/linker/pyproject.toml @@ -0,0 +1,21 @@ +[build-system] +requires = ["setuptools>=68.0"] +build-backend = "setuptools.build_meta" + +[project] +name = "slashkit" +version = "0.1.0" +description = "Utility to link VRT binaries (VBINs) from user IP cores" +license = "MIT" +requires-python = ">=3.9" +dependencies = ["jinja2>=2.11.3"] + +[project.scripts] +"slashkit" = "slashkit.__main__:main" + +[tool.setuptools.packages.find] +include = ["slashkit*"] +exclude = ["test*"] + +[tool.setuptools.package-data] +"slashkit" = ["resources/**/*"] diff --git a/linker/pytest.ini b/linker/pytest.ini new file mode 100644 index 00000000..f6a0dc44 --- /dev/null +++ b/linker/pytest.ini @@ -0,0 +1,4 @@ +[pytest] +testpaths = test +pythonpath = . +addopts = "--cov=slashkit" "--cov=test" \ No newline at end of file diff --git a/linker/slashkit/__main__.py b/linker/slashkit/__main__.py new file mode 100644 index 00000000..c4319774 --- /dev/null +++ b/linker/slashkit/__main__.py @@ -0,0 +1,186 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +import argparse +import logging +import os +import threading +import time + +from slashkit.emit.hw.tcl_gen import generate_tcl +from slashkit.emit.hw.project_gen import ( + build_service_layer_rm, + build_slash_rm, + generate_util_report, + install_static_shell, +) +from slashkit.emit.sim.tcl_gen import generate_sim_tcl +from slashkit.emit.emu.tcl_gen import generate_emu_tcl +from slashkit.emit.sim.project_gen import create_sim_project, build_sim_project +from slashkit.emit.emu.project_gen import build_emu_project, package_emu_artifacts + +from slashkit.emit.metadata.prog_image import build_vbin +from slashkit.core.command_config import LinkerConfiguration, Platform, InstallerConfiguration, CommandConfiguration + + +def _format_duration(seconds: float) -> str: + total = int(round(seconds)) + hours = total // 3600 + minutes = (total % 3600) // 60 + secs = total % 60 + return f"{hours:02d}:{minutes:02d}:{secs:02d}" + + +def profiled(func) -> None: + return lambda: run_with_profiling(func.__name__, func) + + +def run_with_profiling(label: str, func) -> None: + start_wall = time.perf_counter() + start_cpu = time.process_time() + start_rusage = None + cores = os.cpu_count() or 1 + peak_cpu_pct = None + stop_event = threading.Event() + + def _sample_cpu_peak() -> None: + nonlocal peak_cpu_pct + last_wall = time.perf_counter() + last_cpu = time.process_time() + while not stop_event.wait(0.2): + now_wall = time.perf_counter() + now_cpu = time.process_time() + delta_wall = now_wall - last_wall + if delta_wall > 0: + delta_cpu = now_cpu - last_cpu + cpu_pct = (delta_cpu / delta_wall) * 100.0 + if peak_cpu_pct is None or cpu_pct > peak_cpu_pct: + peak_cpu_pct = cpu_pct + last_wall = now_wall + last_cpu = now_cpu + + try: + import resource + start_rusage = resource.getrusage(resource.RUSAGE_SELF) + except Exception: + start_rusage = None + + sampler = threading.Thread(target=_sample_cpu_peak, daemon=True) + sampler.start() + try: + func() + finally: + stop_event.set() + sampler.join(timeout=1.0) + end_wall = time.perf_counter() + end_cpu = time.process_time() + cpu_str = _format_duration(end_cpu - start_cpu) + wall_str = _format_duration(end_wall - start_wall) + avg_cpu_pct = 0.0 + elapsed = end_wall - start_wall + if elapsed > 0: + avg_cpu_pct = ((end_cpu - start_cpu) / elapsed) * 100.0 + rss_part = "" + if start_rusage is not None: + try: + import resource + end_rusage = resource.getrusage(resource.RUSAGE_SELF) + # ru_maxrss is in kilobytes on Linux; convert to MB. + rss_mb = end_rusage.ru_maxrss / 1024.0 + rss_part = f" ; max_rss = {rss_mb:.1f} MB" + except Exception: + rss_part = "" + peak_part = "" + if peak_cpu_pct is not None: + peak_part = f" ; cpu_peak_pct = {peak_cpu_pct:.1f}" + print( + f"{label}: Time (s): cpu = {cpu_str} ; elapsed = {wall_str}" + f" ; cpu_avg_pct = {avg_cpu_pct:.1f}{peak_part} ; cores = {cores}{rss_part}" + ) + + +def link(config: LinkerConfiguration) -> None: + if config.platform == Platform.SIMULATION: + generate_sim_tcl(config) + elif config.platform == Platform.EMULATION: + generate_emu_tcl(config) + else: + generate_tcl(config) + + if config.platform == Platform.SIMULATION: + create_sim_project(config) + build_sim_project(config) + elif config.platform == Platform.EMULATION: + build_emu_project(config) + else: + run_with_profiling("build_slash", lambda: build_slash_rm(config)) + # Only build a service layer if ethernet is enabled + # Will be changed once more service layers become available + if config.networking_enabled: + run_with_profiling("build_service_layer", + lambda: build_service_layer_rm(config)) + + if config.platform == Platform.SIMULATION: + pass + elif config.platform == Platform.EMULATION: + package_emu_artifacts(config) + else: + generate_util_report(config) + build_vbin(config) + + +MAIN_HELP_EPILOG = """ +Typical Workflow: + Most users will use the 'link' subcommand to link kernel IP cores into + an emulation, simulation, or hardware build image. + + The 'install' subcommand is only used during the installation of the linker. + It prepares an static shell definition, which is later used by the 'link' + subcommand to create hardware images. +""" + + +def main(): + logging.basicConfig( + level=logging.INFO, + format="%(asctime)s %(levelname)s %(name)s:%(funcName)s: %(message)s", + ) + + ap = argparse.ArgumentParser(description="Utility to link VRT binaries (VBINs) from user IP cores.", conflict_handler="resolve", epilog=MAIN_HELP_EPILOG, + formatter_class=argparse.RawDescriptionHelpFormatter) + sub_parsers = ap.add_subparsers(required=True) + + link_parser = sub_parsers.add_parser("link") + LinkerConfiguration.populate_argument_parser(link_parser) + link_parser.set_defaults(config_class=LinkerConfiguration, operation=link) + + install_parser = sub_parsers.add_parser("install") + InstallerConfiguration.populate_argument_parser(install_parser) + install_parser.set_defaults( + config_class=InstallerConfiguration, operation=install_static_shell) + + args = ap.parse_args() + + config = args.config_class(args) + args.operation(config) + + +if __name__ == "__main__": + main() diff --git a/linker/slashkit/command_config.py b/linker/slashkit/command_config.py new file mode 100644 index 00000000..cbd4ad7d --- /dev/null +++ b/linker/slashkit/command_config.py @@ -0,0 +1,403 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## +from enum import Enum +from pathlib import Path +from typing import Dict, List, Optional +import re +import os +import shutil +import argparse +import sys +import importlib.resources as resources + +from slashkit.core.bd_ports import load_bd_ports_from_file, BlockDesignPorts +from slashkit.core.kernel import Kernel, KernelInstance +from slashkit.core.connectivity import ConnectivityConfig +from slashkit.parser.config_parser import parse_connectivity_file, apply_config_to_instances +from slashkit.parser.component_parser import parse_component_xml + + +class Platform(Enum): + HARDWARE = "hw" + SIMULATION = "sim" + EMULATION = "emu" + + +def _find_vitis_include() -> Path: + env_candidates = [ + os.environ.get("XILINX_VITIS"), + os.environ.get("VITIS_HOME"), + os.environ.get("VITIS"), + ] + for base in env_candidates: + if not base: + continue + cand = Path(base) / "include" + if cand.exists(): + return cand + + vitis_bin = shutil.which("vitis") + if vitis_bin: + return Path(vitis_bin).resolve().parents[1] / "include" + + raise FileNotFoundError( + "Could not locate Vitis include path. Set XILINX_VITIS/VITIS_HOME " + "or ensure 'vitis' is on PATH." + ) + + +class CommandConfiguration(object): + @classmethod + def populate_argument_parser(cls, ap: argparse.ArgumentParser): + ap.formatter_class = argparse.RawTextHelpFormatter + ap.add_argument("--vivado", required=False, type=Path, default=None, + help="Vivado binary to use for linking. If not given, it will be derived from PATH.") + ap.add_argument("--jobs", required=False, type=int, default=8, + help="Number of parallel jobs for Vivado runs.") + + def __init__(self, args: argparse.Namespace): + self._args = args + + # Resolve, if necessary find, and verify the Vivado binary + self._vivado_bin: Path = args.vivado if args.vivado is not None else Path( + shutil.which("vivado")) + self._vivado_bin = self._vivado_bin.expanduser().resolve() + if not self._vivado_bin.is_file(): + raise FileNotFoundError(self._vivado_bin) + + # Misc. arguments + self._n_jobs: int = args.jobs + + @property + def input_arguments(self) -> argparse.Namespace: + return self._args + + @property + def project_name(self) -> str: + raise NotImplementedError() + + @property + def build_dir(self) -> Path: + raise NotImplementedError() + + @property + def ip_repository(self) -> Path: + return self.build_dir / "iprepo" + + @property + def vivado_bin(self) -> Path: + return self._vivado_bin + + @property + def n_jobs(self) -> int: + return self._n_jobs + + +LINK_HELP_EPILOG = f""" +Typical Workflow: + 1. Create a connectivity configuration file (--config) defining kernel + instances and their connections + 2. Specify one or more kernel IP cores via IP-XACT component.xml files (--kernels) + 3. Run the linker to produce a VBIN archive (--out) + 4. The VBIN archive contains all metadata and artifacts needed to execute + the design on the target platform + +Connectivity Configuration Format: + The configuration file uses an INI-like format with the following sections: + + [connectivity] - Define kernel instances and connections + nk=:[:] + Example: nk=vadd:2:vadd_0.vadd_1 + Creates instances of . Names are auto-generated if omitted. + + stream_connect=.:. + Examples: + stream_connect=dma_in_0.axis_out:passthrough_0.axis_in + stream_connect=traffic_producer_0.axis_out:eth_0.tx0 + Connects AXI-Stream ports between kernel instances and/or ethernet ports. + + sp=.: + Example: sp=vadd_0.m_axi_gmem0:HBM0 + Maps AXI4-Full memory ports to memory banks (HBM0-31, DDR0-3, MEM, HOST). + + [clock] - Specify per-kernel clock frequencies (can be repeated) + krnl= + freqhz= + Example: krnl=vadd_0 + freqhz=400000000 + + [network] - Enable Ethernet interfaces + eth_=<0|1> + Example: eth_0=1 + + [user_region] - Custom TCL scripts + pre_synth= + Example: pre_synth=custom_constraints.tcl + + [debug] - Debug net visibility + net=. + Example: net=vadd_0.axis_out + + Lines starting with '#' or ';' are treated as comments. + +Platform Selection: + emu (emulation) - Fast software-based execution for functional testing + sim (simulation) - RTL simulation for detailed verification + hw (hardware) - Full FPGA bitstream generation for deployment + + WARNING: Hardware builds (-p hw) take significant time, ranging from + minutes to hours depending on design complexity and machine resources. + Use emulation for rapid development and testing. + +Example: + {sys.argv[0]} link -c config.cfg -k kernels/ip/accumulate/component.xml \\ + kernels/ip/increment/component.xml -o accelerator.vbin -p hw + +Build Artifacts: + A project directory (.prj) will be created alongside the output + VBIN archive, containing TCL scripts, Vivado projects, and build logs. +""" + + +class LinkerConfiguration(CommandConfiguration): + + @classmethod + def populate_argument_parser(cls, ap: argparse.ArgumentParser): + super().populate_argument_parser(ap) + ap.description = "Link kernel IP cores into a complete design and build a VBIN archive for emulation, simulation, or hardware execution." + ap.epilog = LINK_HELP_EPILOG + ap.add_argument("-c", "--config", required=True, type=Path, + help="Path to the connectivity configuration file (e.g. config.cfg).") + ap.add_argument("-k", "--kernels", required=True, type=Path, nargs="+", + help="List of component.xml files to load as kernel IP cores.") + ap.add_argument("-o", "--out", required=True, type=Path, + help="Path to the final VBIN archive.") + ap.add_argument("-p", "--platform", choices=["emu", "sim", "hw"], + default="emu", help="Target platform (hw, sim, or emu). Default: emu") + ap.add_argument("--pre-synth-tcls", type=Path, nargs="*", default=[], + help="Paths to TCL scripts to run before synthesis (applies to hardware builds only).") + ap.add_argument("--clock-hz", required=False, + type=int, default=None, help="Target clock frequency in MHz.") + + def __init__(self, args: argparse.Namespace): + super().__init__(args) + + # ============ + # Set up paths + # ============ + + # Resolve and verify the configuration file + configuration_file = args.config.expanduser().resolve() + if not configuration_file.is_file(): + raise FileNotFoundError(configuration_file) + + # Resolve and verify the kernel component files + self._kernel_component_paths: List[Path] = [ + path.expanduser().resolve() for path in args.kernels] + for kernel in self._kernel_component_paths: + if not kernel.is_file(): + raise FileNotFoundError(kernel) + + # Resolve the out path and remove the old output if necessary + self._out_path: Path = args.out.expanduser().resolve() + if self._out_path.is_file(): + self._out_path.unlink() + + # Resolve the build directory, clean up if necessary, and prepare it + self._build_dir: Path = self._out_path.with_name( + f"{self._out_path.name}.prj") + if self._build_dir.is_dir(): + shutil.rmtree(self._build_dir) + if self._build_dir.is_file(): + self._build_dir.unlink() + self._build_dir.mkdir(parents=True) + + # Resolve and verify pre-synthesis TCLs (if any) + self._pre_synth_tcls: List[Path] = [] + for path in args.pre_synth_tcls: + path: Path = path.expanduser().resolve() + if not path.is_file(): + raise FileNotFoundError(path) + self._pre_synth_tcls.append(path) + + # Misc. arguments + self._platform = Platform(args.platform) + self._clock_hz: int = args.clock_hz + + # Sanitize the output file stem as the project name + s2 = re.sub(r"[^A-Za-z0-9_]+", "_", str(self._out_path.stem).strip()) + if not s2: + s2 = "proj" + if s2[0].isdigit(): + s2 = "_" + s2 + self._project_name: str = s2 + + # Resolve the Vitis include directory + self._vitis_include_dir = _find_vitis_include() + + # ======================= + # Argument interpretation + # ======================= + with resources.path("slashkit.resources", "bd_ports.txt") as bd_ports_path: + self._bd_ports: BlockDesignPorts = load_bd_ports_from_file( + bd_ports_path) + + self._kernels: List[Kernel] = [parse_component_xml( + kfile) for kfile in self.kernel_component_paths] + + self._configuration: ConnectivityConfig = parse_connectivity_file( + configuration_file) + self._kernel_instances: List[KernelInstance] = apply_config_to_instances( + self.configuration, self.kernels) + + @property + def block_design_ports(self) -> BlockDesignPorts: + return self._bd_ports + + @property + def configuration(self) -> ConnectivityConfig: + return self._configuration + + @property + def networking_enabled(self) -> bool: + # TODO: Change to some sort of description for different service layers once available. + return len(self.configuration.net.enabled_eth) > 0 + + @property + def out_path(self) -> Path: + return self._out_path + + @property + def platform(self) -> Platform: + return self._platform + + @property + def project_name(self) -> str: + return self._project_name + + @property + def kernel_component_paths(self) -> List[Path]: + return self._kernel_component_paths + + @property + def kernels(self) -> List[Kernel]: + return self._kernels + + @property + def kernel_instances(self) -> Dict[str, KernelInstance]: + return self._kernel_instances + + @property + def build_dir(self) -> Path: + return self._build_dir + + @property + def vitis_include_dir(self) -> Path: + return self._vitis_include_dir + + @property + def pre_synth_tcls(self) -> List[Path]: + return self._pre_synth_tcls + + @property + def clock_hz(self) -> Optional[int]: + return self._clock_hz + + +INSTALL_HELP_EPILOG = f""" +Purpose: + The 'install' subcommand builds the static shell required for + hardware builds. This is a one-time setup operation that creates base images + used by the 'link' subcommand when targeting hardware (-p hw). + +When to Use: + - During initial installation and/or packaging of slashkit + - When the static shell definition needs to be regenerated + + Most users will NOT need to run this command regularly. It is only required + during linker installation/setup. + +What It Does: + 1. Builds the static shell base images from the resource directory + 2. Generates necessary Vivado synthesis artifacts + 3. Creates reusable partial designs for hardware linking + + WARNING: This operation involves full Vivado synthesis and implementation, + which takes significant time (multiple hours depending on the system). + +Build Artifacts: + The build directory (--build-dir) will contain Vivado projects, checkpoints, + and logs. This directory can be removed after successful installation. + +Example: + {sys.argv[0]} install --build-dir ./install.prj --jobs 16 --out-dir linker/slashkit/resources +""" + + +class InstallerConfiguration(CommandConfiguration): + @classmethod + def populate_argument_parser(cls, ap: argparse.ArgumentParser): + super().populate_argument_parser(ap) + ap.description = "Build and install base images for hardware builds." + ap.epilog = INSTALL_HELP_EPILOG + ap.add_argument("--build-dir", required=False, type=Path, default=Path( + "./install.prj"), help="The build directory for the installer. Default: ./install_prj") + ap.add_argument("--aved-repo", required=False, type=str, default="https://github.com/Xilinx/AVED.git", + help="The AVED git repository to check out. Default: https://github.com/Xilinx/AVED.git") + ap.add_argument("--aved-ref", required=False, type=str, default="amd_v80_gen5x8_25.1_xbtest_20251113", + help="The AVED git ref to check out. Default: amd_v80_gen5x8_25.1_xbtest_20251113") + ap.add_argument("--out-dir", required=True, type=Path, + help="The resource directory to install the artifacts to. " + + "If you have checked out the SLASH repository, this would be linker/slashkit/resources") + + def __init__(self, args: argparse.Namespace): + super().__init__(args) + + self._build_dir: Path = args.build_dir.expanduser().resolve() + if self._build_dir.is_dir(): + shutil.rmtree(self._build_dir) + self._build_dir.mkdir(parents=True) + + self._aved_repo: str = args.aved_repo + self._aved_ref: str = args.aved_ref + + self._out_dir: Path = args.out_dir.expanduser().resolve() + if not self._out_dir.is_dir(): + raise FileNotFoundError(self._out_dir) + + @property + def project_name(self) -> str: + return "slash_install" + + @property + def build_dir(self) -> Path: + return self._build_dir + + @property + def aved_repo(self) -> str: + return self._aved_repo + + @property + def aved_ref(self) -> str: + return self._aved_ref + + @property + def out_dir(self) -> Path: + return self._out_dir diff --git a/submodules/v80-vitis-flow/iprepo/.gitkeep b/linker/slashkit/core/__init__.py similarity index 100% rename from submodules/v80-vitis-flow/iprepo/.gitkeep rename to linker/slashkit/core/__init__.py diff --git a/linker/slashkit/core/bd_ports.py b/linker/slashkit/core/bd_ports.py new file mode 100644 index 00000000..310c8fe2 --- /dev/null +++ b/linker/slashkit/core/bd_ports.py @@ -0,0 +1,300 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from dataclasses import dataclass, field +from typing import Dict, Iterable, Optional, List, Tuple +import re + +from slashkit.core.port import BusType + + +# ----------------------------- +# Data classes +# ----------------------------- + +@dataclass(frozen=True) +class BdPort: + """ + A top-level Block Design port / shell endpoint. + + Attributes: + name: Logical name used by your tool (e.g., "HBM0", "DDR0", "VIRT0", "MEM", "clock", "reset"). + ptype: BusType (AXI4FULL, AXILITE, AXIS, CLOCK, RESET, INTERRUPT). + rtl_name: Actual BD interface/pin name in Vivado (e.g., "HBM_AXI_00", "M00_INI", "VIRT_AXI_00", "ap_clk"). + width: Optional data width (AXI/AXIS). For CLOCK/RESET/INTERRUPT, this is forced to 1. + domain: Optional grouping, inferred from logical name for memory ports ("HBM", "DDR", "VIRT", "MEM"). + index: Optional index for memory groups (e.g., HBM0..63 → 0..63, DDR0..3 → 0..3, VIRT0..3 → 0..3). + For MEM lines, usually None (MEM acts as a multi-entry wildcard). + """ + name: str + ptype: BusType + rtl_name: Optional[str] = None + width: Optional[int] = None + domain: Optional[str] = None + index: Optional[int] = None + + +@dataclass +class BlockDesignPorts: + """ + Registry of BD ports with support for multiple RTL endpoints per logical name + (e.g., a single logical 'MEM' mapping to multiple vNOC INI ports). + """ + ports: Dict[str, List[BdPort]] = field(default_factory=dict) + + # ---- registration ---- + + def add(self, port: BdPort) -> None: + lst = self.ports.setdefault(port.name, []) + # Avoid exact duplicate RTL entry under the same logical name & type + if any(p.rtl_name == port.rtl_name and p.ptype == port.ptype for p in lst): + raise ValueError( + f"BD port '{port.name}' already has RTL '{port.rtl_name}' of type {port.ptype.name}." + ) + lst.append(port) + + def add_many(self, ports: Iterable[BdPort]) -> None: + for p in ports: + self.add(p) + + # ---- lookups ---- + + def get(self, name: str) -> BdPort: + """Return a single port for 'name'. Error if zero or more than one exist.""" + lst = self.ports.get(name, []) + if not lst: + raise KeyError(f"BD port '{name}' not found.") + if len(lst) > 1: + raise ValueError( + f"Multiple BD ports registered for '{name}'. Use get_all('{name}').") + return lst[0] + + def get_all(self, name: str) -> List[BdPort]: + """Return all ports for 'name' (useful for 'MEM').""" + lst = self.ports.get(name, []) + if not lst: + raise KeyError(f"BD port '{name}' not found.") + return lst + + def iter_type(self, ptype: BusType): + """Iterate all BdPort entries of a given type across all logical names.""" + for lst in self.ports.values(): + for p in lst: + if p.ptype == ptype: + yield p + + # ---- memory resolution ---- + + def mem_targets(self, domain: str, index: Optional[int] = None) -> List[BdPort]: + """ + Resolve memory target(s) to BdPort(s): + - ('HBM', i) -> [ 'HBM{i}' ] + - ('DDR', i) -> [ 'DDR{i}' ] + - ('VIRT', i) -> [ 'VIRT{i}' ] + - ('MEM', None) -> all 'MEM' entries (file order) + - ('MEM', i) -> the i-th 'MEM' entry (by file order) + """ + d = domain.upper() + if d in ("HBM", "DDR", "VIRT"): + if index is None: + raise ValueError(f"{d} requires an index.") + return [self.get(f"{d}{index}")] + if d == "MEM": + mems = self.get_all("MEM") + if index is None: + return mems + if not (0 <= index < len(mems)): + raise IndexError( + f"MEM index {index} out of range (0..{len(mems)-1}).") + return [mems[index]] + if d == "HOST": + # single logical endpoint named 'HOST' in bd_ports.txt + return [self.get("HOST")] + raise ValueError(f"Unknown memory domain '{domain}'.") + + def mem(self, domain: str, index: Optional[int]) -> BdPort: + """ + Back-compat convenience: return a single BdPort. + For MEM, you must pass an index; otherwise use mem_targets('MEM'). + """ + targets = self.mem_targets(domain, index) + if len(targets) != 1: + raise ValueError( + f"mem('{domain}', index={index}) resolved to {len(targets)} ports. " + f"Use mem_targets('{domain}', index) instead." + ) + return targets[0] + + +# ----------------------------- +# Loader from text file +# ----------------------------- + +_TYPE_MAP = { + "AXI4FULL": BusType.AXI4FULL, + "AXILITE": BusType.AXILITE, + "AXIS": BusType.AXIS, + "CLOCK": BusType.CLOCK, + "RESET": BusType.RESET, + "INTERRUPT": BusType.INTERRUPT, +} + +# HBM / DDR / VIRT with trailing index, e.g. HBM12, DDR3, VIRT2 +_RE_LOGICAL_MEM = re.compile(r"^(HBM|DDR|VIRT)(\d+)$", re.IGNORECASE) + + +def _parse_ptype(s: str) -> BusType: + try: + return _TYPE_MAP[s.strip().upper()] + except KeyError: + raise ValueError( + f"Unknown port type '{s}'. Expected one of {list(_TYPE_MAP)}.") + + +def _infer_domain_index(logical_name: str) -> Tuple[Optional[str], Optional[int]]: + """ + Best-effort inference from logical name: + HBM0..HBM63 -> ('HBM', 0..63) + DDR0..DDR3 -> ('DDR', 0..3) + VIRT0..VIRT3 -> ('VIRT', 0..3) + MEM -> ('MEM', None) + HOST -> ('HOST', None) + """ + ln = logical_name.strip() + if ln.upper() == "MEM": + return "MEM", None + if ln.upper() == "HOST": + return "HOST", None + m = _RE_LOGICAL_MEM.match(ln) + if m: + return m.group(1).upper(), int(m.group(2)) + return None, None + + +def _parse_width(s: Optional[str]) -> Optional[int]: + if not s: + return None + try: + return int(s, 0) # supports "32", "0x20" + except ValueError: + return None + + +def load_bd_ports_from_file(path: str) -> BlockDesignPorts: + """ + File format (one entry per line; comments with # or ; are ignored): + + : [width] + + Examples: + HBM0:HBM_AXI_00 AXI4FULL + DDR0:M00_INI AXI4FULL + VIRT0:VIRT_AXI_00 AXI4FULL + S_AXI_CTRL:S_AXI_CTRL AXILITE 32 + clock:ap_clk CLOCK + reset:ap_rst_n RESET + + # 'MEM' repeated N times (single logical, many RTL endpoints) + MEM:HBM_VNOC_INI_00 AXI4FULL + MEM:HBM_VNOC_INI_01 AXI4FULL + ... + MEM:HBM_VNOC_INI_07 AXI4FULL + """ + bd = BlockDesignPorts() + with open(path, "r", encoding="utf-8") as f: + for ln, raw in enumerate(f, start=1): + line = raw.strip() + if not line or line.startswith("#") or line.startswith(";"): + continue + + # Split ":" and " [width]" + try: + lhs, rhs = line.split(None, 1) + except ValueError: + raise ValueError( + f"{path}:{ln}: Expected ': [width]'. Got: {line!r}") + + if ":" not in lhs: + raise ValueError( + f"{path}:{ln}: Missing ':' in '{lhs}'. Expected ':'.") + + logical, rtl = [t.strip() for t in lhs.split(":", 1)] + parts = rhs.split() + if len(parts) not in (1, 2): + raise ValueError( + f"{path}:{ln}: Invalid RHS. Expected ' [width]'. Got: {rhs!r}") + + ptype = _parse_ptype(parts[0]) + width = _parse_width(parts[1]) if len(parts) == 2 else None + + # Force scalar width for these types + if ptype in (BusType.CLOCK, BusType.RESET, BusType.INTERRUPT): + width = 1 + + domain, index = _infer_domain_index(logical) + bd.add(BdPort( + name=logical, + ptype=ptype, + rtl_name=rtl, + width=width, + domain=domain, + index=index + )) + + return bd + + +# ----------------------------- +# Optional helpers +# ----------------------------- + +def generate_bd_port_lines( + num_hbm: int = 64, + num_ddr: int = 4, + num_mem_vnoc: int = 8, + num_virt: int = 4, +) -> List[str]: + """ + Utility to prefill a mapping file for common shells. + + Returns a list of lines ready to write to a file. Note that 'MEM' is + repeated num_mem_vnoc times with different RTL names, by design. + """ + lines: List[str] = [] + # HBM + for i in range(num_hbm): + lines.append(f"HBM{i}:HBM_AXI_{i:02d} AXI4FULL") + # DDR + for i in range(num_ddr): + lines.append(f"DDR{i}:M{i:02d}_INI AXI4FULL") + # VIRT + for i in range(num_virt): + lines.append(f"VIRT{i}:VIRT_AXI_{i:02d} AXI4FULL") + # Control + clocks/resets + lines += [ + "S_AXI_CTRL:S_AXI_CTRL AXILITE 32", + "clock:ap_clk CLOCK", + "reset:ap_rst_n RESET", + ] + # MEM (vNOC INI) + for i in range(num_mem_vnoc): + lines.append(f"MEM:HBM_VNOC_INI_{i:02d} AXI4FULL") + return lines diff --git a/linker/slashkit/core/bus.py b/linker/slashkit/core/bus.py new file mode 100644 index 00000000..dd3174c4 --- /dev/null +++ b/linker/slashkit/core/bus.py @@ -0,0 +1,68 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from dataclasses import dataclass, field +from typing import Dict, Optional + +from slashkit.core.port import BusType, Port + + +@dataclass(frozen=True) +class Bus: + """ + Represents a bus interface, including a logical->physical port map. + """ + name: str + ptype: BusType + width: Optional[int] = None + logical_to_physical: Dict[str, Port] = field(default_factory=dict) + + def __post_init__(self): + if self.ptype in {BusType.CLOCK, BusType.RESET, BusType.INTERRUPT}: + object.__setattr__(self, "width", 1) + + @property + def btype(self) -> BusType: + """Preferred IP-XACT terminology.""" + return self.ptype + + def physical_port(self, logical: Optional[str] = None) -> Optional[Port]: + """Return a physical Port object for the given logical port (or best default).""" + if not self.logical_to_physical: + return None + if logical: + return self.logical_to_physical.get(logical) + if len(self.logical_to_physical) == 1: + return next(iter(self.logical_to_physical.values())) + for key in ("CLK", "RESET", "RST", "INT", "IRQ"): + if key in self.logical_to_physical: + return self.logical_to_physical[key] + for _, val in self.logical_to_physical.items(): + return val + return None + + def physical_port_name(self, logical: Optional[str] = None) -> Optional[str]: + """Convenience wrapper to return only the physical port name.""" + p = self.physical_port(logical=logical) + return p.name if p is not None else None + + def __repr__(self) -> str: + return f"" diff --git a/linker/slashkit/core/command_config.py b/linker/slashkit/core/command_config.py new file mode 100644 index 00000000..cbd4ad7d --- /dev/null +++ b/linker/slashkit/core/command_config.py @@ -0,0 +1,403 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## +from enum import Enum +from pathlib import Path +from typing import Dict, List, Optional +import re +import os +import shutil +import argparse +import sys +import importlib.resources as resources + +from slashkit.core.bd_ports import load_bd_ports_from_file, BlockDesignPorts +from slashkit.core.kernel import Kernel, KernelInstance +from slashkit.core.connectivity import ConnectivityConfig +from slashkit.parser.config_parser import parse_connectivity_file, apply_config_to_instances +from slashkit.parser.component_parser import parse_component_xml + + +class Platform(Enum): + HARDWARE = "hw" + SIMULATION = "sim" + EMULATION = "emu" + + +def _find_vitis_include() -> Path: + env_candidates = [ + os.environ.get("XILINX_VITIS"), + os.environ.get("VITIS_HOME"), + os.environ.get("VITIS"), + ] + for base in env_candidates: + if not base: + continue + cand = Path(base) / "include" + if cand.exists(): + return cand + + vitis_bin = shutil.which("vitis") + if vitis_bin: + return Path(vitis_bin).resolve().parents[1] / "include" + + raise FileNotFoundError( + "Could not locate Vitis include path. Set XILINX_VITIS/VITIS_HOME " + "or ensure 'vitis' is on PATH." + ) + + +class CommandConfiguration(object): + @classmethod + def populate_argument_parser(cls, ap: argparse.ArgumentParser): + ap.formatter_class = argparse.RawTextHelpFormatter + ap.add_argument("--vivado", required=False, type=Path, default=None, + help="Vivado binary to use for linking. If not given, it will be derived from PATH.") + ap.add_argument("--jobs", required=False, type=int, default=8, + help="Number of parallel jobs for Vivado runs.") + + def __init__(self, args: argparse.Namespace): + self._args = args + + # Resolve, if necessary find, and verify the Vivado binary + self._vivado_bin: Path = args.vivado if args.vivado is not None else Path( + shutil.which("vivado")) + self._vivado_bin = self._vivado_bin.expanduser().resolve() + if not self._vivado_bin.is_file(): + raise FileNotFoundError(self._vivado_bin) + + # Misc. arguments + self._n_jobs: int = args.jobs + + @property + def input_arguments(self) -> argparse.Namespace: + return self._args + + @property + def project_name(self) -> str: + raise NotImplementedError() + + @property + def build_dir(self) -> Path: + raise NotImplementedError() + + @property + def ip_repository(self) -> Path: + return self.build_dir / "iprepo" + + @property + def vivado_bin(self) -> Path: + return self._vivado_bin + + @property + def n_jobs(self) -> int: + return self._n_jobs + + +LINK_HELP_EPILOG = f""" +Typical Workflow: + 1. Create a connectivity configuration file (--config) defining kernel + instances and their connections + 2. Specify one or more kernel IP cores via IP-XACT component.xml files (--kernels) + 3. Run the linker to produce a VBIN archive (--out) + 4. The VBIN archive contains all metadata and artifacts needed to execute + the design on the target platform + +Connectivity Configuration Format: + The configuration file uses an INI-like format with the following sections: + + [connectivity] - Define kernel instances and connections + nk=:[:] + Example: nk=vadd:2:vadd_0.vadd_1 + Creates instances of . Names are auto-generated if omitted. + + stream_connect=.:. + Examples: + stream_connect=dma_in_0.axis_out:passthrough_0.axis_in + stream_connect=traffic_producer_0.axis_out:eth_0.tx0 + Connects AXI-Stream ports between kernel instances and/or ethernet ports. + + sp=.: + Example: sp=vadd_0.m_axi_gmem0:HBM0 + Maps AXI4-Full memory ports to memory banks (HBM0-31, DDR0-3, MEM, HOST). + + [clock] - Specify per-kernel clock frequencies (can be repeated) + krnl= + freqhz= + Example: krnl=vadd_0 + freqhz=400000000 + + [network] - Enable Ethernet interfaces + eth_=<0|1> + Example: eth_0=1 + + [user_region] - Custom TCL scripts + pre_synth= + Example: pre_synth=custom_constraints.tcl + + [debug] - Debug net visibility + net=. + Example: net=vadd_0.axis_out + + Lines starting with '#' or ';' are treated as comments. + +Platform Selection: + emu (emulation) - Fast software-based execution for functional testing + sim (simulation) - RTL simulation for detailed verification + hw (hardware) - Full FPGA bitstream generation for deployment + + WARNING: Hardware builds (-p hw) take significant time, ranging from + minutes to hours depending on design complexity and machine resources. + Use emulation for rapid development and testing. + +Example: + {sys.argv[0]} link -c config.cfg -k kernels/ip/accumulate/component.xml \\ + kernels/ip/increment/component.xml -o accelerator.vbin -p hw + +Build Artifacts: + A project directory (.prj) will be created alongside the output + VBIN archive, containing TCL scripts, Vivado projects, and build logs. +""" + + +class LinkerConfiguration(CommandConfiguration): + + @classmethod + def populate_argument_parser(cls, ap: argparse.ArgumentParser): + super().populate_argument_parser(ap) + ap.description = "Link kernel IP cores into a complete design and build a VBIN archive for emulation, simulation, or hardware execution." + ap.epilog = LINK_HELP_EPILOG + ap.add_argument("-c", "--config", required=True, type=Path, + help="Path to the connectivity configuration file (e.g. config.cfg).") + ap.add_argument("-k", "--kernels", required=True, type=Path, nargs="+", + help="List of component.xml files to load as kernel IP cores.") + ap.add_argument("-o", "--out", required=True, type=Path, + help="Path to the final VBIN archive.") + ap.add_argument("-p", "--platform", choices=["emu", "sim", "hw"], + default="emu", help="Target platform (hw, sim, or emu). Default: emu") + ap.add_argument("--pre-synth-tcls", type=Path, nargs="*", default=[], + help="Paths to TCL scripts to run before synthesis (applies to hardware builds only).") + ap.add_argument("--clock-hz", required=False, + type=int, default=None, help="Target clock frequency in MHz.") + + def __init__(self, args: argparse.Namespace): + super().__init__(args) + + # ============ + # Set up paths + # ============ + + # Resolve and verify the configuration file + configuration_file = args.config.expanduser().resolve() + if not configuration_file.is_file(): + raise FileNotFoundError(configuration_file) + + # Resolve and verify the kernel component files + self._kernel_component_paths: List[Path] = [ + path.expanduser().resolve() for path in args.kernels] + for kernel in self._kernel_component_paths: + if not kernel.is_file(): + raise FileNotFoundError(kernel) + + # Resolve the out path and remove the old output if necessary + self._out_path: Path = args.out.expanduser().resolve() + if self._out_path.is_file(): + self._out_path.unlink() + + # Resolve the build directory, clean up if necessary, and prepare it + self._build_dir: Path = self._out_path.with_name( + f"{self._out_path.name}.prj") + if self._build_dir.is_dir(): + shutil.rmtree(self._build_dir) + if self._build_dir.is_file(): + self._build_dir.unlink() + self._build_dir.mkdir(parents=True) + + # Resolve and verify pre-synthesis TCLs (if any) + self._pre_synth_tcls: List[Path] = [] + for path in args.pre_synth_tcls: + path: Path = path.expanduser().resolve() + if not path.is_file(): + raise FileNotFoundError(path) + self._pre_synth_tcls.append(path) + + # Misc. arguments + self._platform = Platform(args.platform) + self._clock_hz: int = args.clock_hz + + # Sanitize the output file stem as the project name + s2 = re.sub(r"[^A-Za-z0-9_]+", "_", str(self._out_path.stem).strip()) + if not s2: + s2 = "proj" + if s2[0].isdigit(): + s2 = "_" + s2 + self._project_name: str = s2 + + # Resolve the Vitis include directory + self._vitis_include_dir = _find_vitis_include() + + # ======================= + # Argument interpretation + # ======================= + with resources.path("slashkit.resources", "bd_ports.txt") as bd_ports_path: + self._bd_ports: BlockDesignPorts = load_bd_ports_from_file( + bd_ports_path) + + self._kernels: List[Kernel] = [parse_component_xml( + kfile) for kfile in self.kernel_component_paths] + + self._configuration: ConnectivityConfig = parse_connectivity_file( + configuration_file) + self._kernel_instances: List[KernelInstance] = apply_config_to_instances( + self.configuration, self.kernels) + + @property + def block_design_ports(self) -> BlockDesignPorts: + return self._bd_ports + + @property + def configuration(self) -> ConnectivityConfig: + return self._configuration + + @property + def networking_enabled(self) -> bool: + # TODO: Change to some sort of description for different service layers once available. + return len(self.configuration.net.enabled_eth) > 0 + + @property + def out_path(self) -> Path: + return self._out_path + + @property + def platform(self) -> Platform: + return self._platform + + @property + def project_name(self) -> str: + return self._project_name + + @property + def kernel_component_paths(self) -> List[Path]: + return self._kernel_component_paths + + @property + def kernels(self) -> List[Kernel]: + return self._kernels + + @property + def kernel_instances(self) -> Dict[str, KernelInstance]: + return self._kernel_instances + + @property + def build_dir(self) -> Path: + return self._build_dir + + @property + def vitis_include_dir(self) -> Path: + return self._vitis_include_dir + + @property + def pre_synth_tcls(self) -> List[Path]: + return self._pre_synth_tcls + + @property + def clock_hz(self) -> Optional[int]: + return self._clock_hz + + +INSTALL_HELP_EPILOG = f""" +Purpose: + The 'install' subcommand builds the static shell required for + hardware builds. This is a one-time setup operation that creates base images + used by the 'link' subcommand when targeting hardware (-p hw). + +When to Use: + - During initial installation and/or packaging of slashkit + - When the static shell definition needs to be regenerated + + Most users will NOT need to run this command regularly. It is only required + during linker installation/setup. + +What It Does: + 1. Builds the static shell base images from the resource directory + 2. Generates necessary Vivado synthesis artifacts + 3. Creates reusable partial designs for hardware linking + + WARNING: This operation involves full Vivado synthesis and implementation, + which takes significant time (multiple hours depending on the system). + +Build Artifacts: + The build directory (--build-dir) will contain Vivado projects, checkpoints, + and logs. This directory can be removed after successful installation. + +Example: + {sys.argv[0]} install --build-dir ./install.prj --jobs 16 --out-dir linker/slashkit/resources +""" + + +class InstallerConfiguration(CommandConfiguration): + @classmethod + def populate_argument_parser(cls, ap: argparse.ArgumentParser): + super().populate_argument_parser(ap) + ap.description = "Build and install base images for hardware builds." + ap.epilog = INSTALL_HELP_EPILOG + ap.add_argument("--build-dir", required=False, type=Path, default=Path( + "./install.prj"), help="The build directory for the installer. Default: ./install_prj") + ap.add_argument("--aved-repo", required=False, type=str, default="https://github.com/Xilinx/AVED.git", + help="The AVED git repository to check out. Default: https://github.com/Xilinx/AVED.git") + ap.add_argument("--aved-ref", required=False, type=str, default="amd_v80_gen5x8_25.1_xbtest_20251113", + help="The AVED git ref to check out. Default: amd_v80_gen5x8_25.1_xbtest_20251113") + ap.add_argument("--out-dir", required=True, type=Path, + help="The resource directory to install the artifacts to. " + + "If you have checked out the SLASH repository, this would be linker/slashkit/resources") + + def __init__(self, args: argparse.Namespace): + super().__init__(args) + + self._build_dir: Path = args.build_dir.expanduser().resolve() + if self._build_dir.is_dir(): + shutil.rmtree(self._build_dir) + self._build_dir.mkdir(parents=True) + + self._aved_repo: str = args.aved_repo + self._aved_ref: str = args.aved_ref + + self._out_dir: Path = args.out_dir.expanduser().resolve() + if not self._out_dir.is_dir(): + raise FileNotFoundError(self._out_dir) + + @property + def project_name(self) -> str: + return "slash_install" + + @property + def build_dir(self) -> Path: + return self._build_dir + + @property + def aved_repo(self) -> str: + return self._aved_repo + + @property + def aved_ref(self) -> str: + return self._aved_ref + + @property + def out_dir(self) -> Path: + return self._out_dir diff --git a/linker/slashkit/core/connectivity.py b/linker/slashkit/core/connectivity.py new file mode 100644 index 00000000..f3c68561 --- /dev/null +++ b/linker/slashkit/core/connectivity.py @@ -0,0 +1,95 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from dataclasses import dataclass, field +from typing import List + +# ----------------------------- +# Data structures +# ----------------------------- + + +@dataclass +class NetworkSpec: + enabled_eth: set[int] + + +@dataclass +class UserRegionSpec: + pre_synth_tcls: list[str] + + +@dataclass(frozen=True) +class DebugNetSpec: + inst: str + port: str + + +@dataclass +class DebugSpec: + nets: list[DebugNetSpec] + + +@dataclass(frozen=True) +class NKSpec: + kernel_type: str + count: int + instance_names: List[str] + + +@dataclass(frozen=True) +class StreamConnect: + src_inst: str + src_port: str + dst_inst: str + dst_port: str + + +@dataclass(frozen=True) +class MemoryTarget: + domain: str + index: int + + +@dataclass(frozen=True) +class SpMapping: + inst: str + port: str + target: MemoryTarget + + +@dataclass(frozen=True) +class ClockSpec: + inst: str + freq_hz: int + + +@dataclass +class ConnectivityConfig: + nk: List[NKSpec] = field(default_factory=list) + streams: List[StreamConnect] = field(default_factory=list) + sps: List[SpMapping] = field(default_factory=list) + clocks: List[ClockSpec] = field(default_factory=list) + net: NetworkSpec = field( + default_factory=lambda: NetworkSpec(enabled_eth={})) + user_region: UserRegionSpec = field( + default_factory=lambda: UserRegionSpec(pre_synth_tcls=[])) + debug: DebugSpec = field(default_factory=lambda: DebugSpec(nets=[])) diff --git a/linker/slashkit/core/kernel.py b/linker/slashkit/core/kernel.py new file mode 100644 index 00000000..75166d81 --- /dev/null +++ b/linker/slashkit/core/kernel.py @@ -0,0 +1,96 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from dataclasses import dataclass, field +from typing import Dict, Iterable, Optional, List +from pathlib import Path + +from slashkit.core.port import Port, BusType +from slashkit.core.bus import Bus +from slashkit.core.regs import MemoryMap + + +@dataclass(frozen=True) +class Kernel: + """ + Generic kernel/IP *type* definition. + Contains bus and port definitions — not instance-specific data. + """ + name: str + component_xml_path: Path + ports: Dict[str, Port] = field(default_factory=dict) + buses: Dict[str, Bus] = field(default_factory=dict) + vlnv: Optional[str] = None + memory_maps: List[MemoryMap] = field(default_factory=list) # NEW + hls_data_path: Optional[Path] = None + + def port(self, name: str) -> Port: + """Retrieve a port by name.""" + try: + return self.ports[name] + except KeyError as e: + raise KeyError( + f"Kernel '{self.name}' has no port named '{name}'.") from e + + def ports_of_type(self, ptype: BusType) -> Iterable[Port]: + """Iterate over all ports of a given type.""" + return (p for p in self.ports.values() if p.ptype == ptype) + + def bus(self, name: str) -> Bus: + """Retrieve a bus by name.""" + try: + return self.buses[name] + except KeyError as e: + raise KeyError( + f"Kernel '{self.name}' has no bus named '{name}'.") from e + + def buses_of_type(self, ptype: BusType) -> Iterable[Bus]: + """Iterate over all buses of a given type.""" + return (b for b in self.buses.values() if b.ptype == ptype) + + def bus_physical(self, bus_name: str, logical: Optional[str] = None) -> Optional[Port]: + """Return a physical Port object for a bus (or None if unknown).""" + bus = self.buses.get(bus_name) + if bus is None: + return None + return bus.physical_port(logical=logical) + + def bus_physical_port(self, bus_name: str, logical: Optional[str] = None) -> Optional[str]: + """Return a physical port for a bus (or None if unknown).""" + p = self.bus_physical(bus_name, logical=logical) + return p.name if p is not None else None + + +@dataclass +class KernelInstance: + """ + A specific instance of a Kernel (e.g., 'dma_0'). + Holds a pointer to the Kernel type and optional parameters. + """ + name: str + kernel: Kernel + params: Dict[str, object] = field(default_factory=dict) + + def port(self, name: str) -> Port: + return self.kernel.port(name) + + def __repr__(self) -> str: + return f"" diff --git a/examples/02_chain/hls/build.tcl b/linker/slashkit/core/port.py similarity index 53% rename from examples/02_chain/hls/build.tcl rename to linker/slashkit/core/port.py index 6b32d0a6..18a14218 100644 --- a/examples/02_chain/hls/build.tcl +++ b/linker/slashkit/core/port.py @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,61 +18,41 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -set command [lindex $argv 0] -set device [lindex $argv 1] -set ipname [lindex $argv 2] - -set do_sim 0 -set do_syn 0 -set do_export 0 -set do_cosim 0 - -switch $command { - "sim" { - set do_sim 1 - } - "syn" { - set do_syn 1 - } - "ip" { - set do_syn 1 - set do_export 1 - } - "cosim" { - set do_syn 1 - set do_cosim 1 - } - "all" { - set do_sim 1 - set do_syn 1 - set do_export 1 - set do_cosim 1 - } - default { - puts "Unrecognized command" - exit - } -} - - -open_project build_${ipname}.${device} -file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp -add_files $ipname.cpp -cflags "-std=c++14" - -set_top $ipname - -open_solution sol1 - -if {$do_syn} { - set_part $device - create_clock -period 4 -name default - config_interface -m_axi_addr64=true - csynth_design -} - -if {$do_export} { - config_export -format ip_catalog - export_design -} - -exit \ No newline at end of file +from __future__ import annotations +from dataclasses import dataclass +from enum import Enum, auto +from typing import Optional + + +class BusType(Enum): + """Enumerates the supported bus/interface types in the design.""" + CLOCK = auto() + RESET = auto() + AXILITE = auto() + AXI4FULL = auto() + AXIS = auto() + INTERRUPT = auto() # present, but currently unused + + +@dataclass(frozen=True) +class Port: + """ + Represents a single port belonging to a kernel definition. + For AXI/AXIS, width refers to data width (e.g., 32/64/128). + For CLOCK, RESET, and INTERRUPT, width is forced to 1. + """ + name: str + ptype: BusType + width: Optional[int] = None + + def __post_init__(self): + if self.ptype in {BusType.CLOCK, BusType.RESET, BusType.INTERRUPT}: + object.__setattr__(self, "width", 1) + + @property + def btype(self) -> BusType: + """Preferred IP-XACT terminology.""" + return self.ptype + + def __repr__(self) -> str: + return f"" diff --git a/examples/04_freq/hls/build.tcl b/linker/slashkit/core/regs.py similarity index 52% rename from examples/04_freq/hls/build.tcl rename to linker/slashkit/core/regs.py index 7e9a9238..2b169d08 100644 --- a/examples/04_freq/hls/build.tcl +++ b/linker/slashkit/core/regs.py @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,61 +18,49 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -set command [lindex $argv 0] -set device [lindex $argv 1] -set ipname [lindex $argv 2] +from __future__ import annotations +from dataclasses import dataclass, field +from typing import List, Optional -set do_sim 0 -set do_syn 0 -set do_export 0 -set do_cosim 0 -switch $command { - "sim" { - set do_sim 1 - } - "syn" { - set do_syn 1 - } - "ip" { - set do_syn 1 - set do_export 1 - } - "cosim" { - set do_syn 1 - set do_cosim 1 - } - "all" { - set do_sim 1 - set do_syn 1 - set do_export 1 - set do_cosim 1 - } - default { - puts "Unrecognized command" - exit - } -} +@dataclass +class RegField: + name: str + description: Optional[str] + bit_offset: int + bit_width: int + access: Optional[str] = None + modified_write_value: Optional[str] = None + read_action: Optional[str] = None + reset_value: Optional[int] = None -open_project build_${ipname}.${device} -file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp -add_files $ipname.cpp -cflags "-std=c++14" +@dataclass +class Register: + name: str + display_name: Optional[str] + description: Optional[str] + address_offset: int + size: int + access: Optional[str] = None + reset_value: Optional[int] = None + fields: List[RegField] = field(default_factory=list) -set_top $ipname -open_solution sol1 +@dataclass +class AddressBlock: + name: str + base_address: int + range: int + width: int + usage: Optional[str] = None + access: Optional[str] = None + offset_base_param: Optional[str] = None + offset_high_param: Optional[str] = None + registers: List[Register] = field(default_factory=list) -if {$do_syn} { - set_part $device - create_clock -period 2 -name default - config_interface -m_axi_addr64=true - csynth_design -} -if {$do_export} { - config_export -format ip_catalog - export_design -} - -exit \ No newline at end of file +@dataclass +class MemoryMap: + name: str + address_blocks: List[AddressBlock] = field(default_factory=list) diff --git a/linker/slashkit/emit/__init__.py b/linker/slashkit/emit/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/emu/__init__.py b/linker/slashkit/emit/emu/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/emu/project_gen.py b/linker/slashkit/emit/emu/project_gen.py new file mode 100644 index 00000000..0be461ee --- /dev/null +++ b/linker/slashkit/emit/emu/project_gen.py @@ -0,0 +1,339 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +from pathlib import Path +import json +import logging +import os +import re +import shlex +import shutil +import subprocess +import tarfile +from typing import Iterable + +from slashkit.emit.hls_meta import infer_hls_json_from_component_xml +from slashkit.core.command_config import LinkerConfiguration + +logger = logging.getLogger(__name__) + + +def _find_vitis_include() -> Path: + env_candidates = [ + os.environ.get("XILINX_VITIS"), + os.environ.get("VITIS_HOME"), + os.environ.get("VITIS"), + ] + for base in env_candidates: + if not base: + continue + cand = Path(base) / "include" + if cand.exists(): + return cand + + vitis_bin = shutil.which("vitis") + if vitis_bin: + return Path(vitis_bin).resolve().parents[1] / "include" + + raise FileNotFoundError( + "Could not locate Vitis include path. Set XILINX_VITIS/VITIS_HOME " + "or ensure 'vitis' is on PATH." + ) + + +def _collect_kernel_cpp(config: LinkerConfiguration) -> list[Path]: + cpp_files: list[Path] = [] + seen: set[Path] = set() + + for kpath in config.kernel_component_paths: + if not kpath.exists(): + raise FileNotFoundError(f"Kernel component.xml not found: {kpath}") + # component.xml -> ip -> impl -> + sol_dir = kpath.parents[2] + build_dir = sol_dir.parent + + # Prefer the original kernel sources in the build dir (e.g., build_increment.../*.cpp). + candidates = list(build_dir.glob("*.cpp")) + if not candidates: + # Fallbacks for other layouts. + candidates = list(sol_dir.glob("*.cpp")) + if not candidates: + candidates = list((kpath.parent.parent).glob("*.cpp")) + + for cpp in sorted(candidates): + if cpp not in seen: + seen.add(cpp) + cpp_files.append(cpp) + + return cpp_files + + +_LOCAL_INCLUDE_RE = re.compile(r'^\s*#\s*include\s*([<"])\s*([^">]+?)\s*[">]') +_USER_HEADER_SUFFIXES = {".h", ".hh", ".hpp", ".hxx", ".inc"} +_USER_SOURCE_SUFFIXES = {".c", ".cc", ".cpp", ".cxx", ".C"} + + +def _dedupe_paths(paths: Iterable[Path]) -> list[Path]: + out: list[Path] = [] + seen: set[Path] = set() + for p in paths: + rp = p.resolve() + if not rp.exists(): + continue + if rp in seen: + continue + seen.add(rp) + out.append(rp) + return out + + +def _extract_include_dirs_from_cfg(cfg_path: Path) -> list[Path]: + """ + Parse syn.cflags from an HLS cfg file and extract include directories. + Relative paths are resolved relative to cfg_path.parent (the HLS build dir). + """ + include_dirs: list[Path] = [] + if not cfg_path.exists(): + return include_dirs + + def _append_dir(raw: str) -> None: + raw = raw.strip() + if not raw: + return + p = Path(raw) + if not p.is_absolute(): + p = (cfg_path.parent / p).resolve() + if p.exists(): + include_dirs.append(p) + + for raw_line in cfg_path.read_text(encoding="utf-8", errors="ignore").splitlines(): + line = raw_line.strip() + if not line or line.startswith("#") or "=" not in line: + continue + key, value = line.split("=", 1) + if key.strip() != "syn.cflags": + continue + try: + toks = shlex.split(value) + except ValueError: + toks = value.split() + + i = 0 + while i < len(toks): + t = toks[i] + if t == "-I": + if i + 1 < len(toks): + _append_dir(toks[i + 1]) + i += 2 + continue + elif t.startswith("-I") and len(t) > 2: + _append_dir(t[2:]) + elif t in ("-isystem", "-iquote"): + if i + 1 < len(toks): + _append_dir(toks[i + 1]) + i += 2 + continue + i += 1 + + return _dedupe_paths(include_dirs) + + +def _resolve_hls_c_sources(hls_json_path: Path) -> list[Path]: + """ + Resolve original C/C++ sources from hls_data.json Files.CSource. + Falls back to build-dir .cpp scan if metadata is missing/partial. + """ + sources: list[Path] = [] + try: + d = json.loads(hls_json_path.read_text(encoding="utf-8")) + for rel in d.get("Files", {}).get("CSource", []) or []: + p = (hls_json_path.parent / rel).resolve() + if p.suffix in _USER_SOURCE_SUFFIXES and p.exists(): + sources.append(p) + except Exception as e: # pragma: no cover - best-effort discovery + logger.debug("Failed to parse HLS metadata %s: %s", hls_json_path, e) + + if sources: + return _dedupe_paths(sources) + + # Legacy fallback: component.xml -> ip -> impl -> ; build dir contains copied kernel .cpp + try: + # hls_data.json lives in //hls_data.json + sol_dir = hls_json_path.parent + build_dir = sol_dir.parent + for p in sorted(build_dir.glob("*.cpp")): + sources.append(p.resolve()) + except Exception: # pragma: no cover - defensive fallback + pass + return _dedupe_paths(sources) + + +def _collect_user_headers_from_sources(sources: Iterable[Path], include_dirs: Iterable[Path]) -> list[Path]: + """ + Recursively walk local include graphs starting from user C/C++ sources and + collect reachable user headers. These headers are force-included when + compiling emu tb.cpp so user-defined types in HLS top signatures are visible. + """ + roots = _dedupe_paths([p.parent for p in sources] + list(include_dirs)) + header_list: list[Path] = [] + seen_headers: set[Path] = set() + visited_files: set[Path] = set() + + def _resolve_local_include(inc_name: str, cur_dir: Path) -> Path | None: + candidates = [cur_dir] + roots + for base in candidates: + p = (base / inc_name).resolve() + if p.exists() and p.is_file(): + return p + return None + + def _walk_file(path: Path) -> None: + rp = path.resolve() + if rp in visited_files or not rp.exists() or not rp.is_file(): + return + visited_files.add(rp) + + try: + lines = rp.read_text( + encoding="utf-8", errors="ignore").splitlines() + except OSError: + return + + for line in lines: + m = _LOCAL_INCLUDE_RE.match(line) + if not m: + continue + _delim, inc_name = m.groups() + inc = _resolve_local_include(inc_name.strip(), rp.parent) + if inc is None: + continue + if inc.suffix in _USER_HEADER_SUFFIXES: + if inc not in seen_headers: + seen_headers.add(inc) + header_list.append(inc) + _walk_file(inc) + elif inc.suffix in _USER_SOURCE_SUFFIXES: + _walk_file(inc) + + for src in _dedupe_paths(sources): + _walk_file(src) + + return header_list + + +def _collect_emu_compile_inputs(config: LinkerConfiguration) -> tuple[list[Path], list[Path], list[Path]]: + """ + Returns: + (user_cpp_sources, user_include_dirs, force_include_headers) + """ + cpp_files: list[Path] = [] + include_dirs: list[Path] = [] + force_headers: list[Path] = [] + + for kxml in config.kernel_component_paths: + kpath = Path(kxml).resolve() + if not kpath.exists(): + raise FileNotFoundError(f"Kernel component.xml not found: {kpath}") + + hls_json = infer_hls_json_from_component_xml(kpath) + srcs = _resolve_hls_c_sources(hls_json) + cpp_files.extend(srcs) + + # component.xml -> ip -> impl -> ; cfg is copied into build_dir by BuildHLS.cmake + sol_dir = kpath.parents[2] + build_dir = sol_dir.parent + cfgs = sorted(build_dir.glob("*.cfg")) + for cfg in cfgs: + include_dirs.extend(_extract_include_dirs_from_cfg(cfg)) + + include_dirs.extend([p.parent for p in srcs]) + force_headers.extend( + _collect_user_headers_from_sources(srcs, include_dirs)) + + return ( + _dedupe_paths(cpp_files) or _collect_kernel_cpp( + config.kernel_component_paths), + _dedupe_paths(include_dirs), + _dedupe_paths(force_headers), + ) + + +def build_emu_project(config: LinkerConfiguration) -> None: + tb_path = config.build_dir / "tb.cpp" + if not tb_path.exists(): + raise FileNotFoundError(f"tb.cpp not found: {tb_path}") + + kernel_cpps, user_include_dirs, force_headers = _collect_emu_compile_inputs( + config) + cpp_files = [tb_path] + kernel_cpps + if not cpp_files: + raise FileNotFoundError( + "No C++ sources found to build emulation executable.") + + vitis_include = _find_vitis_include() + vpp_emu_path = config.build_dir / "vpp_emu" + + include_flags = [] + for inc in user_include_dirs: + include_flags += ["-I", str(inc)] + + force_include_flags = [] + for hdr in force_headers: + force_include_flags += ["-include", str(hdr)] + + cmd = ( + ["g++", "-O3"] + + include_flags + + force_include_flags + + [str(p) for p in cpp_files] + + ["-o", str(vpp_emu_path), "-I", str(vitis_include), + "-lzmq", "-I", "/usr/include/jsoncpp/", "-ljsoncpp"] + ) + if force_headers: + logger.info("EMU compile force-including %d user header(s)", + len(force_headers)) + if user_include_dirs: + logger.info("EMU compile adding %d user include dir(s)", + len(user_include_dirs)) + logger.info("Building emulation executable: %s", " ".join(cmd)) + subprocess.run(cmd, cwd=str(config.build_dir), check=True) + logger.info("Emulation build outputs in %s", config.build_dir) + + +def package_emu_artifacts(config: LinkerConfiguration) -> Path: + system_map = config.build_dir / "system_map.xml" + vpp_emu = config.build_dir / "vpp_emu" + emu_manifest = config.build_dir / "emu_manifest.json" + + if not system_map.exists(): + raise FileNotFoundError(f"system_map.xml not found: {system_map}") + if not vpp_emu.exists(): + raise FileNotFoundError(f"vpp_emu not found: {vpp_emu}") + + with tarfile.open(config.out_path, mode="w") as tf: + tf.add(system_map, arcname="system_map.xml") + tf.add(vpp_emu, arcname="vpp_emu") + if emu_manifest.exists(): + tf.add(emu_manifest, arcname="emu_manifest.json") + + logger.info("Emulation vbin in %s", config.out_path) + return config.out_path diff --git a/linker/slashkit/emit/emu/tb_ctx.py b/linker/slashkit/emit/emu/tb_ctx.py new file mode 100644 index 00000000..4eca7b67 --- /dev/null +++ b/linker/slashkit/emit/emu/tb_ctx.py @@ -0,0 +1,628 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +from pathlib import Path +import re +from typing import Dict, List + +from slashkit.core.port import BusType +from slashkit.emit.hls_meta import ( + load_hls_metadata, + parse_hls_args, +) +from slashkit.core.kernel import KernelInstance +from slashkit.core.connectivity import StreamConnect + + +def _norm_stream_type(src: str) -> str: + # Canonicalize stream types so downstream checks are stable. + parsed = _parse_stream_type(src) + if parsed is None: + return src.strip() + elem_type, is_ref = parsed + return f"hls::stream<{elem_type}>{'&' if is_ref else ''}" + + +def _parse_stream_type(src: str) -> tuple[str, bool] | None: + """ + Parse stream-like types with nested templates, e.g. + stream, 0>& + hls::stream>& + hls::stream >& + Returns (element_type, is_reference) or None if not a stream type. + """ + s = src.strip() + if not re.match(r"^(?:hls::)?stream\s*<", s): + return None + + lt = s.find("<") + if lt < 0: + return None + + depth = 0 + gt = -1 + for i in range(lt, len(s)): + c = s[i] + if c == "<": + depth += 1 + elif c == ">": + depth -= 1 + if depth == 0: + gt = i + break + if gt < 0: + return None + + inner = s[lt + 1: gt] + tail = s[gt + 1:].strip() + is_ref = tail.endswith("&") + + # Split stream template args at top-level commas only. + parts: list[str] = [] + cur: list[str] = [] + depth = 0 + for ch in inner: + if ch == "<": + depth += 1 + cur.append(ch) + elif ch == ">": + depth = max(0, depth - 1) + cur.append(ch) + elif ch == "," and depth == 0: + parts.append("".join(cur).strip()) + cur = [] + else: + cur.append(ch) + parts.append("".join(cur).strip()) + + if not parts or not parts[0]: + return None + return parts[0], is_ref + + +def _is_stream(cpp_t: str) -> bool: + return _parse_stream_type(cpp_t) is not None + + +def _stream_inner(cpp_t: str) -> str: + parsed = _parse_stream_type(cpp_t) + return parsed[0] if parsed is not None else "ap_uint<512>" + + +def _is_ptr(cpp_t: str) -> bool: + return "*" in cpp_t + + +def _strip_ref(cpp_t: str) -> tuple[str, bool]: + t = cpp_t.strip() + # do not treat hls::stream<...>& as scalar ref + if t.endswith("&") and not _is_stream(t): + return t[:-1].strip(), True + return t, False + + +def _select_register_block(kernel): + mmaps = getattr(kernel, "memory_maps", []) or [] + + for mm in mmaps: + if mm.name and "control" in mm.name.lower(): + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register": + return ab + if mm.address_blocks: + return mm.address_blocks[0] + + for mm in mmaps: + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register": + return ab + + for mm in mmaps: + if mm.address_blocks: + return mm.address_blocks[0] + + return None + + +_REG_SPLIT_RE = re.compile(r".*_\d+$") +_QDMA_PORT_RE = re.compile(r"qdma_(\d+)$") + + +def _is_split_reg_name(name: str) -> bool: + return bool(_REG_SPLIT_RE.fullmatch(name or "")) + + +def _stream_aliases_for_edge(edge, wire_name: str) -> list[str]: + names = [wire_name] + + def _maybe_add(inst_name: str, port_name: str, prefix: str) -> None: + if not inst_name.lower().startswith("cips"): + return + m = _QDMA_PORT_RE.fullmatch(port_name or "") + if not m: + return + names.append(f"{prefix}{m.group(1)}") + + _maybe_add(getattr(edge, "src_inst"), getattr( + edge, "src_port"), "streamingBuffer_") + _maybe_add(getattr(edge, "dst_inst"), getattr( + edge, "dst_port"), "outputStreamingBuffer_") + + # preserve order while deduping + out: list[str] = [] + seen: set[str] = set() + for n in names: + if n not in seen: + seen.add(n) + out.append(n) + return out + + +def _infer_control_mode(*, has_axilite: bool, stream_only: bool) -> str: + if has_axilite: + return "s_axilite" + if stream_only: + return "ap_ctrl_none" + return "unknown" + + +def _call_kind_for_cpp_type(cpp_t: str) -> str: + return "buffer" if _is_ptr(cpp_t) else "scalar" + + +def parse_sol1_data(sol1_json: Path) -> dict: + d = load_hls_metadata(sol1_json, strict=True) + assert d is not None # strict=True guarantees dict or exception + top = str(d.get("Top", "") or "") + args = [] + for order_idx, info in enumerate(parse_hls_args(d)): + idx = info["index"] if info["index"] is not None else order_idx + src_type = info["src_type"] + cpp_type = _norm_stream_type(src_type) + + # interface name if present (axis_in/axis_out/m_axi_gmem0) + iface = None + for ref in info.get("hw_refs", []): + if ref.get("type") == "interface": + iface = ref.get("interface") + break + + args.append( + { + "name": info["name"], + "index": idx, + "direction": info.get("direction"), + "srcType": src_type, + "cppType": cpp_type, + "iface": iface, + } + ) + args.sort(key=lambda a: a["index"]) + return {"Top": top, "Args": args} + + +def build_tb_context(instances: Dict[str, KernelInstance], streams: List[StreamConnect], kernel_sol1_by_type: dict[str, Path]) -> dict: + """ + instances: from apply_config_to_instances(), name -> Instance(kernel=KernelType,...) + streams: list of edges, each with .src_inst .src_port .dst_inst .dst_port (your parser types) + kernel_sol1_by_type: kernel-type-name -> HLS metadata json Path (hls_data.json / sol1_data.json) + """ + + # Load HLS metadata per kernel type + hls_meta: dict[str, dict] = {} + for ktype, sol1p in kernel_sol1_by_type.items(): + hls_meta[ktype] = parse_sol1_data(sol1p) + + # Prototypes: generated from Top + Args (metadata doesn't store full prototype) + prototypes = [] + for ktype, meta in hls_meta.items(): + sig = [f'{a["cppType"]} {a["name"]}' for a in meta["Args"]] + prototypes.append(f'void {meta["Top"]}({", ".join(sig)});') + + # Streams: wire name per stream_connect edge + wires = [] + endpoint_to_wire: dict[str, str] = {} + + def _get_stream_ctype_from_endpoint(inst_name: str, iface: str) -> str | None: + if inst_name not in instances: + return None + ktype = instances[inst_name].kernel.name + meta = hls_meta[ktype] + a = next((x for x in meta["Args"] if x["iface"] + == iface and _is_stream(x["cppType"])), None) + if a is None: + return None + return _stream_inner(a["cppType"]) + + def get_stream_ctype(edge) -> str: + return ( + _get_stream_ctype_from_endpoint(edge.src_inst, edge.src_port) + or _get_stream_ctype_from_endpoint(edge.dst_inst, edge.dst_port) + or "ap_uint<512>" + ) + + stream_routes = [] + for i, e in enumerate(streams): + wname = f"stream_{i}" + ctype = get_stream_ctype(e) + wires.append({"name": wname, "ctype": ctype}) + stream_routes.append( + {"wire": wname, "ctype": ctype, "names": _stream_aliases_for_edge(e, wname)}) + endpoint_to_wire[f"{e.src_inst}.{e.src_port}"] = wname + endpoint_to_wire[f"{e.dst_inst}.{e.dst_port}"] = wname + + # Variables + function dispatch blocks + vars_decl = [] + function_calls = [] + ref_vars = [] + fetch_scalar_cases = [] + autostart_calls = [] + manifest_kernels = [] + + for inst_name, inst in instances.items(): + ktype = inst.kernel.name + meta = hls_meta[ktype] + non_stream_args = [] + + # declare per-arg vars (skip streams) + for a in meta["Args"]: + cpp_t, is_ref = _strip_ref(a["cppType"]) + vname = f"{inst_name}_{a['name']}" + + if _is_stream(cpp_t): + continue + if _is_ptr(cpp_t): + base = cpp_t.split("*", 1)[0].strip() + vars_decl.append(f"{base}* {vname}") + else: + vars_decl.append(f"{cpp_t} {vname}") + if is_ref: + ref_vars.append(vname) + non_stream_args.append( + { + "name": a["name"], + "var": vname, + "cppType": cpp_t, + "is_ref": is_ref, + } + ) + + decode_blocks = [] + call_args = [] + manifest_call_args = [] + + argN = 0 + for a in meta["Args"]: + cpp_t = a["cppType"] + vname = f"{inst_name}_{a['name']}" + + if _is_stream(cpp_t): + w = endpoint_to_wire.get(f"{inst_name}.{a['iface']}") + call_args.append(w if w else "/*MISSING_STREAM*/") + continue + + decode_blocks.append( + f'argType = root["args"]["arg{argN}"]["type"].asString();') + if _is_ptr(cpp_t): + base = cpp_t.split("*", 1)[0].strip() + decode_blocks.append('if (argType == "buffer") {') + decode_blocks.append( + f' std::string bufferName = root["args"]["arg{argN}"]["name"].asString();') + decode_blocks.append( + ' if (buffers.find(bufferName) != buffers.end()) {') + decode_blocks.append( + f' {vname} = static_cast<{base}*>(buffers[bufferName]);') + decode_blocks.append(' }') + decode_blocks.append('}') + else: + decode_blocks.append('if (argType == "scalar") {') + decode_blocks.append( + f' assignValue({vname}, root["args"]["arg{argN}"]["value"]);') + decode_blocks.append('}') + + include_in_manifest_call = True + if (a.get("direction") or "in") == "out" and not _is_ptr(cpp_t): + # VRT emu calls omit scalar/register-style outputs (read back via fetch), + # but still pass pointer outputs (e.g. m_axi write destinations). + include_in_manifest_call = False + + if include_in_manifest_call: + manifest_call_args.append( + { + "arg": f"arg{argN}", + "kind": _call_kind_for_cpp_type(cpp_t), + "source_arg": a["name"], + "cpp_type": cpp_t, + } + ) + call_args.append(vname) + argN += 1 + + function_calls.append( + { + "inst": inst_name, + "top": meta["Top"], + "decode_blocks": decode_blocks, + "call_args": call_args, + } + ) + + has_axilite = any( + True for _ in inst.kernel.ports_of_type(BusType.AXILITE)) + stream_only = bool(meta["Args"]) and all( + _is_stream(a["cppType"]) for a in meta["Args"]) + has_missing_stream = any( + arg == "/*MISSING_STREAM*/" for arg in call_args) + control_mode = _infer_control_mode( + has_axilite=has_axilite, stream_only=stream_only) + autostart = stream_only and not has_axilite and not has_missing_stream + callable_kernel = has_axilite and not has_missing_stream + scheduling_policy = "autostart" if autostart else "call" + autostart_reason = "stream_only_no_axilite" if autostart else "" + shutdown_policy = "fast_exit" if autostart else "normal_exit" + if autostart: + autostart_calls.append( + { + "inst": inst_name, + "top": meta["Top"], + "call_args": call_args, + } + ) + manifest_kernels.append( + { + "instance": inst_name, + "top": meta["Top"], + "has_axilite": has_axilite, + "control_mode": control_mode, + "callable": callable_kernel, + "autostart": autostart, + "autostart_reason": autostart_reason, + "scheduling_policy": scheduling_policy, + "shutdown_policy": shutdown_policy, + "missing_stream_bindings": has_missing_stream, + "call_arg_count": len(manifest_call_args), + "call_args": manifest_call_args, + "registers": [], + "args": [ + { + "name": a["name"], + "cpp_type": a["cppType"], + "iface": a["iface"], + "direction": a.get("direction"), + "is_stream": _is_stream(a["cppType"]), + "is_pointer": _is_ptr(_strip_ref(a["cppType"])[0]), + "call_arg": next( + ( + ca["arg"] + for ca in manifest_call_args + if ca["source_arg"] == a["name"] + ), + None, + ), + "call_kind": next( + ( + ca["kind"] + for ca in manifest_call_args + if ca["source_arg"] == a["name"] + ), + None, + ), + } + for a in meta["Args"] + ], + } + ) + + reg_block = _select_register_block(inst.kernel) + regs = [] + if reg_block is not None and getattr(reg_block, "registers", None): + regs = sorted(reg_block.registers, key=lambda r: r.address_offset) + manifest_kernels[-1]["registers"] = [ + { + "name": (getattr(r, "name", "") or ""), + "offset": int(getattr(r, "address_offset", 0) or 0), + "width": int(getattr(r, "range", 32) or 32), + "access": (getattr(r, "access", "") or ""), + "description": (getattr(r, "description", "") or ""), + } + for r in regs + ] + + # Mirror vrt::Kernel::read() emulation indexing, which starts after the + # first 4 control registers and synthesizes argN based on register order. + if regs: + reg_idx = 4 + fetch_arg_idx = 0 + logical_arg_idx = 0 + prev_value_reg_name: str | None = None + while reg_idx < len(regs): + reg_name = getattr(regs[reg_idx], "name", "") or "" + reg_off = int(getattr(regs[reg_idx], "address_offset", 0) or 0) + + if _is_split_reg_name(reg_name): + # Preserve the logical value name (e.g. "sum" from "sum_1") so a + # following "_ctrl" validity register can be synthesized. + prev_value_reg_name = reg_name.rsplit("_", 1)[0] + if logical_arg_idx < len(non_stream_args): + hi_reg = regs[reg_idx + + 1] if (reg_idx + 1) < len(regs) else None + hi_reg_name = ( + getattr(hi_reg, "name", + "") or "" if hi_reg is not None else "" + ) + hi_reg_off = ( + int(getattr(hi_reg, "address_offset", 0) or 0) + if hi_reg is not None + else None + ) + fetch_scalar_cases.append( + { + "inst": inst_name, + "arg": f"arg{fetch_arg_idx}", + "kind": "var", + "var": non_stream_args[logical_arg_idx]["var"], + "source": "register_metadata", + "register_name": reg_name, + "register_offset": reg_off, + "register_split": True, + } + ) + # Expose the high 32-bit word of the same logical scalar for + # split 64-bit AXI-Lite register reads (e.g. sum_2). + if hi_reg_off is not None: + fetch_scalar_cases.append( + { + "inst": inst_name, + "arg": f"arg{fetch_arg_idx}", + "kind": "var_u32_hi", + "var": non_stream_args[logical_arg_idx]["var"], + "source": "register_metadata", + "register_name": hi_reg_name, + "register_offset": hi_reg_off, + "register_split": True, + "register_split_part": "hi", + } + ) + logical_arg_idx += 1 + fetch_arg_idx += 1 + reg_idx += 2 + continue + + if prev_value_reg_name and reg_name == f"{prev_value_reg_name}_ctrl": + fetch_scalar_cases.append( + { + "inst": inst_name, + "arg": f"arg{fetch_arg_idx}", + "kind": "const_u32", + "value": 1, + "source": "register_metadata", + "register_name": reg_name, + "register_offset": reg_off, + "synthetic": "ctrl_valid", + "derived_from_register": prev_value_reg_name, + } + ) + fetch_arg_idx += 1 + reg_idx += 1 + continue + + if logical_arg_idx < len(non_stream_args): + fetch_scalar_cases.append( + { + "inst": inst_name, + "arg": f"arg{fetch_arg_idx}", + "kind": "var", + "var": non_stream_args[logical_arg_idx]["var"], + "source": "register_metadata", + "register_name": reg_name, + "register_offset": reg_off, + "register_split": False, + } + ) + logical_arg_idx += 1 + prev_value_reg_name = reg_name + else: + prev_value_reg_name = None + + fetch_arg_idx += 1 + reg_idx += 1 + elif non_stream_args: + raise RuntimeError( + "EMU fetch metadata generation requires register metadata for " + f"kernel instance '{inst_name}'" + ) + + fetch_scalar_var_symbols = sorted( + { + c["var"] + for c in fetch_scalar_cases + if c.get("kind") in ("var", "var_u32_hi") and isinstance(c.get("var"), str) + } + ) + + manifest_fetch_scalar = [] + for c in fetch_scalar_cases: + entry = { + "function": c["inst"], + "arg": c["arg"], + "kind": c["kind"], + } + if c["kind"] in ("var", "var_u32_hi"): + entry["var_symbol"] = c["var"] + elif c["kind"] == "const_u32": + entry["value"] = int(c["value"]) + source = {"mode": c.get("source", "unknown")} + if isinstance(c.get("register_name"), str): + source["register_name"] = c["register_name"] + if isinstance(c.get("register_offset"), int): + source["register_offset"] = c["register_offset"] + if c.get("register_split") is not None: + source["register_split"] = bool(c["register_split"]) + if isinstance(c.get("synthetic"), str): + source["synthetic"] = c["synthetic"] + if isinstance(c.get("derived_from_register"), str): + source["derived_from_register"] = c["derived_from_register"] + entry["source"] = source + manifest_fetch_scalar.append(entry) + + return { + "prototypes": prototypes, + "vars": vars_decl, + "wires": wires, + "stream_routes": stream_routes, + "function_calls": function_calls, + "autostart_calls": autostart_calls, + "fetch_scalar_cases": fetch_scalar_cases, + "fetch_scalar_var_symbols": fetch_scalar_var_symbols, + "ref_vars": ref_vars, + "emu_manifest": { + "manifest_schema": { + "name": "slash.sw_emu", + "version": 1, + "required_sections": ["kernels", "streams", "commands", "fetch"], + }, + "emu_protocol_version": 1, + "kernels": manifest_kernels, + "streams": [ + { + "wire": s["wire"], + "ctype": s["ctype"], + "aliases": list(s["names"]), + } + for s in stream_routes + ], + "commands": [ + "populate", + "stream_in", + "stream_out", + "call", + "wait", + "read_register", + "fetch", + "exit", + ], + "fetch": { + "schema_version": 1, + "scalar": manifest_fetch_scalar, + }, + }, + } diff --git a/linker/slashkit/emit/emu/tcl_gen.py b/linker/slashkit/emit/emu/tcl_gen.py new file mode 100644 index 00000000..dc9dd7ba --- /dev/null +++ b/linker/slashkit/emit/emu/tcl_gen.py @@ -0,0 +1,88 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +from pathlib import Path +import json +import logging + +from slashkit.emit.render import render_template +from slashkit.emit.metadata.system_map_ctx import build_system_map_context, resolve_system_map_clock +from slashkit.emit.hw.user_region.addr_ctx import build_axilite_address_context +from slashkit.emit.emu.tb_ctx import build_tb_context +from slashkit.core.command_config import LinkerConfiguration + +logger = logging.getLogger(__name__) + + +def generate_emu_tcl(config: LinkerConfiguration) -> None: + # Retrieve inputs + cfg = config.configuration + instances = {kernel.name: kernel for kernel in config.kernel_instances} + streams = cfg.streams + kernel_hls_by_type = { + kernel.name: kernel.hls_data_path for kernel in config.kernels} + + # Build test bench context + tb_ctx = build_tb_context(instances, streams, kernel_hls_by_type) + if isinstance(tb_ctx.get("emu_manifest"), dict): + tb_ctx["emu_manifest"]["project"] = config._project_name + + # 4.1) Render tb.cpp + tb_path = config.build_dir / "tb.cpp" + tb_path.parent.mkdir(parents=True, exist_ok=True) + render_template( + template="sw_emu_tb.cpp", + out_path=tb_path, + context=tb_ctx, + ) + logger.info("Rendered sw_emu tb.cpp to %s", tb_path) + + # 4.2) Render emu_manifest.json + emu_manifest_path = config.build_dir / "emu_manifest.json" + with emu_manifest_path.open("w", encoding="utf-8") as f: + json.dump(tb_ctx.get("emu_manifest", {}), f, indent=2, sort_keys=True) + logger.info("Rendered emu manifest to %s", emu_manifest_path) + + # 5) Render system map (Emulation) + axilite_ctx = build_axilite_address_context( + instances, + addr_space="S_AXILITE_INI", + base_offset=0x0202_0000_0000, + min_align=0x0001_0000, + ) + clock_hz = resolve_system_map_clock(config.clock_hz, instances) + system_map_ctx = build_system_map_context( + instances, + axilite_ctx.get("axilite_addr", []), + clock_hz=clock_hz, + platform="Emulation", + kernel_hls_by_type=kernel_hls_by_type, + network=getattr(cfg, "network", None), + ) + + system_map_path = config.build_dir / "system_map.xml" + render_template( + template="system_map.xml", + out_path=system_map_path, + context=system_map_ctx, + ) + logger.info("Rendered system map to %s", system_map_path) diff --git a/linker/slashkit/emit/hls_meta.py b/linker/slashkit/emit/hls_meta.py new file mode 100644 index 00000000..b4826b2b --- /dev/null +++ b/linker/slashkit/emit/hls_meta.py @@ -0,0 +1,141 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +from pathlib import Path +import json + + +def infer_hls_json_from_component_xml(component_xml: Path) -> Path: + """ + Given: + .../sol1/impl/ip/component.xml + .../hls/impl/ip/component.xml + Return (preferred order): + .../hls_data.json (alongside the solution dir) + .../hls/hls_data.json (sibling to sol1) + .../sol1_data.json (legacy) + """ + p = component_xml.resolve() + # ip -> impl -> + sol_dir = p.parents[2] + + # Prefer new HLS metadata if present in the solution dir. + hls_json = sol_dir / "hls_data.json" + if hls_json.exists(): + return hls_json + + # Some flows keep hls_data.json in a sibling "hls" dir when component lives in "sol1". + if sol_dir.name != "hls": + sibling_hls = sol_dir.parent / "hls" / "hls_data.json" + if sibling_hls.exists(): + return sibling_hls + + # Legacy fallback. + sol1_json = sol_dir / "sol1_data.json" + if sol1_json.exists(): + return sol1_json + + raise FileNotFoundError( + "Cannot find HLS metadata inferred from " + f"{p} -> tried: {hls_json}, {sol_dir.parent / 'hls' / 'hls_data.json'}, {sol1_json}" + ) + + +def _coerce_int(value: object) -> int | None: + if value is None: + return None + if isinstance(value, int): + return value + txt = str(value).strip() + if txt == "": + return None + try: + return int(txt, 0) + except ValueError: + return None + + +def load_hls_metadata(hls_json: Path, *, strict: bool = True) -> dict | None: + """ + Load HLS metadata JSON. In tolerant mode returns None on missing/invalid data. + """ + try: + data = json.loads(hls_json.read_text()) + except Exception: + if strict: + raise + return None + if not isinstance(data, dict): + if strict: + raise ValueError( + f"HLS metadata root must be a JSON object: {hls_json}") + return None + return data + + +def parse_hls_args(hls_data: dict) -> list[dict]: + """ + Parse hls_data.json Args into a stable list. + """ + args_obj = hls_data.get("Args", {}) + if not isinstance(args_obj, dict): + return [] + + parsed: list[dict] = [] + for arg_name, info in args_obj.items(): + if not isinstance(info, dict): + continue + refs: list[dict] = [] + hw_refs = info.get("hwRefs", []) + if isinstance(hw_refs, list): + for ref in hw_refs: + if not isinstance(ref, dict): + continue + refs.append( + { + "type": str(ref.get("type", "") or ""), + "interface": str(ref.get("interface", "") or ""), + "name": str(ref.get("name", "") or ""), + "usage": str(ref.get("usage", "") or ""), + "direction": str(ref.get("direction", "") or ""), + } + ) + + parsed.append( + { + "name": str(arg_name), + "index": _coerce_int(info.get("index")), + "direction": str(info.get("direction", "") or ""), + "src_type": str(info.get("srcType", "") or ""), + "src_size": _coerce_int(info.get("srcSize")), + "hw_refs": refs, + } + ) + + parsed.sort( + key=lambda a: ( + a["index"] is None, + a["index"] if a["index"] is not None else 10**9, + a["name"], + ) + ) + return parsed diff --git a/linker/slashkit/emit/hw/__init__.py b/linker/slashkit/emit/hw/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/hw/project_gen.py b/linker/slashkit/emit/hw/project_gen.py new file mode 100644 index 00000000..0c7ff7dc --- /dev/null +++ b/linker/slashkit/emit/hw/project_gen.py @@ -0,0 +1,409 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## +from __future__ import annotations + +import os +from enum import Enum +from pathlib import Path +import logging +import re +import shutil +import subprocess +import importlib.resources as resources +from typing import Optional, Dict +from contextlib import ExitStack + +from slashkit.emit.metadata.report_util import convert_report_utilization_to_xml +from slashkit.emit.render import export_package +from slashkit.core.command_config import LinkerConfiguration, InstallerConfiguration, CommandConfiguration + +logger = logging.getLogger(__name__) + +AVED_DESIGN_NAME = "amd_v80_gen5x8_25.1" + + +# Host toolchain flags injected by dpkg-buildpackage (e.g. -mno-omit-leaf-frame-pointer, +# -fcf-protection, -fstack-clash-protection) are not understood by the arm-xilinx-eabi +# cross-compiler used for the AVED AMC firmware. Strip them before shelling out. +_CROSS_BUILD_ENV_BLOCKLIST = ( + "CFLAGS", + "CXXFLAGS", + "CPPFLAGS", + "LDFLAGS", + "FFLAGS", + "FCFLAGS", + "OBJCFLAGS", + "OBJCXXFLAGS", + "GCJFLAGS", + "ASFLAGS", +) + + +def _clean_cross_build_env() -> dict[str, str]: + env = {k: v for k, v in os.environ.items() + if k not in _CROSS_BUILD_ENV_BLOCKLIST} + return {k: v for k, v in env.items() if not k.startswith("DEB_")} + + +def _copy_checked(src: Path, dest: Path) -> None: + if not src.exists(): + raise FileNotFoundError(f"Expected file not found: {src}") + dest.parent.mkdir(parents=True, exist_ok=True) + shutil.copy2(src, dest) + + +def _copy_files(src_files: list[Path], destination: Path) -> None: + destination.mkdir(parents=True, exist_ok=True) + for src in src_files: + dst = destination / src.name + # Allow install_dir to match the staging directory without failing on no-op copies. + if dst.exists(): + try: + if src.samefile(dst): + logger.info( + "Skipping copy because source and destination are the same file: %s", src) + continue + except FileNotFoundError: + pass + shutil.copy2(src, dst) + + +def _copy_tree(src_dir: Path, destination: Path) -> None: + target_dir = destination / src_dir.name + target_dir.parent.mkdir(parents=True, exist_ok=True) + shutil.copytree(src_dir, target_dir, dirs_exist_ok=True) + + +def _ensure_boot_device_pcie_in_bif(bif_path: Path) -> None: + if not bif_path.exists(): + raise FileNotFoundError(f"Expected BIF file not found: {bif_path}") + + lines = bif_path.read_text().splitlines() + if any(line.strip() == "boot_device { pcie }" for line in lines): + return + + # Find id=0x2 + pattern = re.compile(r"^(\s*)id\s*=\s*0x2\s*$") + for idx, line in enumerate(lines): + match = pattern.match(line) + if match: + lines.insert(idx + 1, f"{match.group(1)}boot_device {{ pcie }}") + bif_path.write_text("\n".join(lines) + "\n") + return + + raise ValueError(f"Could not find 'id = 0x2' in BIF file: {bif_path}") + + +def _generate_top_wrapper_pdi_with_bootgen(impl_dir: Path) -> Path: + bif_path = impl_dir / "top_wrapper.bif" + output_pdi = impl_dir / "top_wrapper.pdi" + + _ensure_boot_device_pcie_in_bif(bif_path) + logger.info("Running bootgen in %s to generate %s", + impl_dir, output_pdi.name) + subprocess.run( + [ + "bootgen", + "-arch", + "versal", + "-image", + bif_path.name, + "-w", + "-o", + output_pdi.name, + ], + cwd=str(impl_dir), + check=True, + ) + + if not output_pdi.exists(): + raise FileNotFoundError( + f"Expected bootgen output not found: {output_pdi}") + return output_pdi + + +def _environment_with_udev_ld_preload() -> Dict[str, str]: + """ + Create a dictionary of environment variables (based on the current one), + that works around a weird issue when running Vivado in a container. + + Details: + https://adaptivesupport.amd.com/s/question/0D54U00005Sgst2SAB/failed-batch-mode-execution-in-linux-docker-running-under-windows-host?language=en_US + https://community.flexera.com/t5/InstallAnywhere-Forum/Issues-when-running-Xilinx-tools-or-Other-vendor-tools-in-docker/m-p/245820#M10647 + """ + possible_paths = [ + Path("/lib/x86_64-linux-gnu/libudev.so.1"), Path("/lib64/libudev.so.1")] + existing_paths = [str(path) for path in possible_paths if path.is_file()] + env = dict(os.environ) + if len(existing_paths) > 0: + env["LD_PRELOAD"] = ":".join(existing_paths) + return env + + +def generate_base_pdi_with_aved(config: CommandConfiguration) -> Path: + aved_dir = config.build_dir / "AVED" + + aved_hw_dir = aved_dir / "hw" / AVED_DESIGN_NAME + aved_build_dir = aved_hw_dir / "build" + aved_fpt_dir = aved_hw_dir / "fpt" + aved_fw_profile_dir = aved_dir / "fw" / "AMC" / \ + "src" / "profiles" / "v80" + + logger.info("Starting AVED base build for %s", config.project_name) + aved_build_dir.mkdir(parents=True, exist_ok=True) + + static_impl_dir = config.build_dir / "slash.runs" / "impl_1" + regenerated_top_wrapper_pdi = _generate_top_wrapper_pdi_with_bootgen( + static_impl_dir) + _copy_checked(regenerated_top_wrapper_pdi, + aved_build_dir / "top_wrapper.pdi") + + files_to_copy = [("build_all.sh", aved_hw_dir), ("profile_hal.h", aved_fw_profile_dir), + ("pdi_combine.bif", aved_fpt_dir), (f"{AVED_DESIGN_NAME}.xsa", aved_build_dir)] + + for (file_name, target_dir) in files_to_copy: + with resources.path("slashkit.resources.aved", file_name) as in_path: + _copy_checked(in_path, target_dir / file_name) + + logger.info("Running AVED build script in %s", aved_hw_dir) + subprocess.run( + ["bash", "build_all.sh"], + cwd=str(aved_hw_dir), + env=_clean_cross_build_env(), + check=True, + ) + + aved_pdi = aved_hw_dir / f"{AVED_DESIGN_NAME}.pdi" + if not aved_pdi.exists(): + raise FileNotFoundError(f"Expected AVED output not found: {aved_pdi}") + logger.info("AVED fallback complete. Generated %s", aved_pdi) + return aved_pdi + + +def create_build_project( + config: CommandConfiguration, + action: Optional[str] = None +) -> None: + log_path = config.build_dir / "vivado.log" + + with resources.path("slashkit.resources.base.scripts", "create_project.tcl") as tcl_path: + if not tcl_path.exists(): + raise FileNotFoundError( + f"create_project.tcl not found: {tcl_path}") + cmd = [ + config.vivado_bin, + "-mode", + "batch", + "-nojournal", + "-log", + str(log_path), + "-source", + str(tcl_path), + "-tclargs", + config.project_name, + config.ip_repository + ] + if action: + cmd.append(action) + + subprocess.run(cmd, cwd=str(config.build_dir), check=True, + env=_environment_with_udev_ld_preload()) + + +class RM_KIND(Enum): + SLASH_PROJECT = "slash" + SERVICE_LAYER = "service_layer" + + +def _run_rm_build(config: LinkerConfiguration, rm_kind: RM_KIND) -> None: + # Copy all base IP cores into the ip repository + config.ip_repository.mkdir(parents=True) + export_package("slashkit.resources.base.iprepo", + config.ip_repository / "slash_base") + + if rm_kind == RM_KIND.SLASH_PROJECT: + # Copy all user kernels into the ip repository + for kernel in config.kernels: + shutil.copytree(kernel.component_xml_path.parent, + config.ip_repository / kernel.name) + + logs_dir = config.build_dir / "logs" + image_out_dir = config.build_dir / "images" + rm_work_dir = config.build_dir / f"{rm_kind.value}_rm" + + logs_dir.mkdir(parents=True, exist_ok=True) + image_out_dir.mkdir(parents=True, exist_ok=True) + rm_work_dir.mkdir(parents=True, exist_ok=True) + + if rm_kind == RM_KIND.SERVICE_LAYER: + tcl_name = "service_layer_build.tcl" + static_shell_dcp_name = "static_shell_service_layer.dcp" + base_bd_package = "slashkit.resources.static_shell.service_layer" + base_bd_name = "service_layer.bd" + log_path = logs_dir / "service_layer_build.log" + else: + tcl_name = "slash_project_build.tcl" + static_shell_dcp_name = "static_shell_slash.dcp" + base_bd_package = "slashkit.resources.static_shell.slash_base" + base_bd_name = "slash_base.bd" + log_path = logs_dir / "slash_project_build.log" + + with ExitStack() as stack: + tcl_path = stack.enter_context( + resources.path("slashkit.resources.base.scripts", tcl_name) + ) + static_shell_dcp_path = stack.enter_context( + resources.path("slashkit.resources.static_shell", + static_shell_dcp_name) + ) + base_bd_path = stack.enter_context( + resources.path(base_bd_package, base_bd_name) + ) + + cmd = [ + config.vivado_bin, + "-mode", + "batch", + "-nojournal", + "-log", + str(log_path), + "-source", + str(tcl_path), + "-tclargs", + "--project-name", + config.project_name, + "--ip-repo", + str(config.ip_repository), + "--static-shell-dcp", + str(static_shell_dcp_path), + "--base-bd", + str(base_bd_path), + "--linker-results-dir", + str(config.build_dir), + "--rm-work-dir", + str(rm_work_dir), + "--artifact-out-dir", + str(image_out_dir), + "--jobs", + str(config.n_jobs), + ] + if rm_kind == RM_KIND.SLASH_PROJECT: + util_report_path = config.build_dir / \ + f"report_utilization_{config.project_name}.txt" + util_report_path.parent.mkdir(parents=True, exist_ok=True) + cmd.extend(["--util-report-file", str(util_report_path)]) + + for path in config.pre_synth_tcls: + cmd.extend(["--pre-synth-tcl", str(path)]) + + if rm_kind == RM_KIND.SERVICE_LAYER: + opt_post_tcl = stack.enter_context( + resources.path( + "slashkit.resources.base.constraints.service_layer.eth", "service_layer_eth.opt.post.tcl") + ) + cmd.extend(["--opt-post-tcl", str(opt_post_tcl)]) + + subprocess.run(cmd, cwd=str(config.build_dir), check=True, + env=_environment_with_udev_ld_preload()) + + if rm_kind == RM_KIND.SLASH_PROJECT: + pdi_out_path = image_out_dir / \ + f"top_i_slash_slash_{config.project_name}_inst_0_partial.pdi" + else: + pdi_out_path = image_out_dir / \ + f"top_i_service_layer_service_layer_{config.project_name}_inst_0_partial.pdi" + + if not pdi_out_path.is_file(): + raise FileNotFoundError( + f"{str(pdi_out_path)} is missing! Check {str(log_path)} for errors!") + + +def build_service_layer_rm(config: LinkerConfiguration) -> None: + _run_rm_build(config, RM_KIND.SERVICE_LAYER) + + +def build_slash_rm(config: LinkerConfiguration) -> None: + _run_rm_build(config, RM_KIND.SLASH_PROJECT) + + +def install_static_shell(config: InstallerConfiguration) -> None: + static_shell_dir = config.out_dir / "static_shell" + static_shell_dir.mkdir(parents=True, exist_ok=True) + + # Cloning the AVED repository into the build directory + # We're doing this early so that errors are caught *before* the 10-hour Vivado run! + subprocess.run([ + "git", "clone", + "--recurse-submodules", + "-b", config.aved_ref, + config.aved_repo, + config.build_dir / "AVED" + ], check=True) + + create_build_project(config) + + impl_dir = config.build_dir / "slash.runs" / "impl_1" + dcp_sources = ( + impl_dir / "top_wrapper_routed_bb.dcp", + impl_dir / "static_shell_slash.dcp", + impl_dir / "static_shell_service_layer.dcp", + ) + for src in dcp_sources: + if not src.exists(): + raise FileNotFoundError( + f"Expected install artifact not found: {src}") + _copy_files(list(dcp_sources), static_shell_dir) + + src_dirs = config.build_dir / "slash.srcs" / "sources_1" / "bd" + for src_dir in (src_dirs / "slash_base", src_dirs / "service_layer"): + if not src_dir.is_dir(): + raise FileNotFoundError( + f"Expected install BD directory not found: {src_dir}") + _copy_tree(src_dir, static_shell_dir) + + aved_pdi_path = generate_base_pdi_with_aved(config) + if not aved_pdi_path.exists(): + raise FileNotFoundError( + f"Expected AVED PDI not found in results/base: {aved_pdi_path}") + _copy_files([aved_pdi_path], static_shell_dir) + + def add_init_files(path: Path): + (path / "__init__.py").touch() + for sub_path in path.iterdir(): + if not sub_path.is_dir(): + continue + add_init_files(sub_path) + add_init_files(static_shell_dir) + + +def generate_util_report(config: CommandConfiguration) -> None: + report_path = config.build_dir / \ + f"report_utilization_{config.project_name}.txt" + xml_path = config.build_dir / \ + f"report_utilization_{config.project_name}.xml" + logger.info("Generating utilization report XML for project %s", + config.project_name) + logger.info("Utilization report input: %s", report_path) + logger.info("Utilization report output: %s", xml_path) + if not report_path.exists(): + raise FileNotFoundError(report_path) + convert_report_utilization_to_xml(report_path, xml_path) + logger.info("Utilization report XML generation complete for %s", + config.project_name) diff --git a/linker/slashkit/emit/hw/service_region/__init__.py b/linker/slashkit/emit/hw/service_region/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/hw/service_region/network_ctx.py b/linker/slashkit/emit/hw/service_region/network_ctx.py new file mode 100644 index 00000000..a789d8c7 --- /dev/null +++ b/linker/slashkit/emit/hw/service_region/network_ctx.py @@ -0,0 +1,169 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +import re +from typing import Dict, List, Tuple +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + +# eth_.(tx0|tx1|rx0|rx1) +_ETH_EP_RE = re.compile(r"^eth_(\d+)\.(tx0|tx1|rx0|rx1)$", re.IGNORECASE) + + +def _map_eth_tx_pin(eth_idx: int, lane: int) -> str: + k = eth_idx * 2 + lane + return f"/dcmac_axis_noc_{k}/S00_AXIS" + + +def _map_eth_rx_pin(eth_idx: int, lane: int) -> str: + k = eth_idx * 2 + lane + return f"/dcmac_axis_noc_s_{k}/M00_AXIS" + + +def _is_eth_endpoint(s: str) -> bool: + return _ETH_EP_RE.match(s or "") is not None + + +def _parse_eth_endpoint(s: str) -> Tuple[int, str]: + m = _ETH_EP_RE.match(s) + if not m: + raise ValueError( + f"Invalid eth endpoint '{s}'. Expected eth_<0..3>.(tx0|tx1|rx0|rx1)") + return int(m.group(1)), m.group(2).lower() + + +def _port_norm(s): return re.sub(r"[^a-z0-9]", "", s.lower()) + + +def _resolve_port_name(kernel, requested: str) -> str: + # exact + if requested in kernel.ports: + return requested + # case-insensitive + low = {n.lower(): n for n in kernel.ports.keys()} + rlow = requested.lower() + if rlow in low: + return low[rlow] + # underscore/char-insensitive (remove non-alnum) + norm_map = {_port_norm(n): n for n in kernel.ports.keys()} + rnorm = _port_norm(requested) + if rnorm in norm_map: + return norm_map[rnorm] + raise KeyError( + f"Kernel '{kernel.name}' has no port named '{requested}'. " + f"Available: {list(kernel.ports.keys())}" + ) + +# -------------------------------------------------------------------- + + +def build_network_axis_context( + instances: Dict[str, KernelInstance], + streams, + net, # cfg.network with .enabled_eth +): + """ + Returns: + { + "axis_to_fabric": [{ "src_pin": "/", "dst_pin": ""}], + "axis_from_fabric": [{ "src_pin": "", "dst_pin": "/"}], + "streams_leftover": [ non-eth streams ] + } + """ + to_fabric: List[dict] = [] + from_fabric: List[dict] = [] + leftover = [] + + for s in streams: + src_is_eth = _is_eth_endpoint(f"{s.src_inst}.{s.src_port}") + dst_is_eth = _is_eth_endpoint(f"{s.dst_inst}.{s.dst_port}") + + if not src_is_eth and not dst_is_eth: + leftover.append(s) + continue + if src_is_eth and dst_is_eth: + raise ValueError( + f"stream_connect cannot be eth->eth: '{s.src_inst}.{s.src_port} : {s.dst_inst}.{s.dst_port}'") + + if dst_is_eth: + # inst -> fabric TX + if s.src_inst not in instances: + raise KeyError( + f"Unknown instance '{s.src_inst}' in stream '{s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}'") + src_inst = instances[s.src_inst] + # robust port resolution + src_port = _resolve_port_name(src_inst.kernel, s.src_port) + src_p = src_inst.kernel.port(src_port) + if src_p.ptype != BusType.AXIS: + raise ValueError( + f"{s.src_inst}.{src_port} is not AXIS (got {src_p.ptype.name})") + + eth_idx, lane_name = _parse_eth_endpoint( + f"{s.dst_inst}.{s.dst_port}") + if eth_idx not in getattr(net, "enabled_eth", set()): + raise ValueError( + f"eth_{eth_idx} is not enabled in [network] but is referenced in stream_connect") + + lane = 0 if lane_name == "tx0" else 1 if lane_name == "tx1" else None + if lane is None: + raise ValueError( + f"Only tx0/tx1 valid on fabric TX, got '{lane_name}'") + + dst_pin = _map_eth_tx_pin(eth_idx, lane) + to_fabric.append({ + "src_pin": f"{s.src_inst}/{src_port}", + "dst_pin": dst_pin, + }) + + else: + # fabric RX -> inst + if s.dst_inst not in instances: + raise KeyError( + f"Unknown instance '{s.dst_inst}' in stream '{s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}'") + dst_inst = instances[s.dst_inst] + dst_port = _resolve_port_name(dst_inst.kernel, s.dst_port) + dst_p = dst_inst.kernel.port(dst_port) + if dst_p.ptype != BusType.AXIS: + raise ValueError( + f"{s.dst_inst}.{dst_port} is not AXIS (got {dst_p.ptype.name})") + + eth_idx, lane_name = _parse_eth_endpoint( + f"{s.src_inst}.{s.src_port}") + if eth_idx not in getattr(net, "enabled_eth", set()): + raise ValueError( + f"eth_{eth_idx} is not enabled in [network] but is referenced in stream_connect") + + lane = 0 if lane_name == "rx0" else 1 if lane_name == "rx1" else None + if lane is None: + raise ValueError( + f"Only rx0/rx1 valid on fabric RX, got '{lane_name}'") + + src_pin = _map_eth_rx_pin(eth_idx, lane) + from_fabric.append({ + "src_pin": src_pin, + "dst_pin": f"{s.dst_inst}/{dst_port}", + }) + + return { + "axis_to_fabric": to_fabric, + "axis_from_fabric": from_fabric, + "streams_leftover": leftover, + } diff --git a/linker/slashkit/emit/hw/service_region/service_layer_ctx.py b/linker/slashkit/emit/hw/service_region/service_layer_ctx.py new file mode 100644 index 00000000..98d9e510 --- /dev/null +++ b/linker/slashkit/emit/hw/service_region/service_layer_ctx.py @@ -0,0 +1,162 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from typing import Set, Dict, Any, List +from dataclasses import dataclass +from pathlib import Path + + +@dataclass(frozen=True) +class NetworkSpecView: + enabled_eth: Set[int] + + +def build_service_layer_context(net) -> dict: + """ + Map enabled eth_* to DCMAC enables: + qsfp_0_n_1 -> DCMAC0 ⇔ eth_0 + qsfp_2_n_3 -> DCMAC1 ⇔ eth_2 + Dual-QSFP knobs remain 0 for now. + """ + enabled = getattr(net, "enabled_eth", set()) + dc0 = 1 if 0 in enabled else 0 + dc1 = 1 if 2 in enabled else 0 + return { + "needs_dcmac": (dc0 == 1 or dc1 == 1), + "dc_enable_0": dc0, + "dc_enable_1": dc1, + "dual_qsfp_0": 0, + "dual_qsfp_1": 0, + } + + +def dcmac_paths(dcmac_dir: Path) -> Dict[str, Any]: + """ + Resolve absolute paths for service-layer assets regardless of CWD. + """ + dcmac_tcl = dcmac_dir / "tcl" / "dcmac.tcl" + dcmac_hdl = dcmac_dir / "hdl" + + # add/remove files as needed + hdl_files = [ + "axis_seg_to_unseg_converter.v", + "clock_to_clock_bus.v", + "dcmac200g_ctl_port.v", + "serdes_clock.v", + "syncer_reset.v", + ] + + return { + "dcmac_tcl": str(dcmac_tcl), + "dcmac_hdl_dir": str(dcmac_hdl), + "dcmac_hdl_files": [str(dcmac_hdl / f) for f in hdl_files], + } + + +def build_service_axilite_ctx(net) -> Dict[str, Any]: + """ + Build SmartConnect context for service_layer: + - NUM_CLKS: 2 (aclk0, aclk1) + - NUM_SI: 1 (drives from top 'S_AXILITE') + - NUM_MI: # of enabled DCMAC hier blocks (qsfp_0_n_1, qsfp_2_n_3) + - MI targets: /s_axi + + We map eth_0 -> qsfp_0_n_1, eth_2 -> qsfp_2_n_3 (as per your convention). + """ + enabled = getattr(net, "enabled_eth", set()) + + qsfp_blocks: list[str] = [] + mi_targets: list[str] = [] + + if 0 in enabled: + qsfp_blocks.append("qsfp_0_n_1") + mi_targets.append("qsfp_0_n_1/s_axi") + if 2 in enabled: + qsfp_blocks.append("qsfp_2_n_3") + mi_targets.append("qsfp_2_n_3/s_axi") + + num_mi = len(mi_targets) + + return { + # smartconnect presence + "sl_have_xbar": num_mi > 0, + + # properties + "sl_num_clks": 1, + "sl_num_si": 1, + "sl_num_mi": num_mi, + + # wiring + # top-level service_layer AXI-Lite interface + "sl_si_src_if": "axi_noc_0/M00_AXI", + "sl_clk0": "service_clk", # service_layer clock pins + "sl_rstn": "ilreduced_logic_0/Res", + + # MI endpoints and qsfp blocks for clk/rst tie-off + # e.g. ["qsfp_0_n_1/s_axi", "qsfp_2_n_3/s_axi"] + "sl_mi_targets": mi_targets, + "sl_qsfp_blocks": qsfp_blocks, # e.g. ["qsfp_0_n_1", "qsfp_2_n_3"] + + # preferred instance names + "sl_smartconnect_path": "smartconnect_0", + "sl_smartconnect_name": "sl_xbar", + } + + +# emit/service_layer_ctx.py + + +def build_service_noc_axis_ctx(net) -> Dict[str, Any]: + """ + Build AXIS links between qsfp_* and dummy NoC endpoints inside 'service_layer'. + + Mapping (even indices only): + - eth_0 -> qsfp_0_n_1 uses X = 0 + - eth_2 -> qsfp_2_n_3 uses X = 4 + + Connections: + Fabric -> MAC: dummy_noc_X/M00_AXIS -> qsfp_*/S_AXIS_0 + MAC -> Fabric: qsfp_*/M_AXIS_0 -> dummy_noc_m_X/S00_AXIS + """ + enabled = getattr(net, "enabled_eth", set()) + links: List[dict] = [] + + if 0 in enabled: + links.append({ # fabric -> MAC + "src_pin": "dummy_noc_0/M00_AXIS", + "dst_pin": "qsfp_0_n_1/S_AXIS_0", + }) + links.append({ # MAC -> fabric + "src_pin": "qsfp_0_n_1/M_AXIS_0", + "dst_pin": "dummy_noc_m_0/S00_AXIS", + }) + + if 2 in enabled: + links.append({ + "src_pin": "dummy_noc_4/M00_AXIS", + "dst_pin": "qsfp_2_n_3/S_AXIS_0", + }) + links.append({ + "src_pin": "qsfp_2_n_3/M_AXIS_0", + "dst_pin": "dummy_noc_m_4/S00_AXIS", + }) + + return {"sl_axis_noc_links": links} diff --git a/linker/slashkit/emit/hw/service_region/stream_ctx.py b/linker/slashkit/emit/hw/service_region/stream_ctx.py new file mode 100644 index 00000000..fd684f44 --- /dev/null +++ b/linker/slashkit/emit/hw/service_region/stream_ctx.py @@ -0,0 +1,93 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +import re +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + +_ETH_EP_RE = re.compile(r"^eth_(\d+)\.(tx0|tx1|rx0|rx1)$", re.IGNORECASE) +def _port_norm(s): return re.sub(r"[^a-z0-9]", "", s.lower()) + + +def _resolve_port_name(kernel, requested: str) -> str: + if requested in kernel.ports: + return requested + low = {n.lower(): n for n in kernel.ports.keys()} + rlow = requested.lower() + if rlow in low: + return low[rlow] + norm_map = {_port_norm(n): n for n in kernel.ports.keys()} + rnorm = _port_norm(requested) + if rnorm in norm_map: + return norm_map[rnorm] + raise KeyError( + f"Kernel '{kernel.name}' has no port named '{requested}'. " + f"Available: {list(kernel.ports.keys())}" + ) + + +def build_stream_connect_context( + instances: Dict[str, KernelInstance], + streams: List[object], +) -> dict: + """ + Convert config 'stream_connect=src_inst.src_port:dst_inst.dst_port' + into {src_pin, dst_pin}, validating AXIS. + NOTE: pass ONLY non-eth streams here (use build_network_axis_context first). + """ + out: List[dict] = [] + + for s in streams: + # prevent accidental eth_* usage here + if _ETH_EP_RE.match(f"{s.src_inst}.{s.src_port}") or _ETH_EP_RE.match(f"{s.dst_inst}.{s.dst_port}"): + raise ValueError( + "eth_* endpoint seen in generic builder. " + "Call build_network_axis_context() first and pass only its 'streams_leftover' here." + ) + + if s.src_inst not in instances: + raise KeyError(f"stream_connect: unknown instance '{s.src_inst}'") + if s.dst_inst not in instances: + raise KeyError(f"stream_connect: unknown instance '{s.dst_inst}'") + + src_inst = instances[s.src_inst] + dst_inst = instances[s.dst_inst] + + src_port = _resolve_port_name(src_inst.kernel, s.src_port) + dst_port = _resolve_port_name(dst_inst.kernel, s.dst_port) + + src_p = src_inst.kernel.port(src_port) + dst_p = dst_inst.kernel.port(dst_port) + + if src_p.ptype != BusType.AXIS: + raise ValueError( + f"stream_connect: {s.src_inst}.{src_port} is not AXIS (got {src_p.ptype.name})") + if dst_p.ptype != BusType.AXIS: + raise ValueError( + f"stream_connect: {s.dst_inst}.{dst_port} is not AXIS (got {dst_p.ptype.name})") + + out.append({ + "src_pin": f"{s.src_inst}/{src_port}", + "dst_pin": f"{s.dst_inst}/{dst_port}", + }) + + return {"axis_streams": out} diff --git a/linker/slashkit/emit/hw/tcl_gen.py b/linker/slashkit/emit/hw/tcl_gen.py new file mode 100644 index 00000000..a472012d --- /dev/null +++ b/linker/slashkit/emit/hw/tcl_gen.py @@ -0,0 +1,352 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +import logging +import re + +from slashkit.emit.render import render_template, export_package +from slashkit.emit.hw.user_region.kernel_ctx import build_kernel_add_context +from slashkit.emit.hw.user_region.smartconnect_ctx import build_axilite_smartconnect_context +from slashkit.emit.hw.user_region.hbm_ctx import build_hbm_smartconnect_context +from slashkit.emit.hw.user_region.ddr_ctx import build_ddr_smartconnect_context +from slashkit.emit.hw.user_region.mem_ctx import build_mem_smartconnect_context +from slashkit.emit.hw.user_region.virt_ctx import build_virt_smartconnect_context +from slashkit.emit.hw.user_region.terminator_ctx import build_axi_terminators_context +from slashkit.emit.hw.user_region.terminator_ctx import build_ddr_noc_terminators +from slashkit.emit.hw.user_region.terminator_ctx import build_mem_noc_terminators +from slashkit.emit.hw.user_region.terminator_ctx import build_virt_noc_terminators +from slashkit.emit.hw.user_region.terminator_ctx import build_host_noc_terminator +from slashkit.emit.hw.service_region.network_ctx import build_network_axis_context +from slashkit.emit.hw.service_region.stream_ctx import build_stream_connect_context +from slashkit.emit.hw.user_region.host_ctx import build_host_smartconnect_context +from slashkit.emit.hw.user_region.addr_ctx import build_axilite_address_context +from slashkit.emit.hw.user_region.param_ctx import build_data_width_param_context +from slashkit.emit.metadata.system_map_ctx import build_system_map_context, resolve_system_map_clock +from slashkit.emit.hw.service_region.service_layer_ctx import * + +from slashkit.core.command_config import LinkerConfiguration + +logger = logging.getLogger(__name__) + +_RX_SRC_PIN_RE = re.compile(r"^/?dcmac_axis_noc_s_(\d+)/M00_AXIS$") + + +def _collect_used_targets(ctx: dict) -> set[str]: + """! @brief Collect used NoC/BD targets from a rendered context. + + @param ctx Render context dictionary. + @return Set of target names/pins that are already used. + """ + used: set[str] = set() + + # HBM uses BD ports (HBM_AXI_XX) via root MI -> port + for o in ctx.get("hbm_root_out", []): + used.add(o["dst_port"]) # e.g., HBM_AXI_00 + + # DDR uses NoC pins + for item in ctx.get("ddr_direct", []): + used.add(item["dst_pin"]) # e.g., /ddr_noc_0/S00_AXI + for item in ctx.get("ddr_smart_roots", []): + used.add(item["dst_pin"]) + + # MEM (VNOC) uses NoC pins + for item in ctx.get("mem_direct", []): + used.add(item["dst_pin"]) # e.g., /hbm_vnoc_00/S00_AXI + for item in ctx.get("mem_smart_roots", []): + used.add(item["dst_pin"]) + + # VIRT now also uses NoC pins (noc_virt_00..03/S00_AXI) + for item in ctx.get("virt_direct", []): + used.add(item["dst_pin"]) + for item in ctx.get("virt_smart_roots", []): + used.add(item["dst_pin"]) + + # HOST (QDMA bridge) uses NoC pin + for item in ctx.get("host_direct", []): + used.add(item["dst_pin"]) + for item in ctx.get("host_smart_roots", []): + used.add(item["dst_pin"]) + + return used + + +def print_memory_maps(k): + """! @brief Print memory map details for a kernel. + + @param k Kernel object with memory_maps metadata. + """ + if not getattr(k, "memory_maps", None): + print(" (no memory maps)") + return + print(" Memory maps:") + for mm in k.memory_maps: + print(f" - map: {mm.name}") + for ab in mm.address_blocks: + ba = f"0x{ab.base_address:X}" + rg = f"0x{ab.range:X}" + print( + f" block {ab.name}: base={ba} range={rg} width={ab.width} usage={ab.usage or '-'} access={ab.access or '-'}") + if ab.offset_base_param or ab.offset_high_param: + print( + f" params: base_param={ab.offset_base_param or '-'} high_param={ab.offset_high_param or '-'}") + if ab.registers: + for r in ab.registers: + off = f"0x{r.address_offset:X}" + print( + f" reg {r.name}: off={off} size={r.size} access={r.access or '-'} reset={('0x%X' % r.reset_value) if r.reset_value is not None else '-'}") + if r.fields: + for f in r.fields: + rng = f"[{f.bit_offset + f.bit_width - 1}:{f.bit_offset}]" + print(f" - {f.name} {rng} access={f.access or '-'}" + f" reset={('0x%X' % f.reset_value) if f.reset_value is not None else '-'}") + + +def print_kernel(k): + """! @brief Print a kernel summary to stdout. + + @param k Kernel object to print. + """ + print(f"\nKernel: {k.name}") + for p in k.ports.values(): + print(f" - {p.name:24s} {p.ptype.name:9s} width={p.width}") + print_memory_maps(k) + + +def print_cfg(cfg): + """! @brief Print connectivity config summary to stdout. + + @param cfg Connectivity config object. + """ + print("\n[connectivity] nk entries:") + if cfg.nk: + for nk in cfg.nk: + print( + f" - {nk.kernel_type}: count={nk.count}, names={nk.instance_names}") + else: + print(" (none)") + + print("\n[connectivity] stream_connect:") + if cfg.streams: + for s in cfg.streams: + print(f" - {s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}") + else: + print(" (none)") + + print("\n[connectivity] sp mappings:") + if cfg.sps: + for sp in cfg.sps: + print( + f" - {sp.inst}.{sp.port} -> {sp.target.domain}{sp.target.index}") + else: + print(" (none)") + + print("\n[clock] specs:") + if cfg.clocks: + for c in cfg.clocks: + print(f" - {c.inst}: {c.freq_hz} Hz") + else: + print(" (none)") + + debug = getattr(cfg, "debug", None) + debug_nets = getattr(debug, "nets", []) if debug is not None else [] + print("\n[debug] nets:") + if debug_nets: + for n in debug_nets: + print(f" - {n.inst}.{n.port}") + else: + print(" (none)") + + +def print_instances(instances, stream_edges): + """! @brief Print instantiated kernels and stream edges to stdout. + + @param instances Mapping of instance name to instance object. + @param stream_edges Stream edge list. + """ + print("\nInstances created:") + if not instances: + print(" (none)") + return + for name, inst in instances.items(): + print(f" - {name} : kernel={inst.kernel.name}") + if inst.params: + clk = inst.params.get("clock_hz") + if clk is not None: + print(f" clock_hz: {clk}") + mem_sp = inst.params.get("mem_sp") + if mem_sp: + for port, tgt in mem_sp.items(): + idx = "" if tgt.get("index") is None else str(tgt["index"]) + print(f" sp: {port} -> {tgt['domain']}{idx}") + others = {k: v for k, v in inst.params.items() if k not in { + "clock_hz", "mem_sp"}} + for k, v in others.items(): + print(f" {k}: {v}") + + print("\nStream connections to wire:") + if stream_edges: + for s in stream_edges: + print(f" - {s.src_inst}.{s.src_port} -> {s.dst_inst}.{s.dst_port}") + else: + print(" (none)") + + +def print_bd_ports(bd): + """! @brief Print block design ports to stdout. + + @param bd Block design ports container. + """ + print("\nBlock Design Ports:") + if not bd.ports: + print(" (none)") + return + for logical in sorted(bd.ports.keys()): + for p in bd.get_all(logical): + dom = "" if p.domain is None else str(p.domain) + idx = "" if p.index is None else str(p.index) + wid = "" if p.width is None else str(p.width) + rtl = "" if p.rtl_name is None else p.rtl_name + print( + f" - {logical:12s} -> rtl={rtl:20s} {p.ptype.name:9s} width={wid:>4s} domain={dom:>4s} index={idx:>2s}") + + +def generate_tcl(config: LinkerConfiguration) -> None: + """! @brief Generate Tcl and system map artifacts from inputs. + + @param args Parsed CLI arguments. + """ + bd = config.block_design_ports + cfg = config.configuration + instances = {kernel.name: kernel for kernel in config.kernel_instances} + streams = cfg.streams + kernel_hls_by_type = { + kernel.name: kernel.hls_data_path for kernel in config.kernels} + + ctx = build_kernel_add_context(instances) + ctx.update(build_data_width_param_context(instances)) + ctx.update(build_axilite_smartconnect_context(instances)) + ctx.update(build_hbm_smartconnect_context(instances, bd, max_si=16)) + ctx.update(build_ddr_smartconnect_context(instances, max_si=16)) + ctx.update(build_mem_smartconnect_context( + instances, num_mem_ports=8, max_si=16)) + ctx.update(build_host_smartconnect_context(instances, bd, max_si=16)) + ctx.update(build_virt_smartconnect_context(instances, bd, max_si=16)) + net_ctx = build_network_axis_context(instances, streams, cfg.net) + ctx.update({ + # inst.AXIS -> /dcmac_axis_noc_k/S00_AXIS + "axis_to_fabric": net_ctx["axis_to_fabric"], + # /dcmac_axis_noc_s_k/M00_AXIS -> inst.AXIS + "axis_from_fabric": net_ctx["axis_from_fabric"], + }) + used_rx_slots: set[int] = set() + for e in net_ctx.get("axis_from_fabric", []): + m = _RX_SRC_PIN_RE.match(str(e.get("src_pin", "")).strip()) + if m: + used_rx_slots.add(int(m.group(1))) + + # Tie-off RX NoC tready only for unused RX slots (0..7). + # If no RX is used, we tie all 8. + dcmac_rx_tready_tie_slots = [i for i in range(8) if i not in used_rx_slots] + ctx["dcmac_rx_tready_tie_pins"] = [ + f"dcmac_axis_noc_s_{i}/M00_AXIS_tready" for i in dcmac_rx_tready_tie_slots + ] + + ctx.update(build_stream_connect_context( + instances, net_ctx["streams_leftover"])) + + used_targets = _collect_used_targets(ctx) + + for s in ctx.get("hbm_sc_sinks", []): + used_targets.add(s["dst"]) + + terms_generic = build_axi_terminators_context( + bd, used_targets) # HBM/VIRT BD ports only + terms_ddr_noc = build_ddr_noc_terminators( + used_targets, num_ddr=4, noc_pin_fmt="/ddr_noc_{index}/S00_AXI") + terms_mem_noc = build_mem_noc_terminators( + used_targets, num_mem=8, noc_pin_fmt="/hbm_vnoc_0{index}/S00_AXI") + terms_virt_noc = build_virt_noc_terminators( + used_targets, num_virt=4, noc_pin_fmt="/noc_virt_0{index}/S00_AXI") + terms_host_noc = build_host_noc_terminator(used_targets) + + ctx["axi_terminators"] = ( + terms_generic.get("axi_terminators", []) + + terms_ddr_noc.get("axi_terminators", []) + + terms_mem_noc.get("axi_terminators", []) + + terms_virt_noc.get("axi_terminators", []) + + terms_host_noc.get("axi_terminators", []) + ) + axilite_ctx = build_axilite_address_context( + instances, + addr_space="S_AXILITE_INI", + base_offset=0x0202_0000_0000, + min_align=0x0001_0000, + ) + ctx.update(axilite_ctx) + ctx["project_name"] = config.project_name + ctx["slash_bd_name"] = f"slash_{config.project_name}" + out_path = config.build_dir / "slash.tcl" # slash.tcl + render_template( + template="slash.tcl", + out_path=out_path, + context=ctx, + ) + logger.info("Rendered Tcl to %s", out_path) + + clock_hz = resolve_system_map_clock(config.clock_hz, instances) + system_map_ctx = build_system_map_context( + instances, + axilite_ctx.get("axilite_addr", []), + clock_hz=clock_hz, + platform="Hardware", + kernel_hls_by_type=kernel_hls_by_type, + network=getattr(cfg, "network", None), + ) + system_map_out = config.build_dir / "system_map.xml" + render_template( + template="system_map.xml", + out_path=system_map_out, + context=system_map_ctx, + ) + logger.info("Rendered system map to %s", system_map_out) + + svc_ctx = {} + svc_ctx.update(build_service_layer_context(cfg.net)) + svc_ctx.update(build_service_axilite_ctx(cfg.net) + ) # SmartConnect + MI targets + svc_ctx.update(build_service_noc_axis_ctx(cfg.net)) + + svc_ctx["project_name"] = config.project_name + svc_ctx["service_layer_bd_name"] = f"service_layer_{config.project_name}" + + # --- Render service-layer Tcl --- + svc_out = config.build_dir / "service_layer.tcl" + + dcmac_dir = config.build_dir / "dcmac" + export_package("slashkit.resources.dcmac", dcmac_dir) + + svc_ctx.update(dcmac_paths(dcmac_dir)) + render_template( + template="service_layer.tcl", + out_path=svc_out, + context=svc_ctx, + ) + + logger.info("Rendered service layer Tcl to %s", svc_out) diff --git a/linker/slashkit/emit/hw/user_region/__init__.py b/linker/slashkit/emit/hw/user_region/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/hw/user_region/addr_ctx.py b/linker/slashkit/emit/hw/user_region/addr_ctx.py new file mode 100644 index 00000000..c00f66df --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/addr_ctx.py @@ -0,0 +1,104 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +def _align_up(x: int, a: int) -> int: + return (x + (a - 1)) & ~(a - 1) + + +def _register_block_for_axilite(inst: KernelInstance, busif: str): + """ + Find the 'register' usage addressBlock for an AXI-Lite bus interface. + Heuristics: + - memoryMap.name equals busif; use its first 'register' addressBlock + - otherwise, first 'register' block in any map + """ + k = inst.kernel + mmaps = getattr(k, "memory_maps", []) or [] + + for mm in mmaps: + if mm.name and mm.name.lower() == busif.lower(): + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register": + return ab + for mm in mmaps: + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register": + return ab + + raise ValueError( + f"No AXI-Lite register addressBlock found in component.xml for " + f"kernel '{k.name}' bus interface '{busif}'" + ) + + +def build_axilite_address_context( + instances: Dict[str, KernelInstance], + *, + addr_space: str = "S_AXILITE_INI", + base_offset: int = 0x0202_0000_0000, # your example + min_align: int = 0x0000_0100 # 256Bx alignment +) -> dict: + """ + Returns: + { + "axilite_addr": [ + { "inst": "...", "busif": "S_AXI_CONTROL", "segment": "", + "offset": 0x..., "range": 0x..., "addr_space": "S_AXILITE_INI" }, + ... + ] + } + """ + # Build a stable list (sorted for determinism) + items: List[dict] = [] + next_off = base_offset + + for iname in sorted(instances.keys()): + inst = instances[iname] + # For each AXI-Lite interface on this kernel + for p in inst.kernel.ports_of_type(BusType.AXILITE): + # Derive both segment name and range from the register addressBlock in component.xml. + ab = _register_block_for_axilite(inst, p.name) + rg = int(ab.range) + if rg <= 0: + raise ValueError( + f"AXI-Lite register addressBlock '{ab.name}' for kernel '{inst.kernel.name}' " + f"bus interface '{p.name}' has invalid range {rg}" + ) + # Hardware address windows should be aligned to their size (and at least min_align) + align = max(min_align, rg) + next_off = _align_up(next_off, align) + + items.append({ + "inst": iname, + "busif": p.name, + "segment": ab.name, + "offset": next_off, + "range": rg, + "addr_space": addr_space, + }) + next_off += _align_up(rg, align) + + return {"axilite_addr": items} diff --git a/linker/slashkit/emit/hw/user_region/ddr_ctx.py b/linker/slashkit/emit/hw/user_region/ddr_ctx.py new file mode 100644 index 00000000..9e14439e --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/ddr_ctx.py @@ -0,0 +1,101 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +def build_ddr_smartconnect_context( + instances: Dict[str, KernelInstance], + *, + max_si: int = 16, + base_name: str = "sc_ddr", + # absolute path to NoC slave pin + noc_pin_fmt: str = "/ddr_noc_{index}/S00_AXI", +) -> dict: + """ + Plan SmartConnect reduction per DDR. If only 1 source -> direct connect to + '/ddr_noc_/S00_AXI'. If >1, build a reduction tree with nodes having up to + 'max_si' SIs and 1 MI. + + Returns keys for the template: + - ddr_direct: [{src_pin, dst_pin}] + - ddr_smart_nodes: [{name, num_si, si:[{slot, src}], ...}] + - ddr_smart_roots: [{sc_name, dst_pin}] + """ + # 1) Collect all AXI4FULL kernel pins targeting DDR + by_ddr: Dict[int, List[str]] = defaultdict(list) + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") == "DDR" and tgt.get("index") is not None: + if inst.kernel.port(k_port).ptype == BusType.AXI4FULL: + by_ddr[int(tgt["index"])].append(f"{inst.name}/{k_port}") + + ddr_direct: List[dict] = [] + ddr_smart_nodes: List[dict] = [] + ddr_smart_roots: List[dict] = [] + + # 2) For each DDR, either direct connect or build a reduction tree + for d_idx in sorted(by_ddr.keys()): + dst_pin = noc_pin_fmt.format(index=d_idx) + sources = by_ddr[d_idx] + + if len(sources) == 1: + ddr_direct.append({"src_pin": sources[0], "dst_pin": dst_pin}) + continue + + # Build reduction tree with <= max_si SIs per node + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] + for i in range(0, len(current), max_si)] + next_level = [] + + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{d_idx}_{level}_{g_idx}" + node = { + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + } + ddr_smart_nodes.append(node) + # Output of this SC is M00_AXI + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + + current = next_level + level += 1 + + if root_sc_name: + ddr_smart_roots.append( + {"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "ddr_direct": ddr_direct, + "ddr_smart_nodes": ddr_smart_nodes, + "ddr_smart_roots": ddr_smart_roots, + } diff --git a/linker/slashkit/emit/hw/user_region/debug_ctx.py b/linker/slashkit/emit/hw/user_region/debug_ctx.py new file mode 100644 index 00000000..10dd6e23 --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/debug_ctx.py @@ -0,0 +1,105 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +import re +from typing import Dict + +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +_AXIS_ILA_NAME = "axis_ila_debug_0" +_MAX_MONITOR_SLOTS = 16 +def _port_norm(s): return re.sub(r"[^a-z0-9]", "", s.lower()) + + +def _resolve_port_name(kernel, requested: str) -> str: + if requested in kernel.ports: + return requested + + low = {n.lower(): n for n in kernel.ports.keys()} + rlow = requested.lower() + if rlow in low: + return low[rlow] + + norm_map = {_port_norm(n): n for n in kernel.ports.keys()} + rnorm = _port_norm(requested) + if rnorm in norm_map: + return norm_map[rnorm] + + raise KeyError( + f"Port '{requested}' not found on kernel '{kernel.name}'. " + f"Available: {list(kernel.ports.keys())}" + ) + + +def _axis_ila_slot_meta(ptype: BusType) -> tuple[str, str]: + if ptype == BusType.AXIS: + return ("AXIS", "xilinx.com:interface:axis_rtl:1.0") + if ptype in {BusType.AXILITE, BusType.AXI4FULL}: + return ("AXI", "xilinx.com:interface:aximm_rtl:1.0") + raise ValueError( + "[debug] only AXIS/AXILITE/AXI4FULL ports are supported for axis_ila probes." + ) + + +def build_system_ila_debug_context( + instances: Dict[str, KernelInstance], + debug_spec, +) -> dict: + """Build context for one multi-slot axis_ila core.""" + debug_nets = list(getattr(debug_spec, "nets", []) or []) + if len(debug_nets) > _MAX_MONITOR_SLOTS: + raise ValueError( + f"[debug] configured {len(debug_nets)} nets, but axis_ila supports at most " + f"{_MAX_MONITOR_SLOTS} monitor slots." + ) + + slots: list[dict] = [] + for idx, net in enumerate(debug_nets): + inst_name = getattr(net, "inst", "") + port_name = getattr(net, "port", "") + + if inst_name not in instances: + raise KeyError( + f"[debug] net refers to unknown instance '{inst_name}'.") + + inst = instances[inst_name] + canon_port = _resolve_port_name(inst.kernel, port_name) + slot_suffix, intf_type = _axis_ila_slot_meta( + inst.kernel.port(canon_port).ptype) + + slots.append( + { + "idx": idx, + "src_pin": f"{inst_name}/{canon_port}", + "slot_pin": f"SLOT_{idx}_{slot_suffix}", + "intf_type": intf_type, + } + ) + + return { + "debug_axis_ila_enabled": bool(slots), + "debug_axis_ila_name": _AXIS_ILA_NAME, + "debug_axis_ila_slots": slots, + "debug_axis_ila_num_slots": len(slots), + } diff --git a/linker/slashkit/emit/hw/user_region/hbm_ctx.py b/linker/slashkit/emit/hw/user_region/hbm_ctx.py new file mode 100644 index 00000000..30d585cc --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/hbm_ctx.py @@ -0,0 +1,149 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List, Optional +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType +from slashkit.core.bd_ports import BlockDesignPorts + + +def _to_int_or_none(v: Optional[object]) -> Optional[int]: + if v is None: + return None + if isinstance(v, int): + return v + s = str(v).strip() + if s == "": + return None + try: + return int(s, 0) + except ValueError: + return None + + +def build_hbm_smartconnect_context( + instances: Dict[str, KernelInstance], + bd: BlockDesignPorts, + *, + max_si: int = 16, + base_name: str = "hbm_sc" +) -> dict: + """ + Instantiate per-HBM-channel SmartConnect ONLY if that channel has ≥1 AXI4FULL writers. + Otherwise leave the HBM port unused so the generic terminator can handle it. + """ + # Gather AXI4FULL kernel pins targeting HBM + by_hbm: Dict[int, List[str]] = defaultdict(list) + + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + # Only care about AXI4FULL ports + try: + if inst.kernel.port(k_port).ptype != BusType.AXI4FULL: + continue + except KeyError: + continue + + dom = str(tgt.get("domain", "")).upper() + if dom != "HBM": + continue + + idx = _to_int_or_none(tgt.get("index")) + if idx is None: + # HBM requires an index; skip malformed entries + continue + + by_hbm[idx].append(f"{inst.name}/{k_port}") + + hbm_reduce_nodes: List[dict] = [] + hbm_root_create: List[dict] = [] + hbm_root_in: List[dict] = [] + hbm_root_out: List[dict] = [] + + for h_idx in sorted(by_hbm.keys()): + sources = by_hbm[h_idx] + if not sources: + continue + + # Destination BD port name (HBM_AXI_XX) + dst_bd = bd.mem("HBM", h_idx) + dst_port = dst_bd.rtl_name or dst_bd.name + + # Root SC config: 2 clocks (aclk, aclk1), 1 SI, 1 MI + root_name = f"{base_name}_{h_idx:02d}" + clk0 = "user_clk" + clk1 = "[get_bd_ports static_region_clk]" + rst = "ilreduced_logic_0/Res" + + hbm_root_create.append({ + "name": root_name, + "idx": h_idx, + "clk0": clk0, + "clk1": clk1, + "rst": rst, + }) + + if len(sources) == 1: + # Single writer → feed root directly + hbm_root_in.append({ + "src_pin": sources[0], + "dst_pin": f"{root_name}/S00_AXI", + }) + else: + # Reduction tree → last MI feeds root + level = 0 + current = [{"src": s} for s in sources] + while len(current) > 1: + groups = [current[i:i+max_si] + for i in range(0, len(current), max_si)] + next_level = [] + for g_idx, group in enumerate(groups): + scn = f"{base_name}_{h_idx:02d}_L{level}_{g_idx}" + hbm_reduce_nodes.append({ + "name": scn, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + "clk": clk0, + "rst": rst, + }) + next_level.append({"src": f"{scn}/M00_AXI"}) + current = next_level + level += 1 + + hbm_root_in.append({ + "src_pin": current[0]["src"], + "dst_pin": f"{root_name}/S00_AXI", + }) + + # Root MI -> real HBM port + hbm_root_out.append({ + "src_pin": f"{root_name}/M00_AXI", + "dst_port": dst_port, + }) + + return { + "hbm_reduce_nodes": hbm_reduce_nodes, + "hbm_root_create": hbm_root_create, + "hbm_root_in": hbm_root_in, + "hbm_root_out": hbm_root_out, + } diff --git a/linker/slashkit/emit/hw/user_region/host_ctx.py b/linker/slashkit/emit/hw/user_region/host_ctx.py new file mode 100644 index 00000000..89188aff --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/host_ctx.py @@ -0,0 +1,89 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType +from slashkit.core.bd_ports import BlockDesignPorts + + +def build_host_smartconnect_context( + instances: Dict[str, KernelInstance], + bd: BlockDesignPorts, + *, + max_si: int = 16, + base_name: str = "host_sc_m", +) -> dict: + """ + Plan connections for kernels that target HOST (QDMA slave bridge). + Sink is the NoC pin: /qdma_slave_bridge_noc/S00_AXI + + Returns: + - host_direct: [{src_pin, dst_pin}] + - host_smart_nodes: [{name, num_si, si:[{slot, src}], ...}] + - host_smart_roots: [{sc_name, dst_pin}] + """ + # Gather AXI4FULL sources that map to HOST + host_sources: List[str] = [] + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if (str(tgt.get("domain", "")).upper() == "HOST" + and inst.kernel.port(k_port).ptype == BusType.AXI4FULL): + host_sources.append(f"{inst.name}/{k_port}") + + host_direct: List[dict] = [] + host_smart_nodes: List[dict] = [] + host_smart_roots: List[dict] = [] + + dst_pin = "/qdma_slave_bridge_noc/S00_AXI" + + if len(host_sources) == 1: + host_direct.append({"src_pin": host_sources[0], "dst_pin": dst_pin}) + elif len(host_sources) > 1: + # reduction tree to respect max_si + level = 0 + current = [{"src": s} for s in host_sources] + root_sc_name = None + while len(current) > 1: + groups = [current[i:i + max_si] + for i in range(0, len(current), max_si)] + next_level = [] + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{level}_{g_idx}" + host_smart_nodes.append({ + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + }) + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + current = next_level + level += 1 + if root_sc_name: + host_smart_roots.append( + {"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "host_direct": host_direct, + "host_smart_nodes": host_smart_nodes, + "host_smart_roots": host_smart_roots, + } diff --git a/deploy/base_pdi/tcl/noc_solution.tcl b/linker/slashkit/emit/hw/user_region/kernel_ctx.py similarity index 53% rename from deploy/base_pdi/tcl/noc_solution.tcl rename to linker/slashkit/emit/hw/user_region/kernel_ctx.py index 580aee26..aad62450 100644 --- a/deploy/base_pdi/tcl/noc_solution.tcl +++ b/linker/slashkit/emit/hw/user_region/kernel_ctx.py @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,33 +18,31 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -proc run_noc_solution { parentCell } { - - variable script_folder - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - set_property NOC_SOLUTION_FILE "" [get_runs impl_1] -} \ No newline at end of file +from __future__ import annotations +from collections import OrderedDict +from typing import Dict +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +def build_kernel_add_context(instances: Dict[str, KernelInstance]) -> dict: + """ + Context for your Jinja template: + - instances: OrderedDict[name -> KernelInstance] + - clocks: [{"src_pin": "/"} ...] + """ + ordered = OrderedDict((name, instances[name]) + for name in sorted(instances.keys())) + + clocks = [] + resets = [] + for name, inst in ordered.items(): + for p in inst.kernel.ports_of_type(BusType.CLOCK): + phys = inst.kernel.bus_physical_port(p.name) or p.name + clocks.append({"src_pin": f"{inst.name}/{phys}"}) + + for p in inst.kernel.ports_of_type(BusType.RESET): + phys = inst.kernel.bus_physical_port(p.name) or p.name + resets.append({"src_pin": f"{inst.name}/{phys}"}) + + return {"instances": ordered, "clocks": clocks, "resets": resets} diff --git a/linker/slashkit/emit/hw/user_region/mem_ctx.py b/linker/slashkit/emit/hw/user_region/mem_ctx.py new file mode 100644 index 00000000..1a4b8ed0 --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/mem_ctx.py @@ -0,0 +1,142 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from typing import Dict, List, Optional, Tuple, Any +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +def _coerce_optional_int(v: Any) -> Optional[int]: + """Return int(v) if v is not None and looks like an int (decimal or 0x..), else None.""" + if v is None: + return None + if isinstance(v, int): + return v + if isinstance(v, str): + s = v.strip() + try: + return int(s, 0) + except ValueError: + return None + return None + + +def build_mem_smartconnect_context( + instances: Dict[str, KernelInstance], + *, + num_mem_ports: int = 8, + max_si: int = 16, + base_name: str = "sc_mem", + noc_pin_fmt: str = "/hbm_vnoc_0{index}/S00_AXI" +) -> dict: + """ + Map all AXI4FULL masters targeting MEM to 8 VNOC slaves using round-robin, + unless a MEM index is explicitly specified in the config (sp=...:MEM). + If a VNOC bucket has >1 masters, build a SmartConnect reduction tree with + <= max_si SIs per node (NUM_CLKS=1, NUM_MI=1). + + Returns: + { + "mem_direct": [{src_pin, dst_pin}], + "mem_smart_nodes": [{name, num_si, si:[{slot, src}], ...}], + "mem_smart_roots": [{sc_name, dst_pin}], + } + """ + # 1) Collect all AXI4FULL kernel pins that target MEM + # Also capture an optional explicit index (if provided by config). + # (src_pin, explicit_index or None) + mem_sources: List[Tuple[str, Optional[int]]] = [] + + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") == "MEM": + # Only AXI4FULL should be in mem_sp for memory mapping + if inst.kernel.port(k_port).ptype == BusType.AXI4FULL: + src_pin = f"{inst.name}/{k_port}" + # Some configs may carry an explicit MEM index; usually None. + idx = _coerce_optional_int(tgt.get("index")) + if idx is not None and not (0 <= idx < num_mem_ports): + raise ValueError( + f"MEM index {idx} out of range (0..{num_mem_ports-1}) for {src_pin}") + mem_sources.append((src_pin, idx)) + + if not mem_sources: + return {"mem_direct": [], "mem_smart_nodes": [], "mem_smart_roots": []} + + # 2) Round-robin assign to MEM buckets (respect explicit indices when present) + buckets: Dict[int, List[str]] = {i: [] for i in range(num_mem_ports)} + rr = 0 + for src_pin, explicit in mem_sources: + if explicit is not None: + buckets[explicit].append(src_pin) + else: + buckets[rr % num_mem_ports].append(src_pin) + rr += 1 + + mem_direct: List[dict] = [] + mem_smart_nodes: List[dict] = [] + mem_smart_roots: List[dict] = [] + + # 3) For each MEM bucket, either direct-connect or reduce via SmartConnect tree + for m_idx in range(num_mem_ports): + dst_pin = noc_pin_fmt.format(index=m_idx) + sources = buckets[m_idx] + if len(sources) == 0: + continue + if len(sources) == 1: + mem_direct.append({"src_pin": sources[0], "dst_pin": dst_pin}) + continue + + # Reduction tree (≤ max_si SIs per node) + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] + for i in range(0, len(current), max_si)] + next_level: List[dict] = [] + + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{m_idx}_{level}_{g_idx}" + node = { + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + } + mem_smart_nodes.append(node) + # Output of this SC is single MI: M00_AXI + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + + current = next_level + level += 1 + + if root_sc_name: + mem_smart_roots.append( + {"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "mem_direct": mem_direct, + "mem_smart_nodes": mem_smart_nodes, + "mem_smart_roots": mem_smart_roots, + } diff --git a/linker/slashkit/emit/hw/user_region/param_ctx.py b/linker/slashkit/emit/hw/user_region/param_ctx.py new file mode 100644 index 00000000..2bca849f --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/param_ctx.py @@ -0,0 +1,82 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +def _param_name_for_busif(busif: str) -> str: + # HLS/packager convention: C__DATA_WIDTH + # e.g., M_AXI_GMEM0 -> C_M_AXI_GMEM0_DATA_WIDTH + return f"C_{busif.upper()}_DATA_WIDTH" + + +def build_data_width_param_context( + instances: Dict[str, KernelInstance], + *, + domains_of_interest=("HBM", "VIRT"), + default_width_by_domain={"HBM": 256, "VIRT": 512} +) -> dict: + """ + For every instance and each AXI4FULL port that is mapped (via cfg.sps/defaults) + to a memory domain in 'domains_of_interest', emit a param set: + set_property CONFIG.C__DATA_WIDTH {} [get_bd_cells ] + + Width resolution order: + 1) Use the port width parsed from component.xml if present (Port.width). + 2) Fallback to default_width_by_domain[domain]. + """ + out: List[dict] = [] + + for inst in instances.values(): + # mem_sp filled earlier by apply_config_to_instances() + mem_map = inst.params.get("mem_sp", {}) or {} + for busif, tgt in mem_map.items(): + dom = str(tgt.get("domain", "")).upper() + if dom not in domains_of_interest: + continue + # Only for AXI4FULL ports + try: + p = inst.kernel.port(busif) + except KeyError: + continue + if p.ptype != BusType.AXI4FULL: + continue + + # Decide width + width = p.width if p.width else default_width_by_domain.get(dom) + if not width: + # If still unknown, skip silently (or raise if you prefer) + continue + + out.append({ + "inst": inst.name, + "param": f"CONFIG.{_param_name_for_busif(busif)}", + "value": int(width), + }) + + # Optional de-dup if multiple entries set the same param for an inst + dedup = {} + for e in out: + key = (e["inst"], e["param"]) + dedup[key] = e # last wins + return {"data_width_params": list(dedup.values())} diff --git a/linker/slashkit/emit/hw/user_region/smartconnect_ctx.py b/linker/slashkit/emit/hw/user_region/smartconnect_ctx.py new file mode 100644 index 00000000..48ce7602 --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/smartconnect_ctx.py @@ -0,0 +1,97 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from collections import OrderedDict +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + + +def build_axilite_smartconnect_context( + instances: Dict[str, KernelInstance], + *, + si_bd_port: str = "axi_noc_0/M00_AXI", + max_mi: int = 16, + chain_slot: int = 15, + base_name: str = "smartconnect", +) -> dict: + """ + SmartConnects to fan out AXI-Lite control to all kernel AXI-Lite ports. + + Returns: + {"smartconnects": [ + { + "index": 0, + "name": "smartconnect_0", + "num_mi": 64 or N, + "chain_slot": 63, + "si_from": {"type":"bd_port","name":"s_axilite"} or {"type":"smartconnect","prev":"smartconnect_0"}, + "mi": [{"slot": 0, "dst_pin": "inst/AXILITE_PIN"}, ...] + }, + ... + ]} + """ + # 1) Collect all AXI-Lite endpoints in a stable order + ordered = OrderedDict((name, instances[name]) + for name in sorted(instances.keys())) + endpoints: List[str] = [] + for inst in ordered.values(): + for p in sorted((pp for pp in inst.kernel.ports.values() if pp.ptype == BusType.AXILITE), key=lambda x: x.name): + endpoints.append(f"{inst.name}/{p.name}") + + N = len(endpoints) + if N == 0: + return {"smartconnects": []} + + # 2) Pack endpoints into one-or-more SCs + smartconnects = [] + remaining = endpoints[:] + idx = 0 + prev_name = None + + while remaining: + sc_name = f"{base_name}_{idx}" + is_last = len(remaining) <= max_mi + if is_last: + payload = remaining[:max_mi] + remaining = [] + num_mi = len(payload) + else: + payload = remaining[: (max_mi - 1)] + remaining = remaining[(max_mi - 1):] + num_mi = max_mi + + sc = { + "index": idx, + "name": sc_name, + "num_mi": num_mi, + "chain_slot": chain_slot, + "si_from": ( + {"type": "bd_port", "name": si_bd_port} if prev_name is None + else {"type": "smartconnect", "prev": prev_name} + ), + "mi": [{"slot": slot, "dst_pin": dst} for slot, dst in enumerate(payload)], + } + smartconnects.append(sc) + prev_name = sc_name + idx += 1 + + return {"smartconnects": smartconnects} diff --git a/linker/slashkit/emit/hw/user_region/terminator_ctx.py b/linker/slashkit/emit/hw/user_region/terminator_ctx.py new file mode 100644 index 00000000..c432b1f0 --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/terminator_ctx.py @@ -0,0 +1,173 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from typing import List, Set +import re +from slashkit.core.port import BusType +from slashkit.core.bd_ports import BlockDesignPorts, BdPort + +_RX_SKIP_TOP = re.compile( + r"^(M\d{2}_INI|HBM_VNOC_INI_\d{2}|HBM_AXI_\d{2})$", re.IGNORECASE) + + +def _is_bd_port(p: BdPort) -> bool: + """True if destination is a *BD interface port* (not a NoC/pin path).""" + return not ((p.rtl_name or "").startswith("/")) + + +def _want_generic_term(p: BdPort) -> bool: + """ + Only terminate VIRT BD ports here. + Skip HBM (handled by hbm_sc_terminators), and skip DDR/MEM (they use NoC-side terminators). + """ + if p.ptype != BusType.AXI4FULL: + return False + dom = (p.domain or "").upper() + + if dom in ("VIRT", "HOST"): + return False # VIRT/HOST use NoC-side terminators no + + # Must be a true BD port (not a NoC path) + if not _is_bd_port(p): + return False + + rtl = (p.rtl_name or p.name) + if _RX_SKIP_TOP.match(rtl): + return False + return True + + +def build_axi_terminators_context( + bd: BlockDesignPorts, + used_targets: Set[str], + *, + base_name: str = "axi_register_slice_term", +) -> dict: + """ + Plan AXI Register Slices ONLY for unused HBM/VIRT BD ports. + DDR and MEM are handled by NoC-specific builders. + """ + terms: List[dict] = [] + seq = 0 + + for lst in bd.ports.values(): + for p in lst: + if not _want_generic_term(p): + continue + dst = (p.rtl_name or p.name) + if dst in used_targets: + continue + terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, + }) + seq += 1 + + return {"axi_terminators": terms} + + +def build_ddr_noc_terminators( + used_targets: Set[str], + *, + num_ddr: int = 4, + noc_pin_fmt: str = "/ddr_noc_{index}/S00_AXI", + base_name: str = "axi_register_slice_ddrterm", +) -> dict: + """Terminate unused DDR NoC pins.""" + axi_terms: List[dict] = [] + seq = 0 + for i in range(num_ddr): + dst = noc_pin_fmt.format(index=i) + if dst in used_targets: + continue + axi_terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, + }) + seq += 1 + return {"axi_terminators": axi_terms} + + +def build_mem_noc_terminators( + used_targets: Set[str], + *, + num_mem: int = 8, + noc_pin_fmt: str = "/hbm_vnoc_0{index}/S00_AXI", + base_name: str = "axi_register_slice_memterm", +) -> dict: + """Terminate unused MEM (VNOC) NoC pins.""" + axi_terms: List[dict] = [] + seq = 0 + for i in range(num_mem): + dst = noc_pin_fmt.format(index=i) + if dst in used_targets: + continue + axi_terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, + }) + seq += 1 + return {"axi_terminators": axi_terms} + + +def build_virt_noc_terminators( + used_targets: set[str], + *, + num_virt: int = 4, + noc_pin_fmt: str = "/noc_virt_0{index}/S00_AXI", + base_name: str = "axi_register_slice_virtterm", +) -> dict: + """Terminate unused VIRT NoC pins (/noc_virt_0X/S00_AXI).""" + axi_terms: List[dict] = [] + seq = 0 + for i in range(num_virt): + dst = noc_pin_fmt.format(index=i) + if dst in used_targets: + continue + axi_terms.append({ + "name": f"{base_name}_{seq}", + "dst": dst, # template uses t.dst + "clk": "user_clk", + "rst": "ilreduced_logic_0/Res", + }) + seq += 1 + return {"axi_terminators": axi_terms} + + +def build_host_noc_terminator( + used_targets: set[str], + *, + noc_pin: str = "/qdma_slave_bridge_noc/S00_AXI", + base_name: str = "axi_register_slice_hostterm", +) -> dict: + """ + Terminate the HOST (QDMA slave bridge) NoC sink if unused. + """ + if noc_pin in used_targets: + return {"axi_terminators": []} + return { + "axi_terminators": [{ + "name": f"{base_name}_0", + "dst": noc_pin, # template expects t.dst + "clk": "user_clk", + "rst": "ilreduced_logic_0/Res", + }] + } diff --git a/linker/slashkit/emit/hw/user_region/virt_ctx.py b/linker/slashkit/emit/hw/user_region/virt_ctx.py new file mode 100644 index 00000000..64af3990 --- /dev/null +++ b/linker/slashkit/emit/hw/user_region/virt_ctx.py @@ -0,0 +1,99 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from collections import defaultdict +from typing import Dict, List +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType +from slashkit.core.bd_ports import BlockDesignPorts + + +def build_virt_smartconnect_context( + instances: Dict[str, KernelInstance], + bd: BlockDesignPorts, + *, + max_si: int = 16, + base_name: str = "virt_sc_m", + num_virt: int = 4, +) -> dict: + """ + Like HBM, but the sinks are VIRT NoC pins: + /noc_virt_00/S00_AXI ... /noc_virt_03/S00_AXI + + Returns: + - virt_direct: [{src_pin, dst_pin}] + - virt_smart_nodes: [{name, num_si, si:[{slot, src}], ...}] + - virt_smart_roots: [{sc_name, dst_pin}] + """ + # Collect AXI4FULL kernel pins that target VIRT + by_virt: Dict[int, List[str]] = defaultdict(list) + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) + for k_port, tgt in mem_sp.items(): + if (tgt.get("domain") == "VIRT" + and tgt.get("index") is not None + and 0 <= int(tgt["index"]) < num_virt): + if inst.kernel.port(k_port).ptype == BusType.AXI4FULL: + by_virt[int(tgt["index"])].append(f"{inst.name}/{k_port}") + + virt_direct: List[dict] = [] + virt_smart_nodes: List[dict] = [] + virt_smart_roots: List[dict] = [] + + for v_idx in sorted(by_virt.keys()): + # Destination is the NoC pin (not a top-level BD port) + dst_pin = f"/noc_virt_0{v_idx}/S00_AXI" + sources = by_virt[v_idx] + + if len(sources) == 1: + virt_direct.append({"src_pin": sources[0], "dst_pin": dst_pin}) + continue + + # Build reduction tree to respect max_si per SmartConnect + level = 0 + current = [{"src": s} for s in sources] + root_sc_name = None + + while len(current) > 1: + groups = [current[i:i + max_si] + for i in range(0, len(current), max_si)] + next_level = [] + for g_idx, group in enumerate(groups): + sc_name = f"{base_name}_{v_idx:02d}_{level}_{g_idx}" + virt_smart_nodes.append({ + "name": sc_name, + "num_si": len(group), + "si": [{"slot": i, "src": g["src"]} for i, g in enumerate(group)], + }) + next_level.append({"src": f"{sc_name}/M00_AXI"}) + root_sc_name = sc_name + current = next_level + level += 1 + + if root_sc_name: + virt_smart_roots.append( + {"sc_name": root_sc_name, "dst_pin": dst_pin}) + + return { + "virt_direct": virt_direct, + "virt_smart_nodes": virt_smart_nodes, + "virt_smart_roots": virt_smart_roots, + } diff --git a/linker/slashkit/emit/metadata/__init__.py b/linker/slashkit/emit/metadata/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/metadata/prog_image.py b/linker/slashkit/emit/metadata/prog_image.py new file mode 100644 index 00000000..85a8bc82 --- /dev/null +++ b/linker/slashkit/emit/metadata/prog_image.py @@ -0,0 +1,64 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## +from __future__ import annotations + +import logging +import tarfile +from pathlib import Path + +from slashkit.core.command_config import LinkerConfiguration + +logger = logging.getLogger(__name__) + + +def build_vbin(config: LinkerConfiguration) -> Path: + """! @brief Build a compressed .vbin tarball for a project. + + @param project_name Project name used to locate results and name the archive. + @param results_dir Optional override of the project results directory. + @return Path to the generated .vbin file. + """ + images_dir = config.build_dir / "images" + service_layer_pdi_path = images_dir / \ + f"top_i_service_layer_service_layer_{config.project_name}_inst_0_partial.pdi" + slash_pdi_path = images_dir / \ + f"top_i_slash_slash_{config.project_name}_inst_0_partial.pdi" + util_xml = config.build_dir / \ + f"report_utilization_{config.project_name}.xml" + system_map = config.build_dir / "system_map.xml" + + files = [slash_pdi_path, util_xml, system_map] + if config.networking_enabled: + files.append(service_layer_pdi_path) + + for file in files: + if not file.exists(): + raise FileNotFoundError(file) + + logger.info("Creating vbin archive: %s", config.out_path) + + with tarfile.open(config.out_path, "w:gz") as tf: + for path in files: + arcname = path.relative_to(config.build_dir) + logger.info("Adding to vbin: %s", arcname) + tf.add(path, arcname=str(arcname)) + + logger.info("vbin archive complete: %s", config.out_path) + return config.out_path diff --git a/linker/slashkit/emit/metadata/report_util.py b/linker/slashkit/emit/metadata/report_util.py new file mode 100644 index 00000000..4817ee24 --- /dev/null +++ b/linker/slashkit/emit/metadata/report_util.py @@ -0,0 +1,340 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +import logging +import re +from dataclasses import dataclass, field +from typing import Dict, List, Optional +import xml.etree.ElementTree as ET + + +@dataclass +class ValueWithPercent: + value: Optional[int] + pct: Optional[float] + + +@dataclass +class UtilRow: + instance_raw: str + instance: str + module: str + pr_attribute: str + + total_pplocs: ValueWithPercent + total_luts: ValueWithPercent + lutrams: ValueWithPercent + srls: ValueWithPercent + ffs: ValueWithPercent + ramb36: ValueWithPercent + ramb18: ValueWithPercent + uram: ValueWithPercent + dsp: ValueWithPercent + + depth: int = 0 + + def ramb_equivalent_18k(self) -> int: + return (self.ramb18.value or 0) + 2 * (self.ramb36.value or 0) + + +@dataclass +class TreeNode: + row: UtilRow + children: List["TreeNode"] = field(default_factory=list) + + +@dataclass +class ResourceTotals: + total_pplocs: int = 0 + total_luts: int = 0 + lutrams: int = 0 + srls: int = 0 + ffs: int = 0 + ramb36: int = 0 + ramb18: int = 0 + uram: int = 0 + dsp: int = 0 + + def add(self, r: UtilRow) -> None: + self.total_pplocs += r.total_pplocs.value or 0 + self.total_luts += r.total_luts.value or 0 + self.lutrams += r.lutrams.value or 0 + self.srls += r.srls.value or 0 + self.ffs += r.ffs.value or 0 + self.ramb36 += r.ramb36.value or 0 + self.ramb18 += r.ramb18.value or 0 + self.uram += r.uram.value or 0 + self.dsp += r.dsp.value or 0 + + def ramb_equivalent_18k(self) -> int: + return self.ramb18 + 2 * self.ramb36 + + +CELL_VALUE_PCT = re.compile( + r"^\s*(?P\d+)\s*(?:\(\s*(?P\d+(?:\.\d+)?)%\s*\))?\s*$") + + +def parse_cell_value_and_percent(cell: str) -> ValueWithPercent: + """! @brief Parse a utilization cell containing a value and optional percent. + + @param cell Raw cell string from the utilization table. + @return Parsed value and percent (if present). + """ + cell = (cell or "").strip() + if not cell or cell == "-": + return ValueWithPercent(None, None) + + m = CELL_VALUE_PCT.match(cell) + if not m: + digits = re.match(r"^\s*(\d+)", cell) + return ValueWithPercent(int(digits.group(1)), None) if digits else ValueWithPercent(None, None) + + val = int(m.group("val")) + pct = float(m.group("pct")) if m.group("pct") is not None else None + return ValueWithPercent(val, pct) + + +def parse_vivado_hierarchical_utilization_table(text: str) -> List[UtilRow]: + """! @brief Parse the Vivado hierarchical utilization table into rows. + + @param text Full report file contents. + @return List of parsed utilization rows. + """ + lines = text.splitlines() + rows: List[UtilRow] = [] + in_table = False + + for ln in lines: + if ln.startswith("|") and "Instance" in ln and "Module" in ln and "Total LUTs" in ln: + in_table = True + continue + + if not in_table: + continue + + if ln.startswith("+") and ln.count("+") > 5: + continue + + if not ln.startswith("|"): + if rows: + break + continue + + raw_parts = ln.strip("\n").strip("|").split("|") + if len(raw_parts) < 13: + continue + + instance_col_raw = raw_parts[0] + module_col_raw = raw_parts[1] + pr_attr_col_raw = raw_parts[2] + + depth = (len(instance_col_raw) - + len(instance_col_raw.lstrip(" "))) // 2 + instance = instance_col_raw.strip() + module = module_col_raw.strip() + pr_attr = pr_attr_col_raw.strip() + + rows.append( + UtilRow( + instance_raw=instance_col_raw, + instance=instance, + module=module, + pr_attribute=pr_attr, + total_pplocs=parse_cell_value_and_percent(raw_parts[3]), + total_luts=parse_cell_value_and_percent(raw_parts[4]), + lutrams=parse_cell_value_and_percent(raw_parts[6]), + srls=parse_cell_value_and_percent(raw_parts[7]), + ffs=parse_cell_value_and_percent(raw_parts[8]), + ramb36=parse_cell_value_and_percent(raw_parts[9]), + ramb18=parse_cell_value_and_percent(raw_parts[10]), + uram=parse_cell_value_and_percent(raw_parts[11]), + dsp=parse_cell_value_and_percent(raw_parts[12]), + depth=depth, + ) + ) + + return rows + + +def build_hierarchy_tree(rows: List[UtilRow]) -> Dict[str, TreeNode]: + """! @brief Build a parent/child hierarchy from flat utilization rows. + + @param rows Utilization rows with depth set. + @return Map of instance name to tree node. + """ + nodes_by_instance: Dict[str, TreeNode] = {} + stack: List[TreeNode] = [] + + for r in rows: + node = TreeNode(row=r) + nodes_by_instance[r.instance] = node + + while stack and stack[-1].row.depth >= r.depth: + stack.pop() + + if stack: + stack[-1].children.append(node) + + stack.append(node) + + return nodes_by_instance + + +def write_totals_attributes_from_row(elem: ET.Element, r: UtilRow) -> None: + """! @brief Write utilization totals (including pct) from a row. + + @param elem XML element to update. + @param r Utilization row source. + """ + def _set_val_pct(elem: ET.Element, base: str, v: ValueWithPercent) -> None: + elem.set(base, str(v.value or 0)) + if v.pct is not None: + elem.set(f"{base}_pct", f"{v.pct:.2f}") + + _set_val_pct(elem, "total_pplocs", r.total_pplocs) + _set_val_pct(elem, "total_luts", r.total_luts) + _set_val_pct(elem, "lutram", r.lutrams) + _set_val_pct(elem, "srl", r.srls) + _set_val_pct(elem, "ff", r.ffs) + _set_val_pct(elem, "ramb36", r.ramb36) + _set_val_pct(elem, "ramb18", r.ramb18) + elem.set("ramb", str(r.ramb_equivalent_18k())) + _set_val_pct(elem, "uram", r.uram) + _set_val_pct(elem, "dsp", r.dsp) + + +def write_totals_attributes_from_totals(elem: ET.Element, t: ResourceTotals) -> None: + """! @brief Write utilization totals from accumulated totals. + + @param elem XML element to update. + @param t Resource totals source. + """ + elem.set("total_pplocs", str(t.total_pplocs)) + elem.set("total_luts", str(t.total_luts)) + elem.set("lutram", str(t.lutrams)) + elem.set("srl", str(t.srls)) + elem.set("ff", str(t.ffs)) + elem.set("ramb36", str(t.ramb36)) + elem.set("ramb18", str(t.ramb18)) + elem.set("ramb", str(t.ramb_equivalent_18k())) + elem.set("uram", str(t.uram)) + elem.set("dsp", str(t.dsp)) + + +def write_cell(parent_element: ET.Element, node: TreeNode, is_kernel=False, recurse=False) -> None: + """! @brief Write a cell/kernel, potentially recursing into sub-cells + + @param parent_element Parent element under which to place the new cell + @param node Utilization tree node. + @param is_kernel If true, call the cell a "kernel." Defaults to False, using the "cell" name. + @param recurse If true, add the cells within the tree node. Defaults to False. + """ + name = "kernel" if is_kernel else "cell" + cell_element = ET.SubElement( + parent_element, name, instance=node.row.instance, module=node.row.module) + write_totals_attributes_from_row( + ET.SubElement(cell_element, "totals"), node.row) + if not recurse or len(node.children) == 0: + return + for child in node.children: + write_cell(cell_element, child, recurse=recurse) + + +def create_utilization_xml(nodes: Dict[str, TreeNode]) -> ET.ElementTree: + """! @brief Create the utilization XML tree from parsed nodes. + + @param nodes Map of instance name to tree node. + @return XML element tree representing utilization report. + """ + root = ET.Element("utilization_report") + write_totals_attributes_from_row(ET.SubElement( + root, "totals"), nodes["top_wrapper"].row) + + for region_name in ["static_region", "service_layer"]: + if region_name not in nodes: + continue + node = nodes[region_name] + element = ET.SubElement(root, region_name) + write_totals_attributes_from_row( + ET.SubElement(element, "totals"), node.row) + + slash_node = nodes["slash"] + slash_element = ET.SubElement(root, "slash") + + kernels = ET.SubElement(slash_element, "kernels") + slash_logic_cells = ET.SubElement(slash_element, "slash_logic") + + kernel_sum = ResourceTotals() + slash_logic_sum = ResourceTotals() + + for child in slash_node.children: + inst = child.row.instance.strip() + if inst.startswith("(") and inst.endswith(")"): + continue + + is_slash_logic = any(p.search(inst) for p in [ + re.compile(r".*_sc_.*"), # hbm_sc_01, etc. + re.compile(r"^smartconnect.*"), # smartconnect_0, etc. + ]) + + if is_slash_logic: + write_cell(slash_logic_cells, child) + slash_logic_sum.add(child.row) + else: + write_cell(kernels, child, recurse=True, is_kernel=True) + kernel_sum.add(child.row) + + write_totals_attributes_from_row(ET.SubElement( + slash_element, "totals"), slash_node.row) + write_totals_attributes_from_totals( + ET.SubElement(slash_element, "kernel_sum"), kernel_sum) + write_totals_attributes_from_totals( + ET.SubElement(slash_element, "slash_logic_sum"), slash_logic_sum) + ET.Comment() + + ET.indent(root) + tree = ET.ElementTree(root) + return tree + + +def convert_report_utilization_to_xml(report_path: str, out_xml_path: str) -> None: + """! @brief Convert Vivado utilization report text to XML. + + @param report_path Path to the report_utilization_*.txt input. + @param out_xml_path Path to the report_utilization_*.xml output. + """ + logger.info("Converting utilization report to XML") + logger.info("Utilization report input: %s", report_path) + logger.info("Utilization report output: %s", out_xml_path) + with open(report_path, "r", encoding="utf-8", errors="replace") as f: + text = f.read() + + rows = parse_vivado_hierarchical_utilization_table(text) + logger.info("Parsed utilization rows: %d", len(rows)) + nodes = build_hierarchy_tree(rows) + logger.info("Built utilization node map: %d", len(nodes)) + tree = create_utilization_xml(nodes) + tree.write(out_xml_path, encoding="utf-8", xml_declaration=True) + logger.info("Utilization report XML generation complete") + + +logger = logging.getLogger(__name__) diff --git a/linker/slashkit/emit/metadata/system_map_ctx.py b/linker/slashkit/emit/metadata/system_map_ctx.py new file mode 100644 index 00000000..1046cee5 --- /dev/null +++ b/linker/slashkit/emit/metadata/system_map_ctx.py @@ -0,0 +1,534 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from pathlib import Path +from typing import Dict, List, Optional, Tuple +import logging +import re + +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType +from slashkit.core.regs import AddressBlock +from slashkit.emit.hls_meta import load_hls_metadata, parse_hls_args + +DEFAULT_CLOCK_HZ = 200_000_000 +_REG_SPLIT_RE = re.compile(r"^(.*)_\d+$") +_CONTROL_REGS = {"ctrl", "gier", "ip_ier", "ip_isr"} +_PORT_NORM_RE = re.compile(r"[^a-z0-9]") +logger = logging.getLogger(__name__) + + +def resolve_system_map_clock( + clock_override: Optional[int], + instances: Dict[str, KernelInstance], + *, + default_hz: int = DEFAULT_CLOCK_HZ, +) -> int: + if clock_override is not None: + return int(clock_override) + freqs = sorted( + { + int(inst.params.get("clock_hz")) + for inst in instances.values() + if inst.params.get("clock_hz") is not None + } + ) + if freqs: + return freqs[0] + return default_hz + + +def _format_hex(value: int) -> str: + if value == 0: + return "0" + return hex(value) + + +def _format_hex_prefixed(value: int) -> str: + return hex(value) + + +def _normalize_access(access: Optional[str]) -> str: + if not access: + return "" + key = access.strip().lower().replace("-", "_") + return { + "read_only": "R", + "readonly": "R", + "ro": "R", + "r": "R", + "write_only": "W", + "writeonly": "W", + "wo": "W", + "w": "W", + "read_write": "RW", + "readwrite": "RW", + "rw": "RW", + }.get(key, access) + + +def _select_register_block(kernel, busif: str) -> Optional[AddressBlock]: + mmaps = getattr(kernel, "memory_maps", []) or [] + + for mm in mmaps: + if mm.name and mm.name.lower() == busif.lower(): + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register": + return ab + if mm.address_blocks: + return mm.address_blocks[0] + + for mm in mmaps: + for ab in mm.address_blocks: + if (ab.usage or "").lower() == "register": + return ab + + for mm in mmaps: + if mm.address_blocks: + return mm.address_blocks[0] + + return None + + +def _register_stem(name: str) -> str: + m = _REG_SPLIT_RE.fullmatch(name or "") + return m.group(1) if m else name + + +def _is_split_register_name(name: str) -> bool: + return _REG_SPLIT_RE.fullmatch(name or "") is not None + + +def _access_flags(access: Optional[str]) -> tuple[int, int]: + norm = _normalize_access(access) + return (1 if "R" in norm else 0, 1 if "W" in norm else 0) + + +def _port_norm(name: str) -> str: + return _PORT_NORM_RE.sub("", (name or "").lower()) + + +def _resolve_axi4full_port_name(kernel, requested: str) -> Optional[str]: + if not requested: + return None + + axi4_ports = [p.name for p in kernel.ports_of_type(BusType.AXI4FULL)] + if requested in axi4_ports: + return requested + + by_lower = {p.lower(): p for p in axi4_ports} + req_low = requested.lower() + if req_low in by_lower: + return by_lower[req_low] + + by_norm = {_port_norm(p): p for p in axi4_ports} + req_norm = _port_norm(requested) + if req_norm in by_norm: + return by_norm[req_norm] + + return None + + +def _build_functional_args_from_hls( + hls_data: dict, + busif: str, + reg_block: Optional[AddressBlock], + *, + kernel=None, + connected_axi_ports: Optional[set[str]] = None, + instance_name: Optional[str] = None, +) -> List[dict]: + if reg_block is None or not reg_block.registers: + return [] + + reg_by_name = { + str(r.name): r for r in reg_block.registers if getattr(r, "name", None)} + out: List[tuple[int, int, dict]] = [] + + for order_idx, arg in enumerate(parse_hls_args(hls_data)): + idx = arg["index"] if arg["index"] is not None else order_idx + refs = [] + seen_names = set() + interface_refs: List[str] = [] + seen_ifaces = set() + for ref in arg.get("hw_refs", []): + ref_type = str(ref.get("type", "")).lower() + if ref_type == "interface": + iface_name = str(ref.get("interface", "") or "") + if iface_name and iface_name not in seen_ifaces: + seen_ifaces.add(iface_name) + interface_refs.append(iface_name) + continue + if ref_type != "register": + continue + usage = str(ref.get("usage", "")).lower() + if usage not in {"data", "address"}: + continue + iface = str(ref.get("interface", "") or "") + if iface and iface.lower() != busif.lower(): + continue + reg_name = str(ref.get("name", "") or "") + if not reg_name or reg_name in seen_names: + continue + reg = reg_by_name.get(reg_name) + if reg is None: + continue + seen_names.add(reg_name) + refs.append(reg) + + if not refs: + continue + + r_flag = 0 + w_flag = 0 + for reg in refs: + r, w = _access_flags(getattr(reg, "access", None)) + r_flag = max(r_flag, r) + w_flag = max(w_flag, w) + if r_flag == 0 and w_flag == 0: + continue + + base_offset = min(int(getattr(reg, "address_offset", 0) or 0) + for reg in refs) + logical_name = _register_stem( + str(getattr(refs[0], "name", "") or arg["name"])) + src_type = str(arg.get("src_type", "")) + src_size = arg.get("src_size") + reg_bits = sum(int(getattr(reg, "size", 32) or 32) for reg in refs) + has_address_ref = any( + str(ref.get("usage", "")).lower() == "address" for ref in (arg.get("hw_refs", []) or []) + ) + arg_type = "buffer" if ( + "*" in src_type or has_address_ref) else "scalar" + + if arg_type == "buffer": + if reg_bits > 0 and src_size is not None and src_size > 0: + range_bits = max(int(src_size), int(reg_bits)) + elif reg_bits > 0: + range_bits = int(reg_bits) + elif src_size is not None and src_size > 0: + range_bits = int(src_size) + else: + range_bits = 32 + else: + if src_size is not None and src_size > 0: + range_bits = int(src_size) + elif reg_bits > 0: + range_bits = int(reg_bits) + else: + range_bits = 32 + + arg_item = { + "idx": int(idx), + "name": logical_name, + "type": arg_type, + "offset": _format_hex_prefixed(base_offset), + "range": str(int(range_bits)), + "r": int(r_flag), + "w": int(w_flag), + } + + if arg_type == "buffer" and kernel is not None and connected_axi_ports is not None: + resolved_port = None + for iface_name in interface_refs: + canonical_port = _resolve_axi4full_port_name( + kernel, iface_name) + if canonical_port is None: + continue + if canonical_port not in connected_axi_ports: + continue + resolved_port = canonical_port + break + if resolved_port is None: + logger.warning( + "Could not correlate buffer arg '%s' on instance '%s' (kernel '%s') " + "to a connected AXI4FULL port from hwRefs interfaces %s; " + "omitting functional_args port metadata.", + arg["name"], + instance_name or "", + getattr(kernel, "name", ""), + interface_refs, + ) + else: + arg_item["port"] = resolved_port + + out.append( + ( + int(idx), + base_offset, + arg_item, + ) + ) + + out.sort(key=lambda item: (item[0], item[1], item[2]["name"])) + dense: List[dict] = [] + for new_idx, (_, _, item) in enumerate(out): + cloned = dict(item) + cloned["idx"] = new_idx + dense.append(cloned) + return dense + + +def _is_control_or_status_register(name: str) -> bool: + low = (name or "").strip().lower() + return low in _CONTROL_REGS or low.endswith("_ctrl") + + +def _infer_fallback_type(stem: str, is_split: bool) -> str: + low = stem.lower() + if is_split and (low.endswith("_r") or "ptr" in low): + return "buffer" + return "scalar" + + +def _build_functional_args_fallback(reg_block: Optional[AddressBlock]) -> List[dict]: + if reg_block is None or not reg_block.registers: + return [] + + groups: Dict[str, dict] = {} + for reg in sorted(reg_block.registers, key=lambda r: r.address_offset): + reg_name = str(getattr(reg, "name", "") or "") + if not reg_name or _is_control_or_status_register(reg_name): + continue + stem = _register_stem(reg_name) + g = groups.get(stem) + if g is None: + g = { + "name": stem, + "offset": int(getattr(reg, "address_offset", 0) or 0), + "regs": [], + "split": False, + } + groups[stem] = g + g["regs"].append(reg) + g["split"] = bool(g["split"] or _is_split_register_name(reg_name)) + g["offset"] = min(g["offset"], int( + getattr(reg, "address_offset", 0) or 0)) + + ordered = sorted(groups.values(), key=lambda g: (g["offset"], g["name"])) + out: List[dict] = [] + next_idx = 0 + for g in ordered: + r_flag = 0 + w_flag = 0 + total_range = 0 + for reg in g["regs"]: + r, w = _access_flags(getattr(reg, "access", None)) + r_flag = max(r_flag, r) + w_flag = max(w_flag, w) + total_range += int(getattr(reg, "size", 32) or 32) + if r_flag == 0 and w_flag == 0: + continue + + out.append( + { + "idx": next_idx, + "name": g["name"], + "type": _infer_fallback_type(g["name"], bool(g["split"])), + "offset": _format_hex_prefixed(int(g["offset"])), + "range": str(int(total_range)), + "r": int(r_flag), + "w": int(w_flag), + } + ) + next_idx += 1 + + return out + + +def _coerce_optional_int(v) -> Optional[int]: + if v is None: + return None + if isinstance(v, int): + return v + s = str(v).strip() + if s == "": + return None + try: + return int(s, 0) + except ValueError: + return None + + +def _assign_mem_indices( + instances: Dict[str, KernelInstance], + *, + num_mem_ports: int = 8, +) -> Dict[Tuple[str, str], int]: + buckets: Dict[int, List[Tuple[str, str]]] = { + i: [] for i in range(num_mem_ports)} + rr = 0 + + for inst in instances.values(): + mem_sp = inst.params.get("mem_sp", {}) or {} + for k_port, tgt in mem_sp.items(): + if tgt.get("domain") != "MEM": + continue + if inst.kernel.port(k_port).ptype != BusType.AXI4FULL: + continue + idx = _coerce_optional_int(tgt.get("index")) + if idx is not None and not (0 <= idx < num_mem_ports): + raise ValueError( + f"MEM index {idx} out of range (0..{num_mem_ports - 1}) for {inst.name}/{k_port}" + ) + if idx is None: + idx = rr % num_mem_ports + rr += 1 + buckets[idx].append((inst.name, k_port)) + + mapping: Dict[Tuple[str, str], int] = {} + for idx, items in buckets.items(): + for inst_name, port in items: + mapping[(inst_name, port)] = idx + return mapping + + +def _format_target(domain: str, index: Optional[int]) -> str: + dom = domain.upper() + if index is None or index == "": + return dom + return f"{dom}{index}" + + +def build_system_map_context( + instances: Dict[str, KernelInstance], + axilite_addr: List[dict], + *, + clock_hz: int, + kernel_hls_by_type: Optional[Dict[str, Path]] = None, + platform: str = "Hardware", + num_mem_ports: int = 8, + num_virt: int = 4, + network: Optional[object] = None, +) -> dict: + axilite_by_inst: Dict[str, List[dict]] = {} + for entry in axilite_addr: + axilite_by_inst.setdefault(entry["inst"], []).append(entry) + + mem_indices = _assign_mem_indices(instances, num_mem_ports=num_mem_ports) + + hls_by_type = kernel_hls_by_type or {} + hls_cache: Dict[str, Optional[dict]] = {} + + def _kernel_hls_data(kernel_type: str) -> Optional[dict]: + if kernel_type in hls_cache: + return hls_cache[kernel_type] + hls_path = hls_by_type.get(kernel_type) + if hls_path is None: + hls_cache[kernel_type] = None + return None + hls_cache[kernel_type] = load_hls_metadata( + Path(hls_path), strict=False) + return hls_cache[kernel_type] + + kernels: List[dict] = [] + for inst_name in sorted(instances.keys()): + inst = instances[inst_name] + entries = sorted(axilite_by_inst.get( + inst_name, []), key=lambda e: e["busif"]) + if not entries: + continue + + selected = None + for e in entries: + if "control" in e["busif"].lower(): + selected = e + break + if selected is None: + for e in entries: + block = _select_register_block(inst.kernel, e["busif"]) + if block and block.registers: + selected = e + break + if selected is None: + selected = entries[0] + + reg_block = _select_register_block(inst.kernel, selected["busif"]) + registers: List[dict] = [] + if reg_block and reg_block.registers: + for reg in sorted(reg_block.registers, key=lambda r: r.address_offset): + registers.append( + { + "offset": _format_hex(reg.address_offset), + "name": reg.name, + "access": _normalize_access(reg.access), + "description": reg.description or "", + "range": str(reg.size), + } + ) + connections: List[dict] = [] + connected_axi_ports: set[str] = set() + mem_sp = inst.params.get("mem_sp", {}) or {} + for port in inst.kernel.ports_of_type(BusType.AXI4FULL): + tgt = mem_sp.get(port.name) + if not tgt: + continue + connected_axi_ports.add(port.name) + domain = str(tgt.get("domain", "")).upper() + idx = _coerce_optional_int(tgt.get("index")) + if domain == "MEM" and idx is None: + idx = mem_indices.get((inst.name, port.name)) + connections.append( + { + "port": port.name, + "target": _format_target(domain, idx), + } + ) + hls_data = _kernel_hls_data(inst.kernel.name) + if hls_data is not None: + functional_args = _build_functional_args_from_hls( + hls_data, + selected["busif"], + reg_block, + kernel=inst.kernel, + connected_axi_ports=connected_axi_ports, + instance_name=inst_name, + ) + else: + functional_args = _build_functional_args_fallback(reg_block) + + kernels.append( + { + "name": inst.name, + "base_addr": _format_hex(int(selected["offset"])), + "range": _format_hex(int(selected["range"])), + "registers": registers, + "functional_args": functional_args, + "connections": connections, + } + ) + + enabled_eth = [] + if network is not None: + enabled_eth = sorted(getattr(network, "enabled_eth", set()) or []) + + service_layer = { + "eth_enabled": bool(enabled_eth), + "eth_indices": enabled_eth, + "virt": [{"index": i, "connection": "unused"} for i in range(num_virt)], + } + + return { + "platform": platform, + "clock_hz": int(clock_hz), + "kernels": kernels, + "service_layer": service_layer, + } diff --git a/linker/slashkit/emit/metadata/timing_freq.py b/linker/slashkit/emit/metadata/timing_freq.py new file mode 100644 index 00000000..ebd49a76 --- /dev/null +++ b/linker/slashkit/emit/metadata/timing_freq.py @@ -0,0 +1,212 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +import logging +import math +import os +from pathlib import Path +import re +from typing import Optional +import xml.etree.ElementTree as ET + +logger = logging.getLogger(__name__) + +HW_BUILD_DIR_ENV_KEYS = ("SLASH_HW_BUILD_DIR", "slash_hw_build_dir") + + +def extract_design_wns_ns(report_text: str) -> Optional[float]: + if not report_text: + return None + + lines = report_text.splitlines() + design_idx = None + for i, line in enumerate(lines): + if "Design Timing Summary" in line: + design_idx = i + break + if design_idx is None: + return None + + header_idx = None + for i in range(design_idx, min(design_idx + 120, len(lines))): + if "WNS(ns)" in lines[i] and "TNS(ns)" in lines[i]: + header_idx = i + break + if header_idx is None: + return None + + for i in range(header_idx + 1, min(header_idx + 20, len(lines))): + line = lines[i].strip() + if not line: + continue + if set(line) <= {"-", " "}: + continue + m = re.match(r"^[-+]?\d+(?:\.\d+)?", line) + if m: + try: + return float(m.group(0)) + except ValueError: + return None + + return None + + +def compute_max_freq_hz_from_wns(wns_ns: float, base_freq_hz: int = 400_000_000) -> Optional[int]: + if base_freq_hz <= 0: + return None + + target_period_ns = 1e9 / float(base_freq_hz) + achievable_period_ns = target_period_ns - float(wns_ns) + if achievable_period_ns <= 0: + return None + + max_freq_hz = math.floor(1e9 / achievable_period_ns) + if max_freq_hz <= 0: + return None + return int(max_freq_hz) + + +def read_system_map_clock_hz(system_map_path: Path) -> Optional[int]: + if not system_map_path.exists(): + return None + + try: + root = ET.parse(system_map_path).getroot() + except ET.ParseError: + return None + + clock_node = root.find("ClockFrequency") + if clock_node is None or clock_node.text is None: + return None + + try: + return int(clock_node.text.strip()) + except ValueError: + return None + + +def write_system_map_clock_hz(system_map_path: Path, new_clock_hz: int) -> None: + tree = ET.parse(system_map_path) + root = tree.getroot() + + clock_node = root.find("ClockFrequency") + if clock_node is None: + clock_node = ET.SubElement(root, "ClockFrequency") + clock_node.text = str(int(new_clock_hz)) + + try: + ET.indent(tree, space=" ") + except AttributeError: + pass + tree.write(system_map_path, encoding="utf-8", xml_declaration=True) + + +def _resolve_hw_build_dir(explicit_hw_build_dir: Optional[Path]) -> Optional[Path]: + if explicit_hw_build_dir is not None: + return explicit_hw_build_dir.expanduser().resolve() + + for key in HW_BUILD_DIR_ENV_KEYS: + configured = os.getenv(key) + if configured: + return Path(configured).expanduser().resolve() + return None + + +def _find_timing_report(project_name: str, hw_build_dir: Path) -> Optional[Path]: + slash_rm_dir = hw_build_dir / "rm" / f"slash_{project_name}" + candidates = [ + slash_rm_dir / f"report_timing_{project_name}.txt", + slash_rm_dir / "report_timing.txt", + ] + for path in candidates: + if path.exists() and path.is_file(): + return path + return None + + +def apply_timing_frequency_cap( + *, + project_name: str, + system_map_path: Path, + base_freq_hz: int = 400_000_000, + hw_build_dir: Optional[Path] = None, +) -> Optional[int]: + user_clock_hz = read_system_map_clock_hz(system_map_path) + if user_clock_hz is None: + logger.warning( + "ClockFrequency missing or invalid in system_map.xml: %s", system_map_path) + return None + + resolved_hw_build_dir = _resolve_hw_build_dir(hw_build_dir) + if resolved_hw_build_dir is None: + logger.warning( + "HW build directory env var is unset; keeping user clock_hz=%d", user_clock_hz) + return user_clock_hz + + timing_report = _find_timing_report(project_name, resolved_hw_build_dir) + if timing_report is None: + logger.warning( + "Timing report not found under %s for project %s; keeping user clock_hz=%d", + resolved_hw_build_dir, + project_name, + user_clock_hz, + ) + return user_clock_hz + + logger.info("Timing report for frequency cap: %s", timing_report) + report_text = timing_report.read_text(encoding="utf-8", errors="replace") + wns_ns = extract_design_wns_ns(report_text) + if wns_ns is None: + logger.warning( + "Could not parse WNS(ns) from timing report %s; keeping user clock_hz=%d", timing_report, user_clock_hz) + return user_clock_hz + + computed_max_hz = compute_max_freq_hz_from_wns( + wns_ns, base_freq_hz=base_freq_hz) + if computed_max_hz is None: + logger.warning( + "Computed max frequency is invalid (WNS=%s ns, base=%d Hz); keeping user clock_hz=%d", + wns_ns, + base_freq_hz, + user_clock_hz, + ) + return user_clock_hz + + final_clock_hz = min(user_clock_hz, computed_max_hz) + logger.info( + "Timing frequency cap: WNS(ns)=%.3f, base_freq_hz=%d, computed_max_hz=%d, user_clock_hz=%d, final_clock_hz=%d", + wns_ns, + base_freq_hz, + computed_max_hz, + user_clock_hz, + final_clock_hz, + ) + + if final_clock_hz != user_clock_hz: + write_system_map_clock_hz(system_map_path, final_clock_hz) + logger.info("Updated system_map ClockFrequency to %d: %s", + final_clock_hz, system_map_path) + else: + logger.info("Keeping user ClockFrequency=%d in system_map: %s", + user_clock_hz, system_map_path) + + return final_clock_hz diff --git a/linker/slashkit/emit/render.py b/linker/slashkit/emit/render.py new file mode 100644 index 00000000..a5e66472 --- /dev/null +++ b/linker/slashkit/emit/render.py @@ -0,0 +1,50 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from jinja2 import Environment, PackageLoader, StrictUndefined +from pathlib import Path +from importlib import resources +import shutil + + +def render_template(template: str | Path, out_path: str | Path, context: dict) -> None: + env = Environment( + loader=PackageLoader("slashkit.resources"), + undefined=StrictUndefined, + trim_blocks=True, + lstrip_blocks=True, + ) + env.filters["zip"] = lambda a, b: zip(a, b) + tmpl = env.get_template(template) + Path(out_path).write_text(tmpl.render(**context), encoding="utf-8") + + +def export_package(package, out_dir: str | Path) -> None: + def impl(traversable, out_path: Path) -> None: + if traversable.is_file(): + with resources.as_file(traversable) as in_path: + shutil.copy(in_path, out_path) + elif traversable.is_dir(): + out_path.mkdir() + for sub_traversable in traversable.iterdir(): + impl(sub_traversable, out_path / sub_traversable.name) + + impl(resources.files(package), out_dir) diff --git a/linker/slashkit/emit/sim/__init__.py b/linker/slashkit/emit/sim/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/emit/sim/project_gen.py b/linker/slashkit/emit/sim/project_gen.py new file mode 100644 index 00000000..fca8a70e --- /dev/null +++ b/linker/slashkit/emit/sim/project_gen.py @@ -0,0 +1,120 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +import importlib.resources as resources +import logging +import os +import shutil +import subprocess +import tarfile + +from slashkit.core.command_config import LinkerConfiguration +from slashkit.emit.render import export_package + +logger = logging.getLogger(__name__) + + +def create_sim_project(config: LinkerConfiguration) -> None: + config.build_dir.mkdir(parents=True, exist_ok=True) + + # Clean generated subfolders but keep run_pre.tcl if already generated. + for sub in ["sim_prj", "build", "xsim.dir"]: + p = config.build_dir / sub + if p.exists(): + shutil.rmtree(p, ignore_errors=True) + for p in config.build_dir.glob("vpp_sim*"): + if p.is_file(): + try: + p.unlink() + except OSError: + pass + + # Copy all kernels into the IP repository + for kernel in config.kernels: + shutil.copytree(kernel.component_xml_path.parent, + config.ip_repository / kernel.name) + + tcl = config.build_dir / "run_pre.tcl" + if not tcl.exists(): + raise FileNotFoundError(f"Simulation TCL not found: {tcl}") + + log_path = config.build_dir / "vivado.log" + + cmd = [ + config.vivado_bin, + "-mode", + "tcl", + "-nojournal", + "-log", + str(log_path), + "-source", + str(tcl), + ] + subprocess.run(cmd, cwd=str(config.build_dir), check=True) + + +def build_sim_project(config: LinkerConfiguration) -> None: + xsim_dir = config.build_dir / "sim_prj" / \ + "sim_prj.sim" / "sim_1" / "behav" / "xsim" + if not xsim_dir.exists(): + raise FileNotFoundError(f"XSIM dir not found: {xsim_dir}") + + subprocess.run(["./compile.sh"], cwd=str(xsim_dir), check=True) + subprocess.run(["./elaborate.sh"], cwd=str(xsim_dir), check=True) + + cmake_build_dir = config.build_dir / "build" + + # Copy xsim.dir into build dir for sim executable + xsim_build_dir = cmake_build_dir / "xsim.dir" + if xsim_build_dir.exists(): + shutil.rmtree(xsim_build_dir, ignore_errors=True) + shutil.copytree(xsim_dir / "xsim.dir", xsim_build_dir) + + sim_src_dir = config.build_dir / "sim_src" + export_package("slashkit.resources.sim", sim_src_dir) + + subprocess.run(["cmake", str(sim_src_dir)], + cwd=str(cmake_build_dir), check=True) + jobs = str(os.cpu_count() or 8) + subprocess.run(["make", "-j", jobs], cwd=str(cmake_build_dir), check=True) + + vpp_sim_path = cmake_build_dir / "vpp_sim" + if not vpp_sim_path.exists(): + raise FileNotFoundError(f"vpp_sim not found: {vpp_sim_path}") + shutil.copy2(vpp_sim_path, config.build_dir / "vpp_sim") + + # Copy xsim.dir next to vpp_sim for runtime + xsim_result_dir = config.build_dir / "xsim.dir" + if xsim_result_dir.exists(): + shutil.rmtree(xsim_result_dir, ignore_errors=True) + shutil.copytree(xsim_build_dir, xsim_result_dir) + + system_map_path = config.build_dir / "system_map.xml" + if not system_map_path.exists(): + raise FileNotFoundError(f"system_map.xml not found: {system_map_path}") + + with tarfile.open(config.out_path, mode="w") as tf: + tf.add(system_map_path, arcname="system_map.xml") + tf.add(vpp_sim_path, arcname="vpp_sim") + tf.add(xsim_build_dir, arcname="xsim.dir") + + logger.info("Simulation build outputs in %s", config.build_dir) diff --git a/linker/slashkit/emit/sim/tcl_gen.py b/linker/slashkit/emit/sim/tcl_gen.py new file mode 100644 index 00000000..d15adf3c --- /dev/null +++ b/linker/slashkit/emit/sim/tcl_gen.py @@ -0,0 +1,371 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations + +from pathlib import Path +import logging +import xml.etree.ElementTree as ET +from typing import List, Tuple +import importlib.resources as resources + +from slashkit.emit.render import render_template +from slashkit.emit.hw.user_region.addr_ctx import build_axilite_address_context +from slashkit.emit.hw.service_region.stream_ctx import build_stream_connect_context +from slashkit.emit.metadata.system_map_ctx import build_system_map_context, resolve_system_map_clock +from slashkit.core.command_config import LinkerConfiguration + +from slashkit.core.kernel import KernelInstance +from slashkit.core.port import BusType + +logger = logging.getLogger(__name__) + +_IPXACT_NS = { + "spirit": "http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009", +} + + +def _xml_text(el: ET.Element | None) -> str | None: + if el is None or el.text is None: + return None + txt = el.text.strip() + return txt if txt else None + + +def _find_sim_checkpoint_dcp(component_xml: Path) -> str | None: + """ + Return the relative DCP path from the xilinx_simulationcheckpoint_view_fileset, if present. + """ + root = ET.parse(component_xml).getroot() + for fs in root.findall("spirit:fileSets/spirit:fileSet", _IPXACT_NS): + if _xml_text(fs.find("spirit:name", _IPXACT_NS)) != "xilinx_simulationcheckpoint_view_fileset": + continue + for f in fs.findall("spirit:file", _IPXACT_NS): + rel = _xml_text(f.find("spirit:name", _IPXACT_NS)) + if not rel: + continue + user_types = { + (_xml_text(uft) or "").lower() + for uft in f.findall("spirit:userFileType", _IPXACT_NS) + } + if "dcp" in user_types or rel.lower().endswith(".dcp"): + return rel + return None + + +def _collect_ports( + instances: dict[str, KernelInstance], +) -> tuple[List[Tuple[str, str]], List[Tuple[str, str]], List[Tuple[str, str]], List[Tuple[str, str]]]: + axilite: List[Tuple[str, str]] = [] + axifull: List[Tuple[str, str]] = [] + clocks: List[Tuple[str, str]] = [] + resets: List[Tuple[str, str]] = [] + + for iname in sorted(instances.keys()): + inst = instances[iname] + ports = sorted(inst.kernel.ports.values(), key=lambda p: p.name) + for p in ports: + if p.ptype == BusType.AXILITE: + axilite.append((iname, p.name)) + elif p.ptype == BusType.AXI4FULL: + axifull.append((iname, p.name)) + elif p.ptype == BusType.CLOCK: + phys = inst.kernel.bus_physical_port(p.name) or p.name + clocks.append((iname, phys)) + elif p.ptype == BusType.RESET: + phys = inst.kernel.bus_physical_port(p.name) or p.name + resets.append((iname, phys)) + + return axilite, axifull, clocks, resets + + +def _fmt_sc_slot(prefix: str, idx: int) -> str: + if idx < 10: + return f"{prefix}0{idx}_AXI" + return f"{prefix}{idx}_AXI" + + +def _build_reduction_tree( + sources: List[str], + *, + max_si: int = 16, + max_roots: int | None = None, + base_name: str = "sc_red", +) -> tuple[List[dict], List[str]]: + """ + Build a SmartConnect reduction tree: + - leaves connect sources to node SIs + - each node outputs M00_AXI + Returns (nodes, roots) where roots are src pins feeding the final consumer. + """ + if max_roots is None: + max_roots = max_si + + if len(sources) <= max_roots: + return [], sources + + nodes: List[dict] = [] + level = 0 + current = [{"src": s} for s in sources] + while len(current) > max_roots: + groups = [current[i:i+max_si] for i in range(0, len(current), max_si)] + next_level = [] + for g_idx, group in enumerate(groups): + name = f"{base_name}_L{level}_{g_idx}" + node = { + "name": name, + "num_si": len(group), + "si": [ + {"slot_name": _fmt_sc_slot("S", i), "src": g["src"]} + for i, g in enumerate(group) + ], + } + nodes.append(node) + next_level.append({"src": f"{name}/M00_AXI"}) + current = next_level + level += 1 + + roots = [g["src"] for g in current] + return nodes, roots + + +def _build_fanout_tree( + endpoints: List[str], + *, + max_mi: int = 16, + base_name: str = "axi_sc", + si_bd_port: str = "s_axi_ctrl", +) -> List[dict]: + """ + Build a SmartConnect fanout tree (1 SI, many MIs) with max_mi per node. + Returns nodes with create+connect metadata. + """ + if not endpoints: + return [] + + nodes: dict[str, dict] = {} + child_parent: dict[str, tuple[str, int]] = {} + + # Build leaf nodes that connect directly to endpoints. + leaves: List[str] = [] + for idx, chunk_start in enumerate(range(0, len(endpoints), max_mi)): + name = f"{base_name}_L0_{idx}" + chunk = endpoints[chunk_start:chunk_start + max_mi] + mi = [{"slot_name": _fmt_sc_slot("M", i), "dst_pin": ep} + for i, ep in enumerate(chunk)] + nodes[name] = {"name": name, "num_mi": len(mi), "mi": mi} + leaves.append(name) + + # Build parent levels that fanout to child smartconnects. + level = 1 + current = leaves + while len(current) > 1: + next_level: List[str] = [] + for g_idx, group_start in enumerate(range(0, len(current), max_mi)): + group = current[group_start:group_start + max_mi] + name = f"{base_name}_L{level}_{g_idx}" + mi = [] + for i, child in enumerate(group): + mi.append({"slot_name": _fmt_sc_slot("M", i), + "dst_pin": f"{child}/S00_AXI"}) + child_parent[child] = (name, i) + nodes[name] = {"name": name, "num_mi": len(mi), "mi": mi} + next_level.append(name) + current = next_level + level += 1 + + root = current[0] + for n in nodes.values(): + if n["name"] == root: + n["si_from"] = {"type": "bd_port", "name": si_bd_port} + else: + parent, slot = child_parent[n["name"]] + n["si_from"] = {"type": "smartconnect", "prev": parent, + "prev_slot_name": _fmt_sc_slot("M", slot)} + + # Stable order: root first, then others by name + ordered = [nodes[root]] + \ + [n for k, n in sorted(nodes.items()) if k != root] + return ordered + + +def _classify_mem_targets(instances: dict[str, KernelInstance]) -> tuple[List[str], List[str]]: + mem0: List[str] = [] + mem1: List[str] = [] + for iname in sorted(instances.keys()): + inst = instances[iname] + mem_map = inst.params.get("mem_sp", {}) + for p in inst.kernel.ports_of_type(BusType.AXI4FULL): + tgt = mem_map.get(p.name, {"domain": "MEM"}) + domain = (tgt.get("domain") or "MEM").upper() + ep = f"{iname}/{p.name}" + if domain == "DDR": + mem1.append(ep) + else: + mem0.append(ep) + return mem0, mem1 + + +def generate_sim_tcl(config: LinkerConfiguration) -> None: + # 1) Parse kernels + cfg = config.configuration + instances = {kernel.name: kernel for kernel in config.kernel_instances} + streams = cfg.streams + kernel_hls_by_type = { + kernel.name: kernel.hls_data_path for kernel in config.kernels} + + kernel_sim_meta: dict[str, dict] = {} + for kernel in config.kernels: + kpath = kernel.component_xml_path + + sim_checkpoint_rel = _find_sim_checkpoint_dcp(kpath) + sim_checkpoint_abs = None + if sim_checkpoint_rel is not None: + sim_checkpoint_abs = (kpath.parent / sim_checkpoint_rel).resolve() + if not sim_checkpoint_abs.exists(): + raise FileNotFoundError( + f"Simulation checkpoint DCP from component.xml not found: {sim_checkpoint_abs}" + ) + kernel_sim_meta[kernel.name] = { + "component_xml": str(kpath), + "sim_checkpoint_dcp": str(sim_checkpoint_abs) if sim_checkpoint_abs else None, + } + + # 4) Build template context + axilite_ports, axifull_ports, clock_ports, reset_ports = _collect_ports( + instances) + + kernels_ctx = [] + for iname in sorted(instances.keys()): + inst = instances[iname] + vlnv = inst.kernel.vlnv or f"xilinx.com:hls:{inst.kernel.name}:1.0" + kernels_ctx.append({"name": iname, "vlnv": vlnv}) + + sim_checkpoint_netlists_ctx = [] + sim_ckpt_out_dir = config.build_dir / "checkpoint_funcsim" + for iname in sorted(instances.keys()): + inst = instances[iname] + sim_meta = kernel_sim_meta.get(inst.kernel.name, {}) + dcp_path = sim_meta.get("sim_checkpoint_dcp") + if not dcp_path: + continue + top_mod = f"top_{iname}_0" + sim_checkpoint_netlists_ctx.append({ + "inst": iname, + "dcp_path": dcp_path, + "funcsim_v_path": str((sim_ckpt_out_dir / f"{top_mod}.v").resolve()), + "rename_top": top_mod, + "rename_prefix": f"{top_mod}_", + }) + + axilite_endpoints = [f"{iname}/{pname}" for iname, pname in axilite_ports] + axilite_sc_ctx = _build_fanout_tree( + axilite_endpoints, + max_mi=16, + base_name="axi_sc", + si_bd_port="s_axi_ctrl", + ) + + mem_reduce_nodes, mem_roots = _build_reduction_tree( + [f"{iname}/{pname}" for iname, pname in axifull_ports], + max_si=16, + max_roots=15, + base_name="mem_sc_red", + ) + mem_roots_ctx = [ + {"slot_name": _fmt_sc_slot("S", idx + 1), "src_pin": src} + for idx, src in enumerate(mem_roots) + ] + mem_sc_num_si = 1 + len(mem_roots_ctx) + + stream_ctx = build_stream_connect_context(instances, streams) + axis_streams_ctx = [] + for s in stream_ctx.get("axis_streams", []): + axis_streams_ctx.append({ + "src_pin": s["src_pin"], + "dst_pin": s["dst_pin"], + "net_name": s["src_pin"].replace("/", "_"), + }) + + axilite_ctx = build_axilite_address_context( + instances, + addr_space="S_AXILITE_INI", + base_offset=0x0202_0000_0000, + min_align=0x0001_0000, + ) + axilite_addr_ctx = [] + for item in axilite_ctx.get("axilite_addr", []): + axilite_addr_ctx.append({ + "inst": item["inst"], + "busif": item["busif"], + "segment": item["segment"], + "offset_hex": f"0x{item['offset']:X}", + "range_hex": f"0x{item['range']:X}", + }) + + # 5) Render sim_prj.tcl template + sim_out = config.build_dir / "run_pre.tcl" + + sim_mem_src = resources.read_text( + "slashkit.resources.sim", "sim_mem.v", encoding="utf-8") + sim_mem_dst = config.build_dir / "sim_mem.v" + sim_mem_dst.write_text(sim_mem_src) + + render_template( + template="sim_prj.tcl", + out_path=sim_out, + context={ + "sim_root": config.build_dir, + "sim_prj_dir": str(config.build_dir / "sim_prj"), + "ip_repo_path": str(config.build_dir / "iprepo"), + "sim_mem_path": str(sim_mem_dst), + "bd_name": "top", + "part": "xcv80-lsva4737-2MHP-e-S", + "kernels": kernels_ctx, + "sim_checkpoint_netlists": sim_checkpoint_netlists_ctx, + "axilite_scs": axilite_sc_ctx, + "mem_reduce_nodes": mem_reduce_nodes, + "mem_roots": mem_roots_ctx, + "mem_sc_num_si": mem_sc_num_si, + "clock_ports": [f"{iname}/{pname}" for iname, pname in clock_ports], + "reset_ports": [f"{iname}/{pname}" for iname, pname in reset_ports], + "axis_streams": axis_streams_ctx, + "axilite_addr": axilite_addr_ctx, + }, + ) + logger.info("Rendered simulation Tcl to %s", sim_out) + + # 6) Render system map (same as HW but marked as Simulation) + clock_hz = resolve_system_map_clock(config.clock_hz, instances) + system_map_ctx = build_system_map_context( + instances, + axilite_ctx.get("axilite_addr", []), + clock_hz=clock_hz, + platform="Simulation", + kernel_hls_by_type=kernel_hls_by_type, + network=getattr(cfg, "network", None), + ) + system_map_out = config.build_dir / "system_map.xml" + render_template( + template="system_map.xml", + out_path=system_map_out, + context=system_map_ctx, + ) + logger.info("Rendered system map to %s", system_map_out) diff --git a/linker/slashkit/parser/__init__.py b/linker/slashkit/parser/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/parser/component_parser.py b/linker/slashkit/parser/component_parser.py new file mode 100644 index 00000000..0c7c087d --- /dev/null +++ b/linker/slashkit/parser/component_parser.py @@ -0,0 +1,282 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from pathlib import Path +from typing import Dict, Optional, List +import xml.etree.ElementTree as ET +import logging + +from slashkit.core.port import Port, BusType +from slashkit.core.bus import Bus +from slashkit.core.kernel import Kernel +from slashkit.core.regs import MemoryMap, AddressBlock, Register, RegField # NEW +from slashkit.emit.hls_meta import infer_hls_json_from_component_xml + +logger = logging.getLogger(__name__) + +# Namespaces used in Xilinx IP-XACT component.xml +NS = { + "spirit": "http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009", + "xilinx": "http://www.xilinx.com", +} + + +def _is_slave(busif: ET.Element) -> bool: + return busif.find("spirit:slave", NS) is not None + + +def _text(el: Optional[ET.Element]) -> Optional[str]: + return el.text.strip() if el is not None and el.text is not None else None + + +def _int(el: Optional[ET.Element]) -> Optional[int]: + t = _text(el) + if t is None: + return None + try: + return int(t, 0) # supports hex/dec + except ValueError: + return None + + +def _param_map(busif: ET.Element) -> Dict[str, str]: + params = {} + for p in busif.findall("spirit:parameters/spirit:parameter", NS): + name = _text(p.find("spirit:name", NS)) + val = _text(p.find("spirit:value", NS)) + if name and val is not None: + params[name.strip().upper()] = val.strip() + return params + + +def _bus_type(busif: ET.Element) -> tuple[str, str, str, str]: + b = busif.find("spirit:busType", NS) + return ( + b.get(f"{{{NS['spirit']}}}vendor", ""), + b.get(f"{{{NS['spirit']}}}library", ""), + b.get(f"{{{NS['spirit']}}}name", ""), + b.get(f"{{{NS['spirit']}}}version", ""), + ) + + +def _port_maps(busif: ET.Element) -> Dict[str, str]: + mapping: Dict[str, str] = {} + for pm in busif.findall("spirit:portMaps/spirit:portMap", NS): + l_name = _text(pm.find("spirit:logicalPort/spirit:name", NS)) + p_name = _text(pm.find("spirit:physicalPort/spirit:name", NS)) + if l_name and p_name: + mapping[l_name] = p_name + return mapping + + +def _logical_to_ports(logical_to_name: Dict[str, str], ptype: BusType) -> Dict[str, Port]: + mapped: Dict[str, Port] = {} + for logical, physical in logical_to_name.items(): + mapped[logical] = Port(name=physical, ptype=ptype) + return mapped + + +def _to_port_type(bus_vendor: str, bus_lib: str, bus_name: str, + params: Dict[str, str], is_slave: bool) -> Optional[BusType]: + key = (bus_vendor, bus_lib, bus_name) + + if key == ("xilinx.com", "interface", "axis"): + return BusType.AXIS + + if key == ("xilinx.com", "interface", "aximm"): + if params.get("PROTOCOL", "").strip().upper() == "AXI4LITE": + return BusType.AXILITE + if is_slave: + return BusType.AXILITE + return BusType.AXI4FULL + + if key == ("xilinx.com", "signal", "clock"): + return BusType.CLOCK + if key == ("xilinx.com", "signal", "reset"): + return BusType.RESET + if key == ("xilinx.com", "signal", "interrupt"): + return BusType.INTERRUPT + + return None + + +def _axis_width_from_params(params: Dict[str, str]) -> Optional[int]: + tbytes = params.get("TDATA_NUM_BYTES") + if tbytes and tbytes.isdigit(): + return int(tbytes) * 8 + return None + + +def _aximm_width_from_params(params: Dict[str, str]) -> Optional[int]: + dw = params.get("DATA_WIDTH") + if dw and dw.isdigit(): + return int(dw) + return None + +# ---------- memory map parsing ---------- + + +def _parse_fields(reg_el: ET.Element) -> List[RegField]: + fields: List[RegField] = [] + for f in reg_el.findall("spirit:field", NS): + fields.append(RegField( + name=_text(f.find("spirit:name", NS)) or "", + description=_text(f.find("spirit:description", NS)), + bit_offset=_int(f.find("spirit:bitOffset", NS)) or 0, + bit_width=_int(f.find("spirit:bitWidth", NS)) or 1, + access=_text(f.find("spirit:access", NS)), + modified_write_value=_text( + f.find("spirit:modifiedWriteValue", NS)), + read_action=_text(f.find("spirit:readAction", NS)), + reset_value=_int(f.find("spirit:reset/spirit:value", NS)), + )) + return fields + + +def _parse_registers(ab_el: ET.Element) -> List[Register]: + regs: List[Register] = [] + for r in ab_el.findall("spirit:register", NS): + regs.append(Register( + name=_text(r.find("spirit:name", NS)) or "", + display_name=_text(r.find("spirit:displayName", NS)), + description=_text(r.find("spirit:description", NS)), + address_offset=_int(r.find("spirit:addressOffset", NS)) or 0, + size=_int(r.find("spirit:size", NS)) or 32, + access=_text(r.find("spirit:access", NS)), + reset_value=_int(r.find("spirit:reset/spirit:value", NS)), + fields=_parse_fields(r), + )) + return regs + + +def _parse_address_blocks(mm_el: ET.Element) -> List[AddressBlock]: + blocks: List[AddressBlock] = [] + for ab in mm_el.findall("spirit:addressBlock", NS): + # Optional named params inside addressBlock/parameters + obp = None + ohp = None + for p in ab.findall("spirit:parameters/spirit:parameter", NS): + pname = _text(p.find("spirit:name", NS)) + pval = _text(p.find("spirit:value", NS)) + if pname == "OFFSET_BASE_PARAM": + obp = pval + elif pname == "OFFSET_HIGH_PARAM": + ohp = pval + + blocks.append(AddressBlock( + name=_text(ab.find("spirit:name", NS)) or "unnamed", + base_address=_int(ab.find("spirit:baseAddress", NS)) or 0, + range=_int(ab.find("spirit:range", NS)) or 0, + width=_int(ab.find("spirit:width", NS)) or 32, + usage=_text(ab.find("spirit:usage", NS)), + access=_text(ab.find("spirit:access", NS)), + offset_base_param=obp, + offset_high_param=ohp, + registers=_parse_registers(ab), + )) + return blocks + + +def _parse_memory_maps(root: ET.Element) -> List[MemoryMap]: + maps: List[MemoryMap] = [] + for mm in root.findall("spirit:memoryMaps/spirit:memoryMap", NS): + maps.append(MemoryMap( + name=_text(mm.find("spirit:name", NS)) or "unnamed", + address_blocks=_parse_address_blocks(mm), + )) + return maps + +# ---------- main entry ---------- + + +def parse_component_xml(path: str | Path) -> Kernel: + path = Path(path) + tree = ET.parse(path) + root = tree.getroot() + + k_vendor = _text(root.find("spirit:vendor", NS)) or "" + k_lib = _text(root.find("spirit:library", NS)) or "" + k_name = _text(root.find("spirit:name", NS)) or "unknown" + k_ver = _text(root.find("spirit:version", NS)) or "" + vlnv = f"{k_vendor}:{k_lib}:{k_name}:{k_ver}" + + kernel_name = k_name + ports: Dict[str, Port] = {} + buses: Dict[str, Bus] = {} + + for busif in root.findall("spirit:busInterfaces/spirit:busInterface", NS): + busif_name = _text(busif.find("spirit:name", NS)) + if not busif_name: + continue + params = _param_map(busif) + vendor, lib, bname, _ = _bus_type(busif) + is_slave = _is_slave(busif) + ptype = _to_port_type(vendor, lib, bname, params, is_slave) + if ptype is None: + continue + + port_maps = _port_maps(busif) + width: Optional[int] = None + if ptype == BusType.AXIS: + width = _axis_width_from_params(params) + elif ptype in (BusType.AXILITE, BusType.AXI4FULL): + width = _aximm_width_from_params(params) + else: + width = 1 + + bus = Bus( + name=busif_name, + ptype=ptype, + width=width, + logical_to_physical=_logical_to_ports(port_maps, ptype), + ) + buses[busif_name] = bus + + # AXI-style interfaces are addressed by bus-interface name in TCL. + # Signal-style interfaces (clock/reset/interrupt) are addressed by pin name. + port_name = busif_name + if ptype in {BusType.CLOCK, BusType.RESET, BusType.INTERRUPT}: + port_name = bus.physical_port_name() or busif_name + + ports[port_name] = Port(name=port_name, ptype=ptype, width=width) + + memory_maps = _parse_memory_maps(root) + + try: + hls_data_path = infer_hls_json_from_component_xml(path) + except FileNotFoundError: + logger.warning( + "No HLS metadata found for kernel type '%s' from component %s; " + "system_map functional_args will use heuristic fallback.", + kernel_name, + path, + ) + hls_data_path = None + + return Kernel( + name=kernel_name, + component_xml_path=path, + ports=ports, + buses=buses, + vlnv=vlnv, + memory_maps=memory_maps, + hls_data_path=hls_data_path + ) diff --git a/linker/slashkit/parser/config_parser.py b/linker/slashkit/parser/config_parser.py new file mode 100644 index 00000000..178a5f03 --- /dev/null +++ b/linker/slashkit/parser/config_parser.py @@ -0,0 +1,312 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +from __future__ import annotations +from dataclasses import dataclass +from pathlib import Path +from typing import Dict, List, Optional, Tuple +import re + +from slashkit.core.kernel import Kernel, KernelInstance +from slashkit.core.connectivity import * +from slashkit.core.port import BusType + + +# ----------------------------- +# Parsing helpers +# ----------------------------- + +_RE_TARGET = re.compile(r"^\s*([A-Za-z]+)\s*(\d*)\s*$") +_RE_NK = re.compile(r"^\s*([^:]+)\s*:\s*(\d+)(?::(.*))?\s*$") +_RE_ETH_KEY = re.compile(r"^eth_(\d+)$", re.IGNORECASE) +_RE_DEBUG_NET = re.compile(r"^\s*([^.:\s]+)\.([^.:\s]+)\s*$") + + +def _parse_target(s: str) -> MemoryTarget: + m = _RE_TARGET.match(s) + if not m: + raise ValueError( + f"Invalid memory target '{s}'. Expected e.g. HBM0, DDR3, MEM, HOST.") + domain, idx_str = m.group(1).upper(), m.group(2) + if domain not in {"HBM", "DDR", "MEM", "VIRT", "HOST"}: + raise ValueError( + f"Unsupported memory domain '{domain}'. Use HBM, DDR, MEM, VIRT or HOST.") + # HOST (and MEM) have no numeric index + idx = int(idx_str) if (idx_str and domain not in {"MEM", "HOST"}) else "" + return MemoryTarget(domain=domain, index=idx) + + +def _split_instance_names(s: str) -> list[str]: + return [x for x in re.split(r"[.\s,]+", s.strip()) if x] + + +def _parse_nk_value(val: str) -> NKSpec: + """ + Accepts: + nk=perf:15:perf_0.perf_1....perf_14 + nk=dma:2:dma_0 dma_1 + nk=offset:1:offset_0 + nk=foo:3 # auto-names: foo_0..foo_2 + """ + m = _RE_NK.match(val) + if not m: + raise ValueError( + f"Invalid nk entry: '{val}' (expected ':[:]').") + + kernel_type = m.group(1).strip() + count = int(m.group(2)) + names_str = (m.group(3) or "").strip() + + names = _split_instance_names(names_str) if names_str else [] + if len(names) != count: + # Auto-fill or trim to match 'count' + base = kernel_type + names = ( + names + [f"{base}_{i}" for i in range(len(names), count)])[:count] + + return NKSpec(kernel_type=kernel_type, count=count, instance_names=names) + + +def _parse_stream_connect_value(val: str) -> StreamConnect: + """ + Expects: 'srcInst.srcPort:dstInst.dstPort' + """ + try: + left, right = val.split(":") + src_inst, src_port = left.split(".", 1) + dst_inst, dst_port = right.split(".", 1) + return StreamConnect(src_inst.strip(), src_port.strip(), + dst_inst.strip(), dst_port.strip()) + except Exception as e: + raise ValueError( + f"Invalid stream_connect '{val}'. Expected 'a.b:c.d'") from e + + +def _parse_sp_value(val: str) -> SpMapping: + """ + Expects: 'inst.port:HBM0' or 'inst.port:DDR3' + """ + try: + left, right = val.split(":") + inst, port = left.split(".", 1) + except Exception as e: + raise ValueError( + f"Invalid sp '{val}'. Expected 'inst.port:TARGET'") from e + target = _parse_target(right.strip()) + return SpMapping(inst=inst.strip(), port=port.strip(), target=target) + + +def _parse_debug_net_value(val: str) -> DebugNetSpec: + m = _RE_DEBUG_NET.match(val) + if not m: + raise ValueError( + f"Invalid debug net '{val}'. Expected '.'.") + return DebugNetSpec(inst=m.group(1).strip(), port=m.group(2).strip()) + + +# ----------------------------- +# Main parser +# ----------------------------- + +def parse_connectivity_file(path: str | Path) -> ConnectivityConfig: + """ + Custom parser that supports repeated [clock] sections, [network] section, + [user_region] section, [debug] section, and a single [connectivity] section. + Lines beginning with '#' or ';' are ignored as comments. + """ + cfg = ConnectivityConfig() + path = Path(path) + lines = path.read_text(encoding="utf-8").splitlines() + + section: Optional[str] = None + pending_clock: Dict[str, str] = {} + enabled_eth: set[int] = set() + pre_synth_tcls: list[str] = [] + debug_nets: list[DebugNetSpec] = [] + + def _commit_clock(): + nonlocal pending_clock + if not pending_clock: + return + krnl = pending_clock.get("krnl") + freq = pending_clock.get("freqhz") + if krnl and freq: + try: + cfg.clocks.append( + ClockSpec(inst=krnl.strip(), freq_hz=int(freq.strip()))) + except ValueError: + raise ValueError(f"Invalid freqhz value in [clock]: '{freq}'") + elif krnl or freq: + raise ValueError( + "Incomplete [clock] block: both 'krnl' and 'freqhz' are required.") + pending_clock = {} + + for raw in lines: + line = raw.strip() + if not line or line.startswith("#") or line.startswith(";"): + continue + + if line.startswith("[") and line.endswith("]"): + # New section starting — commit any pending clock + _commit_clock() + section = line[1:-1].strip().lower() + continue + + if section == "connectivity": + if line.startswith("nk="): + cfg.nk.append(_parse_nk_value(line.split("=", 1)[1].strip())) + elif line.startswith("stream_connect="): + cfg.streams.append(_parse_stream_connect_value( + line.split("=", 1)[1].strip())) + elif line.startswith("sp="): + cfg.sps.append(_parse_sp_value(line.split("=", 1)[1].strip())) + + elif section == "clock": + # Accumulate key-value pairs for this clock block + if "=" in line: + k, v = line.split("=", 1) + pending_clock[k.strip().lower()] = v.strip() + else: + raise ValueError(f"Invalid line in [clock] section: '{line}'") + + elif section == "network": + # Parse eth_=<0|1> (nonzero means enabled) + if "=" not in line: + raise ValueError( + f"Invalid line in [network] section: '{line}'") + k, v = [t.strip() for t in line.split("=", 1)] + m = _RE_ETH_KEY.match(k) + if not m: + # ignore unknown keys in [network] to be lenient + continue + idx = int(m.group(1)) + try: + val = int(v, 0) + except ValueError: + val = 0 + if val != 0: + enabled_eth.add(idx) + + elif section == "user_region": + if "=" not in line: + raise ValueError( + f"Invalid line in [user_region] section: '{line}'") + k, v = [t.strip() for t in line.split("=", 1)] + if k.lower() == "pre_synth": + if not v: + raise ValueError( + "Invalid line in [user_region] section: empty pre_synth path") + tcl_path = Path(v).expanduser() + if not tcl_path.is_absolute(): + tcl_path = path.parent / tcl_path + pre_synth_tcls.append(str(tcl_path.resolve())) + else: + # ignore unknown keys in [user_region] to be lenient + continue + + elif section == "debug": + if "=" not in line: + raise ValueError(f"Invalid line in [debug] section: '{line}'") + k, v = [t.strip() for t in line.split("=", 1)] + if k.lower() != "net": + raise ValueError( + f"Invalid key '{k}' in [debug] section. Only 'net=.' is supported." + ) + debug_nets.append(_parse_debug_net_value(v)) + + else: + pass + + # End of file: commit any trailing clock block + _commit_clock() + + # Attach network spec + cfg.net = NetworkSpec(enabled_eth=enabled_eth) + cfg.user_region = UserRegionSpec(pre_synth_tcls=pre_synth_tcls) + cfg.debug = DebugSpec(nets=debug_nets) + + return cfg + + +def _resolve_port_name_for_kernel(kernel: Kernel, requested: str) -> str: + # Case-insensitive resolution to the canonical name from component.xml + if requested in kernel.ports: + return requested + low_map = {n.lower(): n for n in kernel.ports.keys()} + req = requested.lower() + if req in low_map: + return low_map[req] + raise KeyError( + f"Port '{requested}' not found on kernel '{kernel.name}'. " + f"Available: {list(kernel.ports.keys())}" + ) + + +def apply_config_to_instances( + cfg: ConnectivityConfig, + kernel_library: List[Kernel], + *, + default_ddr_index: int = 0 # DDR0 fallback for missing AXI4FULL ports +) -> List[KernelInstance]: + instances: Dict[str, KernelInstance] = {} + kernel_library = {kernel.name: kernel for kernel in kernel_library} + + # 1) Instantiate from nk + for nk in cfg.nk: + if nk.kernel_type not in kernel_library: + raise KeyError( + f"Kernel type '{nk.kernel_type}' not found in kernel_library.") + k = kernel_library[nk.kernel_type] + for name in nk.instance_names: + if name in instances: + raise ValueError(f"Duplicate instance name '{name}'.") + instances[name] = KernelInstance(name=name, kernel=k) + + # 2) Attach clock frequencies + for c in cfg.clocks: + if c.inst not in instances: + raise KeyError(f"[clock] refers to unknown instance '{c.inst}'.") + instances[c.inst].params["clock_hz"] = c.freq_hz + + # 3) Apply explicit sp mappings (store with CANONICAL port names) + for sp in cfg.sps: + if sp.inst not in instances: + raise KeyError( + f"[connectivity] sp refers to unknown instance '{sp.inst}'.") + inst = instances[sp.inst] + canon_port = _resolve_port_name_for_kernel(inst.kernel, sp.port) + if inst.kernel.port(canon_port).ptype != BusType.AXI4FULL: + raise ValueError( + f"[connectivity] sp '{sp.inst}.{sp.port}' is not an AXI4FULL port on kernel '{inst.kernel.name}'." + ) + mem_map: Dict[str, dict] = inst.params.setdefault("mem_sp", {}) + mem_map[canon_port] = { + "domain": sp.target.domain, "index": sp.target.index} + + # 4) Per-instance fallback: fill ONLY the missing AXI4FULL ports with MEM (round-robin later) + for inst in instances.values(): + mem_map: Dict[str, dict] = inst.params.setdefault("mem_sp", {}) + axi_full_ports = [ + p.name for p in inst.kernel.ports_of_type(BusType.AXI4FULL)] + for pname in axi_full_ports: + if pname not in mem_map: + mem_map[pname] = {"domain": "MEM", "index": ""} + + return list(instances.values()) diff --git a/linker/slashkit/resources/.gitignore b/linker/slashkit/resources/.gitignore new file mode 100644 index 00000000..786f2110 --- /dev/null +++ b/linker/slashkit/resources/.gitignore @@ -0,0 +1 @@ +static_shell diff --git a/linker/slashkit/resources/__init__.py b/linker/slashkit/resources/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/aved/__init__.py b/linker/slashkit/resources/aved/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/aved/amd_v80_gen5x8_25.1.xsa b/linker/slashkit/resources/aved/amd_v80_gen5x8_25.1.xsa new file mode 100644 index 00000000..54af6ea8 Binary files /dev/null and b/linker/slashkit/resources/aved/amd_v80_gen5x8_25.1.xsa differ diff --git a/linker/slashkit/resources/aved/build_all.sh b/linker/slashkit/resources/aved/build_all.sh new file mode 100755 index 00000000..d7b8ef4c --- /dev/null +++ b/linker/slashkit/resources/aved/build_all.sh @@ -0,0 +1,55 @@ +#!/usr/bin/env bash +# Copyright (c) 2024 - 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set -Eeuo pipefail + +# Init +DESIGN="amd_v80_gen5x8_25.1" +HW_DIR=$(realpath ./) +FW_DIR=$(realpath ./../../fw/AMC) +XSA=${XSA:-$(realpath ${HW_DIR})/build/${DESIGN}.xsa} + +# Step FW +# Exempt zero-length-bounds from -Werror (submodule MCTP code uses +# zero-length arrays as flexible-array-member idiom inside a union). +export CFLAGS="${CFLAGS:-} -Wno-error=zero-length-bounds" + +pushd ${FW_DIR} + ./scripts/build.sh -os freertos10_xilinx -profile v80 -xsa $XSA + cp -a ${FW_DIR}/build/amc.elf ${HW_DIR}/build + # Takes in fpt.json and produces fpt.bin +popd + +# Step FPT +pushd ${FW_DIR}/build + ../scripts/gen_fpt.py -f ../scripts/fpt.json + cp -a ${FW_DIR}/build/fpt.bin ${HW_DIR}/build +popd + +# Step PDI combine +# Generate PDI w/ bootgen +pushd ${HW_DIR} + bootgen -arch versal -image ${HW_DIR}/fpt/pdi_combine.bif -w -o ${HW_DIR}/build/${DESIGN}_nofpt.pdi +popd + +# final pdi generation +${HW_DIR}/fpt/fpt_pdi_gen.py --fpt ${HW_DIR}/build/fpt.bin --pdi ${HW_DIR}/build/${DESIGN}_nofpt.pdi --output ${DESIGN}.pdi + diff --git a/linker/slashkit/resources/aved/pdi_combine.bif b/linker/slashkit/resources/aved/pdi_combine.bif new file mode 100755 index 00000000..02a449d9 --- /dev/null +++ b/linker/slashkit/resources/aved/pdi_combine.bif @@ -0,0 +1,14 @@ +/****************************************************************************** +* Copyright (C) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +all: +{ + image { + { type=bootimage, file=./build/top_wrapper.pdi } + } + image { + id = 0x1c000000, name=rpu_subsystem, delay_handoff + { core=r5-0, file=./build/amc.elf } + } +} diff --git a/linker/slashkit/resources/aved/profile_hal.h b/linker/slashkit/resources/aved/profile_hal.h new file mode 100644 index 00000000..4597df28 --- /dev/null +++ b/linker/slashkit/resources/aved/profile_hal.h @@ -0,0 +1,191 @@ +/** + * Copyright (c) 2023 - 2025 Advanced Micro Devices, Inc. All rights reserved. + * SPDX-License-Identifier: MIT + * + * This file contains the hal profile for the V80 + * + * @file profile_hal.h + * + */ + +#ifndef _PROFILE_HAL_H_ +#define _PROFILE_HAL_H_ + +#include "eeprom.h" +#include "xparameters.h" +#include "xil_io.h" +#include "xil_cache.h" +#include "xsdps.h" + +#define HAL_UUID_SIZE ( 16 ) +#define HAL_EMMC_FEATURE ( 1 ) +#define HAL_EMMC_BASE_ADDR ( XPAR_XSDPS_0_BASEADDR ) +#define HAL_EMMC_BLOCK_SIZE ( 512 ) +#define HAL_EMMC_MAX_BLOCKS ( 0x7690000 ) /* 64 GBytes / 512 Bytes */ + +#define HAL_SMBUS_BASE_ADDR ( XPAR_SMBUS_0_BASEADDR ) +#define HAL_SMBUS_ADDR ( 0x18 ) +#define HAL_SMBUS_INTERRUPT ( 85U + 32U) /* pl.dtsi base_logic_axi_smbus_rpu: smbus@80044000 { interrupts = < 0 85 4 > */ + +#define HAL_EEPROM_VERSION ( EEPROM_VERSION_4_0 ) +#define HAL_EEPROM_I2C_BUS ( 0 ) +#define HAL_EEPROM_SLAVE_ADDRESS ( 0x52 ) +#define HAL_EEPROM_ADDRESS_SIZE ( 1 ) +#define HAL_EEPROM_PAGE_SIZE ( 16 ) +#define HAL_EEPROM_NUM_PAGES ( 16 ) +#define HAL_EEPROM_DEVICE_ID ( 0x0A01 ) +#define HAL_EEPROM_DEVICE_ID_ADDRESS ( 0x1A ) +#define HAL_EEPROM_DEVICE_ID_REGISTER ( 0x07 ) + +#define HAL_AMC_CLOCK_CONTROL ( 1 ) +#if ( 0 != HAL_AMC_CLOCK_CONTROL ) +#ifdef XPAR_SHELL_UTILS_UCC_0_BASEADDR +#define HAL_USER_CLOCK_CONTROL_BASE_ADDRESS ( XPAR_SHELL_UTILS_UCC_0_BASEADDR ) +#else +#define HAL_USER_CLOCK_CONTROL_BASE_ADDRESS ( 0x1 ) +#endif +#endif + +/* Apps */ +/* AMC */ +#define HAL_PARTITION_TABLE_SIZE ( 0x1000 ) +#define HAL_PARTITION_TABLE_MAGIC_NO ( 0x564D5230 ) +#define HAL_ENABLE_AMI_COMMS ( 0x1 ) +#define HAL_RPU_RING_BUFFER_LEN ( 0x1000 ) +#define HAL_RPU_SHARED_MEMORY_BASE_ADDR ( 0x38000000 ) +#define HAL_RPU_SHARED_MEMORY_END_ADDR ( 0x3FFFF000 ) +#define HAL_RPU_SHARED_MEMORY_SIZE ( HAL_RPU_SHARED_MEMORY_END_ADDR - HAL_RPU_SHARED_MEMORY_BASE_ADDR ) +#define HAL_RPU_RING_BUFFER_BASE ( HAL_RPU_SHARED_MEMORY_BASE_ADDR + HAL_PARTITION_TABLE_SIZE ) +#define HAL_BASE_LOGIC_GCQ_M2R_S01_AXI_BASEADDR ( XPAR_STATIC_REGION_AVED_BASE_LOGIC_GCQ_M2R_BASEADDR ) + +#define HAL_FLUSH_CACHE_DATA( addr, size ) Xil_DCacheFlushRange( addr, size ) + +/* Definitions for peripheral CIPS_PSPMC_0_PSV_I2C_0 */ +#define HAL_I2C_BUS_0_DEVICE_ID ( 0 ) +#define HAL_I2C_BUS_0_BASEADDR ( XPAR_XIICPS_0_BASEADDR ) +#define HAL_I2C_BUS_0_HIGHADDR ( XPAR_XIICPS_0_HIGHADDR ) +#define HAL_I2C_BUS_0_I2C_CLK_FREQ_HZ ( UTIL_100KHZ ) +#define HAL_I2C_BUS_0_RESET_ON_INIT ( TRUE ) +#define HAL_I2C_BUS_0_HW_DEVICE_RESET ( FALSE ) + +/* Definitions for peripheral CIPS_PSPMC_0_PSV_I2C_1 */ +#define HAL_I2C_BUS_1_DEVICE_ID ( 1 ) +#define HAL_I2C_BUS_1_BASEADDR ( XPAR_XIICPS_1_BASEADDR ) +#define HAL_I2C_BUS_1_HIGHADDR ( XPAR_XIICPS_1_BASEADDR ) +#define HAL_I2C_BUS_1_I2C_CLK_FREQ_HZ ( UTIL_100KHZ ) +#define HAL_I2C_BUS_1_RESET_ON_INIT ( FALSE ) +#define HAL_I2C_BUS_1_HW_DEVICE_RESET ( TRUE ) + +#define HAL_I2C_SW_RESET_BASEADDR ( XPAR_PSV_CRL_0_BASEADDR ) +#define HAL_I2C_BUS_0_SW_RESET_OFFSET ( 0x330 ) +#define HAL_I2C_BUS_1_SW_RESET_OFFSET ( 0x334 ) +#define HAL_I2C_BUS_0_HW_RESET_ADDR ( 0 ) +#define HAL_I2C_BUS_0_HW_RESET_MASK ( 0 ) +#define HAL_I2C_BUS_1_HW_RESET_ADDR ( 0xFF0B0040 ) +#define HAL_I2C_BUS_1_HW_RESET_MASK ( 1 << 13 ) + + +#define HAL_I2C_DEFAULT_SCLK_RATE ( 33333333 ) +#define HAL_I2C_RETRY_COUNT ( 5 ) + +/* Definitions OSPI */ +#define HAL_OSPI_0_DEVICE_ID ( XPAR_OSPI_BASEADDR ) +#define HAL_PSV_PMC_GLOBAL_0_AXI_BASEADDR ( XPAR_PSV_PMC_GLOBAL_0_BASEADDR ) + +/* FAL */ +/* GCQ */ +#ifndef HAL_IO_WRITE32 +#define HAL_IO_WRITE32( val, addr ) ( { Xil_Out32( addr, val ); \ + Xil_DCacheFlushRange( addr, sizeof( uint32_t ) ); } ) +#endif + +#ifndef HAL_IO_WRITE32_NO_FLUSH +#define HAL_IO_WRITE32_NO_FLUSH( val, addr ) ( { Xil_Out32( addr, val ); } ) +#endif + +#ifndef HAL_IO_READ32 +#define HAL_IO_READ32( addr ) ( { Xil_DCacheFlushRange( addr, sizeof( uint32_t ) ); \ + Xil_In32( addr ); } ) +#endif + +#ifndef HAL_IO_READ32_NO_FLUSH +#define HAL_IO_READ32_NO_FLUSH( addr ) ( { Xil_In32( addr ); } ) +#endif + +/* Proxies */ +/* APC */ +#define HAL_APC_PMC_BOOT_REG ( XPAR_PSV_PMC_GLOBAL_0_BASEADDR + 0x00004 ) +#define HAL_APC_PMC_SRST_REG ( XPAR_PSV_PMC_GLOBAL_0_BASEADDR + 0x20084 ) +#define HAL_APC_PDI_BIT_MASK ( 0x14 ) + +/* Core libs */ +/* PLL */ +#define HAL_FSBL_LOG_ADDRESS ( 0xF2019000 ) +#define HAL_FSBL_LOG_SIZE ( 0x4000 ) + +/** + * @struct HAL_PARTITION_TABLE_RING_BUFFER + * + * @brief Stores the ring buffer info - part of the partition table. + */ +typedef struct HAL_PARTITION_TABLE_RING_BUFFER +{ + uint32_t ulRingBufferOff; + uint32_t ulRingBufferLen; + +} HAL_PARTITION_TABLE_RING_BUFFER; + +/** + * @struct HAL_PARTITION_TABLE_STATUS + * + * @brief Stores the AMC status info - part of the partition table. + */ +typedef struct HAL_PARTITION_TABLE_STATUS +{ + uint32_t ulStatusOff; + uint32_t ulStatusLen; + +} HAL_PARTITION_TABLE_STATUS; + +/** + * @struct HAL_PARTITION_TABLE_LOG_MSG + * + * @brief Stores the AMC logs and info - part of the partition table. + */ +typedef struct HAL_PARTITION_TABLE_LOG_MSG +{ + uint32_t ulLogMsgIndex; + uint32_t ulLogMsgBufferOff; + uint32_t ulLogMsgBufferLen; + +} HAL_PARTITION_TABLE_LOG_MSG; + +/** + * @struct HAL_PARTITION_TABLE_DATA + * + * @brief Stores the AMC data - part of the partition table. + */ +typedef struct HAL_PARTITION_TABLE_DATA +{ + uint32_t ulDataStart; + uint32_t ulDataEnd; + +} HAL_PARTITION_TABLE_DATA; + +/** + * @struct HAL_PARTITION_TABLE + * + * @brief Table stored at the top of the shared memory and used by + * AMI to read offsets & state. + */ +typedef struct HAL_PARTITION_TABLE +{ + uint32_t ulMagicNum; + HAL_PARTITION_TABLE_RING_BUFFER xRingBuffer; + HAL_PARTITION_TABLE_STATUS xStatus; + HAL_PARTITION_TABLE_LOG_MSG xLogMsg; + HAL_PARTITION_TABLE_DATA xData; + +} HAL_PARTITION_TABLE; + +#endif diff --git a/linker/slashkit/resources/base/__init__.py b/linker/slashkit/resources/base/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/base/constraints/__init__.py b/linker/slashkit/resources/base/constraints/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/base/constraints/impl.pins.xdc b/linker/slashkit/resources/base/constraints/impl.pins.xdc new file mode 100644 index 00000000..cf1e3daf --- /dev/null +++ b/linker/slashkit/resources/base/constraints/impl.pins.xdc @@ -0,0 +1,364 @@ +# (c) Copyright 2024, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# xcv80-lsva4737-2MHP-e-S pins constraints XDC + +set_property -dict { PACKAGE_PIN BR15 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_act_n[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_ACT_B - IO_L18N_XCC_N6P1_M0P37_700 +set_property -dict { PACKAGE_PIN BP15 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A0 - IO_L18P_XCC_N6P0_M0P36_700 +set_property -dict { PACKAGE_PIN BU8 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[1]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A1 - IO_L17N_N5P5_M0P35_700 +set_property -dict { PACKAGE_PIN BT9 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[2]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A2 - IO_L17P_N5P4_M0P34_700 +set_property -dict { PACKAGE_PIN BR14 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[3]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A3 - IO_L20P_N6P4_M0P40_700 +set_property -dict { PACKAGE_PIN BN10 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[4]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A4 - IO_L12P_GC_XCC_N4P0_M0P24_700 +set_property -dict { PACKAGE_PIN BT6 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[5]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A5 - IO_L26P_N8P4_M0P52_700 +set_property -dict { PACKAGE_PIN BR8 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[6]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A6 - IO_L24P_GC_XCC_N8P0_M0P48_700 +set_property -dict { PACKAGE_PIN BP7 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[7]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A7 - IO_L6N_GC_XCC_N2P1_M0P13_700 +set_property -dict { PACKAGE_PIN BR6 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[8]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A8 - IO_L25N_N8P3_M0P51_700 +set_property -dict { PACKAGE_PIN BN14 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[9]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A9 - IO_L19P_N6P2_M0P38_700 +set_property -dict { PACKAGE_PIN BR12 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[10]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A10 - IO_L21N_XCC_N7P1_M0P43_700 +set_property -dict { PACKAGE_PIN BR7 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[11]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A11 - IO_L25P_N8P2_M0P50_700 +set_property -dict { PACKAGE_PIN BN2 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[12]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A12 - IO_L0N_XCC_N0P1_M0P1_700 +set_property -dict { PACKAGE_PIN BT8 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[13]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_A13 - IO_L24N_GC_XCC_N8P1_M0P49_700 +set_property -dict { PACKAGE_PIN BU10 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[14]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_WE_B - IO_L16N_N5P3_M0P33_700 +set_property -dict { PACKAGE_PIN BR9 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[15]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_CAS_B - IO_L14N_N4P5_M0P29_700 +set_property -dict { PACKAGE_PIN BN13 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_adr[16]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_RAS_B - IO_L19N_N6P3_M0P39_700 +set_property -dict { PACKAGE_PIN BP13 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_ba[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_BA0 - IO_L20N_N6P5_M0P41_700 +set_property -dict { PACKAGE_PIN BN9 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_ba[1]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_BA1 - IO_L12N_GC_XCC_N4P1_M0P25_700 +set_property -dict { PACKAGE_PIN BT13 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_bg[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_BG0 - IO_L21P_XCC_N7P0_M0P42_700 +set_property -dict { PACKAGE_PIN BT11 IOSTANDARD DIFF_SSTL12 } [get_ports "CH0_DDR4_0_0_ck_t[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_CK_T0 - IO_L15P_XCC_N5P0_M0P30_700 +set_property -dict { PACKAGE_PIN BN12 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_cke[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_CKE0 - IO_L23P_N7P4_M0P46_700 +set_property -dict { PACKAGE_PIN BP10 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_cs_n[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_CS_B0 - IO_L14P_N4P4_M0P28_700 +set_property -dict { PACKAGE_PIN BY13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[0]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B0 - IO_L18P_XCC_N6P0_M0P90_701 +set_property -dict { PACKAGE_PIN BU13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[1]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B1 - IO_L12P_GC_XCC_N4P0_M0P78_701 +set_property -dict { PACKAGE_PIN CC7 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[2]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B2 - IO_L6P_GC_XCC_N2P0_M0P120_702 +set_property -dict { PACKAGE_PIN CD9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[3]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B3 - IO_L12P_GC_XCC_N4P0_M0P132_702 +set_property -dict { PACKAGE_PIN CA4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[4]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B4 - IO_L9P_GC_XCC_N3P0_M0P72_701 +set_property -dict { PACKAGE_PIN BV5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[5]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B5 - IO_L0P_XCC_N0P0_M0P54_701 +set_property -dict { PACKAGE_PIN CE2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[6]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B6 - IO_L3P_XCC_N1P0_M0P114_702 +set_property -dict { PACKAGE_PIN BN3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[7]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B7 - IO_L0P_XCC_N0P0_M0P0_700 +set_property -dict { PACKAGE_PIN BN7 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dm_n[8]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DM_B8 - IO_L6P_GC_XCC_N2P0_M0P12_700 +set_property -dict { PACKAGE_PIN BY12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[0]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ0 - IO_L19N_N6P3_M0P93_701 +set_property -dict { PACKAGE_PIN CA11 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[1]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ1 - IO_L22P_N7P2_M0P98_701 +set_property -dict { PACKAGE_PIN CA10 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[2]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ2 - IO_L22N_N7P3_M0P99_701 +set_property -dict { PACKAGE_PIN CB12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[3]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ3 - IO_L20N_N6P5_M0P95_701 +set_property -dict { PACKAGE_PIN CB8 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[4]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ4 - IO_L23N_N7P5_M0P101_701 +set_property -dict { PACKAGE_PIN CA13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[5]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ5 - IO_L19P_N6P2_M0P92_701 +set_property -dict { PACKAGE_PIN CA9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[6]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ6 - IO_L23P_N7P4_M0P100_701 +set_property -dict { PACKAGE_PIN CB13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[7]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ7 - IO_L20P_N6P4_M0P94_701 +set_property -dict { PACKAGE_PIN BV8 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[8]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ8 - IO_L17P_N5P4_M0P88_701 +set_property -dict { PACKAGE_PIN BV9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[9]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ9 - IO_L16P_N5P2_M0P86_701 +set_property -dict { PACKAGE_PIN BV12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[10]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ10 - IO_L13N_N4P3_M0P81_701 +set_property -dict { PACKAGE_PIN BW9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[11]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ11 - IO_L16N_N5P3_M0P87_701 +set_property -dict { PACKAGE_PIN BV7 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[12]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ12 - IO_L17N_N5P5_M0P89_701 +set_property -dict { PACKAGE_PIN BV10 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[13]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ13 - IO_L14N_N4P5_M0P83_701 +set_property -dict { PACKAGE_PIN BV13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[14]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ14 - IO_L13P_N4P2_M0P80_701 +set_property -dict { PACKAGE_PIN BW11 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[15]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ15 - IO_L14P_N4P4_M0P82_701 +set_property -dict { PACKAGE_PIN CD5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[16]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ16 - IO_L10P_N3P2_M0P128_702 +set_property -dict { PACKAGE_PIN CF4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[17]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ17 - IO_L8N_N2P5_M0P125_702 +set_property -dict { PACKAGE_PIN CD4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[18]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ18 - IO_L10N_N3P3_M0P129_702 +set_property -dict { PACKAGE_PIN CF5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[19]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ19 - IO_L7N_N2P3_M0P123_702 +set_property -dict { PACKAGE_PIN CC4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[20]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ20 - IO_L11N_N3P5_M0P131_702 +set_property -dict { PACKAGE_PIN CG5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[21]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ21 - IO_L8P_N2P4_M0P124_702 +set_property -dict { PACKAGE_PIN CC5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[22]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ22 - IO_L11P_N3P4_M0P130_702 +set_property -dict { PACKAGE_PIN CE6 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[23]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ23 - IO_L7P_N2P2_M0P122_702 +set_property -dict { PACKAGE_PIN CJ9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[24]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ24 - IO_L16P_N5P2_M0P140_702 +set_property -dict { PACKAGE_PIN CJ6 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[25]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ25 - IO_L17N_N5P5_M0P143_702 +set_property -dict { PACKAGE_PIN CF9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[26]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ26 - IO_L14P_N4P4_M0P136_702 +set_property -dict { PACKAGE_PIN CJ7 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[27]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ27 - IO_L17P_N5P4_M0P142_702 +set_property -dict { PACKAGE_PIN CE8 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[28]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ28 - IO_L13N_N4P3_M0P135_702 +set_property -dict { PACKAGE_PIN CH8 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[29]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ29 - IO_L16N_N5P3_M0P141_702 +set_property -dict { PACKAGE_PIN CE9 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[30]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ30 - IO_L13P_N4P2_M0P134_702 +set_property -dict { PACKAGE_PIN CF8 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[31]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ31 - IO_L14N_N4P5_M0P137_702 +set_property -dict { PACKAGE_PIN CB2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[32]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ32 - IO_L10N_N3P3_M0P75_701 +set_property -dict { PACKAGE_PIN CA5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[33]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ33 - IO_L7N_N2P3_M0P69_701 +set_property -dict { PACKAGE_PIN CB3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[34]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ34 - IO_L10P_N3P2_M0P74_701 +set_property -dict { PACKAGE_PIN CB5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[35]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ35 - IO_L8N_N2P5_M0P71_701 +set_property -dict { PACKAGE_PIN CA1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[36]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ36 - IO_L11P_N3P4_M0P76_701 +set_property -dict { PACKAGE_PIN BY6 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[37]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ37 - IO_L7P_N2P2_M0P68_701 +set_property -dict { PACKAGE_PIN CB1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[38]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ38 - IO_L11N_N3P5_M0P77_701 +set_property -dict { PACKAGE_PIN CA6 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[39]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ39 - IO_L8P_N2P4_M0P70_701 +set_property -dict { PACKAGE_PIN BV2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[40]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ40 - IO_L5N_N1P5_M0P65_701 +set_property -dict { PACKAGE_PIN BY3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[41]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ41 - IO_L2N_N0P5_M0P59_701 +set_property -dict { PACKAGE_PIN BW1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[42]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ42 - IO_L4N_N1P3_M0P63_701 +set_property -dict { PACKAGE_PIN BW4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[43]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ43 - IO_L1N_N0P3_M0P57_701 +set_property -dict { PACKAGE_PIN BV3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[44]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ44 - IO_L5P_N1P4_M0P64_701 +set_property -dict { PACKAGE_PIN BY4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[45]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ45 - IO_L2P_N0P4_M0P58_701 +set_property -dict { PACKAGE_PIN BW2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[46]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ46 - IO_L4P_N1P2_M0P62_701 +set_property -dict { PACKAGE_PIN BW5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[47]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ47 - IO_L1P_N0P2_M0P56_701 +set_property -dict { PACKAGE_PIN CD2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[48]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ48 - IO_L1P_N0P2_M0P110_702 +set_property -dict { PACKAGE_PIN CF3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[49]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ49 - IO_L4P_N1P2_M0P116_702 +set_property -dict { PACKAGE_PIN CD1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[50]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ50 - IO_L1N_N0P3_M0P111_702 +set_property -dict { PACKAGE_PIN CF2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[51]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ51 - IO_L4N_N1P3_M0P117_702 +set_property -dict { PACKAGE_PIN CE3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[52]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ52 - IO_L2N_N0P5_M0P113_702 +set_property -dict { PACKAGE_PIN CG3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[53]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ53 - IO_L5N_N1P5_M0P119_702 +set_property -dict { PACKAGE_PIN CE4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[54]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ54 - IO_L2P_N0P4_M0P112_702 +set_property -dict { PACKAGE_PIN CH4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[55]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ55 - IO_L5P_N1P4_M0P118_702 +set_property -dict { PACKAGE_PIN BP2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[56]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ56 - IO_L1P_N0P2_M0P2_700 +set_property -dict { PACKAGE_PIN BU2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[57]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ57 - IO_L4N_N1P3_M0P9_700 +set_property -dict { PACKAGE_PIN BR2 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[58]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ58 - IO_L2P_N0P4_M0P4_700 +set_property -dict { PACKAGE_PIN BT1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[59]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ59 - IO_L5P_N1P4_M0P10_700 +set_property -dict { PACKAGE_PIN BP1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[60]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ60 - IO_L1N_N0P3_M0P3_700 +set_property -dict { PACKAGE_PIN BU1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[61]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ61 - IO_L5N_N1P5_M0P11_700 +set_property -dict { PACKAGE_PIN BR1 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[62]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ62 - IO_L2N_N0P5_M0P5_700 +set_property -dict { PACKAGE_PIN BU3 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[63]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ63 - IO_L4P_N1P2_M0P8_700 +set_property -dict { PACKAGE_PIN BN5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[64]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ64 - IO_L8P_N2P4_M0P16_700 +set_property -dict { PACKAGE_PIN BP5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[65]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ65 - IO_L7N_N2P3_M0P15_700 +set_property -dict { PACKAGE_PIN BP6 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[66]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ66 - IO_L7P_N2P2_M0P14_700 +set_property -dict { PACKAGE_PIN BP4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[67]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ67 - IO_L11P_N3P4_M0P22_700 +set_property -dict { PACKAGE_PIN BT4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[68]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ68 - IO_L10N_N3P3_M0P21_700 +set_property -dict { PACKAGE_PIN BN4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[69]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ69 - IO_L8N_N2P5_M0P17_700 +set_property -dict { PACKAGE_PIN BU5 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[70]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ70 - IO_L10P_N3P2_M0P20_700 +set_property -dict { PACKAGE_PIN BR4 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_0_dq[71]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQ71 - IO_L11N_N3P5_M0P23_700 +set_property -dict { PACKAGE_PIN CB11 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[0]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T0 - IO_L21P_XCC_N7P0_M0P96_701 +set_property -dict { PACKAGE_PIN BY11 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[1]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T1 - IO_L15P_XCC_N5P0_M0P84_701 +set_property -dict { PACKAGE_PIN CH5 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[2]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T2 - IO_L9P_GC_XCC_N3P0_M0P126_702 +set_property -dict { PACKAGE_PIN CH9 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[3]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T3 - IO_L15P_XCC_N5P0_M0P138_702 +set_property -dict { PACKAGE_PIN CB7 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[4]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T4 - IO_L6P_GC_XCC_N2P0_M0P66_701 +set_property -dict { PACKAGE_PIN BY2 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[5]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T5 - IO_L3P_XCC_N1P0_M0P60_701 +set_property -dict { PACKAGE_PIN CC3 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[6]"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T6 - IO_L0P_XCC_N0P0_M0P108_702 +set_property -dict { PACKAGE_PIN BR3 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[7]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T7 - IO_L3P_XCC_N1P0_M0P6_700 +set_property -dict { PACKAGE_PIN BU7 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_0_dqs_t[8]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_DQS_T8 - IO_L9P_GC_XCC_N3P0_M0P18_700 +set_property -dict { PACKAGE_PIN BP11 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_0_odt[0]"] ;# Bank 700 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_ODT0 - IO_L23N_N7P5_M0P47_700 +set_property -dict { PACKAGE_PIN BW7 IOSTANDARD LVCMOS12 } [get_ports "CH0_DDR4_0_0_reset_n[0]"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 -Net CH0_DDR4_0_0_RESET_B - IO_L25P_N8P2_M0P104_701 + +set_property -dict { PACKAGE_PIN CG22 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_act_n[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_ACT_B0 - IO_L9N_GC_XCC_N3P1_M1P73_704 +set_property -dict { PACKAGE_PIN CH20 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A0 - IO_L3P_XCC_N1P0_M1P60_704 +set_property -dict { PACKAGE_PIN CG23 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[1]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A1 - IO_L8N_N2P5_M1P71_704 +set_property -dict { PACKAGE_PIN CH23 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[2]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A2 - IO_L11P_N3P4_M1P76_704 +set_property -dict { PACKAGE_PIN BV20 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[3]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A3 - IO_L14N_N4P5_M1P83_704 +set_property -dict { PACKAGE_PIN BU19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[4]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A4 - IO_L14P_N4P4_M1P82_704 +set_property -dict { PACKAGE_PIN CB18 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[5]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A5 - IO_L17P_N5P4_M1P88_704 +set_property -dict { PACKAGE_PIN CC18 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[6]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A6 - IO_L17N_N5P5_M1P89_704 +set_property -dict { PACKAGE_PIN CC19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[7]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A7 - IO_L24P_GC_XCC_N8P0_M1P102_704 +set_property -dict { PACKAGE_PIN CH18 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[8]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A8 - IO_L5N_N1P5_M1P65_704 +set_property -dict { PACKAGE_PIN CF23 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[9]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A9 - IO_L8P_N2P4_M1P70_704 +set_property -dict { PACKAGE_PIN CD20 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[10]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A10 - IO_L25N_N8P3_M1P105_704 +set_property -dict { PACKAGE_PIN BV18 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[11]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A11 - IO_L13N_N4P3_M1P81_704 +set_property -dict { PACKAGE_PIN CD21 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[12]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A12 - IO_L26P_N8P4_M1P106_704 +set_property -dict { PACKAGE_PIN CE19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[13]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A13 - IO_L1P_N0P2_M1P56_704 +set_property -dict { PACKAGE_PIN BY19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[14]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A14 - IO_L15N_XCC_N5P1_M1P85_704 +set_property -dict { PACKAGE_PIN BT19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[15]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A15 - IO_L12P_GC_XCC_N4P0_M1P78_704 +set_property -dict { PACKAGE_PIN CJ19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[16]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A16 - IO_L4N_N1P3_M1P63_704 +set_property -dict { PACKAGE_PIN CG18 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_adr[17]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_A17 - IO_L5P_N1P4_M1P64_704 +set_property -dict { PACKAGE_PIN CD15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_alert_n[0]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_ALERT_B - IO_L25N_N8P3_M1P51_703 +set_property -dict { PACKAGE_PIN CD19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_ba[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_BA0 - IO_L24N_GC_XCC_N8P1_M1P103_704 +set_property -dict { PACKAGE_PIN CF19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_ba[1]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_BA1 - IO_L1N_N0P3_M1P57_704 +set_property -dict { PACKAGE_PIN CE21 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_bg[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_BG0 - IO_L26N_N8P5_M1P107_704 +set_property -dict { PACKAGE_PIN CG21 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_bg[1]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_BG1 - IO_L9P_GC_XCC_N3P0_M1P72_704 +set_property -dict { PACKAGE_PIN CF21 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_ck_t[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_CK_T0 - IO_L7N_N2P3_M1P69_704 +set_property -dict { PACKAGE_PIN CE22 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_ck_c[0]"] ;# TODO why standard not diff ? # Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_CK_C0 - IO_L7P_N2P2_M1P68_704 +set_property -dict { PACKAGE_PIN CJ22 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_cke[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_CKE0 - IO_L11N_N3P5_M1P77_704 +set_property -dict { PACKAGE_PIN CH19 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_cs_n[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_CS_B0 - IO_L4P_N1P2_M1P62_704 +set_property -dict { PACKAGE_PIN BV17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[0]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ0 - IO_L20N_N6P5_M1P41_703 +set_property -dict { PACKAGE_PIN BT17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[1]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ1 - IO_L19N_N6P3_M1P39_703 +set_property -dict { PACKAGE_PIN BT16 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[2]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ2 - IO_L19P_N6P2_M1P38_703 +set_property -dict { PACKAGE_PIN BU16 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[3]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ3 - IO_L20P_N6P4_M1P40_703 +set_property -dict { PACKAGE_PIN BV15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[4]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ4 - IO_L22P_N7P2_M1P44_703 +set_property -dict { PACKAGE_PIN BW15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[5]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ5 - IO_L22N_N7P3_M1P45_703 +set_property -dict { PACKAGE_PIN BW14 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[6]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ6 - IO_L23N_N7P5_M1P47_703 +set_property -dict { PACKAGE_PIN BV14 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[7]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ7 - IO_L23P_N7P4_M1P46_703 +set_property -dict { PACKAGE_PIN BU24 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[8]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ8 - IO_L19P_N6P2_M1P146_705 +set_property -dict { PACKAGE_PIN BU25 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[9]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ9 - IO_L20P_N6P4_M1P148_705 +set_property -dict { PACKAGE_PIN BV24 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[10]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ10 - IO_L19N_N6P3_M1P147_705 +set_property -dict { PACKAGE_PIN BV26 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[11]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ11 - IO_L20N_N6P5_M1P149_705 +set_property -dict { PACKAGE_PIN BV29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[12]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ12 - IO_L22N_N7P3_M1P153_705 +set_property -dict { PACKAGE_PIN BW29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[13]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ13 - IO_L23N_N7P5_M1P155_705 +set_property -dict { PACKAGE_PIN BW28 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[14]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ14 - IO_L23P_N7P4_M1P154_705 +set_property -dict { PACKAGE_PIN BU28 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[15]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ15 - IO_L22P_N7P2_M1P152_705 +set_property -dict { PACKAGE_PIN CF26 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[16]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ16 - IO_L8N_N2P5_M1P125_705 +set_property -dict { PACKAGE_PIN CE26 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[17]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ17 - IO_L8P_N2P4_M1P124_705 +set_property -dict { PACKAGE_PIN CF25 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[18]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ18 - IO_L7N_N2P3_M1P123_705 +set_property -dict { PACKAGE_PIN CE24 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[19]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ19 - IO_L7P_N2P2_M1P122_705 +set_property -dict { PACKAGE_PIN CE29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[20]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ20 - IO_L10P_N3P2_M1P128_705 +set_property -dict { PACKAGE_PIN CF29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[21]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ21 - IO_L10N_N3P3_M1P129_705 +set_property -dict { PACKAGE_PIN CG28 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[22]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ22 - IO_L11P_N3P4_M1P130_705 +set_property -dict { PACKAGE_PIN CH28 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[23]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ23 - IO_L11N_N3P5_M1P131_705 +set_property -dict { PACKAGE_PIN CB23 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[24]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ24 - IO_L14P_N4P4_M1P136_705 +set_property -dict { PACKAGE_PIN BY25 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[25]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ25 - IO_L13P_N4P2_M1P134_705 +set_property -dict { PACKAGE_PIN CC23 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[26]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ26 - IO_L14N_N4P5_M1P137_705 +set_property -dict { PACKAGE_PIN CA26 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[27]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ27 - IO_L13N_N4P3_M1P135_705 +set_property -dict { PACKAGE_PIN CB28 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[28]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ28 - IO_L16N_N5P3_M1P141_705 +set_property -dict { PACKAGE_PIN CA29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[29]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ29 - IO_L16P_N5P2_M1P140_705 +set_property -dict { PACKAGE_PIN CC28 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[30]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ30 - IO_L17P_N5P4_M1P142_705 +set_property -dict { PACKAGE_PIN CC29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[31]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ31 - IO_L17N_N5P5_M1P143_705 +set_property -dict { PACKAGE_PIN CF14 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[32]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ32 - IO_L7N_N2P3_M1P15_703 +set_property -dict { PACKAGE_PIN CF13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[33]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ33 - IO_L7P_N2P2_M1P14_703 +set_property -dict { PACKAGE_PIN CG15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[34]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ34 - IO_L8N_N2P5_M1P17_703 +set_property -dict { PACKAGE_PIN CF15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[35]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ35 - IO_L8P_N2P4_M1P16_703 +set_property -dict { PACKAGE_PIN CG17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[36]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ36 - IO_L11N_N3P5_M1P23_703 +set_property -dict { PACKAGE_PIN CF16 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[37]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ37 - IO_L10N_N3P3_M1P21_703 +set_property -dict { PACKAGE_PIN CE17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[38]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ38 - IO_L10P_N3P2_M1P20_703 +set_property -dict { PACKAGE_PIN CG16 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[39]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ39 - IO_L11P_N3P4_M1P22_703 +set_property -dict { PACKAGE_PIN CJ14 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[40]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ40 - IO_L2N_N0P5_M1P5_703 +set_property -dict { PACKAGE_PIN CH13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[41]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ41 - IO_L2P_N0P4_M1P4_703 +set_property -dict { PACKAGE_PIN CJ12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[42]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ42 - IO_L1N_N0P3_M1P3_703 +set_property -dict { PACKAGE_PIN CH12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[43]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ43 - IO_L1P_N0P2_M1P2_703 +set_property -dict { PACKAGE_PIN CH15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[44]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ44 - IO_L4P_N1P2_M1P8_703 +set_property -dict { PACKAGE_PIN CJ16 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[45]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ45 - IO_L4N_N1P3_M1P9_703 +set_property -dict { PACKAGE_PIN CH17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[46]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ46 - IO_L5P_N1P4_M1P10_703 +set_property -dict { PACKAGE_PIN CJ17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[47]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ47 - IO_L5N_N1P5_M1P11_703 +set_property -dict { PACKAGE_PIN BV21 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[48]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ48 - IO_L19P_N6P2_M1P92_704 +set_property -dict { PACKAGE_PIN BY21 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[49]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ49 - IO_L20N_N6P5_M1P95_704 +set_property -dict { PACKAGE_PIN BW20 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[50]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ50 - IO_L20P_N6P4_M1P94_704 +set_property -dict { PACKAGE_PIN BW22 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[51]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ51 - IO_L19N_N6P3_M1P93_704 +set_property -dict { PACKAGE_PIN CB20 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[52]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ52 - IO_L22N_N7P3_M1P99_704 +set_property -dict { PACKAGE_PIN CA20 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[53]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ53 - IO_L22P_N7P2_M1P98_704 +set_property -dict { PACKAGE_PIN CB21 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[54]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ54 - IO_L23P_N7P4_M1P100_704 +set_property -dict { PACKAGE_PIN CB22 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[55]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ55 - IO_L23N_N7P5_M1P101_704 +set_property -dict { PACKAGE_PIN CH25 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[56]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ56 - IO_L1N_N0P3_M1P111_705 +set_property -dict { PACKAGE_PIN CJ25 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[57]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ57 - IO_L2P_N0P4_M1P112_705 +set_property -dict { PACKAGE_PIN CG25 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[58]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ58 - IO_L1P_N0P2_M1P110_705 +set_property -dict { PACKAGE_PIN CJ26 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[59]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ59 - IO_L2N_N0P5_M1P113_705 +set_property -dict { PACKAGE_PIN CJ29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[60]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ60 - IO_L5N_N1P5_M1P119_705 +set_property -dict { PACKAGE_PIN CH29 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[61]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ61 - IO_L5P_N1P4_M1P118_705 +set_property -dict { PACKAGE_PIN CH27 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[62]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ62 - IO_L4P_N1P2_M1P116_705 +set_property -dict { PACKAGE_PIN CJ27 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[63]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ63 - IO_L4N_N1P3_M1P117_705 +set_property -dict { PACKAGE_PIN CA15 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[64]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ64 - IO_L13N_N4P3_M1P27_703 +set_property -dict { PACKAGE_PIN BY16 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[65]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ65 - IO_L13P_N4P2_M1P26_703 +set_property -dict { PACKAGE_PIN CC17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[66]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ66 - IO_L14P_N4P4_M1P28_703 +set_property -dict { PACKAGE_PIN CD17 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[67]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ67 - IO_L14N_N4P5_M1P29_703 +set_property -dict { PACKAGE_PIN CC14 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[68]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ68 - IO_L16N_N5P3_M1P33_703 +set_property -dict { PACKAGE_PIN CC13 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[69]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ69 - IO_L16P_N5P2_M1P32_703 +set_property -dict { PACKAGE_PIN CD12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[70]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ70 - IO_L17N_N5P5_M1P35_703 +set_property -dict { PACKAGE_PIN CC12 IOSTANDARD POD12 } [get_ports "CH0_DDR4_0_1_dq[71]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQ71 - IO_L17P_N5P4_M1P34_703 +set_property -dict { PACKAGE_PIN BT14 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[0]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T0 - IO_L18P_XCC_N6P0_M1P36_703 +set_property -dict { PACKAGE_PIN BV23 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[1]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T1 - IO_L18P_XCC_N6P0_M1P144_705 +set_property -dict { PACKAGE_PIN CE23 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[2]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T2 - IO_L6P_GC_XCC_N2P0_M1P120_705 +set_property -dict { PACKAGE_PIN BW25 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[3]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T3 - IO_L12P_GC_XCC_N4P0_M1P132_705 +set_property -dict { PACKAGE_PIN CE12 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[4]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T4 - IO_L6P_GC_XCC_N2P0_M1P12_703 +set_property -dict { PACKAGE_PIN CG12 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[5]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T5 - IO_L0P_XCC_N0P0_M1P0_703 +set_property -dict { PACKAGE_PIN BU21 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[6]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T6 - IO_L18P_XCC_N6P0_M1P90_704 +set_property -dict { PACKAGE_PIN CH24 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[7]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T7 - IO_L0P_XCC_N0P0_M1P108_705 +set_property -dict { PACKAGE_PIN BY14 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[8]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T8 - IO_L12P_GC_XCC_N4P0_M1P24_703 +set_property -dict { PACKAGE_PIN BW16 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[9]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T9 - IO_L21P_XCC_N7P0_M1P42_703 +set_property -dict { PACKAGE_PIN BU27 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[10]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T10 - IO_L21P_XCC_N7P0_M1P150_705 +set_property -dict { PACKAGE_PIN CE28 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[11]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T11 - IO_L9P_GC_XCC_N3P0_M1P126_705 +set_property -dict { PACKAGE_PIN CB25 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[12]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T12 - IO_L15P_XCC_N5P0_M1P138_705 +set_property -dict { PACKAGE_PIN CD16 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[13]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T13 - IO_L9P_GC_XCC_N3P0_M1P18_703 +set_property -dict { PACKAGE_PIN CH14 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[14]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T14 - IO_L3P_XCC_N1P0_M1P6_703 +set_property -dict { PACKAGE_PIN BY22 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[15]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T15 - IO_L21P_XCC_N7P0_M1P96_704 +set_property -dict { PACKAGE_PIN CG26 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[16]"] ;# Bank 705 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T16 - IO_L3P_XCC_N1P0_M1P114_705 +set_property -dict { PACKAGE_PIN CA17 IOSTANDARD DIFF_POD12 } [get_ports "CH0_DDR4_0_1_dqs_t[17]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_DQS_T17 - IO_L15P_XCC_N5P0_M1P30_703 +set_property -dict { PACKAGE_PIN BY18 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_odt[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_ODT0 - IO_L16P_N5P2_M1P86_704 +set_property -dict { PACKAGE_PIN CJ20 IOSTANDARD SSTL12 } [get_ports "CH0_DDR4_0_1_par[0]"] ;# Bank 704 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_PAR0 - IO_L3N_XCC_N1P1_M1P61_704 +set_property -dict { PACKAGE_PIN CC15 IOSTANDARD LVCMOS12 } [get_ports "CH0_DDR4_0_1_reset_n[0]"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM -Net CH0_DDR4_0_1_RESET_B - IO_L25P_N8P2_M1P50_703 + +set_property -dict { PACKAGE_PIN BY9 IOSTANDARD LVDS15 } [get_ports "sys_clk0_0_clk_p"] ;# Bank 701 VCCO - VR_1V2_VCCO_DDR4 - IO_L24P_GC_XCC_N8P0_M0P102_701 +set_property -dict { PACKAGE_PIN CB15 IOSTANDARD LVDS15 } [get_ports "sys_clk0_1_clk_p"] ;# Bank 703 VCCO - VR_1V2_VCCO_DIMM - IO_L24P_GC_XCC_N8P0_M1P48_703 + +set_property -dict { PACKAGE_PIN N18 } [get_ports "hbm_ref_clk_0_clk_p"] ;# Bank 800 " C4CCIO_PAD1_0_800 +set_property -dict { PACKAGE_PIN N19 } [get_ports "hbm_ref_clk_0_clk_n"] ;# Bank 800 " C4CCIO_PAD1_0_800 +set_property -dict { PACKAGE_PIN N38 } [get_ports "hbm_ref_clk_1_clk_p"] ;# Bank 801 " C4CCIO_PAD1_1_801 +set_property -dict { PACKAGE_PIN N37 } [get_ports "hbm_ref_clk_1_clk_n"] ;# Bank 801 " C4CCIO_PAD1_1_801 + +set_property -dict { PACKAGE_PIN CG6 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8 } [get_ports "smbus_0_scl_io"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 +set_property -dict { PACKAGE_PIN CH7 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8 } [get_ports "smbus_0_sda_io"] ;# Bank 702 VCCO - VR_1V2_VCCO_DDR4 + +# Uncomment below qsfp and mcio pins as design requires +set_property -dict { PACKAGE_PIN AR51 } [get_ports "qsfp0_322mhz_clk_p"] ;# Bank 209 " GTM_REFCLKP0_209 +# + set_property -dict { PACKAGE_PIN AE67 } [get_ports "qsfp0_4x_grx_p[0]"] ;# Bank 209 " GTM_RXP0_209 + set_property -dict { PACKAGE_PIN AE64 } [get_ports "qsfp0_4x_grx_p[1]"] ;# Bank 209 " GTM_RXP1_209 + set_property -dict { PACKAGE_PIN AC67 } [get_ports "qsfp0_4x_grx_p[2]"] ;# Bank 209 " GTM_RXP2_209 + set_property -dict { PACKAGE_PIN AC64 } [get_ports "qsfp0_4x_grx_p[3]"] ;# Bank 209 " GTM_RXP3_209 + + set_property -dict { PACKAGE_PIN AG61 } [get_ports "qsfp0_4x_gtx_p[0]"] ;# Bank 209 " GTM_TXP0_209 + set_property -dict { PACKAGE_PIN AG58 } [get_ports "qsfp0_4x_gtx_p[1]"] ;# Bank 209 " GTM_TXP1_209 + set_property -dict { PACKAGE_PIN AE61 } [get_ports "qsfp0_4x_gtx_p[2]"] ;# Bank 209 " GTM_TXP2_209 + set_property -dict { PACKAGE_PIN AE58 } [get_ports "qsfp0_4x_gtx_p[3]"] ;# Bank 209 " GTM_TXP3_209 +# + set_property -dict { PACKAGE_PIN AA67 } [get_ports "qsfp1_4x_grx_p[0]"] ;# Bank 210 " GTM_RXP0_210 + set_property -dict { PACKAGE_PIN AA64 } [get_ports "qsfp1_4x_grx_p[1]"] ;# Bank 210 " GTM_RXP1_210 + set_property -dict { PACKAGE_PIN W67 } [get_ports "qsfp1_4x_grx_p[2]"] ;# Bank 210 " GTM_RXP2_210 + set_property -dict { PACKAGE_PIN W64 } [get_ports "qsfp1_4x_grx_p[3]"] ;# Bank 210 " GTM_RXP3_210 + + set_property -dict { PACKAGE_PIN AC61 } [get_ports "qsfp1_4x_gtx_p[0]"] ;# Bank 210 " GTM_TXP0_210 + set_property -dict { PACKAGE_PIN AC58 } [get_ports "qsfp1_4x_gtx_p[1]"] ;# Bank 210 " GTM_TXP1_210 + set_property -dict { PACKAGE_PIN AA61 } [get_ports "qsfp1_4x_gtx_p[2]"] ;# Bank 210 " GTM_TXP2_210 + set_property -dict { PACKAGE_PIN AA58 } [get_ports "qsfp1_4x_gtx_p[3]"] ;# Bank 210 " GTM_TXP3_210 +# + set_property -dict { PACKAGE_PIN AL17 } [get_ports "qsfp2_322mhz_clk_p"] ;# Bank 111 " GTM_REFCLKP0_111 + + set_property -dict { PACKAGE_PIN U3 } [get_ports "qsfp2_4x_grx_p[0]"] ;# Bank 112 " GTM_RXP0_112 + set_property -dict { PACKAGE_PIN U6 } [get_ports "qsfp2_4x_grx_p[1]"] ;# Bank 112 " GTM_RXP1_112 + set_property -dict { PACKAGE_PIN R3 } [get_ports "qsfp2_4x_grx_p[2]"] ;# Bank 112 " GTM_RXP2_112 + set_property -dict { PACKAGE_PIN R6 } [get_ports "qsfp2_4x_grx_p[3]"] ;# Bank 112 " GTM_RXP3_112 + + set_property -dict { PACKAGE_PIN U9 } [get_ports "qsfp2_4x_gtx_p[0]"] ;# Bank 112 " GTM_TXP0_112 + set_property -dict { PACKAGE_PIN U12 } [get_ports "qsfp2_4x_gtx_p[1]"] ;# Bank 112 " GTM_TXP1_112 + set_property -dict { PACKAGE_PIN R9 } [get_ports "qsfp2_4x_gtx_p[2]"] ;# Bank 112 " GTM_TXP2_112 + set_property -dict { PACKAGE_PIN R12 } [get_ports "qsfp2_4x_gtx_p[3]"] ;# Bank 112 " GTM_TXP3_112 +# + set_property -dict { PACKAGE_PIN AA3 } [get_ports "qsfp3_4x_grx_p[0]"] ;# Bank 111 " GTM_RXP0_111 + set_property -dict { PACKAGE_PIN AA6 } [get_ports "qsfp3_4x_grx_p[1]"] ;# Bank 111 " GTM_RXP1_111 + set_property -dict { PACKAGE_PIN W3 } [get_ports "qsfp3_4x_grx_p[2]"] ;# Bank 111 " GTM_RXP2_111 + set_property -dict { PACKAGE_PIN W6 } [get_ports "qsfp3_4x_grx_p[3]"] ;# Bank 111 " GTM_RXP3_111 + + set_property -dict { PACKAGE_PIN AA9 } [get_ports "qsfp3_4x_gtx_p[0]"] ;# Bank 111 " GTM_TXP0_111 + set_property -dict { PACKAGE_PIN AA12 } [get_ports "qsfp3_4x_gtx_p[1]"] ;# Bank 111 " GTM_TXP1_111 + set_property -dict { PACKAGE_PIN W9 } [get_ports "qsfp3_4x_gtx_p[2]"] ;# Bank 111 " GTM_TXP2_111 + set_property -dict { PACKAGE_PIN W12 } [get_ports "qsfp3_4x_gtx_p[3]"] ;# Bank 111 " GTM_TXP3_111 +# +# set_property -dict { PACKAGE_PIN BP53 } [get_ports "mcio0_100mhz_clk_p"] ;# Bank 200 " GTYP_REFCLKP0_200 +# +# set_property -dict { PACKAGE_PIN BP66 } [get_ports "mcio0_4x_grx_p[0]"] ;# Bank 200 " GTYP_RXP0_200 +# set_property -dict { PACKAGE_PIN BP62 } [get_ports "mcio0_4x_grx_p[1]"] ;# Bank 200 " GTYP_RXP1_200 +# set_property -dict { PACKAGE_PIN BN68 } [get_ports "mcio0_4x_grx_p[2]"] ;# Bank 200 " GTYP_RXP2_200 +# set_property -dict { PACKAGE_PIN BN64 } [get_ports "mcio0_4x_grx_p[3]"] ;# Bank 200 " GTYP_RXP3_200 +# +# set_property -dict { PACKAGE_PIN BR59 } [get_ports "mcio0_4x_gtx_p[0]"] ;# Bank 200 " GTYP_TXP0_200 +# set_property -dict { PACKAGE_PIN BR55 } [get_ports "mcio0_4x_gtx_p[1]"] ;# Bank 200 " GTYP_TXP1_200 +# set_property -dict { PACKAGE_PIN BP57 } [get_ports "mcio0_4x_gtx_p[2]"] ;# Bank 200 " GTYP_TXP2_200 +# set_property -dict { PACKAGE_PIN BN59 } [get_ports "mcio0_4x_gtx_p[3]"] ;# Bank 200 " GTYP_TXP3_200 +# +# set_property -dict { PACKAGE_PIN AG55 } [get_ports "mcio1_100mhz_clk_p"] ;# Bank 213 " GTYP_REFCLKP0_213 +# +# set_property -dict { PACKAGE_PIN D66 } [get_ports "mcio1_a_4x_grx_p[0]"] ;# Bank 213 " GTYP_RXP0_213 +# set_property -dict { PACKAGE_PIN B65 } [get_ports "mcio1_a_4x_grx_p[1]"] ;# Bank 213 " GTYP_RXP1_213 +# set_property -dict { PACKAGE_PIN D64 } [get_ports "mcio1_a_4x_grx_p[2]"] ;# Bank 213 " GTYP_RXP2_213 +# set_property -dict { PACKAGE_PIN B63 } [get_ports "mcio1_a_4x_grx_p[3]"] ;# Bank 213 " GTYP_RXP3_213 +# +# set_property -dict { PACKAGE_PIN G69 } [get_ports "mcio1_a_4x_gtx_p[0]"] ;# Bank 213 " GTYP_TXP0_213 +# set_property -dict { PACKAGE_PIN E68 } [get_ports "mcio1_a_4x_gtx_p[1]"] ;# Bank 213 " GTYP_TXP1_213 +# set_property -dict { PACKAGE_PIN G67 } [get_ports "mcio1_a_4x_gtx_p[2]"] ;# Bank 213 " GTYP_TXP2_213 +# set_property -dict { PACKAGE_PIN G65 } [get_ports "mcio1_a_4x_gtx_p[3]"] ;# Bank 213 " GTYP_TXP3_213 +# +# set_property -dict { PACKAGE_PIN D62 } [get_ports "mcio1_b_4x_grx_p[0]"] ;# Bank 214 " GTYP_RXP0_214 +# set_property -dict { PACKAGE_PIN B61 } [get_ports "mcio1_b_4x_grx_p[1]"] ;# Bank 214 " GTYP_RXP1_214 +# set_property -dict { PACKAGE_PIN D60 } [get_ports "mcio1_b_4x_grx_p[2]"] ;# Bank 214 " GTYP_RXP2_214 +# set_property -dict { PACKAGE_PIN B59 } [get_ports "mcio1_b_4x_grx_p[3]"] ;# Bank 214 " GTYP_RXP3_214 +# +# set_property -dict { PACKAGE_PIN G63 } [get_ports "mcio1_b_4x_gtx_p[0]"] ;# Bank 214 " GTYP_TXP0_214 +# set_property -dict { PACKAGE_PIN G61 } [get_ports "mcio1_b_4x_gtx_p[1]"] ;# Bank 214 " GTYP_TXP1_214 +# set_property -dict { PACKAGE_PIN J60 } [get_ports "mcio1_b_4x_gtx_p[2]"] ;# Bank 214 " GTYP_TXP2_214 +# set_property -dict { PACKAGE_PIN G59 } [get_ports "mcio1_b_4x_gtx_p[3]"] ;# Bank 214 " GTYP_TXP3_214 +# +# set_property -dict { PACKAGE_PIN AB53 } [get_ports "mcio2_100mhz_clk_p"] ;# Bank 218 " GTYP_REFCLKP0_218 +# +# set_property -dict { PACKAGE_PIN D46 } [get_ports "mcio2_4x_grx_p[0]"] ;# Bank 218 " GTYP_RXP0_218 +# set_property -dict { PACKAGE_PIN B45 } [get_ports "mcio2_4x_grx_p[1]"] ;# Bank 218 " GTYP_RXP1_218 +# set_property -dict { PACKAGE_PIN D44 } [get_ports "mcio2_4x_grx_p[2]"] ;# Bank 218 " GTYP_RXP2_218 +# set_property -dict { PACKAGE_PIN B43 } [get_ports "mcio2_4x_grx_p[3]"] ;# Bank 218 " GTYP_RXP3_218 +# +# set_property -dict { PACKAGE_PIN J46 } [get_ports "mcio2_4x_gtx_p[0]"] ;# Bank 218 " GTYP_TXP0_218 +# set_property -dict { PACKAGE_PIN G45 } [get_ports "mcio2_4x_gtx_p[1]"] ;# Bank 218 " GTYP_TXP1_218 +# set_property -dict { PACKAGE_PIN J44 } [get_ports "mcio2_4x_gtx_p[2]"] ;# Bank 218 " GTYP_TXP2_218 +# set_property -dict { PACKAGE_PIN G43 } [get_ports "mcio2_4x_gtx_p[3]"] ;# Bank 218 " GTYP_TXP3_218 + diff --git a/linker/slashkit/resources/base/constraints/impl.xdc b/linker/slashkit/resources/base/constraints/impl.xdc new file mode 100644 index 00000000..94def793 --- /dev/null +++ b/linker/slashkit/resources/base/constraints/impl.xdc @@ -0,0 +1,74 @@ +# (c) Copyright 2024, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +create_pblock pblock_slash +add_cells_to_pblock [get_pblocks pblock_slash] [get_cells -quiet [list top_i/slash]] +resize_pblock [get_pblocks pblock_slash] -add {SLICE_X28Y716:SLICE_X351Y879 SLICE_X48Y620:SLICE_X351Y715 SLICE_X244Y575:SLICE_X351Y619 SLICE_X84Y575:SLICE_X163Y619 SLICE_X244Y574:SLICE_X323Y574} +resize_pblock [get_pblocks pblock_slash] -add {BUFG_FABRIC_X4Y144:BUFG_FABRIC_X4Y239 BUFG_FABRIC_X3Y168:BUFG_FABRIC_X3Y239 BUFG_FABRIC_X0Y144:BUFG_FABRIC_X2Y239} +resize_pblock [get_pblocks pblock_slash] -add {BUFG_PS_X2Y48:BUFG_PS_X2Y59} +resize_pblock [get_pblocks pblock_slash] -add {DSP58_CPLX_X0Y310:DSP58_CPLX_X11Y439 DSP58_CPLX_X8Y287:DSP58_CPLX_X11Y309 DSP58_CPLX_X0Y287:DSP58_CPLX_X3Y309} +resize_pblock [get_pblocks pblock_slash] -add {DSP_X0Y310:DSP_X23Y439 DSP_X16Y287:DSP_X23Y309 DSP_X0Y287:DSP_X7Y309} +resize_pblock [get_pblocks pblock_slash] -add {IRI_QUAD_X18Y2892:IRI_QUAD_X229Y3547 IRI_QUAD_X29Y2508:IRI_QUAD_X229Y2891 IRI_QUAD_X65Y2328:IRI_QUAD_X83Y2507 IRI_QUAD_X33Y2328:IRI_QUAD_X48Y2507 IRI_QUAD_X65Y2324:IRI_QUAD_X80Y2327} +resize_pblock [get_pblocks pblock_slash] -add {NOC_NMU512_X0Y13:NOC_NMU512_X3Y17 NOC_NMU512_X3Y12:NOC_NMU512_X3Y12 NOC_NMU512_X0Y12:NOC_NMU512_X1Y12} +resize_pblock [get_pblocks pblock_slash] -add {NOC_NPS_VNOC_X0Y26:NOC_NPS_VNOC_X3Y36 NOC_NPS_VNOC_X3Y24:NOC_NPS_VNOC_X3Y25 NOC_NPS_VNOC_X0Y24:NOC_NPS_VNOC_X1Y25} +resize_pblock [get_pblocks pblock_slash] -add {NOC_NSU512_X0Y13:NOC_NSU512_X3Y18 NOC_NSU512_X3Y12:NOC_NSU512_X3Y12 NOC_NSU512_X0Y12:NOC_NSU512_X1Y12} +resize_pblock [get_pblocks pblock_slash] -add {RAMB18_X1Y312:RAMB18_X15Y441 RAMB18_X10Y288:RAMB18_X15Y311 RAMB18_X2Y288:RAMB18_X5Y311} +resize_pblock [get_pblocks pblock_slash] -add {RAMB36_X1Y156:RAMB36_X15Y220 RAMB36_X10Y144:RAMB36_X15Y155 RAMB36_X2Y144:RAMB36_X5Y155} +resize_pblock [get_pblocks pblock_slash] -add {URAM288_X0Y180:URAM288_X7Y220 URAM288_X1Y156:URAM288_X7Y179 URAM288_X6Y144:URAM288_X7Y155 URAM288_X2Y144:URAM288_X3Y155} +resize_pblock [get_pblocks pblock_slash] -add {URAM_CAS_DLY_X0Y8:URAM_CAS_DLY_X7Y8 URAM_CAS_DLY_X1Y7:URAM_CAS_DLY_X7Y7 URAM_CAS_DLY_X6Y6:URAM_CAS_DLY_X7Y6 URAM_CAS_DLY_X2Y6:URAM_CAS_DLY_X3Y6} +resize_pblock [get_pblocks pblock_slash] -add {CLOCKREGION_X4Y7:CLOCKREGION_X5Y7} +set_property SNAPPING_MODE ON [get_pblocks pblock_slash] +set_property IS_SOFT FALSE [get_pblocks pblock_slash] +create_pblock pblock_service_layer +add_cells_to_pblock [get_pblocks pblock_service_layer] [get_cells -quiet [list top_i/service_layer]] +resize_pblock [get_pblocks pblock_service_layer] -add {SLICE_X0Y525:SLICE_X27Y619 SLICE_X256Y522:SLICE_X363Y524 SLICE_X0Y428:SLICE_X163Y524 SLICE_X244Y428:SLICE_X363Y521 SLICE_X0Y284:SLICE_X363Y427 SLICE_X48Y236:SLICE_X363Y283} +resize_pblock [get_pblocks pblock_service_layer] -add {BUFGCE_X11Y0:BUFGCE_X12Y23} +resize_pblock [get_pblocks pblock_service_layer] -add {BUFG_FABRIC_X4Y48:BUFG_FABRIC_X4Y143 BUFG_FABRIC_X3Y48:BUFG_FABRIC_X3Y119 BUFG_FABRIC_X1Y48:BUFG_FABRIC_X2Y143 BUFG_FABRIC_X0Y72:BUFG_FABRIC_X0Y143} +resize_pblock [get_pblocks pblock_service_layer] -add {BUFG_GT_X0Y167:BUFG_GT_X1Y48} +resize_pblock [get_pblocks pblock_service_layer] -add {BUFG_GT_SYNC_X0Y286:BUFG_GT_SYNC_X1Y82} +resize_pblock [get_pblocks pblock_service_layer] -add {BUFG_PS_X1Y24:BUFG_PS_X1Y47} +resize_pblock [get_pblocks pblock_service_layer] -add {DCMAC_X0Y2:DCMAC_X1Y0} +resize_pblock [get_pblocks pblock_service_layer] -add {DPLL_X14Y6:DPLL_X14Y7 DPLL_X3Y8:DPLL_X3Y11 DPLL_X1Y7:DPLL_X1Y7 DPLL_X0Y10:DPLL_X0Y13} +resize_pblock [get_pblocks pblock_service_layer] -add {DSP58_CPLX_X8Y118:DSP58_CPLX_X11Y262 DSP58_CPLX_X4Y118:DSP58_CPLX_X7Y213 DSP58_CPLX_X0Y118:DSP58_CPLX_X3Y262} +resize_pblock [get_pblocks pblock_service_layer] -add {DSP_X16Y118:DSP_X23Y262 DSP_X8Y118:DSP_X15Y213 DSP_X0Y118:DSP_X7Y262} +resize_pblock [get_pblocks pblock_service_layer] -add {GTM_QUAD_X1Y7:GTM_QUAD_X1Y8 GTM_QUAD_X0Y9:GTM_QUAD_X0Y10} +resize_pblock [get_pblocks pblock_service_layer] -add {GTM_REFCLK_X1Y14:GTM_REFCLK_X1Y17 GTM_REFCLK_X0Y18:GTM_REFCLK_X0Y21} +resize_pblock [get_pblocks pblock_service_layer] -add {HSC_X0Y1:HSC_X0Y1} +resize_pblock [get_pblocks pblock_service_layer] -add {ILKNF_X0Y0:ILKNF_X0Y0} +resize_pblock [get_pblocks pblock_service_layer] -add {IRI_QUAD_X0Y2128:IRI_QUAD_X3Y2507 IRI_QUAD_X67Y2116:IRI_QUAD_X86Y2127 IRI_QUAD_X0Y1740:IRI_QUAD_X48Y2127 IRI_QUAD_X65Y1740:IRI_QUAD_X86Y2115 IRI_QUAD_X29Y1356:IRI_QUAD_X86Y1739 IRI_QUAD_X0Y1164:IRI_QUAD_X244Y1355 IRI_QUAD_X29Y972:IRI_QUAD_X244Y1163} +resize_pblock [get_pblocks pblock_service_layer] -add {MMCM_X11Y0:MMCM_X12Y0} +resize_pblock [get_pblocks pblock_service_layer] -add {MRMAC_X0Y3:MRMAC_X1Y1} +resize_pblock [get_pblocks pblock_service_layer] -add {NOC_NMU512_X3Y5:NOC_NMU512_X3Y10 NOC_NMU512_X2Y5:NOC_NMU512_X2Y8 NOC_NMU512_X0Y5:NOC_NMU512_X1Y10} +resize_pblock [get_pblocks pblock_service_layer] -add {NOC_NPS_VNOC_X3Y10:NOC_NPS_VNOC_X3Y21 NOC_NPS_VNOC_X2Y10:NOC_NPS_VNOC_X2Y17 NOC_NPS_VNOC_X0Y10:NOC_NPS_VNOC_X1Y21} +resize_pblock [get_pblocks pblock_service_layer] -add {NOC_NSU512_X3Y5:NOC_NSU512_X3Y10 NOC_NSU512_X2Y5:NOC_NSU512_X2Y8 NOC_NSU512_X0Y5:NOC_NSU512_X1Y10} +resize_pblock [get_pblocks pblock_service_layer] -add {RAMB18_X10Y120:RAMB18_X16Y265 RAMB18_X6Y120:RAMB18_X9Y215 RAMB18_X1Y120:RAMB18_X5Y265 RAMB18_X0Y144:RAMB18_X0Y311} +resize_pblock [get_pblocks pblock_service_layer] -add {RAMB36_X10Y60:RAMB36_X16Y132 RAMB36_X6Y60:RAMB36_X9Y107 RAMB36_X1Y60:RAMB36_X5Y132 RAMB36_X0Y72:RAMB36_X0Y155} +resize_pblock [get_pblocks pblock_service_layer] -add {URAM288_X6Y60:URAM288_X8Y132 URAM288_X4Y60:URAM288_X5Y107 URAM288_X1Y60:URAM288_X3Y132 URAM288_X0Y72:URAM288_X0Y132} +resize_pblock [get_pblocks pblock_service_layer] -add {URAM_CAS_DLY_X6Y2:URAM_CAS_DLY_X8Y5 URAM_CAS_DLY_X4Y2:URAM_CAS_DLY_X5Y4 URAM_CAS_DLY_X1Y2:URAM_CAS_DLY_X3Y5 URAM_CAS_DLY_X0Y3:URAM_CAS_DLY_X0Y5} +set_property SNAPPING_MODE ON [get_pblocks pblock_service_layer] +set_property IS_SOFT FALSE [get_pblocks pblock_service_layer] +set_property NOC_HIGH_ID_MAX 63 [get_pblocks pblock_service_layer] +set_property NOC_HIGH_ID_MIN 49 [get_pblocks pblock_service_layer] +set_property NOC_HIGH_ID_MAX 48 [get_pblocks pblock_slash] +set_property NOC_HIGH_ID_MIN 31 [get_pblocks pblock_slash] + + #set_false_path -reset_path -from [get_pins {top_i/static_region/clk_rst_shell/proc_sys_reset_0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C}] + #set_false_path -reset_path -from [get_pins {top_i/static_region/clk_rst_shell/proc_sys_reset_1/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C}] diff --git a/linker/slashkit/resources/base/constraints/opt.post.tcl b/linker/slashkit/resources/base/constraints/opt.post.tcl new file mode 100644 index 00000000..a0074dfd --- /dev/null +++ b/linker/slashkit/resources/base/constraints/opt.post.tcl @@ -0,0 +1,31 @@ +# (c) Copyright 2024, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# Set pdi properties to accelerate device download +set_property bitstream.general.npiDmaMode Yes [current_design] +set_property bitstream.general.compress true [current_design] +# set_param place.runBufgInsertion false +# set_param place.runBufgInsertionVersal false + +set_property LOC GTM_QUAD_X0Y10 [get_cells top_i/service_layer/qsfp_2_n_3/DCMAC_subsys/dcmac_gt1_wrapper/gt0_quad/inst/quad_inst ] +set_property LOC GTM_QUAD_X1Y7 [get_cells top_i/service_layer/qsfp_0_n_1/DCMAC_subsys/dcmac_gt0_wrapper/gt0_quad/inst/quad_inst ] +set_property -dict { PACKAGE_PIN AR51 } [get_ports "qsfp0_322mhz_clk_p"] +set_property -dict { PACKAGE_PIN AL17 } [get_ports "qsfp2_322mhz_clk_p"] \ No newline at end of file diff --git a/linker/slashkit/resources/base/constraints/place.pre.tcl b/linker/slashkit/resources/base/constraints/place.pre.tcl new file mode 100644 index 00000000..e4b1e26f --- /dev/null +++ b/linker/slashkit/resources/base/constraints/place.pre.tcl @@ -0,0 +1,34 @@ +# (c) Copyright 2024, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# Connect the DMA reset detection signal to the PMC Interrupt input to allow a full PDI reload to be triggered on PCIe hot reset +set PS9_IRQ_pin [get_pins -of [get_cells -hierarchical PS9_inst -filter { PARENT =~ "top_i/static_region/aved/cips*"}] -filter { REF_PIN_NAME =~ "PMCPLIRQ[4]"}] +if {[llength ${PS9_IRQ_pin}] == 1} { + # Remove dont_touch + set_property dont_touch 0 [get_nets -of [get_pins top_i/static_region/aved/clock_reset/pcie_mgmt_pdi_reset/pcie_mgmt_pdi_reset_gpio/gpio2_io_i]] + set_property dont_touch 0 [get_cells top_i/static_region/aved/cips/inst/pspmc_0/inst] + set_property dont_touch 0 [get_cells top_i/static_region/aved/cips] + disconnect_net -objects ${PS9_IRQ_pin} + connect_net -hierarchical -net [get_nets -of [get_pins top_i/static_region/aved/clock_reset/pcie_mgmt_pdi_reset/pcie_mgmt_pdi_reset_gpio/gpio2_io_i]] -objects ${PS9_IRQ_pin} +} else { + puts "Unable to get PMCPLIRQ pin for Force Reset rewiring." +} + diff --git a/linker/slashkit/resources/base/constraints/service_layer/__init__.py b/linker/slashkit/resources/base/constraints/service_layer/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/base/constraints/service_layer/eth/__init__.py b/linker/slashkit/resources/base/constraints/service_layer/eth/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/base/constraints/service_layer/eth/service_layer_eth.opt.post.tcl b/linker/slashkit/resources/base/constraints/service_layer/eth/service_layer_eth.opt.post.tcl new file mode 100644 index 00000000..bc4e320e --- /dev/null +++ b/linker/slashkit/resources/base/constraints/service_layer/eth/service_layer_eth.opt.post.tcl @@ -0,0 +1,24 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set_property -quiet LOC GTM_QUAD_X0Y10 [get_cells -quiet {top_i/service_layer/qsfp_2_n_3/DCMAC_subsys/dcmac_gt1_wrapper/gt0_quad/inst/quad_inst}] +set_property -quiet LOC GTM_QUAD_X1Y7 [get_cells -quiet {top_i/service_layer/qsfp_0_n_1/DCMAC_subsys/dcmac_gt0_wrapper/gt0_quad/inst/quad_inst}] +set_property -quiet -dict { PACKAGE_PIN AR51 } [get_ports -quiet {qsfp0_322mhz_clk_p}] +set_property -quiet -dict { PACKAGE_PIN AL17 } [get_ports -quiet {qsfp2_322mhz_clk_p}] diff --git a/linker/slashkit/resources/base/constraints/write_device_image.pre.tcl b/linker/slashkit/resources/base/constraints/write_device_image.pre.tcl new file mode 100644 index 00000000..ec3bdbcf --- /dev/null +++ b/linker/slashkit/resources/base/constraints/write_device_image.pre.tcl @@ -0,0 +1,126 @@ +# (c) Copyright 2024, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# TODO Remove interface UUID once ART is available +# TODO should we also allow user to provide the UUID value, or other values to add in UUID ROM (e.g. version, etc) +# TODO should we also allow user to provide bitstream USR_ACCESS 32-bit register value (e.g. version, etc)? + + # For now, this script: + # - Calculates a platform Logic-UUID from the synthesized checkpoint, and populates the UUID ROM with it; + # - Calculates a platform Interface-UUID from the routed checkpoint; + # - Inserts the Logic-UUID and Interface-UUID into a dictionary in a file used by write_hw_platform. + # ========================================================================= + + proc find_dir {base name} { + set res [glob -nocomplain -types d -directory $base $name] + if {$res != {}} { + return $res + } + foreach dir [glob -nocomplain -types d -directory $base *] { + set res [find_dir [file join $base $dir] $name] + if {$res != {}} { + return $res + } + } + return {} + } + + # Procedure to update the Logic UUID ROM + # Input is 64 hex character string (256-bit UUID) + + proc update_logic_uuid_rom {uuid} { + + # Get the absolute directory path of the shel_utils_uuid_rom_v2_0 Tcl directory + set scr_fname {} + + foreach ip_repo_path [get_property IP_REPO_PATHS [current_project]] { + set scr_fname [find_dir $ip_repo_path shell_utils_uuid_rom_v2_0] + if {$scr_fname != {}} { + break + } + } + set update_uuid_rom [file join $scr_fname tcl update_uuid_rom.tcl] + + # Source the update UUID ROM script, return an error if not found + if {[file exists $update_uuid_rom]} { + source $update_uuid_rom + } else { + return -code error "ERROR: update_uuid_rom.tcl script not found, Logic UUID not populated." + } + + # Search for the BLP_LOGIC_UUID_ROM cell path in the netlist, return an error if not found + set uuid_cell [get_cells -hier -filter {NAME =~ "*uuid_rom" && PARENT =~ "*base_logic"}] + if {$uuid_cell eq ""} { + return -code error "ERROR: BLP_LOGIC_UUID_ROM cell not found in netlist, Logic UUID not populated." + } + + # Call the update_uuid_rom script to update the Logic UUID ROM, return the response + return [update_uuid_rom $uuid $uuid_cell] + } + + set top_name [get_property TOP [current_design]] + + # Code to generate a Logic-UUID from the synthesized checkpoint + # Get the absolute directory path of the project synth_1 run + set synth_fname [file normalize "../synth_1/"] + + # Use md5sum to calculate a Logic-UUID and then populate the ROM with it, or return an error if the checkpoint isn't found + if {[file exists ${synth_fname}/${top_name}.dcp]} { + set logic_uuid [lindex [exec md5sum ${synth_fname}/${top_name}.dcp] 0] + puts "Logic-UUID is $logic_uuid" + update_logic_uuid_rom $logic_uuid + } else { + return -code error "ERROR: synthesized checkpoint ${top_name}.dcp not found, cannot generate Logic-UUID." + } + + # Create a dictionary of each cell that will require a generated UUID, starting with design top + set design_top [lindex [get_cells] 0] + set uuid_dict [dict create logic_uuid $logic_uuid] + + # Generate a UUID and add it to the dictionary for ulp cell + set dfx_cells [list top_i/ulp] + if {1 != [llength $dfx_cells]} { + return -code error "ERROR: more than one reconfigurable partition found; this is not currently supported, so cannot generate Interface-UUID." + } + foreach {dfx_cell} $dfx_cells { + # Code to generate an Interface-UUID from the routed checkpoint + # Get the absolute directory path of the project impl_1 run + set route_fname [file normalize "./"] + + # Use md5sum to calculate an Interface-UUID, or return an error if the checkpoint isn't found + if {[file exists ${route_fname}/${top_name}_routed.dcp]} { + set interface_uuid [lindex [exec md5sum ${route_fname}/${top_name}_routed.dcp] 0] + puts "Interface-UUID is $interface_uuid" + dict set uuid_dict interface_uuid ${interface_uuid} + } else { + return -code error "ERROR: routed checkpoint ${top_name}_routed.dcp not found, cannot generate Interface-UUID." + } + } + + # Now write the full dictionary, consisting of key-value pairs of the top cell and its Logic-UUID, and the reconfigurable module + # and its Interface-UUID, to a file with predetermined name required for the write_hw_platform flow. + set uuid_file [open [file join [get_property DIRECTORY [current_project]] "pfm_uuid_manifest.dict"] w] + puts $uuid_file $uuid_dict + close $uuid_file + +# Enable automatic loading of bitstream USR_ACCESS 32-bit register with timestamp +# TODO why is this set here and not in build_hw.tcl? +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] diff --git a/linker/slashkit/resources/base/iprepo/.gitignore b/linker/slashkit/resources/base/iprepo/.gitignore new file mode 100644 index 00000000..ed26ed49 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/.gitignore @@ -0,0 +1 @@ +smbus_* diff --git a/linker/slashkit/resources/base/iprepo/Makefile b/linker/slashkit/resources/base/iprepo/Makefile new file mode 100644 index 00000000..8e2d76f5 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/Makefile @@ -0,0 +1,46 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +SUBDIRS := hbm_bandwidth traffic_producer +SUBTARGET ?= all + +.PHONY: all clean rebuild $(SUBDIRS) build-% clean-% rebuild-% + +all: $(SUBDIRS) + +$(SUBDIRS): + $(MAKE) -C $@ $(SUBTARGET) + +clean: + @for d in $(SUBDIRS); do \ + $(MAKE) -C $$d clean || exit $$?; \ + done + +rebuild: clean all + +build-%: + $(MAKE) -C $* $(SUBTARGET) + +clean-%: + $(MAKE) -C $* clean + +rebuild-%: + $(MAKE) -C $* clean + $(MAKE) -C $* $(SUBTARGET) diff --git a/linker/slashkit/resources/base/iprepo/__init__.py b/linker/slashkit/resources/base/iprepo/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/component.xml b/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/component.xml new file mode 100644 index 00000000..c52d7ea9 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/component.xml @@ -0,0 +1,2563 @@ + + + user.org + user + axi4_full_passthrough + 1.0 + + + m_axi + + + + + + + + + AWID + + + m_axi_awid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWLEN + + + m_axi_awlen + + + + + AWSIZE + + + m_axi_awsize + + + + + AWBURST + + + m_axi_awburst + + + + + AWLOCK + + + m_axi_awlock + + + + + AWCACHE + + + m_axi_awcache + + + + + AWPROT + + + m_axi_awprot + + + + + AWREGION + + + m_axi_awregion + + + + + AWQOS + + + m_axi_awqos + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + AWREADY + + + m_axi_awready + + + + + WDATA + + + m_axi_wdata + + + + + WSTRB + + + m_axi_wstrb + + + + + WLAST + + + m_axi_wlast + + + + + WUSER + + + m_axi_wuser + + + + + WVALID + + + m_axi_wvalid + + + + + WREADY + + + m_axi_wready + + + + + BID + + + m_axi_bid + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + BREADY + + + m_axi_bready + + + + + ARID + + + m_axi_arid + + + + + ARADDR + + + m_axi_araddr + + + + + ARLEN + + + m_axi_arlen + + + + + ARSIZE + + + m_axi_arsize + + + + + ARBURST + + + m_axi_arburst + + + + + ARLOCK + + + m_axi_arlock + + + + + ARCACHE + + + m_axi_arcache + + + + + ARPROT + + + m_axi_arprot + + + + + ARREGION + + + m_axi_arregion + + + + + ARQOS + + + m_axi_arqos + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + ARREADY + + + m_axi_arready + + + + + RID + + + m_axi_rid + + + + + RDATA + + + m_axi_rdata + + + + + RRESP + + + m_axi_rresp + + + + + RLAST + + + m_axi_rlast + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + RREADY + + + m_axi_rready + + + + + + s_axi + + + + + + + + + AWID + + + s_axi_awid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWLEN + + + s_axi_awlen + + + + + AWSIZE + + + s_axi_awsize + + + + + AWBURST + + + s_axi_awburst + + + + + AWLOCK + + + s_axi_awlock + + + + + AWCACHE + + + s_axi_awcache + + + + + AWPROT + + + s_axi_awprot + + + + + AWREGION + + + s_axi_awregion + + + + + AWQOS + + + s_axi_awqos + + + + + AWUSER + + + s_axi_awuser + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WLAST + + + s_axi_wlast + + + + + WUSER + + + s_axi_wuser + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BID + + + s_axi_bid + + + + + BRESP + + + s_axi_bresp + + + + + BUSER + + + s_axi_buser + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARID + + + s_axi_arid + + + + + ARADDR + + + s_axi_araddr + + + + + ARLEN + + + s_axi_arlen + + + + + ARSIZE + + + s_axi_arsize + + + + + ARBURST + + + s_axi_arburst + + + + + ARLOCK + + + s_axi_arlock + + + + + ARCACHE + + + s_axi_arcache + + + + + ARPROT + + + s_axi_arprot + + + + + ARREGION + + + s_axi_arregion + + + + + ARQOS + + + s_axi_arqos + + + + + ARUSER + + + s_axi_aruser + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RID + + + s_axi_rid + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RLAST + + + s_axi_rlast + + + + + RUSER + + + s_axi_ruser + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axi:s_axi + + + ASSOCIATED_RESET + aresetn + + + + + + + m_axi + m_axi + 16777216T + 256 + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 16777216T + 256 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi4_full_passthrough + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 10e55076 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi4_full_passthrough + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 10e55076 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + a9b817df + + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awid + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awlen + + in + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awsize + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awburst + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_awlock + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awcache + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 3 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awqos + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awregion + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awuser + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wlast + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wuser + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bid + + out + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_buser + + out + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arid + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arlen + + in + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arsize + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_arburst + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_arlock + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arcache + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 3 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arqos + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arregion + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aruser + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rid + + out + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ruser + + out + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_awid + + out + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awaddr + + out + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awlen + + out + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awsize + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awburst + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awlock + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awcache + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awqos + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awregion + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awuser + + out + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_wdata + + out + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wstrb + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wuser + + out + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bid + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_buser + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arid + + out + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_araddr + + out + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arlen + + out + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arlock + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arregion + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rid + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rdata + + in + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rlast + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_ruser + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + AXI_ID_WIDTH + Axi Id Width + 6 + + + AXI_ADDR_WIDTH + Axi Addr Width + 64 + + + AXI_DATA_WIDTH + Axi Data Width + 256 + + + AXI_AWUSER_WIDTH + Axi Awuser Width + 1 + + + AXI_WUSER_WIDTH + Axi Wuser Width + 1 + + + AXI_BUSER_WIDTH + Axi Buser Width + 1 + + + AXI_ARUSER_WIDTH + Axi Aruser Width + 1 + + + AXI_RUSER_WIDTH + Axi Ruser Width + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axi_passthrough.v + verilogSource + CHECKSUM_10e55076 + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axi_passthrough.v + verilogSource + IMPORTED_FILE + + + + xilinx_xpgui_view_fileset + + xgui/axi4_full_passthrough_v1_0.tcl + tclSource + CHECKSUM_a9b817df + XGUI_VERSION_2 + + + + axi4_full_passthrough_v1_0 + + + AXI_ID_WIDTH + Axi Id Width + 6 + + + AXI_ADDR_WIDTH + Axi Addr Width + 64 + + + AXI_DATA_WIDTH + Axi Data Width + 256 + + + AXI_AWUSER_WIDTH + Axi Awuser Width + 1 + + + AXI_WUSER_WIDTH + Axi Wuser Width + 1 + + + AXI_BUSER_WIDTH + Axi Buser Width + 1 + + + AXI_ARUSER_WIDTH + Axi Aruser Width + 1 + + + AXI_RUSER_WIDTH + Axi Ruser Width + 1 + + + Component_Name + axi4_full_passthrough_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + axi4_full_passthrough_v1_0 + package_project + 2 + 2026-01-15T12:25:18Z + + + 2024.2 + + + + + + + + + + diff --git a/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/src/axi_passthrough.v b/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/src/axi_passthrough.v new file mode 100644 index 00000000..0f85a2c6 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/src/axi_passthrough.v @@ -0,0 +1,216 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +module axi4_full_passthrough #( + parameter integer AXI_ID_WIDTH = 6, + parameter integer AXI_ADDR_WIDTH = 64, + parameter integer AXI_DATA_WIDTH = 256, + parameter integer AXI_AWUSER_WIDTH = 1, + parameter integer AXI_WUSER_WIDTH = 1, + parameter integer AXI_BUSER_WIDTH = 1, + parameter integer AXI_ARUSER_WIDTH = 1, + parameter integer AXI_RUSER_WIDTH = 1 +)( + input wire aclk, + input wire aresetn, + + // ----------------------- + // Slave AXI4-Full (S_AXI) + // ----------------------- + // Write address channel + input wire [AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [7:0] s_axi_awlen, + input wire [2:0] s_axi_awsize, + input wire [1:0] s_axi_awburst, + input wire s_axi_awlock, + input wire [3:0] s_axi_awcache, + input wire [2:0] s_axi_awprot, + input wire [3:0] s_axi_awqos, + input wire [3:0] s_axi_awregion, + input wire [AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire s_axi_awvalid, + output wire s_axi_awready, + + // Write data channel + input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [(AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire s_axi_wvalid, + output wire s_axi_wready, + + // Write response channel + output wire [AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [1:0] s_axi_bresp, + output wire [AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire s_axi_bvalid, + input wire s_axi_bready, + + // Read address channel + input wire [AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [7:0] s_axi_arlen, + input wire [2:0] s_axi_arsize, + input wire [1:0] s_axi_arburst, + input wire s_axi_arlock, + input wire [3:0] s_axi_arcache, + input wire [2:0] s_axi_arprot, + input wire [3:0] s_axi_arqos, + input wire [3:0] s_axi_arregion, + input wire [AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire s_axi_arvalid, + output wire s_axi_arready, + + // Read data channel + output wire [AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // ------------------------ + // Master AXI4-Full (M_AXI) + // ------------------------ + // Write address channel + output wire [AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire [3:0] m_axi_awqos, + output wire [3:0] m_axi_awregion, + output wire [AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // Write data channel + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [(AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // Write response channel + input wire [AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire [AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // Read address channel + output wire [AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire [3:0] m_axi_arqos, + output wire [3:0] m_axi_arregion, + output wire [AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // Read data channel + input wire [AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready +); + + // aclk/aresetn are intentionally unused (wire-through) + wire _unused = aclk ^ aresetn; + + // ------------------------- + // AW channel passthrough + // ------------------------- + assign m_axi_awid = s_axi_awid; + assign m_axi_awaddr = s_axi_awaddr; + assign m_axi_awlen = s_axi_awlen; + assign m_axi_awsize = s_axi_awsize; + assign m_axi_awburst = s_axi_awburst; + assign m_axi_awlock = s_axi_awlock; + assign m_axi_awcache = s_axi_awcache; + assign m_axi_awprot = s_axi_awprot; + assign m_axi_awqos = s_axi_awqos; + assign m_axi_awregion = s_axi_awregion; + assign m_axi_awuser = s_axi_awuser; + assign m_axi_awvalid = s_axi_awvalid; + assign s_axi_awready = m_axi_awready; + + // ------------------------- + // W channel passthrough + // ------------------------- + assign m_axi_wdata = s_axi_wdata; + assign m_axi_wstrb = s_axi_wstrb; + assign m_axi_wlast = s_axi_wlast; + assign m_axi_wuser = s_axi_wuser; + assign m_axi_wvalid = s_axi_wvalid; + assign s_axi_wready = m_axi_wready; + + // ------------------------- + // B channel passthrough + // ------------------------- + assign s_axi_bid = m_axi_bid; + assign s_axi_bresp = m_axi_bresp; + assign s_axi_buser = m_axi_buser; + assign s_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = s_axi_bready; + + // ------------------------- + // AR channel passthrough + // ------------------------- + assign m_axi_arid = s_axi_arid; + assign m_axi_araddr = s_axi_araddr; + assign m_axi_arlen = s_axi_arlen; + assign m_axi_arsize = s_axi_arsize; + assign m_axi_arburst = s_axi_arburst; + assign m_axi_arlock = s_axi_arlock; + assign m_axi_arcache = s_axi_arcache; + assign m_axi_arprot = s_axi_arprot; + assign m_axi_arqos = s_axi_arqos; + assign m_axi_arregion = s_axi_arregion; + assign m_axi_aruser = s_axi_aruser; + assign m_axi_arvalid = s_axi_arvalid; + assign s_axi_arready = m_axi_arready; + + // ------------------------- + // R channel passthrough + // ------------------------- + assign s_axi_rid = m_axi_rid; + assign s_axi_rdata = m_axi_rdata; + assign s_axi_rresp = m_axi_rresp; + assign s_axi_rlast = m_axi_rlast; + assign s_axi_ruser = m_axi_ruser; + assign s_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = s_axi_rready; + +endmodule diff --git a/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/xgui/axi4_full_passthrough_v1_0.tcl b/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/xgui/axi4_full_passthrough_v1_0.tcl new file mode 100644 index 00000000..9a05574b --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/axi4_full_passthrough/xgui/axi4_full_passthrough_v1_0.tcl @@ -0,0 +1,130 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_ARUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_AWUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_BUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_ID_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_RUSER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_WUSER_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to update AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to validate AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_ARUSER_WIDTH { PARAM_VALUE.AXI_ARUSER_WIDTH } { + # Procedure called to update AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ARUSER_WIDTH { PARAM_VALUE.AXI_ARUSER_WIDTH } { + # Procedure called to validate AXI_ARUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_AWUSER_WIDTH { PARAM_VALUE.AXI_AWUSER_WIDTH } { + # Procedure called to update AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_AWUSER_WIDTH { PARAM_VALUE.AXI_AWUSER_WIDTH } { + # Procedure called to validate AXI_AWUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_BUSER_WIDTH { PARAM_VALUE.AXI_BUSER_WIDTH } { + # Procedure called to update AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_BUSER_WIDTH { PARAM_VALUE.AXI_BUSER_WIDTH } { + # Procedure called to validate AXI_BUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to validate AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to update AXI_ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to validate AXI_ID_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_RUSER_WIDTH { PARAM_VALUE.AXI_RUSER_WIDTH } { + # Procedure called to update AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_RUSER_WIDTH { PARAM_VALUE.AXI_RUSER_WIDTH } { + # Procedure called to validate AXI_RUSER_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_WUSER_WIDTH { PARAM_VALUE.AXI_WUSER_WIDTH } { + # Procedure called to update AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_WUSER_WIDTH { PARAM_VALUE.AXI_WUSER_WIDTH } { + # Procedure called to validate AXI_WUSER_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.AXI_ID_WIDTH { MODELPARAM_VALUE.AXI_ID_WIDTH PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH}] ${MODELPARAM_VALUE.AXI_ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_ADDR_WIDTH { MODELPARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_AWUSER_WIDTH { MODELPARAM_VALUE.AXI_AWUSER_WIDTH PARAM_VALUE.AXI_AWUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.AXI_AWUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_WUSER_WIDTH { MODELPARAM_VALUE.AXI_WUSER_WIDTH PARAM_VALUE.AXI_WUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.AXI_WUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_BUSER_WIDTH { MODELPARAM_VALUE.AXI_BUSER_WIDTH PARAM_VALUE.AXI_BUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.AXI_BUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_ARUSER_WIDTH { MODELPARAM_VALUE.AXI_ARUSER_WIDTH PARAM_VALUE.AXI_ARUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.AXI_ARUSER_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_RUSER_WIDTH { MODELPARAM_VALUE.AXI_RUSER_WIDTH PARAM_VALUE.AXI_RUSER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.AXI_RUSER_WIDTH} +} + diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/bd/bd.tcl b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/bd/bd.tcl new file mode 100644 index 00000000..b3886c84 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/bd/bd.tcl @@ -0,0 +1,27 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +#==========================================================# +# Post IP Configuration Procedure +#==========================================================# + +proc post_config_ip { cellPath otherInfo } { +} diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/component.xml b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/component.xml new file mode 100644 index 00000000..f974edf6 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/component.xml @@ -0,0 +1,1948 @@ + + + xilinx.com + ip + cmd_queue + 2.0 + + + S00_AXI + + + + + + + ARADDR + + + s00_axi_araddr + + + + + ARREADY + + + s00_axi_arready + + + + + ARVALID + + + s00_axi_arvalid + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWREADY + + + s00_axi_awready + + + + + AWVALID + + + s00_axi_awvalid + + + + + BREADY + + + s00_axi_bready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + RDATA + + + s00_axi_rdata + + + + + RREADY + + + s00_axi_rready + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + WDATA + + + s00_axi_wdata + + + + + WREADY + + + s00_axi_wready + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + + S01_AXI + + + + + + + ARADDR + + + s01_axi_araddr + + + + + ARREADY + + + s01_axi_arready + + + + + ARVALID + + + s01_axi_arvalid + + + + + AWADDR + + + s01_axi_awaddr + + + + + AWREADY + + + s01_axi_awready + + + + + AWVALID + + + s01_axi_awvalid + + + + + BREADY + + + s01_axi_bready + + + + + BRESP + + + s01_axi_bresp + + + + + BVALID + + + s01_axi_bvalid + + + + + RDATA + + + s01_axi_rdata + + + + + RREADY + + + s01_axi_rready + + + + + RRESP + + + s01_axi_rresp + + + + + RVALID + + + s01_axi_rvalid + + + + + WDATA + + + s01_axi_wdata + + + + + WREADY + + + s01_axi_wready + + + + + WSTRB + + + s01_axi_wstrb + + + + + WVALID + + + s01_axi_wvalid + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + S00_AXI:S01_AXI + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + aclk frequency + aclk frequency + 250000000 + + + + + irq_sq + irq_sq + + + + + + + INTERRUPT + + + irq_sq + + + + + + SENSITIVITY + EDGE_RISING + + + + + irq_cq + irq_cq + + + + + + + INTERRUPT + + + irq_cq + + + + + + SENSITIVITY + EDGE_RISING + + + + + + + S00_AXI + S00_AXI memory map + + S00_AXI_Reg + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S00_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S00_AXI_HIGHADDR + + + + SQ_TAIL_POINTER + SQ_TAIL_POINTER + Submission Queue Tail Pointer Register + 0x000 + 32 + read-write + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Submission Queue Tail Pointer Offset +Configure the Tail Pointer offset for the Submission Queue. +If the INTERRUPT_TYPE field in SQ_RESET_INTERRUPT_CTRL register is 0x0, then a write to this register triggers the submission queue interrupt. +Once triggered, the submission queue interrupt can only be cleared by reading the the SQ_TAIL_POINTER register on the S01_AXI interface. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + SQ_INTERRUPT_REG + SQ_INTERRUPT_REG + Submission Queue Interrupt Register + 0x004 + 32 + read-write + + 0x0 + + + INTERRUPT + INTERRUPT + Submission Queue Interrupt +When set - and while the INTERRUPT_TYPE field is 0x1, INTERRUPT_ENABLE field is 0x1, and RESET field is 0x0 in SQ_RESET_INTERRUPT_CTRL register - triggers an interrupt on the submission queue. +Once triggered, the submission queue interrupt can only be cleared by reading the INTERRUPT_STATUS field of the SQ_INTERRUPT_STATUS register. +0x0 - Do not trigger an interrupt on the submission queue +0x1 - Trigger an interrupt on the submission queue + + 0 + 1 + write-only + + 0 + 0 + + false + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Submission Queue Interrupt Status +Reports the current status of the Submission Queue interrupt. +0x0 - Submission Queue interrupt de-asserted +0x1 - Submission Queue interrupt asserted + + 1 + 1 + read-only + + 0 + 0 + + false + + + + SQ_QUEUE_MEM_ADDR_LOW + SQ_QUEUE_MEM_ADDR_LOW + Submission Queue Memory Address Low + 0x008 + 32 + read-write + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Submission Queue Memory Address Low +Represents bits 31:0 of the submission queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + SQ_RESET_INTERRUPT_CTRL + SQ_RESET_INTERRUPT_CTRL + Submission Queue Reset and Interrupt Control + 0x00C + 32 + read-write + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Submission Queue Interrupt Enable +When set, enables the submission queue interrupt output. +0x0 - Disable submission queue interrupt +0x1 - Enable submission queue interrupt + + 0 + 1 + read-write + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Submission Queue Interrupt Type +Determines the interrupt type in use for the submission queue. +0x0 - Interrupt for the submission queue is triggered on a write operation to the SQ_TAIL_POINTER register +0x1 - Interrupt for the submission queue is triggered by setting the INTERRUPT field of the SQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-write + + 0 + 0 + + false + + + RESET + RESET + Reset +Performs a soft reset of all submission queue and completion queue registers. +0x0 - Do not reset all submission/completion queue registers +0x1 - Reset all submission/completion queue registers +This field is self-clearing once set. + + 31 + 1 + write-only + + 0 + 0 + + false + + + + SQ_QUEUE_MEM_ADDR_HIGH + SQ_QUEUE_MEM_ADDR_HIGH + Submission Queue Memory Address High + 0x010 + 32 + read-write + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Submission Queue Memory Address High +Represents bits 63:32 of the submission queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + CQ_TAIL_POINTER + CQ_TAIL_POINTER + Completion Queue Tail Pointer Register + 0x100 + 32 + read-only + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Completion Queue Tail Pointer Offset +Returns the tail pointer offset for the completion queue. +If the INTERRUPT_TYPE field in CQ_RESET_INTERRUPT_CTRL is 0x0, then reading this register clears the completion queue interrupt if asserted. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + CQ_INTERRUPT_STATUS + CQ_INTERRUPT_STATUS + Completion Queue Interrupt Status Register + 0x104 + 32 + read-only + + 0x0 + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Completion Queue Interrupt Status +Returns the current state of the interrupt for the completion queue. +If the INTERRUPT_TYPE field in CQ_RESET_INTERRUPT_CTRL is 0x1, then reading this register clears the completion queue interrupt if asserted. + + 0 + 1 + read-only + + 0 + 0 + + clear + false + + + + CQ_QUEUE_MEM_ADDR_LOW + CQ_QUEUE_MEM_ADDR_LOW + Completion Queue Memory Address Low + 0x108 + 32 + read-only + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Completion Queue Memory Address Low +Returns bits 31:0 of the completion queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + CQ_RESET_INTERRUPT_CTRL + CQ_RESET_INTERRUPT_CTRL + Completion Queue Reset and Interrupt Control + 0x10C + 32 + read-only + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Completion Queue Interrupt Enable +Returns the enable state for completion queue interrupt. +0x0 - Completion Queue interrupt output disabled +0x1 - Completion Queue interrupt output enabled + + 0 + 1 + read-only + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Completion Queue Interrupt Type +Returns the interrupt type for the completion queue. +0x0 - Interrupt for the completion queue is triggered on a write operation to the CQ_TAIL_POINTER register +0x1 - Interrupt for the completion queue is triggered by setting the INTERRUPT field of the CQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-only + + 0 + 0 + + false + + + + CQ_QUEUE_MEM_ADDR_HIGH + CQ_QUEUE_MEM_ADDR_HIGH + Completion Queue Memory Address High + 0x110 + 32 + read-only + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Completion Queue Memory Address High +Returns bits 63:32 of the completion queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + + + S01_AXI + S01_AXI memory map + + S01_AXI_Reg + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S01_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S01_AXI_HIGHADDR + + + + CQ_TAIL_POINTER + CQ_TAIL_POINTER + Completion Queue Tail Pointer Register + 0x000 + 32 + read-write + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Completion Queue Tail Pointer Offset +Configure the Tail Pointer offset for the Completion Queue. +If the INTERRUPT_TYPE field in CQ_RESET_INTERRUPT_CTRL register is 0x0, then a write to this register triggers the completion queue interrupt. +Once triggered, the completion queue interrupt can only be cleared by reading the the CQ_TAIL_POINTER register on the S00_AXI interface. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + CQ_INTERRUPT_REG + CQ_INTERRUPT_REG + Completion Queue Interrupt Register + 0x004 + 32 + read-write + + 0x0 + + + INTERRUPT + INTERRUPT + Completion Queue Interrupt +When set - and while the INTERRUPT_TYPE field is 0x1, INTERRUPT_ENABLE field is 0x1, and RESET field is 0x0 in SQ_RESET_INTERRUPT_CTRL register - triggers an interrupt on the completion queue. +Once triggered, the submission queue interrupt can only be cleared by reading the INTERRUPT_STATUS field of the CQ_INTERRUPT_STATUS register. +0x0 - Do not trigger an interrupt on the completion queue +0x1 - Trigger an interrupt on the completion queue + + 0 + 1 + write-only + + 0 + 0 + + false + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Completion Queue Interrupt Status +Reports the current status of the Completion Queue interrupt. +0x0 - Completion Queue interrupt de-asserted +0x1 - Completion Queue interrupt asserted + + 1 + 1 + read-only + + 0 + 0 + + false + + + + CQ_QUEUE_MEM_ADDR_LOW + CQ_QUEUE_MEM_ADDR_LOW + Completion Queue Memory Address Low + 0x008 + 32 + read-write + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Completion Queue Memory Address Low +Represents bits 31:0 of the completion queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + CQ_RESET_INTERRUPT_CTRL + CQ_RESET_INTERRUPT_CTRL + Completion Queue Reset and Interrupt Control + 0x00C + 32 + read-write + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Completion Queue Interrupt Enable +When set, enables the completion queue interrupt output. +0x0 - Disable completion queue interrupt +0x1 - Enable completion queue interrupt + + 0 + 1 + read-write + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Completion Queue Interrupt Type +Determines the interrupt type in use for the completion queue. +0x0 - Interrupt for the completion queue is triggered on a write operation to the CQ_TAIL_POINTER register +0x1 - Interrupt for the completion queue is triggered by setting the INTERRUPT field of the CQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-write + + 0 + 0 + + false + + + RESET + RESET + Reset +Performs a soft reset of all submission queue and completion queue registers. +0x0 - Do not reset all submission/completion queue registers +0x1 - Reset all submission/completion queue registers +This field is self-clearing once set. + + 31 + 1 + write-only + + 0 + 0 + + false + + + + CQ_QUEUE_MEM_ADDR_HIGH + CQ_QUEUE_MEM_ADDR_HIGH + Completion Queue Memory Address High + 0x010 + 32 + read-write + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Completion Queue Memory Address High +Represents bits 63:32 of the completion queue device memory address. + + 0 + 32 + read-write + + 0 + 0 + + false + + + + SQ_TAIL_POINTER + SQ_TAIL_POINTER + Submission Queue Tail Pointer Register + 0x100 + 32 + read-only + + 0x0 + + + TAIL_POINTER_OFFSET + TAIL_POINTER_OFFSET + Submission Queue Tail Pointer Offset +Returns the tail pointer offset for the submission queue. +If the INTERRUPT_TYPE field in SQ_RESET_INTERRUPT_CTRL is 0x0, then reading this register clears the submission queue interrupt if asserted. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + SQ_INTERRUPT_STATUS + SQ_INTERRUPT_STATUS + Submission Queue Interrupt Status Register + 0x104 + 32 + read-only + + 0x0 + + + INTERRUPT_STATUS + INTERRUPT_STATUS + Submission Queue Interrupt Status +Returns the current state of the interrupt for the submission queue. +If the INTERRUPT_TYPE field in SQ_RESET_INTERRUPT_CTRL is 0x1, then reading this register clears the submission queue interrupt if asserted. + + 0 + 1 + read-only + + 0 + 0 + + clear + false + + + + SQ_QUEUE_MEM_ADDR_LOW + SQ_QUEUE_MEM_ADDR_LOW + Submission Queue Memory Address Low + 0x108 + 32 + read-only + + 0x0 + + + MEM_ADDR_LOW + MEM_ADDR_LOW + Submission Queue Memory Address Low +Returns bits 31:0 of the submission queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + SQ_RESET_INTERRUPT_CTRL + SQ_RESET_INTERRUPT_CTRL + Submission Queue Reset and Interrupt Control + 0x10C + 32 + read-only + + 0x0 + + + INTERRUPT_ENABLE + INTERRUPT_ENABLE + Submission Queue Interrupt Enable +Returns the enable state for submission queue interrupt. +0x0 - Submission Queue interrupt output disabled +0x1 - Submission Queue interrupt output enabled + + 0 + 1 + read-only + + 0 + 0 + + false + + + INTERRUPT_TYPE + INTERRUPT_TYPE + Submission Queue Interrupt Type +Returns the interrupt type for the submission queue. +0x0 - Interrupt for the submission queue is triggered on a write operation to the SQ_TAIL_POINTER register +0x1 - Interrupt for the submission queue is triggered by setting the INTERRUPT field of the SQ_INTERRUPT_REG register to 0x1 + + 1 + 1 + read-only + + 0 + 0 + + false + + + + SQ_QUEUE_MEM_ADDR_HIGH + SQ_QUEUE_MEM_ADDR_HIGH + Submission Queue Memory Address High + 0x110 + 32 + read-only + + 0x0 + + + MEM_ADDR_HIGH + MEM_ADDR_HIGH + Submission Queue Memory Address High +Returns bits 63:32 of the submission queue device memory address. + + 0 + 32 + read-only + + 0 + 0 + + false + + + + + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + viewChecksum + 5bbca8ec + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 1eb13238 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + cmd_queue_v2_0_0 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 7420b60d + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + cmd_queue_v2_0_0 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7420b60d + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 11 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_araddr + + in + + 11 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_awaddr + + in + + 11 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_araddr + + in + + 11 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s01_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq_sq + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq_cq + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_S00_ADDR_WIDTH + 12 + + + C_S01_ADDR_WIDTH + 12 + + + C_S00_AXI_BASEADDR + 0xFFFFFFFF + + + + true + + + + + + C_S00_AXI_HIGHADDR + 0x00000000 + + + + true + + + + + + C_S01_AXI_BASEADDR + 0xFFFFFFFF + + + + true + + + + + + C_S01_AXI_HIGHADDR + 0x00000000 + + + + true + + + + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + cmd_queue_v2_0_0 + + + + xilinx_xpgui_view_fileset + + xgui/cmd_queue_v2_0.tcl + tclSource + XGUI_VERSION_2 + cmd_queue_v2_0_0 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/cmd_queue_v2_0_axi_if.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_reg_if.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi_reg.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_regs.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_top.sv + systemVerilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0.v + verilogSource + USED_IN_ipstatic + cmd_queue_v2_0_0 + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/cmd_queue_v2_0_axi_if.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_reg_if.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi_reg.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_axi.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_regs.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0_top.sv + systemVerilogSource + cmd_queue_v2_0_0 + + + hdl/cmd_queue_v2_0.v + verilogSource + CHECKSUM_1469164e + cmd_queue_v2_0_0 + + + + xilinx_versioninformation_view_fileset + + doc/cmd_queue_v2_0_changelog.txt + text + cmd_queue_v2_0_0 + + + + Generic Command Queue IP to facilitate communications between different devices + + + Component_Name + cmd_queue_v2_0 + + + + + + /Shell_Subsystems + + Generic Command Queue + level_beta + (GENERIC_FAMILY = versal) + http://www.xilinx.com/ + 0 + 2023-10-11T08:38:32Z + + + 2023.1 + + + + + + + + + diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/doc/cmd_queue_v2_0_changelog.txt b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/doc/cmd_queue_v2_0_changelog.txt new file mode 100644 index 00000000..c1422f9a --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/doc/cmd_queue_v2_0_changelog.txt @@ -0,0 +1,28 @@ +2023.1: + * Version 2.0 + * No changes + +2022.2.2: + * Version 2.0 + * No changes + +2022.2.1: + * Version 2.0 + * No changes + +2022.2: + * Version 2.0 + * Port Change: Updated clock/reset port naming to indicate common clock/reset association with S00/S01 + +2022.1.2: + * Version 1.0 + * No changes + +2022.1.1: + * Version 1.0 + * No changes + +2022.1: + * Version 1.0 + * Initial Release + diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0.v b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0.v new file mode 100644 index 00000000..c1e5495f --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0.v @@ -0,0 +1,138 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +module cmd_queue_v2_0_0 #( + parameter integer C_S00_ADDR_WIDTH = 12, + parameter integer C_S01_ADDR_WIDTH = 12, + parameter C_S00_AXI_BASEADDR = 32'hFFFFFFFF, + parameter C_S00_AXI_HIGHADDR = 32'h00000000, + parameter C_S01_AXI_BASEADDR = 32'hFFFFFFFF, + parameter C_S01_AXI_HIGHADDR = 32'h00000000 +) ( + // Clock Ports + input wire aclk, + + // Reset Ports + input wire aresetn, + + // S00_AXI Interface Ports + input wire [C_S00_ADDR_WIDTH-1:0] s00_axi_awaddr, + input wire s00_axi_awvalid, + output wire s00_axi_awready, + input wire [32-1:0] s00_axi_wdata, + input wire [4-1:0] s00_axi_wstrb, + input wire s00_axi_wvalid, + output wire s00_axi_wready, + output wire [2-1:0] s00_axi_bresp, + output wire s00_axi_bvalid, + input wire s00_axi_bready, + input wire [C_S00_ADDR_WIDTH-1:0] s00_axi_araddr, + input wire s00_axi_arvalid, + output wire s00_axi_arready, + output wire [32-1:0] s00_axi_rdata, + output wire [2-1:0] s00_axi_rresp, + output wire s00_axi_rvalid, + input wire s00_axi_rready, + + // S01_AXI Interface Ports + input wire [C_S01_ADDR_WIDTH-1:0] s01_axi_awaddr, + input wire s01_axi_awvalid, + output wire s01_axi_awready, + input wire [32-1:0] s01_axi_wdata, + input wire [4-1:0] s01_axi_wstrb, + input wire s01_axi_wvalid, + output wire s01_axi_wready, + output wire [2-1:0] s01_axi_bresp, + output wire s01_axi_bvalid, + input wire s01_axi_bready, + input wire [C_S01_ADDR_WIDTH-1:0] s01_axi_araddr, + input wire s01_axi_arvalid, + output wire s01_axi_arready, + output wire [32-1:0] s01_axi_rdata, + output wire [2-1:0] s01_axi_rresp, + output wire s01_axi_rvalid, + input wire s01_axi_rready, + + // Interrupt Ports + output wire irq_sq, + output wire irq_cq +); + +// -------------------------------------------------------- +// GCQ Top Level Instantiation +// -------------------------------------------------------- +cmd_queue_v2_0_0_top #( + .C_S00_ADDR_WIDTH(C_S00_ADDR_WIDTH), + .C_S01_ADDR_WIDTH(C_S01_ADDR_WIDTH) +) cmd_queue_top_inst ( + // Clocks + .aclk(aclk), + + // Resets + .aresetn(aresetn), + + // S00_AXI Interface + .s00_axi_awaddr(s00_axi_awaddr), + .s00_axi_awvalid(s00_axi_awvalid), + .s00_axi_awready(s00_axi_awready), + .s00_axi_wdata(s00_axi_wdata), + .s00_axi_wstrb(s00_axi_wstrb), + .s00_axi_wvalid(s00_axi_wvalid), + .s00_axi_wready(s00_axi_wready), + .s00_axi_bresp(s00_axi_bresp), + .s00_axi_bvalid(s00_axi_bvalid), + .s00_axi_bready(s00_axi_bready), + .s00_axi_araddr(s00_axi_araddr), + .s00_axi_arvalid(s00_axi_arvalid), + .s00_axi_arready(s00_axi_arready), + .s00_axi_rdata(s00_axi_rdata), + .s00_axi_rresp(s00_axi_rresp), + .s00_axi_rvalid(s00_axi_rvalid), + .s00_axi_rready(s00_axi_rready), + + // S01_AXI Interface + .s01_axi_awaddr(s01_axi_awaddr), + .s01_axi_awvalid(s01_axi_awvalid), + .s01_axi_awready(s01_axi_awready), + .s01_axi_wdata(s01_axi_wdata), + .s01_axi_wstrb(s01_axi_wstrb), + .s01_axi_wvalid(s01_axi_wvalid), + .s01_axi_wready(s01_axi_wready), + .s01_axi_bresp(s01_axi_bresp), + .s01_axi_bvalid(s01_axi_bvalid), + .s01_axi_bready(s01_axi_bready), + .s01_axi_araddr(s01_axi_araddr), + .s01_axi_arvalid(s01_axi_arvalid), + .s01_axi_arready(s01_axi_arready), + .s01_axi_rdata(s01_axi_rdata), + .s01_axi_rresp(s01_axi_rresp), + .s01_axi_rvalid(s01_axi_rvalid), + .s01_axi_rready(s01_axi_rready), + + // Interrupts + .irq_sq(irq_sq), + .irq_cq(irq_cq) + +); + +endmodule diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi.sv b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi.sv new file mode 100644 index 00000000..bddae6e6 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi.sv @@ -0,0 +1,167 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_axi #( + parameter int C_S00_ADDR_WIDTH = 12, // Address width of SQ AXI and Reg interfaces + parameter int C_S01_ADDR_WIDTH = 12, // Address Width of CQ AXI and Reg interfaces + parameter int C_S00_DATA_WIDTH = 32, // Data width of SQ AXI and Reg interfaces + parameter int C_S01_DATA_WIDTH = 32 // Data width of CQ AXI and Reg interfaces +) ( + // AXI4-Lite Subordinate Interface + cmd_queue_v2_0_0_axi_if.sub sq_axi_if, + cmd_queue_v2_0_0_axi_if.sub cq_axi_if, + + // Manager Register Interfaces + cmd_queue_v2_0_0_reg_if.man sq_reg_if, + cmd_queue_v2_0_0_reg_if.man cq_reg_if, + + // Clock/Reset + input logic aclk, + input logic aresetn +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- + +logic sq_reg_rd_valid; +logic [C_S00_ADDR_WIDTH-1:0] sq_reg_rd_addr; +logic sq_reg_rd_done; +logic [1:0] sq_reg_rd_resp; +logic [C_S00_DATA_WIDTH-1:0] sq_reg_rd_data; +logic sq_reg_wr_valid; +logic [C_S00_ADDR_WIDTH-1:0] sq_reg_wr_addr; +logic [(C_S00_DATA_WIDTH/8)-1:0] sq_reg_wr_be; +logic [C_S00_DATA_WIDTH-1:0] sq_reg_wr_data; +logic sq_reg_wr_done; +logic [1:0] sq_reg_wr_resp; + +logic cq_reg_rd_valid; +logic [C_S01_ADDR_WIDTH-1:0] cq_reg_rd_addr; +logic cq_reg_rd_done; +logic [1:0] cq_reg_rd_resp; +logic [C_S01_DATA_WIDTH-1:0] cq_reg_rd_data; +logic cq_reg_wr_valid; +logic [C_S01_ADDR_WIDTH-1:0] cq_reg_wr_addr; +logic [(C_S01_DATA_WIDTH/8)-1:0] cq_reg_wr_be; +logic [C_S01_DATA_WIDTH-1:0] cq_reg_wr_data; +logic cq_reg_wr_done; +logic [1:0] cq_reg_wr_resp; + +// ======================================================== + +// -------------------------------------------------------- +// SQ AXI Register Interface Module Instantiation + +cmd_queue_v2_0_0_axi_reg #( + .C_ADDR_WIDTH(C_S00_ADDR_WIDTH), + .C_DATA_WIDTH(C_S00_DATA_WIDTH) +) sq_axi_reg_inst ( + .axi_if(sq_axi_if), + .aclk, + .aresetn, + .reg_rd_valid_o(sq_reg_rd_valid), + .reg_rd_addr_o(sq_reg_rd_addr), + .reg_rd_done_i(sq_reg_rd_done), + .reg_rd_resp_i(sq_reg_rd_resp), + .reg_rd_data_i(sq_reg_rd_data), + .reg_wr_valid_o(sq_reg_wr_valid), + .reg_wr_addr_o(sq_reg_wr_addr), + .reg_wr_be_o(sq_reg_wr_be), + .reg_wr_data_o(sq_reg_wr_data), + .reg_wr_done_i(sq_reg_wr_done), + .reg_wr_resp_i(sq_reg_wr_resp) +); + +// -------------------------------------------------------- +// CQ AXI Register Interface Module Instantiation + +cmd_queue_v2_0_0_axi_reg #( + .C_ADDR_WIDTH(C_S01_ADDR_WIDTH), + .C_DATA_WIDTH(C_S01_DATA_WIDTH) +) cq_axi_reg_inst ( + .axi_if(cq_axi_if), + .aclk, + .aresetn, + .reg_rd_valid_o(cq_reg_rd_valid), + .reg_rd_addr_o(cq_reg_rd_addr), + .reg_rd_done_i(cq_reg_rd_done), + .reg_rd_resp_i(cq_reg_rd_resp), + .reg_rd_data_i(cq_reg_rd_data), + .reg_wr_valid_o(cq_reg_wr_valid), + .reg_wr_addr_o(cq_reg_wr_addr), + .reg_wr_be_o(cq_reg_wr_be), + .reg_wr_data_o(cq_reg_wr_data), + .reg_wr_done_i(cq_reg_wr_done), + .reg_wr_resp_i(cq_reg_wr_resp) +); + +// -------------------------------------------------------- +// Register Interface assignments + +// SQ Register Interface +assign sq_reg_if.reg_rd_valid = sq_reg_rd_valid; +assign sq_reg_if.reg_rd_addr = sq_reg_rd_addr; +assign sq_reg_rd_done = sq_reg_if.reg_rd_done; +assign sq_reg_rd_resp = sq_reg_if.reg_rd_resp; +assign sq_reg_rd_data = sq_reg_if.reg_rd_data; + +assign sq_reg_if.reg_wr_valid = sq_reg_wr_valid; +assign sq_reg_if.reg_wr_addr = sq_reg_wr_addr; +assign sq_reg_if.reg_wr_be = sq_reg_wr_be; +assign sq_reg_if.reg_wr_data = sq_reg_wr_data; +assign sq_reg_wr_done = sq_reg_if.reg_wr_done; +assign sq_reg_wr_resp = sq_reg_if.reg_wr_resp; + +// CQ Register Interface +assign cq_reg_if.reg_rd_valid = cq_reg_rd_valid; +assign cq_reg_if.reg_rd_addr = cq_reg_rd_addr; +assign cq_reg_rd_done = cq_reg_if.reg_rd_done; +assign cq_reg_rd_resp = cq_reg_if.reg_rd_resp; +assign cq_reg_rd_data = cq_reg_if.reg_rd_data; + +assign cq_reg_if.reg_wr_valid = cq_reg_wr_valid; +assign cq_reg_if.reg_wr_addr = cq_reg_wr_addr; +assign cq_reg_if.reg_wr_be = cq_reg_wr_be; +assign cq_reg_if.reg_wr_data = cq_reg_wr_data; +assign cq_reg_wr_done = cq_reg_if.reg_wr_done; +assign cq_reg_wr_resp = cq_reg_if.reg_wr_resp; + +endmodule : cmd_queue_v2_0_0_axi diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_if.sv b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_if.sv new file mode 100644 index 00000000..a5e858cf --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_if.sv @@ -0,0 +1,134 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +interface cmd_queue_v2_0_0_axi_if #( + parameter int C_DATA_WIDTH = 32, + parameter int C_ADDR_WIDTH = 32 +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// AXI4-Lite Interface Signals +// -------------------------------------------------------- + +// Write Address Channel +logic [C_ADDR_WIDTH-1:0] awaddr; +logic awvalid; +logic awready; + +// Write Data Channel +logic [C_DATA_WIDTH-1:0] wdata; +logic [(C_DATA_WIDTH/8)-1:0] wstrb; +logic wvalid; +logic wready; + +// Write Response Channel +logic bvalid; +logic bready; +logic [1:0] bresp; + +// Read Address Channel +logic [C_ADDR_WIDTH-1:0] araddr; +logic arvalid; +logic arready; + +// Read Data Channel +logic [C_DATA_WIDTH-1:0] rdata; +logic [1:0] rresp; +logic rvalid; +logic rready; + +// -------------------------------------------------------- +// AXI4-Lite Manager Interface +// -------------------------------------------------------- +modport man ( + output awaddr, + output awvalid, + input awready, + output wdata, + output wstrb, + output wvalid, + input wready, + input bvalid, + input bresp, + output bready, + output araddr, + output arvalid, + input arready, + input rdata, + input rresp, + input rvalid, + output rready +); + +// -------------------------------------------------------- +// AXI4-Lite Subordinate Interface +// -------------------------------------------------------- +modport sub ( + input awaddr, + input awvalid, + output awready, + input wdata, + input wstrb, + input wvalid, + output wready, + output bvalid, + output bresp, + input bready, + input araddr, + input arvalid, + output arready, + output rdata, + output rresp, + output rvalid, + input rready +); + +// -------------------------------------------------------- +// AXI4-Lite Monitor Interface +// -------------------------------------------------------- +modport mon ( + input awaddr, + input awvalid, + input awready, + input wdata, + input wstrb, + input wvalid, + input wready, + input bvalid, + input bresp, + input bready, + input araddr, + input arvalid, + input arready, + input rdata, + input rresp, + input rvalid, + input rready +); + +endinterface : cmd_queue_v2_0_0_axi_if diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_reg.sv b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_reg.sv new file mode 100644 index 00000000..f883e475 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_axi_reg.sv @@ -0,0 +1,168 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_axi_reg #( + parameter int C_DATA_WIDTH = 32, // Data width + parameter int C_ADDR_WIDTH = 32 // Address width +) ( + // AXI4-Lite Subordinate Interface + cmd_queue_v2_0_0_axi_if.sub axi_if, + + // Clock/Reset + input logic aclk, + input logic aresetn, + + // Register Read Interface + output logic reg_rd_valid_o, + output logic [C_ADDR_WIDTH-1:0] reg_rd_addr_o, + input logic reg_rd_done_i, + input logic [1:0] reg_rd_resp_i, + input logic [C_DATA_WIDTH-1:0] reg_rd_data_i, + + // Register Write Interface + output logic reg_wr_valid_o, + output logic [C_ADDR_WIDTH-1:0] reg_wr_addr_o, + output logic [(C_DATA_WIDTH/8)-1:0] reg_wr_be_o, + output logic [C_DATA_WIDTH-1:0] reg_wr_data_o, + input logic reg_wr_done_i, + input logic [1:0] reg_wr_resp_i +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- +logic wr_rdy; +logic wr_wait; +logic rd_wait; + +// ======================================================== + +// AXI Write +always_ff @(posedge aclk) begin + if (!aresetn) begin + wr_rdy <= '0; + wr_wait <= '0; + reg_wr_valid_o <= '0; + reg_wr_addr_o <= '0; + reg_wr_be_o <= '0; + reg_wr_data_o <= '0; + axi_if.bvalid <= '0; + axi_if.bresp <= '0; + end else begin + // Defaults + wr_rdy <= '0; + wr_wait <= wr_wait; + reg_wr_valid_o <= '0; + reg_wr_addr_o <= reg_wr_addr_o; + reg_wr_be_o <= reg_wr_be_o; + reg_wr_data_o <= reg_wr_data_o; + axi_if.bvalid <= '0; + axi_if.bresp <= '0; + // coverage off -item c 1 -feccondrow 4 + if (!wr_wait && !wr_rdy && axi_if.awvalid && axi_if.wvalid) begin + // coverage on + wr_rdy <= 1'b1; + wr_wait <= 1'b1; + reg_wr_valid_o <= 1'b1; + reg_wr_addr_o <= axi_if.awaddr; + reg_wr_be_o <= axi_if.wstrb; + reg_wr_data_o <= axi_if.wdata; + end else if (reg_wr_done_i) begin + axi_if.bvalid <= 1'b1; + axi_if.bresp <= reg_wr_resp_i; + reg_wr_addr_o <= '0; + reg_wr_be_o <= '0; + reg_wr_data_o <= '0; + end else if (axi_if.bvalid) begin + if (!axi_if.bready) begin + axi_if.bvalid <= axi_if.bvalid; + axi_if.bresp <= axi_if.bresp; + end else begin + wr_wait <= 1'b0; + end + end + end +end +assign axi_if.awready = wr_rdy; +assign axi_if.wready = wr_rdy; + +// AXI Read +always_ff @(posedge aclk) begin + if (!aresetn) begin + axi_if.arready <= '0; + rd_wait <= '0; + reg_rd_valid_o <= '0; + reg_rd_addr_o <= '0; + axi_if.rvalid <= '0; + axi_if.rresp <= '0; + axi_if.rdata <= '0; + end else begin + // Defaults + axi_if.arready <= '0; + rd_wait <= rd_wait; + reg_rd_valid_o <= '0; + reg_rd_addr_o <= '0; + axi_if.rvalid <= '0; + axi_if.rresp <= '0; + axi_if.rdata <= '0; + // coverage off -item c 1 -feccondrow 4 + if (!rd_wait && !axi_if.arready && axi_if.arvalid) begin + // coverage on + axi_if.arready <= 1'b1; + rd_wait <= 1'b1; + reg_rd_valid_o <= 1'b1; + reg_rd_addr_o <= axi_if.araddr; + end else if (reg_rd_done_i) begin + axi_if.rvalid <= 1'b1; + axi_if.rresp <= reg_rd_resp_i; + axi_if.rdata <= reg_rd_data_i; + end else if (axi_if.rvalid) begin + if (!axi_if.rready) begin + axi_if.rvalid <= axi_if.rvalid; + axi_if.rresp <= axi_if.rresp; + axi_if.rdata <= axi_if.rdata; + end else begin + rd_wait <= 1'b0; + end + end + end +end + +endmodule : cmd_queue_v2_0_0_axi_reg diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_reg_if.sv b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_reg_if.sv new file mode 100644 index 00000000..dec51c56 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_reg_if.sv @@ -0,0 +1,89 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +interface cmd_queue_v2_0_0_reg_if #( + parameter int C_DATA_WIDTH = 32, + parameter int C_ADDR_WIDTH = 32 +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Register Read Interface +// -------------------------------------------------------- + +logic reg_rd_valid; +logic [C_ADDR_WIDTH-1:0] reg_rd_addr; +logic reg_rd_done; +logic [1:0] reg_rd_resp; +logic [C_DATA_WIDTH-1:0] reg_rd_data; + +// -------------------------------------------------------- +// Register Write Interface +// -------------------------------------------------------- + +logic reg_wr_valid; +logic [C_ADDR_WIDTH-1:0] reg_wr_addr; +logic [(C_DATA_WIDTH/8)-1:0] reg_wr_be; +logic [C_DATA_WIDTH-1:0] reg_wr_data; +logic reg_wr_done; +logic [1:0] reg_wr_resp; + +// -------------------------------------------------------- +// Register Manager Interface +// -------------------------------------------------------- +modport man ( + output reg_rd_valid, + output reg_rd_addr, + input reg_rd_done, + input reg_rd_resp, + input reg_rd_data, + output reg_wr_valid, + output reg_wr_addr, + output reg_wr_be, + output reg_wr_data, + input reg_wr_done, + input reg_wr_resp +); + +// -------------------------------------------------------- +// Register Subordinate Interface +// -------------------------------------------------------- +modport sub ( + input reg_rd_valid, + input reg_rd_addr, + output reg_rd_done, + output reg_rd_resp, + output reg_rd_data, + input reg_wr_valid, + input reg_wr_addr, + input reg_wr_be, + input reg_wr_data, + output reg_wr_done, + output reg_wr_resp +); + +endinterface : cmd_queue_v2_0_0_reg_if diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_regs.sv b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_regs.sv new file mode 100644 index 00000000..bc94bdd8 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_regs.sv @@ -0,0 +1,450 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_regs +( + // Register Interface + cmd_queue_v2_0_0_reg_if.sub sq_reg_if, + cmd_queue_v2_0_0_reg_if.sub cq_reg_if, + + // Clock/Reset + input logic aclk, + input logic aresetn, + + // Interrupts + output logic irq_sq, + output logic irq_cq +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- +localparam int C_SQ_ADDR_WIDTH = $bits(sq_reg_if.reg_wr_addr); +localparam int C_CQ_ADDR_WIDTH = $bits(cq_reg_if.reg_wr_addr); +localparam int IRQ_SR_WIDTH = 2; + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- + +logic [31:0] sq_tail_pntr; +logic sq_irq_tail_pntr; +logic sq_irq_tail_pntr_isr; +logic sq_irq_tail_pntr_clr; +logic sq_irq_reg; +logic sq_irq_reg_isr; +logic sq_irq_reg_clr; +logic sq_irq_en; +logic [IRQ_SR_WIDTH-1:0] sq_irq_en_sr; +logic sq_irq_type; +logic sq_rst; +logic [31:0] sq_mem_addr_lo; +logic [31:0] sq_mem_addr_hi; + +logic [31:0] cq_tail_pntr; +logic cq_irq_tail_pntr; +logic cq_irq_tail_pntr_isr; +logic cq_irq_tail_pntr_clr; +logic cq_irq_reg; +logic cq_irq_reg_isr; +logic cq_irq_reg_clr; +logic cq_irq_en; +logic [IRQ_SR_WIDTH-1:0] cq_irq_en_sr; +logic cq_irq_type; +logic cq_rst; +logic [31:0] cq_mem_addr_lo; +logic [31:0] cq_mem_addr_hi; + +logic soft_rst; + +// ======================================================== + +// Assert the soft reset when either SQ/CQ resets are set +assign soft_rst = sq_rst | cq_rst; + +// ======================================================== + +// Interrupt Generation +always_ff @(posedge aclk) begin + if (!aresetn) begin + irq_sq <= '0; + sq_irq_en_sr <= '0; + sq_irq_reg_isr <= '0; + sq_irq_tail_pntr_isr <= '0; + irq_cq <= '0; + cq_irq_en_sr <= '0; + cq_irq_reg_isr <= '0; + cq_irq_tail_pntr_isr <= '0; + end else begin + // Defaults + irq_sq <= '0; + sq_irq_en_sr <= {sq_irq_en_sr[IRQ_SR_WIDTH-2:0],1'b1}; + irq_cq <= '0; + cq_irq_en_sr <= {cq_irq_en_sr[IRQ_SR_WIDTH-2:0],1'b1}; + + // SQ Interrupt Generation + + // SQ Register Interrupt - Asserted when the Interrupt Register is written + + if ((sq_irq_reg_clr && sq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + sq_irq_reg_isr <= '0; + sq_irq_en_sr <= '0; + end + + if (sq_irq_type && sq_irq_reg) begin + // Assert the SQ register interrupt when the interrupt register is written + sq_irq_reg_isr <= '1; + end else if (!sq_irq_type) begin + // If the interrupt type is configured for the tail pointer, then clear any pending register + // interrupts that get asserted + sq_irq_reg_isr <= '0; + end + + // SQ Tail Pointer Interrupt - Asserted when the Tail Pointer register is written + + if ((sq_irq_tail_pntr_clr && !sq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + sq_irq_tail_pntr_isr <= '0; + sq_irq_en_sr <= '0; + end + + if (!sq_irq_type && sq_irq_tail_pntr) begin + // Assert the interrupt when the tail pointer register is written + sq_irq_tail_pntr_isr <= '1; + end else if (sq_irq_type) begin + // If the interrupt type is configured for register interrupt, then clear any pending tail + // pointer interrupts that get asserted + sq_irq_tail_pntr_isr <= '0; + end + + if (sq_irq_en) begin + // Assert the SQ interrupt output when enabled and either the register or tail pointer + // interrupts are set. The MSB of the shift register ensures that the interrupt de-asserts + // in the event of a coincident interrupt set/clear that would prevent a new rising-edge + irq_sq <= (sq_irq_reg_isr | sq_irq_tail_pntr_isr) & sq_irq_en_sr[IRQ_SR_WIDTH-1]; + end + + // ======================================================== + + // CQ Interrupt Generation + + // CQ Register Interrupt - Asserted when the Interrupt Register is written + + if ((cq_irq_reg_clr && cq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + cq_irq_reg_isr <= '0; + cq_irq_en_sr <= '0; + end + + if (cq_irq_type && cq_irq_reg) begin + // Assert the CQ register interrupt when the interrupt register is written + cq_irq_reg_isr <= '1; + end else if (!cq_irq_type) begin + // If the interrupt type is configured for the tail pointer, then clear any pending register + // interrupts that get asserted + cq_irq_reg_isr <= '0; + end + + // CQ Tail Pointer Interrupt - Asserted when the Tail Pointer register is written + + if ((cq_irq_tail_pntr_clr && !cq_irq_type) || soft_rst) begin + // Clear the register interrupt when the interrupt status register is read or on a soft reset + cq_irq_tail_pntr_isr <= '0; + cq_irq_en_sr <= '0; + end + + if (!cq_irq_type && cq_irq_tail_pntr) begin + // Assert the interrupt when the tail pointer register is written + cq_irq_tail_pntr_isr <= '1; + end else if (cq_irq_type) begin + // If the interrupt type is configured for register interrupt, then clear any pending tail + // pointer interrupts that get asserted + cq_irq_tail_pntr_isr <= '0; + end + + if (cq_irq_en) begin + // Assert the CQ interrupt output when enabled and either the register or tail pointer + // interrupts are set. The MSB of the shift register ensures that the interrupt de-asserts + // in the event of a coincident interrupt set/clear that would prevent a new rising-edge + irq_cq <= (cq_irq_reg_isr | cq_irq_tail_pntr_isr) & cq_irq_en_sr[IRQ_SR_WIDTH-1]; + end + end +end + +// ======================================================== + +// Producer Register Interface - Write +always_ff @(posedge aclk) begin + if (!aresetn) begin + sq_tail_pntr <= '0; + sq_irq_tail_pntr <= '0; + sq_irq_reg <= '0; + sq_irq_en <= '0; + sq_irq_type <= '0; + sq_mem_addr_hi <= '0; + sq_mem_addr_lo <= '0; + sq_rst <= '0; + sq_reg_if.reg_wr_done <= '0; + end else begin + // Defaults + sq_reg_if.reg_wr_done <= '0; + sq_rst <= '0; + sq_irq_tail_pntr <= '0; + sq_irq_reg <= '0; + + if (sq_reg_if.reg_wr_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|sq_reg_if.reg_wr_addr[C_SQ_ADDR_WIDTH-1:9])) begin + case (sq_reg_if.reg_wr_addr[8:0]) inside + 9'b0000000??: // SQ Tail Pointer - 0x000 + begin + sq_tail_pntr <= sq_reg_if.reg_wr_data; + sq_irq_tail_pntr <= '1; + end + 9'b0000001??: // SQ IRQ Control - 0x004 + sq_irq_reg <= sq_reg_if.reg_wr_data[0]; + 9'b0000010??: // SQ Queue Memory Address Low - 0x008 + sq_mem_addr_lo <= sq_reg_if.reg_wr_data; + 9'b0000011??: // SQ Reset IRQ Control - 0x00C + begin + sq_irq_en <= sq_reg_if.reg_wr_data[0]; + sq_irq_type <= sq_reg_if.reg_wr_data[1]; + sq_rst <= sq_reg_if.reg_wr_data[31]; + end + 9'b0000100??: // SQ Queue Memory Address High - 0x010 + sq_mem_addr_hi <= sq_reg_if.reg_wr_data; + endcase + end + // Signal write done + sq_reg_if.reg_wr_done <= 1'b1; + end + + // Clear the registers on a soft reset + if (soft_rst) begin + sq_tail_pntr <= '0; + sq_irq_en <= '0; + sq_irq_type <= '0; + sq_mem_addr_hi <= '0; + sq_mem_addr_lo <= '0; + end + end +end + +// Always respond with OKAY to writes +assign sq_reg_if.reg_wr_resp = '0; + +// ======================================================== + +// Producer Register Interface - Read +always_ff @(posedge aclk) begin + //Defaults + sq_reg_if.reg_rd_data <= '0; + sq_reg_if.reg_rd_done <= '0; + cq_irq_reg_clr <= '0; + cq_irq_tail_pntr_clr <= '0; + + if (sq_reg_if.reg_rd_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|sq_reg_if.reg_rd_addr[C_SQ_ADDR_WIDTH-1:9])) begin + case (sq_reg_if.reg_rd_addr[8:0]) inside + 9'b0000000??: // SQ Tail Pointer - 0x000 + sq_reg_if.reg_rd_data <= sq_tail_pntr; + 9'b0000001??: // SQ IRQ Control - 0x004 + sq_reg_if.reg_rd_data[1] <= sq_irq_reg_isr | sq_irq_tail_pntr_isr; + 9'b0000010??: // SQ Queue Memory Address Low - 0x008 + sq_reg_if.reg_rd_data <= sq_mem_addr_lo; + 9'b0000011??: // SQ Reset IRQ Control - 0x00C + begin + sq_reg_if.reg_rd_data[1] <= sq_irq_type; + sq_reg_if.reg_rd_data[0] <= sq_irq_en; + end + 9'b0000100??: // SQ Queue Memory Address High - 0x010 + sq_reg_if.reg_rd_data <= sq_mem_addr_hi; + 9'b1000000??: // CQ Tail Pointer - 0x100 + begin + sq_reg_if.reg_rd_data <= cq_tail_pntr; + cq_irq_tail_pntr_clr <= '1; + end + 9'b1000001??: // CQ IRQ Status - 0x104 + begin + sq_reg_if.reg_rd_data[0] <= cq_irq_reg_isr; + cq_irq_reg_clr <= '1; + end + 9'b1000010??: // CQ Queue Memory Address Low - 0x108 + sq_reg_if.reg_rd_data <= cq_mem_addr_lo; + 9'b1000011??: // CQ Reset IRQ Control - 0x10C + begin + sq_reg_if.reg_rd_data[1] <= cq_irq_type; + sq_reg_if.reg_rd_data[0] <= cq_irq_en; + end + 9'b1000100??: // CQ Queue Memory Address High - 0x110 + sq_reg_if.reg_rd_data <= cq_mem_addr_hi; + default: + sq_reg_if.reg_rd_data <= '0; + endcase + end + // Signal read done + sq_reg_if.reg_rd_done <= 1'b1; + end +end + +// Always respond with OKAY to reads +assign sq_reg_if.reg_rd_resp = '0; + +// ======================================================== + +// Consumer Register Interface - Write +always_ff @(posedge aclk) begin + if (!aresetn) begin + cq_tail_pntr <= '0; + cq_irq_tail_pntr <= '0; + cq_irq_reg <= '0; + cq_irq_en <= '0; + cq_irq_type <= '0; + cq_mem_addr_hi <= '0; + cq_mem_addr_lo <= '0; + cq_rst <= '0; + cq_reg_if.reg_wr_done <= '0; + end else begin + // Defaults + cq_reg_if.reg_wr_done <= '0; + cq_rst <= '0; + cq_irq_tail_pntr <= '0; + cq_irq_reg <= '0; + + if (cq_reg_if.reg_wr_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|cq_reg_if.reg_wr_addr[C_CQ_ADDR_WIDTH-1:9])) begin + case (cq_reg_if.reg_wr_addr[8:0]) inside + 9'b0000000??: // CQ Tail Pointer - 0x000 + begin + cq_tail_pntr <= cq_reg_if.reg_wr_data; + cq_irq_tail_pntr <= '1; + end + 9'b0000001??: // CQ IRQ Control - 0x004 + cq_irq_reg <= cq_reg_if.reg_wr_data[0]; + 9'b0000010??: // CQ Queue Memory Address Low - 0x008 + cq_mem_addr_lo <= cq_reg_if.reg_wr_data; + 9'b0000011??: // CQ Reset IRQ Control - 0x00C + begin + cq_irq_en <= cq_reg_if.reg_wr_data[0]; + cq_irq_type <= cq_reg_if.reg_wr_data[1]; + cq_rst <= cq_reg_if.reg_wr_data[31]; + end + 9'b0000100??: // CQ Queue Memory Address High - 0x010 + cq_mem_addr_hi <= cq_reg_if.reg_wr_data; + endcase + end + // Signal write done + cq_reg_if.reg_wr_done <= 1'b1; + end + + // Clear the registers on a soft reset + if (soft_rst) begin + cq_tail_pntr <= '0; + cq_irq_en <= '0; + cq_irq_type <= '0; + cq_mem_addr_hi <= '0; + cq_mem_addr_lo <= '0; + end + end +end + +// Always respond with OKAY to writes +assign cq_reg_if.reg_wr_resp = '0; + +// ======================================================== + +// Consumer Register Interface - Read +always_ff @(posedge aclk) begin + //Defaults + cq_reg_if.reg_rd_data <= '0; + cq_reg_if.reg_rd_done <= '0; + sq_irq_reg_clr <= '0; + sq_irq_tail_pntr_clr <= '0; + + if (cq_reg_if.reg_rd_valid) begin + // Exclude unused address space to prevent aliasing + if (!(|cq_reg_if.reg_rd_addr[C_CQ_ADDR_WIDTH-1:9])) begin + case (cq_reg_if.reg_rd_addr[8:0]) inside + 9'b0000000??: // CQ Tail Pointer - 0x000 + cq_reg_if.reg_rd_data <= cq_tail_pntr; + 9'b0000001??: // CQ IRQ Control - 0x004 + cq_reg_if.reg_rd_data[1] <= cq_irq_reg_isr | cq_irq_tail_pntr_isr; + 9'b0000010??: // CQ Queue Memory Address Low - 0x008 + cq_reg_if.reg_rd_data <= cq_mem_addr_lo; + 9'b0000011??: // CQ Reset IRQ Control - 0x00C + begin + cq_reg_if.reg_rd_data[1] <= cq_irq_type; + cq_reg_if.reg_rd_data[0] <= cq_irq_en; + end + 9'b0000100??: // CQ Queue Memory Address High - 0x010 + cq_reg_if.reg_rd_data <= cq_mem_addr_hi; + 9'b1000000??: // SQ Tail Pointer - 0x100 + begin + cq_reg_if.reg_rd_data <= sq_tail_pntr; + sq_irq_tail_pntr_clr <= '1; + end + 9'b1000001??: // SQ IRQ Status - 0x104 + begin + cq_reg_if.reg_rd_data[0] <= sq_irq_reg_isr; + sq_irq_reg_clr <= '1; + end + 9'b1000010??: // SQ Queue Memory Address Low - 0x108 + cq_reg_if.reg_rd_data <= sq_mem_addr_lo; + 9'b1000011??: // SQ Reset IRQ Control - 0x10C + begin + cq_reg_if.reg_rd_data[1] <= sq_irq_type; + cq_reg_if.reg_rd_data[0] <= sq_irq_en; + end + 9'b1000100??: // SQ Queue Memory Address High - 0x110 + cq_reg_if.reg_rd_data <= sq_mem_addr_hi; + default: + cq_reg_if.reg_rd_data <= '0; + endcase + end + // Signal read done + cq_reg_if.reg_rd_done <= 1'b1; + end +end + +// Always respond with OKAY to reads +assign cq_reg_if.reg_rd_resp = '0; + +// ======================================================== + +endmodule : cmd_queue_v2_0_0_regs diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_top.sv b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_top.sv new file mode 100644 index 00000000..4fe9481b --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/hdl/cmd_queue_v2_0_top.sv @@ -0,0 +1,181 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////// + +module cmd_queue_v2_0_0_top #( + parameter int C_S00_ADDR_WIDTH = 12, + parameter int C_S01_ADDR_WIDTH = 12 +) ( + // Clock Ports + input logic aclk, + + // Reset Ports + input logic aresetn, + + // S00_AXI Interface Ports + input logic [C_S00_ADDR_WIDTH-1:0] s00_axi_awaddr, + input logic s00_axi_awvalid, + output logic s00_axi_awready, + input logic [32-1:0] s00_axi_wdata, + input logic [4-1:0] s00_axi_wstrb, + input logic s00_axi_wvalid, + output logic s00_axi_wready, + output logic [2-1:0] s00_axi_bresp, + output logic s00_axi_bvalid, + input logic s00_axi_bready, + input logic [C_S00_ADDR_WIDTH-1:0] s00_axi_araddr, + input logic s00_axi_arvalid, + output logic s00_axi_arready, + output logic [32-1:0] s00_axi_rdata, + output logic [2-1:0] s00_axi_rresp, + output logic s00_axi_rvalid, + input logic s00_axi_rready, + + // S01_AXI Interface Ports + input logic [C_S01_ADDR_WIDTH-1:0] s01_axi_awaddr, + input logic s01_axi_awvalid, + output logic s01_axi_awready, + input logic [32-1:0] s01_axi_wdata, + input logic [4-1:0] s01_axi_wstrb, + input logic s01_axi_wvalid, + output logic s01_axi_wready, + output logic [2-1:0] s01_axi_bresp, + output logic s01_axi_bvalid, + input logic s01_axi_bready, + input logic [C_S01_ADDR_WIDTH-1:0] s01_axi_araddr, + input logic s01_axi_arvalid, + output logic s01_axi_arready, + output logic [32-1:0] s01_axi_rdata, + output logic [2-1:0] s01_axi_rresp, + output logic s01_axi_rvalid, + input logic s01_axi_rready, + + // Interrupt Ports + output logic irq_sq, + output logic irq_cq +); + +// -------------------------------------------------------- +// Time Units/Precision +// -------------------------------------------------------- +// synthesis translate_off +timeunit 1ns/1ps; +// synthesis translate_on + +// -------------------------------------------------------- +// Package Import +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Parameters +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Types +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Functions +// -------------------------------------------------------- + +// -------------------------------------------------------- +// Variables/Nets +// -------------------------------------------------------- + +// ======================================================== + +// AXI4-Lite Interface Instantiations +cmd_queue_v2_0_0_axi_if #(.C_ADDR_WIDTH(C_S00_ADDR_WIDTH)) sq_axi_if(); +cmd_queue_v2_0_0_axi_if #(.C_ADDR_WIDTH(C_S01_ADDR_WIDTH)) cq_axi_if(); + +// Producer (SQ) AXI-Lite Interface/port connections +assign sq_axi_if.awaddr = s00_axi_awaddr; +assign sq_axi_if.awvalid = s00_axi_awvalid; +assign s00_axi_awready = sq_axi_if.awready; +assign sq_axi_if.wdata = s00_axi_wdata; +assign sq_axi_if.wstrb = s00_axi_wstrb; +assign sq_axi_if.wvalid = s00_axi_wvalid; +assign s00_axi_wready = sq_axi_if.wready; +assign s00_axi_bresp = sq_axi_if.bresp; +assign s00_axi_bvalid = sq_axi_if.bvalid; +assign sq_axi_if.bready = s00_axi_bready; +assign sq_axi_if.araddr = s00_axi_araddr; +assign sq_axi_if.arvalid = s00_axi_arvalid; +assign s00_axi_arready = sq_axi_if.arready; +assign s00_axi_rdata = sq_axi_if.rdata; +assign s00_axi_rresp = sq_axi_if.rresp; +assign s00_axi_rvalid = sq_axi_if.rvalid; +assign sq_axi_if.rready = s00_axi_rready; + +// Consumer (CQ) AXI-Lite Interface/port connections +assign cq_axi_if.awaddr = s01_axi_awaddr; +assign cq_axi_if.awvalid = s01_axi_awvalid; +assign s01_axi_awready = cq_axi_if.awready; +assign cq_axi_if.wdata = s01_axi_wdata; +assign cq_axi_if.wstrb = s01_axi_wstrb; +assign cq_axi_if.wvalid = s01_axi_wvalid; +assign s01_axi_wready = cq_axi_if.wready; +assign s01_axi_bresp = cq_axi_if.bresp; +assign s01_axi_bvalid = cq_axi_if.bvalid; +assign cq_axi_if.bready = s01_axi_bready; +assign cq_axi_if.araddr = s01_axi_araddr; +assign cq_axi_if.arvalid = s01_axi_arvalid; +assign s01_axi_arready = cq_axi_if.arready; +assign s01_axi_rdata = cq_axi_if.rdata; +assign s01_axi_rresp = cq_axi_if.rresp; +assign s01_axi_rvalid = cq_axi_if.rvalid; +assign cq_axi_if.rready = s01_axi_rready; + +// ======================================================== + +// Register Interface Instantiations +cmd_queue_v2_0_0_reg_if #(.C_ADDR_WIDTH(C_S00_ADDR_WIDTH)) sq_reg_if(); +cmd_queue_v2_0_0_reg_if #(.C_ADDR_WIDTH(C_S01_ADDR_WIDTH)) cq_reg_if(); + +// ======================================================== + +// AXI Module Instantiation +cmd_queue_v2_0_0_axi #( + .C_S00_ADDR_WIDTH(C_S00_ADDR_WIDTH), + .C_S01_ADDR_WIDTH(C_S01_ADDR_WIDTH) +) axi_inst ( + .sq_axi_if, + .cq_axi_if, + .sq_reg_if, + .cq_reg_if, + .aclk, + .aresetn +); + +// ======================================================== + +// Command Queue Registers Module Instantiation +cmd_queue_v2_0_0_regs top_reg_inst ( + .sq_reg_if, + .cq_reg_if, + .aclk, + .aresetn, + .irq_sq, + .irq_cq +); + +// ======================================================== + +endmodule : cmd_queue_v2_0_0_top \ No newline at end of file diff --git a/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/xgui/cmd_queue_v2_0.tcl b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/xgui/cmd_queue_v2_0.tcl new file mode 100644 index 00000000..84782a49 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/cmd_queue_v2_0/xgui/cmd_queue_v2_0.tcl @@ -0,0 +1,26 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + +} diff --git a/linker/slashkit/resources/base/iprepo/hbm_bandwidth/.gitignore b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/.gitignore new file mode 100644 index 00000000..0b542583 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/.gitignore @@ -0,0 +1 @@ +ip/ diff --git a/linker/slashkit/resources/base/iprepo/hbm_bandwidth/Makefile b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/Makefile new file mode 100644 index 00000000..6cefd215 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/Makefile @@ -0,0 +1,28 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +.PHONY: all clean + +all: + v++ -c --mode hls --config hbm_bandwidth.cfg --work_dir ip + vitis-run --mode hls --package --config hbm_bandwidth.cfg --work_dir ip + +clean: + rm -rf ip/ .Xil *.json \ No newline at end of file diff --git a/linker/slashkit/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cfg b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cfg new file mode 100644 index 00000000..edf5c447 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=hbm_bandwidth +syn.file=hbm_bandwidth.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/linker/slashkit/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cpp b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cpp new file mode 100644 index 00000000..4a001a33 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hbm_bandwidth/hbm_bandwidth.cpp @@ -0,0 +1,54 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#define DATA_WIDTH 256 +typedef ap_uint uint256_t; +#define LENGTH 0x1000000 + +extern "C" void hbm_bandwidth( + uint256_t* hbm_ptr, // HBM memory-mapped pointer + ap_uint<32> wr, + ap_uint<32>& out_acc +) { +#pragma HLS INTERFACE m_axi port=hbm_ptr offset=slave bundle=gmem0 max_read_burst_length=64 max_write_burst_length=64 depth=536870912 +#pragma HLS INTERFACE s_axilite port=hbm_ptr bundle=control +#pragma HLS INTERFACE s_axilite port=wr bundle=control +#pragma HLS INTERFACE s_axilite port=out_acc bundle=control +#pragma HLS INTERFACE s_axilite port=return bundle=control + + ap_uint<32> acc = 0; + if (wr == 0) { + for (uint32_t i = 0; i < LENGTH; i++) { + #pragma HLS PIPELINE II=1 + hbm_ptr[i] = i; + } + } else { + for (uint32_t i = 0; i < LENGTH; i++) { + #pragma HLS PIPELINE II=1 + uint256_t val = hbm_ptr[i]; + acc ^= val.range(31, 0); + } + out_acc = acc; + } +} + diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/bd/bd.tcl b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/bd/bd.tcl new file mode 100644 index 00000000..362e33a5 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/bd/bd.tcl @@ -0,0 +1,201 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +proc post_config_ip {cellpath otherInfo } { +} + +proc pre_propagate {cellpath undefined_params} { + set props [list \ + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF0_BAR_INDEX C_PF0_HIGH_OFFSET C_PF0_LOW_OFFSET \ + C_PF0_ENTRY_TYPE_0 C_PF0_ENTRY_TYPE_1 C_PF0_ENTRY_TYPE_2 C_PF0_ENTRY_TYPE_3 C_PF0_ENTRY_TYPE_4 C_PF0_ENTRY_TYPE_5 C_PF0_ENTRY_TYPE_6 C_PF0_ENTRY_TYPE_7 C_PF0_ENTRY_TYPE_8 C_PF0_ENTRY_TYPE_9 C_PF0_ENTRY_TYPE_10 C_PF0_ENTRY_TYPE_11 C_PF0_ENTRY_TYPE_12 C_PF0_ENTRY_TYPE_13 \ + C_PF0_ENTRY_BAR_0 C_PF0_ENTRY_BAR_1 C_PF0_ENTRY_BAR_2 C_PF0_ENTRY_BAR_3 C_PF0_ENTRY_BAR_4 C_PF0_ENTRY_BAR_5 C_PF0_ENTRY_BAR_6 C_PF0_ENTRY_BAR_7 C_PF0_ENTRY_BAR_8 C_PF0_ENTRY_BAR_9 C_PF0_ENTRY_BAR_10 C_PF0_ENTRY_BAR_11 C_PF0_ENTRY_BAR_12 C_PF0_ENTRY_BAR_13 \ + C_PF0_ENTRY_ADDR_0 C_PF0_ENTRY_ADDR_1 C_PF0_ENTRY_ADDR_2 C_PF0_ENTRY_ADDR_3 C_PF0_ENTRY_ADDR_4 C_PF0_ENTRY_ADDR_5 C_PF0_ENTRY_ADDR_6 C_PF0_ENTRY_ADDR_7 C_PF0_ENTRY_ADDR_8 C_PF0_ENTRY_ADDR_9 C_PF0_ENTRY_ADDR_10 C_PF0_ENTRY_ADDR_11 C_PF0_ENTRY_ADDR_12 C_PF0_ENTRY_ADDR_13 \ + C_PF0_ENTRY_VERSION_TYPE_0 C_PF0_ENTRY_VERSION_TYPE_1 C_PF0_ENTRY_VERSION_TYPE_2 C_PF0_ENTRY_VERSION_TYPE_3 C_PF0_ENTRY_VERSION_TYPE_4 C_PF0_ENTRY_VERSION_TYPE_5 C_PF0_ENTRY_VERSION_TYPE_6 C_PF0_ENTRY_VERSION_TYPE_7 C_PF0_ENTRY_VERSION_TYPE_8 C_PF0_ENTRY_VERSION_TYPE_9 C_PF0_ENTRY_VERSION_TYPE_10 C_PF0_ENTRY_VERSION_TYPE_11 C_PF0_ENTRY_VERSION_TYPE_12 C_PF0_ENTRY_VERSION_TYPE_13 \ + C_PF0_ENTRY_MAJOR_VERSION_0 C_PF0_ENTRY_MAJOR_VERSION_1 C_PF0_ENTRY_MAJOR_VERSION_2 C_PF0_ENTRY_MAJOR_VERSION_3 C_PF0_ENTRY_MAJOR_VERSION_4 C_PF0_ENTRY_MAJOR_VERSION_5 C_PF0_ENTRY_MAJOR_VERSION_6 C_PF0_ENTRY_MAJOR_VERSION_7 C_PF0_ENTRY_MAJOR_VERSION_8 C_PF0_ENTRY_MAJOR_VERSION_9 C_PF0_ENTRY_MAJOR_VERSION_10 C_PF0_ENTRY_MAJOR_VERSION_11 C_PF0_ENTRY_MAJOR_VERSION_12 C_PF0_ENTRY_MAJOR_VERSION_13 \ + C_PF0_ENTRY_MINOR_VERSION_0 C_PF0_ENTRY_MINOR_VERSION_1 C_PF0_ENTRY_MINOR_VERSION_2 C_PF0_ENTRY_MINOR_VERSION_3 C_PF0_ENTRY_MINOR_VERSION_4 C_PF0_ENTRY_MINOR_VERSION_5 C_PF0_ENTRY_MINOR_VERSION_6 C_PF0_ENTRY_MINOR_VERSION_7 C_PF0_ENTRY_MINOR_VERSION_8 C_PF0_ENTRY_MINOR_VERSION_9 C_PF0_ENTRY_MINOR_VERSION_10 C_PF0_ENTRY_MINOR_VERSION_11 C_PF0_ENTRY_MINOR_VERSION_12 C_PF0_ENTRY_MINOR_VERSION_13 \ + C_PF0_ENTRY_RSVD0_0 C_PF0_ENTRY_RSVD0_1 C_PF0_ENTRY_RSVD0_2 C_PF0_ENTRY_RSVD0_3 C_PF0_ENTRY_RSVD0_4 C_PF0_ENTRY_RSVD0_5 C_PF0_ENTRY_RSVD0_6 C_PF0_ENTRY_RSVD0_7 C_PF0_ENTRY_RSVD0_8 C_PF0_ENTRY_RSVD0_9 C_PF0_ENTRY_RSVD0_10 C_PF0_ENTRY_RSVD0_11 C_PF0_ENTRY_RSVD0_12 C_PF0_ENTRY_RSVD0_13 \ + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF1_BAR_INDEX C_PF1_HIGH_OFFSET C_PF1_LOW_OFFSET \ + C_PF1_ENTRY_TYPE_0 C_PF1_ENTRY_TYPE_1 C_PF1_ENTRY_TYPE_2 C_PF1_ENTRY_TYPE_3 C_PF1_ENTRY_TYPE_4 C_PF1_ENTRY_TYPE_5 C_PF1_ENTRY_TYPE_6 C_PF1_ENTRY_TYPE_7 C_PF1_ENTRY_TYPE_8 C_PF1_ENTRY_TYPE_9 C_PF1_ENTRY_TYPE_10 C_PF1_ENTRY_TYPE_11 C_PF1_ENTRY_TYPE_12 C_PF1_ENTRY_TYPE_13 \ + C_PF1_ENTRY_BAR_0 C_PF1_ENTRY_BAR_1 C_PF1_ENTRY_BAR_2 C_PF1_ENTRY_BAR_3 C_PF1_ENTRY_BAR_4 C_PF1_ENTRY_BAR_5 C_PF1_ENTRY_BAR_6 C_PF1_ENTRY_BAR_7 C_PF1_ENTRY_BAR_8 C_PF1_ENTRY_BAR_9 C_PF1_ENTRY_BAR_10 C_PF1_ENTRY_BAR_11 C_PF1_ENTRY_BAR_12 C_PF1_ENTRY_BAR_13 \ + C_PF1_ENTRY_ADDR_0 C_PF1_ENTRY_ADDR_1 C_PF1_ENTRY_ADDR_2 C_PF1_ENTRY_ADDR_3 C_PF1_ENTRY_ADDR_4 C_PF1_ENTRY_ADDR_5 C_PF1_ENTRY_ADDR_6 C_PF1_ENTRY_ADDR_7 C_PF1_ENTRY_ADDR_8 C_PF1_ENTRY_ADDR_9 C_PF1_ENTRY_ADDR_10 C_PF1_ENTRY_ADDR_11 C_PF1_ENTRY_ADDR_12 C_PF1_ENTRY_ADDR_13 \ + C_PF1_ENTRY_VERSION_TYPE_0 C_PF1_ENTRY_VERSION_TYPE_1 C_PF1_ENTRY_VERSION_TYPE_2 C_PF1_ENTRY_VERSION_TYPE_3 C_PF1_ENTRY_VERSION_TYPE_4 C_PF1_ENTRY_VERSION_TYPE_5 C_PF1_ENTRY_VERSION_TYPE_6 C_PF1_ENTRY_VERSION_TYPE_7 C_PF1_ENTRY_VERSION_TYPE_8 C_PF1_ENTRY_VERSION_TYPE_9 C_PF1_ENTRY_VERSION_TYPE_10 C_PF1_ENTRY_VERSION_TYPE_11 C_PF1_ENTRY_VERSION_TYPE_12 C_PF1_ENTRY_VERSION_TYPE_13 \ + C_PF1_ENTRY_MAJOR_VERSION_0 C_PF1_ENTRY_MAJOR_VERSION_1 C_PF1_ENTRY_MAJOR_VERSION_2 C_PF1_ENTRY_MAJOR_VERSION_3 C_PF1_ENTRY_MAJOR_VERSION_4 C_PF1_ENTRY_MAJOR_VERSION_5 C_PF1_ENTRY_MAJOR_VERSION_6 C_PF1_ENTRY_MAJOR_VERSION_7 C_PF1_ENTRY_MAJOR_VERSION_8 C_PF1_ENTRY_MAJOR_VERSION_9 C_PF1_ENTRY_MAJOR_VERSION_10 C_PF1_ENTRY_MAJOR_VERSION_11 C_PF1_ENTRY_MAJOR_VERSION_12 C_PF1_ENTRY_MAJOR_VERSION_13 \ + C_PF1_ENTRY_MINOR_VERSION_0 C_PF1_ENTRY_MINOR_VERSION_1 C_PF1_ENTRY_MINOR_VERSION_2 C_PF1_ENTRY_MINOR_VERSION_3 C_PF1_ENTRY_MINOR_VERSION_4 C_PF1_ENTRY_MINOR_VERSION_5 C_PF1_ENTRY_MINOR_VERSION_6 C_PF1_ENTRY_MINOR_VERSION_7 C_PF1_ENTRY_MINOR_VERSION_8 C_PF1_ENTRY_MINOR_VERSION_9 C_PF1_ENTRY_MINOR_VERSION_10 C_PF1_ENTRY_MINOR_VERSION_11 C_PF1_ENTRY_MINOR_VERSION_12 C_PF1_ENTRY_MINOR_VERSION_13 \ + C_PF1_ENTRY_RSVD0_0 C_PF1_ENTRY_RSVD0_1 C_PF1_ENTRY_RSVD0_2 C_PF1_ENTRY_RSVD0_3 C_PF1_ENTRY_RSVD0_4 C_PF1_ENTRY_RSVD0_5 C_PF1_ENTRY_RSVD0_6 C_PF1_ENTRY_RSVD0_7 C_PF1_ENTRY_RSVD0_8 C_PF1_ENTRY_RSVD0_9 C_PF1_ENTRY_RSVD0_10 C_PF1_ENTRY_RSVD0_11 C_PF1_ENTRY_RSVD0_12 C_PF1_ENTRY_RSVD0_13 \ + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF2_BAR_INDEX C_PF2_HIGH_OFFSET C_PF2_LOW_OFFSET \ + C_PF2_ENTRY_TYPE_0 C_PF2_ENTRY_TYPE_1 C_PF2_ENTRY_TYPE_2 C_PF2_ENTRY_TYPE_3 C_PF2_ENTRY_TYPE_4 C_PF2_ENTRY_TYPE_5 C_PF2_ENTRY_TYPE_6 C_PF2_ENTRY_TYPE_7 C_PF2_ENTRY_TYPE_8 C_PF2_ENTRY_TYPE_9 C_PF2_ENTRY_TYPE_10 C_PF2_ENTRY_TYPE_11 C_PF2_ENTRY_TYPE_12 C_PF2_ENTRY_TYPE_13 \ + C_PF2_ENTRY_BAR_0 C_PF2_ENTRY_BAR_1 C_PF2_ENTRY_BAR_2 C_PF2_ENTRY_BAR_3 C_PF2_ENTRY_BAR_4 C_PF2_ENTRY_BAR_5 C_PF2_ENTRY_BAR_6 C_PF2_ENTRY_BAR_7 C_PF2_ENTRY_BAR_8 C_PF2_ENTRY_BAR_9 C_PF2_ENTRY_BAR_10 C_PF2_ENTRY_BAR_11 C_PF2_ENTRY_BAR_12 C_PF2_ENTRY_BAR_13 \ + C_PF2_ENTRY_ADDR_0 C_PF2_ENTRY_ADDR_1 C_PF2_ENTRY_ADDR_2 C_PF2_ENTRY_ADDR_3 C_PF2_ENTRY_ADDR_4 C_PF2_ENTRY_ADDR_5 C_PF2_ENTRY_ADDR_6 C_PF2_ENTRY_ADDR_7 C_PF2_ENTRY_ADDR_8 C_PF2_ENTRY_ADDR_9 C_PF2_ENTRY_ADDR_10 C_PF2_ENTRY_ADDR_11 C_PF2_ENTRY_ADDR_12 C_PF2_ENTRY_ADDR_13 \ + C_PF2_ENTRY_VERSION_TYPE_0 C_PF2_ENTRY_VERSION_TYPE_1 C_PF2_ENTRY_VERSION_TYPE_2 C_PF2_ENTRY_VERSION_TYPE_3 C_PF2_ENTRY_VERSION_TYPE_4 C_PF2_ENTRY_VERSION_TYPE_5 C_PF2_ENTRY_VERSION_TYPE_6 C_PF2_ENTRY_VERSION_TYPE_7 C_PF2_ENTRY_VERSION_TYPE_8 C_PF2_ENTRY_VERSION_TYPE_9 C_PF2_ENTRY_VERSION_TYPE_10 C_PF2_ENTRY_VERSION_TYPE_11 C_PF2_ENTRY_VERSION_TYPE_12 C_PF2_ENTRY_VERSION_TYPE_13 \ + C_PF2_ENTRY_MAJOR_VERSION_0 C_PF2_ENTRY_MAJOR_VERSION_1 C_PF2_ENTRY_MAJOR_VERSION_2 C_PF2_ENTRY_MAJOR_VERSION_3 C_PF2_ENTRY_MAJOR_VERSION_4 C_PF2_ENTRY_MAJOR_VERSION_5 C_PF2_ENTRY_MAJOR_VERSION_6 C_PF2_ENTRY_MAJOR_VERSION_7 C_PF2_ENTRY_MAJOR_VERSION_8 C_PF2_ENTRY_MAJOR_VERSION_9 C_PF2_ENTRY_MAJOR_VERSION_10 C_PF2_ENTRY_MAJOR_VERSION_11 C_PF2_ENTRY_MAJOR_VERSION_12 C_PF2_ENTRY_MAJOR_VERSION_13 \ + C_PF2_ENTRY_MINOR_VERSION_0 C_PF2_ENTRY_MINOR_VERSION_1 C_PF2_ENTRY_MINOR_VERSION_2 C_PF2_ENTRY_MINOR_VERSION_3 C_PF2_ENTRY_MINOR_VERSION_4 C_PF2_ENTRY_MINOR_VERSION_5 C_PF2_ENTRY_MINOR_VERSION_6 C_PF2_ENTRY_MINOR_VERSION_7 C_PF2_ENTRY_MINOR_VERSION_8 C_PF2_ENTRY_MINOR_VERSION_9 C_PF2_ENTRY_MINOR_VERSION_10 C_PF2_ENTRY_MINOR_VERSION_11 C_PF2_ENTRY_MINOR_VERSION_12 C_PF2_ENTRY_MINOR_VERSION_13 \ + C_PF2_ENTRY_RSVD0_0 C_PF2_ENTRY_RSVD0_1 C_PF2_ENTRY_RSVD0_2 C_PF2_ENTRY_RSVD0_3 C_PF2_ENTRY_RSVD0_4 C_PF2_ENTRY_RSVD0_5 C_PF2_ENTRY_RSVD0_6 C_PF2_ENTRY_RSVD0_7 C_PF2_ENTRY_RSVD0_8 C_PF2_ENTRY_RSVD0_9 C_PF2_ENTRY_RSVD0_10 C_PF2_ENTRY_RSVD0_11 C_PF2_ENTRY_RSVD0_12 C_PF2_ENTRY_RSVD0_13 \ + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE C_PF3_BAR_INDEX C_PF3_HIGH_OFFSET C_PF3_LOW_OFFSET \ + C_PF3_ENTRY_TYPE_0 C_PF3_ENTRY_TYPE_1 C_PF3_ENTRY_TYPE_2 C_PF3_ENTRY_TYPE_3 C_PF3_ENTRY_TYPE_4 C_PF3_ENTRY_TYPE_5 C_PF3_ENTRY_TYPE_6 C_PF3_ENTRY_TYPE_7 C_PF3_ENTRY_TYPE_8 C_PF3_ENTRY_TYPE_9 C_PF3_ENTRY_TYPE_10 C_PF3_ENTRY_TYPE_11 C_PF3_ENTRY_TYPE_12 C_PF3_ENTRY_TYPE_13 \ + C_PF3_ENTRY_BAR_0 C_PF3_ENTRY_BAR_1 C_PF3_ENTRY_BAR_2 C_PF3_ENTRY_BAR_3 C_PF3_ENTRY_BAR_4 C_PF3_ENTRY_BAR_5 C_PF3_ENTRY_BAR_6 C_PF3_ENTRY_BAR_7 C_PF3_ENTRY_BAR_8 C_PF3_ENTRY_BAR_9 C_PF3_ENTRY_BAR_10 C_PF3_ENTRY_BAR_11 C_PF3_ENTRY_BAR_12 C_PF3_ENTRY_BAR_13 \ + C_PF3_ENTRY_ADDR_0 C_PF3_ENTRY_ADDR_1 C_PF3_ENTRY_ADDR_2 C_PF3_ENTRY_ADDR_3 C_PF3_ENTRY_ADDR_4 C_PF3_ENTRY_ADDR_5 C_PF3_ENTRY_ADDR_6 C_PF3_ENTRY_ADDR_7 C_PF3_ENTRY_ADDR_8 C_PF3_ENTRY_ADDR_9 C_PF3_ENTRY_ADDR_10 C_PF3_ENTRY_ADDR_11 C_PF3_ENTRY_ADDR_12 C_PF3_ENTRY_ADDR_13 \ + C_PF3_ENTRY_VERSION_TYPE_0 C_PF3_ENTRY_VERSION_TYPE_1 C_PF3_ENTRY_VERSION_TYPE_2 C_PF3_ENTRY_VERSION_TYPE_3 C_PF3_ENTRY_VERSION_TYPE_4 C_PF3_ENTRY_VERSION_TYPE_5 C_PF3_ENTRY_VERSION_TYPE_6 C_PF3_ENTRY_VERSION_TYPE_7 C_PF3_ENTRY_VERSION_TYPE_8 C_PF3_ENTRY_VERSION_TYPE_9 C_PF3_ENTRY_VERSION_TYPE_10 C_PF3_ENTRY_VERSION_TYPE_11 C_PF3_ENTRY_VERSION_TYPE_12 C_PF3_ENTRY_VERSION_TYPE_13 \ + C_PF3_ENTRY_MAJOR_VERSION_0 C_PF3_ENTRY_MAJOR_VERSION_1 C_PF3_ENTRY_MAJOR_VERSION_2 C_PF3_ENTRY_MAJOR_VERSION_3 C_PF3_ENTRY_MAJOR_VERSION_4 C_PF3_ENTRY_MAJOR_VERSION_5 C_PF3_ENTRY_MAJOR_VERSION_6 C_PF3_ENTRY_MAJOR_VERSION_7 C_PF3_ENTRY_MAJOR_VERSION_8 C_PF3_ENTRY_MAJOR_VERSION_9 C_PF3_ENTRY_MAJOR_VERSION_10 C_PF3_ENTRY_MAJOR_VERSION_11 C_PF3_ENTRY_MAJOR_VERSION_12 C_PF3_ENTRY_MAJOR_VERSION_13 \ + C_PF3_ENTRY_MINOR_VERSION_0 C_PF3_ENTRY_MINOR_VERSION_1 C_PF3_ENTRY_MINOR_VERSION_2 C_PF3_ENTRY_MINOR_VERSION_3 C_PF3_ENTRY_MINOR_VERSION_4 C_PF3_ENTRY_MINOR_VERSION_5 C_PF3_ENTRY_MINOR_VERSION_6 C_PF3_ENTRY_MINOR_VERSION_7 C_PF3_ENTRY_MINOR_VERSION_8 C_PF3_ENTRY_MINOR_VERSION_9 C_PF3_ENTRY_MINOR_VERSION_10 C_PF3_ENTRY_MINOR_VERSION_11 C_PF3_ENTRY_MINOR_VERSION_12 C_PF3_ENTRY_MINOR_VERSION_13 \ + C_PF3_ENTRY_RSVD0_0 C_PF3_ENTRY_RSVD0_1 C_PF3_ENTRY_RSVD0_2 C_PF3_ENTRY_RSVD0_3 C_PF3_ENTRY_RSVD0_4 C_PF3_ENTRY_RSVD0_5 C_PF3_ENTRY_RSVD0_6 C_PF3_ENTRY_RSVD0_7 C_PF3_ENTRY_RSVD0_8 C_PF3_ENTRY_RSVD0_9 C_PF3_ENTRY_RSVD0_10 C_PF3_ENTRY_RSVD0_11 C_PF3_ENTRY_RSVD0_12 C_PF3_ENTRY_RSVD0_13] + set cell [get_bd_cells $cellpath] + puts "\[VSEC-BAR\] Cell: ${cellpath}" + if {[get_property CONFIG.C_MANUAL $cell] == 0} { + set dflt [dict create] + foreach p $props { + dict set dflt CONFIG.${p}.VALUE_SRC DEFAULT + } + set_property -dict $dflt $cell + + if {[llength [get_property CONFIG.C_INJECT_ENDPOINTS $cell]] > 1} { + set inject 1 + puts "\[VSEC-BAR\] ${cell} : Injecting PCIE Mapping Info from C_INJECT_ENDPOINTS" + } elseif {([llength [namespace which vitis::get_pcie_mapping_for]] == 0 || [llength [namespace which vitis::get_endpoints_for_pcie_bar]] == 0)} { + error "\[VSEC-BAR\] Cell ${cell} is configured for auto configuration, but necessary procedures to auto configure are not present." + return + } else { + set inject 0 + puts "\[VSEC-BAR\] ${cell} is being automatically configured." + } + } else { + puts "\[VSEC-BAR\] ${cell} is manually configured, and is skipping automatic configuration." + return + } + + set prop_vals [dict create] + set num_pfs [get_property CONFIG.C_NUM_PFS [get_bd_cells $cellpath]] + puts "\[VSEC-BAR\] ${cell} : Number of PFs = ${num_pfs}" + + if {$inject == 0} { + if {[llength [vitis::get_pcie_mapping_info]] > 0} { + puts "\[VSEC-BAR\] ${cell} : Getting PCIE Mapping Info" + foreach {pcie_info} [vitis::get_pcie_mapping_info] { + set pf [dict get $pcie_info physical_function] + set bar [dict get $pcie_info bar] + puts "\[VSEC-BAR\] ${cell} : Physical Function = ${pf}" + puts "\[VSEC-BAR\] ${cell} : BAR = ${bar}" + foreach {endpoint} [vitis::get_endpoints_for_pcie_bar $pf $bar "ALL"] { + puts "\[VSEC-BAR\] ${cell} : Endpoint = ${endpoint}" + set bar_cell [bd::utils::get_parent [dict get $endpoint intf]] + if {[string match "xilinx.com:ip:hw_discovery:*" [get_property VLNV $bar_cell]]} { + set bar_high_addr [format 0x%08X [expr [dict get $endpoint offset] >> 32]] + set bar_low_addr [format 0x%07X [expr ([dict get $endpoint offset] & 0xFFFFFFFF) / 16]] + dict set prop_vals CONFIG.C_PF${pf}_BAR_INDEX $bar + dict set prop_vals CONFIG.C_PF${pf}_HIGH_OFFSET $bar_high_addr + dict set prop_vals CONFIG.C_PF${pf}_LOW_OFFSET $bar_low_addr + puts "\[VSEC\] Setting $cell bar reference to [dict get $endpoint intf], @ high $bar_high_addr, low $bar_low_addr" + } + } + } + } else { + error "\[VSEC-BAR\] ${cell} : No PCIE Mapping Info found" + } + } else { + set pcie_mapping_info [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] pcie_mapping_info] + foreach {pcie_info} ${pcie_mapping_info} { + puts "\[VSEC-BAR\] ${cell} : PCIE Info: $pcie_info" + set pf [dict get $pcie_info physical_function] + set bar [dict get $pcie_info bar] + puts "\[VSEC-BAR\] ${cell} : Physical Function = ${pf}" + puts "\[VSEC-BAR\] ${cell} : BAR = ${bar}" + set endpoints_for_pcie_bar [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] endpoints_for_pcie_bar $pf $bar] + foreach {endpoint} ${endpoints_for_pcie_bar} { + puts "\[VSEC-BAR\] ${cell} : Endpoint = ${endpoint}" + set bar_cell [bd::utils::get_parent [dict get $endpoint intf]] + if {[llength $bar_cell] > 0} { + if {[string match "xilinx.com:ip:hw_discovery:*" [get_property VLNV $bar_cell]]} { + set bar_high_addr [format 0x%08X [expr [dict get ${endpoint} offset] >> 32]] + set bar_low_addr [format 0x%07X [expr ([dict get ${endpoint} offset] & 0xFFFFFFFF) / 16]] + dict set prop_vals CONFIG.C_PF${pf}_BAR_INDEX $bar + dict set prop_vals CONFIG.C_PF${pf}_HIGH_OFFSET $bar_high_addr + dict set prop_vals CONFIG.C_PF${pf}_LOW_OFFSET $bar_low_addr + puts "\[VSEC\] Setting $cell bar reference to [dict get ${endpoint} intf], @ high $bar_high_addr, low $bar_low_addr" + } + } + } + } + } + + for {set i 0} {$i < $num_pfs} {incr i } { + set bar_info [list] + if {$inject == 0} { + puts "\[VSEC-BAR\] ${cell} : Getting PCIe Mapping Info for ${cell}/s_axi_ctrl_pf${i}" + set bar_info [vitis::get_pcie_mapping_for [get_bd_intf_pins $cell/s_axi_ctrl_pf${i}]] + } else { + puts "\[VSEC-BAR\] ${cell} : Injecting PCIe Mapping Info for ${cell}/s_axi_ctrl_pf${i}" + if {[dict exist [get_property CONFIG.C_INJECT_ENDPOINTS $cell] pcie_mapping_for [get_bd_intf_pins $cell/s_axi_ctrl_pf${i}]]} { + set bar_info [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] pcie_mapping_for [get_bd_intf_pins $cell/s_axi_ctrl_pf${i}]] + } + } + + if {[llength $bar_info] == 0} { + error "\[VSEC-BAR\] ${cell} Could not find a PCIe mapped BAR address" + return + } + set first_bar [lindex $bar_info 0] + set pf [dict get $first_bar physical_function] + set bar [dict get $first_bar bar] + set ep_filter [get_property CONFIG.C_PF${pf}_ENDPOINT_NAMES $cell] + if {[llength [dict keys $ep_filter]] == 0} { + error "\[VSEC-BAR\] ${cell} Unrecognized BAR layout for Physical Function $pf" + } else { + puts "\[VSEC-BAR\] ${cell} Setting BAR layout for Physical Function $pf" + } + set index 0 + dict set prop_vals CONFIG.C_PF${pf}_NUM_SLOTS_BAR_LAYOUT_TABLE $index + if {$inject == 0} { + set endpoints [vitis::get_endpoints_for_pcie_bar $pf $bar] + } else { + set endpoints [dict get [get_property CONFIG.C_INJECT_ENDPOINTS $cell] endpoints_for_pcie_bar $pf $bar] + } + foreach {pcie_peer} ${endpoints} { + puts "\[VSEC-BAR\] ${cell} : PCIe Peer = ${pcie_peer}" + if {[dict exists $ep_filter [dict get $pcie_peer xrt_endpoint_name]]} { + set vlnv_list [split [dict get $pcie_peer reg_abs] ":"] + set vlnv_version_list [split [lindex $vlnv_list 3] "."] + set ep_info [dict get $ep_filter [dict get $pcie_peer xrt_endpoint_name]] + dict unset ep_filter [dict get $pcie_peer xrt_endpoint_name] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_ADDR_${index} [format 0x%012X [dict get $pcie_peer offset]] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_BAR_${index} $bar + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_MAJOR_VERSION_${index} [lindex $vlnv_version_list 0] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_MINOR_VERSION_${index} [lindex $vlnv_version_list 1] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_TYPE_${index} [dict get $ep_info type] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_RSVD0_${index} [dict get $ep_info reserve] + dict set prop_vals CONFIG.C_PF${pf}_ENTRY_VERSION_TYPE_${index} 0x1 + + puts "\[VSEC-BAR\] Adding record to ${cell} for [dict get $pcie_peer xrt_endpoint_name] for endpoint [dict get $pcie_peer intf] at address [format 0x%012X [dict get $pcie_peer offset]]" + incr index + dict set prop_vals CONFIG.C_PF${pf}_NUM_SLOTS_BAR_LAYOUT_TABLE $index + } + } + set err 0 + foreach {ep x} ${ep_filter} { + puts "\[VSEC-BAR\] Expected to find ${ep} on physical function ${pf} bar ${bar}, but failed to find any such endpoint" + set err 1 + } + if {$err == 1} { + error "\[VSEC-BAR\] Aborting BAR layout table configuration due to being malformed" + return + } + } + puts "\[VSEC-BAR\] Configuring $cell with $prop_vals" + set_property -dict $prop_vals $cell +} diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/component.xml b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/component.xml new file mode 100644 index 00000000..c57fc84e --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/component.xml @@ -0,0 +1,13406 @@ + + + xilinx.com + ip + hw_discovery + 1.0 + + + s_pcie4_cfg_ext + + + + + + + function_number + + + s_pcie4_cfg_ext_function_number + + + + + read_data + + + s_pcie4_cfg_ext_read_data + + + + + read_data_valid + + + s_pcie4_cfg_ext_read_data_valid + + + + + read_received + + + s_pcie4_cfg_ext_read_received + + + + + register_number + + + s_pcie4_cfg_ext_register_number + + + + + write_byte_enable + + + s_pcie4_cfg_ext_write_byte_enable + + + + + write_data + + + s_pcie4_cfg_ext_write_data + + + + + write_received + + + s_pcie4_cfg_ext_write_received + + + + + + m_pcie4_cfg_ext + + + + + + + function_number + + + m_pcie4_cfg_ext_function_number + + + + + read_data + + + m_pcie4_cfg_ext_read_data + + + + + read_data_valid + + + m_pcie4_cfg_ext_read_data_valid + + + + + read_received + + + m_pcie4_cfg_ext_read_received + + + + + register_number + + + m_pcie4_cfg_ext_register_number + + + + + write_byte_enable + + + m_pcie4_cfg_ext_write_byte_enable + + + + + write_data + + + m_pcie4_cfg_ext_write_data + + + + + write_received + + + m_pcie4_cfg_ext_write_received + + + + + + + false + + + + + + s_axi_ctrl_pf0 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf0_araddr + + + + + ARREADY + + + s_axi_ctrl_pf0_arready + + + + + ARVALID + + + s_axi_ctrl_pf0_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf0_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf0_awready + + + + + AWVALID + + + s_axi_ctrl_pf0_awvalid + + + + + BREADY + + + s_axi_ctrl_pf0_bready + + + + + BRESP + + + s_axi_ctrl_pf0_bresp + + + + + BVALID + + + s_axi_ctrl_pf0_bvalid + + + + + RDATA + + + s_axi_ctrl_pf0_rdata + + + + + RREADY + + + s_axi_ctrl_pf0_rready + + + + + RRESP + + + s_axi_ctrl_pf0_rresp + + + + + RVALID + + + s_axi_ctrl_pf0_rvalid + + + + + WDATA + + + s_axi_ctrl_pf0_wdata + + + + + WREADY + + + s_axi_ctrl_pf0_wready + + + + + WSTRB + + + s_axi_ctrl_pf0_wstrb + + + + + WVALID + + + s_axi_ctrl_pf0_wvalid + + + + + + s_axi_ctrl_pf1 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf1_araddr + + + + + ARREADY + + + s_axi_ctrl_pf1_arready + + + + + ARVALID + + + s_axi_ctrl_pf1_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf1_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf1_awready + + + + + AWVALID + + + s_axi_ctrl_pf1_awvalid + + + + + BREADY + + + s_axi_ctrl_pf1_bready + + + + + BRESP + + + s_axi_ctrl_pf1_bresp + + + + + BVALID + + + s_axi_ctrl_pf1_bvalid + + + + + RDATA + + + s_axi_ctrl_pf1_rdata + + + + + RREADY + + + s_axi_ctrl_pf1_rready + + + + + RRESP + + + s_axi_ctrl_pf1_rresp + + + + + RVALID + + + s_axi_ctrl_pf1_rvalid + + + + + WDATA + + + s_axi_ctrl_pf1_wdata + + + + + WREADY + + + s_axi_ctrl_pf1_wready + + + + + WSTRB + + + s_axi_ctrl_pf1_wstrb + + + + + WVALID + + + s_axi_ctrl_pf1_wvalid + + + + + + + false + + + + + + s_axi_ctrl_pf2 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf2_araddr + + + + + ARREADY + + + s_axi_ctrl_pf2_arready + + + + + ARVALID + + + s_axi_ctrl_pf2_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf2_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf2_awready + + + + + AWVALID + + + s_axi_ctrl_pf2_awvalid + + + + + BREADY + + + s_axi_ctrl_pf2_bready + + + + + BRESP + + + s_axi_ctrl_pf2_bresp + + + + + BVALID + + + s_axi_ctrl_pf2_bvalid + + + + + RDATA + + + s_axi_ctrl_pf2_rdata + + + + + RREADY + + + s_axi_ctrl_pf2_rready + + + + + RRESP + + + s_axi_ctrl_pf2_rresp + + + + + RVALID + + + s_axi_ctrl_pf2_rvalid + + + + + WDATA + + + s_axi_ctrl_pf2_wdata + + + + + WREADY + + + s_axi_ctrl_pf2_wready + + + + + WSTRB + + + s_axi_ctrl_pf2_wstrb + + + + + WVALID + + + s_axi_ctrl_pf2_wvalid + + + + + + + false + + + + + + s_axi_ctrl_pf3 + + + + + + + + + ARADDR + + + s_axi_ctrl_pf3_araddr + + + + + ARREADY + + + s_axi_ctrl_pf3_arready + + + + + ARVALID + + + s_axi_ctrl_pf3_arvalid + + + + + AWADDR + + + s_axi_ctrl_pf3_awaddr + + + + + AWREADY + + + s_axi_ctrl_pf3_awready + + + + + AWVALID + + + s_axi_ctrl_pf3_awvalid + + + + + BREADY + + + s_axi_ctrl_pf3_bready + + + + + BRESP + + + s_axi_ctrl_pf3_bresp + + + + + BVALID + + + s_axi_ctrl_pf3_bvalid + + + + + RDATA + + + s_axi_ctrl_pf3_rdata + + + + + RREADY + + + s_axi_ctrl_pf3_rready + + + + + RRESP + + + s_axi_ctrl_pf3_rresp + + + + + RVALID + + + s_axi_ctrl_pf3_rvalid + + + + + WDATA + + + s_axi_ctrl_pf3_wdata + + + + + WREADY + + + s_axi_ctrl_pf3_wready + + + + + WSTRB + + + s_axi_ctrl_pf3_wstrb + + + + + WVALID + + + s_axi_ctrl_pf3_wvalid + + + + + + + false + + + + + + aresetn_pcie + + + + + + + RST + + + aresetn_pcie + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk_pcie + + + + + + + CLK + + + aclk_pcie + + + + + + ASSOCIATED_BUSIF + s_pcie4_cfg_ext:m_pcie4_cfg_ext + + + ASSOCIATED_RESET + aresetn_pcie + + + FREQ_HZ + aclk_pcie frequency + aclk_pcie frequency + 250000000 + + + + + aresetn_ctrl + + + + + + + RST + + + aresetn_ctrl + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk_ctrl + + + + + + + CLK + + + aclk_ctrl + + + + + + ASSOCIATED_BUSIF + s_axi_ctrl_pf0:s_axi_ctrl_pf1:s_axi_ctrl_pf2:s_axi_ctrl_pf3 + + + ASSOCIATED_RESET + aresetn_ctrl + + + FREQ_HZ + S_AXI_ACLK frequency + S_AXI_ACLK frequency + 250000000 + + + + + + + s_axi_ctrl_pf0 + BAR Layout Table for PF0 + + reg0 + 0 + 4294967296 + 32 + register + read-only + + Header Reg0 + 0x00 + 1 + read-only + + HEADER_RESERVED + 29 + 3 + read-only + + 0 + 0 + + false + + + HEADER_LAST_CAP + 28 + 1 + read-only + + 0 + 0 + + false + + + HEADER_REV + 20 + 8 + read-only + + 0 + 0 + + false + + + HEADER_FORMAT + 0 + 20 + read-only + + 0 + 0 + + false + + + + Header Reg1 + 0x04 + 1 + read-only + + HEADER_LENGTH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Header Reg2 + 0x08 + 1 + read-only + + FORMAT_ENTRY_SIZE + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg0 + 0x10 + 1 + read-only + + C_ENTRY_ADDR_00_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_00 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg1 + 0x14 + 1 + read-only + + C_ENTRY_ADDR_00_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot00 Reg2 + 0x18 + 1 + read-only + + C_ENTRY_RSVD0_00 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_00 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_00 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg0 + 0x20 + 1 + read-only + + C_ENTRY_ADDR_01_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_01 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg1 + 0x24 + 1 + read-only + + C_ENTRY_ADDR_01_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot01 Reg2 + 0x28 + 1 + read-only + + C_ENTRY_RSVD0_01 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_01 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_01 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg0 + 0x30 + 1 + read-only + + C_ENTRY_ADDR_02_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_02 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg1 + 0x34 + 1 + read-only + + C_ENTRY_ADDR_02_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot02 Reg2 + 0x38 + 1 + read-only + + C_ENTRY_RSVD0_02 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_02 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_02 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg0 + 0x40 + 1 + read-only + + C_ENTRY_ADDR_03_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_03 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg1 + 0x44 + 1 + read-only + + C_ENTRY_ADDR_03_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot03 Reg2 + 0x48 + 1 + read-only + + C_ENTRY_RSVD0_03 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_03 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_03 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg0 + 0x50 + 1 + read-only + + C_ENTRY_ADDR_04_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_04 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg1 + 0x54 + 1 + read-only + + C_ENTRY_ADDR_04_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot04 Reg2 + 0x58 + 1 + read-only + + C_ENTRY_RSVD0_04 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_04 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_04 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg0 + 0x60 + 1 + read-only + + C_ENTRY_ADDR_05_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_05 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg1 + 0x64 + 1 + read-only + + C_ENTRY_ADDR_05_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot05 Reg2 + 0x68 + 1 + read-only + + C_ENTRY_RSVD0_05 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_05 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_05 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg0 + 0x70 + 1 + read-only + + C_ENTRY_ADDR_06_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_06 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg1 + 0x74 + 1 + read-only + + C_ENTRY_ADDR_06_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot06 Reg2 + 0x78 + 1 + read-only + + C_ENTRY_RSVD0_06 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_06 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_06 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg0 + 0x80 + 1 + read-only + + C_ENTRY_ADDR_07_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_07 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg1 + 0x84 + 1 + read-only + + C_ENTRY_ADDR_07_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot07 Reg2 + 0x88 + 1 + read-only + + C_ENTRY_RSVD0_07 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_07 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_07 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg0 + 0x90 + 1 + read-only + + C_ENTRY_ADDR_08_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_08 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg1 + 0x94 + 1 + read-only + + C_ENTRY_ADDR_08_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot08 Reg2 + 0x98 + 1 + read-only + + C_ENTRY_RSVD0_08 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_08 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_08 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg0 + 0xA0 + 1 + read-only + + C_ENTRY_ADDR_09_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_09 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg1 + 0xA4 + 1 + read-only + + C_ENTRY_ADDR_09_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot09 Reg2 + 0xA8 + 1 + read-only + + C_ENTRY_RSVD0_09 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_09 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_09 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg0 + 0xB0 + 1 + read-only + + C_ENTRY_ADDR_10_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_10 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg1 + 0xB4 + 1 + read-only + + C_ENTRY_ADDR_10_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot10 Reg2 + 0xB8 + 1 + read-only + + C_ENTRY_RSVD0_10 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_10 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_10 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg0 + 0xC0 + 1 + read-only + + C_ENTRY_ADDR_11_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_11 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg1 + 0xC4 + 1 + read-only + + C_ENTRY_ADDR_11_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot11 Reg2 + 0xC8 + 1 + read-only + + C_ENTRY_RSVD0_11 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_11 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_11 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg0 + 0xD0 + 1 + read-only + + C_ENTRY_ADDR_12_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_12 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg1 + 0xD4 + 1 + read-only + + C_ENTRY_ADDR_12_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot12 Reg2 + 0xD8 + 1 + read-only + + C_ENTRY_RSVD0_12 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_12 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_12 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg0 + 0xE0 + 1 + read-only + + C_ENTRY_ADDR_13_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_13 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg1 + 0xE4 + 1 + read-only + + C_ENTRY_ADDR_13_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot13 Reg2 + 0xE8 + 1 + read-only + + C_ENTRY_RSVD0_13 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_13 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_13 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + + + s_axi_ctrl_pf1 + BAR Layout Table for PF1 + + reg0 + 0 + 4294967296 + 32 + register + read-only + + Slot00 Reg0 + 0x10 + 1 + read-only + + C_ENTRY_ADDR_00_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_00 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg1 + 0x14 + 1 + read-only + + C_ENTRY_ADDR_00_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot00 Reg2 + 0x18 + 1 + read-only + + C_ENTRY_RSVD0_00 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_00 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_00 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg0 + 0x20 + 1 + read-only + + C_ENTRY_ADDR_01_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_01 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg1 + 0x24 + 1 + read-only + + C_ENTRY_ADDR_01_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot01 Reg2 + 0x28 + 1 + read-only + + C_ENTRY_RSVD0_01 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_01 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_01 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg0 + 0x30 + 1 + read-only + + C_ENTRY_ADDR_02_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_02 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg1 + 0x34 + 1 + read-only + + C_ENTRY_ADDR_02_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot02 Reg2 + 0x38 + 1 + read-only + + C_ENTRY_RSVD0_02 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_02 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_02 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg0 + 0x40 + 1 + read-only + + C_ENTRY_ADDR_03_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_03 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg1 + 0x44 + 1 + read-only + + C_ENTRY_ADDR_03_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot03 Reg2 + 0x48 + 1 + read-only + + C_ENTRY_RSVD0_03 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_03 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_03 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg0 + 0x50 + 1 + read-only + + C_ENTRY_ADDR_04_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_04 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg1 + 0x54 + 1 + read-only + + C_ENTRY_ADDR_04_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot04 Reg2 + 0x58 + 1 + read-only + + C_ENTRY_RSVD0_04 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_04 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_04 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg0 + 0x60 + 1 + read-only + + C_ENTRY_ADDR_05_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_05 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg1 + 0x64 + 1 + read-only + + C_ENTRY_ADDR_05_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot05 Reg2 + 0x68 + 1 + read-only + + C_ENTRY_RSVD0_05 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_05 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_05 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg0 + 0x70 + 1 + read-only + + C_ENTRY_ADDR_06_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_06 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg1 + 0x74 + 1 + read-only + + C_ENTRY_ADDR_06_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot06 Reg2 + 0x78 + 1 + read-only + + C_ENTRY_RSVD0_06 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_06 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_06 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg0 + 0x80 + 1 + read-only + + C_ENTRY_ADDR_07_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_07 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg1 + 0x84 + 1 + read-only + + C_ENTRY_ADDR_07_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot07 Reg2 + 0x88 + 1 + read-only + + C_ENTRY_RSVD0_07 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_07 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_07 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg0 + 0x90 + 1 + read-only + + C_ENTRY_ADDR_08_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_08 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg1 + 0x94 + 1 + read-only + + C_ENTRY_ADDR_08_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot08 Reg2 + 0x98 + 1 + read-only + + C_ENTRY_RSVD0_08 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_08 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_08 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg0 + 0xA0 + 1 + read-only + + C_ENTRY_ADDR_09_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_09 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg1 + 0xA4 + 1 + read-only + + C_ENTRY_ADDR_09_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot09 Reg2 + 0xA8 + 1 + read-only + + C_ENTRY_RSVD0_09 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_09 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_09 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg0 + 0xB0 + 1 + read-only + + C_ENTRY_ADDR_10_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_10 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg1 + 0xB4 + 1 + read-only + + C_ENTRY_ADDR_10_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot10 Reg2 + 0xB8 + 1 + read-only + + C_ENTRY_RSVD0_10 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_10 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_10 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg0 + 0xC0 + 1 + read-only + + C_ENTRY_ADDR_11_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_11 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg1 + 0xC4 + 1 + read-only + + C_ENTRY_ADDR_11_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot11 Reg2 + 0xC8 + 1 + read-only + + C_ENTRY_RSVD0_11 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_11 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_11 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg0 + 0xD0 + 1 + read-only + + C_ENTRY_ADDR_12_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_12 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg1 + 0xD4 + 1 + read-only + + C_ENTRY_ADDR_12_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot12 Reg2 + 0xD8 + 1 + read-only + + C_ENTRY_RSVD0_12 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_12 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_12 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg0 + 0xE0 + 1 + read-only + + C_ENTRY_ADDR_13_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_13 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg1 + 0xE4 + 1 + read-only + + C_ENTRY_ADDR_13_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot13 Reg2 + 0xE8 + 1 + read-only + + C_ENTRY_RSVD0_13 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_13 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_13 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + + + s_axi_ctrl_pf2 + BAR Layout Table for PF2 + + reg0 + 0 + 4294967296 + 32 + register + read-only + + Slot00 Reg0 + 0x10 + 1 + read-only + + C_ENTRY_ADDR_00_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_00 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg1 + 0x14 + 1 + read-only + + C_ENTRY_ADDR_00_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot00 Reg2 + 0x18 + 1 + read-only + + C_ENTRY_RSVD0_00 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_00 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_00 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg0 + 0x20 + 1 + read-only + + C_ENTRY_ADDR_01_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_01 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg1 + 0x24 + 1 + read-only + + C_ENTRY_ADDR_01_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot01 Reg2 + 0x28 + 1 + read-only + + C_ENTRY_RSVD0_01 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_01 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_01 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg0 + 0x30 + 1 + read-only + + C_ENTRY_ADDR_02_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_02 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg1 + 0x34 + 1 + read-only + + C_ENTRY_ADDR_02_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot02 Reg2 + 0x38 + 1 + read-only + + C_ENTRY_RSVD0_02 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_02 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_02 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg0 + 0x40 + 1 + read-only + + C_ENTRY_ADDR_03_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_03 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg1 + 0x44 + 1 + read-only + + C_ENTRY_ADDR_03_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot03 Reg2 + 0x48 + 1 + read-only + + C_ENTRY_RSVD0_03 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_03 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_03 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg0 + 0x50 + 1 + read-only + + C_ENTRY_ADDR_04_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_04 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg1 + 0x54 + 1 + read-only + + C_ENTRY_ADDR_04_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot04 Reg2 + 0x58 + 1 + read-only + + C_ENTRY_RSVD0_04 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_04 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_04 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg0 + 0x60 + 1 + read-only + + C_ENTRY_ADDR_05_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_05 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg1 + 0x64 + 1 + read-only + + C_ENTRY_ADDR_05_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot05 Reg2 + 0x68 + 1 + read-only + + C_ENTRY_RSVD0_05 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_05 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_05 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg0 + 0x70 + 1 + read-only + + C_ENTRY_ADDR_06_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_06 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg1 + 0x74 + 1 + read-only + + C_ENTRY_ADDR_06_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot06 Reg2 + 0x78 + 1 + read-only + + C_ENTRY_RSVD0_06 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_06 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_06 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg0 + 0x80 + 1 + read-only + + C_ENTRY_ADDR_07_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_07 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg1 + 0x84 + 1 + read-only + + C_ENTRY_ADDR_07_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot07 Reg2 + 0x88 + 1 + read-only + + C_ENTRY_RSVD0_07 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_07 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_07 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg0 + 0x90 + 1 + read-only + + C_ENTRY_ADDR_08_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_08 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg1 + 0x94 + 1 + read-only + + C_ENTRY_ADDR_08_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot08 Reg2 + 0x98 + 1 + read-only + + C_ENTRY_RSVD0_08 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_08 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_08 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg0 + 0xA0 + 1 + read-only + + C_ENTRY_ADDR_09_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_09 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg1 + 0xA4 + 1 + read-only + + C_ENTRY_ADDR_09_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot09 Reg2 + 0xA8 + 1 + read-only + + C_ENTRY_RSVD0_09 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_09 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_09 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg0 + 0xB0 + 1 + read-only + + C_ENTRY_ADDR_10_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_10 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg1 + 0xB4 + 1 + read-only + + C_ENTRY_ADDR_10_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot10 Reg2 + 0xB8 + 1 + read-only + + C_ENTRY_RSVD0_10 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_10 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_10 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg0 + 0xC0 + 1 + read-only + + C_ENTRY_ADDR_11_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_11 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg1 + 0xC4 + 1 + read-only + + C_ENTRY_ADDR_11_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot11 Reg2 + 0xC8 + 1 + read-only + + C_ENTRY_RSVD0_11 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_11 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_11 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg0 + 0xD0 + 1 + read-only + + C_ENTRY_ADDR_12_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_12 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg1 + 0xD4 + 1 + read-only + + C_ENTRY_ADDR_12_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot12 Reg2 + 0xD8 + 1 + read-only + + C_ENTRY_RSVD0_12 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_12 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_12 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg0 + 0xE0 + 1 + read-only + + C_ENTRY_ADDR_13_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_13 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg1 + 0xE4 + 1 + read-only + + C_ENTRY_ADDR_13_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot13 Reg2 + 0xE8 + 1 + read-only + + C_ENTRY_RSVD0_13 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_13 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_13 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + + + s_axi_ctrl_pf3 + BAR Layout Table for PF3 + + reg0 + 0 + 4294967296 + 32 + register + read-only + + Slot00 Reg0 + 0x10 + 1 + read-only + + C_ENTRY_ADDR_00_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_00 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot00 Reg1 + 0x14 + 1 + read-only + + C_ENTRY_ADDR_00_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot00 Reg2 + 0x18 + 1 + read-only + + C_ENTRY_RSVD0_00 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_00 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_00 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_00 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg0 + 0x20 + 1 + read-only + + C_ENTRY_ADDR_01_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_01 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot01 Reg1 + 0x24 + 1 + read-only + + C_ENTRY_ADDR_01_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot01 Reg2 + 0x28 + 1 + read-only + + C_ENTRY_RSVD0_01 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_01 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_01 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_01 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg0 + 0x30 + 1 + read-only + + C_ENTRY_ADDR_02_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_02 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot02 Reg1 + 0x34 + 1 + read-only + + C_ENTRY_ADDR_02_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot02 Reg2 + 0x38 + 1 + read-only + + C_ENTRY_RSVD0_02 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_02 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_02 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_02 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg0 + 0x40 + 1 + read-only + + C_ENTRY_ADDR_03_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_03 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot03 Reg1 + 0x44 + 1 + read-only + + C_ENTRY_ADDR_03_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot03 Reg2 + 0x48 + 1 + read-only + + C_ENTRY_RSVD0_03 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_03 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_03 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_03 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg0 + 0x50 + 1 + read-only + + C_ENTRY_ADDR_04_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_04 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot04 Reg1 + 0x54 + 1 + read-only + + C_ENTRY_ADDR_04_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot04 Reg2 + 0x58 + 1 + read-only + + C_ENTRY_RSVD0_04 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_04 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_04 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_04 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg0 + 0x60 + 1 + read-only + + C_ENTRY_ADDR_05_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_05 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot05 Reg1 + 0x64 + 1 + read-only + + C_ENTRY_ADDR_05_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot05 Reg2 + 0x68 + 1 + read-only + + C_ENTRY_RSVD0_05 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_05 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_05 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_05 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg0 + 0x70 + 1 + read-only + + C_ENTRY_ADDR_06_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_06 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot06 Reg1 + 0x74 + 1 + read-only + + C_ENTRY_ADDR_06_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot06 Reg2 + 0x78 + 1 + read-only + + C_ENTRY_RSVD0_06 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_06 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_06 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_06 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg0 + 0x80 + 1 + read-only + + C_ENTRY_ADDR_07_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_07 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot07 Reg1 + 0x84 + 1 + read-only + + C_ENTRY_ADDR_07_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot07 Reg2 + 0x88 + 1 + read-only + + C_ENTRY_RSVD0_07 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_07 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_07 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_07 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg0 + 0x90 + 1 + read-only + + C_ENTRY_ADDR_08_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_08 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot08 Reg1 + 0x94 + 1 + read-only + + C_ENTRY_ADDR_08_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot08 Reg2 + 0x98 + 1 + read-only + + C_ENTRY_RSVD0_08 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_08 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_08 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_08 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg0 + 0xA0 + 1 + read-only + + C_ENTRY_ADDR_09_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_09 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot09 Reg1 + 0xA4 + 1 + read-only + + C_ENTRY_ADDR_09_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot09 Reg2 + 0xA8 + 1 + read-only + + C_ENTRY_RSVD0_09 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_09 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_09 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_09 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg0 + 0xB0 + 1 + read-only + + C_ENTRY_ADDR_10_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_10 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot10 Reg1 + 0xB4 + 1 + read-only + + C_ENTRY_ADDR_10_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot10 Reg2 + 0xB8 + 1 + read-only + + C_ENTRY_RSVD0_10 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_10 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_10 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_10 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg0 + 0xC0 + 1 + read-only + + C_ENTRY_ADDR_11_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_11 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot11 Reg1 + 0xC4 + 1 + read-only + + C_ENTRY_ADDR_11_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot11 Reg2 + 0xC8 + 1 + read-only + + C_ENTRY_RSVD0_11 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_11 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_11 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_11 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg0 + 0xD0 + 1 + read-only + + C_ENTRY_ADDR_12_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_12 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot12 Reg1 + 0xD4 + 1 + read-only + + C_ENTRY_ADDR_12_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot12 Reg2 + 0xD8 + 1 + read-only + + C_ENTRY_RSVD0_12 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_12 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_12 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_12 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg0 + 0xE0 + 1 + read-only + + C_ENTRY_ADDR_13_LOW + 16 + 16 + read-only + + 0 + 0 + + false + + + C_ENTRY_BAR_13 + 13 + 3 + read-only + + 0 + 0 + + false + + + ENTRY_REVISION + 8 + 5 + read-only + + 0 + 0 + + false + + + C_ENTRY_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + Slot13 Reg1 + 0xE4 + 1 + read-only + + C_ENTRY_ADDR_13_HIGH + 0 + 32 + read-only + + 0 + 0 + + false + + + + Slot13 Reg2 + 0xE8 + 1 + read-only + + C_ENTRY_RSVD0_13 + 24 + 4 + read-only + + 0 + 0 + + false + + + C_ENTRY_MAJOR_VERSION_13 + 16 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_MINOR_VERSION_13 + 8 + 8 + read-only + + 0 + 0 + + false + + + C_ENTRY_VERSION_TYPE_13 + 0 + 8 + read-only + + 0 + 0 + + false + + + + + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + hw_discovery_v1_0_0_hw_discovery + + xilinx_blockdiagram_view_fileset + + + + viewChecksum + 2b00f7e0 + + + + + xilinx_examples + Examples + :vivado.xilinx.com:examples + hw_discovery_v1_0_0_hw_discovery + + xilinx_examples_view_fileset + + + + viewChecksum + 9f3415d8 + + + + + xilinx_examplesscriptext + Examples Script Extension + :vivado.xilinx.com:examples.scriptext + hw_discovery_v1_0_0_hw_discovery + + xilinx_examplesscriptext_xilinx_com_ip_axi_vip_1_1__ref_view_fileset + + + xilinx_examplesscriptext_view_fileset + + + + viewChecksum + d083363b + + + + + xilinx_examplessimulation + Examples Simulation + :vivado.xilinx.com:examples.simulation + hw_discovery_v1_0_0_hw_discovery + + xilinx_examplessimulation_view_fileset + + + + viewChecksum + 7328ef6b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + hw_discovery_v1_0_0_hw_discovery + + xilinx_xpgui_view_fileset + + + + viewChecksum + 7851c6a8 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + hw_discovery_v1_0_0_hw_discovery + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9bbae5cb + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + hw_discovery_v1_0_0_hw_discovery + + xilinx_anylanguagesynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9bbae5cb + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + hw_discovery_v1_0_0_hw_discovery + + xilinx_versioninformation_view_fileset + + + + + + aclk_pcie + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn_pcie + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk_ctrl + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn_ctrl + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_function_number + + in + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_read_data + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_read_data_valid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_read_received + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_register_number + + in + + 9 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_write_byte_enable + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_write_data + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_pcie4_cfg_ext_write_received + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_function_number + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_read_data + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_read_data_valid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_read_received + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_register_number + + out + + 9 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_write_byte_enable + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_write_data + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_pcie4_cfg_ext_write_received + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_awaddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_araddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf0_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_awaddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_araddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf1_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_awaddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_araddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf2_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_awaddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_araddr + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_ctrl_pf3_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_NUM_PFS + NUMBER OF PFs + 1 + + + C_CAP_BASE_ADDR + PCIe Extended Capability Base Address + 0x000 + + + C_NEXT_CAP_ADDR + Next Capability Pointer + 0x000 + + + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF0 + 1 + + + C_PF0_BAR_INDEX + PF0 BAR Index + 0 + + + C_PF0_LOW_OFFSET + PF0 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF0_HIGH_OFFSET + PF0 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF0_ENTRY_TYPE_0 + PF0 Table Entry 0 Type + 0x00 + + + C_PF0_ENTRY_BAR_0 + PF0 Table Entry 0 BAR + 0 + + + C_PF0_ENTRY_ADDR_0 + PF0 Table Entry 0 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_0 + PF0 Table Entry 0 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_0 + PF0 Table Entry 0 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_0 + PF0 Table Entry 0 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_0 + PF0 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_1 + PF0 Table Entry 1 Type + 0x00 + + + C_PF0_ENTRY_BAR_1 + PF0 Table Entry 1 BAR + 0 + + + C_PF0_ENTRY_ADDR_1 + PF0 Table Entry 1 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_1 + PF0 Table Entry 1 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_1 + PF0 Table Entry 1 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_1 + PF0 Table Entry 1 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_1 + PF0 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_2 + PF0 Table Entry 2 Type + 0x00 + + + C_PF0_ENTRY_BAR_2 + PF0 Table Entry 2 BAR + 0 + + + C_PF0_ENTRY_ADDR_2 + PF0 Table Entry 2 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_2 + PF0 Table Entry 2 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_2 + PF0 Table Entry 2 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_2 + PF0 Table Entry 2 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_2 + PF0 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_3 + PF0 Table Entry 3 Type + 0x00 + + + C_PF0_ENTRY_BAR_3 + PF0 Table Entry 3 BAR + 0 + + + C_PF0_ENTRY_ADDR_3 + PF0 Table Entry 3 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_3 + PF0 Table Entry 3 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_3 + PF0 Table Entry 3 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_3 + PF0 Table Entry 3 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_3 + PF0 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_4 + PF0 Table Entry 4 Type + 0x00 + + + C_PF0_ENTRY_BAR_4 + PF0 Table Entry 4 BAR + 0 + + + C_PF0_ENTRY_ADDR_4 + PF0 Table Entry 4 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_4 + PF0 Table Entry 4 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_4 + PF0 Table Entry 4 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_4 + PF0 Table Entry 4 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_5 + PF0 Table Entry 5 Type + 0x00 + + + C_PF0_ENTRY_BAR_5 + PF0 Table Entry 5 BAR + 0 + + + C_PF0_ENTRY_ADDR_5 + PF0 Table Entry 5 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_5 + PF0 Table Entry 5 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_5 + PF0 Table Entry 5 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_5 + PF0 Table Entry 5 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_5 + PF0 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_6 + PF0 Table Entry 6 Type + 0x00 + + + C_PF0_ENTRY_BAR_6 + PF0 Table Entry 6 BAR + 0 + + + C_PF0_ENTRY_ADDR_6 + PF0 Table Entry 6 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_6 + PF0 Table Entry 6 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_6 + PF0 Table Entry 6 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_6 + PF0 Table Entry 6 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_6 + PF0 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_7 + PF0 Table Entry 7 Type + 0x00 + + + C_PF0_ENTRY_BAR_7 + PF0 Table Entry 7 BAR + 0 + + + C_PF0_ENTRY_ADDR_7 + PF0 Table Entry 7 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_7 + PF0 Table Entry 7 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_7 + PF0 Table Entry 7 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_7 + PF0 Table Entry 7 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_7 + PF0 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_8 + PF0 Table Entry 8 Type + 0x00 + + + C_PF0_ENTRY_BAR_8 + PF0 Table Entry 8 BAR + 0 + + + C_PF0_ENTRY_ADDR_8 + PF0 Table Entry 8 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_8 + PF0 Table Entry 8 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_8 + PF0 Table Entry 8 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_8 + PF0 Table Entry 8 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_8 + PF0 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_9 + PF0 Table Entry 9 Type + 0x00 + + + C_PF0_ENTRY_BAR_9 + PF0 Table Entry 9 BAR + 0 + + + C_PF0_ENTRY_ADDR_9 + PF0 Table Entry 9 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_9 + PF0 Table Entry 9 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_9 + PF0 Table Entry 9 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_9 + PF0 Table Entry 9 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_9 + PF0 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_10 + PF0 Table Entry 10 Type + 0x00 + + + C_PF0_ENTRY_BAR_10 + PF0 Table Entry 10 BAR + 0 + + + C_PF0_ENTRY_ADDR_10 + PF0 Table Entry 10 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_10 + PF0 Table Entry 10 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_10 + PF0 Table Entry 10 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_10 + PF0 Table Entry 10 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_10 + PF0 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_11 + PF0 Table Entry 11 Type + 0x00 + + + C_PF0_ENTRY_BAR_11 + PF0 Table Entry 11 BAR + 0 + + + C_PF0_ENTRY_ADDR_11 + PF0 Table Entry 11 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_11 + PF0 Table Entry 11 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_11 + PF0 Table Entry 11 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_11 + PF0 Table Entry 11 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_11 + PF0 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_12 + PF0 Table Entry 12 Type + 0x00 + + + C_PF0_ENTRY_BAR_12 + PF0 Table Entry 12 BAR + 0 + + + C_PF0_ENTRY_ADDR_12 + PF0 Table Entry 12 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_12 + PF0 Table Entry 12 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_12 + PF0 Table Entry 12 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_12 + PF0 Table Entry 12 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_12 + PF0 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_13 + PF0 Table Entry 13 Type + 0x00 + + + C_PF0_ENTRY_BAR_13 + PF0 Table Entry 13 BAR + 0 + + + C_PF0_ENTRY_ADDR_13 + PF0 Table Entry 13 Address + 0x000000000000 + + + C_PF0_ENTRY_MAJOR_VERSION_13 + PF0 Table Entry 13 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_13 + PF0 Table Entry 13 Minor Version + 0 + + + C_PF0_ENTRY_VERSION_TYPE_13 + PF0 Table Entry 13 Version Type + 0x00 + + + C_PF0_ENTRY_RSVD0_13 + PF0 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF0_S_AXI_ADDR_WIDTH + PF0 AXI Interface Address Width + 32 + + + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF1 + 1 + + + C_PF1_BAR_INDEX + PF1 BAR Index + 0 + + + C_PF1_LOW_OFFSET + PF1 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF1_HIGH_OFFSET + PF1 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF1_ENTRY_TYPE_0 + PF1 Table Entry 0 Type + 0x00 + + + C_PF1_ENTRY_BAR_0 + PF1 Table Entry 0 BAR + 0 + + + C_PF1_ENTRY_ADDR_0 + PF1 Table Entry 0 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_0 + PF1 Table Entry 0 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_0 + PF1 Table Entry 0 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_0 + PF1 Table Entry 0 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_0 + PF1 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_1 + PF1 Table Entry 1 Type + 0x00 + + + C_PF1_ENTRY_BAR_1 + PF1 Table Entry 1 BAR + 0 + + + C_PF1_ENTRY_ADDR_1 + PF1 Table Entry 1 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_1 + PF1 Table Entry 1 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_1 + PF1 Table Entry 1 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_1 + PF1 Table Entry 1 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_1 + PF1 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_2 + PF1 Table Entry 2 Type + 0x00 + + + C_PF1_ENTRY_BAR_2 + PF1 Table Entry 2 BAR + 0 + + + C_PF1_ENTRY_ADDR_2 + PF1 Table Entry 2 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_2 + PF1 Table Entry 2 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_2 + PF1 Table Entry 2 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_2 + PF1 Table Entry 2 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_2 + PF1 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_3 + PF1 Table Entry 3 Type + 0x00 + + + C_PF1_ENTRY_BAR_3 + PF1 Table Entry 3 BAR + 0 + + + C_PF1_ENTRY_ADDR_3 + PF1 Table Entry 3 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_3 + PF1 Table Entry 3 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_3 + PF1 Table Entry 3 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_3 + PF1 Table Entry 3 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_3 + PF1 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_4 + PF1 Table Entry 4 Type + 0x00 + + + C_PF1_ENTRY_BAR_4 + PF1 Table Entry 4 BAR + 0 + + + C_PF1_ENTRY_ADDR_4 + PF1 Table Entry 4 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_4 + PF1 Table Entry 4 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_4 + PF1 Table Entry 4 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_4 + PF1 Table Entry 4 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_5 + PF1 Table Entry 5 Type + 0x00 + + + C_PF1_ENTRY_BAR_5 + PF1 Table Entry 5 BAR + 0 + + + C_PF1_ENTRY_ADDR_5 + PF1 Table Entry 5 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_5 + PF1 Table Entry 5 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_5 + PF1 Table Entry 5 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_5 + PF1 Table Entry 5 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_5 + PF1 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_6 + PF1 Table Entry 6 Type + 0x00 + + + C_PF1_ENTRY_BAR_6 + PF1 Table Entry 6 BAR + 0 + + + C_PF1_ENTRY_ADDR_6 + PF1 Table Entry 6 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_6 + PF1 Table Entry 6 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_6 + PF1 Table Entry 6 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_6 + PF1 Table Entry 6 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_6 + PF1 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_7 + PF1 Table Entry 7 Type + 0x00 + + + C_PF1_ENTRY_BAR_7 + PF1 Table Entry 7 BAR + 0 + + + C_PF1_ENTRY_ADDR_7 + PF1 Table Entry 7 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_7 + PF1 Table Entry 7 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_7 + PF1 Table Entry 7 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_7 + PF1 Table Entry 7 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_7 + PF1 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_8 + PF1 Table Entry 8 Type + 0x00 + + + C_PF1_ENTRY_BAR_8 + PF1 Table Entry 8 BAR + 0 + + + C_PF1_ENTRY_ADDR_8 + PF1 Table Entry 8 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_8 + PF1 Table Entry 8 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_8 + PF1 Table Entry 8 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_8 + PF1 Table Entry 8 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_8 + PF1 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_9 + PF1 Table Entry 9 Type + 0x00 + + + C_PF1_ENTRY_BAR_9 + PF1 Table Entry 9 BAR + 0 + + + C_PF1_ENTRY_ADDR_9 + PF1 Table Entry 9 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_9 + PF1 Table Entry 9 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_9 + PF1 Table Entry 9 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_9 + PF1 Table Entry 9 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_9 + PF1 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_10 + PF1 Table Entry 10 Type + 0x00 + + + C_PF1_ENTRY_BAR_10 + PF1 Table Entry 10 BAR + 0 + + + C_PF1_ENTRY_ADDR_10 + PF1 Table Entry 10 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_10 + PF1 Table Entry 10 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_10 + PF1 Table Entry 10 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_10 + PF1 Table Entry 10 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_10 + PF1 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_11 + PF1 Table Entry 11 Type + 0x00 + + + C_PF1_ENTRY_BAR_11 + PF1 Table Entry 11 BAR + 0 + + + C_PF1_ENTRY_ADDR_11 + PF1 Table Entry 11 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_11 + PF1 Table Entry 11 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_11 + PF1 Table Entry 11 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_11 + PF1 Table Entry 11 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_11 + PF1 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_12 + PF1 Table Entry 12 Type + 0x00 + + + C_PF1_ENTRY_BAR_12 + PF1 Table Entry 12 BAR + 0 + + + C_PF1_ENTRY_ADDR_12 + PF1 Table Entry 12 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_12 + PF1 Table Entry 12 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_12 + PF1 Table Entry 12 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_12 + PF1 Table Entry 12 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_12 + PF1 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_13 + PF1 Table Entry 13 Type + 0x00 + + + C_PF1_ENTRY_BAR_13 + PF1 Table Entry 13 BAR + 0 + + + C_PF1_ENTRY_ADDR_13 + PF1 Table Entry 13 Address + 0x000000000000 + + + C_PF1_ENTRY_MAJOR_VERSION_13 + PF1 Table Entry 13 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_13 + PF1 Table Entry 13 Minor Version + 0 + + + C_PF1_ENTRY_VERSION_TYPE_13 + PF1 Table Entry 13 Version Type + 0x00 + + + C_PF1_ENTRY_RSVD0_13 + PF1 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF1_S_AXI_ADDR_WIDTH + PF1 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF2 + 1 + + + C_PF2_BAR_INDEX + PF2 BAR Index + 0 + + + C_PF2_LOW_OFFSET + PF2 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF2_HIGH_OFFSET + PF2 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF2_ENTRY_TYPE_0 + PF2 Table Entry 0 Type + 0x00 + + + C_PF2_ENTRY_BAR_0 + PF2 Table Entry 0 BAR + 0 + + + C_PF2_ENTRY_ADDR_0 + PF2 Table Entry 0 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_0 + PF2 Table Entry 0 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_0 + PF2 Table Entry 0 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_0 + PF2 Table Entry 0 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_0 + PF2 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_1 + PF2 Table Entry 1 Type + 0x00 + + + C_PF2_ENTRY_BAR_1 + PF2 Table Entry 1 BAR + 0 + + + C_PF2_ENTRY_ADDR_1 + PF2 Table Entry 1 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_1 + PF2 Table Entry 1 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_1 + PF2 Table Entry 1 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_1 + PF2 Table Entry 1 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_1 + PF2 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_2 + PF2 Table Entry 2 Type + 0x00 + + + C_PF2_ENTRY_BAR_2 + PF2 Table Entry 2 BAR + 0 + + + C_PF2_ENTRY_ADDR_2 + PF2 Table Entry 2 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_2 + PF2 Table Entry 2 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_2 + PF2 Table Entry 2 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_2 + PF2 Table Entry 2 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_2 + PF2 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_3 + PF2 Table Entry 3 Type + 0x00 + + + C_PF2_ENTRY_BAR_3 + PF2 Table Entry 3 BAR + 0 + + + C_PF2_ENTRY_ADDR_3 + PF2 Table Entry 3 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_3 + PF2 Table Entry 3 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_3 + PF2 Table Entry 3 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_3 + PF2 Table Entry 3 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_3 + PF2 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_4 + PF2 Table Entry 4 Type + 0x00 + + + C_PF2_ENTRY_BAR_4 + PF2 Table Entry 4 BAR + 0 + + + C_PF2_ENTRY_ADDR_4 + PF2 Table Entry 4 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_4 + PF2 Table Entry 4 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_4 + PF2 Table Entry 4 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_4 + PF2 Table Entry 4 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_5 + PF2 Table Entry 5 Type + 0x00 + + + C_PF2_ENTRY_BAR_5 + PF2 Table Entry 5 BAR + 0 + + + C_PF2_ENTRY_ADDR_5 + PF2 Table Entry 5 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_5 + PF2 Table Entry 5 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_5 + PF2 Table Entry 5 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_5 + PF2 Table Entry 5 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_5 + PF2 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_6 + PF2 Table Entry 6 Type + 0x00 + + + C_PF2_ENTRY_BAR_6 + PF2 Table Entry 6 BAR + 0 + + + C_PF2_ENTRY_ADDR_6 + PF2 Table Entry 6 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_6 + PF2 Table Entry 6 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_6 + PF2 Table Entry 6 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_6 + PF2 Table Entry 6 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_6 + PF2 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_7 + PF2 Table Entry 7 Type + 0x00 + + + C_PF2_ENTRY_BAR_7 + PF2 Table Entry 7 BAR + 0 + + + C_PF2_ENTRY_ADDR_7 + PF2 Table Entry 7 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_7 + PF2 Table Entry 7 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_7 + PF2 Table Entry 7 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_7 + PF2 Table Entry 7 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_7 + PF2 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_8 + PF2 Table Entry 8 Type + 0x00 + + + C_PF2_ENTRY_BAR_8 + PF2 Table Entry 8 BAR + 0 + + + C_PF2_ENTRY_ADDR_8 + PF2 Table Entry 8 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_8 + PF2 Table Entry 8 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_8 + PF2 Table Entry 8 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_8 + PF2 Table Entry 8 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_8 + PF2 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_9 + PF2 Table Entry 9 Type + 0x00 + + + C_PF2_ENTRY_BAR_9 + PF2 Table Entry 9 BAR + 0 + + + C_PF2_ENTRY_ADDR_9 + PF2 Table Entry 9 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_9 + PF2 Table Entry 9 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_9 + PF2 Table Entry 9 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_9 + PF2 Table Entry 9 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_9 + PF2 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_10 + PF2 Table Entry 10 Type + 0x00 + + + C_PF2_ENTRY_BAR_10 + PF2 Table Entry 10 BAR + 0 + + + C_PF2_ENTRY_ADDR_10 + PF2 Table Entry 10 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_10 + PF2 Table Entry 10 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_10 + PF2 Table Entry 10 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_10 + PF2 Table Entry 10 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_10 + PF2 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_11 + PF2 Table Entry 11 Type + 0x00 + + + C_PF2_ENTRY_BAR_11 + PF2 Table Entry 11 BAR + 0 + + + C_PF2_ENTRY_ADDR_11 + PF2 Table Entry 11 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_11 + PF2 Table Entry 11 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_11 + PF2 Table Entry 11 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_11 + PF2 Table Entry 11 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_11 + PF2 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_12 + PF2 Table Entry 12 Type + 0x00 + + + C_PF2_ENTRY_BAR_12 + PF2 Table Entry 12 BAR + 0 + + + C_PF2_ENTRY_ADDR_12 + PF2 Table Entry 12 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_12 + PF2 Table Entry 12 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_12 + PF2 Table Entry 12 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_12 + PF2 Table Entry 12 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_12 + PF2 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_13 + PF2 Table Entry 13 Type + 0x00 + + + C_PF2_ENTRY_BAR_13 + PF2 Table Entry 13 BAR + 0 + + + C_PF2_ENTRY_ADDR_13 + PF2 Table Entry 13 Address + 0x000000000000 + + + C_PF2_ENTRY_MAJOR_VERSION_13 + PF2 Table Entry 13 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_13 + PF2 Table Entry 13 Minor Version + 0 + + + C_PF2_ENTRY_VERSION_TYPE_13 + PF2 Table Entry 13 Version Type + 0x00 + + + C_PF2_ENTRY_RSVD0_13 + PF2 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF2_S_AXI_ADDR_WIDTH + PF2 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF3 + 1 + + + C_PF3_BAR_INDEX + PF3 BAR Index + 0 + + + C_PF3_LOW_OFFSET + PF3 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF3_HIGH_OFFSET + PF3 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF3_ENTRY_TYPE_0 + PF3 Table Entry 0 Type + 0x00 + + + C_PF3_ENTRY_BAR_0 + PF3 Table Entry 0 BAR + 0 + + + C_PF3_ENTRY_ADDR_0 + PF3 Table Entry 0 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_0 + PF3 Table Entry 0 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_0 + PF3 Table Entry 0 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_0 + PF3 Table Entry 0 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_0 + PF3 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_1 + PF3 Table Entry 1 Type + 0x00 + + + C_PF3_ENTRY_BAR_1 + PF3 Table Entry 1 BAR + 0 + + + C_PF3_ENTRY_ADDR_1 + PF3 Table Entry 1 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_1 + PF3 Table Entry 1 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_1 + PF3 Table Entry 1 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_1 + PF3 Table Entry 1 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_1 + PF3 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_2 + PF3 Table Entry 2 Type + 0x00 + + + C_PF3_ENTRY_BAR_2 + PF3 Table Entry 2 BAR + 0 + + + C_PF3_ENTRY_ADDR_2 + PF3 Table Entry 2 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_2 + PF3 Table Entry 2 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_2 + PF3 Table Entry 2 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_2 + PF3 Table Entry 2 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_2 + PF3 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_3 + PF3 Table Entry 3 Type + 0x00 + + + C_PF3_ENTRY_BAR_3 + PF3 Table Entry 3 BAR + 0 + + + C_PF3_ENTRY_ADDR_3 + PF3 Table Entry 3 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_3 + PF3 Table Entry 3 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_3 + PF3 Table Entry 3 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_3 + PF3 Table Entry 3 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_3 + PF3 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_4 + PF3 Table Entry 4 Type + 0x00 + + + C_PF3_ENTRY_BAR_4 + PF3 Table Entry 4 BAR + 0 + + + C_PF3_ENTRY_ADDR_4 + PF3 Table Entry 4 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_4 + PF3 Table Entry 4 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_4 + PF3 Table Entry 4 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_4 + PF3 Table Entry 4 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_5 + PF3 Table Entry 5 Type + 0x00 + + + C_PF3_ENTRY_BAR_5 + PF3 Table Entry 5 BAR + 0 + + + C_PF3_ENTRY_ADDR_5 + PF3 Table Entry 5 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_5 + PF3 Table Entry 5 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_5 + PF3 Table Entry 5 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_5 + PF3 Table Entry 5 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_5 + PF3 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_6 + PF3 Table Entry 6 Type + 0x00 + + + C_PF3_ENTRY_BAR_6 + PF3 Table Entry 6 BAR + 0 + + + C_PF3_ENTRY_ADDR_6 + PF3 Table Entry 6 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_6 + PF3 Table Entry 6 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_6 + PF3 Table Entry 6 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_6 + PF3 Table Entry 6 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_6 + PF3 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_7 + PF3 Table Entry 7 Type + 0x00 + + + C_PF3_ENTRY_BAR_7 + PF3 Table Entry 7 BAR + 0 + + + C_PF3_ENTRY_ADDR_7 + PF3 Table Entry 7 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_7 + PF3 Table Entry 7 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_7 + PF3 Table Entry 7 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_7 + PF3 Table Entry 7 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_7 + PF3 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_8 + PF3 Table Entry 8 Type + 0x00 + + + C_PF3_ENTRY_BAR_8 + PF3 Table Entry 8 BAR + 0 + + + C_PF3_ENTRY_ADDR_8 + PF3 Table Entry 8 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_8 + PF3 Table Entry 8 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_8 + PF3 Table Entry 8 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_8 + PF3 Table Entry 8 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_8 + PF3 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_9 + PF3 Table Entry 9 Type + 0x00 + + + C_PF3_ENTRY_BAR_9 + PF3 Table Entry 9 BAR + 0 + + + C_PF3_ENTRY_ADDR_9 + PF3 Table Entry 9 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_9 + PF3 Table Entry 9 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_9 + PF3 Table Entry 9 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_9 + PF3 Table Entry 9 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_9 + PF3 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_10 + PF3 Table Entry 10 Type + 0x00 + + + C_PF3_ENTRY_BAR_10 + PF3 Table Entry 10 BAR + 0 + + + C_PF3_ENTRY_ADDR_10 + PF3 Table Entry 10 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_10 + PF3 Table Entry 10 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_10 + PF3 Table Entry 10 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_10 + PF3 Table Entry 10 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_10 + PF3 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_11 + PF3 Table Entry 11 Type + 0x00 + + + C_PF3_ENTRY_BAR_11 + PF3 Table Entry 11 BAR + 0 + + + C_PF3_ENTRY_ADDR_11 + PF3 Table Entry 11 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_11 + PF3 Table Entry 11 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_11 + PF3 Table Entry 11 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_11 + PF3 Table Entry 11 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_11 + PF3 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_12 + PF3 Table Entry 12 Type + 0x00 + + + C_PF3_ENTRY_BAR_12 + PF3 Table Entry 12 BAR + 0 + + + C_PF3_ENTRY_ADDR_12 + PF3 Table Entry 12 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_12 + PF3 Table Entry 12 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_12 + PF3 Table Entry 12 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_12 + PF3 Table Entry 12 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_12 + PF3 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_13 + PF3 Table Entry 13 Type + 0x00 + + + C_PF3_ENTRY_BAR_13 + PF3 Table Entry 13 BAR + 0 + + + C_PF3_ENTRY_ADDR_13 + PF3 Table Entry 13 Address + 0x000000000000 + + + C_PF3_ENTRY_MAJOR_VERSION_13 + PF3 Table Entry 13 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_13 + PF3 Table Entry 13 Minor Version + 0 + + + C_PF3_ENTRY_VERSION_TYPE_13 + PF3 Table Entry 13 Version Type + 0x00 + + + C_PF3_ENTRY_RSVD0_13 + PF3 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF3_S_AXI_ADDR_WIDTH + PF3 AXI Interface Address Width + 32 + + + + false + + + + + + C_XDEVICEFAMILY + no_family + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + hw_discovery_v1_0_0 + + + + xilinx_examples_view_fileset + + ttcl/example_wrapper_sv.xit + xit + hw_discovery_v1_0_0 + + + + xilinx_examplesscriptext_view_fileset + + ttcl/example_scriptext.tcl + tclSource + hw_discovery_v1_0_0 + + + + xilinx_examplesscriptext_xilinx_com_ip_axi_vip_1_1__ref_view_fileset + + + + + + + + + + xilinx_examplessimulation_view_fileset + + ttcl/example_tb_sv.xit + xit + + + + xilinx_xpgui_view_fileset + + xgui/hw_discovery_v1_0.tcl + tclSource + XGUI_VERSION_2 + hw_discovery_v1_0_0 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/pcie_vsec.vhd + vhdlSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + hdl/bar_layout_table.vhd + vhdlSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + hdl/hw_disc.vhd + vhdlSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + hdl/hw_discovery.v + verilogSource + USED_IN_ipstatic + hw_discovery_v1_0_0 + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/pcie_vsec.vhd + vhdlSource + hw_discovery_v1_0_0 + + + hdl/bar_layout_table.vhd + vhdlSource + hw_discovery_v1_0_0 + + + hdl/hw_disc.vhd + vhdlSource + hw_discovery_v1_0_0 + + + hdl/hw_discovery.v + verilogSource + CHECKSUM_dd4357f8 + hw_discovery_v1_0_0 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + xilinx_versioninformation_view_fileset + + doc/hw_discovery_v1_0_changelog.txt + text + hw_discovery_v1_0_0 + + + + The HW Discovery IP provides PCIe VSEC supporting Xilinx ALF and Bar Layout table. + + + Component_Name + hw_discovery_0 + + + C_MANUAL + Manually Configure + 1 + + + C_NUM_PFS + NUMBER OF PFs + 1 + + + C_INJECT_ENDPOINTS + Inject Endpoint Info for Test + 0 + + + C_PF0_ENDPOINT_NAMES + PF0 List of Endpoint Names + 0 + + + C_PF1_ENDPOINT_NAMES + PF1 List of Endpoint Names + 0 + + + + false + + + + + + C_PF2_ENDPOINT_NAMES + PF2 List of Endpoint Names + 0 + + + + false + + + + + + C_PF3_ENDPOINT_NAMES + PF3 List of Endpoint Names + 0 + + + + false + + + + + + C_CAP_BASE_ADDR + PCIe Extended Capability Base Address + 0x000 + + + C_NEXT_CAP_ADDR + Next Capability Pointer + 0x000 + + + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF0 + 1 + + + C_PF0_BAR_INDEX + PF0 BAR Index + 0 + + + C_PF0_LOW_OFFSET + PF0 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF0_HIGH_OFFSET + PF0 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF0_S_AXI_ADDR_WIDTH + PF0 AXI Interface Address Width + 32 + + + C_PF0_ENTRY_TYPE_0 + PF0 Table Entry 0 Type + 0x00 + + + C_PF0_ENTRY_BAR_0 + PF0 Table Entry 0 BAR + 0 + + + C_PF0_ENTRY_ADDR_0 + PF0 Table Entry 0 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_0 + PF0 Table Entry 0 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_0 + PF0 Table Entry 0 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_0 + PF0 Table Entry 0 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_0 + PF0 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_1 + PF0 Table Entry 1 Type + 0x00 + + + C_PF0_ENTRY_BAR_1 + PF0 Table Entry 1 BAR + 0 + + + C_PF0_ENTRY_ADDR_1 + PF0 Table Entry 1 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_1 + PF0 Table Entry 1 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_1 + PF0 Table Entry 1 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_1 + PF0 Table Entry 1 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_1 + PF0 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_2 + PF0 Table Entry 2 Type + 0x00 + + + C_PF0_ENTRY_BAR_2 + PF0 Table Entry 2 BAR + 0 + + + C_PF0_ENTRY_ADDR_2 + PF0 Table Entry 2 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_2 + PF0 Table Entry 2 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_2 + PF0 Table Entry 2 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_2 + PF0 Table Entry 2 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_2 + PF0 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_3 + PF0 Table Entry 3 Type + 0x00 + + + C_PF0_ENTRY_BAR_3 + PF0 Table Entry 3 BAR + 0 + + + C_PF0_ENTRY_ADDR_3 + PF0 Table Entry 3 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_3 + PF0 Table Entry 3 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_3 + PF0 Table Entry 3 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_3 + PF0 Table Entry 3 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_3 + PF0 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_4 + PF0 Table Entry 4 Type + 0x00 + + + C_PF0_ENTRY_BAR_4 + PF0 Table Entry 4 BAR + 0 + + + C_PF0_ENTRY_ADDR_4 + PF0 Table Entry 4 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_4 + PF0 Table Entry 4 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_4 + PF0 Table Entry 4 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_4 + PF0 Table Entry 4 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_5 + PF0 Table Entry 5 Type + 0x00 + + + C_PF0_ENTRY_BAR_5 + PF0 Table Entry 5 BAR + 0 + + + C_PF0_ENTRY_ADDR_5 + PF0 Table Entry 5 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_5 + PF0 Table Entry 5 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_5 + PF0 Table Entry 5 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_5 + PF0 Table Entry 5 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_5 + PF0 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_6 + PF0 Table Entry 6 Type + 0x00 + + + C_PF0_ENTRY_BAR_6 + PF0 Table Entry 6 BAR + 0 + + + C_PF0_ENTRY_ADDR_6 + PF0 Table Entry 6 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_6 + PF0 Table Entry 6 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_6 + PF0 Table Entry 6 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_6 + PF0 Table Entry 6 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_6 + PF0 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_7 + PF0 Table Entry 7 Type + 0x00 + + + C_PF0_ENTRY_BAR_7 + PF0 Table Entry 7 BAR + 0 + + + C_PF0_ENTRY_ADDR_7 + PF0 Table Entry 7 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_7 + PF0 Table Entry 7 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_7 + PF0 Table Entry 7 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_7 + PF0 Table Entry 7 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_7 + PF0 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_8 + PF0 Table Entry 8 Type + 0x00 + + + C_PF0_ENTRY_BAR_8 + PF0 Table Entry 8 BAR + 0 + + + C_PF0_ENTRY_ADDR_8 + PF0 Table Entry 8 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_8 + PF0 Table Entry 8 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_8 + PF0 Table Entry 8 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_8 + PF0 Table Entry 8 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_8 + PF0 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_9 + PF0 Table Entry 9 Type + 0x00 + + + C_PF0_ENTRY_BAR_9 + PF0 Table Entry 9 BAR + 0 + + + C_PF0_ENTRY_ADDR_9 + PF0 Table Entry 9 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_9 + PF0 Table Entry 9 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_9 + PF0 Table Entry 9 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_9 + PF0 Table Entry 9 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_9 + PF0 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_10 + PF0 Table Entry 10 Type + 0x00 + + + C_PF0_ENTRY_BAR_10 + PF0 Table Entry 10 BAR + 0 + + + C_PF0_ENTRY_ADDR_10 + PF0 Table Entry 10 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_10 + PF0 Table Entry 10 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_10 + PF0 Table Entry 10 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_10 + PF0 Table Entry 10 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_10 + PF0 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_11 + PF0 Table Entry 11 Type + 0x00 + + + C_PF0_ENTRY_BAR_11 + PF0 Table Entry 11 BAR + 0 + + + C_PF0_ENTRY_ADDR_11 + PF0 Table Entry 11 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_11 + PF0 Table Entry 11 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_11 + PF0 Table Entry 11 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_11 + PF0 Table Entry 11 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_11 + PF0 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_12 + PF0 Table Entry 12 Type + 0x00 + + + C_PF0_ENTRY_BAR_12 + PF0 Table Entry 12 BAR + 0 + + + C_PF0_ENTRY_ADDR_12 + PF0 Table Entry 12 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_12 + PF0 Table Entry 12 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_12 + PF0 Table Entry 12 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_12 + PF0 Table Entry 12 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_12 + PF0 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF0_ENTRY_TYPE_13 + PF0 Table Entry 13 Type + 0x00 + + + C_PF0_ENTRY_BAR_13 + PF0 Table Entry 13 BAR + 0 + + + C_PF0_ENTRY_ADDR_13 + PF0 Table Entry 13 Address + 0x000000000000 + + + C_PF0_ENTRY_VERSION_TYPE_13 + PF0 Table Entry 13 Version Type + 0x00 + + + C_PF0_ENTRY_MAJOR_VERSION_13 + PF0 Table Entry 13 Major Version + 0 + + + C_PF0_ENTRY_MINOR_VERSION_13 + PF0 Table Entry 13 Minor Version + 0 + + + C_PF0_ENTRY_RSVD0_13 + PF0 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF1 + 1 + + + C_PF1_BAR_INDEX + PF1 BAR Index + 0 + + + C_PF1_LOW_OFFSET + PF1 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF1_HIGH_OFFSET + PF1 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF1_S_AXI_ADDR_WIDTH + PF1 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF1_ENTRY_TYPE_0 + PF1 Table Entry 0 Type + 0x00 + + + C_PF1_ENTRY_BAR_0 + PF1 Table Entry 0 BAR + 0 + + + C_PF1_ENTRY_ADDR_0 + PF1 Table Entry 0 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_0 + PF1 Table Entry 0 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_0 + PF1 Table Entry 0 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_0 + PF1 Table Entry 0 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_0 + PF1 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_1 + PF1 Table Entry 1 Type + 0x00 + + + C_PF1_ENTRY_BAR_1 + PF1 Table Entry 1 BAR + 0 + + + C_PF1_ENTRY_ADDR_1 + PF1 Table Entry 1 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_1 + PF1 Table Entry 1 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_1 + PF1 Table Entry 1 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_1 + PF1 Table Entry 1 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_1 + PF1 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_2 + PF1 Table Entry 2 Type + 0x00 + + + C_PF1_ENTRY_BAR_2 + PF1 Table Entry 2 BAR + 0 + + + C_PF1_ENTRY_ADDR_2 + PF1 Table Entry 2 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_2 + PF1 Table Entry 2 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_2 + PF1 Table Entry 2 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_2 + PF1 Table Entry 2 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_2 + PF1 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_3 + PF1 Table Entry 3 Type + 0x00 + + + C_PF1_ENTRY_BAR_3 + PF1 Table Entry 3 BAR + 0 + + + C_PF1_ENTRY_ADDR_3 + PF1 Table Entry 3 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_3 + PF1 Table Entry 3 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_3 + PF1 Table Entry 3 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_3 + PF1 Table Entry 3 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_3 + PF1 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_4 + PF1 Table Entry 4 Type + 0x00 + + + C_PF1_ENTRY_BAR_4 + PF1 Table Entry 4 BAR + 0 + + + C_PF1_ENTRY_ADDR_4 + PF1 Table Entry 4 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_4 + PF1 Table Entry 4 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_4 + PF1 Table Entry 4 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_4 + PF1 Table Entry 4 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_5 + PF1 Table Entry 5 Type + 0x00 + + + C_PF1_ENTRY_BAR_5 + PF1 Table Entry 5 BAR + 0 + + + C_PF1_ENTRY_ADDR_5 + PF1 Table Entry 5 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_5 + PF1 Table Entry 5 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_5 + PF1 Table Entry 5 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_5 + PF1 Table Entry 5 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_5 + PF1 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_6 + PF1 Table Entry 6 Type + 0x00 + + + C_PF1_ENTRY_BAR_6 + PF1 Table Entry 6 BAR + 0 + + + C_PF1_ENTRY_ADDR_6 + PF1 Table Entry 6 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_6 + PF1 Table Entry 6 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_6 + PF1 Table Entry 6 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_6 + PF1 Table Entry 6 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_6 + PF1 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_7 + PF1 Table Entry 7 Type + 0x00 + + + C_PF1_ENTRY_BAR_7 + PF1 Table Entry 7 BAR + 0 + + + C_PF1_ENTRY_ADDR_7 + PF1 Table Entry 7 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_7 + PF1 Table Entry 7 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_7 + PF1 Table Entry 7 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_7 + PF1 Table Entry 7 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_7 + PF1 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_8 + PF1 Table Entry 8 Type + 0x00 + + + C_PF1_ENTRY_BAR_8 + PF1 Table Entry 8 BAR + 0 + + + C_PF1_ENTRY_ADDR_8 + PF1 Table Entry 8 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_8 + PF1 Table Entry 8 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_8 + PF1 Table Entry 8 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_8 + PF1 Table Entry 8 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_8 + PF1 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_9 + PF1 Table Entry 9 Type + 0x00 + + + C_PF1_ENTRY_BAR_9 + PF1 Table Entry 9 BAR + 0 + + + C_PF1_ENTRY_ADDR_9 + PF1 Table Entry 9 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_9 + PF1 Table Entry 9 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_9 + PF1 Table Entry 9 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_9 + PF1 Table Entry 9 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_9 + PF1 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_10 + PF1 Table Entry 10 Type + 0x00 + + + C_PF1_ENTRY_BAR_10 + PF1 Table Entry 10 BAR + 0 + + + C_PF1_ENTRY_ADDR_10 + PF1 Table Entry 10 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_10 + PF1 Table Entry 10 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_10 + PF1 Table Entry 10 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_10 + PF1 Table Entry 10 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_10 + PF1 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_11 + PF1 Table Entry 11 Type + 0x00 + + + C_PF1_ENTRY_BAR_11 + PF1 Table Entry 11 BAR + 0 + + + C_PF1_ENTRY_ADDR_11 + PF1 Table Entry 11 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_11 + PF1 Table Entry 11 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_11 + PF1 Table Entry 11 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_11 + PF1 Table Entry 11 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_11 + PF1 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_12 + PF1 Table Entry 12 Type + 0x00 + + + C_PF1_ENTRY_BAR_12 + PF1 Table Entry 12 BAR + 0 + + + C_PF1_ENTRY_ADDR_12 + PF1 Table Entry 12 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_12 + PF1 Table Entry 12 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_12 + PF1 Table Entry 12 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_12 + PF1 Table Entry 12 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_12 + PF1 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF1_ENTRY_TYPE_13 + PF1 Table Entry 13 Type + 0x00 + + + C_PF1_ENTRY_BAR_13 + PF1 Table Entry 13 BAR + 0 + + + C_PF1_ENTRY_ADDR_13 + PF1 Table Entry 13 Address + 0x000000000000 + + + C_PF1_ENTRY_VERSION_TYPE_13 + PF1 Table Entry 13 Version Type + 0x00 + + + C_PF1_ENTRY_MAJOR_VERSION_13 + PF1 Table Entry 13 Major Version + 0 + + + C_PF1_ENTRY_MINOR_VERSION_13 + PF1 Table Entry 13 Minor Version + 0 + + + C_PF1_ENTRY_RSVD0_13 + PF1 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF2 + 1 + + + C_PF2_BAR_INDEX + PF2 BAR Index + 0 + + + C_PF2_LOW_OFFSET + PF2 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF2_HIGH_OFFSET + PF2 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF2_S_AXI_ADDR_WIDTH + PF2 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF2_ENTRY_TYPE_0 + PF2 Table Entry 0 Type + 0x00 + + + C_PF2_ENTRY_BAR_0 + PF2 Table Entry 0 BAR + 0 + + + C_PF2_ENTRY_ADDR_0 + PF2 Table Entry 0 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_0 + PF2 Table Entry 0 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_0 + PF2 Table Entry 0 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_0 + PF2 Table Entry 0 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_0 + PF2 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_1 + PF2 Table Entry 1 Type + 0x00 + + + C_PF2_ENTRY_BAR_1 + PF2 Table Entry 1 BAR + 0 + + + C_PF2_ENTRY_ADDR_1 + PF2 Table Entry 1 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_1 + PF2 Table Entry 1 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_1 + PF2 Table Entry 1 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_1 + PF2 Table Entry 1 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_1 + PF2 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_2 + PF2 Table Entry 2 Type + 0x00 + + + C_PF2_ENTRY_BAR_2 + PF2 Table Entry 2 BAR + 0 + + + C_PF2_ENTRY_ADDR_2 + PF2 Table Entry 2 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_2 + PF2 Table Entry 2 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_2 + PF2 Table Entry 2 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_2 + PF2 Table Entry 2 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_2 + PF2 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_3 + PF2 Table Entry 3 Type + 0x00 + + + C_PF2_ENTRY_BAR_3 + PF2 Table Entry 3 BAR + 0 + + + C_PF2_ENTRY_ADDR_3 + PF2 Table Entry 3 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_3 + PF2 Table Entry 3 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_3 + PF2 Table Entry 3 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_3 + PF2 Table Entry 3 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_3 + PF2 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_4 + PF2 Table Entry 4 Type + 0x00 + + + C_PF2_ENTRY_BAR_4 + PF2 Table Entry 4 BAR + 0 + + + C_PF2_ENTRY_ADDR_4 + PF2 Table Entry 4 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_4 + PF2 Table Entry 4 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_4 + PF2 Table Entry 4 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_4 + PF2 Table Entry 4 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_5 + PF2 Table Entry 5 Type + 0x00 + + + C_PF2_ENTRY_BAR_5 + PF2 Table Entry 5 BAR + 0 + + + C_PF2_ENTRY_ADDR_5 + PF2 Table Entry 5 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_5 + PF2 Table Entry 5 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_5 + PF2 Table Entry 5 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_5 + PF2 Table Entry 5 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_5 + PF2 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_6 + PF2 Table Entry 6 Type + 0x00 + + + C_PF2_ENTRY_BAR_6 + PF2 Table Entry 6 BAR + 0 + + + C_PF2_ENTRY_ADDR_6 + PF2 Table Entry 6 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_6 + PF2 Table Entry 6 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_6 + PF2 Table Entry 6 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_6 + PF2 Table Entry 6 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_6 + PF2 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_7 + PF2 Table Entry 7 Type + 0x00 + + + C_PF2_ENTRY_BAR_7 + PF2 Table Entry 7 BAR + 0 + + + C_PF2_ENTRY_ADDR_7 + PF2 Table Entry 7 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_7 + PF2 Table Entry 7 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_7 + PF2 Table Entry 7 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_7 + PF2 Table Entry 7 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_7 + PF2 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_8 + PF2 Table Entry 8 Type + 0x00 + + + C_PF2_ENTRY_BAR_8 + PF2 Table Entry 8 BAR + 0 + + + C_PF2_ENTRY_ADDR_8 + PF2 Table Entry 8 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_8 + PF2 Table Entry 8 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_8 + PF2 Table Entry 8 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_8 + PF2 Table Entry 8 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_8 + PF2 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_9 + PF2 Table Entry 9 Type + 0x00 + + + C_PF2_ENTRY_BAR_9 + PF2 Table Entry 9 BAR + 0 + + + C_PF2_ENTRY_ADDR_9 + PF2 Table Entry 9 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_9 + PF2 Table Entry 9 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_9 + PF2 Table Entry 9 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_9 + PF2 Table Entry 9 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_9 + PF2 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_10 + PF2 Table Entry 10 Type + 0x00 + + + C_PF2_ENTRY_BAR_10 + PF2 Table Entry 10 BAR + 0 + + + C_PF2_ENTRY_ADDR_10 + PF2 Table Entry 10 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_10 + PF2 Table Entry 10 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_10 + PF2 Table Entry 10 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_10 + PF2 Table Entry 10 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_10 + PF2 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_11 + PF2 Table Entry 11 Type + 0x00 + + + C_PF2_ENTRY_BAR_11 + PF2 Table Entry 11 BAR + 0 + + + C_PF2_ENTRY_ADDR_11 + PF2 Table Entry 11 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_11 + PF2 Table Entry 11 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_11 + PF2 Table Entry 11 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_11 + PF2 Table Entry 11 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_11 + PF2 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_12 + PF2 Table Entry 12 Type + 0x00 + + + C_PF2_ENTRY_BAR_12 + PF2 Table Entry 12 BAR + 0 + + + C_PF2_ENTRY_ADDR_12 + PF2 Table Entry 12 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_12 + PF2 Table Entry 12 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_12 + PF2 Table Entry 12 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_12 + PF2 Table Entry 12 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_12 + PF2 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF2_ENTRY_TYPE_13 + PF2 Table Entry 13 Type + 0x00 + + + C_PF2_ENTRY_BAR_13 + PF2 Table Entry 13 BAR + 0 + + + C_PF2_ENTRY_ADDR_13 + PF2 Table Entry 13 Address + 0x000000000000 + + + C_PF2_ENTRY_VERSION_TYPE_13 + PF2 Table Entry 13 Version Type + 0x00 + + + C_PF2_ENTRY_MAJOR_VERSION_13 + PF2 Table Entry 13 Major Version + 0 + + + C_PF2_ENTRY_MINOR_VERSION_13 + PF2 Table Entry 13 Minor Version + 0 + + + C_PF2_ENTRY_RSVD0_13 + PF2 Table Entry 13 Reserved Field 0 + 0x0 + + + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + Number of Bar Layout Table Entries for PF3 + 1 + + + C_PF3_BAR_INDEX + PF3 BAR Index + 0 + + + C_PF3_LOW_OFFSET + PF3 BAR Layout Table Low Address Offset + 0x0000000 + + + C_PF3_HIGH_OFFSET + PF3 BAR Layout Table High Address Offset + 0x00000000 + + + C_PF3_S_AXI_ADDR_WIDTH + PF3 AXI Interface Address Width + 32 + + + + false + + + + + + C_PF3_ENTRY_TYPE_0 + PF3 Table Entry 0 Type + 0x00 + + + C_PF3_ENTRY_BAR_0 + PF3 Table Entry 0 BAR + 0 + + + C_PF3_ENTRY_ADDR_0 + PF3 Table Entry 0 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_0 + PF3 Table Entry 0 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_0 + PF3 Table Entry 0 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_0 + PF3 Table Entry 0 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_0 + PF3 Table Entry 0 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_1 + PF3 Table Entry 1 Type + 0x00 + + + C_PF3_ENTRY_BAR_1 + PF3 Table Entry 1 BAR + 0 + + + C_PF3_ENTRY_ADDR_1 + PF3 Table Entry 1 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_1 + PF3 Table Entry 1 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_1 + PF3 Table Entry 1 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_1 + PF3 Table Entry 1 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_1 + PF3 Table Entry 1 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_2 + PF3 Table Entry 2 Type + 0x00 + + + C_PF3_ENTRY_BAR_2 + PF3 Table Entry 2 BAR + 0 + + + C_PF3_ENTRY_ADDR_2 + PF3 Table Entry 2 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_2 + PF3 Table Entry 2 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_2 + PF3 Table Entry 2 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_2 + PF3 Table Entry 2 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_2 + PF3 Table Entry 2 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_3 + PF3 Table Entry 3 Type + 0x00 + + + C_PF3_ENTRY_BAR_3 + PF3 Table Entry 3 BAR + 0 + + + C_PF3_ENTRY_ADDR_3 + PF3 Table Entry 3 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_3 + PF3 Table Entry 3 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_3 + PF3 Table Entry 3 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_3 + PF3 Table Entry 3 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_3 + PF3 Table Entry 3 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_4 + PF3 Table Entry 4 Type + 0x00 + + + C_PF3_ENTRY_BAR_4 + PF3 Table Entry 4 BAR + 0 + + + C_PF3_ENTRY_ADDR_4 + PF3 Table Entry 4 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_4 + PF3 Table Entry 4 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_4 + PF3 Table Entry 4 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_4 + PF3 Table Entry 4 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_4 + Table Entry 4 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_5 + PF3 Table Entry 5 Type + 0x00 + + + C_PF3_ENTRY_BAR_5 + PF3 Table Entry 5 BAR + 0 + + + C_PF3_ENTRY_ADDR_5 + PF3 Table Entry 5 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_5 + PF3 Table Entry 5 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_5 + PF3 Table Entry 5 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_5 + PF3 Table Entry 5 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_5 + PF3 Table Entry 5 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_6 + PF3 Table Entry 6 Type + 0x00 + + + C_PF3_ENTRY_BAR_6 + PF3 Table Entry 6 BAR + 0 + + + C_PF3_ENTRY_ADDR_6 + PF3 Table Entry 6 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_6 + PF3 Table Entry 6 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_6 + PF3 Table Entry 6 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_6 + PF3 Table Entry 6 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_6 + PF3 Table Entry 6 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_7 + PF3 Table Entry 7 Type + 0x00 + + + C_PF3_ENTRY_BAR_7 + PF3 Table Entry 7 BAR + 0 + + + C_PF3_ENTRY_ADDR_7 + PF3 Table Entry 7 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_7 + PF3 Table Entry 7 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_7 + PF3 Table Entry 7 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_7 + PF3 Table Entry 7 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_7 + PF3 Table Entry 7 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_8 + PF3 Table Entry 8 Type + 0x00 + + + C_PF3_ENTRY_BAR_8 + PF3 Table Entry 8 BAR + 0 + + + C_PF3_ENTRY_ADDR_8 + PF3 Table Entry 8 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_8 + PF3 Table Entry 8 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_8 + PF3 Table Entry 8 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_8 + PF3 Table Entry 8 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_8 + PF3 Table Entry 8 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_9 + PF3 Table Entry 9 Type + 0x00 + + + C_PF3_ENTRY_BAR_9 + PF3 Table Entry 9 BAR + 0 + + + C_PF3_ENTRY_ADDR_9 + PF3 Table Entry 9 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_9 + PF3 Table Entry 9 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_9 + PF3 Table Entry 9 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_9 + PF3 Table Entry 9 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_9 + PF3 Table Entry 9 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_10 + PF3 Table Entry 10 Type + 0x00 + + + C_PF3_ENTRY_BAR_10 + PF3 Table Entry 10 BAR + 0 + + + C_PF3_ENTRY_ADDR_10 + PF3 Table Entry 10 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_10 + PF3 Table Entry 10 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_10 + PF3 Table Entry 10 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_10 + PF3 Table Entry 10 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_10 + PF3 Table Entry 10 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_11 + PF3 Table Entry 11 Type + 0x00 + + + C_PF3_ENTRY_BAR_11 + PF3 Table Entry 11 BAR + 0 + + + C_PF3_ENTRY_ADDR_11 + PF3 Table Entry 11 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_11 + PF3 Table Entry 11 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_11 + PF3 Table Entry 11 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_11 + PF3 Table Entry 11 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_11 + PF3 Table Entry 11 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_12 + PF3 Table Entry 12 Type + 0x00 + + + C_PF3_ENTRY_BAR_12 + PF3 Table Entry 12 BAR + 0 + + + C_PF3_ENTRY_ADDR_12 + PF3 Table Entry 12 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_12 + PF3 Table Entry 12 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_12 + PF3 Table Entry 12 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_12 + PF3 Table Entry 12 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_12 + PF3 Table Entry 12 Reserved Field 0 + 0x0 + + + C_PF3_ENTRY_TYPE_13 + PF3 Table Entry 13 Type + 0x00 + + + C_PF3_ENTRY_BAR_13 + PF3 Table Entry 13 BAR + 0 + + + C_PF3_ENTRY_ADDR_13 + PF3 Table Entry 13 Address + 0x000000000000 + + + C_PF3_ENTRY_VERSION_TYPE_13 + PF3 Table Entry 13 Version Type + 0x00 + + + C_PF3_ENTRY_MAJOR_VERSION_13 + PF3 Table Entry 13 Major Version + 0 + + + C_PF3_ENTRY_MINOR_VERSION_13 + PF3 Table Entry 13 Minor Version + 0 + + + C_PF3_ENTRY_RSVD0_13 + PF3 Table Entry 13 Reserved Field 0 + 0x0 + + + + + + /Shell_Subsystems + + HW Discovery + level_beta + (GENERIC_FAMILY = versal) + + XPM_MEMORY + + + IPI + + http://www.xilinx.com/ + 0 + 2023-10-11T08:39:15Z + + + 2023.1 + + + + + + + + + diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/doc/hw_discovery_v1_0_changelog.txt b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/doc/hw_discovery_v1_0_changelog.txt new file mode 100644 index 00000000..d0029c28 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/doc/hw_discovery_v1_0_changelog.txt @@ -0,0 +1,9 @@ +2023.2: + * Version 1.0 (Rev. 1) + * Bug Fix: Upgraded warning to error when required endpoint metadata not found + * Bug Fix: Ports pcie*_cfg_ext function_number width increased to 16 to match cips + +2023.1: + * Version 1.0 + * New Feature: Initial Release + diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/bar_layout_table.vhd b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/bar_layout_table.vhd new file mode 100644 index 00000000..c06a188c --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/bar_layout_table.vhd @@ -0,0 +1,457 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +library hw_discovery_v1_0_0; + +entity hw_discovery_v1_0_0_bar_layout_table is + generic ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_XDEVICEFAMILY : string := "no_family" + ); + port ( + + ----------------------------------------------------------------------- + -- Processor AXI Interface (S_AXI_ACLK) + ----------------------------------------------------------------------- + + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic + ); + +end hw_discovery_v1_0_0_bar_layout_table; + + +architecture top of hw_discovery_v1_0_0_bar_layout_table is + + + ------------------------------------------------------------------------------- + -- Constant Declarations + ------------------------------------------------------------------------------- + + constant ZEROES : std_logic_vector(0 to 31) := X"00000000"; + + constant C_FAMILY : string := C_XDEVICEFAMILY; + + constant REG_BASEADDR : std_logic_vector := X"00000000"; + + impure function makemask (Width: INTEGER) return std_logic_vector is + variable retv: std_logic_vector (31 downto 0) := (others => '0'); + begin + for i in (Width - 1) downto 0 loop + retv(i) := '1'; + end loop; + return retv; + end function; + + constant REG_HIGHADDR : std_logic_vector(0 to 31) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( + ZEROES & REG_BASEADDR, + ZEROES & REG_HIGHADDR + ); + + constant C_ARD_IDX_REGS : integer := 0; + + constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( + C_ARD_IDX_REGS => 1 + ); + + constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_USE_WSTRB : integer := 0; + + constant C_DPHASE_TIMEOUT : integer := 12; + + subtype IIC_CE_RNG is integer range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0) to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0) + C_ARD_NUM_CE_ARRAY(0) - 1; + + attribute ram_style : string; + + -- BAR Layout Table ROM type + type bar_layout_rom_type is array (0 to 63) of std_logic_vector(31 downto 0); + type rom_header_type is array (0 to 3) of std_logic_vector(31 downto 0); + type rom_entry_type is array (0 to 63) of std_logic_vector(31 downto 0); + + -- Field Constants + constant HEADER_FORMAT : std_logic_vector(19 downto 0) := x"00001"; + constant HEADER_REV : std_logic_vector(7 downto 0) := x"00"; + constant HEADER_LAST_CAP : std_logic := '1'; + constant HEADER_RESERVED : std_logic_vector(2 downto 0) := "000"; + constant HEADER_LENGTH : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned((C_NUM_SLOTS_BAR_LAYOUT_TABLE * 16) + 32, 32)); + constant FORMAT_ENTRY_SIZE : std_logic_vector(7 downto 0) := x"10"; + constant ENTRY_REVISION : std_logic_vector(4 downto 0) := (others => '0'); + constant ENTRY_END_OF_TABLE : std_logic_vector(7 downto 0) := (others => '1'); + + constant ROM_HEADER : rom_header_type := (0 => (HEADER_RESERVED & HEADER_LAST_CAP & HEADER_REV & HEADER_FORMAT), + 1 => HEADER_LENGTH, + 2 => (x"000000" & FORMAT_ENTRY_SIZE), + 3 => (others => '0')); + + constant ROM_ENTRIES : rom_entry_type := (0 => (C_ENTRY_ADDR_0(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_0, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_0), + 1 => C_ENTRY_ADDR_0(47 downto 16), + 2 => x"0" & C_ENTRY_RSVD0_0 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_0, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_0, 8)) & C_ENTRY_VERSION_TYPE_0, + 3 => x"00000000", + 4 => (C_ENTRY_ADDR_1(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_1, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_1), + 5 => C_ENTRY_ADDR_1(47 downto 16), + 6 => x"0" & C_ENTRY_RSVD0_1 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_1, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_1, 8)) & C_ENTRY_VERSION_TYPE_1, + 7 => x"00000000", + 8 => (C_ENTRY_ADDR_2(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_2, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_2), + 9 => C_ENTRY_ADDR_2(47 downto 16), + 10 => x"0" & C_ENTRY_RSVD0_2 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_2, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_2, 8)) & C_ENTRY_VERSION_TYPE_2, + 11 => x"00000000", + 12 => (C_ENTRY_ADDR_3(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_3, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_3), + 13 => C_ENTRY_ADDR_3(47 downto 16), + 14 => x"0" & C_ENTRY_RSVD0_3 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_3, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_3, 8)) & C_ENTRY_VERSION_TYPE_3, + 15 => x"00000000", + 16 => (C_ENTRY_ADDR_4(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_4, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_4), + 17 => C_ENTRY_ADDR_4(47 downto 16), + 18 => x"0" & C_ENTRY_RSVD0_4 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_4, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_4, 8)) & C_ENTRY_VERSION_TYPE_4, + 19 => x"00000000", + 20 => (C_ENTRY_ADDR_5(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_5, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_5), + 21 => C_ENTRY_ADDR_5(47 downto 16), + 22 => x"0" & C_ENTRY_RSVD0_5 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_5, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_5, 8)) & C_ENTRY_VERSION_TYPE_5, + 23 => x"00000000", + 24 => (C_ENTRY_ADDR_6(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_6, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_6), + 25 => C_ENTRY_ADDR_6(47 downto 16), + 26 => x"0" & C_ENTRY_RSVD0_6 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_6, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_6, 8)) & C_ENTRY_VERSION_TYPE_6, + 27 => x"00000000", + 28 => (C_ENTRY_ADDR_7(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_7, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_7), + 29 => C_ENTRY_ADDR_7(47 downto 16), + 30 => x"0" & C_ENTRY_RSVD0_7 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_7, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_7, 8)) & C_ENTRY_VERSION_TYPE_7, + 31 => x"00000000", + 32 => (C_ENTRY_ADDR_8(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_8, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_8), + 33 => C_ENTRY_ADDR_8(47 downto 16), + 34 => x"0" & C_ENTRY_RSVD0_8 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_8, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_8, 8)) & C_ENTRY_VERSION_TYPE_8, + 35 => x"00000000", + 36 => (C_ENTRY_ADDR_9(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_9, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_9), + 37 => C_ENTRY_ADDR_9(47 downto 16), + 38 => x"0" & C_ENTRY_RSVD0_9 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_9, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_9, 8)) & C_ENTRY_VERSION_TYPE_9, + 39 => x"00000000", + 40 => (C_ENTRY_ADDR_10(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_10, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_10), + 41 => C_ENTRY_ADDR_10(47 downto 16), + 42 => x"0" & C_ENTRY_RSVD0_10 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_10, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_10, 8)) & C_ENTRY_VERSION_TYPE_10, + 43 => x"00000000", + 44 => (C_ENTRY_ADDR_11(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_11, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_11), + 45 => C_ENTRY_ADDR_11(47 downto 16), + 46 => x"0" & C_ENTRY_RSVD0_11 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_11, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_11, 8)) & C_ENTRY_VERSION_TYPE_11, + 47 => x"00000000", + 48 => (C_ENTRY_ADDR_12(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_12, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_12), + 49 => C_ENTRY_ADDR_12(47 downto 16), + 50 => x"0" & C_ENTRY_RSVD0_12 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_12, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_12, 8)) & C_ENTRY_VERSION_TYPE_12, + 51 => x"00000000", + 52 => (C_ENTRY_ADDR_13(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_13, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_13), + 53 => C_ENTRY_ADDR_13(47 downto 16), + 54 => x"0" & C_ENTRY_RSVD0_13 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_13, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_13, 8)) & C_ENTRY_VERSION_TYPE_13, + 55 => x"00000000", + 56 => (C_ENTRY_ADDR_14(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_14, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_14), + 57 => C_ENTRY_ADDR_14(47 downto 16), + 58 => x"0" & C_ENTRY_RSVD0_14 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_14, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_14, 8)) & C_ENTRY_VERSION_TYPE_14, + 59 => x"00000000", + 60 => (C_ENTRY_ADDR_15(15 downto 0) & std_logic_vector(to_unsigned(C_ENTRY_BAR_15, 3)) & ENTRY_REVISION & C_ENTRY_TYPE_15), + 61 => C_ENTRY_ADDR_15(47 downto 16), + 62 => x"0" & C_ENTRY_RSVD0_15 & std_logic_vector(to_unsigned(C_ENTRY_MAJOR_VERSION_15, 8)) & std_logic_vector(to_unsigned(C_ENTRY_MINOR_VERSION_15, 8)) & C_ENTRY_VERSION_TYPE_15, + 63 => x"00000000"); + + ------------------------------------------------------------------------------- + -- Function Declarations + ------------------------------------------------------------------------------- + + function fn_rom_init return bar_layout_rom_type is + + variable rom : bar_layout_rom_type := (others => (others => '0')); + variable j : integer := 0; + + begin + + -- Insert the ROM Header & Format Fields + for i in rom_header_type'RANGE loop + + rom(i) := ROM_HEADER(i); + + end loop; + + -- Insert the configured table entries + j := 0; + + for i in 4 to (C_NUM_SLOTS_BAR_LAYOUT_TABLE * 4 + 3) loop + + rom(i) := ROM_ENTRIES(j); + j := j + 1; + + end loop; + + -- Insert the end of table entry + rom((C_NUM_SLOTS_BAR_LAYOUT_TABLE * 4 + 4)) := x"000000" & ENTRY_END_OF_TABLE; + + return rom; + + end function; + + ------------------------------------------------------------------------------- + -- Signal Declarations + ------------------------------------------------------------------------------- + + signal Bus2IP_Clk : std_logic := '0'; + signal Bus2IP_Resetn : std_logic := '0'; + signal Bus2IP_Addr : std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0) := (others => '0'); + signal Bus2IP_RNW : std_logic := '0'; + signal Bus2IP_BE : std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0) := (others => '0'); + signal Bus2IP_CS : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2-1) downto 0) := (others => '0'); + signal Bus2IP_RdCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0) := (others => '0'); + signal Bus2IP_WrCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0) := (others => '0'); + signal Bus2IP_Data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0'); + signal IP2Bus_Data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0'); + signal IP2Bus_WrAck : std_logic := '0'; + signal IP2Bus_RdAck : std_logic := '0'; + signal IP2Bus_Error : std_logic := '0'; + signal IP2Bus_Ack : std_logic_vector(1 to 4) := (others => '0'); + signal BAR_Layout_ROM : bar_layout_rom_type := fn_rom_init; + + attribute ram_style of BAR_Layout_ROM : signal is "distributed"; + +begin + + axi_lite_ipif_1 : entity axi_lite_ipif_v3_0_4.axi_lite_ipif + generic map + ( + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, + C_USE_WSTRB => C_USE_WSTRB, + C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, + C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, + C_FAMILY => C_FAMILY + ) + port map ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + Bus2IP_Clk => Bus2IP_Clk, + Bus2IP_Resetn => Bus2IP_Resetn, + Bus2IP_Addr => Bus2IP_Addr, + Bus2IP_RNW => Bus2IP_RNW, + Bus2IP_BE => Bus2IP_BE, + Bus2IP_CS => Bus2IP_CS, + Bus2IP_RdCE => Bus2IP_RdCE, + Bus2IP_WrCE => Bus2IP_WrCE, + Bus2IP_Data => Bus2IP_Data, + IP2Bus_Data => IP2Bus_Data, + IP2Bus_WrAck => IP2Bus_WrAck, + IP2Bus_RdAck => IP2Bus_RdAck, + IP2Bus_Error => IP2Bus_Error + ); + + axi_dec : process(Bus2IP_Clk) + + variable Addr_Slice1 : std_logic_vector(7 downto 2) := (others => '0'); + + begin + + if rising_edge(Bus2IP_Clk) then + + -- Default assignments + IP2Bus_Data <= (others => '0'); + IP2Bus_Ack <= (others => '0'); + IP2Bus_WrAck <= '0'; + IP2Bus_RdAck <= '0'; + + if (Bus2IP_CS(0) = '1') then + + Addr_Slice1 := Bus2IP_Addr(Addr_Slice1'RANGE); + + -- Read the BAR Layout Table ROM + IP2Bus_Data <= BAR_Layout_ROM(to_integer(unsigned(Addr_Slice1))); + + -- Generate the Ack shift reg + IP2Bus_Ack <= '1' & IP2Bus_Ack(1 to IP2Bus_Ack'HIGH-1); + + end if; + + -- Single cycle Rd/Wr Ack to IPIF + if ((IP2Bus_Ack(3) = '1') and (IP2Bus_Ack(4) = '0')) then + + IP2Bus_WrAck <= '1'; + IP2Bus_RdAck <= '1'; + + end if; + + end if; + + end process axi_dec; + + IP2Bus_Error <= '0'; + + +end top; diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_disc.vhd b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_disc.vhd new file mode 100644 index 00000000..468c2eb8 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_disc.vhd @@ -0,0 +1,1285 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_misc.all; + use ieee.numeric_std.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +library xpm; + use xpm.vcomponents.all; + +library hw_discovery_v1_0_0; + +entity hw_discovery_v1_0_0_hw_disc is + generic ( + C_NUM_PFS : integer range 1 to 4 := 1; + C_CAP_BASE_ADDR : std_logic_vector(11 downto 0) := x"480"; -- 0x480 default for PCIE4 + C_NEXT_CAP_ADDR : std_logic_vector(11 downto 0) := (others => '0'); + C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF0_BAR_INDEX : integer range 0 to 6 := 0; + C_PF0_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF0_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF0_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF0_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF0_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF0_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF0_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF0_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF0_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF1_BAR_INDEX : integer range 0 to 6 := 0; + C_PF1_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF1_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF1_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF1_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF1_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF1_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF1_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF1_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF1_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF2_BAR_INDEX : integer range 0 to 6 := 0; + C_PF2_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF2_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF2_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF2_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF2_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF2_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF2_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF2_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF2_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE : integer range 1 to 16 := 1; + C_PF3_BAR_INDEX : integer range 0 to 6 := 0; + C_PF3_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF3_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_0 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_0 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_0 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_0 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_0 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_1 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_1 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_1 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_1 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_1 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_2 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_2 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_2 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_2 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_2 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_3 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_3 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_3 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_3 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_3 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_4 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_4 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_4 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_4 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_4 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_5 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_5 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_5 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_5 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_5 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_6 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_6 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_6 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_6 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_6 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_7 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_7 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_7 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_7 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_7 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_8 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_8 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_8 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_8 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_8 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_9 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_9 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_9 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_9 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_9 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_10 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_10 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_10 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_10 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_10 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_11 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_11 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_11 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_11 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_11 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_12 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_12 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_12 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_12 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_12 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_13 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_13 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_13 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_13 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_13 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_14 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_14 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_14 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_14 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_14 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_ENTRY_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_BAR_15 : integer range 0 to 6 := 0; + C_PF3_ENTRY_ADDR_15 : std_logic_vector(47 downto 0) := (others => '0'); + C_PF3_ENTRY_MAJOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF3_ENTRY_MINOR_VERSION_15 : integer range 0 to 255 := 0; + C_PF3_ENTRY_VERSION_TYPE_15 : std_logic_vector(7 downto 0) := (others => '0'); + C_PF3_ENTRY_RSVD0_15 : std_logic_vector(3 downto 0) := (others => '0'); + C_PF3_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_PF3_S_AXI_ADDR_WIDTH : integer range 1 to 64 := 32; + C_XDEVICEFAMILY : string := "no_family" + ); + port ( + ----------------------------------------------------------------------- + -- Clocks & Resets + ----------------------------------------------------------------------- + + aclk_pcie : in std_logic; + aresetn_pcie : in std_logic; + + aclk_ctrl : in std_logic; + aresetn_ctrl : in std_logic; + + ----------------------------------------------------------------------- + -- slave pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + s_pcie4_cfg_ext_function_number : in std_logic_vector(15 downto 0); + s_pcie4_cfg_ext_read_data : out std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_read_data_valid : out std_logic; + s_pcie4_cfg_ext_read_received : in std_logic; + s_pcie4_cfg_ext_register_number : in std_logic_vector(9 downto 0); + s_pcie4_cfg_ext_write_byte_enable : in std_logic_vector(3 downto 0); + s_pcie4_cfg_ext_write_data : in std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_write_received : in std_logic; + + ----------------------------------------------------------------------- + -- master pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + m_pcie4_cfg_ext_function_number : out std_logic_vector(15 downto 0); + m_pcie4_cfg_ext_read_data : in std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_read_data_valid : in std_logic; + m_pcie4_cfg_ext_read_received : out std_logic; + m_pcie4_cfg_ext_register_number : out std_logic_vector(9 downto 0); + m_pcie4_cfg_ext_write_byte_enable : out std_logic_vector(3 downto 0); + m_pcie4_cfg_ext_write_data : out std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_write_received : out std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF0 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf0_awaddr : in std_logic_vector(C_PF0_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf0_awvalid : in std_logic; + s_axi_ctrl_pf0_awready : out std_logic; + s_axi_ctrl_pf0_wdata : in std_logic_vector(C_PF0_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf0_wstrb : in std_logic_vector((C_PF0_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf0_wvalid : in std_logic; + s_axi_ctrl_pf0_wready : out std_logic; + s_axi_ctrl_pf0_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf0_bvalid : out std_logic; + s_axi_ctrl_pf0_bready : in std_logic; + s_axi_ctrl_pf0_araddr : in std_logic_vector(C_PF0_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf0_arvalid : in std_logic; + s_axi_ctrl_pf0_arready : out std_logic; + s_axi_ctrl_pf0_rdata : out std_logic_vector(C_PF0_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf0_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf0_rvalid : out std_logic; + s_axi_ctrl_pf0_rready : in std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF1 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf1_awaddr : in std_logic_vector(C_PF1_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf1_awvalid : in std_logic; + s_axi_ctrl_pf1_awready : out std_logic; + s_axi_ctrl_pf1_wdata : in std_logic_vector(C_PF1_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf1_wstrb : in std_logic_vector((C_PF1_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf1_wvalid : in std_logic; + s_axi_ctrl_pf1_wready : out std_logic; + s_axi_ctrl_pf1_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf1_bvalid : out std_logic; + s_axi_ctrl_pf1_bready : in std_logic; + s_axi_ctrl_pf1_araddr : in std_logic_vector(C_PF1_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf1_arvalid : in std_logic; + s_axi_ctrl_pf1_arready : out std_logic; + s_axi_ctrl_pf1_rdata : out std_logic_vector(C_PF1_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf1_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf1_rvalid : out std_logic; + s_axi_ctrl_pf1_rready : in std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF2 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf2_awaddr : in std_logic_vector(C_PF2_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf2_awvalid : in std_logic; + s_axi_ctrl_pf2_awready : out std_logic; + s_axi_ctrl_pf2_wdata : in std_logic_vector(C_PF2_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf2_wstrb : in std_logic_vector((C_PF2_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf2_wvalid : in std_logic; + s_axi_ctrl_pf2_wready : out std_logic; + s_axi_ctrl_pf2_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf2_bvalid : out std_logic; + s_axi_ctrl_pf2_bready : in std_logic; + s_axi_ctrl_pf2_araddr : in std_logic_vector(C_PF2_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf2_arvalid : in std_logic; + s_axi_ctrl_pf2_arready : out std_logic; + s_axi_ctrl_pf2_rdata : out std_logic_vector(C_PF2_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf2_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf2_rvalid : out std_logic; + s_axi_ctrl_pf2_rready : in std_logic; + + ----------------------------------------------------------------------- + -- AXI Interface (aclk_ctrl) for PF3 + ----------------------------------------------------------------------- + + s_axi_ctrl_pf3_awaddr : in std_logic_vector(C_PF3_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf3_awvalid : in std_logic; + s_axi_ctrl_pf3_awready : out std_logic; + s_axi_ctrl_pf3_wdata : in std_logic_vector(C_PF3_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf3_wstrb : in std_logic_vector((C_PF3_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_ctrl_pf3_wvalid : in std_logic; + s_axi_ctrl_pf3_wready : out std_logic; + s_axi_ctrl_pf3_bresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf3_bvalid : out std_logic; + s_axi_ctrl_pf3_bready : in std_logic; + s_axi_ctrl_pf3_araddr : in std_logic_vector(C_PF3_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_ctrl_pf3_arvalid : in std_logic; + s_axi_ctrl_pf3_arready : out std_logic; + s_axi_ctrl_pf3_rdata : out std_logic_vector(C_PF3_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_ctrl_pf3_rresp : out std_logic_vector(1 downto 0); + s_axi_ctrl_pf3_rvalid : out std_logic; + s_axi_ctrl_pf3_rready : in std_logic + + ); + +end hw_discovery_v1_0_0_hw_disc; + +architecture rtl of hw_discovery_v1_0_0_hw_disc is + + ------------------------------------------------------------------------------- + -- Constant Declarations + ------------------------------------------------------------------------------- + + -- Constants for AXI4-Lite. + constant ZEROES : std_logic_vector(0 to 31) := (others => '0'); + constant ONES : std_logic_vector(0 to 31) := (others => '1'); + + constant C_FAMILY : string := C_XDEVICEFAMILY; + +begin + + pcie_vsec_inst : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_pcie_vsec + generic map ( + C_NUM_PFS => C_NUM_PFS, + C_CAP_BASE_ADDR => C_CAP_BASE_ADDR, + C_NEXT_CAP_ADDR => C_NEXT_CAP_ADDR, + C_PF0_BAR_INDEX => C_PF0_BAR_INDEX, + C_PF0_LOW_OFFSET => C_PF0_LOW_OFFSET, + C_PF0_HIGH_OFFSET => C_PF0_HIGH_OFFSET, + C_PF1_BAR_INDEX => C_PF1_BAR_INDEX, + C_PF1_LOW_OFFSET => C_PF1_LOW_OFFSET, + C_PF1_HIGH_OFFSET => C_PF1_HIGH_OFFSET, + C_PF2_BAR_INDEX => C_PF2_BAR_INDEX, + C_PF2_LOW_OFFSET => C_PF2_LOW_OFFSET, + C_PF2_HIGH_OFFSET => C_PF2_HIGH_OFFSET, + C_PF3_BAR_INDEX => C_PF3_BAR_INDEX, + C_PF3_LOW_OFFSET => C_PF3_LOW_OFFSET, + C_PF3_HIGH_OFFSET => C_PF3_HIGH_OFFSET, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + aclk_pcie => aclk_pcie, + aresetn_pcie => aresetn_pcie, + s_pcie4_cfg_ext_function_number => s_pcie4_cfg_ext_function_number, + s_pcie4_cfg_ext_read_data => s_pcie4_cfg_ext_read_data, + s_pcie4_cfg_ext_read_data_valid => s_pcie4_cfg_ext_read_data_valid, + s_pcie4_cfg_ext_read_received => s_pcie4_cfg_ext_read_received, + s_pcie4_cfg_ext_register_number => s_pcie4_cfg_ext_register_number, + s_pcie4_cfg_ext_write_byte_enable => s_pcie4_cfg_ext_write_byte_enable, + s_pcie4_cfg_ext_write_data => s_pcie4_cfg_ext_write_data, + s_pcie4_cfg_ext_write_received => s_pcie4_cfg_ext_write_received, + m_pcie4_cfg_ext_function_number => m_pcie4_cfg_ext_function_number, + m_pcie4_cfg_ext_read_data => m_pcie4_cfg_ext_read_data, + m_pcie4_cfg_ext_read_data_valid => m_pcie4_cfg_ext_read_data_valid, + m_pcie4_cfg_ext_read_received => m_pcie4_cfg_ext_read_received, + m_pcie4_cfg_ext_register_number => m_pcie4_cfg_ext_register_number, + m_pcie4_cfg_ext_write_byte_enable => m_pcie4_cfg_ext_write_byte_enable, + m_pcie4_cfg_ext_write_data => m_pcie4_cfg_ext_write_data, + m_pcie4_cfg_ext_write_received => m_pcie4_cfg_ext_write_received + ); + + G_GENERATE: for i in 0 to C_NUM_PFS-1 generate + + G_GENERATE_PF0 : if (i = 0) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_0 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF0_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF0_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF0_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF0_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF0_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF0_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF0_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF0_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF0_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF0_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF0_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF0_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF0_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF0_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF0_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF0_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF0_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF0_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF0_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF0_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF0_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF0_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF0_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF0_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF0_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF0_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF0_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF0_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF0_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF0_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF0_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF0_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF0_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF0_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF0_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF0_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF0_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF0_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF0_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF0_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF0_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF0_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF0_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF0_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF0_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF0_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF0_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF0_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF0_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF0_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF0_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF0_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF0_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF0_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF0_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF0_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF0_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF0_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF0_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF0_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF0_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF0_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF0_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF0_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF0_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF0_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF0_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF0_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF0_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF0_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF0_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF0_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF0_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF0_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF0_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF0_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF0_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF0_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF0_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF0_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF0_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF0_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF0_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF0_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF0_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF0_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF0_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF0_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF0_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF0_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF0_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF0_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF0_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF0_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF0_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF0_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF0_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF0_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF0_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF0_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF0_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF0_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF0_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF0_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF0_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF0_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF0_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF0_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF0_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF0_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF0_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF0_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF0_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF0_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf0_awaddr, + s_axi_awvalid => s_axi_ctrl_pf0_awvalid, + s_axi_awready => s_axi_ctrl_pf0_awready, + s_axi_wdata => s_axi_ctrl_pf0_wdata, + s_axi_wstrb => s_axi_ctrl_pf0_wstrb, + s_axi_wvalid => s_axi_ctrl_pf0_wvalid, + s_axi_wready => s_axi_ctrl_pf0_wready, + s_axi_bresp => s_axi_ctrl_pf0_bresp, + s_axi_bvalid => s_axi_ctrl_pf0_bvalid, + s_axi_bready => s_axi_ctrl_pf0_bready, + s_axi_araddr => s_axi_ctrl_pf0_araddr, + s_axi_arvalid => s_axi_ctrl_pf0_arvalid, + s_axi_arready => s_axi_ctrl_pf0_arready, + s_axi_rdata => s_axi_ctrl_pf0_rdata, + s_axi_rresp => s_axi_ctrl_pf0_rresp, + s_axi_rvalid => s_axi_ctrl_pf0_rvalid, + s_axi_rready => s_axi_ctrl_pf0_rready + ); + + end generate G_GENERATE_PF0; + + G_GENERATE_PF1 : if (i = 1) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_1 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF1_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF1_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF1_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF1_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF1_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF1_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF1_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF1_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF1_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF1_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF1_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF1_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF1_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF1_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF1_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF1_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF1_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF1_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF1_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF1_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF1_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF1_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF1_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF1_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF1_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF1_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF1_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF1_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF1_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF1_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF1_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF1_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF1_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF1_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF1_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF1_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF1_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF1_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF1_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF1_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF1_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF1_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF1_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF1_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF1_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF1_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF1_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF1_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF1_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF1_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF1_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF1_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF1_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF1_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF1_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF1_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF1_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF1_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF1_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF1_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF1_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF1_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF1_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF1_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF1_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF1_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF1_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF1_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF1_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF1_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF1_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF1_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF1_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF1_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF1_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF1_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF1_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF1_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF1_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF1_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF1_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF1_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF1_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF1_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF1_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF1_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF1_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF1_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF1_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF1_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF1_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF1_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF1_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF1_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF1_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF1_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF1_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF1_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF1_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF1_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF1_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF1_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF1_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF1_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF1_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF1_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF1_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF1_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF1_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF1_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF1_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF1_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF1_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF1_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf1_awaddr, + s_axi_awvalid => s_axi_ctrl_pf1_awvalid, + s_axi_awready => s_axi_ctrl_pf1_awready, + s_axi_wdata => s_axi_ctrl_pf1_wdata, + s_axi_wstrb => s_axi_ctrl_pf1_wstrb, + s_axi_wvalid => s_axi_ctrl_pf1_wvalid, + s_axi_wready => s_axi_ctrl_pf1_wready, + s_axi_bresp => s_axi_ctrl_pf1_bresp, + s_axi_bvalid => s_axi_ctrl_pf1_bvalid, + s_axi_bready => s_axi_ctrl_pf1_bready, + s_axi_araddr => s_axi_ctrl_pf1_araddr, + s_axi_arvalid => s_axi_ctrl_pf1_arvalid, + s_axi_arready => s_axi_ctrl_pf1_arready, + s_axi_rdata => s_axi_ctrl_pf1_rdata, + s_axi_rresp => s_axi_ctrl_pf1_rresp, + s_axi_rvalid => s_axi_ctrl_pf1_rvalid, + s_axi_rready => s_axi_ctrl_pf1_rready + ); + + end generate G_GENERATE_PF1; + + G_GENERATE_PF2: if (i = 2) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_2 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF2_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF2_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF2_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF2_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF2_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF2_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF2_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF2_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF2_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF2_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF2_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF2_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF2_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF2_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF2_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF2_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF2_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF2_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF2_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF2_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF2_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF2_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF2_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF2_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF2_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF2_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF2_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF2_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF2_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF2_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF2_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF2_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF2_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF2_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF2_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF2_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF2_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF2_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF2_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF2_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF2_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF2_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF2_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF2_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF2_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF2_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF2_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF2_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF2_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF2_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF2_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF2_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF2_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF2_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF2_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF2_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF2_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF2_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF2_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF2_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF2_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF2_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF2_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF2_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF2_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF2_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF2_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF2_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF2_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF2_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF2_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF2_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF2_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF2_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF2_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF2_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF2_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF2_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF2_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF2_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF2_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF2_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF2_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF2_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF2_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF2_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF2_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF2_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF2_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF2_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF2_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF2_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF2_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF2_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF2_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF2_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF2_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF2_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF2_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF2_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF2_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF2_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF2_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF2_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF2_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF2_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF2_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF2_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF2_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF2_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF2_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF2_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF2_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF2_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf2_awaddr, + s_axi_awvalid => s_axi_ctrl_pf2_awvalid, + s_axi_awready => s_axi_ctrl_pf2_awready, + s_axi_wdata => s_axi_ctrl_pf2_wdata, + s_axi_wstrb => s_axi_ctrl_pf2_wstrb, + s_axi_wvalid => s_axi_ctrl_pf2_wvalid, + s_axi_wready => s_axi_ctrl_pf2_wready, + s_axi_bresp => s_axi_ctrl_pf2_bresp, + s_axi_bvalid => s_axi_ctrl_pf2_bvalid, + s_axi_bready => s_axi_ctrl_pf2_bready, + s_axi_araddr => s_axi_ctrl_pf2_araddr, + s_axi_arvalid => s_axi_ctrl_pf2_arvalid, + s_axi_arready => s_axi_ctrl_pf2_arready, + s_axi_rdata => s_axi_ctrl_pf2_rdata, + s_axi_rresp => s_axi_ctrl_pf2_rresp, + s_axi_rvalid => s_axi_ctrl_pf2_rvalid, + s_axi_rready => s_axi_ctrl_pf2_rready + ); + + end generate G_GENERATE_PF2; + + G_GENERATE_PF3 : if (i = 3) generate + + -- Instantiate BAR Layout table + BAR_LAYOUT_TABLE_inst_3 : entity hw_discovery_v1_0_0.hw_discovery_v1_0_0_bar_layout_table + generic map ( + C_NUM_SLOTS_BAR_LAYOUT_TABLE => C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE, + C_ENTRY_TYPE_0 => C_PF3_ENTRY_TYPE_0, + C_ENTRY_BAR_0 => C_PF3_ENTRY_BAR_0, + C_ENTRY_ADDR_0 => C_PF3_ENTRY_ADDR_0, + C_ENTRY_MAJOR_VERSION_0 => C_PF3_ENTRY_MAJOR_VERSION_0, + C_ENTRY_MINOR_VERSION_0 => C_PF3_ENTRY_MINOR_VERSION_0, + C_ENTRY_VERSION_TYPE_0 => C_PF3_ENTRY_VERSION_TYPE_0, + C_ENTRY_RSVD0_0 => C_PF3_ENTRY_RSVD0_0, + C_ENTRY_TYPE_1 => C_PF3_ENTRY_TYPE_1, + C_ENTRY_BAR_1 => C_PF3_ENTRY_BAR_1, + C_ENTRY_ADDR_1 => C_PF3_ENTRY_ADDR_1, + C_ENTRY_MAJOR_VERSION_1 => C_PF3_ENTRY_MAJOR_VERSION_1, + C_ENTRY_MINOR_VERSION_1 => C_PF3_ENTRY_MINOR_VERSION_1, + C_ENTRY_VERSION_TYPE_1 => C_PF3_ENTRY_VERSION_TYPE_1, + C_ENTRY_RSVD0_1 => C_PF3_ENTRY_RSVD0_1, + C_ENTRY_TYPE_2 => C_PF3_ENTRY_TYPE_2, + C_ENTRY_BAR_2 => C_PF3_ENTRY_BAR_2, + C_ENTRY_ADDR_2 => C_PF3_ENTRY_ADDR_2, + C_ENTRY_MAJOR_VERSION_2 => C_PF3_ENTRY_MAJOR_VERSION_2, + C_ENTRY_MINOR_VERSION_2 => C_PF3_ENTRY_MINOR_VERSION_2, + C_ENTRY_VERSION_TYPE_2 => C_PF3_ENTRY_VERSION_TYPE_2, + C_ENTRY_RSVD0_2 => C_PF3_ENTRY_RSVD0_2, + C_ENTRY_TYPE_3 => C_PF3_ENTRY_TYPE_3, + C_ENTRY_BAR_3 => C_PF3_ENTRY_BAR_3, + C_ENTRY_ADDR_3 => C_PF3_ENTRY_ADDR_3, + C_ENTRY_MAJOR_VERSION_3 => C_PF3_ENTRY_MAJOR_VERSION_3, + C_ENTRY_MINOR_VERSION_3 => C_PF3_ENTRY_MINOR_VERSION_3, + C_ENTRY_VERSION_TYPE_3 => C_PF3_ENTRY_VERSION_TYPE_3, + C_ENTRY_RSVD0_3 => C_PF3_ENTRY_RSVD0_3, + C_ENTRY_TYPE_4 => C_PF3_ENTRY_TYPE_4, + C_ENTRY_BAR_4 => C_PF3_ENTRY_BAR_4, + C_ENTRY_ADDR_4 => C_PF3_ENTRY_ADDR_4, + C_ENTRY_MAJOR_VERSION_4 => C_PF3_ENTRY_MAJOR_VERSION_4, + C_ENTRY_MINOR_VERSION_4 => C_PF3_ENTRY_MINOR_VERSION_4, + C_ENTRY_VERSION_TYPE_4 => C_PF3_ENTRY_VERSION_TYPE_4, + C_ENTRY_RSVD0_4 => C_PF3_ENTRY_RSVD0_4, + C_ENTRY_TYPE_5 => C_PF3_ENTRY_TYPE_5, + C_ENTRY_BAR_5 => C_PF3_ENTRY_BAR_5, + C_ENTRY_ADDR_5 => C_PF3_ENTRY_ADDR_5, + C_ENTRY_MAJOR_VERSION_5 => C_PF3_ENTRY_MAJOR_VERSION_5, + C_ENTRY_MINOR_VERSION_5 => C_PF3_ENTRY_MINOR_VERSION_5, + C_ENTRY_VERSION_TYPE_5 => C_PF3_ENTRY_VERSION_TYPE_5, + C_ENTRY_RSVD0_5 => C_PF3_ENTRY_RSVD0_5, + C_ENTRY_TYPE_6 => C_PF3_ENTRY_TYPE_6, + C_ENTRY_BAR_6 => C_PF3_ENTRY_BAR_6, + C_ENTRY_ADDR_6 => C_PF3_ENTRY_ADDR_6, + C_ENTRY_MAJOR_VERSION_6 => C_PF3_ENTRY_MAJOR_VERSION_6, + C_ENTRY_MINOR_VERSION_6 => C_PF3_ENTRY_MINOR_VERSION_6, + C_ENTRY_VERSION_TYPE_6 => C_PF3_ENTRY_VERSION_TYPE_6, + C_ENTRY_RSVD0_6 => C_PF3_ENTRY_RSVD0_6, + C_ENTRY_TYPE_7 => C_PF3_ENTRY_TYPE_7, + C_ENTRY_BAR_7 => C_PF3_ENTRY_BAR_7, + C_ENTRY_ADDR_7 => C_PF3_ENTRY_ADDR_7, + C_ENTRY_MAJOR_VERSION_7 => C_PF3_ENTRY_MAJOR_VERSION_7, + C_ENTRY_MINOR_VERSION_7 => C_PF3_ENTRY_MINOR_VERSION_7, + C_ENTRY_VERSION_TYPE_7 => C_PF3_ENTRY_VERSION_TYPE_7, + C_ENTRY_RSVD0_7 => C_PF3_ENTRY_RSVD0_7, + C_ENTRY_TYPE_8 => C_PF3_ENTRY_TYPE_8, + C_ENTRY_BAR_8 => C_PF3_ENTRY_BAR_8, + C_ENTRY_ADDR_8 => C_PF3_ENTRY_ADDR_8, + C_ENTRY_MAJOR_VERSION_8 => C_PF3_ENTRY_MAJOR_VERSION_8, + C_ENTRY_MINOR_VERSION_8 => C_PF3_ENTRY_MINOR_VERSION_8, + C_ENTRY_VERSION_TYPE_8 => C_PF3_ENTRY_VERSION_TYPE_8, + C_ENTRY_RSVD0_8 => C_PF3_ENTRY_RSVD0_8, + C_ENTRY_TYPE_9 => C_PF3_ENTRY_TYPE_9, + C_ENTRY_BAR_9 => C_PF3_ENTRY_BAR_9, + C_ENTRY_ADDR_9 => C_PF3_ENTRY_ADDR_9, + C_ENTRY_MAJOR_VERSION_9 => C_PF3_ENTRY_MAJOR_VERSION_9, + C_ENTRY_MINOR_VERSION_9 => C_PF3_ENTRY_MINOR_VERSION_9, + C_ENTRY_VERSION_TYPE_9 => C_PF3_ENTRY_VERSION_TYPE_9, + C_ENTRY_RSVD0_9 => C_PF3_ENTRY_RSVD0_9, + C_ENTRY_TYPE_10 => C_PF3_ENTRY_TYPE_10, + C_ENTRY_BAR_10 => C_PF3_ENTRY_BAR_10, + C_ENTRY_ADDR_10 => C_PF3_ENTRY_ADDR_10, + C_ENTRY_MAJOR_VERSION_10 => C_PF3_ENTRY_MAJOR_VERSION_10, + C_ENTRY_MINOR_VERSION_10 => C_PF3_ENTRY_MINOR_VERSION_10, + C_ENTRY_VERSION_TYPE_10 => C_PF3_ENTRY_VERSION_TYPE_10, + C_ENTRY_RSVD0_10 => C_PF3_ENTRY_RSVD0_10, + C_ENTRY_TYPE_11 => C_PF3_ENTRY_TYPE_11, + C_ENTRY_BAR_11 => C_PF3_ENTRY_BAR_11, + C_ENTRY_ADDR_11 => C_PF3_ENTRY_ADDR_11, + C_ENTRY_MAJOR_VERSION_11 => C_PF3_ENTRY_MAJOR_VERSION_11, + C_ENTRY_MINOR_VERSION_11 => C_PF3_ENTRY_MINOR_VERSION_11, + C_ENTRY_VERSION_TYPE_11 => C_PF3_ENTRY_VERSION_TYPE_11, + C_ENTRY_RSVD0_11 => C_PF3_ENTRY_RSVD0_11, + C_ENTRY_TYPE_12 => C_PF3_ENTRY_TYPE_12, + C_ENTRY_BAR_12 => C_PF3_ENTRY_BAR_12, + C_ENTRY_ADDR_12 => C_PF3_ENTRY_ADDR_12, + C_ENTRY_MAJOR_VERSION_12 => C_PF3_ENTRY_MAJOR_VERSION_12, + C_ENTRY_MINOR_VERSION_12 => C_PF3_ENTRY_MINOR_VERSION_12, + C_ENTRY_VERSION_TYPE_12 => C_PF3_ENTRY_VERSION_TYPE_12, + C_ENTRY_RSVD0_12 => C_PF3_ENTRY_RSVD0_12, + C_ENTRY_TYPE_13 => C_PF3_ENTRY_TYPE_13, + C_ENTRY_BAR_13 => C_PF3_ENTRY_BAR_13, + C_ENTRY_ADDR_13 => C_PF3_ENTRY_ADDR_13, + C_ENTRY_MAJOR_VERSION_13 => C_PF3_ENTRY_MAJOR_VERSION_13, + C_ENTRY_MINOR_VERSION_13 => C_PF3_ENTRY_MINOR_VERSION_13, + C_ENTRY_VERSION_TYPE_13 => C_PF3_ENTRY_VERSION_TYPE_13, + C_ENTRY_RSVD0_13 => C_PF3_ENTRY_RSVD0_13, + C_ENTRY_TYPE_14 => C_PF3_ENTRY_TYPE_14, + C_ENTRY_BAR_14 => C_PF3_ENTRY_BAR_14, + C_ENTRY_ADDR_14 => C_PF3_ENTRY_ADDR_14, + C_ENTRY_MAJOR_VERSION_14 => C_PF3_ENTRY_MAJOR_VERSION_14, + C_ENTRY_MINOR_VERSION_14 => C_PF3_ENTRY_MINOR_VERSION_14, + C_ENTRY_VERSION_TYPE_14 => C_PF3_ENTRY_VERSION_TYPE_14, + C_ENTRY_RSVD0_14 => C_PF3_ENTRY_RSVD0_14, + C_ENTRY_TYPE_15 => C_PF3_ENTRY_TYPE_15, + C_ENTRY_BAR_15 => C_PF3_ENTRY_BAR_15, + C_ENTRY_ADDR_15 => C_PF3_ENTRY_ADDR_15, + C_ENTRY_MAJOR_VERSION_15 => C_PF3_ENTRY_MAJOR_VERSION_15, + C_ENTRY_MINOR_VERSION_15 => C_PF3_ENTRY_MINOR_VERSION_15, + C_ENTRY_VERSION_TYPE_15 => C_PF3_ENTRY_VERSION_TYPE_15, + C_ENTRY_RSVD0_15 => C_PF3_ENTRY_RSVD0_15, + C_S_AXI_DATA_WIDTH => C_PF3_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_PF3_S_AXI_ADDR_WIDTH, + C_XDEVICEFAMILY => C_XDEVICEFAMILY + ) + port map ( + s_axi_aclk => aclk_ctrl, + s_axi_aresetn => aresetn_ctrl, + s_axi_awaddr => s_axi_ctrl_pf3_awaddr, + s_axi_awvalid => s_axi_ctrl_pf3_awvalid, + s_axi_awready => s_axi_ctrl_pf3_awready, + s_axi_wdata => s_axi_ctrl_pf3_wdata, + s_axi_wstrb => s_axi_ctrl_pf3_wstrb, + s_axi_wvalid => s_axi_ctrl_pf3_wvalid, + s_axi_wready => s_axi_ctrl_pf3_wready, + s_axi_bresp => s_axi_ctrl_pf3_bresp, + s_axi_bvalid => s_axi_ctrl_pf3_bvalid, + s_axi_bready => s_axi_ctrl_pf3_bready, + s_axi_araddr => s_axi_ctrl_pf3_araddr, + s_axi_arvalid => s_axi_ctrl_pf3_arvalid, + s_axi_arready => s_axi_ctrl_pf3_arready, + s_axi_rdata => s_axi_ctrl_pf3_rdata, + s_axi_rresp => s_axi_ctrl_pf3_rresp, + s_axi_rvalid => s_axi_ctrl_pf3_rvalid, + s_axi_rready => s_axi_ctrl_pf3_rready + ); + + end generate G_GENERATE_PF3; + + end generate G_GENERATE; + +end architecture rtl; diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_discovery.v b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_discovery.v new file mode 100644 index 00000000..88d32f60 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/hw_discovery.v @@ -0,0 +1,1054 @@ +// (c) Copyright 2022, Advanced Micro Devices, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module hw_discovery_v1_0_0_hw_discovery #( + parameter integer C_NUM_PFS = 1, + parameter [11:0] C_CAP_BASE_ADDR = 12'h0, + parameter [11:0] C_NEXT_CAP_ADDR = 12'h0, + parameter integer C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF0_BAR_INDEX = 0, + parameter [27:0] C_PF0_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF0_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF0_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF0_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF0_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF0_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF0_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF0_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF0_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF0_S_AXI_ADDR_WIDTH = 32, + parameter integer C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF1_BAR_INDEX = 0, + parameter [27:0] C_PF1_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF1_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF1_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF1_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF1_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF1_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF1_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF1_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF1_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF1_S_AXI_ADDR_WIDTH = 32, + parameter integer C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF2_BAR_INDEX = 0, + parameter [27:0] C_PF2_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF2_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF2_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF2_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF2_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF2_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF2_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF2_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF2_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF2_S_AXI_ADDR_WIDTH = 32, + parameter integer C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE = 1, + parameter integer C_PF3_BAR_INDEX = 0, + parameter [27:0] C_PF3_LOW_OFFSET = 28'h0, + parameter [31:0] C_PF3_HIGH_OFFSET = 32'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_0 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_0 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_0 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_0 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_0 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_0 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_0 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_1 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_1 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_1 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_1 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_1 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_1 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_1 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_2 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_2 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_2 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_2 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_2 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_2 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_2 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_3 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_3 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_3 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_3 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_3 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_3 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_3 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_4 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_4 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_4 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_4 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_4 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_4 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_4 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_5 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_5 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_5 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_5 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_5 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_5 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_5 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_6 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_6 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_6 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_6 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_6 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_6 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_6 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_7 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_7 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_7 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_7 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_7 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_7 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_7 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_8 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_8 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_8 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_8 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_8 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_8 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_8 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_9 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_9 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_9 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_9 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_9 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_9 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_9 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_10 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_10 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_10 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_10 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_10 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_10 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_10 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_11 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_11 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_11 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_11 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_11 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_11 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_11 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_12 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_12 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_12 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_12 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_12 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_12 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_12 = 4'h0, + parameter [7:0] C_PF3_ENTRY_TYPE_13 = 8'h0, + parameter integer C_PF3_ENTRY_BAR_13 = 0, + parameter [47:0] C_PF3_ENTRY_ADDR_13 = 48'h0, + parameter integer C_PF3_ENTRY_MAJOR_VERSION_13 = 0, + parameter integer C_PF3_ENTRY_MINOR_VERSION_13 = 0, + parameter [7:0] C_PF3_ENTRY_VERSION_TYPE_13 = 8'h0, + parameter [3:0] C_PF3_ENTRY_RSVD0_13 = 4'h0, + parameter integer C_PF3_S_AXI_ADDR_WIDTH = 32, + parameter C_XDEVICEFAMILY = "no_family" + ) + ( + // Clocks & Resets + input wire aclk_pcie, + input wire aresetn_pcie, + input wire aclk_ctrl, + input wire aresetn_ctrl, + + // slave pcie4_cfg_ext Interface (aclk_pcie) + input wire [15:0] s_pcie4_cfg_ext_function_number, + output wire [31:0] s_pcie4_cfg_ext_read_data, + output wire s_pcie4_cfg_ext_read_data_valid, + input wire s_pcie4_cfg_ext_read_received, + input wire [9:0] s_pcie4_cfg_ext_register_number, + input wire [3:0] s_pcie4_cfg_ext_write_byte_enable, + input wire [31:0] s_pcie4_cfg_ext_write_data, + input wire s_pcie4_cfg_ext_write_received, + + // slave pcie4_cfg_ext Interface (aclk_pcie) + output wire [15:0] m_pcie4_cfg_ext_function_number, + input wire [31:0] m_pcie4_cfg_ext_read_data, + input wire m_pcie4_cfg_ext_read_data_valid, + output wire m_pcie4_cfg_ext_read_received, + output wire [9:0] m_pcie4_cfg_ext_register_number, + output wire [3:0] m_pcie4_cfg_ext_write_byte_enable, + output wire [31:0] m_pcie4_cfg_ext_write_data, + output wire m_pcie4_cfg_ext_write_received, + + // AXI Interface (aclk_ctrl) for PF0 + input wire [C_PF0_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf0_awaddr, + input wire s_axi_ctrl_pf0_awvalid, + output wire s_axi_ctrl_pf0_awready, + input wire [32-1:0] s_axi_ctrl_pf0_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf0_wstrb, + input wire s_axi_ctrl_pf0_wvalid, + output wire s_axi_ctrl_pf0_wready, + output wire [1:0] s_axi_ctrl_pf0_bresp, + output wire s_axi_ctrl_pf0_bvalid, + input wire s_axi_ctrl_pf0_bready, + input wire [C_PF0_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf0_araddr, + input wire s_axi_ctrl_pf0_arvalid, + output wire s_axi_ctrl_pf0_arready, + output wire [32-1:0] s_axi_ctrl_pf0_rdata, + output wire [1:0] s_axi_ctrl_pf0_rresp, + output wire s_axi_ctrl_pf0_rvalid, + input wire s_axi_ctrl_pf0_rready, + + // AXI Interface (aclk_ctrl) for PF1 + input wire [C_PF1_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf1_awaddr, + input wire s_axi_ctrl_pf1_awvalid, + output wire s_axi_ctrl_pf1_awready, + input wire [32-1:0] s_axi_ctrl_pf1_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf1_wstrb, + input wire s_axi_ctrl_pf1_wvalid, + output wire s_axi_ctrl_pf1_wready, + output wire [1:0] s_axi_ctrl_pf1_bresp, + output wire s_axi_ctrl_pf1_bvalid, + input wire s_axi_ctrl_pf1_bready, + input wire [C_PF1_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf1_araddr, + input wire s_axi_ctrl_pf1_arvalid, + output wire s_axi_ctrl_pf1_arready, + output wire [32-1:0] s_axi_ctrl_pf1_rdata, + output wire [1:0] s_axi_ctrl_pf1_rresp, + output wire s_axi_ctrl_pf1_rvalid, + input wire s_axi_ctrl_pf1_rready, + + // AXI Interface (aclk_ctrl) for PF2 + input wire [C_PF2_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf2_awaddr, + input wire s_axi_ctrl_pf2_awvalid, + output wire s_axi_ctrl_pf2_awready, + input wire [32-1:0] s_axi_ctrl_pf2_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf2_wstrb, + input wire s_axi_ctrl_pf2_wvalid, + output wire s_axi_ctrl_pf2_wready, + output wire [1:0] s_axi_ctrl_pf2_bresp, + output wire s_axi_ctrl_pf2_bvalid, + input wire s_axi_ctrl_pf2_bready, + input wire [C_PF2_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf2_araddr, + input wire s_axi_ctrl_pf2_arvalid, + output wire s_axi_ctrl_pf2_arready, + output wire [32-1:0] s_axi_ctrl_pf2_rdata, + output wire [1:0] s_axi_ctrl_pf2_rresp, + output wire s_axi_ctrl_pf2_rvalid, + input wire s_axi_ctrl_pf2_rready, + + // AXI Interface (aclk_ctrl) for PF3 + input wire [C_PF3_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf3_awaddr, + input wire s_axi_ctrl_pf3_awvalid, + output wire s_axi_ctrl_pf3_awready, + input wire [32-1:0] s_axi_ctrl_pf3_wdata, + input wire [32/8-1:0] s_axi_ctrl_pf3_wstrb, + input wire s_axi_ctrl_pf3_wvalid, + output wire s_axi_ctrl_pf3_wready, + output wire [1:0] s_axi_ctrl_pf3_bresp, + output wire s_axi_ctrl_pf3_bvalid, + input wire s_axi_ctrl_pf3_bready, + input wire [C_PF3_S_AXI_ADDR_WIDTH-1:0] s_axi_ctrl_pf3_araddr, + input wire s_axi_ctrl_pf3_arvalid, + output wire s_axi_ctrl_pf3_arready, + output wire [32-1:0] s_axi_ctrl_pf3_rdata, + output wire [1:0] s_axi_ctrl_pf3_rresp, + output wire s_axi_ctrl_pf3_rvalid, + input wire s_axi_ctrl_pf3_rready + ); + + hw_discovery_v1_0_0_hw_disc #( + .C_NUM_PFS (C_NUM_PFS ), + .C_CAP_BASE_ADDR (C_CAP_BASE_ADDR ), + .C_NEXT_CAP_ADDR (C_NEXT_CAP_ADDR ), + .C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF0_BAR_INDEX (C_PF0_BAR_INDEX ), + .C_PF0_LOW_OFFSET (C_PF0_LOW_OFFSET ), + .C_PF0_HIGH_OFFSET (C_PF0_HIGH_OFFSET ), + .C_PF0_ENTRY_TYPE_0 (C_PF0_ENTRY_TYPE_0 ), + .C_PF0_ENTRY_BAR_0 (C_PF0_ENTRY_BAR_0 ), + .C_PF0_ENTRY_ADDR_0 (C_PF0_ENTRY_ADDR_0 ), + .C_PF0_ENTRY_MAJOR_VERSION_0 (C_PF0_ENTRY_MAJOR_VERSION_0 ), + .C_PF0_ENTRY_MINOR_VERSION_0 (C_PF0_ENTRY_MINOR_VERSION_0 ), + .C_PF0_ENTRY_VERSION_TYPE_0 (C_PF0_ENTRY_VERSION_TYPE_0 ), + .C_PF0_ENTRY_RSVD0_0 (C_PF0_ENTRY_RSVD0_0 ), + .C_PF0_ENTRY_TYPE_1 (C_PF0_ENTRY_TYPE_1 ), + .C_PF0_ENTRY_BAR_1 (C_PF0_ENTRY_BAR_1 ), + .C_PF0_ENTRY_ADDR_1 (C_PF0_ENTRY_ADDR_1 ), + .C_PF0_ENTRY_MAJOR_VERSION_1 (C_PF0_ENTRY_MAJOR_VERSION_1 ), + .C_PF0_ENTRY_MINOR_VERSION_1 (C_PF0_ENTRY_MINOR_VERSION_1 ), + .C_PF0_ENTRY_VERSION_TYPE_1 (C_PF0_ENTRY_VERSION_TYPE_1 ), + .C_PF0_ENTRY_RSVD0_1 (C_PF0_ENTRY_RSVD0_1 ), + .C_PF0_ENTRY_TYPE_2 (C_PF0_ENTRY_TYPE_2 ), + .C_PF0_ENTRY_BAR_2 (C_PF0_ENTRY_BAR_2 ), + .C_PF0_ENTRY_ADDR_2 (C_PF0_ENTRY_ADDR_2 ), + .C_PF0_ENTRY_MAJOR_VERSION_2 (C_PF0_ENTRY_MAJOR_VERSION_2 ), + .C_PF0_ENTRY_MINOR_VERSION_2 (C_PF0_ENTRY_MINOR_VERSION_2 ), + .C_PF0_ENTRY_VERSION_TYPE_2 (C_PF0_ENTRY_VERSION_TYPE_2 ), + .C_PF0_ENTRY_RSVD0_2 (C_PF0_ENTRY_RSVD0_2 ), + .C_PF0_ENTRY_TYPE_3 (C_PF0_ENTRY_TYPE_3 ), + .C_PF0_ENTRY_BAR_3 (C_PF0_ENTRY_BAR_3 ), + .C_PF0_ENTRY_ADDR_3 (C_PF0_ENTRY_ADDR_3 ), + .C_PF0_ENTRY_MAJOR_VERSION_3 (C_PF0_ENTRY_MAJOR_VERSION_3 ), + .C_PF0_ENTRY_MINOR_VERSION_3 (C_PF0_ENTRY_MINOR_VERSION_3 ), + .C_PF0_ENTRY_VERSION_TYPE_3 (C_PF0_ENTRY_VERSION_TYPE_3 ), + .C_PF0_ENTRY_RSVD0_3 (C_PF0_ENTRY_RSVD0_3 ), + .C_PF0_ENTRY_TYPE_4 (C_PF0_ENTRY_TYPE_4 ), + .C_PF0_ENTRY_BAR_4 (C_PF0_ENTRY_BAR_4 ), + .C_PF0_ENTRY_ADDR_4 (C_PF0_ENTRY_ADDR_4 ), + .C_PF0_ENTRY_MAJOR_VERSION_4 (C_PF0_ENTRY_MAJOR_VERSION_4 ), + .C_PF0_ENTRY_MINOR_VERSION_4 (C_PF0_ENTRY_MINOR_VERSION_4 ), + .C_PF0_ENTRY_VERSION_TYPE_4 (C_PF0_ENTRY_VERSION_TYPE_4 ), + .C_PF0_ENTRY_RSVD0_4 (C_PF0_ENTRY_RSVD0_4 ), + .C_PF0_ENTRY_TYPE_5 (C_PF0_ENTRY_TYPE_5 ), + .C_PF0_ENTRY_BAR_5 (C_PF0_ENTRY_BAR_5 ), + .C_PF0_ENTRY_ADDR_5 (C_PF0_ENTRY_ADDR_5 ), + .C_PF0_ENTRY_MAJOR_VERSION_5 (C_PF0_ENTRY_MAJOR_VERSION_5 ), + .C_PF0_ENTRY_MINOR_VERSION_5 (C_PF0_ENTRY_MINOR_VERSION_5 ), + .C_PF0_ENTRY_VERSION_TYPE_5 (C_PF0_ENTRY_VERSION_TYPE_5 ), + .C_PF0_ENTRY_RSVD0_5 (C_PF0_ENTRY_RSVD0_5 ), + .C_PF0_ENTRY_TYPE_6 (C_PF0_ENTRY_TYPE_6 ), + .C_PF0_ENTRY_BAR_6 (C_PF0_ENTRY_BAR_6 ), + .C_PF0_ENTRY_ADDR_6 (C_PF0_ENTRY_ADDR_6 ), + .C_PF0_ENTRY_MAJOR_VERSION_6 (C_PF0_ENTRY_MAJOR_VERSION_6 ), + .C_PF0_ENTRY_MINOR_VERSION_6 (C_PF0_ENTRY_MINOR_VERSION_6 ), + .C_PF0_ENTRY_VERSION_TYPE_6 (C_PF0_ENTRY_VERSION_TYPE_6 ), + .C_PF0_ENTRY_RSVD0_6 (C_PF0_ENTRY_RSVD0_6 ), + .C_PF0_ENTRY_TYPE_7 (C_PF0_ENTRY_TYPE_7 ), + .C_PF0_ENTRY_BAR_7 (C_PF0_ENTRY_BAR_7 ), + .C_PF0_ENTRY_ADDR_7 (C_PF0_ENTRY_ADDR_7 ), + .C_PF0_ENTRY_MAJOR_VERSION_7 (C_PF0_ENTRY_MAJOR_VERSION_7 ), + .C_PF0_ENTRY_MINOR_VERSION_7 (C_PF0_ENTRY_MINOR_VERSION_7 ), + .C_PF0_ENTRY_VERSION_TYPE_7 (C_PF0_ENTRY_VERSION_TYPE_7 ), + .C_PF0_ENTRY_RSVD0_7 (C_PF0_ENTRY_RSVD0_7 ), + .C_PF0_ENTRY_TYPE_8 (C_PF0_ENTRY_TYPE_8 ), + .C_PF0_ENTRY_BAR_8 (C_PF0_ENTRY_BAR_8 ), + .C_PF0_ENTRY_ADDR_8 (C_PF0_ENTRY_ADDR_8 ), + .C_PF0_ENTRY_MAJOR_VERSION_8 (C_PF0_ENTRY_MAJOR_VERSION_8 ), + .C_PF0_ENTRY_MINOR_VERSION_8 (C_PF0_ENTRY_MINOR_VERSION_8 ), + .C_PF0_ENTRY_VERSION_TYPE_8 (C_PF0_ENTRY_VERSION_TYPE_8 ), + .C_PF0_ENTRY_RSVD0_8 (C_PF0_ENTRY_RSVD0_8 ), + .C_PF0_ENTRY_TYPE_9 (C_PF0_ENTRY_TYPE_9 ), + .C_PF0_ENTRY_BAR_9 (C_PF0_ENTRY_BAR_9 ), + .C_PF0_ENTRY_ADDR_9 (C_PF0_ENTRY_ADDR_9 ), + .C_PF0_ENTRY_MAJOR_VERSION_9 (C_PF0_ENTRY_MAJOR_VERSION_9 ), + .C_PF0_ENTRY_MINOR_VERSION_9 (C_PF0_ENTRY_MINOR_VERSION_9 ), + .C_PF0_ENTRY_VERSION_TYPE_9 (C_PF0_ENTRY_VERSION_TYPE_9 ), + .C_PF0_ENTRY_RSVD0_9 (C_PF0_ENTRY_RSVD0_9 ), + .C_PF0_ENTRY_TYPE_10 (C_PF0_ENTRY_TYPE_10 ), + .C_PF0_ENTRY_BAR_10 (C_PF0_ENTRY_BAR_10 ), + .C_PF0_ENTRY_ADDR_10 (C_PF0_ENTRY_ADDR_10 ), + .C_PF0_ENTRY_MAJOR_VERSION_10 (C_PF0_ENTRY_MAJOR_VERSION_10 ), + .C_PF0_ENTRY_MINOR_VERSION_10 (C_PF0_ENTRY_MINOR_VERSION_10 ), + .C_PF0_ENTRY_VERSION_TYPE_10 (C_PF0_ENTRY_VERSION_TYPE_10 ), + .C_PF0_ENTRY_RSVD0_10 (C_PF0_ENTRY_RSVD0_10 ), + .C_PF0_ENTRY_TYPE_11 (C_PF0_ENTRY_TYPE_11 ), + .C_PF0_ENTRY_BAR_11 (C_PF0_ENTRY_BAR_11 ), + .C_PF0_ENTRY_ADDR_11 (C_PF0_ENTRY_ADDR_11 ), + .C_PF0_ENTRY_MAJOR_VERSION_11 (C_PF0_ENTRY_MAJOR_VERSION_11 ), + .C_PF0_ENTRY_MINOR_VERSION_11 (C_PF0_ENTRY_MINOR_VERSION_11 ), + .C_PF0_ENTRY_VERSION_TYPE_11 (C_PF0_ENTRY_VERSION_TYPE_11 ), + .C_PF0_ENTRY_RSVD0_11 (C_PF0_ENTRY_RSVD0_11 ), + .C_PF0_ENTRY_TYPE_12 (C_PF0_ENTRY_TYPE_12 ), + .C_PF0_ENTRY_BAR_12 (C_PF0_ENTRY_BAR_12 ), + .C_PF0_ENTRY_ADDR_12 (C_PF0_ENTRY_ADDR_12 ), + .C_PF0_ENTRY_MAJOR_VERSION_12 (C_PF0_ENTRY_MAJOR_VERSION_12 ), + .C_PF0_ENTRY_MINOR_VERSION_12 (C_PF0_ENTRY_MINOR_VERSION_12 ), + .C_PF0_ENTRY_VERSION_TYPE_12 (C_PF0_ENTRY_VERSION_TYPE_12 ), + .C_PF0_ENTRY_RSVD0_12 (C_PF0_ENTRY_RSVD0_12 ), + .C_PF0_ENTRY_TYPE_13 (C_PF0_ENTRY_TYPE_13 ), + .C_PF0_ENTRY_BAR_13 (C_PF0_ENTRY_BAR_13 ), + .C_PF0_ENTRY_ADDR_13 (C_PF0_ENTRY_ADDR_13 ), + .C_PF0_ENTRY_MAJOR_VERSION_13 (C_PF0_ENTRY_MAJOR_VERSION_13 ), + .C_PF0_ENTRY_MINOR_VERSION_13 (C_PF0_ENTRY_MINOR_VERSION_13 ), + .C_PF0_ENTRY_VERSION_TYPE_13 (C_PF0_ENTRY_VERSION_TYPE_13 ), + .C_PF0_ENTRY_RSVD0_13 (C_PF0_ENTRY_RSVD0_13 ), + .C_PF0_S_AXI_ADDR_WIDTH (C_PF0_S_AXI_ADDR_WIDTH ), + .C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF1_BAR_INDEX (C_PF1_BAR_INDEX ), + .C_PF1_LOW_OFFSET (C_PF1_LOW_OFFSET ), + .C_PF1_HIGH_OFFSET (C_PF1_HIGH_OFFSET ), + .C_PF1_ENTRY_TYPE_0 (C_PF1_ENTRY_TYPE_0 ), + .C_PF1_ENTRY_BAR_0 (C_PF1_ENTRY_BAR_0 ), + .C_PF1_ENTRY_ADDR_0 (C_PF1_ENTRY_ADDR_0 ), + .C_PF1_ENTRY_MAJOR_VERSION_0 (C_PF1_ENTRY_MAJOR_VERSION_0 ), + .C_PF1_ENTRY_MINOR_VERSION_0 (C_PF1_ENTRY_MINOR_VERSION_0 ), + .C_PF1_ENTRY_VERSION_TYPE_0 (C_PF1_ENTRY_VERSION_TYPE_0 ), + .C_PF1_ENTRY_RSVD0_0 (C_PF1_ENTRY_RSVD0_0 ), + .C_PF1_ENTRY_TYPE_1 (C_PF1_ENTRY_TYPE_1 ), + .C_PF1_ENTRY_BAR_1 (C_PF1_ENTRY_BAR_1 ), + .C_PF1_ENTRY_ADDR_1 (C_PF1_ENTRY_ADDR_1 ), + .C_PF1_ENTRY_MAJOR_VERSION_1 (C_PF1_ENTRY_MAJOR_VERSION_1 ), + .C_PF1_ENTRY_MINOR_VERSION_1 (C_PF1_ENTRY_MINOR_VERSION_1 ), + .C_PF1_ENTRY_VERSION_TYPE_1 (C_PF1_ENTRY_VERSION_TYPE_1 ), + .C_PF1_ENTRY_RSVD0_1 (C_PF1_ENTRY_RSVD0_1 ), + .C_PF1_ENTRY_TYPE_2 (C_PF1_ENTRY_TYPE_2 ), + .C_PF1_ENTRY_BAR_2 (C_PF1_ENTRY_BAR_2 ), + .C_PF1_ENTRY_ADDR_2 (C_PF1_ENTRY_ADDR_2 ), + .C_PF1_ENTRY_MAJOR_VERSION_2 (C_PF1_ENTRY_MAJOR_VERSION_2 ), + .C_PF1_ENTRY_MINOR_VERSION_2 (C_PF1_ENTRY_MINOR_VERSION_2 ), + .C_PF1_ENTRY_VERSION_TYPE_2 (C_PF1_ENTRY_VERSION_TYPE_2 ), + .C_PF1_ENTRY_RSVD0_2 (C_PF1_ENTRY_RSVD0_2 ), + .C_PF1_ENTRY_TYPE_3 (C_PF1_ENTRY_TYPE_3 ), + .C_PF1_ENTRY_BAR_3 (C_PF1_ENTRY_BAR_3 ), + .C_PF1_ENTRY_ADDR_3 (C_PF1_ENTRY_ADDR_3 ), + .C_PF1_ENTRY_MAJOR_VERSION_3 (C_PF1_ENTRY_MAJOR_VERSION_3 ), + .C_PF1_ENTRY_MINOR_VERSION_3 (C_PF1_ENTRY_MINOR_VERSION_3 ), + .C_PF1_ENTRY_VERSION_TYPE_3 (C_PF1_ENTRY_VERSION_TYPE_3 ), + .C_PF1_ENTRY_RSVD0_3 (C_PF1_ENTRY_RSVD0_3 ), + .C_PF1_ENTRY_TYPE_4 (C_PF1_ENTRY_TYPE_4 ), + .C_PF1_ENTRY_BAR_4 (C_PF1_ENTRY_BAR_4 ), + .C_PF1_ENTRY_ADDR_4 (C_PF1_ENTRY_ADDR_4 ), + .C_PF1_ENTRY_MAJOR_VERSION_4 (C_PF1_ENTRY_MAJOR_VERSION_4 ), + .C_PF1_ENTRY_MINOR_VERSION_4 (C_PF1_ENTRY_MINOR_VERSION_4 ), + .C_PF1_ENTRY_VERSION_TYPE_4 (C_PF1_ENTRY_VERSION_TYPE_4 ), + .C_PF1_ENTRY_RSVD0_4 (C_PF1_ENTRY_RSVD0_4 ), + .C_PF1_ENTRY_TYPE_5 (C_PF1_ENTRY_TYPE_5 ), + .C_PF1_ENTRY_BAR_5 (C_PF1_ENTRY_BAR_5 ), + .C_PF1_ENTRY_ADDR_5 (C_PF1_ENTRY_ADDR_5 ), + .C_PF1_ENTRY_MAJOR_VERSION_5 (C_PF1_ENTRY_MAJOR_VERSION_5 ), + .C_PF1_ENTRY_MINOR_VERSION_5 (C_PF1_ENTRY_MINOR_VERSION_5 ), + .C_PF1_ENTRY_VERSION_TYPE_5 (C_PF1_ENTRY_VERSION_TYPE_5 ), + .C_PF1_ENTRY_RSVD0_5 (C_PF1_ENTRY_RSVD0_5 ), + .C_PF1_ENTRY_TYPE_6 (C_PF1_ENTRY_TYPE_6 ), + .C_PF1_ENTRY_BAR_6 (C_PF1_ENTRY_BAR_6 ), + .C_PF1_ENTRY_ADDR_6 (C_PF1_ENTRY_ADDR_6 ), + .C_PF1_ENTRY_MAJOR_VERSION_6 (C_PF1_ENTRY_MAJOR_VERSION_6 ), + .C_PF1_ENTRY_MINOR_VERSION_6 (C_PF1_ENTRY_MINOR_VERSION_6 ), + .C_PF1_ENTRY_VERSION_TYPE_6 (C_PF1_ENTRY_VERSION_TYPE_6 ), + .C_PF1_ENTRY_RSVD0_6 (C_PF1_ENTRY_RSVD0_6 ), + .C_PF1_ENTRY_TYPE_7 (C_PF1_ENTRY_TYPE_7 ), + .C_PF1_ENTRY_BAR_7 (C_PF1_ENTRY_BAR_7 ), + .C_PF1_ENTRY_ADDR_7 (C_PF1_ENTRY_ADDR_7 ), + .C_PF1_ENTRY_MAJOR_VERSION_7 (C_PF1_ENTRY_MAJOR_VERSION_7 ), + .C_PF1_ENTRY_MINOR_VERSION_7 (C_PF1_ENTRY_MINOR_VERSION_7 ), + .C_PF1_ENTRY_VERSION_TYPE_7 (C_PF1_ENTRY_VERSION_TYPE_7 ), + .C_PF1_ENTRY_RSVD0_7 (C_PF1_ENTRY_RSVD0_7 ), + .C_PF1_ENTRY_TYPE_8 (C_PF1_ENTRY_TYPE_8 ), + .C_PF1_ENTRY_BAR_8 (C_PF1_ENTRY_BAR_8 ), + .C_PF1_ENTRY_ADDR_8 (C_PF1_ENTRY_ADDR_8 ), + .C_PF1_ENTRY_MAJOR_VERSION_8 (C_PF1_ENTRY_MAJOR_VERSION_8 ), + .C_PF1_ENTRY_MINOR_VERSION_8 (C_PF1_ENTRY_MINOR_VERSION_8 ), + .C_PF1_ENTRY_VERSION_TYPE_8 (C_PF1_ENTRY_VERSION_TYPE_8 ), + .C_PF1_ENTRY_RSVD0_8 (C_PF1_ENTRY_RSVD0_8 ), + .C_PF1_ENTRY_TYPE_9 (C_PF1_ENTRY_TYPE_9 ), + .C_PF1_ENTRY_BAR_9 (C_PF1_ENTRY_BAR_9 ), + .C_PF1_ENTRY_ADDR_9 (C_PF1_ENTRY_ADDR_9 ), + .C_PF1_ENTRY_MAJOR_VERSION_9 (C_PF1_ENTRY_MAJOR_VERSION_9 ), + .C_PF1_ENTRY_MINOR_VERSION_9 (C_PF1_ENTRY_MINOR_VERSION_9 ), + .C_PF1_ENTRY_VERSION_TYPE_9 (C_PF1_ENTRY_VERSION_TYPE_9 ), + .C_PF1_ENTRY_RSVD0_9 (C_PF1_ENTRY_RSVD0_9 ), + .C_PF1_ENTRY_TYPE_10 (C_PF1_ENTRY_TYPE_10 ), + .C_PF1_ENTRY_BAR_10 (C_PF1_ENTRY_BAR_10 ), + .C_PF1_ENTRY_ADDR_10 (C_PF1_ENTRY_ADDR_10 ), + .C_PF1_ENTRY_MAJOR_VERSION_10 (C_PF1_ENTRY_MAJOR_VERSION_10 ), + .C_PF1_ENTRY_MINOR_VERSION_10 (C_PF1_ENTRY_MINOR_VERSION_10 ), + .C_PF1_ENTRY_VERSION_TYPE_10 (C_PF1_ENTRY_VERSION_TYPE_10 ), + .C_PF1_ENTRY_RSVD0_10 (C_PF1_ENTRY_RSVD0_10 ), + .C_PF1_ENTRY_TYPE_11 (C_PF1_ENTRY_TYPE_11 ), + .C_PF1_ENTRY_BAR_11 (C_PF1_ENTRY_BAR_11 ), + .C_PF1_ENTRY_ADDR_11 (C_PF1_ENTRY_ADDR_11 ), + .C_PF1_ENTRY_MAJOR_VERSION_11 (C_PF1_ENTRY_MAJOR_VERSION_11 ), + .C_PF1_ENTRY_MINOR_VERSION_11 (C_PF1_ENTRY_MINOR_VERSION_11 ), + .C_PF1_ENTRY_VERSION_TYPE_11 (C_PF1_ENTRY_VERSION_TYPE_11 ), + .C_PF1_ENTRY_RSVD0_11 (C_PF1_ENTRY_RSVD0_11 ), + .C_PF1_ENTRY_TYPE_12 (C_PF1_ENTRY_TYPE_12 ), + .C_PF1_ENTRY_BAR_12 (C_PF1_ENTRY_BAR_12 ), + .C_PF1_ENTRY_ADDR_12 (C_PF1_ENTRY_ADDR_12 ), + .C_PF1_ENTRY_MAJOR_VERSION_12 (C_PF1_ENTRY_MAJOR_VERSION_12 ), + .C_PF1_ENTRY_MINOR_VERSION_12 (C_PF1_ENTRY_MINOR_VERSION_12 ), + .C_PF1_ENTRY_VERSION_TYPE_12 (C_PF1_ENTRY_VERSION_TYPE_12 ), + .C_PF1_ENTRY_RSVD0_12 (C_PF1_ENTRY_RSVD0_12 ), + .C_PF1_ENTRY_TYPE_13 (C_PF1_ENTRY_TYPE_13 ), + .C_PF1_ENTRY_BAR_13 (C_PF1_ENTRY_BAR_13 ), + .C_PF1_ENTRY_ADDR_13 (C_PF1_ENTRY_ADDR_13 ), + .C_PF1_ENTRY_MAJOR_VERSION_13 (C_PF1_ENTRY_MAJOR_VERSION_13 ), + .C_PF1_ENTRY_MINOR_VERSION_13 (C_PF1_ENTRY_MINOR_VERSION_13 ), + .C_PF1_ENTRY_VERSION_TYPE_13 (C_PF1_ENTRY_VERSION_TYPE_13 ), + .C_PF1_ENTRY_RSVD0_13 (C_PF1_ENTRY_RSVD0_13 ), + .C_PF1_S_AXI_ADDR_WIDTH (C_PF1_S_AXI_ADDR_WIDTH ), + .C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF2_BAR_INDEX (C_PF2_BAR_INDEX ), + .C_PF2_LOW_OFFSET (C_PF2_LOW_OFFSET ), + .C_PF2_HIGH_OFFSET (C_PF2_HIGH_OFFSET ), + .C_PF2_ENTRY_TYPE_0 (C_PF2_ENTRY_TYPE_0 ), + .C_PF2_ENTRY_BAR_0 (C_PF2_ENTRY_BAR_0 ), + .C_PF2_ENTRY_ADDR_0 (C_PF2_ENTRY_ADDR_0 ), + .C_PF2_ENTRY_MAJOR_VERSION_0 (C_PF2_ENTRY_MAJOR_VERSION_0 ), + .C_PF2_ENTRY_MINOR_VERSION_0 (C_PF2_ENTRY_MINOR_VERSION_0 ), + .C_PF2_ENTRY_VERSION_TYPE_0 (C_PF2_ENTRY_VERSION_TYPE_0 ), + .C_PF2_ENTRY_RSVD0_0 (C_PF2_ENTRY_RSVD0_0 ), + .C_PF2_ENTRY_TYPE_1 (C_PF2_ENTRY_TYPE_1 ), + .C_PF2_ENTRY_BAR_1 (C_PF2_ENTRY_BAR_1 ), + .C_PF2_ENTRY_ADDR_1 (C_PF2_ENTRY_ADDR_1 ), + .C_PF2_ENTRY_MAJOR_VERSION_1 (C_PF2_ENTRY_MAJOR_VERSION_1 ), + .C_PF2_ENTRY_MINOR_VERSION_1 (C_PF2_ENTRY_MINOR_VERSION_1 ), + .C_PF2_ENTRY_VERSION_TYPE_1 (C_PF2_ENTRY_VERSION_TYPE_1 ), + .C_PF2_ENTRY_RSVD0_1 (C_PF2_ENTRY_RSVD0_1 ), + .C_PF2_ENTRY_TYPE_2 (C_PF2_ENTRY_TYPE_2 ), + .C_PF2_ENTRY_BAR_2 (C_PF2_ENTRY_BAR_2 ), + .C_PF2_ENTRY_ADDR_2 (C_PF2_ENTRY_ADDR_2 ), + .C_PF2_ENTRY_MAJOR_VERSION_2 (C_PF2_ENTRY_MAJOR_VERSION_2 ), + .C_PF2_ENTRY_MINOR_VERSION_2 (C_PF2_ENTRY_MINOR_VERSION_2 ), + .C_PF2_ENTRY_VERSION_TYPE_2 (C_PF2_ENTRY_VERSION_TYPE_2 ), + .C_PF2_ENTRY_RSVD0_2 (C_PF2_ENTRY_RSVD0_2 ), + .C_PF2_ENTRY_TYPE_3 (C_PF2_ENTRY_TYPE_3 ), + .C_PF2_ENTRY_BAR_3 (C_PF2_ENTRY_BAR_3 ), + .C_PF2_ENTRY_ADDR_3 (C_PF2_ENTRY_ADDR_3 ), + .C_PF2_ENTRY_MAJOR_VERSION_3 (C_PF2_ENTRY_MAJOR_VERSION_3 ), + .C_PF2_ENTRY_MINOR_VERSION_3 (C_PF2_ENTRY_MINOR_VERSION_3 ), + .C_PF2_ENTRY_VERSION_TYPE_3 (C_PF2_ENTRY_VERSION_TYPE_3 ), + .C_PF2_ENTRY_RSVD0_3 (C_PF2_ENTRY_RSVD0_3 ), + .C_PF2_ENTRY_TYPE_4 (C_PF2_ENTRY_TYPE_4 ), + .C_PF2_ENTRY_BAR_4 (C_PF2_ENTRY_BAR_4 ), + .C_PF2_ENTRY_ADDR_4 (C_PF2_ENTRY_ADDR_4 ), + .C_PF2_ENTRY_MAJOR_VERSION_4 (C_PF2_ENTRY_MAJOR_VERSION_4 ), + .C_PF2_ENTRY_MINOR_VERSION_4 (C_PF2_ENTRY_MINOR_VERSION_4 ), + .C_PF2_ENTRY_VERSION_TYPE_4 (C_PF2_ENTRY_VERSION_TYPE_4 ), + .C_PF2_ENTRY_RSVD0_4 (C_PF2_ENTRY_RSVD0_4 ), + .C_PF2_ENTRY_TYPE_5 (C_PF2_ENTRY_TYPE_5 ), + .C_PF2_ENTRY_BAR_5 (C_PF2_ENTRY_BAR_5 ), + .C_PF2_ENTRY_ADDR_5 (C_PF2_ENTRY_ADDR_5 ), + .C_PF2_ENTRY_MAJOR_VERSION_5 (C_PF2_ENTRY_MAJOR_VERSION_5 ), + .C_PF2_ENTRY_MINOR_VERSION_5 (C_PF2_ENTRY_MINOR_VERSION_5 ), + .C_PF2_ENTRY_VERSION_TYPE_5 (C_PF2_ENTRY_VERSION_TYPE_5 ), + .C_PF2_ENTRY_RSVD0_5 (C_PF2_ENTRY_RSVD0_5 ), + .C_PF2_ENTRY_TYPE_6 (C_PF2_ENTRY_TYPE_6 ), + .C_PF2_ENTRY_BAR_6 (C_PF2_ENTRY_BAR_6 ), + .C_PF2_ENTRY_ADDR_6 (C_PF2_ENTRY_ADDR_6 ), + .C_PF2_ENTRY_MAJOR_VERSION_6 (C_PF2_ENTRY_MAJOR_VERSION_6 ), + .C_PF2_ENTRY_MINOR_VERSION_6 (C_PF2_ENTRY_MINOR_VERSION_6 ), + .C_PF2_ENTRY_VERSION_TYPE_6 (C_PF2_ENTRY_VERSION_TYPE_6 ), + .C_PF2_ENTRY_RSVD0_6 (C_PF2_ENTRY_RSVD0_6 ), + .C_PF2_ENTRY_TYPE_7 (C_PF2_ENTRY_TYPE_7 ), + .C_PF2_ENTRY_BAR_7 (C_PF2_ENTRY_BAR_7 ), + .C_PF2_ENTRY_ADDR_7 (C_PF2_ENTRY_ADDR_7 ), + .C_PF2_ENTRY_MAJOR_VERSION_7 (C_PF2_ENTRY_MAJOR_VERSION_7 ), + .C_PF2_ENTRY_MINOR_VERSION_7 (C_PF2_ENTRY_MINOR_VERSION_7 ), + .C_PF2_ENTRY_VERSION_TYPE_7 (C_PF2_ENTRY_VERSION_TYPE_7 ), + .C_PF2_ENTRY_RSVD0_7 (C_PF2_ENTRY_RSVD0_7 ), + .C_PF2_ENTRY_TYPE_8 (C_PF2_ENTRY_TYPE_8 ), + .C_PF2_ENTRY_BAR_8 (C_PF2_ENTRY_BAR_8 ), + .C_PF2_ENTRY_ADDR_8 (C_PF2_ENTRY_ADDR_8 ), + .C_PF2_ENTRY_MAJOR_VERSION_8 (C_PF2_ENTRY_MAJOR_VERSION_8 ), + .C_PF2_ENTRY_MINOR_VERSION_8 (C_PF2_ENTRY_MINOR_VERSION_8 ), + .C_PF2_ENTRY_VERSION_TYPE_8 (C_PF2_ENTRY_VERSION_TYPE_8 ), + .C_PF2_ENTRY_RSVD0_8 (C_PF2_ENTRY_RSVD0_8 ), + .C_PF2_ENTRY_TYPE_9 (C_PF2_ENTRY_TYPE_9 ), + .C_PF2_ENTRY_BAR_9 (C_PF2_ENTRY_BAR_9 ), + .C_PF2_ENTRY_ADDR_9 (C_PF2_ENTRY_ADDR_9 ), + .C_PF2_ENTRY_MAJOR_VERSION_9 (C_PF2_ENTRY_MAJOR_VERSION_9 ), + .C_PF2_ENTRY_MINOR_VERSION_9 (C_PF2_ENTRY_MINOR_VERSION_9 ), + .C_PF2_ENTRY_VERSION_TYPE_9 (C_PF2_ENTRY_VERSION_TYPE_9 ), + .C_PF2_ENTRY_RSVD0_9 (C_PF2_ENTRY_RSVD0_9 ), + .C_PF2_ENTRY_TYPE_10 (C_PF2_ENTRY_TYPE_10 ), + .C_PF2_ENTRY_BAR_10 (C_PF2_ENTRY_BAR_10 ), + .C_PF2_ENTRY_ADDR_10 (C_PF2_ENTRY_ADDR_10 ), + .C_PF2_ENTRY_MAJOR_VERSION_10 (C_PF2_ENTRY_MAJOR_VERSION_10 ), + .C_PF2_ENTRY_MINOR_VERSION_10 (C_PF2_ENTRY_MINOR_VERSION_10 ), + .C_PF2_ENTRY_VERSION_TYPE_10 (C_PF2_ENTRY_VERSION_TYPE_10 ), + .C_PF2_ENTRY_RSVD0_10 (C_PF2_ENTRY_RSVD0_10 ), + .C_PF2_ENTRY_TYPE_11 (C_PF2_ENTRY_TYPE_11 ), + .C_PF2_ENTRY_BAR_11 (C_PF2_ENTRY_BAR_11 ), + .C_PF2_ENTRY_ADDR_11 (C_PF2_ENTRY_ADDR_11 ), + .C_PF2_ENTRY_MAJOR_VERSION_11 (C_PF2_ENTRY_MAJOR_VERSION_11 ), + .C_PF2_ENTRY_MINOR_VERSION_11 (C_PF2_ENTRY_MINOR_VERSION_11 ), + .C_PF2_ENTRY_VERSION_TYPE_11 (C_PF2_ENTRY_VERSION_TYPE_11 ), + .C_PF2_ENTRY_RSVD0_11 (C_PF2_ENTRY_RSVD0_11 ), + .C_PF2_ENTRY_TYPE_12 (C_PF2_ENTRY_TYPE_12 ), + .C_PF2_ENTRY_BAR_12 (C_PF2_ENTRY_BAR_12 ), + .C_PF2_ENTRY_ADDR_12 (C_PF2_ENTRY_ADDR_12 ), + .C_PF2_ENTRY_MAJOR_VERSION_12 (C_PF2_ENTRY_MAJOR_VERSION_12 ), + .C_PF2_ENTRY_MINOR_VERSION_12 (C_PF2_ENTRY_MINOR_VERSION_12 ), + .C_PF2_ENTRY_VERSION_TYPE_12 (C_PF2_ENTRY_VERSION_TYPE_12 ), + .C_PF2_ENTRY_RSVD0_12 (C_PF2_ENTRY_RSVD0_12 ), + .C_PF2_ENTRY_TYPE_13 (C_PF2_ENTRY_TYPE_13 ), + .C_PF2_ENTRY_BAR_13 (C_PF2_ENTRY_BAR_13 ), + .C_PF2_ENTRY_ADDR_13 (C_PF2_ENTRY_ADDR_13 ), + .C_PF2_ENTRY_MAJOR_VERSION_13 (C_PF2_ENTRY_MAJOR_VERSION_13 ), + .C_PF2_ENTRY_MINOR_VERSION_13 (C_PF2_ENTRY_MINOR_VERSION_13 ), + .C_PF2_ENTRY_VERSION_TYPE_13 (C_PF2_ENTRY_VERSION_TYPE_13 ), + .C_PF2_ENTRY_RSVD0_13 (C_PF2_ENTRY_RSVD0_13 ), + .C_PF2_S_AXI_ADDR_WIDTH (C_PF2_S_AXI_ADDR_WIDTH ), + .C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE (C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE ), + .C_PF3_BAR_INDEX (C_PF3_BAR_INDEX ), + .C_PF3_LOW_OFFSET (C_PF3_LOW_OFFSET ), + .C_PF3_HIGH_OFFSET (C_PF3_HIGH_OFFSET ), + .C_PF3_ENTRY_TYPE_0 (C_PF3_ENTRY_TYPE_0 ), + .C_PF3_ENTRY_BAR_0 (C_PF3_ENTRY_BAR_0 ), + .C_PF3_ENTRY_ADDR_0 (C_PF3_ENTRY_ADDR_0 ), + .C_PF3_ENTRY_MAJOR_VERSION_0 (C_PF3_ENTRY_MAJOR_VERSION_0 ), + .C_PF3_ENTRY_MINOR_VERSION_0 (C_PF3_ENTRY_MINOR_VERSION_0 ), + .C_PF3_ENTRY_VERSION_TYPE_0 (C_PF3_ENTRY_VERSION_TYPE_0 ), + .C_PF3_ENTRY_RSVD0_0 (C_PF3_ENTRY_RSVD0_0 ), + .C_PF3_ENTRY_TYPE_1 (C_PF3_ENTRY_TYPE_1 ), + .C_PF3_ENTRY_BAR_1 (C_PF3_ENTRY_BAR_1 ), + .C_PF3_ENTRY_ADDR_1 (C_PF3_ENTRY_ADDR_1 ), + .C_PF3_ENTRY_MAJOR_VERSION_1 (C_PF3_ENTRY_MAJOR_VERSION_1 ), + .C_PF3_ENTRY_MINOR_VERSION_1 (C_PF3_ENTRY_MINOR_VERSION_1 ), + .C_PF3_ENTRY_VERSION_TYPE_1 (C_PF3_ENTRY_VERSION_TYPE_1 ), + .C_PF3_ENTRY_RSVD0_1 (C_PF3_ENTRY_RSVD0_1 ), + .C_PF3_ENTRY_TYPE_2 (C_PF3_ENTRY_TYPE_2 ), + .C_PF3_ENTRY_BAR_2 (C_PF3_ENTRY_BAR_2 ), + .C_PF3_ENTRY_ADDR_2 (C_PF3_ENTRY_ADDR_2 ), + .C_PF3_ENTRY_MAJOR_VERSION_2 (C_PF3_ENTRY_MAJOR_VERSION_2 ), + .C_PF3_ENTRY_MINOR_VERSION_2 (C_PF3_ENTRY_MINOR_VERSION_2 ), + .C_PF3_ENTRY_VERSION_TYPE_2 (C_PF3_ENTRY_VERSION_TYPE_2 ), + .C_PF3_ENTRY_RSVD0_2 (C_PF3_ENTRY_RSVD0_2 ), + .C_PF3_ENTRY_TYPE_3 (C_PF3_ENTRY_TYPE_3 ), + .C_PF3_ENTRY_BAR_3 (C_PF3_ENTRY_BAR_3 ), + .C_PF3_ENTRY_ADDR_3 (C_PF3_ENTRY_ADDR_3 ), + .C_PF3_ENTRY_MAJOR_VERSION_3 (C_PF3_ENTRY_MAJOR_VERSION_3 ), + .C_PF3_ENTRY_MINOR_VERSION_3 (C_PF3_ENTRY_MINOR_VERSION_3 ), + .C_PF3_ENTRY_VERSION_TYPE_3 (C_PF3_ENTRY_VERSION_TYPE_3 ), + .C_PF3_ENTRY_RSVD0_3 (C_PF3_ENTRY_RSVD0_3 ), + .C_PF3_ENTRY_TYPE_4 (C_PF3_ENTRY_TYPE_4 ), + .C_PF3_ENTRY_BAR_4 (C_PF3_ENTRY_BAR_4 ), + .C_PF3_ENTRY_ADDR_4 (C_PF3_ENTRY_ADDR_4 ), + .C_PF3_ENTRY_MAJOR_VERSION_4 (C_PF3_ENTRY_MAJOR_VERSION_4 ), + .C_PF3_ENTRY_MINOR_VERSION_4 (C_PF3_ENTRY_MINOR_VERSION_4 ), + .C_PF3_ENTRY_VERSION_TYPE_4 (C_PF3_ENTRY_VERSION_TYPE_4 ), + .C_PF3_ENTRY_RSVD0_4 (C_PF3_ENTRY_RSVD0_4 ), + .C_PF3_ENTRY_TYPE_5 (C_PF3_ENTRY_TYPE_5 ), + .C_PF3_ENTRY_BAR_5 (C_PF3_ENTRY_BAR_5 ), + .C_PF3_ENTRY_ADDR_5 (C_PF3_ENTRY_ADDR_5 ), + .C_PF3_ENTRY_MAJOR_VERSION_5 (C_PF3_ENTRY_MAJOR_VERSION_5 ), + .C_PF3_ENTRY_MINOR_VERSION_5 (C_PF3_ENTRY_MINOR_VERSION_5 ), + .C_PF3_ENTRY_VERSION_TYPE_5 (C_PF3_ENTRY_VERSION_TYPE_5 ), + .C_PF3_ENTRY_RSVD0_5 (C_PF3_ENTRY_RSVD0_5 ), + .C_PF3_ENTRY_TYPE_6 (C_PF3_ENTRY_TYPE_6 ), + .C_PF3_ENTRY_BAR_6 (C_PF3_ENTRY_BAR_6 ), + .C_PF3_ENTRY_ADDR_6 (C_PF3_ENTRY_ADDR_6 ), + .C_PF3_ENTRY_MAJOR_VERSION_6 (C_PF3_ENTRY_MAJOR_VERSION_6 ), + .C_PF3_ENTRY_MINOR_VERSION_6 (C_PF3_ENTRY_MINOR_VERSION_6 ), + .C_PF3_ENTRY_VERSION_TYPE_6 (C_PF3_ENTRY_VERSION_TYPE_6 ), + .C_PF3_ENTRY_RSVD0_6 (C_PF3_ENTRY_RSVD0_6 ), + .C_PF3_ENTRY_TYPE_7 (C_PF3_ENTRY_TYPE_7 ), + .C_PF3_ENTRY_BAR_7 (C_PF3_ENTRY_BAR_7 ), + .C_PF3_ENTRY_ADDR_7 (C_PF3_ENTRY_ADDR_7 ), + .C_PF3_ENTRY_MAJOR_VERSION_7 (C_PF3_ENTRY_MAJOR_VERSION_7 ), + .C_PF3_ENTRY_MINOR_VERSION_7 (C_PF3_ENTRY_MINOR_VERSION_7 ), + .C_PF3_ENTRY_VERSION_TYPE_7 (C_PF3_ENTRY_VERSION_TYPE_7 ), + .C_PF3_ENTRY_RSVD0_7 (C_PF3_ENTRY_RSVD0_7 ), + .C_PF3_ENTRY_TYPE_8 (C_PF3_ENTRY_TYPE_8 ), + .C_PF3_ENTRY_BAR_8 (C_PF3_ENTRY_BAR_8 ), + .C_PF3_ENTRY_ADDR_8 (C_PF3_ENTRY_ADDR_8 ), + .C_PF3_ENTRY_MAJOR_VERSION_8 (C_PF3_ENTRY_MAJOR_VERSION_8 ), + .C_PF3_ENTRY_MINOR_VERSION_8 (C_PF3_ENTRY_MINOR_VERSION_8 ), + .C_PF3_ENTRY_VERSION_TYPE_8 (C_PF3_ENTRY_VERSION_TYPE_8 ), + .C_PF3_ENTRY_RSVD0_8 (C_PF3_ENTRY_RSVD0_8 ), + .C_PF3_ENTRY_TYPE_9 (C_PF3_ENTRY_TYPE_9 ), + .C_PF3_ENTRY_BAR_9 (C_PF3_ENTRY_BAR_9 ), + .C_PF3_ENTRY_ADDR_9 (C_PF3_ENTRY_ADDR_9 ), + .C_PF3_ENTRY_MAJOR_VERSION_9 (C_PF3_ENTRY_MAJOR_VERSION_9 ), + .C_PF3_ENTRY_MINOR_VERSION_9 (C_PF3_ENTRY_MINOR_VERSION_9 ), + .C_PF3_ENTRY_VERSION_TYPE_9 (C_PF3_ENTRY_VERSION_TYPE_9 ), + .C_PF3_ENTRY_RSVD0_9 (C_PF3_ENTRY_RSVD0_9 ), + .C_PF3_ENTRY_TYPE_10 (C_PF3_ENTRY_TYPE_10 ), + .C_PF3_ENTRY_BAR_10 (C_PF3_ENTRY_BAR_10 ), + .C_PF3_ENTRY_ADDR_10 (C_PF3_ENTRY_ADDR_10 ), + .C_PF3_ENTRY_MAJOR_VERSION_10 (C_PF3_ENTRY_MAJOR_VERSION_10 ), + .C_PF3_ENTRY_MINOR_VERSION_10 (C_PF3_ENTRY_MINOR_VERSION_10 ), + .C_PF3_ENTRY_VERSION_TYPE_10 (C_PF3_ENTRY_VERSION_TYPE_10 ), + .C_PF3_ENTRY_RSVD0_10 (C_PF3_ENTRY_RSVD0_10 ), + .C_PF3_ENTRY_TYPE_11 (C_PF3_ENTRY_TYPE_11 ), + .C_PF3_ENTRY_BAR_11 (C_PF3_ENTRY_BAR_11 ), + .C_PF3_ENTRY_ADDR_11 (C_PF3_ENTRY_ADDR_11 ), + .C_PF3_ENTRY_MAJOR_VERSION_11 (C_PF3_ENTRY_MAJOR_VERSION_11 ), + .C_PF3_ENTRY_MINOR_VERSION_11 (C_PF3_ENTRY_MINOR_VERSION_11 ), + .C_PF3_ENTRY_VERSION_TYPE_11 (C_PF3_ENTRY_VERSION_TYPE_11 ), + .C_PF3_ENTRY_RSVD0_11 (C_PF3_ENTRY_RSVD0_11 ), + .C_PF3_ENTRY_TYPE_12 (C_PF3_ENTRY_TYPE_12 ), + .C_PF3_ENTRY_BAR_12 (C_PF3_ENTRY_BAR_12 ), + .C_PF3_ENTRY_ADDR_12 (C_PF3_ENTRY_ADDR_12 ), + .C_PF3_ENTRY_MAJOR_VERSION_12 (C_PF3_ENTRY_MAJOR_VERSION_12 ), + .C_PF3_ENTRY_MINOR_VERSION_12 (C_PF3_ENTRY_MINOR_VERSION_12 ), + .C_PF3_ENTRY_VERSION_TYPE_12 (C_PF3_ENTRY_VERSION_TYPE_12 ), + .C_PF3_ENTRY_RSVD0_12 (C_PF3_ENTRY_RSVD0_12 ), + .C_PF3_ENTRY_TYPE_13 (C_PF3_ENTRY_TYPE_13 ), + .C_PF3_ENTRY_BAR_13 (C_PF3_ENTRY_BAR_13 ), + .C_PF3_ENTRY_ADDR_13 (C_PF3_ENTRY_ADDR_13 ), + .C_PF3_ENTRY_MAJOR_VERSION_13 (C_PF3_ENTRY_MAJOR_VERSION_13 ), + .C_PF3_ENTRY_MINOR_VERSION_13 (C_PF3_ENTRY_MINOR_VERSION_13 ), + .C_PF3_ENTRY_VERSION_TYPE_13 (C_PF3_ENTRY_VERSION_TYPE_13 ), + .C_PF3_ENTRY_RSVD0_13 (C_PF3_ENTRY_RSVD0_13 ), + .C_PF3_S_AXI_ADDR_WIDTH (C_PF3_S_AXI_ADDR_WIDTH ), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY ) + ) hw_disc_inst ( + .aclk_pcie (aclk_pcie ), + .aresetn_pcie (aresetn_pcie ), + .aclk_ctrl (aclk_ctrl ), + .aresetn_ctrl (aresetn_ctrl ), + .s_pcie4_cfg_ext_function_number (s_pcie4_cfg_ext_function_number ), + .s_pcie4_cfg_ext_read_data (s_pcie4_cfg_ext_read_data ), + .s_pcie4_cfg_ext_read_data_valid (s_pcie4_cfg_ext_read_data_valid ), + .s_pcie4_cfg_ext_read_received (s_pcie4_cfg_ext_read_received ), + .s_pcie4_cfg_ext_register_number (s_pcie4_cfg_ext_register_number ), + .s_pcie4_cfg_ext_write_byte_enable (s_pcie4_cfg_ext_write_byte_enable ), + .s_pcie4_cfg_ext_write_data (s_pcie4_cfg_ext_write_data ), + .s_pcie4_cfg_ext_write_received (s_pcie4_cfg_ext_write_received ), + .m_pcie4_cfg_ext_function_number (m_pcie4_cfg_ext_function_number ), + .m_pcie4_cfg_ext_read_data (m_pcie4_cfg_ext_read_data ), + .m_pcie4_cfg_ext_read_data_valid (m_pcie4_cfg_ext_read_data_valid ), + .m_pcie4_cfg_ext_read_received (m_pcie4_cfg_ext_read_received ), + .m_pcie4_cfg_ext_register_number (m_pcie4_cfg_ext_register_number ), + .m_pcie4_cfg_ext_write_byte_enable (m_pcie4_cfg_ext_write_byte_enable ), + .m_pcie4_cfg_ext_write_data (m_pcie4_cfg_ext_write_data ), + .m_pcie4_cfg_ext_write_received (m_pcie4_cfg_ext_write_received ), + .s_axi_ctrl_pf0_awaddr (s_axi_ctrl_pf0_awaddr ), + .s_axi_ctrl_pf0_awvalid (s_axi_ctrl_pf0_awvalid ), + .s_axi_ctrl_pf0_awready (s_axi_ctrl_pf0_awready ), + .s_axi_ctrl_pf0_wdata (s_axi_ctrl_pf0_wdata ), + .s_axi_ctrl_pf0_wstrb (s_axi_ctrl_pf0_wstrb ), + .s_axi_ctrl_pf0_wvalid (s_axi_ctrl_pf0_wvalid ), + .s_axi_ctrl_pf0_wready (s_axi_ctrl_pf0_wready ), + .s_axi_ctrl_pf0_bresp (s_axi_ctrl_pf0_bresp ), + .s_axi_ctrl_pf0_bvalid (s_axi_ctrl_pf0_bvalid ), + .s_axi_ctrl_pf0_bready (s_axi_ctrl_pf0_bready ), + .s_axi_ctrl_pf0_araddr (s_axi_ctrl_pf0_araddr ), + .s_axi_ctrl_pf0_arvalid (s_axi_ctrl_pf0_arvalid ), + .s_axi_ctrl_pf0_arready (s_axi_ctrl_pf0_arready ), + .s_axi_ctrl_pf0_rdata (s_axi_ctrl_pf0_rdata ), + .s_axi_ctrl_pf0_rresp (s_axi_ctrl_pf0_rresp ), + .s_axi_ctrl_pf0_rvalid (s_axi_ctrl_pf0_rvalid ), + .s_axi_ctrl_pf0_rready (s_axi_ctrl_pf0_rready ), + .s_axi_ctrl_pf1_awaddr (s_axi_ctrl_pf1_awaddr ), + .s_axi_ctrl_pf1_awvalid (s_axi_ctrl_pf1_awvalid ), + .s_axi_ctrl_pf1_awready (s_axi_ctrl_pf1_awready ), + .s_axi_ctrl_pf1_wdata (s_axi_ctrl_pf1_wdata ), + .s_axi_ctrl_pf1_wstrb (s_axi_ctrl_pf1_wstrb ), + .s_axi_ctrl_pf1_wvalid (s_axi_ctrl_pf1_wvalid ), + .s_axi_ctrl_pf1_wready (s_axi_ctrl_pf1_wready ), + .s_axi_ctrl_pf1_bresp (s_axi_ctrl_pf1_bresp ), + .s_axi_ctrl_pf1_bvalid (s_axi_ctrl_pf1_bvalid ), + .s_axi_ctrl_pf1_bready (s_axi_ctrl_pf1_bready ), + .s_axi_ctrl_pf1_araddr (s_axi_ctrl_pf1_araddr ), + .s_axi_ctrl_pf1_arvalid (s_axi_ctrl_pf1_arvalid ), + .s_axi_ctrl_pf1_arready (s_axi_ctrl_pf1_arready ), + .s_axi_ctrl_pf1_rdata (s_axi_ctrl_pf1_rdata ), + .s_axi_ctrl_pf1_rresp (s_axi_ctrl_pf1_rresp ), + .s_axi_ctrl_pf1_rvalid (s_axi_ctrl_pf1_rvalid ), + .s_axi_ctrl_pf1_rready (s_axi_ctrl_pf1_rready ), + .s_axi_ctrl_pf2_awaddr (s_axi_ctrl_pf2_awaddr ), + .s_axi_ctrl_pf2_awvalid (s_axi_ctrl_pf2_awvalid ), + .s_axi_ctrl_pf2_awready (s_axi_ctrl_pf2_awready ), + .s_axi_ctrl_pf2_wdata (s_axi_ctrl_pf2_wdata ), + .s_axi_ctrl_pf2_wstrb (s_axi_ctrl_pf2_wstrb ), + .s_axi_ctrl_pf2_wvalid (s_axi_ctrl_pf2_wvalid ), + .s_axi_ctrl_pf2_wready (s_axi_ctrl_pf2_wready ), + .s_axi_ctrl_pf2_bresp (s_axi_ctrl_pf2_bresp ), + .s_axi_ctrl_pf2_bvalid (s_axi_ctrl_pf2_bvalid ), + .s_axi_ctrl_pf2_bready (s_axi_ctrl_pf2_bready ), + .s_axi_ctrl_pf2_araddr (s_axi_ctrl_pf2_araddr ), + .s_axi_ctrl_pf2_arvalid (s_axi_ctrl_pf2_arvalid ), + .s_axi_ctrl_pf2_arready (s_axi_ctrl_pf2_arready ), + .s_axi_ctrl_pf2_rdata (s_axi_ctrl_pf2_rdata ), + .s_axi_ctrl_pf2_rresp (s_axi_ctrl_pf2_rresp ), + .s_axi_ctrl_pf2_rvalid (s_axi_ctrl_pf2_rvalid ), + .s_axi_ctrl_pf2_rready (s_axi_ctrl_pf2_rready ), + .s_axi_ctrl_pf3_awaddr (s_axi_ctrl_pf3_awaddr ), + .s_axi_ctrl_pf3_awvalid (s_axi_ctrl_pf3_awvalid ), + .s_axi_ctrl_pf3_awready (s_axi_ctrl_pf3_awready ), + .s_axi_ctrl_pf3_wdata (s_axi_ctrl_pf3_wdata ), + .s_axi_ctrl_pf3_wstrb (s_axi_ctrl_pf3_wstrb ), + .s_axi_ctrl_pf3_wvalid (s_axi_ctrl_pf3_wvalid ), + .s_axi_ctrl_pf3_wready (s_axi_ctrl_pf3_wready ), + .s_axi_ctrl_pf3_bresp (s_axi_ctrl_pf3_bresp ), + .s_axi_ctrl_pf3_bvalid (s_axi_ctrl_pf3_bvalid ), + .s_axi_ctrl_pf3_bready (s_axi_ctrl_pf3_bready ), + .s_axi_ctrl_pf3_araddr (s_axi_ctrl_pf3_araddr ), + .s_axi_ctrl_pf3_arvalid (s_axi_ctrl_pf3_arvalid ), + .s_axi_ctrl_pf3_arready (s_axi_ctrl_pf3_arready ), + .s_axi_ctrl_pf3_rdata (s_axi_ctrl_pf3_rdata ), + .s_axi_ctrl_pf3_rresp (s_axi_ctrl_pf3_rresp ), + .s_axi_ctrl_pf3_rvalid (s_axi_ctrl_pf3_rvalid ), + .s_axi_ctrl_pf3_rready (s_axi_ctrl_pf3_rready ) + ); + +endmodule diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/pcie_vsec.vhd b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/pcie_vsec.vhd new file mode 100644 index 00000000..6e5ac270 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/hdl/pcie_vsec.vhd @@ -0,0 +1,381 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_misc.all; + use ieee.numeric_std.all; + +library hw_discovery_v1_0_0; + +entity hw_discovery_v1_0_0_pcie_vsec is + generic( + C_NUM_PFS : integer range 1 to 4 := 1; + C_CAP_BASE_ADDR : std_logic_vector(11 downto 0) := x"480"; -- 0x480 default for PCIE4 + C_NEXT_CAP_ADDR : std_logic_vector(11 downto 0) := (others => '0'); + C_PF0_BAR_INDEX : integer range 0 to 6 := 0; + C_PF0_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF0_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF1_BAR_INDEX : integer range 0 to 6 := 0; + C_PF1_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF1_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF2_BAR_INDEX : integer range 0 to 6 := 0; + C_PF2_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF2_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_PF3_BAR_INDEX : integer range 0 to 6 := 0; + C_PF3_LOW_OFFSET : std_logic_vector(27 downto 0) := (others => '0'); + C_PF3_HIGH_OFFSET : std_logic_vector(31 downto 0) := (others => '0'); + C_XDEVICEFAMILY : string := "no_family" + ); + port( + + ----------------------------------------------------------------------- + -- Clocks & Resets + ----------------------------------------------------------------------- + + aclk_pcie : in std_logic; + aresetn_pcie : in std_logic; + + ----------------------------------------------------------------------- + -- pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + s_pcie4_cfg_ext_function_number : in std_logic_vector(15 downto 0); + s_pcie4_cfg_ext_read_data : out std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_read_data_valid : out std_logic; + s_pcie4_cfg_ext_read_received : in std_logic; + s_pcie4_cfg_ext_register_number : in std_logic_vector(9 downto 0); + s_pcie4_cfg_ext_write_byte_enable : in std_logic_vector(3 downto 0); + s_pcie4_cfg_ext_write_data : in std_logic_vector(31 downto 0); + s_pcie4_cfg_ext_write_received : in std_logic; + + ----------------------------------------------------------------------- + -- pcie4_cfg_ext Interface (aclk_pcie) + ----------------------------------------------------------------------- + + m_pcie4_cfg_ext_function_number : out std_logic_vector(15 downto 0); + m_pcie4_cfg_ext_read_data : in std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_read_data_valid : in std_logic; + m_pcie4_cfg_ext_read_received : out std_logic; + m_pcie4_cfg_ext_register_number : out std_logic_vector(9 downto 0); + m_pcie4_cfg_ext_write_byte_enable : out std_logic_vector(3 downto 0); + m_pcie4_cfg_ext_write_data : out std_logic_vector(31 downto 0); + m_pcie4_cfg_ext_write_received : out std_logic + + ); +end entity hw_discovery_v1_0_0_pcie_vsec; + +architecture rtl of hw_discovery_v1_0_0_pcie_vsec is + +------------------------------------------------------------------------------- +-- +-- CONSTANTS +-- +------------------------------------------------------------------------------- + +constant CAP_ID : std_logic_vector(15 downto 0) := x"000B"; +constant CAP_VERSION : std_logic_vector(3 downto 0) := x"1"; +constant VSEC_ID : std_logic_vector(15 downto 0) := x"0020"; +constant VSEC_REV : std_logic_vector(3 downto 0) := x"0"; +constant VSEC_LENGTH : std_logic_vector(11 downto 0) := x"010"; +constant NEXT_CAP_BASE_ADDR : integer := (to_integer(unsigned(C_CAP_BASE_ADDR)) + 16); +constant NEXT_CAP_CONFIG_ADDR : integer := (to_integer(unsigned(C_NEXT_CAP_ADDR))); +constant CAP_BASE_BYTE_ADDR : integer := (to_integer(unsigned(C_CAP_BASE_ADDR)) / 4); +constant CAP_BASE_ADDR : integer := (to_integer(unsigned(C_CAP_BASE_ADDR)) / 16); +constant ALF_VSEC_NXT_REG : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(NEXT_CAP_BASE_ADDR, 12)); +constant ALF_VSEC_CONFIG_NXT : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(NEXT_CAP_CONFIG_ADDR, 12)); +constant ALF_VSEC_BASE_REG : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(CAP_BASE_ADDR, 8)); +constant ALF_VSEC_REG_0 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned(CAP_BASE_BYTE_ADDR, s_pcie4_cfg_ext_register_number'LENGTH)); +constant ALF_VSEC_REG_1 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned((CAP_BASE_BYTE_ADDR + 1), s_pcie4_cfg_ext_register_number'LENGTH)); +constant ALF_VSEC_REG_2 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned((CAP_BASE_BYTE_ADDR + 2), s_pcie4_cfg_ext_register_number'LENGTH)); +constant ALF_VSEC_REG_3 : std_logic_vector(s_pcie4_cfg_ext_register_number'RANGE) := std_logic_vector(to_unsigned((CAP_BASE_BYTE_ADDR + 3), s_pcie4_cfg_ext_register_number'LENGTH)); +constant PF0_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF0_BAR_INDEX, 3)); +constant PF1_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF1_BAR_INDEX, 3)); +constant PF2_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF2_BAR_INDEX, 3)); +constant PF3_BAR_INDEX : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_PF3_BAR_INDEX, 3)); +constant NUM_PFS : std_logic_vector(1 downto 0) := std_logic_vector(to_unsigned((C_NUM_PFS - 1), 2)); + +------------------------------------------------------------------------------- +-- +-- SIGNALS +-- +------------------------------------------------------------------------------- + +signal cfg_ext_read_data : std_logic_vector(31 downto 0) := (others => '0'); +signal cfg_ext_read_data_valid : std_logic := '0'; + +signal enable_m_cfg_ext : std_logic := '0'; + +begin + + G_GENERATE_M_PCIE4_NXT_CFG_EXT : if (NEXT_CAP_CONFIG_ADDR >= NEXT_CAP_BASE_ADDR) generate + + CF: + process(aclk_pcie) + + begin + + if (rising_edge(aclk_pcie)) then + + m_pcie4_cfg_ext_function_number <= s_pcie4_cfg_ext_function_number; + m_pcie4_cfg_ext_read_received <= s_pcie4_cfg_ext_read_received; + m_pcie4_cfg_ext_register_number <= s_pcie4_cfg_ext_register_number; + m_pcie4_cfg_ext_write_byte_enable <= s_pcie4_cfg_ext_write_byte_enable; + m_pcie4_cfg_ext_write_data <= s_pcie4_cfg_ext_write_data; + m_pcie4_cfg_ext_write_received <= s_pcie4_cfg_ext_write_received; + + if (enable_m_cfg_ext = '1') then + s_pcie4_cfg_ext_read_data <= m_pcie4_cfg_ext_read_data; + s_pcie4_cfg_ext_read_data_valid <= m_pcie4_cfg_ext_read_data_valid; + else + s_pcie4_cfg_ext_read_data <= cfg_ext_read_data; + s_pcie4_cfg_ext_read_data_valid <= cfg_ext_read_data_valid; + end if; + + end if; + + end process; + + end generate G_GENERATE_M_PCIE4_NXT_CFG_EXT; + + G_GENERATE_M_PCIE4_CFG_EXT : if (NEXT_CAP_CONFIG_ADDR < NEXT_CAP_BASE_ADDR) generate + + CF: + process(aclk_pcie) + + begin + + if (rising_edge(aclk_pcie)) then + + s_pcie4_cfg_ext_read_data <= cfg_ext_read_data; + s_pcie4_cfg_ext_read_data_valid <= cfg_ext_read_data_valid; + + m_pcie4_cfg_ext_function_number <= (others => '0'); + m_pcie4_cfg_ext_read_received <= '0'; + m_pcie4_cfg_ext_register_number <= (others => '0'); + m_pcie4_cfg_ext_write_byte_enable <= (others => '0'); + m_pcie4_cfg_ext_write_data <= (others => '0'); + m_pcie4_cfg_ext_write_received <= '0'; + + end if; + + end process; + + end generate G_GENERATE_M_PCIE4_CFG_EXT; + + RD: + process(aclk_pcie) + + variable func_num_var : std_logic_vector(1 downto 0); + variable reg_num_var : std_logic_vector(1 downto 0); + + begin + + if (rising_edge(aclk_pcie)) then + + if (aresetn_pcie = '0') then + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + func_num_var := s_pcie4_cfg_ext_function_number(1 downto 0); + reg_num_var := s_pcie4_cfg_ext_register_number(1 downto 0); + enable_m_cfg_ext <= '0'; + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + + else + + -- default assignment + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + func_num_var := s_pcie4_cfg_ext_function_number(1 downto 0); + reg_num_var := s_pcie4_cfg_ext_register_number(1 downto 0); + + if (s_pcie4_cfg_ext_read_received = '1') then + + enable_m_cfg_ext <= '0'; + if (s_pcie4_cfg_ext_register_number(9 downto 2) = ALF_VSEC_BASE_REG) then + + -- default read response + cfg_ext_read_data_valid <= '1'; + cfg_ext_read_data <= (others => '0'); + + case func_num_var is + + when "00" => -- PF0 + + case reg_num_var is + + when "00" => + + -- PF0 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF0_LOW_OFFSET & '0' & PF0_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF0_HIGH_OFFSET; + + end case; + + when "01" => -- PF2 + + if (NUM_PFS > "00") then + + case reg_num_var is + + when "00" => + + -- PF1 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF1_LOW_OFFSET & '0' & PF1_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF1_HIGH_OFFSET; + + end case; + + end if; + + when "10" => -- PF2 + + if (NUM_PFS(1) = '1') then + + case reg_num_var is + + when "00" => + + -- PF0 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF2_LOW_OFFSET & '0' & PF2_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF2_HIGH_OFFSET; + + end case; + + end if; + + when others => -- PF3 + + if (NUM_PFS = "11") then + + case reg_num_var is + + when "00" => + + -- PF0 Extended Capability Header + + cfg_ext_read_data <= C_NEXT_CAP_ADDR & CAP_VERSION & CAP_ID; + + when "01" => + + -- VSEC Header - Identifies as Xilinx Additional List of Features (ALF) + + cfg_ext_read_data <= VSEC_LENGTH & VSEC_REV & VSEC_ID; + + when "10" => + + -- ALF Field 1 (BAR Index & Low Offset) + + cfg_ext_read_data <= C_PF3_LOW_OFFSET & '0' & PF3_BAR_INDEX; + + when others => + + -- ALF Field 2 (High Offset) + + cfg_ext_read_data <= C_PF3_HIGH_OFFSET; + + end case; + + end if; + + end case; + + elsif (NEXT_CAP_CONFIG_ADDR < NEXT_CAP_BASE_ADDR) then + + cfg_ext_read_data_valid <= '1'; + cfg_ext_read_data <= (others => '0'); + + elsif (s_pcie4_cfg_ext_register_number(9 downto 2) >= ALF_VSEC_CONFIG_NXT(11 downto 4)) then + + enable_m_cfg_ext <= '1'; + cfg_ext_read_data_valid <= '0'; + cfg_ext_read_data <= (others => '0'); + + else + + cfg_ext_read_data_valid <= '1'; + cfg_ext_read_data <= (others => '0'); + + end if; + + end if; + end if; + + end if; + + end process; + +end architecture rtl; diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_scriptext.tcl b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_scriptext.tcl new file mode 100644 index 00000000..95c7d800 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_scriptext.tcl @@ -0,0 +1,74 @@ +# (c) Copyright 2023, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set core [get_ips] +#set core [ipx::get_cores -from project] +set CompName [get_property NAME $core] +set ipdef [get_property IPDEF $core] + +create_bd_design ${CompName}_testbd +set dut [ create_bd_cell -type ip -vlnv $ipdef $CompName ] + + set orig [dict create] + foreach p [list_property $core CONFIG.*] { + if {$p != "CONFIG.Component_Name" && [llength [get_property $p $dut]] > 0} { + dict set orig $p [get_property $p $core] + dict set orig $p.VALUE_SRC [get_property $p.VALUE_SRC $core] + } + } + + set_property -dict $orig $dut + + # Create ports + set aresetn_0 [ create_bd_port -dir I -type rst aresetn_0 ] + set aclk_0 [ create_bd_port -dir I -type clk -freq_hz 100000000 aclk_0 ] + set_property CONFIG.ASSOCIATED_RESET {aresetn_0} $aclk_0 + connect_bd_net -net aclk_0_net [get_bd_ports aclk_0] [get_bd_pins $CompName/aclk_pcie] [get_bd_pins $CompName/aclk_ctrl] + connect_bd_net -net aresetn_0_net [get_bd_ports aresetn_0] [get_bd_pins $CompName/aresetn_pcie] [get_bd_pins $CompName/aresetn_ctrl] + make_bd_intf_pins_external [get_bd_intf_pins $CompName/s_pcie4_cfg_ext] + + # Create instances of axi_vip + set num_pfs [get_property CONFIG.C_NUM_PFS $dut] + for {set pf 0} {$pf < $num_pfs} {incr pf} { + set addr_wid [get_property CONFIG.C_PF${pf}_S_AXI_ADDR_WIDTH $dut] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip:* vip_${pf} + set_property -dict [ list \ + CONFIG.ADDR_WIDTH $addr_wid \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.INTERFACE_MODE {MASTER} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] [get_bd_cells vip_${pf}] + connect_bd_net -net aclk_0_net [get_bd_pins vip_${pf}/aclk] + connect_bd_net -net aresetn_0_net [get_bd_pins vip_${pf}/aresetn] + connect_bd_intf_net -intf_net vip_${pf}_net [get_bd_intf_pins vip_${pf}/M_AXI] [get_bd_intf_pins $CompName/s_axi_ctrl_pf${pf}] + } + + # Create address segments + create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_0/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf0/reg0] seg_s_axi_ctrl_pf0 + if {$num_pfs > 1} {create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_1/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf1/reg0] seg_s_axi_ctrl_pf1} + if {$num_pfs > 2} {create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_2/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf2/reg0] seg_s_axi_ctrl_pf2} + if {$num_pfs > 3} {create_bd_addr_seg -offset 0x00000000 -range 0x00010000 [get_bd_addr_spaces vip_3/Master_AXI] [get_bd_addr_segs $CompName/s_axi_ctrl_pf3/reg0] seg_s_axi_ctrl_pf3} + +validate_bd_design +save_bd_design diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_tb_sv.xit b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_tb_sv.xit new file mode 100644 index 00000000..67f83440 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_tb_sv.xit @@ -0,0 +1,197 @@ +# (c) Copyright 2023, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set CompName [get_property PARAM_VALUE.Component_Name] +set TBName ${CompName}_testtb +set DesignName ${CompName}_testbd +set WrapperName ${DesignName}_wrapper +set FILEPATH "simulation/${TBName}.sv" +set fid [add_ipfile ${FILEPATH}] +set num_pfs [get_property PARAM_VALUE.C_NUM_PFS] +puts_ipfile $fid "`timescale 1ps / 1ps" +puts_ipfile $fid "" +puts_ipfile $fid "module $TBName;" +puts_ipfile $fid " localparam CLK_PERIOD = 10000; //ps" +puts_ipfile $fid " localparam RESET_PULSE = 20; // cycles" +puts_ipfile $fid " localparam TIMEOUT = 100000; // cycles" +puts_ipfile $fid " reg aclk;" +puts_ipfile $fid " reg aresetn;" +puts_ipfile $fid " reg done = 0;" +puts_ipfile $fid "" +puts_ipfile $fid " initial begin" +puts_ipfile $fid " aclk = 1'b1;" +puts_ipfile $fid " forever #(CLK_PERIOD / 2) begin" +puts_ipfile $fid " aclk = ~aclk;" +puts_ipfile $fid " end" +puts_ipfile $fid " end" +puts_ipfile $fid "" +puts_ipfile $fid " initial begin" +puts_ipfile $fid " \$display(\"%t: %m: Starting testbench\", \$time);" +puts_ipfile $fid " aresetn = 1'b0;" +puts_ipfile $fid " #(CLK_PERIOD * RESET_PULSE) aresetn = 1'b1;" +puts_ipfile $fid " #(CLK_PERIOD * RESET_PULSE) mst_start_stimulus();" +puts_ipfile $fid " end" +puts_ipfile $fid "" +puts_ipfile $fid " $WrapperName exdes_top" +puts_ipfile $fid " (" +puts_ipfile $fid " .aclk_0(aclk)," +puts_ipfile $fid " .aresetn_0(aresetn)" +puts_ipfile $fid " );" +puts_ipfile $fid "" +puts_ipfile $fid " always @(posedge aclk) begin" +puts_ipfile $fid " if (done) begin" +puts_ipfile $fid " #(CLK_PERIOD * 10) \$display(\"%t: %m: SIMULATION PASSED\", \$time);" +puts_ipfile $fid " \$display(\"%t: %m: Test Completed Successfully\", \$time);" +puts_ipfile $fid " \$stop;" +puts_ipfile $fid " end" +puts_ipfile $fid " end" +puts_ipfile $fid "" +puts_ipfile $fid " initial begin" +puts_ipfile $fid " #(CLK_PERIOD * TIMEOUT) \$display(\"%t: %m: ERROR - Test timed out.\", \$time);" +puts_ipfile $fid " \$stop;" +puts_ipfile $fid " end" +puts_ipfile $fid "" + +set expect [dict create] +set inject [get_property PARAM_VALUE.C_INJECT_ENDPOINTS] +for {set pf 0} {$pf < $num_pfs} {incr pf} { + if {[llength $inject] > 1} { + set index 0 + set ep_filter [get_property PARAM_VALUE.C_PF${pf}_ENDPOINT_NAMES] + set bar_info [dict get $inject pcie_mapping_for /$CompName/s_axi_ctrl_pf${pf}] + set first_bar [lindex $bar_info 0] + set bar [dict get $first_bar bar] + set endpoints [dict get $inject endpoints_for_pcie_bar $pf $bar] + foreach {endpoint} $endpoints { + set endpoint_name [dict get $endpoint xrt_endpoint_name] + if {[dict exists $ep_filter $endpoint_name]} { + dict set expect ${pf} ${index} name $endpoint_name + dict set expect ${pf} ${index} offset [dict get $endpoint offset] + dict set expect ${pf} ${index} bar $bar + set vlnv_list [split [dict get $endpoint reg_abs] ":"] + set vlnv_version_list [split [lindex $vlnv_list 3] "."] + dict set expect ${pf} ${index} major [lindex $vlnv_version_list 0] + dict set expect ${pf} ${index} minor [lindex $vlnv_version_list 1] + dict set expect ${pf} ${index} etype [format %0d [dict get $ep_filter $endpoint_name type]] + dict set expect ${pf} ${index} reserve [format %0d [dict get $ep_filter $endpoint_name reserve]] + dict set expect ${pf} ${index} vtype 1 + incr index + } + } + lappend pf_slots $index + } else { + set num_slots [get_property PARAM_VALUE.C_PF${pf}_NUM_SLOTS_BAR_LAYOUT_TABLE] + lappend pf_slots $num_slots + for {set index 0} {$index < $num_slots} {incr index} { + dict set expect ${pf} ${index} offset [get_property PARAM_VALUE.C_PF${pf}_ENTRY_ADDR_${index}] + dict set expect ${pf} ${index} bar [get_property PARAM_VALUE.C_PF${pf}_ENTRY_BAR_${index}] + dict set expect ${pf} ${index} major [get_property PARAM_VALUE.C_PF${pf}_ENTRY_MAJOR_VERSION_${index}] + dict set expect ${pf} ${index} minor [get_property PARAM_VALUE.C_PF${pf}_ENTRY_MINOR_VERSION_${index}] + dict set expect ${pf} ${index} etype [format %0d [get_property PARAM_VALUE.C_PF${pf}_ENTRY_TYPE_${index}]] + dict set expect ${pf} ${index} reserve [format %0d [get_property PARAM_VALUE.C_PF${pf}_ENTRY_RSVD0_${index}]] + dict set expect ${pf} ${index} vtype [format %0d [get_property PARAM_VALUE.C_PF${pf}_ENTRY_VERSION_TYPE_${index}]] + } + } +} + +puts_ipfile $fid "reg \[31:0\] rdata;" +puts_ipfile $fid "reg \[47:0\] entry_addr;" +puts_ipfile $fid "reg \[2:0\] bar;" +puts_ipfile $fid "reg \[7:0\] major;" +puts_ipfile $fid "reg \[7:0\] minor;" +puts_ipfile $fid "reg \[7:0\] etype;" +puts_ipfile $fid "reg \[3:0\] reserve;" +puts_ipfile $fid "reg \[7:0\] vtype;" +puts_ipfile $fid "import axi_vip_pkg::*;" +for {set pf 0} {$pf < $num_pfs} {incr pf} { + puts_ipfile $fid "import ${DesignName}_vip_${pf}_0_pkg::*;" + puts_ipfile $fid "${DesignName}_vip_${pf}_0_mst_t mst_agent_${pf};" +} +puts_ipfile $fid "axi_transaction rd_trans;" +puts_ipfile $fid "" +puts_ipfile $fid "task mst_start_stimulus();" +for {set pf 0} {$pf < $num_pfs} {incr pf} { + puts_ipfile $fid " mst_agent_${pf} = new(\"master vip agent\",exdes_top.${DesignName}_i.vip_${pf}.inst.IF);" + puts_ipfile $fid " mst_agent_${pf}.start_master();" + puts_ipfile $fid "" + for {set index 0} {$index < [lindex $pf_slots $pf]} {incr index} { + set addr0 [expr 16 * $index + 16] + set addr1 [expr $addr0 + 4] + set addr2 [expr $addr0 + 8] + set bar [dict get $expect ${pf} ${index} bar] + regsub "0x" [format %x [dict get $expect ${pf} ${index} offset]] "" offset + regsub "0x" [format %x [dict get $expect ${pf} ${index} major]] "" major + regsub "0x" [format %x [dict get $expect ${pf} ${index} minor]] "" minor + regsub "0x" [format %x [dict get $expect ${pf} ${index} etype]] "" etype + regsub "0x" [format %x [dict get $expect ${pf} ${index} reserve]] "" reserve + regsub "0x" [format %x [dict get $expect ${pf} ${index} vtype]] "" vtype + puts_ipfile $fid " rd_trans = mst_agent_${pf}.rd_driver.create_transaction(\"read_ctrl_${pf}_${index}_0\");" + puts_ipfile $fid " RD_TRANSACTION_FAIL_${pf}_${index}a:assert(rd_trans.randomize());" + puts_ipfile $fid " rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN);" + puts_ipfile $fid " rd_trans.set_read_cmd(${addr0},XIL_AXI_BURST_TYPE_INCR,0,0,xil_axi_size_t'(2));" + puts_ipfile $fid " mst_agent_${pf}.rd_driver.send(rd_trans); " + puts_ipfile $fid " mst_agent_${pf}.rd_driver.wait_rsp(rd_trans);" + puts_ipfile $fid " rdata = rd_trans.get_data_beat(0);" + puts_ipfile $fid " etype = rdata\[7:0\];" + puts_ipfile $fid " bar = rdata\[15:13\];" + puts_ipfile $fid " entry_addr = rdata\[31:16\];" + puts_ipfile $fid "" + puts_ipfile $fid " rd_trans = mst_agent_${pf}.rd_driver.create_transaction(\"read_ctrl_${pf}_${index}_1\");" + puts_ipfile $fid " RD_TRANSACTION_FAIL_${pf}_${index}b:assert(rd_trans.randomize());" + puts_ipfile $fid " rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN);" + puts_ipfile $fid " rd_trans.set_read_cmd(${addr1},XIL_AXI_BURST_TYPE_INCR,0,0,xil_axi_size_t'(2));" + puts_ipfile $fid " mst_agent_${pf}.rd_driver.send(rd_trans); " + puts_ipfile $fid " mst_agent_${pf}.rd_driver.wait_rsp(rd_trans);" + puts_ipfile $fid " rdata = rd_trans.get_data_beat(0);" + puts_ipfile $fid " entry_addr\[47:16\] = rdata;" + puts_ipfile $fid "" + puts_ipfile $fid " rd_trans = mst_agent_${pf}.rd_driver.create_transaction(\"read_ctrl_${pf}_${index}_2\");" + puts_ipfile $fid " RD_TRANSACTION_FAIL_${pf}_${index}c:assert(rd_trans.randomize());" + puts_ipfile $fid " rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN);" + puts_ipfile $fid " rd_trans.set_read_cmd(${addr2},XIL_AXI_BURST_TYPE_INCR,0,0,xil_axi_size_t'(2));" + puts_ipfile $fid " mst_agent_${pf}.rd_driver.send(rd_trans); " + puts_ipfile $fid " mst_agent_${pf}.rd_driver.wait_rsp(rd_trans);" + puts_ipfile $fid " rdata = rd_trans.get_data_beat(0);" + puts_ipfile $fid " vtype = rdata\[7:0\];" + puts_ipfile $fid " minor = rdata\[15:8\];" + puts_ipfile $fid " major = rdata\[23:16\];" + puts_ipfile $fid " reserve = rdata\[27:24\];" + puts_ipfile $fid "" + if {[dict exists $expect ${pf} ${index} name]} { + set name [dict get $expect ${pf} ${index} name] + puts_ipfile $fid " \$info (\"PF${pf}, INDEX ${index}, ENDPOINT: ${name}\");" + } else { + puts_ipfile $fid " \$info (\"PF${pf}, INDEX ${index}\");" + } + puts_ipfile $fid " assert (entry_addr == 48'h${offset}) \$info (\"C_PF${pf}_ENTRY_ADDR_${index} = %0X.\", entry_addr); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_ADDR_${index} = %0X, expected ${offset}.\", entry_addr);" + puts_ipfile $fid " assert (bar == 3'h${bar}) \$info (\"C_PF${pf}_ENTRY_BAR_${index} = %0X.\", bar); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_BAR_${index} = %0X, expected ${bar}.\", bar);" + puts_ipfile $fid " assert (major == 8'h${major}) \$info (\"C_PF${pf}_ENTRY_MAJOR_VERSION_${index} = %0X.\", major); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_MAJOR_VERSION_${index} = %0X, expected ${major}.\", major);" + puts_ipfile $fid " assert (minor == 8'h${minor}) \$info (\"C_PF${pf}_ENTRY_MINOR_VERSION_${index} = %0X.\", minor); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_MINOR_VERSION_${index} = %0X, expected ${minor}.\", minor);" + puts_ipfile $fid " assert (etype == 8'h${etype}) \$info (\"C_PF${pf}_ENTRY_TYPE_${index} = %0X.\", etype); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_TYPE_${index} = %0X, expected ${etype}.\", etype);" + puts_ipfile $fid " assert (reserve == 4'h${reserve}) \$info (\"C_PF${pf}_ENTRY_RSVD0_${index} = %0X.\", reserve); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_RSVD0_${index} = %0X, expected ${reserve}.\", reserve);" + puts_ipfile $fid " assert (vtype == 8'h${vtype}) \$info (\"C_PF${pf}_ENTRY_VERSION_TYPE_${index} = %0X.\", vtype); else \$fatal (\"Mismatch C_PF${pf}_ENTRY_VERSION_TYPE_${index} = %0X, expected ${vtype}.\", vtype);" + puts_ipfile $fid "" + } +} +puts_ipfile $fid "done = 1;" +puts_ipfile $fid "endtask" +puts_ipfile $fid "" +puts_ipfile $fid "endmodule" +close_ipfile $fid diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_wrapper_sv.xit b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_wrapper_sv.xit new file mode 100644 index 00000000..08c6620e --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/ttcl/example_wrapper_sv.xit @@ -0,0 +1,47 @@ +# (c) Copyright 2023, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ +set CompName [get_property PARAM_VALUE.Component_Name] +set TBName ${CompName}_testtb +set DesignName ${CompName}_testbd +set WrapperName ${DesignName}_wrapper +set FILEPATH "simulation/${WrapperName}.sv" +set fid [add_ipfile ${FILEPATH}] +puts_ipfile $fid "`timescale 1 ps / 1 ps " +puts_ipfile $fid "module $WrapperName " +puts_ipfile $fid " (aclk_0, " +puts_ipfile $fid " aresetn_0); " +puts_ipfile $fid " input aclk_0; " +puts_ipfile $fid " input aresetn_0; " +puts_ipfile $fid " wire aclk_0; " +puts_ipfile $fid " wire aresetn_0; " +puts_ipfile $fid " $DesignName ${DesignName}_i " +puts_ipfile $fid " (.aclk_0(aclk_0), " +puts_ipfile $fid " .aresetn_0(aresetn_0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_function_number(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_read_data(), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_read_data_valid(), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_read_received(1'b0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_register_number(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_write_byte_enable(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_write_data(0), " +puts_ipfile $fid " .s_pcie4_cfg_ext_0_write_received(1'b0)); " +puts_ipfile $fid "endmodule " +close_ipfile $fid diff --git a/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/xgui/hw_discovery_v1_0.tcl b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/xgui/hw_discovery_v1_0.tcl new file mode 100644 index 00000000..381636e8 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/hw_discovery_v1_0/xgui/hw_discovery_v1_0.tcl @@ -0,0 +1,4719 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +proc init_gui { IPINST } { + set Component_Name [ ipgui::add_param $IPINST -parent $IPINST -name Component_Name ] + set General_Config [ipgui::add_page $IPINST -name "General Config"] + set C_MANUAL [ipgui::add_param $IPINST -name C_MANUAL -widget comboBox -parent $General_Config] + set_property tooltip "C_MANUAL: Manually configure all bar layout parameters (disables automatic propagation of endpoint metadata)" $C_MANUAL + set C_NUM_PFS [ipgui::add_param $IPINST -name C_NUM_PFS -widget comboBox -parent $General_Config] + set_property tooltip "C_NUM_PFS: Set the number of PFs" $C_NUM_PFS + set C_CAP_BASE_ADDR [ipgui::add_param $IPINST -name C_CAP_BASE_ADDR -parent $General_Config] + set_property tooltip "C_CAP_BASE_ADDR: Set the PCIe Extended Capability Base Address" $C_CAP_BASE_ADDR + set C_NEXT_CAP_ADDR [ipgui::add_param $IPINST -name C_NEXT_CAP_ADDR -parent $General_Config] + set_property tooltip "C_NEXT_CAP_ADDR: Set the Next Capability Pointer. Leave at 0x000 if this is the last capability. Valid range is from (C_CAP_BASE_ADDR + 0x010) - 0xFFF" $C_NEXT_CAP_ADDR + set C_PF0_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF0_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF0_ENDPOINT_NAMES: Dictionary of endpoint names for PF0" $C_PF0_ENDPOINT_NAMES + set C_PF1_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF1_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF1_ENDPOINT_NAMES: Dictionary of endpoint names for PF1" $C_PF1_ENDPOINT_NAMES + set C_PF2_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF2_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF2_ENDPOINT_NAMES: Dictionary of endpoint names for PF2" $C_PF2_ENDPOINT_NAMES + set C_PF3_ENDPOINT_NAMES [ipgui::add_param $IPINST -name C_PF3_ENDPOINT_NAMES -parent $General_Config] + set_property tooltip "C_PF3_ENDPOINT_NAMES: Dictionary of endpoint names for PF3" $C_PF3_ENDPOINT_NAMES + set C_INJECT_ENDPOINTS [ipgui::add_param $IPINST -name C_INJECT_ENDPOINTS -parent $General_Config] + set_property tooltip "C_INJECT_ENDPOINTS: Endpoint properties dictionary to inject in place of vitis metadata for test (used only if vitis call returns empty string)" $C_INJECT_ENDPOINTS + + set AXI_Group [ipgui::add_group $IPINST -name "AXI Configuration" -parent $General_Config] + set C_PF0_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF0_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF0_S_AXI_ADDR_WIDTH: Set the AXI address width for PF0 AXI inteface" $C_PF0_S_AXI_ADDR_WIDTH + set C_PF1_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF1_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF1_S_AXI_ADDR_WIDTH: Set the AXI address width for PF1 AXI inteface" $C_PF1_S_AXI_ADDR_WIDTH + set C_PF2_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF2_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF2_S_AXI_ADDR_WIDTH: Set the AXI address width for PF2 AXI inteface" $C_PF2_S_AXI_ADDR_WIDTH + set C_PF3_S_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name C_PF3_S_AXI_ADDR_WIDTH -parent $AXI_Group] + set_property tooltip "C_PF3_S_AXI_ADDR_WIDTH: Set the AXI address width for PF3 AXI inteface" $C_PF3_S_AXI_ADDR_WIDTH + + set PF0_Config [ipgui::add_page $IPINST -name "PF0 Configuration"] + set PF0_Group [ipgui::add_group $IPINST -name "PF0 - General Configuration" -parent $PF0_Config] + set C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF0_Group] + set_property tooltip "C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF0 (excluding the End of Table identifier)" $C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF0_BAR_INDEX [ipgui::add_param $IPINST -name C_PF0_BAR_INDEX -parent $PF0_Group] + set_property tooltip "C_PF0_BAR_INDEX: Set the BAR Index for PF0" $C_PF0_BAR_INDEX + set C_PF0_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF0_LOW_OFFSET -parent $PF0_Group] + set_property tooltip "C_PF0_LOW_OFFSET: Set the Low Address Offset for PF0" $C_PF0_LOW_OFFSET + set C_PF0_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF0_HIGH_OFFSET -parent $PF0_Group] + set_property tooltip "C_PF0_HIGH_OFFSET: Set the High Address Offset for PF0" $C_PF0_HIGH_OFFSET + + set PF0_Table_0_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 0 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_0 + set C_PF0_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_0 + set C_PF0_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_0 + set C_PF0_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_0 + set C_PF0_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_0 + set C_PF0_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_0 + set C_PF0_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_0 -parent $PF0_Table_0_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_0 + + set PF0_Table_1_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 1 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_1 + set C_PF0_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_1 + set C_PF0_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_1 + set C_PF0_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_1 + set C_PF0_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_1 + set C_PF0_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_1 + set C_PF0_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_1 -parent $PF0_Table_1_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_1 + + set PF0_Table_2_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 2 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_2 + set C_PF0_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_2 + set C_PF0_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_2 + set C_PF0_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_2 + set C_PF0_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_2 + set C_PF0_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_2 + set C_PF0_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_2 -parent $PF0_Table_2_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_2 + + set PF0_Table_3_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 3 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_3 + set C_PF0_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_3 + set C_PF0_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_3 + set C_PF0_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_3 + set C_PF0_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_3 + set C_PF0_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_3 + set C_PF0_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_3 -parent $PF0_Table_3_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_3 + + set PF0_Table_4_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 4 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_4 + set C_PF0_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_4 + set C_PF0_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_4 + set C_PF0_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_4 + set C_PF0_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_4 + set C_PF0_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_4 + set C_PF0_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_4 -parent $PF0_Table_4_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_4 + + set PF0_Table_5_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 5 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_5 + set C_PF0_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_5 + set C_PF0_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_5 + set C_PF0_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_5 + set C_PF0_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_5 + set C_PF0_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_5 + set C_PF0_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_5 -parent $PF0_Table_5_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_5 + + set PF0_Table_6_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 6 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_6 + set C_PF0_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_6 + set C_PF0_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_6 + set C_PF0_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_6 + set C_PF0_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_6 + set C_PF0_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_6 + set C_PF0_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_6 -parent $PF0_Table_6_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_6 + + set PF0_Table_7_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 7 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_7 + set C_PF0_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_7 + set C_PF0_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_7 + set C_PF0_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_7 + set C_PF0_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_7 + set C_PF0_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_7 + set C_PF0_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_7 -parent $PF0_Table_7_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_7 + + set PF0_Table_8_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 8 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_8 + set C_PF0_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_8 + set C_PF0_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_8 + set C_PF0_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_8 + set C_PF0_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_8 + set C_PF0_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_8 + set C_PF0_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_8 -parent $PF0_Table_8_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_8 + + set PF0_Table_9_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 9 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_9 + set C_PF0_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_9 + set C_PF0_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_9 + set C_PF0_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_9 + set C_PF0_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_9 + set C_PF0_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_9 + set C_PF0_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_9 -parent $PF0_Table_9_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_9 + + set PF0_Table_10_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 10 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_10 + set C_PF0_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_10 + set C_PF0_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_10 + set C_PF0_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_10 + set C_PF0_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_10 + set C_PF0_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_10 + set C_PF0_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_10 -parent $PF0_Table_10_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_10 + + set PF0_Table_11_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 11 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_11 + set C_PF0_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_11 + set C_PF0_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_11 + set C_PF0_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_11 + set C_PF0_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_11 + set C_PF0_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_11 + set C_PF0_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_11 -parent $PF0_Table_11_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_11 + + set PF0_Table_12_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 12 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_12 + set C_PF0_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_12 + set C_PF0_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_12 + set C_PF0_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_12 + set C_PF0_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_12 + set C_PF0_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_12 + set C_PF0_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_12 -parent $PF0_Table_12_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_12 + + set PF0_Table_13_Group [ipgui::add_group $IPINST -name "PF0 - Table Entry 13 Configuration" -parent $PF0_Config] + set C_PF0_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_TYPE_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF0_ENTRY_TYPE_13 + set C_PF0_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_BAR_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF0_ENTRY_BAR_13 + set C_PF0_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_ADDR_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF0_ENTRY_ADDR_13 + set C_PF0_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_VERSION_TYPE_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF0_ENTRY_VERSION_TYPE_13 + set C_PF0_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MAJOR_VERSION_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF0_ENTRY_MAJOR_VERSION_13 + set C_PF0_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_MINOR_VERSION_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF0_ENTRY_MINOR_VERSION_13 + set C_PF0_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF0_ENTRY_RSVD0_13 -parent $PF0_Table_13_Group] + set_property tooltip "C_PF0_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF0_ENTRY_RSVD0_13 + + set PF1_Config [ipgui::add_page $IPINST -name "PF1 Configuration"] + set PF1_Group [ipgui::add_group $IPINST -name "PF1 - General Configuration" -parent $PF1_Config] + set C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF1_Group] + set_property tooltip "C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF1 (excluding the End of Table identifier)" $C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF1_BAR_INDEX [ipgui::add_param $IPINST -name C_PF1_BAR_INDEX -parent $PF1_Group] + set_property tooltip "C_PF1_BAR_INDEX: Set the BAR Index for PF1" $C_PF1_BAR_INDEX + set C_PF1_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF1_LOW_OFFSET -parent $PF1_Group] + set_property tooltip "C_PF1_LOW_OFFSET: Set the Low Address Offset for PF1" $C_PF1_LOW_OFFSET + set C_PF1_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF1_HIGH_OFFSET -parent $PF1_Group] + set_property tooltip "C_PF1_HIGH_OFFSET: Set the High Address Offset for PF1" $C_PF1_HIGH_OFFSET + + set PF1_Table_0_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 0 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_0 + set C_PF1_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_0 + set C_PF1_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_0 + set C_PF1_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_0 + set C_PF1_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_0 + set C_PF1_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_0 + set C_PF1_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_0 -parent $PF1_Table_0_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_0 + + set PF1_Table_1_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 1 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_1 + set C_PF1_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_1 + set C_PF1_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_1 + set C_PF1_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_1 + set C_PF1_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_1 + set C_PF1_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_1 + set C_PF1_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_1 -parent $PF1_Table_1_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_1 + + set PF1_Table_2_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 2 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_2 + set C_PF1_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_2 + set C_PF1_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_2 + set C_PF1_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_2 + set C_PF1_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_2 + set C_PF1_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_2 + set C_PF1_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_2 -parent $PF1_Table_2_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_2 + + set PF1_Table_3_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 3 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_3 + set C_PF1_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_3 + set C_PF1_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_3 + set C_PF1_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_3 + set C_PF1_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_3 + set C_PF1_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_3 + set C_PF1_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_3 -parent $PF1_Table_3_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_3 + + set PF1_Table_4_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 4 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_4 + set C_PF1_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_4 + set C_PF1_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_4 + set C_PF1_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_4 + set C_PF1_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_4 + set C_PF1_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_4 + set C_PF1_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_4 -parent $PF1_Table_4_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_4 + + set PF1_Table_5_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 5 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_5 + set C_PF1_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_5 + set C_PF1_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_5 + set C_PF1_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_5 + set C_PF1_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_5 + set C_PF1_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_5 + set C_PF1_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_5 -parent $PF1_Table_5_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_5 + + set PF1_Table_6_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 6 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_6 + set C_PF1_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_6 + set C_PF1_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_6 + set C_PF1_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_6 + set C_PF1_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_6 + set C_PF1_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_6 + set C_PF1_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_6 -parent $PF1_Table_6_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_6 + + set PF1_Table_7_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 7 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_7 + set C_PF1_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_7 + set C_PF1_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_7 + set C_PF1_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_7 + set C_PF1_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_7 + set C_PF1_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_7 + set C_PF1_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_7 -parent $PF1_Table_7_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_7 + + set PF1_Table_8_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 8 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_8 + set C_PF1_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_8 + set C_PF1_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_8 + set C_PF1_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_8 + set C_PF1_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_8 + set C_PF1_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_8 + set C_PF1_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_8 -parent $PF1_Table_8_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_8 + + set PF1_Table_9_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 9 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_9 + set C_PF1_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_9 + set C_PF1_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_9 + set C_PF1_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_9 + set C_PF1_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_9 + set C_PF1_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_9 + set C_PF1_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_9 -parent $PF1_Table_9_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_9 + + set PF1_Table_10_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 10 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_10 + set C_PF1_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_10 + set C_PF1_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_10 + set C_PF1_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_10 + set C_PF1_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_10 + set C_PF1_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_10 + set C_PF1_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_10 -parent $PF1_Table_10_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_10 + + set PF1_Table_11_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 11 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_11 + set C_PF1_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_11 + set C_PF1_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_11 + set C_PF1_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_11 + set C_PF1_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_11 + set C_PF1_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_11 + set C_PF1_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_11 -parent $PF1_Table_11_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_11 + + set PF1_Table_12_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 12 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_12 + set C_PF1_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_12 + set C_PF1_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_12 + set C_PF1_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_12 + set C_PF1_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_12 + set C_PF1_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_12 + set C_PF1_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_12 -parent $PF1_Table_12_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_12 + + set PF1_Table_13_Group [ipgui::add_group $IPINST -name "PF1 - Table Entry 13 Configuration" -parent $PF1_Config] + set C_PF1_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_TYPE_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF1_ENTRY_TYPE_13 + set C_PF1_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_BAR_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF1_ENTRY_BAR_13 + set C_PF1_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_ADDR_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF1_ENTRY_ADDR_13 + set C_PF1_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_VERSION_TYPE_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF1_ENTRY_VERSION_TYPE_13 + set C_PF1_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MAJOR_VERSION_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF1_ENTRY_MAJOR_VERSION_13 + set C_PF1_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_MINOR_VERSION_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF1_ENTRY_MINOR_VERSION_13 + set C_PF1_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF1_ENTRY_RSVD0_13 -parent $PF1_Table_13_Group] + set_property tooltip "C_PF1_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF1_ENTRY_RSVD0_13 + + set PF2_Config [ipgui::add_page $IPINST -name "PF2 Configuration"] + set PF2_Group [ipgui::add_group $IPINST -name "PF2 - General Configuration" -parent $PF2_Config] + set C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF2_Group] + set_property tooltip "C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF2 (excluding the End of Table identifier)" $C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF2_BAR_INDEX [ipgui::add_param $IPINST -name C_PF2_BAR_INDEX -parent $PF2_Group] + set_property tooltip "C_PF2_BAR_INDEX: Set the BAR Index for PF2" $C_PF2_BAR_INDEX + set C_PF2_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF2_LOW_OFFSET -parent $PF2_Group] + set_property tooltip "C_PF2_LOW_OFFSET: Set the Low Address Offset for PF2" $C_PF2_LOW_OFFSET + set C_PF2_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF2_HIGH_OFFSET -parent $PF2_Group] + set_property tooltip "C_PF2_HIGH_OFFSET: Set the High Address Offset for PF2" $C_PF2_HIGH_OFFSET + + set PF2_Table_0_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 0 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_0 + set C_PF2_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_0 + set C_PF2_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_0 + set C_PF2_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_0 + set C_PF2_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_0 + set C_PF2_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_0 + set C_PF2_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_0 -parent $PF2_Table_0_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_0 + + set PF2_Table_1_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 1 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_1 + set C_PF2_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_1 + set C_PF2_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_1 + set C_PF2_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_1 + set C_PF2_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_1 + set C_PF2_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_1 + set C_PF2_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_1 -parent $PF2_Table_1_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_1 + + set PF2_Table_2_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 2 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_2 + set C_PF2_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_2 + set C_PF2_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_2 + set C_PF2_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_2 + set C_PF2_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_2 + set C_PF2_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_2 + set C_PF2_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_2 -parent $PF2_Table_2_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_2 + + set PF2_Table_3_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 3 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_3 + set C_PF2_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_3 + set C_PF2_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_3 + set C_PF2_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_3 + set C_PF2_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_3 + set C_PF2_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_3 + set C_PF2_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_3 -parent $PF2_Table_3_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_3 + + set PF2_Table_4_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 4 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_4 + set C_PF2_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_4 + set C_PF2_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_4 + set C_PF2_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_4 + set C_PF2_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_4 + set C_PF2_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_4 + set C_PF2_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_4 -parent $PF2_Table_4_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_4 + + set PF2_Table_5_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 5 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_5 + set C_PF2_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_5 + set C_PF2_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_5 + set C_PF2_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_5 + set C_PF2_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_5 + set C_PF2_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_5 + set C_PF2_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_5 -parent $PF2_Table_5_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_5 + + set PF2_Table_6_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 6 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_6 + set C_PF2_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_6 + set C_PF2_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_6 + set C_PF2_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_6 + set C_PF2_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_6 + set C_PF2_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_6 + set C_PF2_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_6 -parent $PF2_Table_6_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_6 + + set PF2_Table_7_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 7 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_7 + set C_PF2_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_7 + set C_PF2_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_7 + set C_PF2_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_7 + set C_PF2_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_7 + set C_PF2_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_7 + set C_PF2_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_7 -parent $PF2_Table_7_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_7 + + set PF2_Table_8_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 8 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_8 + set C_PF2_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_8 + set C_PF2_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_8 + set C_PF2_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_8 + set C_PF2_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_8 + set C_PF2_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_8 + set C_PF2_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_8 -parent $PF2_Table_8_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_8 + + set PF2_Table_9_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 9 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_9 + set C_PF2_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_9 + set C_PF2_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_9 + set C_PF2_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_9 + set C_PF2_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_9 + set C_PF2_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_9 + set C_PF2_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_9 -parent $PF2_Table_9_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_9 + + set PF2_Table_10_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 10 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_10 + set C_PF2_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_10 + set C_PF2_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_10 + set C_PF2_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_10 + set C_PF2_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_10 + set C_PF2_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_10 + set C_PF2_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_10 -parent $PF2_Table_10_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_10 + + set PF2_Table_11_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 11 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_11 + set C_PF2_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_11 + set C_PF2_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_11 + set C_PF2_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_11 + set C_PF2_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_11 + set C_PF2_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_11 + set C_PF2_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_11 -parent $PF2_Table_11_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_11 + + set PF2_Table_12_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 12 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_12 + set C_PF2_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_12 + set C_PF2_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_12 + set C_PF2_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_12 + set C_PF2_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_12 + set C_PF2_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_12 + set C_PF2_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_12 -parent $PF2_Table_12_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_12 + + set PF2_Table_13_Group [ipgui::add_group $IPINST -name "PF2 - Table Entry 13 Configuration" -parent $PF2_Config] + set C_PF2_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_TYPE_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF2_ENTRY_TYPE_13 + set C_PF2_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_BAR_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF2_ENTRY_BAR_13 + set C_PF2_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_ADDR_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF2_ENTRY_ADDR_13 + set C_PF2_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_VERSION_TYPE_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF2_ENTRY_VERSION_TYPE_13 + set C_PF2_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MAJOR_VERSION_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF2_ENTRY_MAJOR_VERSION_13 + set C_PF2_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_MINOR_VERSION_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF2_ENTRY_MINOR_VERSION_13 + set C_PF2_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF2_ENTRY_RSVD0_13 -parent $PF2_Table_13_Group] + set_property tooltip "C_PF2_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF2_ENTRY_RSVD0_13 + + set PF3_Config [ipgui::add_page $IPINST -name "PF3 Configuration"] + set PF3_Group [ipgui::add_group $IPINST -name "PF3 - General Configuration" -parent $PF3_Config] + set C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_param $IPINST -name C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $PF3_Group] + set_property tooltip "C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE: Set the number of Table Entries to be implemented for PF3 (excluding the End of Table identifier)" $C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set C_PF3_BAR_INDEX [ipgui::add_param $IPINST -name C_PF3_BAR_INDEX -parent $PF3_Group] + set_property tooltip "C_PF3_BAR_INDEX: Set the BAR Index for PF3" $C_PF3_BAR_INDEX + set C_PF3_LOW_OFFSET [ipgui::add_param $IPINST -name C_PF3_LOW_OFFSET -parent $PF3_Group] + set_property tooltip "C_PF3_LOW_OFFSET: Set the Low Address Offset for PF3" $C_PF3_LOW_OFFSET + set C_PF3_HIGH_OFFSET [ipgui::add_param $IPINST -name C_PF3_HIGH_OFFSET -parent $PF3_Group] + set_property tooltip "C_PF3_HIGH_OFFSET: Set the High Address Offset for PF3" $C_PF3_HIGH_OFFSET + + set PF3_Table_0_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 0 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_0: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_0 + set C_PF3_ENTRY_BAR_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_BAR_0: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_0 + set C_PF3_ENTRY_ADDR_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_0: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_0 + set C_PF3_ENTRY_VERSION_TYPE_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_0: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_0 + set C_PF3_ENTRY_MAJOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_0: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_0 + set C_PF3_ENTRY_MINOR_VERSION_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_0: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_0 + set C_PF3_ENTRY_RSVD0_0 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_0 -parent $PF3_Table_0_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_0: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_0 + + set PF3_Table_1_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 1 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_1: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_1 + set C_PF3_ENTRY_BAR_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_BAR_1: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_1 + set C_PF3_ENTRY_ADDR_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_1: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_1 + set C_PF3_ENTRY_VERSION_TYPE_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_1: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_1 + set C_PF3_ENTRY_MAJOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_1: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_1 + set C_PF3_ENTRY_MINOR_VERSION_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_1: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_1 + set C_PF3_ENTRY_RSVD0_1 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_1 -parent $PF3_Table_1_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_1: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_1 + + set PF3_Table_2_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 2 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_2: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_2 + set C_PF3_ENTRY_BAR_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_BAR_2: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_2 + set C_PF3_ENTRY_ADDR_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_2: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_2 + set C_PF3_ENTRY_VERSION_TYPE_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_2: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_2 + set C_PF3_ENTRY_MAJOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_2: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_2 + set C_PF3_ENTRY_MINOR_VERSION_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_2: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_2 + set C_PF3_ENTRY_RSVD0_2 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_2 -parent $PF3_Table_2_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_2: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_2 + + set PF3_Table_3_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 3 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_3: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_3 + set C_PF3_ENTRY_BAR_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_BAR_3: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_3 + set C_PF3_ENTRY_ADDR_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_3: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_3 + set C_PF3_ENTRY_VERSION_TYPE_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_3: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_3 + set C_PF3_ENTRY_MAJOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_3: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_3 + set C_PF3_ENTRY_MINOR_VERSION_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_3: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_3 + set C_PF3_ENTRY_RSVD0_3 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_3 -parent $PF3_Table_3_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_3: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_3 + + set PF3_Table_4_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 4 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_4: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_4 + set C_PF3_ENTRY_BAR_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_BAR_4: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_4 + set C_PF3_ENTRY_ADDR_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_4: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_4 + set C_PF3_ENTRY_VERSION_TYPE_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_4: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_4 + set C_PF3_ENTRY_MAJOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_4: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_4 + set C_PF3_ENTRY_MINOR_VERSION_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_4: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_4 + set C_PF3_ENTRY_RSVD0_4 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_4 -parent $PF3_Table_4_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_4: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_4 + + set PF3_Table_5_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 5 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_5: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_5 + set C_PF3_ENTRY_BAR_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_BAR_5: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_5 + set C_PF3_ENTRY_ADDR_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_5: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_5 + set C_PF3_ENTRY_VERSION_TYPE_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_5: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_5 + set C_PF3_ENTRY_MAJOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_5: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_5 + set C_PF3_ENTRY_MINOR_VERSION_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_5: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_5 + set C_PF3_ENTRY_RSVD0_5 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_5 -parent $PF3_Table_5_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_5: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_5 + + set PF3_Table_6_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 6 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_6: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_6 + set C_PF3_ENTRY_BAR_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_BAR_6: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_6 + set C_PF3_ENTRY_ADDR_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_6: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_6 + set C_PF3_ENTRY_VERSION_TYPE_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_6: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_6 + set C_PF3_ENTRY_MAJOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_6: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_6 + set C_PF3_ENTRY_MINOR_VERSION_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_6: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_6 + set C_PF3_ENTRY_RSVD0_6 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_6 -parent $PF3_Table_6_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_6: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_6 + + set PF3_Table_7_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 7 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_7: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_7 + set C_PF3_ENTRY_BAR_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_BAR_7: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_7 + set C_PF3_ENTRY_ADDR_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_7: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_7 + set C_PF3_ENTRY_VERSION_TYPE_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_7: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_7 + set C_PF3_ENTRY_MAJOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_7: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_7 + set C_PF3_ENTRY_MINOR_VERSION_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_7: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_7 + set C_PF3_ENTRY_RSVD0_7 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_7 -parent $PF3_Table_7_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_7: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_7 + + set PF3_Table_8_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 8 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_8: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_8 + set C_PF3_ENTRY_BAR_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_BAR_8: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_8 + set C_PF3_ENTRY_ADDR_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_8: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_8 + set C_PF3_ENTRY_VERSION_TYPE_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_8: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_8 + set C_PF3_ENTRY_MAJOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_8: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_8 + set C_PF3_ENTRY_MINOR_VERSION_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_8: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_8 + set C_PF3_ENTRY_RSVD0_8 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_8 -parent $PF3_Table_8_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_8: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_8 + + set PF3_Table_9_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 9 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_9: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_9 + set C_PF3_ENTRY_BAR_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_BAR_9: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_9 + set C_PF3_ENTRY_ADDR_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_9: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_9 + set C_PF3_ENTRY_VERSION_TYPE_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_9: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_9 + set C_PF3_ENTRY_MAJOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_9: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_9 + set C_PF3_ENTRY_MINOR_VERSION_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_9: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_9 + set C_PF3_ENTRY_RSVD0_9 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_9 -parent $PF3_Table_9_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_9: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_9 + + set PF3_Table_10_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 10 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_10: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_10 + set C_PF3_ENTRY_BAR_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_BAR_10: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_10 + set C_PF3_ENTRY_ADDR_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_10: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_10 + set C_PF3_ENTRY_VERSION_TYPE_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_10: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_10 + set C_PF3_ENTRY_MAJOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_10: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_10 + set C_PF3_ENTRY_MINOR_VERSION_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_10: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_10 + set C_PF3_ENTRY_RSVD0_10 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_10 -parent $PF3_Table_10_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_10: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_10 + + set PF3_Table_11_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 11 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_11: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_11 + set C_PF3_ENTRY_BAR_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_BAR_11: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_11 + set C_PF3_ENTRY_ADDR_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_11: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_11 + set C_PF3_ENTRY_VERSION_TYPE_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_11: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_11 + set C_PF3_ENTRY_MAJOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_11: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_11 + set C_PF3_ENTRY_MINOR_VERSION_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_11: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_11 + set C_PF3_ENTRY_RSVD0_11 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_11 -parent $PF3_Table_11_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_11: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_11 + + set PF3_Table_12_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 12 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_12: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_12 + set C_PF3_ENTRY_BAR_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_BAR_12: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_12 + set C_PF3_ENTRY_ADDR_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_12: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_12 + set C_PF3_ENTRY_VERSION_TYPE_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_12: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_12 + set C_PF3_ENTRY_MAJOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_12: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_12 + set C_PF3_ENTRY_MINOR_VERSION_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_12: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_12 + set C_PF3_ENTRY_RSVD0_12 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_12 -parent $PF3_Table_12_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_12: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_12 + + set PF3_Table_13_Group [ipgui::add_group $IPINST -name "PF3 - Table Entry 13 Configuration" -parent $PF3_Config] + set C_PF3_ENTRY_TYPE_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_TYPE_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_TYPE_13: Set the Type field for Table Entry 0" $C_PF3_ENTRY_TYPE_13 + set C_PF3_ENTRY_BAR_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_BAR_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_BAR_13: Set the BAR number field for Table Entry 0" $C_PF3_ENTRY_BAR_13 + set C_PF3_ENTRY_ADDR_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_ADDR_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_ADDR_13: Set the Address field for Table Entry 0" $C_PF3_ENTRY_ADDR_13 + set C_PF3_ENTRY_VERSION_TYPE_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_VERSION_TYPE_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_VERSION_TYPE_13: Set the Version Type for Table Entry 0" $C_PF3_ENTRY_VERSION_TYPE_13 + set C_PF3_ENTRY_MAJOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MAJOR_VERSION_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_MAJOR_VERSION_13: Set the Major Version field for Table Entry 0" $C_PF3_ENTRY_MAJOR_VERSION_13 + set C_PF3_ENTRY_MINOR_VERSION_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_MINOR_VERSION_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_MINOR_VERSION_13: Set the Minor Version field for Table Entry 0" $C_PF3_ENTRY_MINOR_VERSION_13 + set C_PF3_ENTRY_RSVD0_13 [ipgui::add_param $IPINST -name C_PF3_ENTRY_RSVD0_13 -parent $PF3_Table_13_Group] + set_property tooltip "C_PF3_ENTRY_RSVD0_13: Set the Reserved field 0 for Table Entry 0" $C_PF3_ENTRY_RSVD0_13 + + set PF0_Values [ipgui::add_page $IPINST -name "PF0 Values"] + set PF0_Values_General [ipgui::add_group $IPINST -name "PF0 - General Values" -parent $PF0_Values] + set T_PF0_GENERAL [ipgui::add_table $IPINST -name T_PF0_GENERAL -rows 4 -columns 2 -parent $PF0_Values_General] + set L_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF0_GENERAL] + set L_PF0_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF0_BAR_INDEX -text "C_PF0_BAR_INDEX " -parent $T_PF0_GENERAL] + set L_PF0_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF0_LOW_OFFSET -text "C_PF0_LOW_OFFSET " -parent $T_PF0_GENERAL] + set L_PF0_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF0_HIGH_OFFSET -text "C_PF0_HIGH_OFFSET " -parent $T_PF0_GENERAL] + set V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF0_GENERAL] + set V_PF0_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF0_BAR_INDEX -tclproc VAL_PF0_BAR_INDEX -parent $T_PF0_GENERAL] + set V_PF0_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF0_LOW_OFFSET -tclproc VAL_PF0_LOW_OFFSET -parent $T_PF0_GENERAL] + set V_PF0_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF0_HIGH_OFFSET -tclproc VAL_PF0_HIGH_OFFSET -parent $T_PF0_GENERAL] + set_property cell_location 0,0 $L_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF0_BAR_INDEX + set_property cell_location 2,0 $L_PF0_LOW_OFFSET + set_property cell_location 3,0 $L_PF0_HIGH_OFFSET + set_property cell_location 0,1 $V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF0_BAR_INDEX + set_property cell_location 2,1 $V_PF0_LOW_OFFSET + set_property cell_location 3,1 $V_PF0_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF0_BAR_INDEX + set_property obj_color "192,192,192" $V_PF0_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF0_HIGH_OFFSET + + set PF0_Values_0 [ipgui::add_group $IPINST -name "PF0 - Table Entry 0 Values" -parent $PF0_Values] + set T_PF0_0 [ipgui::add_table $IPINST -name T_PF0_0 -rows 7 -columns 2 -parent $PF0_Values_0] + set L_PF0_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_0 -text "C_PF0_ENTRY_TYPE_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_0 -text "C_PF0_ENTRY_BAR_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_0 -text "C_PF0_ENTRY_ADDR_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_0 -text "C_PF0_ENTRY_VERSION_TYPE_0 " -parent $T_PF0_0] + set L_PF0_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_0 -text "C_PF0_ENTRY_MAJOR_VERSION_0" -parent $T_PF0_0] + set L_PF0_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_0 -text "C_PF0_ENTRY_MINOR_VERSION_0" -parent $T_PF0_0] + set L_PF0_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_0 -text "C_PF0_ENTRY_RSVD0_0 " -parent $T_PF0_0] + set V_PF0_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_0 -tclproc VAL_PF0_ENTRY_TYPE_0 -parent $T_PF0_0] + set V_PF0_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_0 -tclproc VAL_PF0_ENTRY_BAR_0 -parent $T_PF0_0] + set V_PF0_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_0 -tclproc VAL_PF0_ENTRY_ADDR_0 -parent $T_PF0_0] + set V_PF0_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_0 -parent $T_PF0_0] + set V_PF0_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_0 -parent $T_PF0_0] + set V_PF0_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_0 -parent $T_PF0_0] + set V_PF0_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_0 -tclproc VAL_PF0_ENTRY_RSVD0_0 -parent $T_PF0_0] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_0 + + set PF0_Values_1 [ipgui::add_group $IPINST -name "PF0 - Table Entry 1 Values" -parent $PF0_Values] + set T_PF0_1 [ipgui::add_table $IPINST -name T_PF0_1 -rows 7 -columns 2 -parent $PF0_Values_1] + set L_PF0_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_1 -text "C_PF0_ENTRY_TYPE_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_1 -text "C_PF0_ENTRY_BAR_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_1 -text "C_PF0_ENTRY_ADDR_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_1 -text "C_PF0_ENTRY_VERSION_TYPE_1 " -parent $T_PF0_1] + set L_PF0_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_1 -text "C_PF0_ENTRY_MAJOR_VERSION_1" -parent $T_PF0_1] + set L_PF0_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_1 -text "C_PF0_ENTRY_MINOR_VERSION_1" -parent $T_PF0_1] + set L_PF0_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_1 -text "C_PF0_ENTRY_RSVD0_1 " -parent $T_PF0_1] + set V_PF0_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_1 -tclproc VAL_PF0_ENTRY_TYPE_1 -parent $T_PF0_1] + set V_PF0_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_1 -tclproc VAL_PF0_ENTRY_BAR_1 -parent $T_PF0_1] + set V_PF0_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_1 -tclproc VAL_PF0_ENTRY_ADDR_1 -parent $T_PF0_1] + set V_PF0_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_1 -parent $T_PF0_1] + set V_PF0_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_1 -parent $T_PF0_1] + set V_PF0_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_1 -parent $T_PF0_1] + set V_PF0_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_1 -tclproc VAL_PF0_ENTRY_RSVD0_1 -parent $T_PF0_1] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_1 + + set PF0_Values_2 [ipgui::add_group $IPINST -name "PF0 - Table Entry 2 Values" -parent $PF0_Values] + set T_PF0_2 [ipgui::add_table $IPINST -name T_PF0_2 -rows 7 -columns 2 -parent $PF0_Values_2] + set L_PF0_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_2 -text "C_PF0_ENTRY_TYPE_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_2 -text "C_PF0_ENTRY_BAR_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_2 -text "C_PF0_ENTRY_ADDR_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_2 -text "C_PF0_ENTRY_VERSION_TYPE_2 " -parent $T_PF0_2] + set L_PF0_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_2 -text "C_PF0_ENTRY_MAJOR_VERSION_2" -parent $T_PF0_2] + set L_PF0_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_2 -text "C_PF0_ENTRY_MINOR_VERSION_2" -parent $T_PF0_2] + set L_PF0_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_2 -text "C_PF0_ENTRY_RSVD0_2 " -parent $T_PF0_2] + set V_PF0_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_2 -tclproc VAL_PF0_ENTRY_TYPE_2 -parent $T_PF0_2] + set V_PF0_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_2 -tclproc VAL_PF0_ENTRY_BAR_2 -parent $T_PF0_2] + set V_PF0_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_2 -tclproc VAL_PF0_ENTRY_ADDR_2 -parent $T_PF0_2] + set V_PF0_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_2 -parent $T_PF0_2] + set V_PF0_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_2 -parent $T_PF0_2] + set V_PF0_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_2 -parent $T_PF0_2] + set V_PF0_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_2 -tclproc VAL_PF0_ENTRY_RSVD0_2 -parent $T_PF0_2] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_2 + + set PF0_Values_3 [ipgui::add_group $IPINST -name "PF0 - Table Entry 3 Values" -parent $PF0_Values] + set T_PF0_3 [ipgui::add_table $IPINST -name T_PF0_3 -rows 7 -columns 2 -parent $PF0_Values_3] + set L_PF0_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_3 -text "C_PF0_ENTRY_TYPE_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_3 -text "C_PF0_ENTRY_BAR_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_3 -text "C_PF0_ENTRY_ADDR_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_3 -text "C_PF0_ENTRY_VERSION_TYPE_3 " -parent $T_PF0_3] + set L_PF0_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_3 -text "C_PF0_ENTRY_MAJOR_VERSION_3" -parent $T_PF0_3] + set L_PF0_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_3 -text "C_PF0_ENTRY_MINOR_VERSION_3" -parent $T_PF0_3] + set L_PF0_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_3 -text "C_PF0_ENTRY_RSVD0_3 " -parent $T_PF0_3] + set V_PF0_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_3 -tclproc VAL_PF0_ENTRY_TYPE_3 -parent $T_PF0_3] + set V_PF0_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_3 -tclproc VAL_PF0_ENTRY_BAR_3 -parent $T_PF0_3] + set V_PF0_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_3 -tclproc VAL_PF0_ENTRY_ADDR_3 -parent $T_PF0_3] + set V_PF0_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_3 -parent $T_PF0_3] + set V_PF0_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_3 -parent $T_PF0_3] + set V_PF0_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_3 -parent $T_PF0_3] + set V_PF0_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_3 -tclproc VAL_PF0_ENTRY_RSVD0_3 -parent $T_PF0_3] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_3 + + set PF0_Values_4 [ipgui::add_group $IPINST -name "PF0 - Table Entry 4 Values" -parent $PF0_Values] + set T_PF0_4 [ipgui::add_table $IPINST -name T_PF0_4 -rows 7 -columns 2 -parent $PF0_Values_4] + set L_PF0_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_4 -text "C_PF0_ENTRY_TYPE_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_4 -text "C_PF0_ENTRY_BAR_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_4 -text "C_PF0_ENTRY_ADDR_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_4 -text "C_PF0_ENTRY_VERSION_TYPE_4 " -parent $T_PF0_4] + set L_PF0_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_4 -text "C_PF0_ENTRY_MAJOR_VERSION_4" -parent $T_PF0_4] + set L_PF0_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_4 -text "C_PF0_ENTRY_MINOR_VERSION_4" -parent $T_PF0_4] + set L_PF0_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_4 -text "C_PF0_ENTRY_RSVD0_4 " -parent $T_PF0_4] + set V_PF0_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_4 -tclproc VAL_PF0_ENTRY_TYPE_4 -parent $T_PF0_4] + set V_PF0_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_4 -tclproc VAL_PF0_ENTRY_BAR_4 -parent $T_PF0_4] + set V_PF0_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_4 -tclproc VAL_PF0_ENTRY_ADDR_4 -parent $T_PF0_4] + set V_PF0_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_4 -parent $T_PF0_4] + set V_PF0_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_4 -parent $T_PF0_4] + set V_PF0_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_4 -parent $T_PF0_4] + set V_PF0_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_4 -tclproc VAL_PF0_ENTRY_RSVD0_4 -parent $T_PF0_4] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_4 + + set PF0_Values_5 [ipgui::add_group $IPINST -name "PF0 - Table Entry 5 Values" -parent $PF0_Values] + set T_PF0_5 [ipgui::add_table $IPINST -name T_PF0_5 -rows 7 -columns 2 -parent $PF0_Values_5] + set L_PF0_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_5 -text "C_PF0_ENTRY_TYPE_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_5 -text "C_PF0_ENTRY_BAR_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_5 -text "C_PF0_ENTRY_ADDR_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_5 -text "C_PF0_ENTRY_VERSION_TYPE_5 " -parent $T_PF0_5] + set L_PF0_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_5 -text "C_PF0_ENTRY_MAJOR_VERSION_5" -parent $T_PF0_5] + set L_PF0_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_5 -text "C_PF0_ENTRY_MINOR_VERSION_5" -parent $T_PF0_5] + set L_PF0_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_5 -text "C_PF0_ENTRY_RSVD0_5 " -parent $T_PF0_5] + set V_PF0_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_5 -tclproc VAL_PF0_ENTRY_TYPE_5 -parent $T_PF0_5] + set V_PF0_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_5 -tclproc VAL_PF0_ENTRY_BAR_5 -parent $T_PF0_5] + set V_PF0_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_5 -tclproc VAL_PF0_ENTRY_ADDR_5 -parent $T_PF0_5] + set V_PF0_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_5 -parent $T_PF0_5] + set V_PF0_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_5 -parent $T_PF0_5] + set V_PF0_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_5 -parent $T_PF0_5] + set V_PF0_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_5 -tclproc VAL_PF0_ENTRY_RSVD0_5 -parent $T_PF0_5] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_5 + + set PF0_Values_6 [ipgui::add_group $IPINST -name "PF0 - Table Entry 6 Values" -parent $PF0_Values] + set T_PF0_6 [ipgui::add_table $IPINST -name T_PF0_6 -rows 7 -columns 2 -parent $PF0_Values_6] + set L_PF0_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_6 -text "C_PF0_ENTRY_TYPE_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_6 -text "C_PF0_ENTRY_BAR_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_6 -text "C_PF0_ENTRY_ADDR_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_6 -text "C_PF0_ENTRY_VERSION_TYPE_6 " -parent $T_PF0_6] + set L_PF0_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_6 -text "C_PF0_ENTRY_MAJOR_VERSION_6" -parent $T_PF0_6] + set L_PF0_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_6 -text "C_PF0_ENTRY_MINOR_VERSION_6" -parent $T_PF0_6] + set L_PF0_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_6 -text "C_PF0_ENTRY_RSVD0_6 " -parent $T_PF0_6] + set V_PF0_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_6 -tclproc VAL_PF0_ENTRY_TYPE_6 -parent $T_PF0_6] + set V_PF0_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_6 -tclproc VAL_PF0_ENTRY_BAR_6 -parent $T_PF0_6] + set V_PF0_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_6 -tclproc VAL_PF0_ENTRY_ADDR_6 -parent $T_PF0_6] + set V_PF0_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_6 -parent $T_PF0_6] + set V_PF0_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_6 -parent $T_PF0_6] + set V_PF0_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_6 -parent $T_PF0_6] + set V_PF0_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_6 -tclproc VAL_PF0_ENTRY_RSVD0_6 -parent $T_PF0_6] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_6 + + set PF0_Values_7 [ipgui::add_group $IPINST -name "PF0 - Table Entry 7 Values" -parent $PF0_Values] + set T_PF0_7 [ipgui::add_table $IPINST -name T_PF0_7 -rows 7 -columns 2 -parent $PF0_Values_7] + set L_PF0_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_7 -text "C_PF0_ENTRY_TYPE_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_7 -text "C_PF0_ENTRY_BAR_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_7 -text "C_PF0_ENTRY_ADDR_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_7 -text "C_PF0_ENTRY_VERSION_TYPE_7 " -parent $T_PF0_7] + set L_PF0_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_7 -text "C_PF0_ENTRY_MAJOR_VERSION_7" -parent $T_PF0_7] + set L_PF0_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_7 -text "C_PF0_ENTRY_MINOR_VERSION_7" -parent $T_PF0_7] + set L_PF0_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_7 -text "C_PF0_ENTRY_RSVD0_7 " -parent $T_PF0_7] + set V_PF0_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_7 -tclproc VAL_PF0_ENTRY_TYPE_7 -parent $T_PF0_7] + set V_PF0_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_7 -tclproc VAL_PF0_ENTRY_BAR_7 -parent $T_PF0_7] + set V_PF0_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_7 -tclproc VAL_PF0_ENTRY_ADDR_7 -parent $T_PF0_7] + set V_PF0_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_7 -parent $T_PF0_7] + set V_PF0_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_7 -parent $T_PF0_7] + set V_PF0_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_7 -parent $T_PF0_7] + set V_PF0_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_7 -tclproc VAL_PF0_ENTRY_RSVD0_7 -parent $T_PF0_7] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_7 + + set PF0_Values_8 [ipgui::add_group $IPINST -name "PF0 - Table Entry 8 Values" -parent $PF0_Values] + set T_PF0_8 [ipgui::add_table $IPINST -name T_PF0_8 -rows 7 -columns 2 -parent $PF0_Values_8] + set L_PF0_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_8 -text "C_PF0_ENTRY_TYPE_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_8 -text "C_PF0_ENTRY_BAR_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_8 -text "C_PF0_ENTRY_ADDR_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_8 -text "C_PF0_ENTRY_VERSION_TYPE_8 " -parent $T_PF0_8] + set L_PF0_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_8 -text "C_PF0_ENTRY_MAJOR_VERSION_8" -parent $T_PF0_8] + set L_PF0_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_8 -text "C_PF0_ENTRY_MINOR_VERSION_8" -parent $T_PF0_8] + set L_PF0_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_8 -text "C_PF0_ENTRY_RSVD0_8 " -parent $T_PF0_8] + set V_PF0_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_8 -tclproc VAL_PF0_ENTRY_TYPE_8 -parent $T_PF0_8] + set V_PF0_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_8 -tclproc VAL_PF0_ENTRY_BAR_8 -parent $T_PF0_8] + set V_PF0_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_8 -tclproc VAL_PF0_ENTRY_ADDR_8 -parent $T_PF0_8] + set V_PF0_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_8 -parent $T_PF0_8] + set V_PF0_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_8 -parent $T_PF0_8] + set V_PF0_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_8 -parent $T_PF0_8] + set V_PF0_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_8 -tclproc VAL_PF0_ENTRY_RSVD0_8 -parent $T_PF0_8] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_8 + + set PF0_Values_9 [ipgui::add_group $IPINST -name "PF0 - Table Entry 9 Values" -parent $PF0_Values] + set T_PF0_9 [ipgui::add_table $IPINST -name T_PF0_9 -rows 7 -columns 2 -parent $PF0_Values_9] + set L_PF0_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_9 -text "C_PF0_ENTRY_TYPE_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_9 -text "C_PF0_ENTRY_BAR_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_9 -text "C_PF0_ENTRY_ADDR_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_9 -text "C_PF0_ENTRY_VERSION_TYPE_9 " -parent $T_PF0_9] + set L_PF0_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_9 -text "C_PF0_ENTRY_MAJOR_VERSION_9" -parent $T_PF0_9] + set L_PF0_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_9 -text "C_PF0_ENTRY_MINOR_VERSION_9" -parent $T_PF0_9] + set L_PF0_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_9 -text "C_PF0_ENTRY_RSVD0_9 " -parent $T_PF0_9] + set V_PF0_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_9 -tclproc VAL_PF0_ENTRY_TYPE_9 -parent $T_PF0_9] + set V_PF0_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_9 -tclproc VAL_PF0_ENTRY_BAR_9 -parent $T_PF0_9] + set V_PF0_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_9 -tclproc VAL_PF0_ENTRY_ADDR_9 -parent $T_PF0_9] + set V_PF0_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_9 -parent $T_PF0_9] + set V_PF0_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_9 -parent $T_PF0_9] + set V_PF0_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_9 -parent $T_PF0_9] + set V_PF0_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_9 -tclproc VAL_PF0_ENTRY_RSVD0_9 -parent $T_PF0_9] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_9 + + set PF0_Values_10 [ipgui::add_group $IPINST -name "PF0 - Table Entry 10 Values" -parent $PF0_Values] + set T_PF0_10 [ipgui::add_table $IPINST -name T_PF0_10 -rows 7 -columns 2 -parent $PF0_Values_10] + set L_PF0_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_10 -text "C_PF0_ENTRY_TYPE_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_10 -text "C_PF0_ENTRY_BAR_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_10 -text "C_PF0_ENTRY_ADDR_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_10 -text "C_PF0_ENTRY_VERSION_TYPE_10 " -parent $T_PF0_10] + set L_PF0_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_10 -text "C_PF0_ENTRY_MAJOR_VERSION_10" -parent $T_PF0_10] + set L_PF0_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_10 -text "C_PF0_ENTRY_MINOR_VERSION_10" -parent $T_PF0_10] + set L_PF0_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_10 -text "C_PF0_ENTRY_RSVD0_10 " -parent $T_PF0_10] + set V_PF0_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_10 -tclproc VAL_PF0_ENTRY_TYPE_10 -parent $T_PF0_10] + set V_PF0_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_10 -tclproc VAL_PF0_ENTRY_BAR_10 -parent $T_PF0_10] + set V_PF0_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_10 -tclproc VAL_PF0_ENTRY_ADDR_10 -parent $T_PF0_10] + set V_PF0_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_10 -parent $T_PF0_10] + set V_PF0_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_10 -parent $T_PF0_10] + set V_PF0_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_10 -parent $T_PF0_10] + set V_PF0_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_10 -tclproc VAL_PF0_ENTRY_RSVD0_10 -parent $T_PF0_10] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_10 + + set PF0_Values_11 [ipgui::add_group $IPINST -name "PF0 - Table Entry 11 Values" -parent $PF0_Values] + set T_PF0_11 [ipgui::add_table $IPINST -name T_PF0_11 -rows 7 -columns 2 -parent $PF0_Values_11] + set L_PF0_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_11 -text "C_PF0_ENTRY_TYPE_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_11 -text "C_PF0_ENTRY_BAR_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_11 -text "C_PF0_ENTRY_ADDR_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_11 -text "C_PF0_ENTRY_VERSION_TYPE_11 " -parent $T_PF0_11] + set L_PF0_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_11 -text "C_PF0_ENTRY_MAJOR_VERSION_11" -parent $T_PF0_11] + set L_PF0_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_11 -text "C_PF0_ENTRY_MINOR_VERSION_11" -parent $T_PF0_11] + set L_PF0_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_11 -text "C_PF0_ENTRY_RSVD0_11 " -parent $T_PF0_11] + set V_PF0_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_11 -tclproc VAL_PF0_ENTRY_TYPE_11 -parent $T_PF0_11] + set V_PF0_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_11 -tclproc VAL_PF0_ENTRY_BAR_11 -parent $T_PF0_11] + set V_PF0_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_11 -tclproc VAL_PF0_ENTRY_ADDR_11 -parent $T_PF0_11] + set V_PF0_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_11 -parent $T_PF0_11] + set V_PF0_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_11 -parent $T_PF0_11] + set V_PF0_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_11 -parent $T_PF0_11] + set V_PF0_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_11 -tclproc VAL_PF0_ENTRY_RSVD0_11 -parent $T_PF0_11] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_11 + + set PF0_Values_12 [ipgui::add_group $IPINST -name "PF0 - Table Entry 12 Values" -parent $PF0_Values] + set T_PF0_12 [ipgui::add_table $IPINST -name T_PF0_12 -rows 7 -columns 2 -parent $PF0_Values_12] + set L_PF0_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_12 -text "C_PF0_ENTRY_TYPE_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_12 -text "C_PF0_ENTRY_BAR_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_12 -text "C_PF0_ENTRY_ADDR_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_12 -text "C_PF0_ENTRY_VERSION_TYPE_12 " -parent $T_PF0_12] + set L_PF0_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_12 -text "C_PF0_ENTRY_MAJOR_VERSION_12" -parent $T_PF0_12] + set L_PF0_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_12 -text "C_PF0_ENTRY_MINOR_VERSION_12" -parent $T_PF0_12] + set L_PF0_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_12 -text "C_PF0_ENTRY_RSVD0_12 " -parent $T_PF0_12] + set V_PF0_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_12 -tclproc VAL_PF0_ENTRY_TYPE_12 -parent $T_PF0_12] + set V_PF0_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_12 -tclproc VAL_PF0_ENTRY_BAR_12 -parent $T_PF0_12] + set V_PF0_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_12 -tclproc VAL_PF0_ENTRY_ADDR_12 -parent $T_PF0_12] + set V_PF0_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_12 -parent $T_PF0_12] + set V_PF0_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_12 -parent $T_PF0_12] + set V_PF0_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_12 -parent $T_PF0_12] + set V_PF0_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_12 -tclproc VAL_PF0_ENTRY_RSVD0_12 -parent $T_PF0_12] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_12 + + set PF0_Values_13 [ipgui::add_group $IPINST -name "PF0 - Table Entry 13 Values" -parent $PF0_Values] + set T_PF0_13 [ipgui::add_table $IPINST -name T_PF0_13 -rows 7 -columns 2 -parent $PF0_Values_13] + set L_PF0_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_TYPE_13 -text "C_PF0_ENTRY_TYPE_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_BAR_13 -text "C_PF0_ENTRY_BAR_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_ADDR_13 -text "C_PF0_ENTRY_ADDR_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_VERSION_TYPE_13 -text "C_PF0_ENTRY_VERSION_TYPE_13 " -parent $T_PF0_13] + set L_PF0_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MAJOR_VERSION_13 -text "C_PF0_ENTRY_MAJOR_VERSION_13" -parent $T_PF0_13] + set L_PF0_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_MINOR_VERSION_13 -text "C_PF0_ENTRY_MINOR_VERSION_13" -parent $T_PF0_13] + set L_PF0_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF0_ENTRY_RSVD0_13 -text "C_PF0_ENTRY_RSVD0_13 " -parent $T_PF0_13] + set V_PF0_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_TYPE_13 -tclproc VAL_PF0_ENTRY_TYPE_13 -parent $T_PF0_13] + set V_PF0_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_BAR_13 -tclproc VAL_PF0_ENTRY_BAR_13 -parent $T_PF0_13] + set V_PF0_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_ADDR_13 -tclproc VAL_PF0_ENTRY_ADDR_13 -parent $T_PF0_13] + set V_PF0_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF0_ENTRY_VERSION_TYPE_13 -parent $T_PF0_13] + set V_PF0_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF0_ENTRY_MAJOR_VERSION_13 -parent $T_PF0_13] + set V_PF0_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF0_ENTRY_MINOR_VERSION_13 -parent $T_PF0_13] + set V_PF0_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF0_ENTRY_RSVD0_13 -tclproc VAL_PF0_ENTRY_RSVD0_13 -parent $T_PF0_13] + set_property cell_location 0,0 $L_PF0_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF0_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF0_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF0_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF0_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF0_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF0_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF0_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF0_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF0_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF0_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF0_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF0_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF0_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF0_ENTRY_RSVD0_13 + + set PF1_Values [ipgui::add_page $IPINST -name "PF1 Values"] + set PF1_Values_General [ipgui::add_group $IPINST -name "PF1 - General Values" -parent $PF1_Values] + set T_PF1_GENERAL [ipgui::add_table $IPINST -name T_PF1_GENERAL -rows 4 -columns 2 -parent $PF1_Values_General] + set L_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF1_GENERAL] + set L_PF1_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF1_BAR_INDEX -text "C_PF1_BAR_INDEX " -parent $T_PF1_GENERAL] + set L_PF1_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF1_LOW_OFFSET -text "C_PF1_LOW_OFFSET " -parent $T_PF1_GENERAL] + set L_PF1_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF1_HIGH_OFFSET -text "C_PF1_HIGH_OFFSET " -parent $T_PF1_GENERAL] + set V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF1_GENERAL] + set V_PF1_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF1_BAR_INDEX -tclproc VAL_PF1_BAR_INDEX -parent $T_PF1_GENERAL] + set V_PF1_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF1_LOW_OFFSET -tclproc VAL_PF1_LOW_OFFSET -parent $T_PF1_GENERAL] + set V_PF1_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF1_HIGH_OFFSET -tclproc VAL_PF1_HIGH_OFFSET -parent $T_PF1_GENERAL] + set_property cell_location 0,0 $L_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF1_BAR_INDEX + set_property cell_location 2,0 $L_PF1_LOW_OFFSET + set_property cell_location 3,0 $L_PF1_HIGH_OFFSET + set_property cell_location 0,1 $V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF1_BAR_INDEX + set_property cell_location 2,1 $V_PF1_LOW_OFFSET + set_property cell_location 3,1 $V_PF1_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF1_BAR_INDEX + set_property obj_color "192,192,192" $V_PF1_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF1_HIGH_OFFSET + + set PF1_Values_0 [ipgui::add_group $IPINST -name "PF1 - Table Entry 0 Values" -parent $PF1_Values] + set T_PF1_0 [ipgui::add_table $IPINST -name T_PF1_0 -rows 7 -columns 2 -parent $PF1_Values_0] + set L_PF1_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_0 -text "C_PF1_ENTRY_TYPE_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_0 -text "C_PF1_ENTRY_BAR_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_0 -text "C_PF1_ENTRY_ADDR_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_0 -text "C_PF1_ENTRY_VERSION_TYPE_0 " -parent $T_PF1_0] + set L_PF1_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_0 -text "C_PF1_ENTRY_MAJOR_VERSION_0" -parent $T_PF1_0] + set L_PF1_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_0 -text "C_PF1_ENTRY_MINOR_VERSION_0" -parent $T_PF1_0] + set L_PF1_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_0 -text "C_PF1_ENTRY_RSVD0_0 " -parent $T_PF1_0] + set V_PF1_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_0 -tclproc VAL_PF1_ENTRY_TYPE_0 -parent $T_PF1_0] + set V_PF1_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_0 -tclproc VAL_PF1_ENTRY_BAR_0 -parent $T_PF1_0] + set V_PF1_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_0 -tclproc VAL_PF1_ENTRY_ADDR_0 -parent $T_PF1_0] + set V_PF1_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_0 -parent $T_PF1_0] + set V_PF1_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_0 -parent $T_PF1_0] + set V_PF1_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_0 -parent $T_PF1_0] + set V_PF1_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_0 -tclproc VAL_PF1_ENTRY_RSVD0_0 -parent $T_PF1_0] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_0 + + set PF1_Values_1 [ipgui::add_group $IPINST -name "PF1 - Table Entry 1 Values" -parent $PF1_Values] + set T_PF1_1 [ipgui::add_table $IPINST -name T_PF1_1 -rows 7 -columns 2 -parent $PF1_Values_1] + set L_PF1_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_1 -text "C_PF1_ENTRY_TYPE_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_1 -text "C_PF1_ENTRY_BAR_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_1 -text "C_PF1_ENTRY_ADDR_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_1 -text "C_PF1_ENTRY_VERSION_TYPE_1 " -parent $T_PF1_1] + set L_PF1_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_1 -text "C_PF1_ENTRY_MAJOR_VERSION_1" -parent $T_PF1_1] + set L_PF1_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_1 -text "C_PF1_ENTRY_MINOR_VERSION_1" -parent $T_PF1_1] + set L_PF1_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_1 -text "C_PF1_ENTRY_RSVD0_1 " -parent $T_PF1_1] + set V_PF1_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_1 -tclproc VAL_PF1_ENTRY_TYPE_1 -parent $T_PF1_1] + set V_PF1_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_1 -tclproc VAL_PF1_ENTRY_BAR_1 -parent $T_PF1_1] + set V_PF1_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_1 -tclproc VAL_PF1_ENTRY_ADDR_1 -parent $T_PF1_1] + set V_PF1_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_1 -parent $T_PF1_1] + set V_PF1_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_1 -parent $T_PF1_1] + set V_PF1_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_1 -parent $T_PF1_1] + set V_PF1_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_1 -tclproc VAL_PF1_ENTRY_RSVD0_1 -parent $T_PF1_1] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_1 + + set PF1_Values_2 [ipgui::add_group $IPINST -name "PF1 - Table Entry 2 Values" -parent $PF1_Values] + set T_PF1_2 [ipgui::add_table $IPINST -name T_PF1_2 -rows 7 -columns 2 -parent $PF1_Values_2] + set L_PF1_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_2 -text "C_PF1_ENTRY_TYPE_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_2 -text "C_PF1_ENTRY_BAR_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_2 -text "C_PF1_ENTRY_ADDR_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_2 -text "C_PF1_ENTRY_VERSION_TYPE_2 " -parent $T_PF1_2] + set L_PF1_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_2 -text "C_PF1_ENTRY_MAJOR_VERSION_2" -parent $T_PF1_2] + set L_PF1_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_2 -text "C_PF1_ENTRY_MINOR_VERSION_2" -parent $T_PF1_2] + set L_PF1_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_2 -text "C_PF1_ENTRY_RSVD0_2 " -parent $T_PF1_2] + set V_PF1_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_2 -tclproc VAL_PF1_ENTRY_TYPE_2 -parent $T_PF1_2] + set V_PF1_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_2 -tclproc VAL_PF1_ENTRY_BAR_2 -parent $T_PF1_2] + set V_PF1_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_2 -tclproc VAL_PF1_ENTRY_ADDR_2 -parent $T_PF1_2] + set V_PF1_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_2 -parent $T_PF1_2] + set V_PF1_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_2 -parent $T_PF1_2] + set V_PF1_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_2 -parent $T_PF1_2] + set V_PF1_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_2 -tclproc VAL_PF1_ENTRY_RSVD0_2 -parent $T_PF1_2] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_2 + + set PF1_Values_3 [ipgui::add_group $IPINST -name "PF1 - Table Entry 3 Values" -parent $PF1_Values] + set T_PF1_3 [ipgui::add_table $IPINST -name T_PF1_3 -rows 7 -columns 2 -parent $PF1_Values_3] + set L_PF1_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_3 -text "C_PF1_ENTRY_TYPE_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_3 -text "C_PF1_ENTRY_BAR_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_3 -text "C_PF1_ENTRY_ADDR_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_3 -text "C_PF1_ENTRY_VERSION_TYPE_3 " -parent $T_PF1_3] + set L_PF1_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_3 -text "C_PF1_ENTRY_MAJOR_VERSION_3" -parent $T_PF1_3] + set L_PF1_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_3 -text "C_PF1_ENTRY_MINOR_VERSION_3" -parent $T_PF1_3] + set L_PF1_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_3 -text "C_PF1_ENTRY_RSVD0_3 " -parent $T_PF1_3] + set V_PF1_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_3 -tclproc VAL_PF1_ENTRY_TYPE_3 -parent $T_PF1_3] + set V_PF1_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_3 -tclproc VAL_PF1_ENTRY_BAR_3 -parent $T_PF1_3] + set V_PF1_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_3 -tclproc VAL_PF1_ENTRY_ADDR_3 -parent $T_PF1_3] + set V_PF1_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_3 -parent $T_PF1_3] + set V_PF1_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_3 -parent $T_PF1_3] + set V_PF1_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_3 -parent $T_PF1_3] + set V_PF1_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_3 -tclproc VAL_PF1_ENTRY_RSVD0_3 -parent $T_PF1_3] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_3 + + set PF1_Values_4 [ipgui::add_group $IPINST -name "PF1 - Table Entry 4 Values" -parent $PF1_Values] + set T_PF1_4 [ipgui::add_table $IPINST -name T_PF1_4 -rows 7 -columns 2 -parent $PF1_Values_4] + set L_PF1_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_4 -text "C_PF1_ENTRY_TYPE_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_4 -text "C_PF1_ENTRY_BAR_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_4 -text "C_PF1_ENTRY_ADDR_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_4 -text "C_PF1_ENTRY_VERSION_TYPE_4 " -parent $T_PF1_4] + set L_PF1_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_4 -text "C_PF1_ENTRY_MAJOR_VERSION_4" -parent $T_PF1_4] + set L_PF1_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_4 -text "C_PF1_ENTRY_MINOR_VERSION_4" -parent $T_PF1_4] + set L_PF1_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_4 -text "C_PF1_ENTRY_RSVD0_4 " -parent $T_PF1_4] + set V_PF1_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_4 -tclproc VAL_PF1_ENTRY_TYPE_4 -parent $T_PF1_4] + set V_PF1_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_4 -tclproc VAL_PF1_ENTRY_BAR_4 -parent $T_PF1_4] + set V_PF1_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_4 -tclproc VAL_PF1_ENTRY_ADDR_4 -parent $T_PF1_4] + set V_PF1_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_4 -parent $T_PF1_4] + set V_PF1_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_4 -parent $T_PF1_4] + set V_PF1_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_4 -parent $T_PF1_4] + set V_PF1_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_4 -tclproc VAL_PF1_ENTRY_RSVD0_4 -parent $T_PF1_4] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_4 + + set PF1_Values_5 [ipgui::add_group $IPINST -name "PF1 - Table Entry 5 Values" -parent $PF1_Values] + set T_PF1_5 [ipgui::add_table $IPINST -name T_PF1_5 -rows 7 -columns 2 -parent $PF1_Values_5] + set L_PF1_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_5 -text "C_PF1_ENTRY_TYPE_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_5 -text "C_PF1_ENTRY_BAR_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_5 -text "C_PF1_ENTRY_ADDR_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_5 -text "C_PF1_ENTRY_VERSION_TYPE_5 " -parent $T_PF1_5] + set L_PF1_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_5 -text "C_PF1_ENTRY_MAJOR_VERSION_5" -parent $T_PF1_5] + set L_PF1_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_5 -text "C_PF1_ENTRY_MINOR_VERSION_5" -parent $T_PF1_5] + set L_PF1_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_5 -text "C_PF1_ENTRY_RSVD0_5 " -parent $T_PF1_5] + set V_PF1_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_5 -tclproc VAL_PF1_ENTRY_TYPE_5 -parent $T_PF1_5] + set V_PF1_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_5 -tclproc VAL_PF1_ENTRY_BAR_5 -parent $T_PF1_5] + set V_PF1_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_5 -tclproc VAL_PF1_ENTRY_ADDR_5 -parent $T_PF1_5] + set V_PF1_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_5 -parent $T_PF1_5] + set V_PF1_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_5 -parent $T_PF1_5] + set V_PF1_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_5 -parent $T_PF1_5] + set V_PF1_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_5 -tclproc VAL_PF1_ENTRY_RSVD0_5 -parent $T_PF1_5] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_5 + + set PF1_Values_6 [ipgui::add_group $IPINST -name "PF1 - Table Entry 6 Values" -parent $PF1_Values] + set T_PF1_6 [ipgui::add_table $IPINST -name T_PF1_6 -rows 7 -columns 2 -parent $PF1_Values_6] + set L_PF1_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_6 -text "C_PF1_ENTRY_TYPE_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_6 -text "C_PF1_ENTRY_BAR_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_6 -text "C_PF1_ENTRY_ADDR_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_6 -text "C_PF1_ENTRY_VERSION_TYPE_6 " -parent $T_PF1_6] + set L_PF1_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_6 -text "C_PF1_ENTRY_MAJOR_VERSION_6" -parent $T_PF1_6] + set L_PF1_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_6 -text "C_PF1_ENTRY_MINOR_VERSION_6" -parent $T_PF1_6] + set L_PF1_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_6 -text "C_PF1_ENTRY_RSVD0_6 " -parent $T_PF1_6] + set V_PF1_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_6 -tclproc VAL_PF1_ENTRY_TYPE_6 -parent $T_PF1_6] + set V_PF1_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_6 -tclproc VAL_PF1_ENTRY_BAR_6 -parent $T_PF1_6] + set V_PF1_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_6 -tclproc VAL_PF1_ENTRY_ADDR_6 -parent $T_PF1_6] + set V_PF1_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_6 -parent $T_PF1_6] + set V_PF1_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_6 -parent $T_PF1_6] + set V_PF1_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_6 -parent $T_PF1_6] + set V_PF1_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_6 -tclproc VAL_PF1_ENTRY_RSVD0_6 -parent $T_PF1_6] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_6 + + set PF1_Values_7 [ipgui::add_group $IPINST -name "PF1 - Table Entry 7 Values" -parent $PF1_Values] + set T_PF1_7 [ipgui::add_table $IPINST -name T_PF1_7 -rows 7 -columns 2 -parent $PF1_Values_7] + set L_PF1_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_7 -text "C_PF1_ENTRY_TYPE_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_7 -text "C_PF1_ENTRY_BAR_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_7 -text "C_PF1_ENTRY_ADDR_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_7 -text "C_PF1_ENTRY_VERSION_TYPE_7 " -parent $T_PF1_7] + set L_PF1_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_7 -text "C_PF1_ENTRY_MAJOR_VERSION_7" -parent $T_PF1_7] + set L_PF1_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_7 -text "C_PF1_ENTRY_MINOR_VERSION_7" -parent $T_PF1_7] + set L_PF1_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_7 -text "C_PF1_ENTRY_RSVD0_7 " -parent $T_PF1_7] + set V_PF1_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_7 -tclproc VAL_PF1_ENTRY_TYPE_7 -parent $T_PF1_7] + set V_PF1_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_7 -tclproc VAL_PF1_ENTRY_BAR_7 -parent $T_PF1_7] + set V_PF1_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_7 -tclproc VAL_PF1_ENTRY_ADDR_7 -parent $T_PF1_7] + set V_PF1_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_7 -parent $T_PF1_7] + set V_PF1_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_7 -parent $T_PF1_7] + set V_PF1_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_7 -parent $T_PF1_7] + set V_PF1_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_7 -tclproc VAL_PF1_ENTRY_RSVD0_7 -parent $T_PF1_7] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_7 + + set PF1_Values_8 [ipgui::add_group $IPINST -name "PF1 - Table Entry 8 Values" -parent $PF1_Values] + set T_PF1_8 [ipgui::add_table $IPINST -name T_PF1_8 -rows 7 -columns 2 -parent $PF1_Values_8] + set L_PF1_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_8 -text "C_PF1_ENTRY_TYPE_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_8 -text "C_PF1_ENTRY_BAR_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_8 -text "C_PF1_ENTRY_ADDR_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_8 -text "C_PF1_ENTRY_VERSION_TYPE_8 " -parent $T_PF1_8] + set L_PF1_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_8 -text "C_PF1_ENTRY_MAJOR_VERSION_8" -parent $T_PF1_8] + set L_PF1_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_8 -text "C_PF1_ENTRY_MINOR_VERSION_8" -parent $T_PF1_8] + set L_PF1_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_8 -text "C_PF1_ENTRY_RSVD0_8 " -parent $T_PF1_8] + set V_PF1_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_8 -tclproc VAL_PF1_ENTRY_TYPE_8 -parent $T_PF1_8] + set V_PF1_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_8 -tclproc VAL_PF1_ENTRY_BAR_8 -parent $T_PF1_8] + set V_PF1_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_8 -tclproc VAL_PF1_ENTRY_ADDR_8 -parent $T_PF1_8] + set V_PF1_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_8 -parent $T_PF1_8] + set V_PF1_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_8 -parent $T_PF1_8] + set V_PF1_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_8 -parent $T_PF1_8] + set V_PF1_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_8 -tclproc VAL_PF1_ENTRY_RSVD0_8 -parent $T_PF1_8] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_8 + + set PF1_Values_9 [ipgui::add_group $IPINST -name "PF1 - Table Entry 9 Values" -parent $PF1_Values] + set T_PF1_9 [ipgui::add_table $IPINST -name T_PF1_9 -rows 7 -columns 2 -parent $PF1_Values_9] + set L_PF1_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_9 -text "C_PF1_ENTRY_TYPE_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_9 -text "C_PF1_ENTRY_BAR_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_9 -text "C_PF1_ENTRY_ADDR_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_9 -text "C_PF1_ENTRY_VERSION_TYPE_9 " -parent $T_PF1_9] + set L_PF1_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_9 -text "C_PF1_ENTRY_MAJOR_VERSION_9" -parent $T_PF1_9] + set L_PF1_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_9 -text "C_PF1_ENTRY_MINOR_VERSION_9" -parent $T_PF1_9] + set L_PF1_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_9 -text "C_PF1_ENTRY_RSVD0_9 " -parent $T_PF1_9] + set V_PF1_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_9 -tclproc VAL_PF1_ENTRY_TYPE_9 -parent $T_PF1_9] + set V_PF1_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_9 -tclproc VAL_PF1_ENTRY_BAR_9 -parent $T_PF1_9] + set V_PF1_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_9 -tclproc VAL_PF1_ENTRY_ADDR_9 -parent $T_PF1_9] + set V_PF1_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_9 -parent $T_PF1_9] + set V_PF1_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_9 -parent $T_PF1_9] + set V_PF1_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_9 -parent $T_PF1_9] + set V_PF1_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_9 -tclproc VAL_PF1_ENTRY_RSVD0_9 -parent $T_PF1_9] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_9 + + set PF1_Values_10 [ipgui::add_group $IPINST -name "PF1 - Table Entry 10 Values" -parent $PF1_Values] + set T_PF1_10 [ipgui::add_table $IPINST -name T_PF1_10 -rows 7 -columns 2 -parent $PF1_Values_10] + set L_PF1_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_10 -text "C_PF1_ENTRY_TYPE_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_10 -text "C_PF1_ENTRY_BAR_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_10 -text "C_PF1_ENTRY_ADDR_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_10 -text "C_PF1_ENTRY_VERSION_TYPE_10 " -parent $T_PF1_10] + set L_PF1_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_10 -text "C_PF1_ENTRY_MAJOR_VERSION_10" -parent $T_PF1_10] + set L_PF1_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_10 -text "C_PF1_ENTRY_MINOR_VERSION_10" -parent $T_PF1_10] + set L_PF1_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_10 -text "C_PF1_ENTRY_RSVD0_10 " -parent $T_PF1_10] + set V_PF1_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_10 -tclproc VAL_PF1_ENTRY_TYPE_10 -parent $T_PF1_10] + set V_PF1_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_10 -tclproc VAL_PF1_ENTRY_BAR_10 -parent $T_PF1_10] + set V_PF1_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_10 -tclproc VAL_PF1_ENTRY_ADDR_10 -parent $T_PF1_10] + set V_PF1_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_10 -parent $T_PF1_10] + set V_PF1_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_10 -parent $T_PF1_10] + set V_PF1_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_10 -parent $T_PF1_10] + set V_PF1_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_10 -tclproc VAL_PF1_ENTRY_RSVD0_10 -parent $T_PF1_10] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_10 + + set PF1_Values_11 [ipgui::add_group $IPINST -name "PF1 - Table Entry 11 Values" -parent $PF1_Values] + set T_PF1_11 [ipgui::add_table $IPINST -name T_PF1_11 -rows 7 -columns 2 -parent $PF1_Values_11] + set L_PF1_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_11 -text "C_PF1_ENTRY_TYPE_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_11 -text "C_PF1_ENTRY_BAR_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_11 -text "C_PF1_ENTRY_ADDR_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_11 -text "C_PF1_ENTRY_VERSION_TYPE_11 " -parent $T_PF1_11] + set L_PF1_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_11 -text "C_PF1_ENTRY_MAJOR_VERSION_11" -parent $T_PF1_11] + set L_PF1_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_11 -text "C_PF1_ENTRY_MINOR_VERSION_11" -parent $T_PF1_11] + set L_PF1_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_11 -text "C_PF1_ENTRY_RSVD0_11 " -parent $T_PF1_11] + set V_PF1_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_11 -tclproc VAL_PF1_ENTRY_TYPE_11 -parent $T_PF1_11] + set V_PF1_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_11 -tclproc VAL_PF1_ENTRY_BAR_11 -parent $T_PF1_11] + set V_PF1_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_11 -tclproc VAL_PF1_ENTRY_ADDR_11 -parent $T_PF1_11] + set V_PF1_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_11 -parent $T_PF1_11] + set V_PF1_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_11 -parent $T_PF1_11] + set V_PF1_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_11 -parent $T_PF1_11] + set V_PF1_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_11 -tclproc VAL_PF1_ENTRY_RSVD0_11 -parent $T_PF1_11] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_11 + + set PF1_Values_12 [ipgui::add_group $IPINST -name "PF1 - Table Entry 12 Values" -parent $PF1_Values] + set T_PF1_12 [ipgui::add_table $IPINST -name T_PF1_12 -rows 7 -columns 2 -parent $PF1_Values_12] + set L_PF1_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_12 -text "C_PF1_ENTRY_TYPE_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_12 -text "C_PF1_ENTRY_BAR_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_12 -text "C_PF1_ENTRY_ADDR_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_12 -text "C_PF1_ENTRY_VERSION_TYPE_12 " -parent $T_PF1_12] + set L_PF1_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_12 -text "C_PF1_ENTRY_MAJOR_VERSION_12" -parent $T_PF1_12] + set L_PF1_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_12 -text "C_PF1_ENTRY_MINOR_VERSION_12" -parent $T_PF1_12] + set L_PF1_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_12 -text "C_PF1_ENTRY_RSVD0_12 " -parent $T_PF1_12] + set V_PF1_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_12 -tclproc VAL_PF1_ENTRY_TYPE_12 -parent $T_PF1_12] + set V_PF1_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_12 -tclproc VAL_PF1_ENTRY_BAR_12 -parent $T_PF1_12] + set V_PF1_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_12 -tclproc VAL_PF1_ENTRY_ADDR_12 -parent $T_PF1_12] + set V_PF1_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_12 -parent $T_PF1_12] + set V_PF1_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_12 -parent $T_PF1_12] + set V_PF1_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_12 -parent $T_PF1_12] + set V_PF1_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_12 -tclproc VAL_PF1_ENTRY_RSVD0_12 -parent $T_PF1_12] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_12 + + set PF1_Values_13 [ipgui::add_group $IPINST -name "PF1 - Table Entry 13 Values" -parent $PF1_Values] + set T_PF1_13 [ipgui::add_table $IPINST -name T_PF1_13 -rows 7 -columns 2 -parent $PF1_Values_13] + set L_PF1_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_TYPE_13 -text "C_PF1_ENTRY_TYPE_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_BAR_13 -text "C_PF1_ENTRY_BAR_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_ADDR_13 -text "C_PF1_ENTRY_ADDR_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_VERSION_TYPE_13 -text "C_PF1_ENTRY_VERSION_TYPE_13 " -parent $T_PF1_13] + set L_PF1_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MAJOR_VERSION_13 -text "C_PF1_ENTRY_MAJOR_VERSION_13" -parent $T_PF1_13] + set L_PF1_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_MINOR_VERSION_13 -text "C_PF1_ENTRY_MINOR_VERSION_13" -parent $T_PF1_13] + set L_PF1_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF1_ENTRY_RSVD0_13 -text "C_PF1_ENTRY_RSVD0_13 " -parent $T_PF1_13] + set V_PF1_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_TYPE_13 -tclproc VAL_PF1_ENTRY_TYPE_13 -parent $T_PF1_13] + set V_PF1_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_BAR_13 -tclproc VAL_PF1_ENTRY_BAR_13 -parent $T_PF1_13] + set V_PF1_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_ADDR_13 -tclproc VAL_PF1_ENTRY_ADDR_13 -parent $T_PF1_13] + set V_PF1_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF1_ENTRY_VERSION_TYPE_13 -parent $T_PF1_13] + set V_PF1_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF1_ENTRY_MAJOR_VERSION_13 -parent $T_PF1_13] + set V_PF1_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF1_ENTRY_MINOR_VERSION_13 -parent $T_PF1_13] + set V_PF1_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF1_ENTRY_RSVD0_13 -tclproc VAL_PF1_ENTRY_RSVD0_13 -parent $T_PF1_13] + set_property cell_location 0,0 $L_PF1_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF1_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF1_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF1_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF1_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF1_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF1_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF1_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF1_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF1_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF1_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF1_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF1_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF1_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF1_ENTRY_RSVD0_13 + + set PF2_Values [ipgui::add_page $IPINST -name "PF2 Values"] + set PF2_Values_General [ipgui::add_group $IPINST -name "PF2 - General Values" -parent $PF2_Values] + set T_PF2_GENERAL [ipgui::add_table $IPINST -name T_PF2_GENERAL -rows 4 -columns 2 -parent $PF2_Values_General] + set L_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF2_GENERAL] + set L_PF2_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF2_BAR_INDEX -text "C_PF2_BAR_INDEX " -parent $T_PF2_GENERAL] + set L_PF2_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF2_LOW_OFFSET -text "C_PF2_LOW_OFFSET " -parent $T_PF2_GENERAL] + set L_PF2_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF2_HIGH_OFFSET -text "C_PF2_HIGH_OFFSET " -parent $T_PF2_GENERAL] + set V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF2_GENERAL] + set V_PF2_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF2_BAR_INDEX -tclproc VAL_PF2_BAR_INDEX -parent $T_PF2_GENERAL] + set V_PF2_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF2_LOW_OFFSET -tclproc VAL_PF2_LOW_OFFSET -parent $T_PF2_GENERAL] + set V_PF2_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF2_HIGH_OFFSET -tclproc VAL_PF2_HIGH_OFFSET -parent $T_PF2_GENERAL] + set_property cell_location 0,0 $L_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF2_BAR_INDEX + set_property cell_location 2,0 $L_PF2_LOW_OFFSET + set_property cell_location 3,0 $L_PF2_HIGH_OFFSET + set_property cell_location 0,1 $V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF2_BAR_INDEX + set_property cell_location 2,1 $V_PF2_LOW_OFFSET + set_property cell_location 3,1 $V_PF2_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF2_BAR_INDEX + set_property obj_color "192,192,192" $V_PF2_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF2_HIGH_OFFSET + + set PF2_Values_0 [ipgui::add_group $IPINST -name "PF2 - Table Entry 0 Values" -parent $PF2_Values] + set T_PF2_0 [ipgui::add_table $IPINST -name T_PF2_0 -rows 7 -columns 2 -parent $PF2_Values_0] + set L_PF2_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_0 -text "C_PF2_ENTRY_TYPE_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_0 -text "C_PF2_ENTRY_BAR_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_0 -text "C_PF2_ENTRY_ADDR_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_0 -text "C_PF2_ENTRY_VERSION_TYPE_0 " -parent $T_PF2_0] + set L_PF2_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_0 -text "C_PF2_ENTRY_MAJOR_VERSION_0" -parent $T_PF2_0] + set L_PF2_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_0 -text "C_PF2_ENTRY_MINOR_VERSION_0" -parent $T_PF2_0] + set L_PF2_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_0 -text "C_PF2_ENTRY_RSVD0_0 " -parent $T_PF2_0] + set V_PF2_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_0 -tclproc VAL_PF2_ENTRY_TYPE_0 -parent $T_PF2_0] + set V_PF2_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_0 -tclproc VAL_PF2_ENTRY_BAR_0 -parent $T_PF2_0] + set V_PF2_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_0 -tclproc VAL_PF2_ENTRY_ADDR_0 -parent $T_PF2_0] + set V_PF2_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_0 -parent $T_PF2_0] + set V_PF2_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_0 -parent $T_PF2_0] + set V_PF2_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_0 -parent $T_PF2_0] + set V_PF2_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_0 -tclproc VAL_PF2_ENTRY_RSVD0_0 -parent $T_PF2_0] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_0 + + set PF2_Values_1 [ipgui::add_group $IPINST -name "PF2 - Table Entry 1 Values" -parent $PF2_Values] + set T_PF2_1 [ipgui::add_table $IPINST -name T_PF2_1 -rows 7 -columns 2 -parent $PF2_Values_1] + set L_PF2_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_1 -text "C_PF2_ENTRY_TYPE_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_1 -text "C_PF2_ENTRY_BAR_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_1 -text "C_PF2_ENTRY_ADDR_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_1 -text "C_PF2_ENTRY_VERSION_TYPE_1 " -parent $T_PF2_1] + set L_PF2_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_1 -text "C_PF2_ENTRY_MAJOR_VERSION_1" -parent $T_PF2_1] + set L_PF2_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_1 -text "C_PF2_ENTRY_MINOR_VERSION_1" -parent $T_PF2_1] + set L_PF2_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_1 -text "C_PF2_ENTRY_RSVD0_1 " -parent $T_PF2_1] + set V_PF2_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_1 -tclproc VAL_PF2_ENTRY_TYPE_1 -parent $T_PF2_1] + set V_PF2_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_1 -tclproc VAL_PF2_ENTRY_BAR_1 -parent $T_PF2_1] + set V_PF2_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_1 -tclproc VAL_PF2_ENTRY_ADDR_1 -parent $T_PF2_1] + set V_PF2_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_1 -parent $T_PF2_1] + set V_PF2_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_1 -parent $T_PF2_1] + set V_PF2_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_1 -parent $T_PF2_1] + set V_PF2_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_1 -tclproc VAL_PF2_ENTRY_RSVD0_1 -parent $T_PF2_1] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_1 + + set PF2_Values_2 [ipgui::add_group $IPINST -name "PF2 - Table Entry 2 Values" -parent $PF2_Values] + set T_PF2_2 [ipgui::add_table $IPINST -name T_PF2_2 -rows 7 -columns 2 -parent $PF2_Values_2] + set L_PF2_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_2 -text "C_PF2_ENTRY_TYPE_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_2 -text "C_PF2_ENTRY_BAR_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_2 -text "C_PF2_ENTRY_ADDR_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_2 -text "C_PF2_ENTRY_VERSION_TYPE_2 " -parent $T_PF2_2] + set L_PF2_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_2 -text "C_PF2_ENTRY_MAJOR_VERSION_2" -parent $T_PF2_2] + set L_PF2_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_2 -text "C_PF2_ENTRY_MINOR_VERSION_2" -parent $T_PF2_2] + set L_PF2_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_2 -text "C_PF2_ENTRY_RSVD0_2 " -parent $T_PF2_2] + set V_PF2_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_2 -tclproc VAL_PF2_ENTRY_TYPE_2 -parent $T_PF2_2] + set V_PF2_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_2 -tclproc VAL_PF2_ENTRY_BAR_2 -parent $T_PF2_2] + set V_PF2_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_2 -tclproc VAL_PF2_ENTRY_ADDR_2 -parent $T_PF2_2] + set V_PF2_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_2 -parent $T_PF2_2] + set V_PF2_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_2 -parent $T_PF2_2] + set V_PF2_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_2 -parent $T_PF2_2] + set V_PF2_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_2 -tclproc VAL_PF2_ENTRY_RSVD0_2 -parent $T_PF2_2] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_2 + + set PF2_Values_3 [ipgui::add_group $IPINST -name "PF2 - Table Entry 3 Values" -parent $PF2_Values] + set T_PF2_3 [ipgui::add_table $IPINST -name T_PF2_3 -rows 7 -columns 2 -parent $PF2_Values_3] + set L_PF2_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_3 -text "C_PF2_ENTRY_TYPE_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_3 -text "C_PF2_ENTRY_BAR_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_3 -text "C_PF2_ENTRY_ADDR_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_3 -text "C_PF2_ENTRY_VERSION_TYPE_3 " -parent $T_PF2_3] + set L_PF2_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_3 -text "C_PF2_ENTRY_MAJOR_VERSION_3" -parent $T_PF2_3] + set L_PF2_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_3 -text "C_PF2_ENTRY_MINOR_VERSION_3" -parent $T_PF2_3] + set L_PF2_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_3 -text "C_PF2_ENTRY_RSVD0_3 " -parent $T_PF2_3] + set V_PF2_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_3 -tclproc VAL_PF2_ENTRY_TYPE_3 -parent $T_PF2_3] + set V_PF2_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_3 -tclproc VAL_PF2_ENTRY_BAR_3 -parent $T_PF2_3] + set V_PF2_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_3 -tclproc VAL_PF2_ENTRY_ADDR_3 -parent $T_PF2_3] + set V_PF2_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_3 -parent $T_PF2_3] + set V_PF2_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_3 -parent $T_PF2_3] + set V_PF2_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_3 -parent $T_PF2_3] + set V_PF2_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_3 -tclproc VAL_PF2_ENTRY_RSVD0_3 -parent $T_PF2_3] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_3 + + set PF2_Values_4 [ipgui::add_group $IPINST -name "PF2 - Table Entry 4 Values" -parent $PF2_Values] + set T_PF2_4 [ipgui::add_table $IPINST -name T_PF2_4 -rows 7 -columns 2 -parent $PF2_Values_4] + set L_PF2_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_4 -text "C_PF2_ENTRY_TYPE_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_4 -text "C_PF2_ENTRY_BAR_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_4 -text "C_PF2_ENTRY_ADDR_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_4 -text "C_PF2_ENTRY_VERSION_TYPE_4 " -parent $T_PF2_4] + set L_PF2_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_4 -text "C_PF2_ENTRY_MAJOR_VERSION_4" -parent $T_PF2_4] + set L_PF2_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_4 -text "C_PF2_ENTRY_MINOR_VERSION_4" -parent $T_PF2_4] + set L_PF2_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_4 -text "C_PF2_ENTRY_RSVD0_4 " -parent $T_PF2_4] + set V_PF2_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_4 -tclproc VAL_PF2_ENTRY_TYPE_4 -parent $T_PF2_4] + set V_PF2_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_4 -tclproc VAL_PF2_ENTRY_BAR_4 -parent $T_PF2_4] + set V_PF2_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_4 -tclproc VAL_PF2_ENTRY_ADDR_4 -parent $T_PF2_4] + set V_PF2_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_4 -parent $T_PF2_4] + set V_PF2_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_4 -parent $T_PF2_4] + set V_PF2_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_4 -parent $T_PF2_4] + set V_PF2_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_4 -tclproc VAL_PF2_ENTRY_RSVD0_4 -parent $T_PF2_4] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_4 + + set PF2_Values_5 [ipgui::add_group $IPINST -name "PF2 - Table Entry 5 Values" -parent $PF2_Values] + set T_PF2_5 [ipgui::add_table $IPINST -name T_PF2_5 -rows 7 -columns 2 -parent $PF2_Values_5] + set L_PF2_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_5 -text "C_PF2_ENTRY_TYPE_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_5 -text "C_PF2_ENTRY_BAR_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_5 -text "C_PF2_ENTRY_ADDR_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_5 -text "C_PF2_ENTRY_VERSION_TYPE_5 " -parent $T_PF2_5] + set L_PF2_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_5 -text "C_PF2_ENTRY_MAJOR_VERSION_5" -parent $T_PF2_5] + set L_PF2_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_5 -text "C_PF2_ENTRY_MINOR_VERSION_5" -parent $T_PF2_5] + set L_PF2_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_5 -text "C_PF2_ENTRY_RSVD0_5 " -parent $T_PF2_5] + set V_PF2_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_5 -tclproc VAL_PF2_ENTRY_TYPE_5 -parent $T_PF2_5] + set V_PF2_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_5 -tclproc VAL_PF2_ENTRY_BAR_5 -parent $T_PF2_5] + set V_PF2_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_5 -tclproc VAL_PF2_ENTRY_ADDR_5 -parent $T_PF2_5] + set V_PF2_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_5 -parent $T_PF2_5] + set V_PF2_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_5 -parent $T_PF2_5] + set V_PF2_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_5 -parent $T_PF2_5] + set V_PF2_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_5 -tclproc VAL_PF2_ENTRY_RSVD0_5 -parent $T_PF2_5] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_5 + + set PF2_Values_6 [ipgui::add_group $IPINST -name "PF2 - Table Entry 6 Values" -parent $PF2_Values] + set T_PF2_6 [ipgui::add_table $IPINST -name T_PF2_6 -rows 7 -columns 2 -parent $PF2_Values_6] + set L_PF2_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_6 -text "C_PF2_ENTRY_TYPE_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_6 -text "C_PF2_ENTRY_BAR_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_6 -text "C_PF2_ENTRY_ADDR_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_6 -text "C_PF2_ENTRY_VERSION_TYPE_6 " -parent $T_PF2_6] + set L_PF2_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_6 -text "C_PF2_ENTRY_MAJOR_VERSION_6" -parent $T_PF2_6] + set L_PF2_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_6 -text "C_PF2_ENTRY_MINOR_VERSION_6" -parent $T_PF2_6] + set L_PF2_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_6 -text "C_PF2_ENTRY_RSVD0_6 " -parent $T_PF2_6] + set V_PF2_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_6 -tclproc VAL_PF2_ENTRY_TYPE_6 -parent $T_PF2_6] + set V_PF2_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_6 -tclproc VAL_PF2_ENTRY_BAR_6 -parent $T_PF2_6] + set V_PF2_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_6 -tclproc VAL_PF2_ENTRY_ADDR_6 -parent $T_PF2_6] + set V_PF2_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_6 -parent $T_PF2_6] + set V_PF2_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_6 -parent $T_PF2_6] + set V_PF2_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_6 -parent $T_PF2_6] + set V_PF2_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_6 -tclproc VAL_PF2_ENTRY_RSVD0_6 -parent $T_PF2_6] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_6 + + set PF2_Values_7 [ipgui::add_group $IPINST -name "PF2 - Table Entry 7 Values" -parent $PF2_Values] + set T_PF2_7 [ipgui::add_table $IPINST -name T_PF2_7 -rows 7 -columns 2 -parent $PF2_Values_7] + set L_PF2_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_7 -text "C_PF2_ENTRY_TYPE_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_7 -text "C_PF2_ENTRY_BAR_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_7 -text "C_PF2_ENTRY_ADDR_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_7 -text "C_PF2_ENTRY_VERSION_TYPE_7 " -parent $T_PF2_7] + set L_PF2_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_7 -text "C_PF2_ENTRY_MAJOR_VERSION_7" -parent $T_PF2_7] + set L_PF2_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_7 -text "C_PF2_ENTRY_MINOR_VERSION_7" -parent $T_PF2_7] + set L_PF2_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_7 -text "C_PF2_ENTRY_RSVD0_7 " -parent $T_PF2_7] + set V_PF2_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_7 -tclproc VAL_PF2_ENTRY_TYPE_7 -parent $T_PF2_7] + set V_PF2_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_7 -tclproc VAL_PF2_ENTRY_BAR_7 -parent $T_PF2_7] + set V_PF2_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_7 -tclproc VAL_PF2_ENTRY_ADDR_7 -parent $T_PF2_7] + set V_PF2_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_7 -parent $T_PF2_7] + set V_PF2_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_7 -parent $T_PF2_7] + set V_PF2_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_7 -parent $T_PF2_7] + set V_PF2_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_7 -tclproc VAL_PF2_ENTRY_RSVD0_7 -parent $T_PF2_7] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_7 + + set PF2_Values_8 [ipgui::add_group $IPINST -name "PF2 - Table Entry 8 Values" -parent $PF2_Values] + set T_PF2_8 [ipgui::add_table $IPINST -name T_PF2_8 -rows 7 -columns 2 -parent $PF2_Values_8] + set L_PF2_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_8 -text "C_PF2_ENTRY_TYPE_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_8 -text "C_PF2_ENTRY_BAR_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_8 -text "C_PF2_ENTRY_ADDR_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_8 -text "C_PF2_ENTRY_VERSION_TYPE_8 " -parent $T_PF2_8] + set L_PF2_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_8 -text "C_PF2_ENTRY_MAJOR_VERSION_8" -parent $T_PF2_8] + set L_PF2_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_8 -text "C_PF2_ENTRY_MINOR_VERSION_8" -parent $T_PF2_8] + set L_PF2_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_8 -text "C_PF2_ENTRY_RSVD0_8 " -parent $T_PF2_8] + set V_PF2_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_8 -tclproc VAL_PF2_ENTRY_TYPE_8 -parent $T_PF2_8] + set V_PF2_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_8 -tclproc VAL_PF2_ENTRY_BAR_8 -parent $T_PF2_8] + set V_PF2_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_8 -tclproc VAL_PF2_ENTRY_ADDR_8 -parent $T_PF2_8] + set V_PF2_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_8 -parent $T_PF2_8] + set V_PF2_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_8 -parent $T_PF2_8] + set V_PF2_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_8 -parent $T_PF2_8] + set V_PF2_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_8 -tclproc VAL_PF2_ENTRY_RSVD0_8 -parent $T_PF2_8] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_8 + + set PF2_Values_9 [ipgui::add_group $IPINST -name "PF2 - Table Entry 9 Values" -parent $PF2_Values] + set T_PF2_9 [ipgui::add_table $IPINST -name T_PF2_9 -rows 7 -columns 2 -parent $PF2_Values_9] + set L_PF2_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_9 -text "C_PF2_ENTRY_TYPE_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_9 -text "C_PF2_ENTRY_BAR_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_9 -text "C_PF2_ENTRY_ADDR_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_9 -text "C_PF2_ENTRY_VERSION_TYPE_9 " -parent $T_PF2_9] + set L_PF2_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_9 -text "C_PF2_ENTRY_MAJOR_VERSION_9" -parent $T_PF2_9] + set L_PF2_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_9 -text "C_PF2_ENTRY_MINOR_VERSION_9" -parent $T_PF2_9] + set L_PF2_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_9 -text "C_PF2_ENTRY_RSVD0_9 " -parent $T_PF2_9] + set V_PF2_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_9 -tclproc VAL_PF2_ENTRY_TYPE_9 -parent $T_PF2_9] + set V_PF2_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_9 -tclproc VAL_PF2_ENTRY_BAR_9 -parent $T_PF2_9] + set V_PF2_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_9 -tclproc VAL_PF2_ENTRY_ADDR_9 -parent $T_PF2_9] + set V_PF2_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_9 -parent $T_PF2_9] + set V_PF2_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_9 -parent $T_PF2_9] + set V_PF2_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_9 -parent $T_PF2_9] + set V_PF2_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_9 -tclproc VAL_PF2_ENTRY_RSVD0_9 -parent $T_PF2_9] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_9 + + set PF2_Values_10 [ipgui::add_group $IPINST -name "PF2 - Table Entry 10 Values" -parent $PF2_Values] + set T_PF2_10 [ipgui::add_table $IPINST -name T_PF2_10 -rows 7 -columns 2 -parent $PF2_Values_10] + set L_PF2_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_10 -text "C_PF2_ENTRY_TYPE_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_10 -text "C_PF2_ENTRY_BAR_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_10 -text "C_PF2_ENTRY_ADDR_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_10 -text "C_PF2_ENTRY_VERSION_TYPE_10 " -parent $T_PF2_10] + set L_PF2_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_10 -text "C_PF2_ENTRY_MAJOR_VERSION_10" -parent $T_PF2_10] + set L_PF2_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_10 -text "C_PF2_ENTRY_MINOR_VERSION_10" -parent $T_PF2_10] + set L_PF2_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_10 -text "C_PF2_ENTRY_RSVD0_10 " -parent $T_PF2_10] + set V_PF2_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_10 -tclproc VAL_PF2_ENTRY_TYPE_10 -parent $T_PF2_10] + set V_PF2_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_10 -tclproc VAL_PF2_ENTRY_BAR_10 -parent $T_PF2_10] + set V_PF2_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_10 -tclproc VAL_PF2_ENTRY_ADDR_10 -parent $T_PF2_10] + set V_PF2_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_10 -parent $T_PF2_10] + set V_PF2_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_10 -parent $T_PF2_10] + set V_PF2_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_10 -parent $T_PF2_10] + set V_PF2_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_10 -tclproc VAL_PF2_ENTRY_RSVD0_10 -parent $T_PF2_10] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_10 + + set PF2_Values_11 [ipgui::add_group $IPINST -name "PF2 - Table Entry 11 Values" -parent $PF2_Values] + set T_PF2_11 [ipgui::add_table $IPINST -name T_PF2_11 -rows 7 -columns 2 -parent $PF2_Values_11] + set L_PF2_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_11 -text "C_PF2_ENTRY_TYPE_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_11 -text "C_PF2_ENTRY_BAR_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_11 -text "C_PF2_ENTRY_ADDR_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_11 -text "C_PF2_ENTRY_VERSION_TYPE_11 " -parent $T_PF2_11] + set L_PF2_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_11 -text "C_PF2_ENTRY_MAJOR_VERSION_11" -parent $T_PF2_11] + set L_PF2_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_11 -text "C_PF2_ENTRY_MINOR_VERSION_11" -parent $T_PF2_11] + set L_PF2_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_11 -text "C_PF2_ENTRY_RSVD0_11 " -parent $T_PF2_11] + set V_PF2_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_11 -tclproc VAL_PF2_ENTRY_TYPE_11 -parent $T_PF2_11] + set V_PF2_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_11 -tclproc VAL_PF2_ENTRY_BAR_11 -parent $T_PF2_11] + set V_PF2_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_11 -tclproc VAL_PF2_ENTRY_ADDR_11 -parent $T_PF2_11] + set V_PF2_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_11 -parent $T_PF2_11] + set V_PF2_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_11 -parent $T_PF2_11] + set V_PF2_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_11 -parent $T_PF2_11] + set V_PF2_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_11 -tclproc VAL_PF2_ENTRY_RSVD0_11 -parent $T_PF2_11] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_11 + + set PF2_Values_12 [ipgui::add_group $IPINST -name "PF2 - Table Entry 12 Values" -parent $PF2_Values] + set T_PF2_12 [ipgui::add_table $IPINST -name T_PF2_12 -rows 7 -columns 2 -parent $PF2_Values_12] + set L_PF2_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_12 -text "C_PF2_ENTRY_TYPE_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_12 -text "C_PF2_ENTRY_BAR_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_12 -text "C_PF2_ENTRY_ADDR_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_12 -text "C_PF2_ENTRY_VERSION_TYPE_12 " -parent $T_PF2_12] + set L_PF2_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_12 -text "C_PF2_ENTRY_MAJOR_VERSION_12" -parent $T_PF2_12] + set L_PF2_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_12 -text "C_PF2_ENTRY_MINOR_VERSION_12" -parent $T_PF2_12] + set L_PF2_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_12 -text "C_PF2_ENTRY_RSVD0_12 " -parent $T_PF2_12] + set V_PF2_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_12 -tclproc VAL_PF2_ENTRY_TYPE_12 -parent $T_PF2_12] + set V_PF2_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_12 -tclproc VAL_PF2_ENTRY_BAR_12 -parent $T_PF2_12] + set V_PF2_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_12 -tclproc VAL_PF2_ENTRY_ADDR_12 -parent $T_PF2_12] + set V_PF2_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_12 -parent $T_PF2_12] + set V_PF2_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_12 -parent $T_PF2_12] + set V_PF2_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_12 -parent $T_PF2_12] + set V_PF2_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_12 -tclproc VAL_PF2_ENTRY_RSVD0_12 -parent $T_PF2_12] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_12 + + set PF2_Values_13 [ipgui::add_group $IPINST -name "PF2 - Table Entry 13 Values" -parent $PF2_Values] + set T_PF2_13 [ipgui::add_table $IPINST -name T_PF2_13 -rows 7 -columns 2 -parent $PF2_Values_13] + set L_PF2_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_TYPE_13 -text "C_PF2_ENTRY_TYPE_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_BAR_13 -text "C_PF2_ENTRY_BAR_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_ADDR_13 -text "C_PF2_ENTRY_ADDR_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_VERSION_TYPE_13 -text "C_PF2_ENTRY_VERSION_TYPE_13 " -parent $T_PF2_13] + set L_PF2_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MAJOR_VERSION_13 -text "C_PF2_ENTRY_MAJOR_VERSION_13" -parent $T_PF2_13] + set L_PF2_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_MINOR_VERSION_13 -text "C_PF2_ENTRY_MINOR_VERSION_13" -parent $T_PF2_13] + set L_PF2_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF2_ENTRY_RSVD0_13 -text "C_PF2_ENTRY_RSVD0_13 " -parent $T_PF2_13] + set V_PF2_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_TYPE_13 -tclproc VAL_PF2_ENTRY_TYPE_13 -parent $T_PF2_13] + set V_PF2_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_BAR_13 -tclproc VAL_PF2_ENTRY_BAR_13 -parent $T_PF2_13] + set V_PF2_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_ADDR_13 -tclproc VAL_PF2_ENTRY_ADDR_13 -parent $T_PF2_13] + set V_PF2_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF2_ENTRY_VERSION_TYPE_13 -parent $T_PF2_13] + set V_PF2_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF2_ENTRY_MAJOR_VERSION_13 -parent $T_PF2_13] + set V_PF2_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF2_ENTRY_MINOR_VERSION_13 -parent $T_PF2_13] + set V_PF2_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF2_ENTRY_RSVD0_13 -tclproc VAL_PF2_ENTRY_RSVD0_13 -parent $T_PF2_13] + set_property cell_location 0,0 $L_PF2_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF2_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF2_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF2_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF2_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF2_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF2_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF2_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF2_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF2_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF2_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF2_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF2_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF2_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF2_ENTRY_RSVD0_13 + + set PF3_Values [ipgui::add_page $IPINST -name "PF3 Values"] + set PF3_Values_General [ipgui::add_group $IPINST -name "PF3 - General Values" -parent $PF3_Values] + set T_PF3_GENERAL [ipgui::add_table $IPINST -name T_PF3_GENERAL -rows 4 -columns 2 -parent $PF3_Values_General] + set L_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_static_text $IPINST -name L_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -text "C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE" -parent $T_PF3_GENERAL] + set L_PF3_BAR_INDEX [ipgui::add_static_text $IPINST -name L_PF3_BAR_INDEX -text "C_PF3_BAR_INDEX " -parent $T_PF3_GENERAL] + set L_PF3_LOW_OFFSET [ipgui::add_static_text $IPINST -name L_PF3_LOW_OFFSET -text "C_PF3_LOW_OFFSET " -parent $T_PF3_GENERAL] + set L_PF3_HIGH_OFFSET [ipgui::add_static_text $IPINST -name L_PF3_HIGH_OFFSET -text "C_PF3_HIGH_OFFSET " -parent $T_PF3_GENERAL] + set V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE [ipgui::add_dynamic_text $IPINST -name V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -tclproc VAL_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE -parent $T_PF3_GENERAL] + set V_PF3_BAR_INDEX [ipgui::add_dynamic_text $IPINST -name V_PF3_BAR_INDEX -tclproc VAL_PF3_BAR_INDEX -parent $T_PF3_GENERAL] + set V_PF3_LOW_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF3_LOW_OFFSET -tclproc VAL_PF3_LOW_OFFSET -parent $T_PF3_GENERAL] + set V_PF3_HIGH_OFFSET [ipgui::add_dynamic_text $IPINST -name V_PF3_HIGH_OFFSET -tclproc VAL_PF3_HIGH_OFFSET -parent $T_PF3_GENERAL] + set_property cell_location 0,0 $L_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,0 $L_PF3_BAR_INDEX + set_property cell_location 2,0 $L_PF3_LOW_OFFSET + set_property cell_location 3,0 $L_PF3_HIGH_OFFSET + set_property cell_location 0,1 $V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property cell_location 1,1 $V_PF3_BAR_INDEX + set_property cell_location 2,1 $V_PF3_LOW_OFFSET + set_property cell_location 3,1 $V_PF3_HIGH_OFFSET + set_property obj_color "192,192,192" $V_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE + set_property obj_color "192,192,192" $V_PF3_BAR_INDEX + set_property obj_color "192,192,192" $V_PF3_LOW_OFFSET + set_property obj_color "192,192,192" $V_PF3_HIGH_OFFSET + + set PF3_Values_0 [ipgui::add_group $IPINST -name "PF3 - Table Entry 0 Values" -parent $PF3_Values] + set T_PF3_0 [ipgui::add_table $IPINST -name T_PF3_0 -rows 7 -columns 2 -parent $PF3_Values_0] + set L_PF3_ENTRY_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_0 -text "C_PF3_ENTRY_TYPE_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_BAR_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_0 -text "C_PF3_ENTRY_BAR_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_ADDR_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_0 -text "C_PF3_ENTRY_ADDR_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_VERSION_TYPE_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_0 -text "C_PF3_ENTRY_VERSION_TYPE_0 " -parent $T_PF3_0] + set L_PF3_ENTRY_MAJOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_0 -text "C_PF3_ENTRY_MAJOR_VERSION_0" -parent $T_PF3_0] + set L_PF3_ENTRY_MINOR_VERSION_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_0 -text "C_PF3_ENTRY_MINOR_VERSION_0" -parent $T_PF3_0] + set L_PF3_ENTRY_RSVD0_0 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_0 -text "C_PF3_ENTRY_RSVD0_0 " -parent $T_PF3_0] + set V_PF3_ENTRY_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_0 -tclproc VAL_PF3_ENTRY_TYPE_0 -parent $T_PF3_0] + set V_PF3_ENTRY_BAR_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_0 -tclproc VAL_PF3_ENTRY_BAR_0 -parent $T_PF3_0] + set V_PF3_ENTRY_ADDR_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_0 -tclproc VAL_PF3_ENTRY_ADDR_0 -parent $T_PF3_0] + set V_PF3_ENTRY_VERSION_TYPE_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_0 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_0 -parent $T_PF3_0] + set V_PF3_ENTRY_MAJOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_0 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_0 -parent $T_PF3_0] + set V_PF3_ENTRY_MINOR_VERSION_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_0 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_0 -parent $T_PF3_0] + set V_PF3_ENTRY_RSVD0_0 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_0 -tclproc VAL_PF3_ENTRY_RSVD0_0 -parent $T_PF3_0] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_0 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_0 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_0 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_0 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_0 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_0 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_0 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_0 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_0 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_0 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_0 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_0 + + set PF3_Values_1 [ipgui::add_group $IPINST -name "PF3 - Table Entry 1 Values" -parent $PF3_Values] + set T_PF3_1 [ipgui::add_table $IPINST -name T_PF3_1 -rows 7 -columns 2 -parent $PF3_Values_1] + set L_PF3_ENTRY_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_1 -text "C_PF3_ENTRY_TYPE_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_BAR_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_1 -text "C_PF3_ENTRY_BAR_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_ADDR_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_1 -text "C_PF3_ENTRY_ADDR_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_VERSION_TYPE_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_1 -text "C_PF3_ENTRY_VERSION_TYPE_1 " -parent $T_PF3_1] + set L_PF3_ENTRY_MAJOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_1 -text "C_PF3_ENTRY_MAJOR_VERSION_1" -parent $T_PF3_1] + set L_PF3_ENTRY_MINOR_VERSION_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_1 -text "C_PF3_ENTRY_MINOR_VERSION_1" -parent $T_PF3_1] + set L_PF3_ENTRY_RSVD0_1 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_1 -text "C_PF3_ENTRY_RSVD0_1 " -parent $T_PF3_1] + set V_PF3_ENTRY_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_1 -tclproc VAL_PF3_ENTRY_TYPE_1 -parent $T_PF3_1] + set V_PF3_ENTRY_BAR_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_1 -tclproc VAL_PF3_ENTRY_BAR_1 -parent $T_PF3_1] + set V_PF3_ENTRY_ADDR_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_1 -tclproc VAL_PF3_ENTRY_ADDR_1 -parent $T_PF3_1] + set V_PF3_ENTRY_VERSION_TYPE_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_1 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_1 -parent $T_PF3_1] + set V_PF3_ENTRY_MAJOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_1 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_1 -parent $T_PF3_1] + set V_PF3_ENTRY_MINOR_VERSION_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_1 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_1 -parent $T_PF3_1] + set V_PF3_ENTRY_RSVD0_1 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_1 -tclproc VAL_PF3_ENTRY_RSVD0_1 -parent $T_PF3_1] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_1 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_1 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_1 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_1 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_1 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_1 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_1 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_1 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_1 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_1 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_1 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_1 + + set PF3_Values_2 [ipgui::add_group $IPINST -name "PF3 - Table Entry 2 Values" -parent $PF3_Values] + set T_PF3_2 [ipgui::add_table $IPINST -name T_PF3_2 -rows 7 -columns 2 -parent $PF3_Values_2] + set L_PF3_ENTRY_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_2 -text "C_PF3_ENTRY_TYPE_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_BAR_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_2 -text "C_PF3_ENTRY_BAR_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_ADDR_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_2 -text "C_PF3_ENTRY_ADDR_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_VERSION_TYPE_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_2 -text "C_PF3_ENTRY_VERSION_TYPE_2 " -parent $T_PF3_2] + set L_PF3_ENTRY_MAJOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_2 -text "C_PF3_ENTRY_MAJOR_VERSION_2" -parent $T_PF3_2] + set L_PF3_ENTRY_MINOR_VERSION_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_2 -text "C_PF3_ENTRY_MINOR_VERSION_2" -parent $T_PF3_2] + set L_PF3_ENTRY_RSVD0_2 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_2 -text "C_PF3_ENTRY_RSVD0_2 " -parent $T_PF3_2] + set V_PF3_ENTRY_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_2 -tclproc VAL_PF3_ENTRY_TYPE_2 -parent $T_PF3_2] + set V_PF3_ENTRY_BAR_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_2 -tclproc VAL_PF3_ENTRY_BAR_2 -parent $T_PF3_2] + set V_PF3_ENTRY_ADDR_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_2 -tclproc VAL_PF3_ENTRY_ADDR_2 -parent $T_PF3_2] + set V_PF3_ENTRY_VERSION_TYPE_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_2 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_2 -parent $T_PF3_2] + set V_PF3_ENTRY_MAJOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_2 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_2 -parent $T_PF3_2] + set V_PF3_ENTRY_MINOR_VERSION_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_2 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_2 -parent $T_PF3_2] + set V_PF3_ENTRY_RSVD0_2 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_2 -tclproc VAL_PF3_ENTRY_RSVD0_2 -parent $T_PF3_2] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_2 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_2 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_2 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_2 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_2 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_2 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_2 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_2 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_2 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_2 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_2 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_2 + + set PF3_Values_3 [ipgui::add_group $IPINST -name "PF3 - Table Entry 3 Values" -parent $PF3_Values] + set T_PF3_3 [ipgui::add_table $IPINST -name T_PF3_3 -rows 7 -columns 2 -parent $PF3_Values_3] + set L_PF3_ENTRY_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_3 -text "C_PF3_ENTRY_TYPE_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_BAR_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_3 -text "C_PF3_ENTRY_BAR_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_ADDR_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_3 -text "C_PF3_ENTRY_ADDR_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_VERSION_TYPE_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_3 -text "C_PF3_ENTRY_VERSION_TYPE_3 " -parent $T_PF3_3] + set L_PF3_ENTRY_MAJOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_3 -text "C_PF3_ENTRY_MAJOR_VERSION_3" -parent $T_PF3_3] + set L_PF3_ENTRY_MINOR_VERSION_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_3 -text "C_PF3_ENTRY_MINOR_VERSION_3" -parent $T_PF3_3] + set L_PF3_ENTRY_RSVD0_3 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_3 -text "C_PF3_ENTRY_RSVD0_3 " -parent $T_PF3_3] + set V_PF3_ENTRY_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_3 -tclproc VAL_PF3_ENTRY_TYPE_3 -parent $T_PF3_3] + set V_PF3_ENTRY_BAR_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_3 -tclproc VAL_PF3_ENTRY_BAR_3 -parent $T_PF3_3] + set V_PF3_ENTRY_ADDR_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_3 -tclproc VAL_PF3_ENTRY_ADDR_3 -parent $T_PF3_3] + set V_PF3_ENTRY_VERSION_TYPE_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_3 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_3 -parent $T_PF3_3] + set V_PF3_ENTRY_MAJOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_3 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_3 -parent $T_PF3_3] + set V_PF3_ENTRY_MINOR_VERSION_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_3 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_3 -parent $T_PF3_3] + set V_PF3_ENTRY_RSVD0_3 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_3 -tclproc VAL_PF3_ENTRY_RSVD0_3 -parent $T_PF3_3] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_3 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_3 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_3 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_3 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_3 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_3 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_3 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_3 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_3 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_3 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_3 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_3 + + set PF3_Values_4 [ipgui::add_group $IPINST -name "PF3 - Table Entry 4 Values" -parent $PF3_Values] + set T_PF3_4 [ipgui::add_table $IPINST -name T_PF3_4 -rows 7 -columns 2 -parent $PF3_Values_4] + set L_PF3_ENTRY_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_4 -text "C_PF3_ENTRY_TYPE_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_BAR_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_4 -text "C_PF3_ENTRY_BAR_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_ADDR_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_4 -text "C_PF3_ENTRY_ADDR_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_VERSION_TYPE_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_4 -text "C_PF3_ENTRY_VERSION_TYPE_4 " -parent $T_PF3_4] + set L_PF3_ENTRY_MAJOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_4 -text "C_PF3_ENTRY_MAJOR_VERSION_4" -parent $T_PF3_4] + set L_PF3_ENTRY_MINOR_VERSION_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_4 -text "C_PF3_ENTRY_MINOR_VERSION_4" -parent $T_PF3_4] + set L_PF3_ENTRY_RSVD0_4 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_4 -text "C_PF3_ENTRY_RSVD0_4 " -parent $T_PF3_4] + set V_PF3_ENTRY_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_4 -tclproc VAL_PF3_ENTRY_TYPE_4 -parent $T_PF3_4] + set V_PF3_ENTRY_BAR_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_4 -tclproc VAL_PF3_ENTRY_BAR_4 -parent $T_PF3_4] + set V_PF3_ENTRY_ADDR_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_4 -tclproc VAL_PF3_ENTRY_ADDR_4 -parent $T_PF3_4] + set V_PF3_ENTRY_VERSION_TYPE_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_4 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_4 -parent $T_PF3_4] + set V_PF3_ENTRY_MAJOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_4 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_4 -parent $T_PF3_4] + set V_PF3_ENTRY_MINOR_VERSION_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_4 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_4 -parent $T_PF3_4] + set V_PF3_ENTRY_RSVD0_4 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_4 -tclproc VAL_PF3_ENTRY_RSVD0_4 -parent $T_PF3_4] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_4 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_4 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_4 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_4 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_4 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_4 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_4 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_4 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_4 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_4 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_4 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_4 + + set PF3_Values_5 [ipgui::add_group $IPINST -name "PF3 - Table Entry 5 Values" -parent $PF3_Values] + set T_PF3_5 [ipgui::add_table $IPINST -name T_PF3_5 -rows 7 -columns 2 -parent $PF3_Values_5] + set L_PF3_ENTRY_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_5 -text "C_PF3_ENTRY_TYPE_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_BAR_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_5 -text "C_PF3_ENTRY_BAR_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_ADDR_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_5 -text "C_PF3_ENTRY_ADDR_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_VERSION_TYPE_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_5 -text "C_PF3_ENTRY_VERSION_TYPE_5 " -parent $T_PF3_5] + set L_PF3_ENTRY_MAJOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_5 -text "C_PF3_ENTRY_MAJOR_VERSION_5" -parent $T_PF3_5] + set L_PF3_ENTRY_MINOR_VERSION_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_5 -text "C_PF3_ENTRY_MINOR_VERSION_5" -parent $T_PF3_5] + set L_PF3_ENTRY_RSVD0_5 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_5 -text "C_PF3_ENTRY_RSVD0_5 " -parent $T_PF3_5] + set V_PF3_ENTRY_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_5 -tclproc VAL_PF3_ENTRY_TYPE_5 -parent $T_PF3_5] + set V_PF3_ENTRY_BAR_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_5 -tclproc VAL_PF3_ENTRY_BAR_5 -parent $T_PF3_5] + set V_PF3_ENTRY_ADDR_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_5 -tclproc VAL_PF3_ENTRY_ADDR_5 -parent $T_PF3_5] + set V_PF3_ENTRY_VERSION_TYPE_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_5 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_5 -parent $T_PF3_5] + set V_PF3_ENTRY_MAJOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_5 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_5 -parent $T_PF3_5] + set V_PF3_ENTRY_MINOR_VERSION_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_5 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_5 -parent $T_PF3_5] + set V_PF3_ENTRY_RSVD0_5 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_5 -tclproc VAL_PF3_ENTRY_RSVD0_5 -parent $T_PF3_5] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_5 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_5 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_5 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_5 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_5 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_5 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_5 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_5 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_5 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_5 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_5 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_5 + + set PF3_Values_6 [ipgui::add_group $IPINST -name "PF3 - Table Entry 6 Values" -parent $PF3_Values] + set T_PF3_6 [ipgui::add_table $IPINST -name T_PF3_6 -rows 7 -columns 2 -parent $PF3_Values_6] + set L_PF3_ENTRY_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_6 -text "C_PF3_ENTRY_TYPE_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_BAR_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_6 -text "C_PF3_ENTRY_BAR_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_ADDR_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_6 -text "C_PF3_ENTRY_ADDR_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_VERSION_TYPE_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_6 -text "C_PF3_ENTRY_VERSION_TYPE_6 " -parent $T_PF3_6] + set L_PF3_ENTRY_MAJOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_6 -text "C_PF3_ENTRY_MAJOR_VERSION_6" -parent $T_PF3_6] + set L_PF3_ENTRY_MINOR_VERSION_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_6 -text "C_PF3_ENTRY_MINOR_VERSION_6" -parent $T_PF3_6] + set L_PF3_ENTRY_RSVD0_6 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_6 -text "C_PF3_ENTRY_RSVD0_6 " -parent $T_PF3_6] + set V_PF3_ENTRY_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_6 -tclproc VAL_PF3_ENTRY_TYPE_6 -parent $T_PF3_6] + set V_PF3_ENTRY_BAR_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_6 -tclproc VAL_PF3_ENTRY_BAR_6 -parent $T_PF3_6] + set V_PF3_ENTRY_ADDR_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_6 -tclproc VAL_PF3_ENTRY_ADDR_6 -parent $T_PF3_6] + set V_PF3_ENTRY_VERSION_TYPE_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_6 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_6 -parent $T_PF3_6] + set V_PF3_ENTRY_MAJOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_6 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_6 -parent $T_PF3_6] + set V_PF3_ENTRY_MINOR_VERSION_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_6 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_6 -parent $T_PF3_6] + set V_PF3_ENTRY_RSVD0_6 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_6 -tclproc VAL_PF3_ENTRY_RSVD0_6 -parent $T_PF3_6] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_6 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_6 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_6 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_6 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_6 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_6 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_6 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_6 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_6 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_6 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_6 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_6 + + set PF3_Values_7 [ipgui::add_group $IPINST -name "PF3 - Table Entry 7 Values" -parent $PF3_Values] + set T_PF3_7 [ipgui::add_table $IPINST -name T_PF3_7 -rows 7 -columns 2 -parent $PF3_Values_7] + set L_PF3_ENTRY_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_7 -text "C_PF3_ENTRY_TYPE_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_BAR_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_7 -text "C_PF3_ENTRY_BAR_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_ADDR_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_7 -text "C_PF3_ENTRY_ADDR_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_VERSION_TYPE_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_7 -text "C_PF3_ENTRY_VERSION_TYPE_7 " -parent $T_PF3_7] + set L_PF3_ENTRY_MAJOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_7 -text "C_PF3_ENTRY_MAJOR_VERSION_7" -parent $T_PF3_7] + set L_PF3_ENTRY_MINOR_VERSION_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_7 -text "C_PF3_ENTRY_MINOR_VERSION_7" -parent $T_PF3_7] + set L_PF3_ENTRY_RSVD0_7 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_7 -text "C_PF3_ENTRY_RSVD0_7 " -parent $T_PF3_7] + set V_PF3_ENTRY_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_7 -tclproc VAL_PF3_ENTRY_TYPE_7 -parent $T_PF3_7] + set V_PF3_ENTRY_BAR_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_7 -tclproc VAL_PF3_ENTRY_BAR_7 -parent $T_PF3_7] + set V_PF3_ENTRY_ADDR_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_7 -tclproc VAL_PF3_ENTRY_ADDR_7 -parent $T_PF3_7] + set V_PF3_ENTRY_VERSION_TYPE_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_7 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_7 -parent $T_PF3_7] + set V_PF3_ENTRY_MAJOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_7 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_7 -parent $T_PF3_7] + set V_PF3_ENTRY_MINOR_VERSION_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_7 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_7 -parent $T_PF3_7] + set V_PF3_ENTRY_RSVD0_7 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_7 -tclproc VAL_PF3_ENTRY_RSVD0_7 -parent $T_PF3_7] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_7 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_7 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_7 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_7 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_7 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_7 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_7 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_7 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_7 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_7 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_7 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_7 + + set PF3_Values_8 [ipgui::add_group $IPINST -name "PF3 - Table Entry 8 Values" -parent $PF3_Values] + set T_PF3_8 [ipgui::add_table $IPINST -name T_PF3_8 -rows 7 -columns 2 -parent $PF3_Values_8] + set L_PF3_ENTRY_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_8 -text "C_PF3_ENTRY_TYPE_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_BAR_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_8 -text "C_PF3_ENTRY_BAR_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_ADDR_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_8 -text "C_PF3_ENTRY_ADDR_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_VERSION_TYPE_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_8 -text "C_PF3_ENTRY_VERSION_TYPE_8 " -parent $T_PF3_8] + set L_PF3_ENTRY_MAJOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_8 -text "C_PF3_ENTRY_MAJOR_VERSION_8" -parent $T_PF3_8] + set L_PF3_ENTRY_MINOR_VERSION_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_8 -text "C_PF3_ENTRY_MINOR_VERSION_8" -parent $T_PF3_8] + set L_PF3_ENTRY_RSVD0_8 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_8 -text "C_PF3_ENTRY_RSVD0_8 " -parent $T_PF3_8] + set V_PF3_ENTRY_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_8 -tclproc VAL_PF3_ENTRY_TYPE_8 -parent $T_PF3_8] + set V_PF3_ENTRY_BAR_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_8 -tclproc VAL_PF3_ENTRY_BAR_8 -parent $T_PF3_8] + set V_PF3_ENTRY_ADDR_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_8 -tclproc VAL_PF3_ENTRY_ADDR_8 -parent $T_PF3_8] + set V_PF3_ENTRY_VERSION_TYPE_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_8 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_8 -parent $T_PF3_8] + set V_PF3_ENTRY_MAJOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_8 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_8 -parent $T_PF3_8] + set V_PF3_ENTRY_MINOR_VERSION_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_8 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_8 -parent $T_PF3_8] + set V_PF3_ENTRY_RSVD0_8 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_8 -tclproc VAL_PF3_ENTRY_RSVD0_8 -parent $T_PF3_8] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_8 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_8 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_8 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_8 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_8 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_8 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_8 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_8 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_8 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_8 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_8 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_8 + + set PF3_Values_9 [ipgui::add_group $IPINST -name "PF3 - Table Entry 9 Values" -parent $PF3_Values] + set T_PF3_9 [ipgui::add_table $IPINST -name T_PF3_9 -rows 7 -columns 2 -parent $PF3_Values_9] + set L_PF3_ENTRY_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_9 -text "C_PF3_ENTRY_TYPE_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_BAR_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_9 -text "C_PF3_ENTRY_BAR_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_ADDR_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_9 -text "C_PF3_ENTRY_ADDR_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_VERSION_TYPE_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_9 -text "C_PF3_ENTRY_VERSION_TYPE_9 " -parent $T_PF3_9] + set L_PF3_ENTRY_MAJOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_9 -text "C_PF3_ENTRY_MAJOR_VERSION_9" -parent $T_PF3_9] + set L_PF3_ENTRY_MINOR_VERSION_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_9 -text "C_PF3_ENTRY_MINOR_VERSION_9" -parent $T_PF3_9] + set L_PF3_ENTRY_RSVD0_9 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_9 -text "C_PF3_ENTRY_RSVD0_9 " -parent $T_PF3_9] + set V_PF3_ENTRY_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_9 -tclproc VAL_PF3_ENTRY_TYPE_9 -parent $T_PF3_9] + set V_PF3_ENTRY_BAR_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_9 -tclproc VAL_PF3_ENTRY_BAR_9 -parent $T_PF3_9] + set V_PF3_ENTRY_ADDR_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_9 -tclproc VAL_PF3_ENTRY_ADDR_9 -parent $T_PF3_9] + set V_PF3_ENTRY_VERSION_TYPE_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_9 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_9 -parent $T_PF3_9] + set V_PF3_ENTRY_MAJOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_9 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_9 -parent $T_PF3_9] + set V_PF3_ENTRY_MINOR_VERSION_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_9 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_9 -parent $T_PF3_9] + set V_PF3_ENTRY_RSVD0_9 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_9 -tclproc VAL_PF3_ENTRY_RSVD0_9 -parent $T_PF3_9] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_9 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_9 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_9 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_9 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_9 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_9 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_9 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_9 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_9 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_9 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_9 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_9 + + set PF3_Values_10 [ipgui::add_group $IPINST -name "PF3 - Table Entry 10 Values" -parent $PF3_Values] + set T_PF3_10 [ipgui::add_table $IPINST -name T_PF3_10 -rows 7 -columns 2 -parent $PF3_Values_10] + set L_PF3_ENTRY_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_10 -text "C_PF3_ENTRY_TYPE_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_BAR_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_10 -text "C_PF3_ENTRY_BAR_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_ADDR_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_10 -text "C_PF3_ENTRY_ADDR_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_VERSION_TYPE_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_10 -text "C_PF3_ENTRY_VERSION_TYPE_10 " -parent $T_PF3_10] + set L_PF3_ENTRY_MAJOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_10 -text "C_PF3_ENTRY_MAJOR_VERSION_10" -parent $T_PF3_10] + set L_PF3_ENTRY_MINOR_VERSION_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_10 -text "C_PF3_ENTRY_MINOR_VERSION_10" -parent $T_PF3_10] + set L_PF3_ENTRY_RSVD0_10 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_10 -text "C_PF3_ENTRY_RSVD0_10 " -parent $T_PF3_10] + set V_PF3_ENTRY_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_10 -tclproc VAL_PF3_ENTRY_TYPE_10 -parent $T_PF3_10] + set V_PF3_ENTRY_BAR_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_10 -tclproc VAL_PF3_ENTRY_BAR_10 -parent $T_PF3_10] + set V_PF3_ENTRY_ADDR_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_10 -tclproc VAL_PF3_ENTRY_ADDR_10 -parent $T_PF3_10] + set V_PF3_ENTRY_VERSION_TYPE_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_10 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_10 -parent $T_PF3_10] + set V_PF3_ENTRY_MAJOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_10 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_10 -parent $T_PF3_10] + set V_PF3_ENTRY_MINOR_VERSION_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_10 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_10 -parent $T_PF3_10] + set V_PF3_ENTRY_RSVD0_10 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_10 -tclproc VAL_PF3_ENTRY_RSVD0_10 -parent $T_PF3_10] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_10 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_10 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_10 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_10 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_10 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_10 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_10 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_10 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_10 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_10 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_10 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_10 + + set PF3_Values_11 [ipgui::add_group $IPINST -name "PF3 - Table Entry 11 Values" -parent $PF3_Values] + set T_PF3_11 [ipgui::add_table $IPINST -name T_PF3_11 -rows 7 -columns 2 -parent $PF3_Values_11] + set L_PF3_ENTRY_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_11 -text "C_PF3_ENTRY_TYPE_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_BAR_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_11 -text "C_PF3_ENTRY_BAR_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_ADDR_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_11 -text "C_PF3_ENTRY_ADDR_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_VERSION_TYPE_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_11 -text "C_PF3_ENTRY_VERSION_TYPE_11 " -parent $T_PF3_11] + set L_PF3_ENTRY_MAJOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_11 -text "C_PF3_ENTRY_MAJOR_VERSION_11" -parent $T_PF3_11] + set L_PF3_ENTRY_MINOR_VERSION_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_11 -text "C_PF3_ENTRY_MINOR_VERSION_11" -parent $T_PF3_11] + set L_PF3_ENTRY_RSVD0_11 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_11 -text "C_PF3_ENTRY_RSVD0_11 " -parent $T_PF3_11] + set V_PF3_ENTRY_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_11 -tclproc VAL_PF3_ENTRY_TYPE_11 -parent $T_PF3_11] + set V_PF3_ENTRY_BAR_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_11 -tclproc VAL_PF3_ENTRY_BAR_11 -parent $T_PF3_11] + set V_PF3_ENTRY_ADDR_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_11 -tclproc VAL_PF3_ENTRY_ADDR_11 -parent $T_PF3_11] + set V_PF3_ENTRY_VERSION_TYPE_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_11 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_11 -parent $T_PF3_11] + set V_PF3_ENTRY_MAJOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_11 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_11 -parent $T_PF3_11] + set V_PF3_ENTRY_MINOR_VERSION_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_11 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_11 -parent $T_PF3_11] + set V_PF3_ENTRY_RSVD0_11 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_11 -tclproc VAL_PF3_ENTRY_RSVD0_11 -parent $T_PF3_11] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_11 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_11 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_11 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_11 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_11 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_11 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_11 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_11 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_11 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_11 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_11 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_11 + + set PF3_Values_12 [ipgui::add_group $IPINST -name "PF3 - Table Entry 12 Values" -parent $PF3_Values] + set T_PF3_12 [ipgui::add_table $IPINST -name T_PF3_12 -rows 7 -columns 2 -parent $PF3_Values_12] + set L_PF3_ENTRY_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_12 -text "C_PF3_ENTRY_TYPE_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_BAR_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_12 -text "C_PF3_ENTRY_BAR_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_ADDR_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_12 -text "C_PF3_ENTRY_ADDR_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_VERSION_TYPE_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_12 -text "C_PF3_ENTRY_VERSION_TYPE_12 " -parent $T_PF3_12] + set L_PF3_ENTRY_MAJOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_12 -text "C_PF3_ENTRY_MAJOR_VERSION_12" -parent $T_PF3_12] + set L_PF3_ENTRY_MINOR_VERSION_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_12 -text "C_PF3_ENTRY_MINOR_VERSION_12" -parent $T_PF3_12] + set L_PF3_ENTRY_RSVD0_12 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_12 -text "C_PF3_ENTRY_RSVD0_12 " -parent $T_PF3_12] + set V_PF3_ENTRY_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_12 -tclproc VAL_PF3_ENTRY_TYPE_12 -parent $T_PF3_12] + set V_PF3_ENTRY_BAR_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_12 -tclproc VAL_PF3_ENTRY_BAR_12 -parent $T_PF3_12] + set V_PF3_ENTRY_ADDR_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_12 -tclproc VAL_PF3_ENTRY_ADDR_12 -parent $T_PF3_12] + set V_PF3_ENTRY_VERSION_TYPE_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_12 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_12 -parent $T_PF3_12] + set V_PF3_ENTRY_MAJOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_12 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_12 -parent $T_PF3_12] + set V_PF3_ENTRY_MINOR_VERSION_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_12 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_12 -parent $T_PF3_12] + set V_PF3_ENTRY_RSVD0_12 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_12 -tclproc VAL_PF3_ENTRY_RSVD0_12 -parent $T_PF3_12] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_12 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_12 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_12 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_12 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_12 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_12 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_12 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_12 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_12 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_12 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_12 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_12 + + set PF3_Values_13 [ipgui::add_group $IPINST -name "PF3 - Table Entry 13 Values" -parent $PF3_Values] + set T_PF3_13 [ipgui::add_table $IPINST -name T_PF3_13 -rows 7 -columns 2 -parent $PF3_Values_13] + set L_PF3_ENTRY_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_TYPE_13 -text "C_PF3_ENTRY_TYPE_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_BAR_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_BAR_13 -text "C_PF3_ENTRY_BAR_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_ADDR_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_ADDR_13 -text "C_PF3_ENTRY_ADDR_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_VERSION_TYPE_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_VERSION_TYPE_13 -text "C_PF3_ENTRY_VERSION_TYPE_13 " -parent $T_PF3_13] + set L_PF3_ENTRY_MAJOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MAJOR_VERSION_13 -text "C_PF3_ENTRY_MAJOR_VERSION_13" -parent $T_PF3_13] + set L_PF3_ENTRY_MINOR_VERSION_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_MINOR_VERSION_13 -text "C_PF3_ENTRY_MINOR_VERSION_13" -parent $T_PF3_13] + set L_PF3_ENTRY_RSVD0_13 [ipgui::add_static_text $IPINST -name L_PF3_ENTRY_RSVD0_13 -text "C_PF3_ENTRY_RSVD0_13 " -parent $T_PF3_13] + set V_PF3_ENTRY_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_TYPE_13 -tclproc VAL_PF3_ENTRY_TYPE_13 -parent $T_PF3_13] + set V_PF3_ENTRY_BAR_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_BAR_13 -tclproc VAL_PF3_ENTRY_BAR_13 -parent $T_PF3_13] + set V_PF3_ENTRY_ADDR_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_ADDR_13 -tclproc VAL_PF3_ENTRY_ADDR_13 -parent $T_PF3_13] + set V_PF3_ENTRY_VERSION_TYPE_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_VERSION_TYPE_13 -tclproc VAL_PF3_ENTRY_VERSION_TYPE_13 -parent $T_PF3_13] + set V_PF3_ENTRY_MAJOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MAJOR_VERSION_13 -tclproc VAL_PF3_ENTRY_MAJOR_VERSION_13 -parent $T_PF3_13] + set V_PF3_ENTRY_MINOR_VERSION_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_MINOR_VERSION_13 -tclproc VAL_PF3_ENTRY_MINOR_VERSION_13 -parent $T_PF3_13] + set V_PF3_ENTRY_RSVD0_13 [ipgui::add_dynamic_text $IPINST -name V_PF3_ENTRY_RSVD0_13 -tclproc VAL_PF3_ENTRY_RSVD0_13 -parent $T_PF3_13] + set_property cell_location 0,0 $L_PF3_ENTRY_TYPE_13 + set_property cell_location 1,0 $L_PF3_ENTRY_BAR_13 + set_property cell_location 2,0 $L_PF3_ENTRY_ADDR_13 + set_property cell_location 3,0 $L_PF3_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,0 $L_PF3_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,0 $L_PF3_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,0 $L_PF3_ENTRY_RSVD0_13 + set_property cell_location 0,1 $V_PF3_ENTRY_TYPE_13 + set_property cell_location 1,1 $V_PF3_ENTRY_BAR_13 + set_property cell_location 2,1 $V_PF3_ENTRY_ADDR_13 + set_property cell_location 3,1 $V_PF3_ENTRY_VERSION_TYPE_13 + set_property cell_location 4,1 $V_PF3_ENTRY_MAJOR_VERSION_13 + set_property cell_location 5,1 $V_PF3_ENTRY_MINOR_VERSION_13 + set_property cell_location 6,1 $V_PF3_ENTRY_RSVD0_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_TYPE_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_BAR_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_ADDR_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_VERSION_TYPE_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MAJOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_MINOR_VERSION_13 + set_property obj_color "192,192,192" $V_PF3_ENTRY_RSVD0_13 +} + +proc update_PARAM_VALUE.C_PF1_ENDPOINT_NAMES { PARAM_VALUE.C_PF1_ENDPOINT_NAMES PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs > 1} { + set_property enabled true ${PARAM_VALUE.C_PF1_ENDPOINT_NAMES} + } else { + set_property enabled false ${PARAM_VALUE.C_PF1_ENDPOINT_NAMES} + } +} + +proc update_PARAM_VALUE.C_PF2_ENDPOINT_NAMES { PARAM_VALUE.C_PF2_ENDPOINT_NAMES PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >2} { + set_property enabled true ${PARAM_VALUE.C_PF2_ENDPOINT_NAMES} + } else { + set_property enabled false ${PARAM_VALUE.C_PF2_ENDPOINT_NAMES} + } +} + +proc update_PARAM_VALUE.C_PF3_ENDPOINT_NAMES { PARAM_VALUE.C_PF3_ENDPOINT_NAMES PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >3} { + set_property enabled true ${PARAM_VALUE.C_PF3_ENDPOINT_NAMES} + } else { + set_property enabled false ${PARAM_VALUE.C_PF3_ENDPOINT_NAMES} + } +} + +proc update_PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >1} { + set_property enabled true ${PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} + } else { + set_property enabled false ${PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} + } +} + +proc update_PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >2} { + set_property enabled true ${PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} + } else { + set_property enabled false ${PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} + } +} + +proc update_PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH PARAM_VALUE.C_NUM_PFS} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + if {$num_pfs >3} { + set_property enabled true ${PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} + } else { + set_property enabled false ${PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} + } +} + +proc update_MODELPARAM_VALUE.C_NUM_PFS { MODELPARAM_VALUE.C_NUM_PFS PARAM_VALUE.C_NUM_PFS} { + set_property value [get_property value ${PARAM_VALUE.C_NUM_PFS}] ${MODELPARAM_VALUE.C_NUM_PFS} +} + +proc update_MODELPARAM_VALUE.C_CAP_BASE_ADDR { MODELPARAM_VALUE.C_CAP_BASE_ADDR PARAM_VALUE.C_CAP_BASE_ADDR} { + set_property value [get_property value ${PARAM_VALUE.C_CAP_BASE_ADDR}] ${MODELPARAM_VALUE.C_CAP_BASE_ADDR} +} + +proc validate_PARAM_VALUE.C_CAP_BASE_ADDR { PARAM_VALUE.C_CAP_BASE_ADDR IPINST} { + set cap_base_addr [get_property value ${PARAM_VALUE.C_CAP_BASE_ADDR}] + if {[expr $cap_base_addr & 0x00F] == 0x000} { + return true + } else { + set_property errmsg "C_CAP_BASE_ADDR must be a multiple of 0x10." [ipgui::get_paramspec -name C_CAP_BASE_ADDR -of $IPINST ] + return false + } +} + +proc update_MODELPARAM_VALUE.C_NEXT_CAP_ADDR { MODELPARAM_VALUE.C_NEXT_CAP_ADDR PARAM_VALUE.C_NEXT_CAP_ADDR} { + set_property value [get_property value ${PARAM_VALUE.C_NEXT_CAP_ADDR}] ${MODELPARAM_VALUE.C_NEXT_CAP_ADDR} +} + +proc validate_PARAM_VALUE.C_NEXT_CAP_ADDR {PARAM_VALUE.C_CAP_BASE_ADDR PARAM_VALUE.C_NEXT_CAP_ADDR IPINST} { + set cap_base_addr [get_property value ${PARAM_VALUE.C_CAP_BASE_ADDR}] + set calc_cap_base_addr [ expr {$cap_base_addr + 0x010} ] + set nxt_cap_base_addr [get_property value ${PARAM_VALUE.C_NEXT_CAP_ADDR}] + if { $nxt_cap_base_addr == 0x000} { + return true + } elseif {[expr $nxt_cap_base_addr & 0x00F] != 0x000} { + set_property errmsg "C_NEXT_CAP_ADDR must be a multiple of 0x10." [ipgui::get_paramspec -name C_NEXT_CAP_ADDR -of $IPINST ] + return false + } elseif {$nxt_cap_base_addr >= $calc_cap_base_addr} { + return true + } else { + set_property errmsg "C_NEXT_CAP_ADDR must be at least 0x010 above C_CAP_BASE_ADDR." [ipgui::get_paramspec -name C_NEXT_CAP_ADDR -of $IPINST ] + return false + } +} + +proc update_MODELPARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF0_BAR_INDEX { MODELPARAM_VALUE.C_PF0_BAR_INDEX PARAM_VALUE.C_PF0_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF0_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF0_LOW_OFFSET { MODELPARAM_VALUE.C_PF0_LOW_OFFSET PARAM_VALUE.C_PF0_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF0_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF0_HIGH_OFFSET { MODELPARAM_VALUE.C_PF0_HIGH_OFFSET PARAM_VALUE.C_PF0_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF0_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF0_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF0_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF0_ENDPOINT_NAMES PARAM_VALUE.C_PF0_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF0_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF0_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_0 PARAM_VALUE.C_PF0_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_1 PARAM_VALUE.C_PF0_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_2 PARAM_VALUE.C_PF0_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_3 PARAM_VALUE.C_PF0_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_4 PARAM_VALUE.C_PF0_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_5 PARAM_VALUE.C_PF0_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_6 PARAM_VALUE.C_PF0_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_7 PARAM_VALUE.C_PF0_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_8 PARAM_VALUE.C_PF0_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_9 PARAM_VALUE.C_PF0_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_10 PARAM_VALUE.C_PF0_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_11 PARAM_VALUE.C_PF0_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_12 PARAM_VALUE.C_PF0_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_13 PARAM_VALUE.C_PF0_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_0 PARAM_VALUE.C_PF0_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_1 PARAM_VALUE.C_PF0_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_2 PARAM_VALUE.C_PF0_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_3 PARAM_VALUE.C_PF0_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_4 PARAM_VALUE.C_PF0_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_5 PARAM_VALUE.C_PF0_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_6 PARAM_VALUE.C_PF0_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_7 PARAM_VALUE.C_PF0_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_8 PARAM_VALUE.C_PF0_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_9 PARAM_VALUE.C_PF0_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_10 PARAM_VALUE.C_PF0_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_11 PARAM_VALUE.C_PF0_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_12 PARAM_VALUE.C_PF0_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF0_ENTRY_BAR_13 PARAM_VALUE.C_PF0_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_0 PARAM_VALUE.C_PF0_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_1 PARAM_VALUE.C_PF0_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_2 PARAM_VALUE.C_PF0_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_3 PARAM_VALUE.C_PF0_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_4 PARAM_VALUE.C_PF0_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_5 PARAM_VALUE.C_PF0_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_6 PARAM_VALUE.C_PF0_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_7 PARAM_VALUE.C_PF0_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_8 PARAM_VALUE.C_PF0_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_9 PARAM_VALUE.C_PF0_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_10 PARAM_VALUE.C_PF0_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_11 PARAM_VALUE.C_PF0_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_12 PARAM_VALUE.C_PF0_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_13 PARAM_VALUE.C_PF0_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_0 PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_1 PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_2 PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_3 PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_4 PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_5 PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_6 PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_7 PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_8 PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_9 PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_10 PARAM_VALUE.C_PF0_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_11 PARAM_VALUE.C_PF0_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_12 PARAM_VALUE.C_PF0_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_13 PARAM_VALUE.C_PF0_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF0_ENTRY_RSVD0_13}} + +proc update_MODELPARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF1_BAR_INDEX { MODELPARAM_VALUE.C_PF1_BAR_INDEX PARAM_VALUE.C_PF1_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF1_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF1_LOW_OFFSET { MODELPARAM_VALUE.C_PF1_LOW_OFFSET PARAM_VALUE.C_PF1_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF1_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF1_HIGH_OFFSET { MODELPARAM_VALUE.C_PF1_HIGH_OFFSET PARAM_VALUE.C_PF1_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF1_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF1_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF1_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF1_ENDPOINT_NAMES PARAM_VALUE.C_PF1_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF1_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF1_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_0 PARAM_VALUE.C_PF1_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_1 PARAM_VALUE.C_PF1_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_2 PARAM_VALUE.C_PF1_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_3 PARAM_VALUE.C_PF1_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_4 PARAM_VALUE.C_PF1_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_5 PARAM_VALUE.C_PF1_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_6 PARAM_VALUE.C_PF1_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_7 PARAM_VALUE.C_PF1_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_8 PARAM_VALUE.C_PF1_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_9 PARAM_VALUE.C_PF1_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_10 PARAM_VALUE.C_PF1_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_11 PARAM_VALUE.C_PF1_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_12 PARAM_VALUE.C_PF1_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_13 PARAM_VALUE.C_PF1_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_0 PARAM_VALUE.C_PF1_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_1 PARAM_VALUE.C_PF1_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_2 PARAM_VALUE.C_PF1_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_3 PARAM_VALUE.C_PF1_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_4 PARAM_VALUE.C_PF1_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_5 PARAM_VALUE.C_PF1_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_6 PARAM_VALUE.C_PF1_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_7 PARAM_VALUE.C_PF1_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_8 PARAM_VALUE.C_PF1_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_9 PARAM_VALUE.C_PF1_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_10 PARAM_VALUE.C_PF1_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_11 PARAM_VALUE.C_PF1_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_12 PARAM_VALUE.C_PF1_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF1_ENTRY_BAR_13 PARAM_VALUE.C_PF1_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_0 PARAM_VALUE.C_PF1_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_1 PARAM_VALUE.C_PF1_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_2 PARAM_VALUE.C_PF1_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_3 PARAM_VALUE.C_PF1_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_4 PARAM_VALUE.C_PF1_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_5 PARAM_VALUE.C_PF1_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_6 PARAM_VALUE.C_PF1_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_7 PARAM_VALUE.C_PF1_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_8 PARAM_VALUE.C_PF1_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_9 PARAM_VALUE.C_PF1_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_10 PARAM_VALUE.C_PF1_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_11 PARAM_VALUE.C_PF1_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_12 PARAM_VALUE.C_PF1_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_13 PARAM_VALUE.C_PF1_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_0 PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_1 PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_2 PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_3 PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_4 PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_5 PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_6 PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_7 PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_8 PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_9 PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_10 PARAM_VALUE.C_PF1_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_11 PARAM_VALUE.C_PF1_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_12 PARAM_VALUE.C_PF1_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_13 PARAM_VALUE.C_PF1_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF1_ENTRY_RSVD0_13}} + +proc update_MODELPARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF2_BAR_INDEX { MODELPARAM_VALUE.C_PF2_BAR_INDEX PARAM_VALUE.C_PF2_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF2_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF2_LOW_OFFSET { MODELPARAM_VALUE.C_PF2_LOW_OFFSET PARAM_VALUE.C_PF2_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF2_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF2_HIGH_OFFSET { MODELPARAM_VALUE.C_PF2_HIGH_OFFSET PARAM_VALUE.C_PF2_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF2_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF2_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF2_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF2_ENDPOINT_NAMES PARAM_VALUE.C_PF2_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF2_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF2_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_0 PARAM_VALUE.C_PF2_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_1 PARAM_VALUE.C_PF2_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_2 PARAM_VALUE.C_PF2_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_3 PARAM_VALUE.C_PF2_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_4 PARAM_VALUE.C_PF2_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_5 PARAM_VALUE.C_PF2_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_6 PARAM_VALUE.C_PF2_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_7 PARAM_VALUE.C_PF2_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_8 PARAM_VALUE.C_PF2_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_9 PARAM_VALUE.C_PF2_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_10 PARAM_VALUE.C_PF2_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_11 PARAM_VALUE.C_PF2_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_12 PARAM_VALUE.C_PF2_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_13 PARAM_VALUE.C_PF2_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_0 PARAM_VALUE.C_PF2_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_1 PARAM_VALUE.C_PF2_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_2 PARAM_VALUE.C_PF2_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_3 PARAM_VALUE.C_PF2_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_4 PARAM_VALUE.C_PF2_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_5 PARAM_VALUE.C_PF2_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_6 PARAM_VALUE.C_PF2_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_7 PARAM_VALUE.C_PF2_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_8 PARAM_VALUE.C_PF2_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_9 PARAM_VALUE.C_PF2_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_10 PARAM_VALUE.C_PF2_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_11 PARAM_VALUE.C_PF2_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_12 PARAM_VALUE.C_PF2_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF2_ENTRY_BAR_13 PARAM_VALUE.C_PF2_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_0 PARAM_VALUE.C_PF2_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_1 PARAM_VALUE.C_PF2_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_2 PARAM_VALUE.C_PF2_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_3 PARAM_VALUE.C_PF2_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_4 PARAM_VALUE.C_PF2_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_5 PARAM_VALUE.C_PF2_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_6 PARAM_VALUE.C_PF2_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_7 PARAM_VALUE.C_PF2_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_8 PARAM_VALUE.C_PF2_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_9 PARAM_VALUE.C_PF2_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_10 PARAM_VALUE.C_PF2_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_11 PARAM_VALUE.C_PF2_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_12 PARAM_VALUE.C_PF2_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_13 PARAM_VALUE.C_PF2_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_0 PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_1 PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_2 PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_3 PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_4 PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_5 PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_6 PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_7 PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_8 PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_9 PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_10 PARAM_VALUE.C_PF2_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_11 PARAM_VALUE.C_PF2_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_12 PARAM_VALUE.C_PF2_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_13 PARAM_VALUE.C_PF2_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF2_ENTRY_RSVD0_13}} + +proc update_MODELPARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE { MODELPARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE}] ${MODELPARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} +} +proc update_MODELPARAM_VALUE.C_PF3_BAR_INDEX { MODELPARAM_VALUE.C_PF3_BAR_INDEX PARAM_VALUE.C_PF3_BAR_INDEX} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_BAR_INDEX}] ${MODELPARAM_VALUE.C_PF3_BAR_INDEX} +} +proc update_MODELPARAM_VALUE.C_PF3_LOW_OFFSET { MODELPARAM_VALUE.C_PF3_LOW_OFFSET PARAM_VALUE.C_PF3_LOW_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_LOW_OFFSET}] ${MODELPARAM_VALUE.C_PF3_LOW_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF3_HIGH_OFFSET { MODELPARAM_VALUE.C_PF3_HIGH_OFFSET PARAM_VALUE.C_PF3_HIGH_OFFSET} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_HIGH_OFFSET}] ${MODELPARAM_VALUE.C_PF3_HIGH_OFFSET} +} +proc update_MODELPARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_PF3_S_AXI_ADDR_WIDTH} +} +proc update_MODELPARAM_VALUE.C_PF3_ENDPOINT_NAMES { MODELPARAM_VALUE.C_PF3_ENDPOINT_NAMES PARAM_VALUE.C_PF3_ENDPOINT_NAMES} { + set_property value [get_property value ${PARAM_VALUE.C_PF3_ENDPOINT_NAMES}] ${MODELPARAM_VALUE.C_PF3_ENDPOINT_NAMES} +} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_0 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_0 PARAM_VALUE.C_PF3_ENTRY_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_1 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_1 PARAM_VALUE.C_PF3_ENTRY_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_2 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_2 PARAM_VALUE.C_PF3_ENTRY_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_3 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_3 PARAM_VALUE.C_PF3_ENTRY_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_4 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_4 PARAM_VALUE.C_PF3_ENTRY_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_5 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_5 PARAM_VALUE.C_PF3_ENTRY_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_6 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_6 PARAM_VALUE.C_PF3_ENTRY_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_7 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_7 PARAM_VALUE.C_PF3_ENTRY_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_8 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_8 PARAM_VALUE.C_PF3_ENTRY_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_9 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_9 PARAM_VALUE.C_PF3_ENTRY_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_10 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_10 PARAM_VALUE.C_PF3_ENTRY_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_11 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_11 PARAM_VALUE.C_PF3_ENTRY_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_12 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_12 PARAM_VALUE.C_PF3_ENTRY_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_13 { MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_13 PARAM_VALUE.C_PF3_ENTRY_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_0 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_0 PARAM_VALUE.C_PF3_ENTRY_BAR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_1 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_1 PARAM_VALUE.C_PF3_ENTRY_BAR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_2 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_2 PARAM_VALUE.C_PF3_ENTRY_BAR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_3 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_3 PARAM_VALUE.C_PF3_ENTRY_BAR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_4 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_4 PARAM_VALUE.C_PF3_ENTRY_BAR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_5 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_5 PARAM_VALUE.C_PF3_ENTRY_BAR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_6 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_6 PARAM_VALUE.C_PF3_ENTRY_BAR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_7 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_7 PARAM_VALUE.C_PF3_ENTRY_BAR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_8 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_8 PARAM_VALUE.C_PF3_ENTRY_BAR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_9 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_9 PARAM_VALUE.C_PF3_ENTRY_BAR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_10 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_10 PARAM_VALUE.C_PF3_ENTRY_BAR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_11 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_11 PARAM_VALUE.C_PF3_ENTRY_BAR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_12 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_12 PARAM_VALUE.C_PF3_ENTRY_BAR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_BAR_13 { MODELPARAM_VALUE.C_PF3_ENTRY_BAR_13 PARAM_VALUE.C_PF3_ENTRY_BAR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_BAR_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_0 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_0 PARAM_VALUE.C_PF3_ENTRY_ADDR_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_1 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_1 PARAM_VALUE.C_PF3_ENTRY_ADDR_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_2 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_2 PARAM_VALUE.C_PF3_ENTRY_ADDR_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_3 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_3 PARAM_VALUE.C_PF3_ENTRY_ADDR_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_4 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_4 PARAM_VALUE.C_PF3_ENTRY_ADDR_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_5 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_5 PARAM_VALUE.C_PF3_ENTRY_ADDR_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_6 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_6 PARAM_VALUE.C_PF3_ENTRY_ADDR_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_7 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_7 PARAM_VALUE.C_PF3_ENTRY_ADDR_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_8 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_8 PARAM_VALUE.C_PF3_ENTRY_ADDR_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_9 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_9 PARAM_VALUE.C_PF3_ENTRY_ADDR_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_10 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_10 PARAM_VALUE.C_PF3_ENTRY_ADDR_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_11 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_11 PARAM_VALUE.C_PF3_ENTRY_ADDR_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_12 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_12 PARAM_VALUE.C_PF3_ENTRY_ADDR_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_13 { MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_13 PARAM_VALUE.C_PF3_ENTRY_ADDR_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_ADDR_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13 { MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13 PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13 { MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13 PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13 { MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13 PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13}} + +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_0 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_0 PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_0}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_1 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_1 PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_1}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_2 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_2 PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_2}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_3 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_3 PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_3}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_4 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_4 PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_4}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_5 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_5 PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_5}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_6 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_6 PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_6}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_7 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_7 PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_7}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_8 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_8 PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_8}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_9 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_9 PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} ] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_9}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_10 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_10 PARAM_VALUE.C_PF3_ENTRY_RSVD0_10} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_10}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_10}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_11 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_11 PARAM_VALUE.C_PF3_ENTRY_RSVD0_11} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_11}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_11}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_12 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_12 PARAM_VALUE.C_PF3_ENTRY_RSVD0_12} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_12}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_12}} +proc update_MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_13 { MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_13 PARAM_VALUE.C_PF3_ENTRY_RSVD0_13} {set_property value [get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_13}] ${MODELPARAM_VALUE.C_PF3_ENTRY_RSVD0_13}} + +proc VAL_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF0_BAR_INDEX { PARAM_VALUE.C_PF0_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF0_BAR_INDEX}]"} +proc VAL_PF0_LOW_OFFSET { PARAM_VALUE.C_PF0_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF0_LOW_OFFSET}]"} +proc VAL_PF0_HIGH_OFFSET { PARAM_VALUE.C_PF0_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF0_HIGH_OFFSET}]"} + +proc VAL_PF0_ENTRY_TYPE_0 { PARAM_VALUE.C_PF0_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_0} ]"} +proc VAL_PF0_ENTRY_TYPE_1 { PARAM_VALUE.C_PF0_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_1} ]"} +proc VAL_PF0_ENTRY_TYPE_2 { PARAM_VALUE.C_PF0_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_2} ]"} +proc VAL_PF0_ENTRY_TYPE_3 { PARAM_VALUE.C_PF0_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_3} ]"} +proc VAL_PF0_ENTRY_TYPE_4 { PARAM_VALUE.C_PF0_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_4} ]"} +proc VAL_PF0_ENTRY_TYPE_5 { PARAM_VALUE.C_PF0_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_5} ]"} +proc VAL_PF0_ENTRY_TYPE_6 { PARAM_VALUE.C_PF0_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_6} ]"} +proc VAL_PF0_ENTRY_TYPE_7 { PARAM_VALUE.C_PF0_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_7} ]"} +proc VAL_PF0_ENTRY_TYPE_8 { PARAM_VALUE.C_PF0_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_8} ]"} +proc VAL_PF0_ENTRY_TYPE_9 { PARAM_VALUE.C_PF0_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_9} ]"} +proc VAL_PF0_ENTRY_TYPE_10 { PARAM_VALUE.C_PF0_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_10}]"} +proc VAL_PF0_ENTRY_TYPE_11 { PARAM_VALUE.C_PF0_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_11}]"} +proc VAL_PF0_ENTRY_TYPE_12 { PARAM_VALUE.C_PF0_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_12}]"} +proc VAL_PF0_ENTRY_TYPE_13 { PARAM_VALUE.C_PF0_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_TYPE_13}]"} + +proc VAL_PF0_ENTRY_BAR_0 { PARAM_VALUE.C_PF0_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_0} ]"} +proc VAL_PF0_ENTRY_BAR_1 { PARAM_VALUE.C_PF0_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_1} ]"} +proc VAL_PF0_ENTRY_BAR_2 { PARAM_VALUE.C_PF0_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_2} ]"} +proc VAL_PF0_ENTRY_BAR_3 { PARAM_VALUE.C_PF0_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_3} ]"} +proc VAL_PF0_ENTRY_BAR_4 { PARAM_VALUE.C_PF0_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_4} ]"} +proc VAL_PF0_ENTRY_BAR_5 { PARAM_VALUE.C_PF0_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_5} ]"} +proc VAL_PF0_ENTRY_BAR_6 { PARAM_VALUE.C_PF0_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_6} ]"} +proc VAL_PF0_ENTRY_BAR_7 { PARAM_VALUE.C_PF0_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_7} ]"} +proc VAL_PF0_ENTRY_BAR_8 { PARAM_VALUE.C_PF0_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_8} ]"} +proc VAL_PF0_ENTRY_BAR_9 { PARAM_VALUE.C_PF0_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_9} ]"} +proc VAL_PF0_ENTRY_BAR_10 { PARAM_VALUE.C_PF0_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_10} ]"} +proc VAL_PF0_ENTRY_BAR_11 { PARAM_VALUE.C_PF0_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_11} ]"} +proc VAL_PF0_ENTRY_BAR_12 { PARAM_VALUE.C_PF0_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_12} ]"} +proc VAL_PF0_ENTRY_BAR_13 { PARAM_VALUE.C_PF0_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_BAR_13} ]"} + +proc VAL_PF0_ENTRY_ADDR_0 { PARAM_VALUE.C_PF0_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_0} ]"} +proc VAL_PF0_ENTRY_ADDR_1 { PARAM_VALUE.C_PF0_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_1} ]"} +proc VAL_PF0_ENTRY_ADDR_2 { PARAM_VALUE.C_PF0_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_2} ]"} +proc VAL_PF0_ENTRY_ADDR_3 { PARAM_VALUE.C_PF0_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_3} ]"} +proc VAL_PF0_ENTRY_ADDR_4 { PARAM_VALUE.C_PF0_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_4} ]"} +proc VAL_PF0_ENTRY_ADDR_5 { PARAM_VALUE.C_PF0_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_5} ]"} +proc VAL_PF0_ENTRY_ADDR_6 { PARAM_VALUE.C_PF0_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_6} ]"} +proc VAL_PF0_ENTRY_ADDR_7 { PARAM_VALUE.C_PF0_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_7} ]"} +proc VAL_PF0_ENTRY_ADDR_8 { PARAM_VALUE.C_PF0_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_8} ]"} +proc VAL_PF0_ENTRY_ADDR_9 { PARAM_VALUE.C_PF0_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_9} ]"} +proc VAL_PF0_ENTRY_ADDR_10 { PARAM_VALUE.C_PF0_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_10} ]"} +proc VAL_PF0_ENTRY_ADDR_11 { PARAM_VALUE.C_PF0_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_11} ]"} +proc VAL_PF0_ENTRY_ADDR_12 { PARAM_VALUE.C_PF0_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_12} ]"} +proc VAL_PF0_ENTRY_ADDR_13 { PARAM_VALUE.C_PF0_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_ADDR_13} ]"} + +proc VAL_PF0_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF0_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF0_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF0_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF0_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF0_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF0_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_0} ]"} +proc VAL_PF0_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_1} ]"} +proc VAL_PF0_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_2} ]"} +proc VAL_PF0_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_3} ]"} +proc VAL_PF0_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_4} ]"} +proc VAL_PF0_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_5} ]"} +proc VAL_PF0_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_6} ]"} +proc VAL_PF0_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_7} ]"} +proc VAL_PF0_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_8} ]"} +proc VAL_PF0_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_9} ]"} +proc VAL_PF0_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_10} ]"} +proc VAL_PF0_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_11} ]"} +proc VAL_PF0_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_12} ]"} +proc VAL_PF0_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF0_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF0_ENTRY_RSVD0_13} ]"} + +proc VAL_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF1_BAR_INDEX { PARAM_VALUE.C_PF1_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF1_BAR_INDEX}]"} +proc VAL_PF1_LOW_OFFSET { PARAM_VALUE.C_PF1_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF1_LOW_OFFSET}]"} +proc VAL_PF1_HIGH_OFFSET { PARAM_VALUE.C_PF1_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF1_HIGH_OFFSET}]"} + +proc VAL_PF1_ENTRY_TYPE_0 { PARAM_VALUE.C_PF1_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_0} ]"} +proc VAL_PF1_ENTRY_TYPE_1 { PARAM_VALUE.C_PF1_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_1} ]"} +proc VAL_PF1_ENTRY_TYPE_2 { PARAM_VALUE.C_PF1_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_2} ]"} +proc VAL_PF1_ENTRY_TYPE_3 { PARAM_VALUE.C_PF1_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_3} ]"} +proc VAL_PF1_ENTRY_TYPE_4 { PARAM_VALUE.C_PF1_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_4} ]"} +proc VAL_PF1_ENTRY_TYPE_5 { PARAM_VALUE.C_PF1_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_5} ]"} +proc VAL_PF1_ENTRY_TYPE_6 { PARAM_VALUE.C_PF1_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_6} ]"} +proc VAL_PF1_ENTRY_TYPE_7 { PARAM_VALUE.C_PF1_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_7} ]"} +proc VAL_PF1_ENTRY_TYPE_8 { PARAM_VALUE.C_PF1_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_8} ]"} +proc VAL_PF1_ENTRY_TYPE_9 { PARAM_VALUE.C_PF1_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_9} ]"} +proc VAL_PF1_ENTRY_TYPE_10 { PARAM_VALUE.C_PF1_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_10}]"} +proc VAL_PF1_ENTRY_TYPE_11 { PARAM_VALUE.C_PF1_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_11}]"} +proc VAL_PF1_ENTRY_TYPE_12 { PARAM_VALUE.C_PF1_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_12}]"} +proc VAL_PF1_ENTRY_TYPE_13 { PARAM_VALUE.C_PF1_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_TYPE_13}]"} + +proc VAL_PF1_ENTRY_BAR_0 { PARAM_VALUE.C_PF1_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_0} ]"} +proc VAL_PF1_ENTRY_BAR_1 { PARAM_VALUE.C_PF1_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_1} ]"} +proc VAL_PF1_ENTRY_BAR_2 { PARAM_VALUE.C_PF1_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_2} ]"} +proc VAL_PF1_ENTRY_BAR_3 { PARAM_VALUE.C_PF1_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_3} ]"} +proc VAL_PF1_ENTRY_BAR_4 { PARAM_VALUE.C_PF1_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_4} ]"} +proc VAL_PF1_ENTRY_BAR_5 { PARAM_VALUE.C_PF1_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_5} ]"} +proc VAL_PF1_ENTRY_BAR_6 { PARAM_VALUE.C_PF1_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_6} ]"} +proc VAL_PF1_ENTRY_BAR_7 { PARAM_VALUE.C_PF1_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_7} ]"} +proc VAL_PF1_ENTRY_BAR_8 { PARAM_VALUE.C_PF1_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_8} ]"} +proc VAL_PF1_ENTRY_BAR_9 { PARAM_VALUE.C_PF1_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_9} ]"} +proc VAL_PF1_ENTRY_BAR_10 { PARAM_VALUE.C_PF1_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_10} ]"} +proc VAL_PF1_ENTRY_BAR_11 { PARAM_VALUE.C_PF1_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_11} ]"} +proc VAL_PF1_ENTRY_BAR_12 { PARAM_VALUE.C_PF1_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_12} ]"} +proc VAL_PF1_ENTRY_BAR_13 { PARAM_VALUE.C_PF1_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_BAR_13} ]"} + +proc VAL_PF1_ENTRY_ADDR_0 { PARAM_VALUE.C_PF1_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_0} ]"} +proc VAL_PF1_ENTRY_ADDR_1 { PARAM_VALUE.C_PF1_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_1} ]"} +proc VAL_PF1_ENTRY_ADDR_2 { PARAM_VALUE.C_PF1_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_2} ]"} +proc VAL_PF1_ENTRY_ADDR_3 { PARAM_VALUE.C_PF1_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_3} ]"} +proc VAL_PF1_ENTRY_ADDR_4 { PARAM_VALUE.C_PF1_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_4} ]"} +proc VAL_PF1_ENTRY_ADDR_5 { PARAM_VALUE.C_PF1_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_5} ]"} +proc VAL_PF1_ENTRY_ADDR_6 { PARAM_VALUE.C_PF1_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_6} ]"} +proc VAL_PF1_ENTRY_ADDR_7 { PARAM_VALUE.C_PF1_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_7} ]"} +proc VAL_PF1_ENTRY_ADDR_8 { PARAM_VALUE.C_PF1_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_8} ]"} +proc VAL_PF1_ENTRY_ADDR_9 { PARAM_VALUE.C_PF1_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_9} ]"} +proc VAL_PF1_ENTRY_ADDR_10 { PARAM_VALUE.C_PF1_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_10} ]"} +proc VAL_PF1_ENTRY_ADDR_11 { PARAM_VALUE.C_PF1_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_11} ]"} +proc VAL_PF1_ENTRY_ADDR_12 { PARAM_VALUE.C_PF1_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_12} ]"} +proc VAL_PF1_ENTRY_ADDR_13 { PARAM_VALUE.C_PF1_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_ADDR_13} ]"} + +proc VAL_PF1_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF1_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF1_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF1_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF1_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF1_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF1_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_0} ]"} +proc VAL_PF1_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_1} ]"} +proc VAL_PF1_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_2} ]"} +proc VAL_PF1_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_3} ]"} +proc VAL_PF1_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_4} ]"} +proc VAL_PF1_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_5} ]"} +proc VAL_PF1_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_6} ]"} +proc VAL_PF1_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_7} ]"} +proc VAL_PF1_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_8} ]"} +proc VAL_PF1_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_9} ]"} +proc VAL_PF1_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_10} ]"} +proc VAL_PF1_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_11} ]"} +proc VAL_PF1_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_12} ]"} +proc VAL_PF1_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF1_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF1_ENTRY_RSVD0_13} ]"} + +proc VAL_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF2_BAR_INDEX { PARAM_VALUE.C_PF2_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF2_BAR_INDEX}]"} +proc VAL_PF2_LOW_OFFSET { PARAM_VALUE.C_PF2_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF2_LOW_OFFSET}]"} +proc VAL_PF2_HIGH_OFFSET { PARAM_VALUE.C_PF2_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF2_HIGH_OFFSET}]"} + +proc VAL_PF2_ENTRY_TYPE_0 { PARAM_VALUE.C_PF2_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_0} ]"} +proc VAL_PF2_ENTRY_TYPE_1 { PARAM_VALUE.C_PF2_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_1} ]"} +proc VAL_PF2_ENTRY_TYPE_2 { PARAM_VALUE.C_PF2_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_2} ]"} +proc VAL_PF2_ENTRY_TYPE_3 { PARAM_VALUE.C_PF2_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_3} ]"} +proc VAL_PF2_ENTRY_TYPE_4 { PARAM_VALUE.C_PF2_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_4} ]"} +proc VAL_PF2_ENTRY_TYPE_5 { PARAM_VALUE.C_PF2_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_5} ]"} +proc VAL_PF2_ENTRY_TYPE_6 { PARAM_VALUE.C_PF2_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_6} ]"} +proc VAL_PF2_ENTRY_TYPE_7 { PARAM_VALUE.C_PF2_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_7} ]"} +proc VAL_PF2_ENTRY_TYPE_8 { PARAM_VALUE.C_PF2_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_8} ]"} +proc VAL_PF2_ENTRY_TYPE_9 { PARAM_VALUE.C_PF2_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_9} ]"} +proc VAL_PF2_ENTRY_TYPE_10 { PARAM_VALUE.C_PF2_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_10}]"} +proc VAL_PF2_ENTRY_TYPE_11 { PARAM_VALUE.C_PF2_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_11}]"} +proc VAL_PF2_ENTRY_TYPE_12 { PARAM_VALUE.C_PF2_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_12}]"} +proc VAL_PF2_ENTRY_TYPE_13 { PARAM_VALUE.C_PF2_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_TYPE_13}]"} + +proc VAL_PF2_ENTRY_BAR_0 { PARAM_VALUE.C_PF2_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_0} ]"} +proc VAL_PF2_ENTRY_BAR_1 { PARAM_VALUE.C_PF2_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_1} ]"} +proc VAL_PF2_ENTRY_BAR_2 { PARAM_VALUE.C_PF2_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_2} ]"} +proc VAL_PF2_ENTRY_BAR_3 { PARAM_VALUE.C_PF2_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_3} ]"} +proc VAL_PF2_ENTRY_BAR_4 { PARAM_VALUE.C_PF2_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_4} ]"} +proc VAL_PF2_ENTRY_BAR_5 { PARAM_VALUE.C_PF2_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_5} ]"} +proc VAL_PF2_ENTRY_BAR_6 { PARAM_VALUE.C_PF2_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_6} ]"} +proc VAL_PF2_ENTRY_BAR_7 { PARAM_VALUE.C_PF2_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_7} ]"} +proc VAL_PF2_ENTRY_BAR_8 { PARAM_VALUE.C_PF2_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_8} ]"} +proc VAL_PF2_ENTRY_BAR_9 { PARAM_VALUE.C_PF2_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_9} ]"} +proc VAL_PF2_ENTRY_BAR_10 { PARAM_VALUE.C_PF2_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_10} ]"} +proc VAL_PF2_ENTRY_BAR_11 { PARAM_VALUE.C_PF2_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_11} ]"} +proc VAL_PF2_ENTRY_BAR_12 { PARAM_VALUE.C_PF2_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_12} ]"} +proc VAL_PF2_ENTRY_BAR_13 { PARAM_VALUE.C_PF2_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_BAR_13} ]"} + +proc VAL_PF2_ENTRY_ADDR_0 { PARAM_VALUE.C_PF2_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_0} ]"} +proc VAL_PF2_ENTRY_ADDR_1 { PARAM_VALUE.C_PF2_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_1} ]"} +proc VAL_PF2_ENTRY_ADDR_2 { PARAM_VALUE.C_PF2_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_2} ]"} +proc VAL_PF2_ENTRY_ADDR_3 { PARAM_VALUE.C_PF2_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_3} ]"} +proc VAL_PF2_ENTRY_ADDR_4 { PARAM_VALUE.C_PF2_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_4} ]"} +proc VAL_PF2_ENTRY_ADDR_5 { PARAM_VALUE.C_PF2_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_5} ]"} +proc VAL_PF2_ENTRY_ADDR_6 { PARAM_VALUE.C_PF2_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_6} ]"} +proc VAL_PF2_ENTRY_ADDR_7 { PARAM_VALUE.C_PF2_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_7} ]"} +proc VAL_PF2_ENTRY_ADDR_8 { PARAM_VALUE.C_PF2_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_8} ]"} +proc VAL_PF2_ENTRY_ADDR_9 { PARAM_VALUE.C_PF2_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_9} ]"} +proc VAL_PF2_ENTRY_ADDR_10 { PARAM_VALUE.C_PF2_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_10} ]"} +proc VAL_PF2_ENTRY_ADDR_11 { PARAM_VALUE.C_PF2_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_11} ]"} +proc VAL_PF2_ENTRY_ADDR_12 { PARAM_VALUE.C_PF2_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_12} ]"} +proc VAL_PF2_ENTRY_ADDR_13 { PARAM_VALUE.C_PF2_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_ADDR_13} ]"} + +proc VAL_PF2_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF2_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF2_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF2_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF2_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF2_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF2_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_0} ]"} +proc VAL_PF2_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_1} ]"} +proc VAL_PF2_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_2} ]"} +proc VAL_PF2_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_3} ]"} +proc VAL_PF2_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_4} ]"} +proc VAL_PF2_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_5} ]"} +proc VAL_PF2_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_6} ]"} +proc VAL_PF2_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_7} ]"} +proc VAL_PF2_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_8} ]"} +proc VAL_PF2_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_9} ]"} +proc VAL_PF2_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_10} ]"} +proc VAL_PF2_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_11} ]"} +proc VAL_PF2_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_12} ]"} +proc VAL_PF2_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF2_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF2_ENTRY_RSVD0_13} ]"} + +proc VAL_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE { PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} {return "[get_property value ${PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE}]"} +proc VAL_PF3_BAR_INDEX { PARAM_VALUE.C_PF3_BAR_INDEX } {return "[get_property value ${PARAM_VALUE.C_PF3_BAR_INDEX}]"} +proc VAL_PF3_LOW_OFFSET { PARAM_VALUE.C_PF3_LOW_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF3_LOW_OFFSET}]"} +proc VAL_PF3_HIGH_OFFSET { PARAM_VALUE.C_PF3_HIGH_OFFSET } {return "[get_property value ${PARAM_VALUE.C_PF3_HIGH_OFFSET}]"} + +proc VAL_PF3_ENTRY_TYPE_0 { PARAM_VALUE.C_PF3_ENTRY_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_0} ]"} +proc VAL_PF3_ENTRY_TYPE_1 { PARAM_VALUE.C_PF3_ENTRY_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_1} ]"} +proc VAL_PF3_ENTRY_TYPE_2 { PARAM_VALUE.C_PF3_ENTRY_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_2} ]"} +proc VAL_PF3_ENTRY_TYPE_3 { PARAM_VALUE.C_PF3_ENTRY_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_3} ]"} +proc VAL_PF3_ENTRY_TYPE_4 { PARAM_VALUE.C_PF3_ENTRY_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_4} ]"} +proc VAL_PF3_ENTRY_TYPE_5 { PARAM_VALUE.C_PF3_ENTRY_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_5} ]"} +proc VAL_PF3_ENTRY_TYPE_6 { PARAM_VALUE.C_PF3_ENTRY_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_6} ]"} +proc VAL_PF3_ENTRY_TYPE_7 { PARAM_VALUE.C_PF3_ENTRY_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_7} ]"} +proc VAL_PF3_ENTRY_TYPE_8 { PARAM_VALUE.C_PF3_ENTRY_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_8} ]"} +proc VAL_PF3_ENTRY_TYPE_9 { PARAM_VALUE.C_PF3_ENTRY_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_9} ]"} +proc VAL_PF3_ENTRY_TYPE_10 { PARAM_VALUE.C_PF3_ENTRY_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_10}]"} +proc VAL_PF3_ENTRY_TYPE_11 { PARAM_VALUE.C_PF3_ENTRY_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_11}]"} +proc VAL_PF3_ENTRY_TYPE_12 { PARAM_VALUE.C_PF3_ENTRY_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_12}]"} +proc VAL_PF3_ENTRY_TYPE_13 { PARAM_VALUE.C_PF3_ENTRY_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_TYPE_13}]"} + +proc VAL_PF3_ENTRY_BAR_0 { PARAM_VALUE.C_PF3_ENTRY_BAR_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_0} ]"} +proc VAL_PF3_ENTRY_BAR_1 { PARAM_VALUE.C_PF3_ENTRY_BAR_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_1} ]"} +proc VAL_PF3_ENTRY_BAR_2 { PARAM_VALUE.C_PF3_ENTRY_BAR_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_2} ]"} +proc VAL_PF3_ENTRY_BAR_3 { PARAM_VALUE.C_PF3_ENTRY_BAR_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_3} ]"} +proc VAL_PF3_ENTRY_BAR_4 { PARAM_VALUE.C_PF3_ENTRY_BAR_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_4} ]"} +proc VAL_PF3_ENTRY_BAR_5 { PARAM_VALUE.C_PF3_ENTRY_BAR_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_5} ]"} +proc VAL_PF3_ENTRY_BAR_6 { PARAM_VALUE.C_PF3_ENTRY_BAR_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_6} ]"} +proc VAL_PF3_ENTRY_BAR_7 { PARAM_VALUE.C_PF3_ENTRY_BAR_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_7} ]"} +proc VAL_PF3_ENTRY_BAR_8 { PARAM_VALUE.C_PF3_ENTRY_BAR_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_8} ]"} +proc VAL_PF3_ENTRY_BAR_9 { PARAM_VALUE.C_PF3_ENTRY_BAR_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_9} ]"} +proc VAL_PF3_ENTRY_BAR_10 { PARAM_VALUE.C_PF3_ENTRY_BAR_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_10} ]"} +proc VAL_PF3_ENTRY_BAR_11 { PARAM_VALUE.C_PF3_ENTRY_BAR_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_11} ]"} +proc VAL_PF3_ENTRY_BAR_12 { PARAM_VALUE.C_PF3_ENTRY_BAR_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_12} ]"} +proc VAL_PF3_ENTRY_BAR_13 { PARAM_VALUE.C_PF3_ENTRY_BAR_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_BAR_13} ]"} + +proc VAL_PF3_ENTRY_ADDR_0 { PARAM_VALUE.C_PF3_ENTRY_ADDR_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_0} ]"} +proc VAL_PF3_ENTRY_ADDR_1 { PARAM_VALUE.C_PF3_ENTRY_ADDR_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_1} ]"} +proc VAL_PF3_ENTRY_ADDR_2 { PARAM_VALUE.C_PF3_ENTRY_ADDR_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_2} ]"} +proc VAL_PF3_ENTRY_ADDR_3 { PARAM_VALUE.C_PF3_ENTRY_ADDR_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_3} ]"} +proc VAL_PF3_ENTRY_ADDR_4 { PARAM_VALUE.C_PF3_ENTRY_ADDR_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_4} ]"} +proc VAL_PF3_ENTRY_ADDR_5 { PARAM_VALUE.C_PF3_ENTRY_ADDR_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_5} ]"} +proc VAL_PF3_ENTRY_ADDR_6 { PARAM_VALUE.C_PF3_ENTRY_ADDR_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_6} ]"} +proc VAL_PF3_ENTRY_ADDR_7 { PARAM_VALUE.C_PF3_ENTRY_ADDR_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_7} ]"} +proc VAL_PF3_ENTRY_ADDR_8 { PARAM_VALUE.C_PF3_ENTRY_ADDR_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_8} ]"} +proc VAL_PF3_ENTRY_ADDR_9 { PARAM_VALUE.C_PF3_ENTRY_ADDR_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_9} ]"} +proc VAL_PF3_ENTRY_ADDR_10 { PARAM_VALUE.C_PF3_ENTRY_ADDR_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_10} ]"} +proc VAL_PF3_ENTRY_ADDR_11 { PARAM_VALUE.C_PF3_ENTRY_ADDR_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_11} ]"} +proc VAL_PF3_ENTRY_ADDR_12 { PARAM_VALUE.C_PF3_ENTRY_ADDR_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_12} ]"} +proc VAL_PF3_ENTRY_ADDR_13 { PARAM_VALUE.C_PF3_ENTRY_ADDR_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_ADDR_13} ]"} + +proc VAL_PF3_ENTRY_VERSION_TYPE_0 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_0} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_1 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_1} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_2 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_2} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_3 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_3} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_4 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_4} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_5 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_5} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_6 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_6} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_7 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_7} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_8 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_8} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_9 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_9} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_10 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_10} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_11 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_11} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_12 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_12} ]"} +proc VAL_PF3_ENTRY_VERSION_TYPE_13 { PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_VERSION_TYPE_13} ]"} + +proc VAL_PF3_ENTRY_MAJOR_VERSION_0 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_0} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_1 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_1} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_2 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_2} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_3 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_3} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_4 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_4} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_5 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_5} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_6 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_6} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_7 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_7} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_8 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_8} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_9 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_9} ]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_10 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_10}]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_11 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_11}]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_12 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_12}]"} +proc VAL_PF3_ENTRY_MAJOR_VERSION_13 { PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MAJOR_VERSION_13}]"} + +proc VAL_PF3_ENTRY_MINOR_VERSION_0 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_0} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_1 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_1} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_2 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_2} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_3 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_3} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_4 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_4} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_5 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_5} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_6 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_6} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_7 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_7} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_8 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_8} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_9 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_9} ]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_10 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_10}]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_11 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_11}]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_12 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_12}]"} +proc VAL_PF3_ENTRY_MINOR_VERSION_13 { PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_MINOR_VERSION_13}]"} + +proc VAL_PF3_ENTRY_RSVD0_0 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_0} ]"} +proc VAL_PF3_ENTRY_RSVD0_1 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_1} ]"} +proc VAL_PF3_ENTRY_RSVD0_2 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_2} ]"} +proc VAL_PF3_ENTRY_RSVD0_3 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_3} ]"} +proc VAL_PF3_ENTRY_RSVD0_4 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_4} ]"} +proc VAL_PF3_ENTRY_RSVD0_5 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_5} ]"} +proc VAL_PF3_ENTRY_RSVD0_6 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_6} ]"} +proc VAL_PF3_ENTRY_RSVD0_7 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_7} ]"} +proc VAL_PF3_ENTRY_RSVD0_8 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_8} ]"} +proc VAL_PF3_ENTRY_RSVD0_9 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_9} ]"} +proc VAL_PF3_ENTRY_RSVD0_10 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_10} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_10} ]"} +proc VAL_PF3_ENTRY_RSVD0_11 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_11} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_11} ]"} +proc VAL_PF3_ENTRY_RSVD0_12 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_12} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_12} ]"} +proc VAL_PF3_ENTRY_RSVD0_13 { PARAM_VALUE.C_PF3_ENTRY_RSVD0_13} {return "[get_property value ${PARAM_VALUE.C_PF3_ENTRY_RSVD0_13} ]"} + +proc update_gui_for_PARAM_VALUE.C_NUM_PFS {IPINST PARAM_VALUE.C_NUM_PFS PARAM_VALUE.C_MANUAL} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + set manual [get_property value ${PARAM_VALUE.C_MANUAL}] + if {$manual == 1} { + set_property visible true [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } + + if {$manual == 0} { + set_property visible true [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_MANUAL {IPINST PARAM_VALUE.C_NUM_PFS PARAM_VALUE.C_MANUAL} { + set num_pfs [get_property value ${PARAM_VALUE.C_NUM_PFS}] + set manual [get_property value ${PARAM_VALUE.C_MANUAL}] + if {$manual == 1} { + set_property visible true [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Configuration" -of $IPINST] + } + if {$manual == 1 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Configuration" -of $IPINST] + } + + if {$manual == 0} { + set_property visible true [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF0 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 1} { + set_property visible true [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF1 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 2} { + set_property visible true [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF2 Values" -of $IPINST] + } + if {$manual == 0 && $num_pfs > 3} { + set_property visible true [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_pagespec -name "PF3 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf0_num_slots [get_property value ${PARAM_VALUE.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf0_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 1 Values" -of $IPINST] + } + if {$pf0_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 2 Values" -of $IPINST] + } + if {$pf0_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 3 Values" -of $IPINST] + } + if {$pf0_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 4 Values" -of $IPINST] + } + if {$pf0_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 5 Values" -of $IPINST] + } + if {$pf0_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 6 Values" -of $IPINST] + } + if {$pf0_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 7 Values" -of $IPINST] + } + if {$pf0_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 8 Values" -of $IPINST] + } + if {$pf0_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 9 Values" -of $IPINST] + } + if {$pf0_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 10 Values" -of $IPINST] + } + if {$pf0_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 11 Values" -of $IPINST] + } + if {$pf0_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 12 Values" -of $IPINST] + } + if {$pf0_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF0 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF0 - Table Entry 13 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf1_num_slots [get_property value ${PARAM_VALUE.C_PF1_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf1_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 1 Values" -of $IPINST] + } + if {$pf1_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 2 Values" -of $IPINST] + } + if {$pf1_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 3 Values" -of $IPINST] + } + if {$pf1_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 4 Values" -of $IPINST] + } + if {$pf1_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 5 Values" -of $IPINST] + } + if {$pf1_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 6 Values" -of $IPINST] + } + if {$pf1_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 7 Values" -of $IPINST] + } + if {$pf1_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 8 Values" -of $IPINST] + } + if {$pf1_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 9 Values" -of $IPINST] + } + if {$pf1_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 10 Values" -of $IPINST] + } + if {$pf1_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 11 Values" -of $IPINST] + } + if {$pf1_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 12 Values" -of $IPINST] + } + if {$pf1_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF1 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF1 - Table Entry 13 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf2_num_slots [get_property value ${PARAM_VALUE.C_PF2_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf2_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 1 Values" -of $IPINST] + } + if {$pf2_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 2 Values" -of $IPINST] + } + if {$pf2_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 3 Values" -of $IPINST] + } + if {$pf2_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 4 Values" -of $IPINST] + } + if {$pf2_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 5 Values" -of $IPINST] + } + if {$pf2_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 6 Values" -of $IPINST] + } + if {$pf2_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 7 Values" -of $IPINST] + } + if {$pf2_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 8 Values" -of $IPINST] + } + if {$pf2_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 9 Values" -of $IPINST] + } + if {$pf2_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 10 Values" -of $IPINST] + } + if {$pf2_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 11 Values" -of $IPINST] + } + if {$pf2_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 12 Values" -of $IPINST] + } + if {$pf2_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF2 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF2 - Table Entry 13 Values" -of $IPINST] + } +} + +proc update_gui_for_PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE {IPINST PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE} { + set pf3_num_slots [get_property value ${PARAM_VALUE.C_PF3_NUM_SLOTS_BAR_LAYOUT_TABLE}] + if {$pf3_num_slots > 1} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 1 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 1 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 1 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 1 Values" -of $IPINST] + } + if {$pf3_num_slots > 2} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 2 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 2 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 2 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 2 Values" -of $IPINST] + } + if {$pf3_num_slots > 3} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 3 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 3 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 3 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 3 Values" -of $IPINST] + } + if {$pf3_num_slots > 4} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 4 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 4 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 4 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 4 Values" -of $IPINST] + } + if {$pf3_num_slots > 5} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 5 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 5 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 5 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 5 Values" -of $IPINST] + } + if {$pf3_num_slots > 6} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 6 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 6 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 6 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 6 Values" -of $IPINST] + } + if {$pf3_num_slots > 7} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 7 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 7 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 7 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 7 Values" -of $IPINST] + } + if {$pf3_num_slots > 8} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 8 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 8 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 8 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 8 Values" -of $IPINST] + } + if {$pf3_num_slots > 9} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 9 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 9 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 9 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 9 Values" -of $IPINST] + } + if {$pf3_num_slots > 10} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 10 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 10 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 10 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 10 Values" -of $IPINST] + } + if {$pf3_num_slots > 11} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 11 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 11 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 11 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 11 Values" -of $IPINST] + } + if {$pf3_num_slots > 12} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 12 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 12 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 12 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 12 Values" -of $IPINST] + } + if {$pf3_num_slots > 13} { + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 13 Configuration" -of $IPINST] + set_property visible true [ipgui::get_groupspec -name "PF3 - Table Entry 13 Values" -of $IPINST] + } else { + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 13 Configuration" -of $IPINST] + set_property visible false [ipgui::get_groupspec -name "PF3 - Table Entry 13 Values" -of $IPINST] + } +} + diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/bd/bd.tcl b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/bd/bd.tcl new file mode 100644 index 00000000..76b1672e --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/bd/bd.tcl @@ -0,0 +1,34 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +#==============================================================================# +# Post IP Configuration Procedure +#==============================================================================# + +proc post_config_ip { cell args } { + set ip [get_bd_cells $cell] + set s_axi_intf [get_bd_intf_pins $ip/S_AXI] + + # Set interface as READ_ONLY + set_property CONFIG.READ_WRITE_MODE READ_ONLY $s_axi_intf + set_property CONFIG.READ_WRITE_MODE.VALUE_SRC CONSTANT $s_axi_intf + +} diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/component.xml b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/component.xml new file mode 100644 index 00000000..7aee78d6 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/component.xml @@ -0,0 +1,530 @@ + + + xilinx.com + ip + shell_utils_uuid_rom + 2.0 + + + S_AXI + + + + + + + + + ARADDR + + + S_AXI_ARADDR + + + + + ARREADY + + + S_AXI_ARREADY + + + + + ARVALID + + + S_AXI_ARVALID + + + + + RDATA + + + S_AXI_RDATA + + + + + RREADY + + + S_AXI_RREADY + + + + + RRESP + + + S_AXI_RRESP + + + + + RVALID + + + S_AXI_RVALID + + + + + + S_AXI_signal_reset + + + + + + + RST + + + S_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXI_signal_clock + + + + + + + CLK + + + S_AXI_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + S_AXI_ARESETN + + + FREQ_HZ + 250000000 + + + + + + + S_AXI + + reg0 + 0 + 16 + 32 + register + + + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + viewChecksum + 83d8451f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + d40d867a + + + + + xilinx_miscfiles + Miscellaneous + :vivado.xilinx.com:misc.files + + xilinx_miscfiles_view_fileset + + + + viewChecksum + a3b49e2c + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + d40ac7ba + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + shell_utils_uuid_rom + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 5f2ab460 + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + shell_utils_uuid_rom + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 5f2ab460 + + + + + + + S_AXI_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_ARESETN + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + S_AXI_ARADDR + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + S_AXI_ARVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + S_AXI_ARREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXI_RREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + + C_S_AXI_DATA_WIDTH + 32 + + + C_S_AXI_ADDR_WIDTH + 4 + + + C_MEMORY_INIT + 0 + + + C_XDEVICEFAMILY + no_family + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_xpgui_view_fileset + + xgui/shell_utils_uuid_rom_v2_0.tcl + tclSource + XGUI_VERSION_2 + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_miscfiles_view_fileset + + yml/uuid_rom_csr_reg.yml + unknown + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_utilityxitfiles_view_fileset + + tcl/update_uuid_rom.tcl + tclSource + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_versioninformation_view_fileset + + doc/shell_utils_uuid_rom_v2_0_changelog.txt + text + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd + vhdlSource + CHECKSUM_5f2ab460 + shell_utils_uuid_rom_v2_0_0 + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + + + + + + + + Shell Utility UUID ROM + + + Component_Name + shell_utils_uuid_rom_v2_0 + + + C_INITIAL_UUID + UUID initialization value (128-bit hex string) + 00000000000000000000000000000000 + + + + + + /Shell_Subsystems + + Shell Utility UUID ROM + level_2 + + XPM_MEMORY + + http://www.xilinx.com + 0 + 2023-10-11T08:40:40Z + + + 2023.1 + + + + + + + + + diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/doc/shell_utils_uuid_rom_v2_0_changelog.txt b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/doc/shell_utils_uuid_rom_v2_0_changelog.txt new file mode 100644 index 00000000..f123aada --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/doc/shell_utils_uuid_rom_v2_0_changelog.txt @@ -0,0 +1,84 @@ +2023.1: + * Version 2.0 + * No changes + +2022.2.2: + * Version 2.0 + * No changes + +2022.2.1: + * Version 2.0 + * No changes + +2022.2: + * Version 2.0 + * No changes + +2022.1.2: + * Version 2.0 + * No changes + +2022.1.1: + * Version 2.0 + * No changes + +2022.1: + * Version 2.0 + * No changes + +2021.2.2: + * Version 2.0 + * No changes + +2021.2.1: + * Version 2.0 + * No changes + +2021.2: + * Version 2.0 + * No changes + +2021.1.1: + * Version 2.0 + * No changes + +2021.1: + * Version 2.0 + * No changes + +2020.3: + * Version 2.0 + * No changes + +2020.2.2: + * Version 2.0 + * No changes + +2020.2.1: + * Version 2.0 + * No changes + +2020.2: + * Version 2.0 + * No changes + +2020.1.1: + * Version 2.0 + * No changes + +2020.1: + * Version 2.0 + * S_AXI interface supports READ_ONLY, updates to work with 2020.1 tools + +2019.2.2: + * Version 1.0 + * No changes + +2019.2.1: + * Version 1.0 + * No changes + +2019.2: + * Version 1.0 + * Initial Release + diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd new file mode 100644 index 00000000..02dfb4db --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/hdl/shell_utils_uuid_rom_v2_0_vh_rfs.vhd @@ -0,0 +1,209 @@ +-- (c) Copyright 2022, Advanced Micro Devices, Inc. +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +library xpm; + use xpm.vcomponents.all; + +entity shell_utils_uuid_rom is + generic ( + ------------------------------------------------------------------------ + C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_S_AXI_ADDR_WIDTH : integer range 3 to 9 := 4; + C_MEMORY_INIT : string := "0"; + C_XDEVICEFAMILY : string := "no_family" + ------------------------------------------------------------------------ + ); + port ( + ------------------------------------------------------------------------ + -- Processor AXI Interface + ------------------------------------------------------------------------ + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + +end shell_utils_uuid_rom; + +architecture rtl of shell_utils_uuid_rom is + + ------------------------------------------------------------------------------- + -- Constant Declarations + ------------------------------------------------------------------------------- + + -- Constants for AXI4-Lite. + constant ZEROES : std_logic_vector(0 to 31) := (others => '0'); + constant ONES : std_logic_vector(0 to 31) := (others => '1'); + + constant C_FAMILY : string := C_XDEVICEFAMILY; + + constant REG_BASEADDR : std_logic_vector := X"00000000"; + + impure function makemask (Width: INTEGER) return std_logic_vector is + variable retv: std_logic_vector (31 downto 0) := (others => '0'); + begin + for i in (Width - 1) downto 0 loop + retv(i) := '1'; + end loop; + return retv; + end function; + + constant REG_HIGHADDR : std_logic_vector(0 to 31) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( + ZEROES(0 to 31) & REG_BASEADDR, + ZEROES(0 to 31) & REG_HIGHADDR + ); + + constant C_ARD_IDX_REGS : integer := 0; + + constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( + C_ARD_IDX_REGS => 1 + ); + + constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := makemask(C_S_AXI_ADDR_WIDTH); + + constant C_USE_WSTRB : integer := 0; + + constant C_DPHASE_TIMEOUT : integer := 3; + + constant XPM_ADDR_WIDTH : integer := C_S_AXI_ADDR_WIDTH - 2; + constant XPM_MEMORY_SIZE : integer := (2 ** XPM_ADDR_WIDTH) * C_S_AXI_DATA_WIDTH; + + attribute DONT_TOUCH : string; + attribute DONT_TOUCH of xpm_memory_spram_inst: label is "TRUE"; + + ------------------------------------------------------------------------------- + -- SIGNALS + ------------------------------------------------------------------------------- + signal Bus2IP_Clk : std_logic := '0'; + signal Bus2IP_Resetn : std_logic; + signal Bus2IP_Addr : std_logic_vector((C_S_AXI_ADDR_WIDTH - 1) downto 0); + signal Bus2IP_RNW : std_logic; + signal Bus2IP_BE : std_logic_vector(((C_S_AXI_DATA_WIDTH / 8) - 1) downto 0); + signal Bus2IP_CS : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length) / 2 - 1) downto 0); + signal Bus2IP_RdCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); + signal Bus2IP_WrCE : std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); + signal Bus2IP_Data : std_logic_vector((C_S_AXI_DATA_WIDTH - 1) downto 0); + signal IP2Bus_Data : std_logic_vector((C_S_AXI_DATA_WIDTH - 1) downto 0); + signal IP2Bus_WrAck : std_logic := '0'; + signal IP2Bus_RdAck : std_logic := '0'; + signal IP2Bus_Error : std_logic := '0'; + +begin + +axi_lite_ipif_1 : entity axi_lite_ipif_v3_0_4.axi_lite_ipif + generic map( + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, + C_USE_WSTRB => C_USE_WSTRB, + C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, + C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, + C_FAMILY => C_FAMILY) + port map( + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => (others => '0'), + S_AXI_AWVALID => '0', + S_AXI_AWREADY => open, + S_AXI_WDATA => (others => '0'), + S_AXI_WSTRB => (others => '0'), + S_AXI_WVALID => '0', + S_AXI_WREADY => open, + S_AXI_BRESP => open, + S_AXI_BVALID => open, + S_AXI_BREADY => '0', + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + Bus2IP_Clk => Bus2IP_Clk, + Bus2IP_Resetn => Bus2IP_Resetn, + Bus2IP_Addr => Bus2IP_Addr, + Bus2IP_RNW => Bus2IP_RNW, + Bus2IP_BE => Bus2IP_BE, + Bus2IP_CS => Bus2IP_CS, + Bus2IP_RdCE => Bus2IP_RdCE, + Bus2IP_WrCE => Bus2IP_WrCE, + Bus2IP_Data => Bus2IP_Data, + IP2Bus_Data => IP2Bus_Data, + IP2Bus_WrAck => IP2Bus_WrAck, + IP2Bus_RdAck => IP2Bus_RdAck, + IP2Bus_Error => IP2Bus_Error); + +xpm_memory_spram_inst : xpm_memory_spram + generic map ( + ADDR_WIDTH_A => XPM_ADDR_WIDTH, + AUTO_SLEEP_TIME => 0, + BYTE_WRITE_WIDTH_A => C_S_AXI_DATA_WIDTH, + CASCADE_HEIGHT => 0, + ECC_MODE => "no_ecc", + MEMORY_INIT_FILE => "none", + MEMORY_INIT_PARAM => C_MEMORY_INIT, + MEMORY_OPTIMIZATION => "true", + MEMORY_PRIMITIVE => "distributed", + MEMORY_SIZE => XPM_MEMORY_SIZE, + MESSAGE_CONTROL => 0, + READ_DATA_WIDTH_A => C_S_AXI_DATA_WIDTH, + READ_LATENCY_A => 1, + READ_RESET_VALUE_A => "0", + RST_MODE_A => "SYNC", + SIM_ASSERT_CHK => 0, + USE_MEM_INIT => 1, + WAKEUP_TIME => "disable_sleep", + WRITE_DATA_WIDTH_A => C_S_AXI_DATA_WIDTH, + WRITE_MODE_A => "read_first" + ) + port map ( + dbiterra => open, + douta => IP2Bus_Data, + sbiterra => open, + addra => Bus2IP_Addr(C_S_AXI_ADDR_WIDTH-1 downto 2), + clka => Bus2IP_Clk, + ena => Bus2IP_CS(0), + injectdbiterra => '0', + injectsbiterra => '0', + regcea => '0', + rsta => '0', + sleep => '0', + wea => Bus2IP_WrCE(0 downto 0), + dina => Bus2IP_Data + ); + +end architecture rtl; + + diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/tcl/update_uuid_rom.tcl b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/tcl/update_uuid_rom.tcl new file mode 100644 index 00000000..54fa2194 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/tcl/update_uuid_rom.tcl @@ -0,0 +1,231 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +proc conv_hex_bin { s } { + binary scan [binary format H* $s] B* x + return $x +} + +proc conv_bin_hex { s } { + binary scan [binary format B4 $s] H1 x + return $x +} + +proc update_uuid_rom {uuid cell} { + + puts "\nINFO: Updaing UUID ROM with UUID: ${uuid}" + puts "INFO: Updating UUID ROM cell: ${cell}\n" + + # validate UUID format + if {![string is xdigit ${uuid}]} { + + puts "ERROR: UUID should be a 128 bit hex value" + puts " Found ${uuid}" + puts "Aborting UUID update" + return 1 + + } + + # validate UUID length + set uuid_length [string length ${uuid}] + + if {${uuid_length} != 32} { + + puts "ERROR: UUID should be 128 bits. Found [expr 4 * ${uuid_length}] bits" + puts " ${uuid}" + puts "Aborting UUID update" + return 1 + + } + + # validate cell name + if {[get_cells -quiet ${cell}] eq ""} { + + puts "ERROR: Specified UUID cell does not exist in the design" + puts " ${cell}" + puts "Aborting UUID update" + return 1 + + } + + # get path to base of the UUID memory element + set filter "PRIMITIVE_TYPE == CLB.LUTRAM.RAM32X1S && PRIMITIVE_LEVEL == \"MACRO\" && NAME =~ ${cell}*0_0" + set uuid_rom_cell_base [string trimright [get_cells -hierarchical -filter ${filter}] 0_] + + if {${uuid_rom_cell_base} eq ""} { + + puts "ERROR: Correct UUID ROM structure not detected. Please check the CLB.LUTRAM.RAM32X1S memory elements exist in the implemented design" + puts "Aborting UUID update" + return 1 + + } + + # split uuid into 4x32 bit hex strings + set uuid_split_hex {} + for {set i 0} {$i < 4} {incr i} { + lappend uuid_split_hex [string range ${uuid} [expr 8 * ${i}] [expr (8 * ${i}) + 7 ]] + } + + + # convert to 4x32 bit binary strings + set uuid_split_bin {} + foreach uuid_split_hex_item ${uuid_split_hex} { + + lappend uuid_split_bin [conv_hex_bin ${uuid_split_hex_item}] + + } + + # produce the muxed 32x4 bit binary string from the input 4x32 bit string + set uuid_muxed_bin {} + for {set j 0} {$j < 32} {incr j} { + + set temp "" + for {set k 0} {$k < 4} {incr k} { + + append temp [string index [lindex ${uuid_split_bin} $k] [expr 31 - $j]] + + } + lappend uuid_muxed_bin ${temp} + } + + # convert to 32x4 bit hex strings + set uuid_muxed_hex {} + foreach uuid_muxed_bin_item ${uuid_muxed_bin} { + + lappend uuid_muxed_hex [conv_bin_hex ${uuid_muxed_bin_item}] + + } + + #puts "DEBUG: UUID length (chars): ${uuid_length}" + #puts "DEBUG: UUID split (hex): ${uuid_split_hex}" + #puts "DEBUG: UUID split (bin): ${uuid_split_bin}" + #puts "DEBUG: UUID muxed (bin): ${uuid_muxed_bin}" + #puts "DEBUG: UUID muxed (hex): ${uuid_muxed_hex}" + #puts "DEBUG: UUID cell base: ${uuid_rom_cell_base}" + + # update INIT properties on the UUID ROM sub-memories + set m 0 + foreach uuid_muxed_hex_item ${uuid_muxed_hex} { + + set uuid_rom_sub_cell [get_cells ${uuid_rom_cell_base}_${m}_${m}] + if {${uuid_rom_sub_cell} eq ""} { + + puts "ERROR: UUID ROM sub-cell not found. Please check it exists in the implemented design" + puts " ${uuid_rom_cell_base}_${m}_${m}" + puts "Aborting UUID update" + return 1 + + } + + puts "INFO: Setting INIT=000000${uuid_muxed_hex_item} on cell ${uuid_rom_sub_cell}" + set_property INIT 32'h00000000${uuid_muxed_hex_item} ${uuid_rom_sub_cell} + incr m + + } + puts "\nINFO: UUID ROM successfully updated\n" + return 0 + +} + +proc read_uuid_rom {cell} { + + puts "\nINFO: Reading UUID ROM cell: ${cell}\n" + + # validate cell name + if {[get_cells -quiet ${cell}] eq ""} { + + puts "ERROR: Specified UUID cell does not exist in the design" + puts " ${cell}" + puts "Aborting UUID read" + return -code error "ERROR: Specified UUID cell does not exist in the design" + + } + + # get path to base of the UUID memory element + set filter "PRIMITIVE_TYPE == CLB.LUTRAM.RAM32X1S && PRIMITIVE_LEVEL == \"MACRO\" && NAME =~ ${cell}*0_0" + set uuid_rom_cell_base [string trimright [get_cells -hierarchical -filter ${filter}] 0_] + + if {${uuid_rom_cell_base} eq ""} { + + puts "ERROR: Correct UUID ROM structure not detected. Please check the CLB.LUTRAM.RAM32X1S memory elements exist in the implemented design" + puts "Aborting UUID read" + return -code error "ERROR: Correct UUID ROM structure not detected. Please check the CLB.LUTRAM.RAM32X1S memory elements exist in the implemented design" + + } + + # read INIT properties from the UUID ROM sub-memories + for {set i 0} {$i < 32} {incr i} { + + set uuid_rom_sub_cell [get_cells ${uuid_rom_cell_base}_${i}_${i}] + if {${uuid_rom_sub_cell} eq ""} { + + puts "ERROR: UUID ROM sub-cell not found. Please check it exists in the implemented design" + puts " ${uuid_rom_cell_base}_${i}_${i}" + puts "Aborting UUID read" + return -code error "ERROR: UUID ROM sub-cell not found. Please check it exists in the implemented design" + + } + + set sub_cell_init [get_property INIT ${uuid_rom_sub_cell}] + puts "INFO: Read INIT=${sub_cell_init} on cell ${uuid_rom_sub_cell}" + lappend uuid_inits $sub_cell_init + + } + + # construct the binary representation of each dword + for {set i 0} {$i < 32} {incr i} { + + set hex_per_bit [string range [lindex $uuid_inits $i] 10 11] + set bin_per_bit [conv_hex_bin $hex_per_bit] + + lappend dw0 [string index $bin_per_bit 7] + lappend dw1 [string index $bin_per_bit 6] + lappend dw2 [string index $bin_per_bit 5] + lappend dw3 [string index $bin_per_bit 4] + + } + + lappend bin_dwords $dw3 $dw2 $dw1 $dw0 + + # construct the hex representation of each dword - bit slice and rotate + foreach dword $bin_dwords { + set dw_hex "" + for {set i 7} {$i >= 0} {incr i -1} { + set nibble "" + for {set j 3} {$j >= 0} {incr j -1} { + append nibble [lindex $dword [expr $i * 4 + $j]] + } + append dw_hex [conv_bin_hex $nibble] + } + lappend hex_dwords $dw_hex + } + + # construct the final hex representation of the full UUID + set uuid "" + foreach dword $hex_dwords { + append uuid $dword + } + + puts "\nINFO: Read UUID ROM value: ${uuid}\n" + + return $uuid + +} diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/xgui/shell_utils_uuid_rom_v2_0.tcl b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/xgui/shell_utils_uuid_rom_v2_0.tcl new file mode 100644 index 00000000..5f3a70b7 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/xgui/shell_utils_uuid_rom_v2_0.tcl @@ -0,0 +1,114 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# Definitional proc to organize widgets for parameters. + +proc init_gui { IPINST } { + + ipgui::add_param $IPINST -name "Component_Name" + + #---> Adding Page -----------------------------------------------------------------------------------------------------------------------# + + set General_Config [ipgui::add_page $IPINST -name "General Configuration"] + + set C_INITIAL_UUID [ipgui::add_param $IPINST -name C_INITIAL_UUID -parent $General_Config] + set_property tooltip "Set a default 128-bit UUID to be initialized in the ROM during synthesis" $C_INITIAL_UUID + +} + +#==========================================================================================================================================# +# Parameter Validation Procedures +#==========================================================================================================================================# + +# Validate the entered UUID + +proc validate_PARAM_VALUE.C_INITIAL_UUID {PARAM_VALUE.C_INITIAL_UUID IPINST} { + + # Verify the UUID string is 32 characters in length + set uuid_length [string length [get_property value ${PARAM_VALUE.C_INITIAL_UUID}]] + + if {[expr $uuid_length != 32]} { + set_property errmsg "UUID string length of $uuid_length is not equal to 32" [ipgui::get_paramspec -name C_INITIAL_UUID -of $IPINST ] + return false + } + + # Verify the UUID string is valid hexadecimal + return [RangeCheck4HexDec C_INITIAL_UUID [get_property value ${PARAM_VALUE.C_INITIAL_UUID}] 00000000000000000000000000000000 FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF $IPINST] + +} + +#==========================================================================================================================================# +# Parameter Update Procedures +#==========================================================================================================================================# + +proc update_MODELPARAM_VALUE.C_MEMORY_INIT { MODELPARAM_VALUE.C_MEMORY_INIT PARAM_VALUE.C_INITIAL_UUID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + + set uuid "" + set uuid_chars [split [get_property value ${PARAM_VALUE.C_INITIAL_UUID}] {}] + + # Split the UUID into dword's and rotate to match the XPM_MEM string init format + for {set dw 3} {$dw >= 0} {incr dw -1} { + set dword "" + for {set n 0} {$n < 8} {incr n} { + append dword [lindex $uuid_chars [expr $dw * 8 + $n]] + } + if {[expr $dw == 3]} { + append uuid $dword + } else { + append uuid "," $dword + } + } + set_property value $uuid ${MODELPARAM_VALUE.C_MEMORY_INIT} + +} + +#==========================================================================================================================================# +# Helper Procedures +#==========================================================================================================================================# + +# Proc to validate that the entered Hex string value is within the correct range +proc RangeCheck4HexDec {param paramValue MinValue MaxValue IPINST} { + + if { [regexp -all {[a-fA-F0-9]} $paramValue] != [ string length $paramValue ]} { + + set_property errmsg "Entered invalid Hexadecimal value $paramValue" [ipgui::get_paramspec -name $param -of $IPINST ] + return false + + } + + if {$paramValue == ""} { + + set_property errmsg "Entered invalid Hexadecimal value $paramValue" [ipgui::get_paramspec -name $param -of $IPINST ] + return false + + } + + if {[expr 0x$MaxValue ] < [expr 0x$paramValue ] || [expr 0x$paramValue ] < [expr 0x$MinValue]} { + + set_property errmsg "Entered Hexadecimal value $paramValue is out of range." [ipgui::get_paramspec -name $param -of $IPINST ] + return false + + } + + return true + +} diff --git a/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/yml/uuid_rom_csr_reg.yml b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/yml/uuid_rom_csr_reg.yml new file mode 100644 index 00000000..3d40a8d7 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/shell_utils_uuid_rom_v2_0/yml/uuid_rom_csr_reg.yml @@ -0,0 +1,55 @@ +# (c) Copyright 2022, Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +############################################################ + +# ------------------------------------------------------------------- +# UUID ROM IP - Register Definition File +# ------------------------------------------------------------------- +# +# This file defines the discrete registers that are instantiated in +# the UUID ROM RTL module. +# +--- +blockdef: uuid_rom_csr_reg +width: 32 +registers: +################ UUID Registers ################ + +- reg: UUID[4] @ 0x0 + summary: UUID Registers + access: RO + step: 4 + i: UUID ROM + fields: + - field: UUID[31:0] + i: | + This register table contains the 128-bit UUID + UUID_0: Index 0 of UUID + Data[31:0] - UUID[31:0] + + UUID_1: Index 1 of UUID + Data[31:0] - UUID[63:32] + + UUID_2: Index 2 of UUID + Data[31:0] - UUID[95:64] + + UUID_3: Index 3 of UUID + Data[31:0] - UUID[127:96] + diff --git a/linker/slashkit/resources/base/iprepo/traffic_producer/.gitignore b/linker/slashkit/resources/base/iprepo/traffic_producer/.gitignore new file mode 100644 index 00000000..0b542583 --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/traffic_producer/.gitignore @@ -0,0 +1 @@ +ip/ diff --git a/examples/04_freq/hls/Makefile b/linker/slashkit/resources/base/iprepo/traffic_producer/Makefile similarity index 83% rename from examples/04_freq/hls/Makefile rename to linker/slashkit/resources/base/iprepo/traffic_producer/Makefile index 5e008237..e4780e56 100644 --- a/examples/04_freq/hls/Makefile +++ b/linker/slashkit/resources/base/iprepo/traffic_producer/Makefile @@ -18,17 +18,11 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -TARGET=ip -DEVICE=xcv80-lsva4737-2MHP-e-S +.PHONY: all clean -VADD_BUILD_DIR=build_vadd.$(DEVICE) - -all: $(VADD_BUILD_DIR) - -$(VADD_BUILD_DIR): - if [ ! -d "$(VADD_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) vadd; \ - fi +all: + v++ -c --mode hls --config traffic_producer.cfg --work_dir ip + vitis-run --mode hls --package --config traffic_producer.cfg --work_dir ip clean: - rm -rf $(VADD_BUILD_DIR) vitis_hls.log \ No newline at end of file + rm -rf ip/ .Xil *.json \ No newline at end of file diff --git a/linker/slashkit/resources/base/iprepo/traffic_producer/traffic_producer.cfg b/linker/slashkit/resources/base/iprepo/traffic_producer/traffic_producer.cfg new file mode 100644 index 00000000..52b0a43d --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/traffic_producer/traffic_producer.cfg @@ -0,0 +1,11 @@ +part=xcv80-lsva4737-2MHP-e-S + +[hls] +flow_target=vivado + +syn.top=traffic_producer +syn.file=traffic_producer.cpp +clock=2ns + +package.output.format=ip_catalog +package.output.syn=false diff --git a/linker/slashkit/resources/base/iprepo/traffic_producer/traffic_producer.cpp b/linker/slashkit/resources/base/iprepo/traffic_producer/traffic_producer.cpp new file mode 100644 index 00000000..2f81dd8d --- /dev/null +++ b/linker/slashkit/resources/base/iprepo/traffic_producer/traffic_producer.cpp @@ -0,0 +1,35 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +#include "ap_axi_sdata.h" +#include "ap_int.h" +#include "hls_stream.h" + +#define DWIDTH 512 +#define TDWIDTH 3 + +typedef ap_axiu pkt; + +void traffic_producer(hls::stream &axis_out, + ap_uint<32> flits, + ap_uint dest){ + +#pragma HLS INTERFACE mode=axis port=axis_out depth=16 +#pragma HLS INTERFACE mode=s_axilite port=dest bundle=control +#pragma HLS INTERFACE mode=s_axilite port=flits bundle=control +#pragma HLS INTERFACE mode=s_axilite port=return bundle=control + + pkt axi_word; +generator: + for(unsigned int i=0; i< flits; i++){ + #pragma HLS PIPELINE II=1 + for(unsigned int j=0; j 0}] + set have_bd_service [file exists $bd_service_dir] + set have_bd_slash [file exists $bd_slash_dir] + + if {$have_impl || $have_bd_service || $have_bd_slash} { + puts "Removing stale design for project '$project_name' ..." + + set bd_files {} + set service_bd [file normalize [file join $bd_service_dir "service_layer_${project_name}.bd"]] + if {[file exists $service_bd]} { + lappend bd_files $service_bd + } + + set slash_bd [file normalize [file join $bd_slash_dir "slash_${project_name}.bd"]] + if {[file exists $slash_bd]} { + lappend bd_files $slash_bd + } + + if {[llength $bd_files] > 0} { + remove_files $bd_files + } + + if {[file exists $bd_service_dir]} { + file delete -force $bd_service_dir + } + + set gen_service_dir [file normalize [file join $project_build_dir "slash.gen" "sources_1" "bd" "service_layer_${project_name}"]] + if {[file exists $gen_service_dir]} { + file delete -force $gen_service_dir + } + + if {[file exists $bd_slash_dir]} { + file delete -force $bd_slash_dir + } + + set gen_slash_dir [file normalize [file join $project_build_dir "slash.gen" "sources_1" "bd" "slash_${project_name}"]] + if {[file exists $gen_slash_dir]} { + file delete -force $gen_slash_dir + } + + if {$have_impl} { + delete_runs "${project_name}_impl_1" + } + } else { + puts "INFO: No stale design artifacts found for project '$project_name'." + } +} + +if {[info exists ::argv0] && [file normalize [info script]] eq [file normalize $::argv0]} { + if {[llength $argv] < 1} { + puts "INFO: No project_name provided via -tclargs; defaulting to 'user'." + set project_name "user" + } else { + set project_name [lindex $argv 0] + } + set src_dir "" + if {[llength $argv] >= 2} { + set src_dir [lindex $argv 1] + } + set design_name "slash" + if {[llength $argv] >= 3} { + set design_name [lindex $argv 2] + } + clean_project $project_name $src_dir $design_name +} diff --git a/linker/slashkit/resources/base/scripts/create_project.tcl b/linker/slashkit/resources/base/scripts/create_project.tcl new file mode 100644 index 00000000..9fd9b3b1 --- /dev/null +++ b/linker/slashkit/resources/base/scripts/create_project.tcl @@ -0,0 +1,115 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set src_dir [file dirname [file normalize [info script]]] +set cwd [pwd] + +if {[llength $argv] < 1} { + puts "INFO: No project_name provided via -tclargs; defaulting to 'user'." + set project_name "user" +} else { + set project_name [lindex $argv 0] +} + +# Optional IP repository path(s) via -tclargs; defaults to ../iprepo +set default_iprepos [file normalize [file join $src_dir ".." "iprepo"]] +set iprepos $default_iprepos + +# Optional action via -tclargs: create | build | all (default: all) +set action "all" + +if {[llength $argv] >= 2} { + set arg1 [lindex $argv 1] + if {[llength $argv] == 2} { + if {[lsearch -exact {create build all} $arg1] >= 0} { + set action $arg1 + } else { + set iprepos $arg1 + } + } else { + set iprepos $arg1 + } +} + +if {[llength $argv] >= 3} { + set action [lindex $argv 2] +} + +set do_create 0 +set do_build 0 +switch -exact -- $action { + "create" { set do_create 1 } + "build" { set do_build 1 } + "all" { set do_create 1; set do_build 1 } + default { error "Unknown action '$action'. Expected: create, build, or all." } +} + +# Design/BD names +set design_name "slash" +set bd_slash_name "slash_${project_name}" +set bd_service_layer_name "service_layer_${project_name}" + +puts "PROJECT: $project_name" +puts "IP REPOS: $iprepos" +puts "ACTION: $action" +puts "BUILD DIR: $cwd" + + +set proj_exists [file normalize [file join $cwd "${design_name}.xpr"]] +if {![file exists $proj_exists]} { + if {!$do_create} { + error "Project not found at $proj_exists. Run with action 'create' first." + } + lappend iprepos $default_iprepos + puts "INFO: Creating new project '$design_name' in '$cwd' ..." + create_project $design_name $cwd -part xcv80-lsva4737-2MHP-e-S -force + set_property ip_repo_paths $iprepos [current_project] + update_ip_catalog + + # Base shell / containers + source [file normalize [file join $src_dir "slash_base.tcl"]] + source [file normalize [file join $src_dir "service_layer.tcl"]] + source [file normalize [file join $src_dir "top.tcl"]] + source [file normalize [file join $src_dir "enable_dfx_bdc.tcl"]] + + # Wrapper / XDC / build + source [file normalize [file join $src_dir "make_wrapper.tcl"]] + source [file normalize [file join $src_dir "add_constraints.tcl"]] +} else { + puts "INFO: Project already exists; opening '$proj_exists'." + open_project [file normalize [file join $cwd "slash.xpr"]] + if {$do_create} { + set repos [get_property ip_repo_paths [current_project]] + set iprepos [concat $iprepos $repos] + set_property ip_repo_paths $iprepos [current_project] + update_ip_catalog + puts "INFO: Project already exists; create step is a no-op for base-image flow." + } +} + +if {$do_build} { + source [file normalize [file join $src_dir "build_project.tcl"]] + build_project $project_name + puts "INFO: Project build complete." +} elseif {$do_create} { + puts "INFO: Project creation complete (build skipped)." +} else { + puts "INFO: Build skipped." +} diff --git a/linker/slashkit/resources/base/scripts/enable_dfx_bdc.tcl b/linker/slashkit/resources/base/scripts/enable_dfx_bdc.tcl new file mode 100644 index 00000000..47672b67 --- /dev/null +++ b/linker/slashkit/resources/base/scripts/enable_dfx_bdc.tcl @@ -0,0 +1,30 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +current_bd_design [get_bd_designs top] + +set_property -dict [list CONFIG.ENABLE_DFX {true}] [get_bd_cells slash] +set_property -dict [list CONFIG.ENABLE_DFX {true}] [get_bd_cells service_layer] + +set_property -dict [list CONFIG.LOCK_PROPAGATE {true}] [get_bd_cells slash] +set_property -dict [list CONFIG.LOCK_PROPAGATE {true}] [get_bd_cells service_layer] + +validate_bd_design +save_bd_design diff --git a/linker/slashkit/resources/base/scripts/make_wrapper.tcl b/linker/slashkit/resources/base/scripts/make_wrapper.tcl new file mode 100644 index 00000000..cce6328c --- /dev/null +++ b/linker/slashkit/resources/base/scripts/make_wrapper.tcl @@ -0,0 +1,24 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_files -norecurse [make_wrapper -files [get_files "top.bd"] -top] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 +set_property top top_wrapper [current_fileset] diff --git a/linker/slashkit/resources/base/scripts/service_layer.tcl b/linker/slashkit/resources/base/scripts/service_layer.tcl new file mode 100644 index 00000000..b71b4c12 --- /dev/null +++ b/linker/slashkit/resources/base/scripts/service_layer.tcl @@ -0,0 +1,1833 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2025.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source service_layer_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# dcmac_syncer_reset, dcmac_syncer_reset, clock_to_clock_bus, clock_to_serdes, clock_to_clock_bus, clock_to_serdes, clock_to_serdes, dcmac200g_ctl_port, clock_to_clock_bus, clock_to_serdes, axis_seg_to_unseg_converter, axis_unseg_to_seg_converter, dcmac_syncer_reset, dcmac_syncer_reset, clock_to_clock_bus, clock_to_serdes, clock_to_clock_bus, clock_to_serdes, clock_to_serdes, dcmac200g_ctl_port, clock_to_clock_bus, clock_to_serdes, axis_seg_to_unseg_converter, axis_unseg_to_seg_converter + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcv80-lsva4737-2MHP-e-S +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name service_layer + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axis_noc:1.0\ +xilinx.com:hls:hbm_bandwidth:1.0\ +xilinx.com:ip:axi_noc:*\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:hls:traffic_producer:1.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:clk_wizard:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:axis_dwidth_converter:1.1\ +xilinx.com:ip:axis_data_fifo:2.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:xlslice:1.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:inline_hdl:ilreduced_logic:1.0\ +xilinx.com:ip:dcmac:3.0\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:gt_quad_base:1.1\ +xilinx.com:ip:bufg_gt:1.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 0 +if { $bCheckModules == 1 } { + set list_check_mods "\ +dcmac_syncer_reset\ +dcmac_syncer_reset\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_serdes\ +dcmac200g_ctl_port\ +clock_to_clock_bus\ +clock_to_serdes\ +axis_seg_to_unseg_converter\ +axis_unseg_to_seg_converter\ +dcmac_syncer_reset\ +dcmac_syncer_reset\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_clock_bus\ +clock_to_serdes\ +clock_to_serdes\ +dcmac200g_ctl_port\ +clock_to_clock_bus\ +clock_to_serdes\ +axis_seg_to_unseg_converter\ +axis_unseg_to_seg_converter\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + +proc add_dcmac_inst {} { + + set DCMAC0_ENABLED 1 + set DCMAC1_ENABLED 1 + + ## Each DCMAC can support 2 QSFP56 interfaces + ## select how many QSFP56 you want for each DCMAC, provided they are enabled + + ## Setup number of QSFP56 interfaces for DCMAC0 + set DUAL_QSFP_DCMAC0 0 + + ## Setup number of QSFP56 interfaces for DCMAC1 + set DUAL_QSFP_DCMAC1 0 + + # Create network hierarchy + if { ${DCMAC0_ENABLED} == "1" } { + create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} + } + if { ${DCMAC1_ENABLED} == "1" } { + create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} + } +} +set current_file [file normalize [info script]] +set current_dir [file normalize ${current_file}] +set dcmac_base [file normalize [file join $current_dir .. .. .. dcmac]] + +# Absolute paths (normalized) +set ::slash_dcmac_tcl [file join $dcmac_base tcl dcmac.tcl] +set ::slash_dcmac_hdl [file join $dcmac_base hdl] + +# Source the DCMAC Tcl helpers +source $::slash_dcmac_tcl + +# Import DCMAC source files +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl axis_seg_to_unseg_converter.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl clock_to_clock_bus.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl dcmac200g_ctl_port.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl serdes_clock.v] +import_files -fileset sources_1 -norecurse [file join $::slash_dcmac_hdl syncer_reset.v] + +# --- DCMAC creation variables --- +set DCMAC0_ENABLED 1 +set DCMAC1_ENABLED 1 +set DUAL_QSFP_DCMAC0 0 +set DUAL_QSFP_DCMAC1 0 + + +proc create_root_design { parentCell } { + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M_DCMAC_INIS0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS0 + + set M_DCMAC_INIS1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS1 + + set M_DCMAC_INIS2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS2 + + set M_DCMAC_INIS3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS3 + + set M_DCMAC_INIS4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS4 + + set M_DCMAC_INIS5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS5 + + set M_DCMAC_INIS6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS6 + + set M_DCMAC_INIS7 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS7 + + set M_VIRT_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_0 + + set M_VIRT_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_1 + + set M_VIRT_2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_2 + + set M_VIRT_3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_VIRT_3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_VIRT_3 + + set S_DCMAC_INIS0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS0 + + set S_DCMAC_INIS1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS1 + + set S_DCMAC_INIS2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS2 + + set S_DCMAC_INIS3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS3 + + set S_DCMAC_INIS4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS4 + + set S_DCMAC_INIS5 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS5 + + set S_DCMAC_INIS6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS6 + + set S_DCMAC_INIS7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS7 + + set SL2NOC_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_0 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_0 + + set SL2NOC_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_1 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_1 + + set SL2NOC_2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_2 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_2 + + set SL2NOC_3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_3 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_3 + + set SL2NOC_4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_4 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_4 + + set SL2NOC_5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_5 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_5 + + set SL2NOC_6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_6 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_6 + + set SL2NOC_7 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL2NOC_7 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL2NOC_7 + + set qsfp1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1_4x ] + + set qsfp3_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp3_4x ] + + set S_AXILITE_INI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_AXILITE_INI ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_AXILITE_INI + + set S_VIRT_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_VIRT_00 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_VIRT_00 + + set S_VIRT_01 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_VIRT_01 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_VIRT_01 + + set S_VIRT_02 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_VIRT_02 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_VIRT_02 + + set S_VIRT_03 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_VIRT_03 ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_VIRT_03 + + set S_QDMA_SLV_BRIDGE [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_QDMA_SLV_BRIDGE ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_QDMA_SLV_BRIDGE + + set M_QDMA_SLV_BRIDGE [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M_QDMA_SLV_BRIDGE ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {driver} \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_QDMA_SLV_BRIDGE + + set qsfp0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0_4x ] + + set qsfp0_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_322mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp0_322mhz + + set qsfp2_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp2_4x ] + + set qsfp2_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp2_322mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp2_322mhz + + + # Create ports + set service_clk [ create_bd_port -dir I -type clk -freq_hz 300000000 service_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {arstn} \ + CONFIG.CLK_DOMAIN {bd_4885_pspmc_0_0_pl0_ref_clk} \ + ] $service_clk + set arstn [ create_bd_port -dir I -type rst arstn ] + + # Create instance: dummy_noc_0, and set properties + set dummy_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_0/aclk0] + + # Create instance: dummy_noc_1, and set properties + set dummy_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_1/aclk0] + + # Create instance: dummy_noc_2, and set properties + set dummy_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_2/aclk0] + + # Create instance: dummy_noc_3, and set properties + set dummy_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_3/aclk0] + + # Create instance: dummy_noc_4, and set properties + set dummy_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_4/aclk0] + + # Create instance: dummy_noc_5, and set properties + set dummy_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_5/aclk0] + + # Create instance: dummy_noc_6, and set properties + set dummy_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_6/aclk0] + + # Create instance: dummy_noc_7, and set properties + set dummy_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_7/aclk0] + + # Create instance: dummy_noc_m_0, and set properties + set dummy_noc_m_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_0/aclk0] + + # Create instance: dummy_noc_m_1, and set properties + set dummy_noc_m_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_1/aclk0] + + # Create instance: dummy_noc_m_2, and set properties + set dummy_noc_m_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_2/aclk0] + + # Create instance: dummy_noc_m_3, and set properties + set dummy_noc_m_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_3/aclk0] + + # Create instance: dummy_noc_m_4, and set properties + set dummy_noc_m_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_4/aclk0] + + # Create instance: dummy_noc_m_5, and set properties + set dummy_noc_m_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_5/aclk0] + + # Create instance: dummy_noc_m_6, and set properties + set dummy_noc_m_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_6/aclk0] + + # Create instance: dummy_noc_m_7, and set properties + set dummy_noc_m_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_7/aclk0] + + # Create instance: eth_0, and set properties + set eth_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_0 ] + + # Create instance: eth_1, and set properties + set eth_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_1 ] + + # Create instance: eth_2, and set properties + set eth_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_2 ] + + # Create instance: eth_3, and set properties + set eth_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_3 ] + + # Create instance: eth_4, and set properties + set eth_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_4 ] + + # Create instance: eth_5, and set properties + set eth_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_5 ] + + # Create instance: eth_6, and set properties + set eth_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_6 ] + + # Create instance: eth_7, and set properties + set eth_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 eth_7 ] + + # Create instance: sl2noc_0, and set properties + set sl2noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_0/aclk0] + + # Create instance: sl2noc_1, and set properties + set sl2noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_1/aclk0] + + # Create instance: sl2noc_2, and set properties + set sl2noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_2/aclk0] + + # Create instance: sl2noc_3, and set properties + set sl2noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_3/aclk0] + + # Create instance: sl2noc_4, and set properties + set sl2noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_4/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_4/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_4/aclk0] + + # Create instance: sl2noc_5, and set properties + set sl2noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_5/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_5/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_5/aclk0] + + # Create instance: sl2noc_6, and set properties + set sl2noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_6/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_6/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_6/aclk0] + + # Create instance: sl2noc_7, and set properties + set sl2noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /sl2noc_7/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_7/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_7/aclk0] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {14} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + + # Create instance: traffic_producer_1, and set properties + set traffic_producer_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_1 ] + + # Create instance: traffic_producer_2, and set properties + set traffic_producer_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_2 ] + + # Create instance: traffic_producer_3, and set properties + set traffic_producer_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_3 ] + + # Create instance: traffic_producer_5, and set properties + set traffic_producer_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_5 ] + + # Create instance: traffic_producer_6, and set properties + set traffic_producer_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_6 ] + + # Create instance: traffic_producer_7, and set properties + set traffic_producer_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_7 ] + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + + #### DCMAC entry points #### + add_dcmac_inst + + # Create instance: smartconnect_1, and set properties + set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {3} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_1 + + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x203_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_0/aclk0] + + # Create instance: noc_virt_0, and set properties + set noc_virt_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_0/aclk0] + + # Create instance: noc_virt_1, and set properties + set noc_virt_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_1/aclk0] + + # Create instance: noc_virt_2, and set properties + set noc_virt_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_2/aclk0] + + # Create instance: noc_virt_3, and set properties + set noc_virt_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_3/aclk0] + + # Create instance: noc_virt_4, and set properties + set noc_virt_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_4/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_4/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_4/aclk0] + + # Create instance: axi_noc_1, and set properties + set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_1 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_1 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_1/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_1/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_1/aclk0] + + # Create instance: axi4_full_passthrough_0, and set properties + set axi4_full_passthrough_0 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_0 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_0 + + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + + # Create instance: axi_register_slice_1, and set properties + set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ] + + # Create instance: axi_noc_2, and set properties + set axi_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_2 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_2 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_2/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_2/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_2/aclk0] + + # Create instance: axi_noc_3, and set properties + set axi_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_3 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_3 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_3/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_3/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_3/aclk0] + + # Create instance: axi_noc_4, and set properties + set axi_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_4 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_4 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_4/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_4/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_4/aclk0] + + # Create instance: axi_noc_5, and set properties + set axi_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_5 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_5 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_5/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_5/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_5/aclk0] + + # Create instance: axi4_full_passthrough_1, and set properties + set axi4_full_passthrough_1 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_1 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_1 + + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + + # Create instance: axi_register_slice_3, and set properties + set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ] + + # Create instance: axi4_full_passthrough_2, and set properties + set axi4_full_passthrough_2 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_2 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_2 + + + # Create instance: axi_register_slice_4, and set properties + set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ] + + # Create instance: axi_register_slice_5, and set properties + set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ] + + # Create instance: axi4_full_passthrough_3, and set properties + set axi4_full_passthrough_3 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_3 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_3 + + + # Create instance: axi_register_slice_6, and set properties + set axi_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_6 ] + + # Create instance: axi_register_slice_7, and set properties + set axi_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_7 ] + + # Create instance: axi4_full_passthrough_4, and set properties + set axi4_full_passthrough_4 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_4 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_4 + + + # Create instance: axi_register_slice_8, and set properties + set axi_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_8 ] + + # Create instance: axi_register_slice_9, and set properties + set axi_register_slice_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_9 ] + + # Create instance: ilreduced_logic_0, and set properties + set ilreduced_logic_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic:1.0 ilreduced_logic_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $ilreduced_logic_0 + + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {BUFG_FABRIC} $util_ds_buf_0 + + + # Create instance: c_shift_ram_0, and set properties + set c_shift_ram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 c_shift_ram_0 ] + set_property -dict [list \ + CONFIG.Depth {1} \ + CONFIG.Width {1} \ + ] $c_shift_ram_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins dummy_noc_m_0/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dummy_noc_m_1/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dummy_noc_m_2/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dummy_noc_m_3/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dummy_noc_m_4/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dummy_noc_m_5/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dummy_noc_m_6/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dummy_noc_m_7/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS7] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins dummy_noc_0/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dummy_noc_1/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dummy_noc_2/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dummy_noc_3/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dummy_noc_4/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dummy_noc_5/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dummy_noc_6/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dummy_noc_7/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS7] + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net S_AXIS_0_1 [get_bd_intf_pins qsfp_0_n_1/S_AXIS_0] [get_bd_intf_pins dummy_noc_0/M00_AXIS] + connect_bd_intf_net -intf_net S_QDMA_SLV_BRIDGE_1 [get_bd_intf_ports S_QDMA_SLV_BRIDGE] [get_bd_intf_pins axi_noc_5/S00_INI] + connect_bd_intf_net -intf_net S_VIRT_00_1 [get_bd_intf_ports S_VIRT_00] [get_bd_intf_pins axi_noc_1/S00_INI] + connect_bd_intf_net -intf_net S_VIRT_01_1 [get_bd_intf_ports S_VIRT_01] [get_bd_intf_pins axi_noc_2/S00_INI] + connect_bd_intf_net -intf_net S_VIRT_02_1 [get_bd_intf_ports S_VIRT_02] [get_bd_intf_pins axi_noc_3/S00_INI] + connect_bd_intf_net -intf_net S_VIRT_03_1 [get_bd_intf_ports S_VIRT_03] [get_bd_intf_pins axi_noc_4/S00_INI] + connect_bd_intf_net -intf_net axi4_full_passthrough_0_m_axi [get_bd_intf_pins axi_register_slice_1/S_AXI] [get_bd_intf_pins axi4_full_passthrough_0/m_axi] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi [get_bd_intf_pins axi4_full_passthrough_1/m_axi] [get_bd_intf_pins axi_register_slice_3/S_AXI] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi1 [get_bd_intf_pins axi4_full_passthrough_2/m_axi] [get_bd_intf_pins axi_register_slice_5/S_AXI] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi2 [get_bd_intf_pins axi4_full_passthrough_3/m_axi] [get_bd_intf_pins axi_register_slice_7/S_AXI] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi3 [get_bd_intf_pins axi4_full_passthrough_4/m_axi] [get_bd_intf_pins axi_register_slice_9/S_AXI] + connect_bd_intf_net -intf_net axi_noc_0_M00_AXI [get_bd_intf_pins axi_noc_0/M00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_noc_1_M00_AXI [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_noc_1/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_1_M00_INI [get_bd_intf_ports M_VIRT_0] [get_bd_intf_pins noc_virt_0/M00_INI] + connect_bd_intf_net -intf_net axi_noc_2_M00_AXI [get_bd_intf_pins axi_register_slice_2/S_AXI] [get_bd_intf_pins axi_noc_2/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_2_M00_INI [get_bd_intf_ports M_VIRT_1] [get_bd_intf_pins noc_virt_1/M00_INI] + connect_bd_intf_net -intf_net axi_noc_3_M00_AXI [get_bd_intf_pins axi_register_slice_4/S_AXI] [get_bd_intf_pins axi_noc_3/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_3_M00_INI [get_bd_intf_ports M_VIRT_2] [get_bd_intf_pins noc_virt_2/M00_INI] + connect_bd_intf_net -intf_net axi_noc_4_M00_AXI [get_bd_intf_pins axi_register_slice_6/S_AXI] [get_bd_intf_pins axi_noc_4/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_4_M00_INI [get_bd_intf_ports M_VIRT_3] [get_bd_intf_pins noc_virt_3/M00_INI] + connect_bd_intf_net -intf_net axi_noc_5_M00_AXI [get_bd_intf_pins axi_register_slice_8/S_AXI] [get_bd_intf_pins axi_noc_5/M00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins axi4_full_passthrough_0/s_axi] + connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins noc_virt_0/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_register_slice_2/M_AXI] [get_bd_intf_pins axi4_full_passthrough_1/s_axi] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI1 [get_bd_intf_pins axi_register_slice_4/M_AXI] [get_bd_intf_pins axi4_full_passthrough_2/s_axi] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI2 [get_bd_intf_pins axi_register_slice_6/M_AXI] [get_bd_intf_pins axi4_full_passthrough_3/s_axi] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI3 [get_bd_intf_pins axi_register_slice_8/M_AXI] [get_bd_intf_pins axi4_full_passthrough_4/s_axi] + connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins noc_virt_1/S00_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_pins axi_register_slice_5/M_AXI] [get_bd_intf_pins noc_virt_2/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_7_M_AXI [get_bd_intf_pins axi_register_slice_7/M_AXI] [get_bd_intf_pins noc_virt_3/S00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_9_M_AXI [get_bd_intf_pins axi_register_slice_9/M_AXI] [get_bd_intf_pins noc_virt_4/S00_AXI] + connect_bd_intf_net -intf_net dummy_noc_4_M00_AXIS [get_bd_intf_pins dummy_noc_4/M00_AXIS] [get_bd_intf_pins qsfp_2_n_3/S_AXIS_0] + connect_bd_intf_net -intf_net eth_0_m_axi_gmem0 [get_bd_intf_pins eth_0/m_axi_gmem0] [get_bd_intf_pins sl2noc_0/S00_AXI] + connect_bd_intf_net -intf_net eth_1_m_axi_gmem0 [get_bd_intf_pins eth_1/m_axi_gmem0] [get_bd_intf_pins sl2noc_1/S00_AXI] + connect_bd_intf_net -intf_net eth_2_m_axi_gmem0 [get_bd_intf_pins eth_2/m_axi_gmem0] [get_bd_intf_pins sl2noc_2/S00_AXI] + connect_bd_intf_net -intf_net eth_3_m_axi_gmem0 [get_bd_intf_pins eth_3/m_axi_gmem0] [get_bd_intf_pins sl2noc_3/S00_AXI] + connect_bd_intf_net -intf_net eth_4_m_axi_gmem0 [get_bd_intf_pins eth_4/m_axi_gmem0] [get_bd_intf_pins sl2noc_4/S00_AXI] + connect_bd_intf_net -intf_net eth_5_m_axi_gmem0 [get_bd_intf_pins eth_5/m_axi_gmem0] [get_bd_intf_pins sl2noc_5/S00_AXI] + connect_bd_intf_net -intf_net eth_6_m_axi_gmem0 [get_bd_intf_pins eth_6/m_axi_gmem0] [get_bd_intf_pins sl2noc_6/S00_AXI] + connect_bd_intf_net -intf_net eth_7_m_axi_gmem0 [get_bd_intf_pins eth_7/m_axi_gmem0] [get_bd_intf_pins sl2noc_7/S00_AXI] + connect_bd_intf_net -intf_net noc_virt_5_M00_INI [get_bd_intf_ports M_QDMA_SLV_BRIDGE] [get_bd_intf_pins noc_virt_4/M00_INI] + connect_bd_intf_net -intf_net qsfp0_322mhz_1 [get_bd_intf_ports qsfp0_322mhz] [get_bd_intf_pins qsfp_0_n_1/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net qsfp2_322mhz_1 [get_bd_intf_ports qsfp2_322mhz] [get_bd_intf_pins qsfp_2_n_3/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net qsfp_0_n_1_M_AXIS_0 [get_bd_intf_pins dummy_noc_m_0/S00_AXIS] [get_bd_intf_pins qsfp_0_n_1/M_AXIS_0] + connect_bd_intf_net -intf_net qsfp_0_n_1_qsfp_gt0 [get_bd_intf_ports qsfp0_4x] [get_bd_intf_pins qsfp_0_n_1/qsfp_gt0] + connect_bd_intf_net -intf_net qsfp_2_n_3_M_AXIS_0 [get_bd_intf_pins dummy_noc_m_4/S00_AXIS] [get_bd_intf_pins qsfp_2_n_3/M_AXIS_0] + connect_bd_intf_net -intf_net qsfp_2_n_3_qsfp_gt0 [get_bd_intf_ports qsfp2_4x] [get_bd_intf_pins qsfp_2_n_3/qsfp_gt0] + connect_bd_intf_net -intf_net sl2noc_0_M00_INI [get_bd_intf_ports SL2NOC_0] [get_bd_intf_pins sl2noc_0/M00_INI] + connect_bd_intf_net -intf_net sl2noc_1_M00_INI [get_bd_intf_ports SL2NOC_1] [get_bd_intf_pins sl2noc_1/M00_INI] + connect_bd_intf_net -intf_net sl2noc_2_M00_INI [get_bd_intf_ports SL2NOC_2] [get_bd_intf_pins sl2noc_2/M00_INI] + connect_bd_intf_net -intf_net sl2noc_3_M00_INI [get_bd_intf_ports SL2NOC_3] [get_bd_intf_pins sl2noc_3/M00_INI] + connect_bd_intf_net -intf_net sl2noc_4_M00_INI [get_bd_intf_ports SL2NOC_4] [get_bd_intf_pins sl2noc_4/M00_INI] + connect_bd_intf_net -intf_net sl2noc_5_M00_INI [get_bd_intf_ports SL2NOC_5] [get_bd_intf_pins sl2noc_5/M00_INI] + connect_bd_intf_net -intf_net sl2noc_6_M00_INI [get_bd_intf_ports SL2NOC_6] [get_bd_intf_pins sl2noc_6/M00_INI] + connect_bd_intf_net -intf_net sl2noc_7_M00_INI [get_bd_intf_ports SL2NOC_7] [get_bd_intf_pins sl2noc_7/M00_INI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins eth_5/s_axi_control] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins traffic_producer_1/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins smartconnect_0/M02_AXI] [get_bd_intf_pins traffic_producer_2/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins smartconnect_0/M03_AXI] [get_bd_intf_pins traffic_producer_3/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins eth_6/s_axi_control] [get_bd_intf_pins smartconnect_0/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins smartconnect_0/M05_AXI] [get_bd_intf_pins traffic_producer_5/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins smartconnect_0/M06_AXI] [get_bd_intf_pins traffic_producer_6/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins smartconnect_0/M07_AXI] [get_bd_intf_pins traffic_producer_7/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_0_M08_AXI [get_bd_intf_pins eth_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M08_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M09_AXI [get_bd_intf_pins eth_1/s_axi_control] [get_bd_intf_pins smartconnect_0/M09_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M10_AXI [get_bd_intf_pins eth_2/s_axi_control] [get_bd_intf_pins smartconnect_0/M10_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M11_AXI [get_bd_intf_pins eth_3/s_axi_control] [get_bd_intf_pins smartconnect_0/M11_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M12_AXI [get_bd_intf_pins eth_4/s_axi_control] [get_bd_intf_pins smartconnect_0/M12_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M13_AXI [get_bd_intf_pins smartconnect_1/S00_AXI] [get_bd_intf_pins smartconnect_0/M13_AXI] + connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins smartconnect_1/M00_AXI] [get_bd_intf_pins eth_7/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_1_M01_AXI [get_bd_intf_pins smartconnect_1/M01_AXI] [get_bd_intf_pins qsfp_0_n_1/s_axi] + connect_bd_intf_net -intf_net smartconnect_1_M02_AXI [get_bd_intf_pins smartconnect_1/M02_AXI] [get_bd_intf_pins qsfp_2_n_3/s_axi] + connect_bd_intf_net -intf_net traffic_producer_1_axis_out [get_bd_intf_pins traffic_producer_1/axis_out] [get_bd_intf_pins dummy_noc_m_1/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_2_axis_out [get_bd_intf_pins traffic_producer_2/axis_out] [get_bd_intf_pins dummy_noc_m_2/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_3_axis_out [get_bd_intf_pins traffic_producer_3/axis_out] [get_bd_intf_pins dummy_noc_m_3/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_5_axis_out [get_bd_intf_pins traffic_producer_5/axis_out] [get_bd_intf_pins dummy_noc_m_5/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_6_axis_out [get_bd_intf_pins traffic_producer_6/axis_out] [get_bd_intf_pins dummy_noc_m_6/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_7_axis_out [get_bd_intf_pins traffic_producer_7/axis_out] [get_bd_intf_pins dummy_noc_m_7/S00_AXIS] + + # Create port connections + connect_bd_net -net arstn_1 [get_bd_ports arstn] \ + [get_bd_pins c_shift_ram_0/D] + connect_bd_net -net c_shift_ram_0_Q [get_bd_pins c_shift_ram_0/Q] \ + [get_bd_pins util_ds_buf_0/BUFG_FABRIC_I] + + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_ports service_clk] \ + [get_bd_pins dummy_noc_0/aclk0] \ + [get_bd_pins dummy_noc_1/aclk0] \ + [get_bd_pins dummy_noc_2/aclk0] \ + [get_bd_pins dummy_noc_3/aclk0] \ + [get_bd_pins dummy_noc_4/aclk0] \ + [get_bd_pins dummy_noc_5/aclk0] \ + [get_bd_pins dummy_noc_6/aclk0] \ + [get_bd_pins dummy_noc_7/aclk0] \ + [get_bd_pins dummy_noc_m_0/aclk0] \ + [get_bd_pins dummy_noc_m_1/aclk0] \ + [get_bd_pins dummy_noc_m_2/aclk0] \ + [get_bd_pins dummy_noc_m_3/aclk0] \ + [get_bd_pins dummy_noc_m_4/aclk0] \ + [get_bd_pins dummy_noc_m_5/aclk0] \ + [get_bd_pins dummy_noc_m_6/aclk0] \ + [get_bd_pins dummy_noc_m_7/aclk0] \ + [get_bd_pins traffic_producer_1/ap_clk] \ + [get_bd_pins traffic_producer_2/ap_clk] \ + [get_bd_pins traffic_producer_3/ap_clk] \ + [get_bd_pins traffic_producer_5/ap_clk] \ + [get_bd_pins traffic_producer_6/ap_clk] \ + [get_bd_pins traffic_producer_7/ap_clk] \ + [get_bd_pins smartconnect_0/aclk] \ + [get_bd_pins eth_0/ap_clk] \ + [get_bd_pins eth_1/ap_clk] \ + [get_bd_pins eth_2/ap_clk] \ + [get_bd_pins eth_3/ap_clk] \ + [get_bd_pins eth_4/ap_clk] \ + [get_bd_pins eth_5/ap_clk] \ + [get_bd_pins eth_6/ap_clk] \ + [get_bd_pins eth_7/ap_clk] \ + [get_bd_pins sl2noc_0/aclk0] \ + [get_bd_pins sl2noc_1/aclk0] \ + [get_bd_pins sl2noc_2/aclk0] \ + [get_bd_pins sl2noc_3/aclk0] \ + [get_bd_pins sl2noc_4/aclk0] \ + [get_bd_pins sl2noc_5/aclk0] \ + [get_bd_pins sl2noc_6/aclk0] \ + [get_bd_pins sl2noc_7/aclk0] \ + [get_bd_pins qsfp_0_n_1/ap_clk] \ + [get_bd_pins qsfp_2_n_3/ap_clk] \ + [get_bd_pins smartconnect_1/aclk] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins noc_virt_0/aclk0] \ + [get_bd_pins axi_noc_1/aclk0] \ + [get_bd_pins axi4_full_passthrough_0/aclk] \ + [get_bd_pins axi_register_slice_0/aclk] \ + [get_bd_pins axi_register_slice_1/aclk] \ + [get_bd_pins axi_noc_5/aclk0] \ + [get_bd_pins axi_noc_4/aclk0] \ + [get_bd_pins axi_noc_3/aclk0] \ + [get_bd_pins axi_noc_2/aclk0] \ + [get_bd_pins axi_register_slice_3/aclk] \ + [get_bd_pins axi4_full_passthrough_1/aclk] \ + [get_bd_pins axi_register_slice_2/aclk] \ + [get_bd_pins noc_virt_1/aclk0] \ + [get_bd_pins axi4_full_passthrough_2/aclk] \ + [get_bd_pins axi_register_slice_5/aclk] \ + [get_bd_pins axi_register_slice_4/aclk] \ + [get_bd_pins axi4_full_passthrough_3/aclk] \ + [get_bd_pins axi_register_slice_7/aclk] \ + [get_bd_pins axi_register_slice_6/aclk] \ + [get_bd_pins axi4_full_passthrough_4/aclk] \ + [get_bd_pins axi_register_slice_9/aclk] \ + [get_bd_pins axi_register_slice_8/aclk] \ + [get_bd_pins noc_virt_3/aclk0] \ + [get_bd_pins noc_virt_2/aclk0] \ + [get_bd_pins noc_virt_4/aclk0] \ + [get_bd_pins c_shift_ram_0/CLK] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins ilreduced_logic_0/Res] \ + [get_bd_pins traffic_producer_1/ap_rst_n] \ + [get_bd_pins traffic_producer_2/ap_rst_n] \ + [get_bd_pins traffic_producer_3/ap_rst_n] \ + [get_bd_pins traffic_producer_5/ap_rst_n] \ + [get_bd_pins traffic_producer_6/ap_rst_n] \ + [get_bd_pins traffic_producer_7/ap_rst_n] \ + [get_bd_pins eth_0/ap_rst_n] \ + [get_bd_pins eth_1/ap_rst_n] \ + [get_bd_pins eth_2/ap_rst_n] \ + [get_bd_pins eth_3/ap_rst_n] \ + [get_bd_pins eth_4/ap_rst_n] \ + [get_bd_pins eth_5/ap_rst_n] \ + [get_bd_pins eth_6/ap_rst_n] \ + [get_bd_pins eth_7/ap_rst_n] \ + [get_bd_pins qsfp_0_n_1/ap_rst_n] \ + [get_bd_pins qsfp_2_n_3/ap_rst_n] \ + [get_bd_pins axi4_full_passthrough_0/aresetn] \ + [get_bd_pins axi_register_slice_0/aresetn] \ + [get_bd_pins axi_register_slice_1/aresetn] \ + [get_bd_pins axi_register_slice_3/aresetn] \ + [get_bd_pins axi4_full_passthrough_1/aresetn] \ + [get_bd_pins axi_register_slice_2/aresetn] \ + [get_bd_pins axi_register_slice_5/aresetn] \ + [get_bd_pins axi4_full_passthrough_2/aresetn] \ + [get_bd_pins axi_register_slice_4/aresetn] \ + [get_bd_pins axi_register_slice_7/aresetn] \ + [get_bd_pins axi4_full_passthrough_3/aresetn] \ + [get_bd_pins axi_register_slice_6/aresetn] \ + [get_bd_pins axi_register_slice_9/aresetn] \ + [get_bd_pins axi4_full_passthrough_4/aresetn] \ + [get_bd_pins axi_register_slice_8/aresetn] \ + [get_bd_pins smartconnect_1/aresetn] \ + [get_bd_pins smartconnect_0/aresetn] + + connect_bd_net -net util_ds_buf_0_BUFG_FABRIC_O [get_bd_pins util_ds_buf_0/BUFG_FABRIC_O] \ + [get_bd_pins ilreduced_logic_0/Op1] + + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] \ + [get_bd_pins dummy_noc_1/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_2/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_3/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_5/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_6/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_7/M00_AXIS_tready] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_0/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_0/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_1/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_1/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_2/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_2/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_3/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_3/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_4/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_4/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_5/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_5/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_6/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_6/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces eth_7/Data_m_axi_gmem0] [get_bd_addr_segs SL2NOC_7/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces axi4_full_passthrough_0/m_axi] [get_bd_addr_segs M_VIRT_0/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces axi4_full_passthrough_1/m_axi] [get_bd_addr_segs M_VIRT_1/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces axi4_full_passthrough_2/m_axi] [get_bd_addr_segs M_VIRT_2/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces axi4_full_passthrough_3/m_axi] [get_bd_addr_segs M_VIRT_3/Reg] -force + assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi4_full_passthrough_4/m_axi] [get_bd_addr_segs M_QDMA_SLV_BRIDGE/Reg] -force + # assign_bd_address -offset 0x020302040400 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + # assign_bd_address -offset 0x020303040400 -range 0x00000100 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + # assign_bd_address -offset 0x020302040000 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + # assign_bd_address -offset 0x020303040000 -range 0x00000100 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + # assign_bd_address -offset 0x020302040200 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + # assign_bd_address -offset 0x020303040200 -range 0x00000100 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + # assign_bd_address -offset 0x020302040600 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + # assign_bd_address -offset 0x020303040600 -range 0x00000100 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + # assign_bd_address -offset 0x020302000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + # assign_bd_address -offset 0x020303000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + assign_bd_address -offset 0x020300000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs eth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces S_QDMA_SLV_BRIDGE] [get_bd_addr_segs axi4_full_passthrough_4/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces S_VIRT_00] [get_bd_addr_segs axi4_full_passthrough_0/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces S_VIRT_01] [get_bd_addr_segs axi4_full_passthrough_1/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces S_VIRT_02] [get_bd_addr_segs axi4_full_passthrough_2/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces S_VIRT_03] [get_bd_addr_segs axi4_full_passthrough_3/s_axi/reg0] -force + + set_property USAGE memory [get_bd_addr_segs M_VIRT_0/Reg] + set_property USAGE memory [get_bd_addr_segs M_VIRT_1/Reg] + set_property USAGE memory [get_bd_addr_segs M_VIRT_2/Reg] + set_property USAGE memory [get_bd_addr_segs M_VIRT_3/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_0/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_1/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_2/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_3/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_4/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_5/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_6/Reg] + set_property USAGE memory [get_bd_addr_segs SL2NOC_7/Reg] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/linker/slashkit/resources/base/scripts/service_layer_build.tcl b/linker/slashkit/resources/base/scripts/service_layer_build.tcl new file mode 100644 index 00000000..034ad0a1 --- /dev/null +++ b/linker/slashkit/resources/base/scripts/service_layer_build.tcl @@ -0,0 +1,150 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +proc _service_usage {} { + return "Expected -tclargs: --project-name --ip-repo --static-shell-dcp --base-bd --opt-post-tcl --linker-results-dir --rm-work-dir --artifact-out-dir --jobs " +} + +proc _require_file {path label} { + if {![file exists $path]} { + error "Missing ${label}: $path" + } +} + +proc _require_dir {path label} { + if {![file isdirectory $path]} { + error "Missing ${label}: $path" + } +} + +array set opts { + --project-name "" + --ip-repo "" + --static-shell-dcp "" + --base-bd "" + --opt-post-tcl "" + --linker-results-dir "" + --rm-work-dir "" + --artifact-out-dir "" + --jobs 8 +} + +set idx 0 +while {$idx < [llength $argv]} { + set key [lindex $argv $idx] + if {![info exists opts($key)]} { + error "Unknown argument '$key'. [_service_usage]" + } + incr idx + if {$idx >= [llength $argv]} { + error "Missing value for '$key'. [_service_usage]" + } + set opts($key) [lindex $argv $idx] + incr idx +} + +foreach req {--project-name --ip-repo --static-shell-dcp --base-bd --opt-post-tcl --linker-results-dir --rm-work-dir --artifact-out-dir} { + if {$opts($req) eq ""} { + error "Missing required argument '$req'. [_service_usage]" + } +} + +set proj_name $opts(--project-name) +set ip_repo [file normalize $opts(--ip-repo)] +set static_shell_dcp [file normalize $opts(--static-shell-dcp)] +set base_bd [file normalize $opts(--base-bd)] +set opt_post_tcl [file normalize $opts(--opt-post-tcl)] +set linker_results_dir [file normalize $opts(--linker-results-dir)] +set rm_work_dir $opts(--rm-work-dir) +set artifact_out_dir $opts(--artifact-out-dir) +set jobs $opts(--jobs) + +file mkdir $rm_work_dir +file mkdir $artifact_out_dir +set rm_work_dir [file normalize $rm_work_dir] +set artifact_out_dir [file normalize $artifact_out_dir] + +set generated_bd_tcl [file join $linker_results_dir "service_layer.tcl"] + +_require_dir $ip_repo "IP repository directory" +_require_file $static_shell_dcp "static shell DCP" +_require_file $base_bd "installed service_layer BD" +_require_file $generated_bd_tcl "generated service_layer BD Tcl" +_require_file $opt_post_tcl "service_layer eth opt.post Tcl" + +puts "PROJECT NAME: $proj_name" +puts "IP REPO: $ip_repo" +puts "LINKER RESULTS: $linker_results_dir" +puts "RM WORK DIR: $rm_work_dir" +puts "ARTIFACT OUT DIR: $artifact_out_dir" +puts "JOBS: $jobs" +puts "OPT POST HOOK: $opt_post_tcl" + +set rm_proj_name "service_layer_${proj_name}" +set rm_name "${rm_proj_name}_rm" + +create_project $rm_proj_name $rm_work_dir -part xcv80-lsva4737-2MHP-e-S -force + +set_property ip_repo_paths [list $ip_repo] [current_project] +update_ip_catalog +add_files $static_shell_dcp +import_files $base_bd +set_property PR_FLOW 1 [current_project] +set_property DESIGN_MODE GateLvl [current_fileset] +set_property top top_wrapper [current_fileset] +set_property source_mgmt_mode All [current_project] + +create_partition_def -name $rm_proj_name -module service_layer +create_reconfig_module -name $rm_name -partition_def [get_partition_defs $rm_proj_name] -define_from service_layer + +create_pr_configuration -name config_1 -partitions [list top_i/service_layer:$rm_name] +set_property USE_BLACKBOX 0 [get_pr_configuration config_1] +set_property PR_CONFIGURATION config_1 [get_runs impl_1] + +add_files -fileset utils_1 -norecurse $opt_post_tcl +set opt_post_hook [lindex [get_files -of_objects [get_filesets utils_1] [list "*service_layer_eth.opt.post.tcl"]] 0] +if {$opt_post_hook eq ""} { + error "Failed to import service-layer opt.post hook into utils_1: $opt_post_tcl" +} + + +set imported_bd [file join $rm_work_dir "${rm_proj_name}.srcs" "sources_1" "bd" "service_layer" "service_layer.bd"] +open_bd_design $imported_bd +foreach p [get_bd_intf_ports] { + set_property HDL_ATTRIBUTE.LOCKED {TRUE} $p +} +source $generated_bd_tcl + +launch_runs "${rm_name}_synth_1" -jobs $jobs +wait_on_run "${rm_name}_synth_1" + +set rm_synth_dcp [file join $rm_work_dir "${rm_proj_name}.runs" "${rm_name}_synth_1" "service_layer.dcp"] +add_files $rm_synth_dcp +set_property SCOPED_TO_CELLS {top_i/service_layer} [get_files $rm_synth_dcp] +set_property strategy Congestion_SSI_SpreadLogic_high [get_runs impl_1] +set_property STEPS.OPT_DESIGN.TCL.POST $opt_post_hook [get_runs impl_1] +puts "Attached impl_1 post-opt hook: $opt_post_hook" + +launch_runs impl_1 -jobs $jobs +wait_on_run impl_1 +open_run impl_1 + +set partial_pdi [file join $artifact_out_dir "top_i_service_layer_service_layer_${proj_name}_inst_0_partial.pdi"] +write_device_image -cell top_i/service_layer -force $partial_pdi diff --git a/linker/slashkit/resources/base/scripts/slash_base.tcl b/linker/slashkit/resources/base/scripts/slash_base.tcl new file mode 100644 index 00000000..6411e11c --- /dev/null +++ b/linker/slashkit/resources/base/scripts/slash_base.tcl @@ -0,0 +1,4016 @@ + +################################################################ +# This is a generated script based on design: slash_base +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2025.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source slash_base_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcv80-lsva4737-2MHP-e-S +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name slash_base + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:hls:hbm_bandwidth:1.0\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:axi_noc:1.1\ +xilinx.com:ip:axis_noc:1.0\ +xilinx.com:hls:traffic_producer:1.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:c_shift_ram:12.0\ +xilinx.com:inline_hdl:ilreduced_logic:1.0\ +xilinx.com:ip:util_ds_buf:2.2\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set HBM_AXI_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_00 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_00 + + set HBM_AXI_01 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_01 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_01 + + set HBM_AXI_10 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_10 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_10 + + set HBM_AXI_11 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_11 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_11 + + set HBM_AXI_12 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_12 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_12 + + set HBM_AXI_13 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_13 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_13 + + set HBM_AXI_14 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_14 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_14 + + set HBM_AXI_15 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_15 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_15 + + set HBM_AXI_16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_16 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_16 + + set HBM_AXI_17 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_17 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_17 + + set HBM_AXI_18 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_18 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_18 + + set HBM_AXI_19 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_19 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_19 + + set HBM_AXI_02 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_02 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_02 + + set HBM_AXI_20 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_20 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_20 + + set HBM_AXI_21 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_21 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_21 + + set HBM_AXI_22 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_22 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_22 + + set HBM_AXI_23 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_23 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_23 + + set HBM_AXI_24 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_24 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_24 + + set HBM_AXI_25 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_25 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_25 + + set HBM_AXI_26 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_26 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_26 + + set HBM_AXI_27 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_27 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_27 + + set HBM_AXI_28 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_28 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_28 + + set HBM_AXI_29 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_29 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_29 + + set HBM_AXI_03 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_03 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_03 + + set HBM_AXI_30 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_30 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_30 + + set HBM_AXI_31 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_31 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_31 + + set HBM_AXI_32 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_32 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_32 + + set HBM_AXI_33 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_33 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_33 + + set HBM_AXI_34 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_34 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_34 + + set HBM_AXI_35 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_35 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_35 + + set HBM_AXI_36 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_36 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_36 + + set HBM_AXI_37 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_37 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_37 + + set HBM_AXI_38 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_38 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_38 + + set HBM_AXI_39 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_39 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_39 + + set HBM_AXI_04 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_04 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_04 + + set HBM_AXI_40 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_40 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_40 + + set HBM_AXI_41 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_41 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_41 + + set HBM_AXI_42 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_42 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_42 + + set HBM_AXI_43 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_43 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_43 + + set HBM_AXI_44 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_44 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_44 + + set HBM_AXI_45 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_45 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_45 + + set HBM_AXI_46 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_46 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_46 + + set HBM_AXI_47 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_47 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_47 + + set HBM_AXI_48 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_48 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_48 + + set HBM_AXI_49 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_49 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_49 + + set HBM_AXI_05 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_05 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_05 + + set HBM_AXI_50 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_50 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_50 + + set HBM_AXI_51 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_51 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_51 + + set HBM_AXI_52 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_52 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_52 + + set HBM_AXI_53 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_53 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_53 + + set HBM_AXI_54 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_54 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_54 + + set HBM_AXI_55 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_55 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_55 + + set HBM_AXI_56 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_56 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_56 + + set HBM_AXI_57 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_57 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_57 + + set HBM_AXI_58 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_58 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_58 + + set HBM_AXI_59 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_59 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_59 + + set HBM_AXI_06 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_06 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_06 + + set HBM_AXI_60 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_60 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_60 + + set HBM_AXI_61 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_61 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_61 + + set HBM_AXI_62 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_62 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_62 + + set HBM_AXI_63 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_63 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_63 + + set HBM_AXI_07 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_07 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_07 + + set HBM_AXI_08 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_08 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_08 + + set HBM_AXI_09 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM_AXI_09 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {400000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_RRESP {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $HBM_AXI_09 + + set M00_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI ] + + set M01_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M01_INI ] + + set M02_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M02_INI ] + + set M03_INI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M03_INI ] + + set HBM_VNOC_INI_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_00 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_00 + + set HBM_VNOC_INI_01 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_01 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_01 + + set HBM_VNOC_INI_02 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_02 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_02 + + set HBM_VNOC_INI_03 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_03 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_03 + + set HBM_VNOC_INI_04 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_04 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_04 + + set HBM_VNOC_INI_05 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_05 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_05 + + set HBM_VNOC_INI_06 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_06 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_06 + + set HBM_VNOC_INI_07 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 HBM_VNOC_INI_07 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $HBM_VNOC_INI_07 + + set M_DCMAC_INIS0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS0 + + set M_DCMAC_INIS1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS1 + + set M_DCMAC_INIS2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS2 + + set M_DCMAC_INIS3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS3 + + set M_DCMAC_INIS4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS4 + + set M_DCMAC_INIS5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS5 + + set M_DCMAC_INIS6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS6 + + set M_DCMAC_INIS7 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $M_DCMAC_INIS7 + + set S_DCMAC_INIS0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS0 + + set S_DCMAC_INIS1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS1 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS1 + + set S_DCMAC_INIS2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS2 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS2 + + set S_DCMAC_INIS3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS3 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS3 + + set S_DCMAC_INIS4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS4 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS4 + + set S_DCMAC_INIS5 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS5 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS5 + + set S_DCMAC_INIS6 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS6 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS6 + + set S_DCMAC_INIS7 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S_DCMAC_INIS7 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] $S_DCMAC_INIS7 + + set S_AXILITE_INI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S_AXILITE_INI ] + set_property -dict [ list \ + CONFIG.COMPUTED_STRATEGY {load} \ + CONFIG.INI_STRATEGY {load} \ + ] $S_AXILITE_INI + set_property APERTURES {{0x202_0000_0000 128M}} [get_bd_intf_ports S_AXILITE_INI] + + set SL_VIRT_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL_VIRT_00 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL_VIRT_00 + + set SL_VIRT_01 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL_VIRT_01 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL_VIRT_01 + + set SL_VIRT_02 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL_VIRT_02 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL_VIRT_02 + + set SL_VIRT_03 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 SL_VIRT_03 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $SL_VIRT_03 + + set QDMA_SLAVE_BRIDGE_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 QDMA_SLAVE_BRIDGE_0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] $QDMA_SLAVE_BRIDGE_0 + + + # Create ports + set arstn [ create_bd_port -dir I -type rst arstn ] + set static_region_clk [ create_bd_port -dir I -type clk -freq_hz 400000000 static_region_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {HBM_AXI_63:HBM_AXI_62:HBM_AXI_61:HBM_AXI_60:HBM_AXI_59:HBM_AXI_58:HBM_AXI_57:HBM_AXI_56:HBM_AXI_55:HBM_AXI_54:HBM_AXI_53:HBM_AXI_52:HBM_AXI_51:HBM_AXI_50:HBM_AXI_49:HBM_AXI_48:HBM_AXI_47:HBM_AXI_46:HBM_AXI_45:HBM_AXI_44:HBM_AXI_43:HBM_AXI_42:HBM_AXI_41:HBM_AXI_40:HBM_AXI_39:HBM_AXI_38:HBM_AXI_37:HBM_AXI_36:HBM_AXI_35:HBM_AXI_34:HBM_AXI_33:HBM_AXI_32:HBM_AXI_31:HBM_AXI_30:HBM_AXI_29:HBM_AXI_28:HBM_AXI_27:HBM_AXI_26:HBM_AXI_25:HBM_AXI_24:HBM_AXI_23:HBM_AXI_22:HBM_AXI_21:HBM_AXI_20:HBM_AXI_19:HBM_AXI_18:HBM_AXI_17:HBM_AXI_16:HBM_AXI_15:HBM_AXI_14:HBM_AXI_13:HBM_AXI_12:HBM_AXI_11:HBM_AXI_10:HBM_AXI_09:HBM_AXI_08:HBM_AXI_07:HBM_AXI_06:HBM_AXI_05:HBM_AXI_04:HBM_AXI_03:HBM_AXI_02:HBM_AXI_01:HBM_AXI_00} \ + CONFIG.CLK_DOMAIN {top_clk_wizard_0_0_clk_out1} \ + ] $static_region_clk + set user_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 user_clk ] + + # Create instance: ddr_bandwidth_64, and set properties + set ddr_bandwidth_64 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_64 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_64 + + + # Create instance: ddr_bandwidth_65, and set properties + set ddr_bandwidth_65 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_65 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_65 + + + # Create instance: ddr_bandwidth_66, and set properties + set ddr_bandwidth_66 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_66 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_66 + + + # Create instance: ddr_bandwidth_67, and set properties + set ddr_bandwidth_67 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 ddr_bandwidth_67 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $ddr_bandwidth_67 + + + # Create instance: hbm_bandwidth_0, and set properties + set hbm_bandwidth_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_0 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_0 + + + # Create instance: hbm_bandwidth_1, and set properties + set hbm_bandwidth_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_1 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_1 + + + # Create instance: hbm_bandwidth_10, and set properties + set hbm_bandwidth_10 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_10 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_10 + + + # Create instance: hbm_bandwidth_11, and set properties + set hbm_bandwidth_11 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_11 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_11 + + + # Create instance: hbm_bandwidth_12, and set properties + set hbm_bandwidth_12 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_12 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_12 + + + # Create instance: hbm_bandwidth_13, and set properties + set hbm_bandwidth_13 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_13 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_13 + + + # Create instance: hbm_bandwidth_14, and set properties + set hbm_bandwidth_14 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_14 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_14 + + + # Create instance: hbm_bandwidth_15, and set properties + set hbm_bandwidth_15 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_15 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_15 + + + # Create instance: hbm_bandwidth_16, and set properties + set hbm_bandwidth_16 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_16 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_16 + + + # Create instance: hbm_bandwidth_17, and set properties + set hbm_bandwidth_17 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_17 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_17 + + + # Create instance: hbm_bandwidth_18, and set properties + set hbm_bandwidth_18 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_18 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_18 + + + # Create instance: hbm_bandwidth_19, and set properties + set hbm_bandwidth_19 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_19 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_19 + + + # Create instance: hbm_bandwidth_2, and set properties + set hbm_bandwidth_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_2 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_2 + + + # Create instance: hbm_bandwidth_20, and set properties + set hbm_bandwidth_20 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_20 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_20 + + + # Create instance: hbm_bandwidth_21, and set properties + set hbm_bandwidth_21 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_21 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_21 + + + # Create instance: hbm_bandwidth_22, and set properties + set hbm_bandwidth_22 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_22 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_22 + + + # Create instance: hbm_bandwidth_23, and set properties + set hbm_bandwidth_23 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_23 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_23 + + + # Create instance: hbm_bandwidth_24, and set properties + set hbm_bandwidth_24 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_24 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_24 + + + # Create instance: hbm_bandwidth_25, and set properties + set hbm_bandwidth_25 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_25 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_25 + + + # Create instance: hbm_bandwidth_26, and set properties + set hbm_bandwidth_26 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_26 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_26 + + + # Create instance: hbm_bandwidth_27, and set properties + set hbm_bandwidth_27 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_27 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_27 + + + # Create instance: hbm_bandwidth_28, and set properties + set hbm_bandwidth_28 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_28 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_28 + + + # Create instance: hbm_bandwidth_29, and set properties + set hbm_bandwidth_29 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_29 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_29 + + + # Create instance: hbm_bandwidth_3, and set properties + set hbm_bandwidth_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_3 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_3 + + + # Create instance: hbm_bandwidth_30, and set properties + set hbm_bandwidth_30 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_30 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_30 + + + # Create instance: hbm_bandwidth_31, and set properties + set hbm_bandwidth_31 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_31 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_31 + + + # Create instance: hbm_bandwidth_32, and set properties + set hbm_bandwidth_32 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_32 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_32 + + + # Create instance: hbm_bandwidth_33, and set properties + set hbm_bandwidth_33 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_33 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_33 + + + # Create instance: hbm_bandwidth_34, and set properties + set hbm_bandwidth_34 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_34 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_34 + + + # Create instance: hbm_bandwidth_35, and set properties + set hbm_bandwidth_35 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_35 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_35 + + + # Create instance: hbm_bandwidth_36, and set properties + set hbm_bandwidth_36 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_36 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_36 + + + # Create instance: hbm_bandwidth_37, and set properties + set hbm_bandwidth_37 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_37 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_37 + + + # Create instance: hbm_bandwidth_38, and set properties + set hbm_bandwidth_38 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_38 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_38 + + + # Create instance: hbm_bandwidth_39, and set properties + set hbm_bandwidth_39 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_39 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_39 + + + # Create instance: hbm_bandwidth_4, and set properties + set hbm_bandwidth_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_4 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_4 + + + # Create instance: hbm_bandwidth_40, and set properties + set hbm_bandwidth_40 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_40 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_40 + + + # Create instance: hbm_bandwidth_41, and set properties + set hbm_bandwidth_41 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_41 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_41 + + + # Create instance: hbm_bandwidth_42, and set properties + set hbm_bandwidth_42 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_42 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_42 + + + # Create instance: hbm_bandwidth_43, and set properties + set hbm_bandwidth_43 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_43 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_43 + + + # Create instance: hbm_bandwidth_44, and set properties + set hbm_bandwidth_44 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_44 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_44 + + + # Create instance: hbm_bandwidth_45, and set properties + set hbm_bandwidth_45 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_45 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_45 + + + # Create instance: hbm_bandwidth_46, and set properties + set hbm_bandwidth_46 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_46 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_46 + + + # Create instance: hbm_bandwidth_47, and set properties + set hbm_bandwidth_47 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_47 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_47 + + + # Create instance: hbm_bandwidth_48, and set properties + set hbm_bandwidth_48 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_48 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_48 + + + # Create instance: hbm_bandwidth_49, and set properties + set hbm_bandwidth_49 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_49 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_49 + + + # Create instance: hbm_bandwidth_5, and set properties + set hbm_bandwidth_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_5 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_5 + + + # Create instance: hbm_bandwidth_50, and set properties + set hbm_bandwidth_50 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_50 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_50 + + + # Create instance: hbm_bandwidth_51, and set properties + set hbm_bandwidth_51 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_51 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_51 + + + # Create instance: hbm_bandwidth_52, and set properties + set hbm_bandwidth_52 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_52 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_52 + + + # Create instance: hbm_bandwidth_53, and set properties + set hbm_bandwidth_53 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_53 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_53 + + + # Create instance: hbm_bandwidth_54, and set properties + set hbm_bandwidth_54 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_54 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_54 + + + # Create instance: hbm_bandwidth_55, and set properties + set hbm_bandwidth_55 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_55 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_55 + + + # Create instance: hbm_bandwidth_56, and set properties + set hbm_bandwidth_56 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_56 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_56 + + + # Create instance: hbm_bandwidth_57, and set properties + set hbm_bandwidth_57 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_57 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_57 + + + # Create instance: hbm_bandwidth_58, and set properties + set hbm_bandwidth_58 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_58 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_58 + + + # Create instance: hbm_bandwidth_59, and set properties + set hbm_bandwidth_59 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_59 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_59 + + + # Create instance: hbm_bandwidth_6, and set properties + set hbm_bandwidth_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_6 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_6 + + + # Create instance: hbm_bandwidth_60, and set properties + set hbm_bandwidth_60 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_60 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_60 + + + # Create instance: hbm_bandwidth_61, and set properties + set hbm_bandwidth_61 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_61 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_61 + + + # Create instance: hbm_bandwidth_62, and set properties + set hbm_bandwidth_62 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_62 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_62 + + + # Create instance: hbm_bandwidth_63, and set properties + set hbm_bandwidth_63 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_63 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_63 + + + # Create instance: hbm_bandwidth_7, and set properties + set hbm_bandwidth_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_7 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_7 + + + # Create instance: hbm_bandwidth_8, and set properties + set hbm_bandwidth_8 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_8 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_8 + + + # Create instance: hbm_bandwidth_9, and set properties + set hbm_bandwidth_9 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_9 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_9 + + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + + # Create instance: ddr_noc_0, and set properties + set ddr_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_0/aclk0] + + # Create instance: ddr_noc_1, and set properties + set ddr_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_1/aclk0] + + # Create instance: ddr_noc_2, and set properties + set ddr_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_2/aclk0] + + # Create instance: ddr_noc_3, and set properties + set ddr_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 ddr_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_3/aclk0] + + # Create instance: hbm_bandwidth_64, and set properties + set hbm_bandwidth_64 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_64 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_64 + + + # Create instance: hbm_bandwidth_65, and set properties + set hbm_bandwidth_65 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_65 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_65 + + + # Create instance: hbm_bandwidth_66, and set properties + set hbm_bandwidth_66 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_66 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_66 + + + # Create instance: hbm_bandwidth_67, and set properties + set hbm_bandwidth_67 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_67 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_67 + + + # Create instance: hbm_bandwidth_68, and set properties + set hbm_bandwidth_68 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_68 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_68 + + + # Create instance: hbm_bandwidth_69, and set properties + set hbm_bandwidth_69 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_69 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_69 + + + # Create instance: hbm_bandwidth_70, and set properties + set hbm_bandwidth_70 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_70 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_70 + + + # Create instance: hbm_bandwidth_71, and set properties + set hbm_bandwidth_71 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_71 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {256} $hbm_bandwidth_71 + + + # Create instance: hbm_vnoc_00, and set properties + set hbm_vnoc_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_00 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_00 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_00/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_00/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_00/aclk0] + + # Create instance: hbm_vnoc_01, and set properties + set hbm_vnoc_01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_01 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_01 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_01/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_01/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_01/aclk0] + + # Create instance: hbm_vnoc_02, and set properties + set hbm_vnoc_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_02 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_02 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_02/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_02/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_02/aclk0] + + # Create instance: hbm_vnoc_03, and set properties + set hbm_vnoc_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_03 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_03 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_03/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_03/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_03/aclk0] + + # Create instance: hbm_vnoc_04, and set properties + set hbm_vnoc_04 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_04 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_04 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_04/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_04/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_04/aclk0] + + # Create instance: hbm_vnoc_05, and set properties + set hbm_vnoc_05 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_05 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_05 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_05/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_05/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_05/aclk0] + + # Create instance: hbm_vnoc_06, and set properties + set hbm_vnoc_06 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_06 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_06 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_06/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_06/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_06/aclk0] + + # Create instance: hbm_vnoc_07, and set properties + set hbm_vnoc_07 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 hbm_vnoc_07 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_07 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_07/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_07/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_07/aclk0] + + # Create instance: dcmac_axis_noc_0, and set properties + set dcmac_axis_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_0/aclk0] + + # Create instance: dcmac_axis_noc_1, and set properties + set dcmac_axis_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_1/aclk0] + + # Create instance: dcmac_axis_noc_2, and set properties + set dcmac_axis_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_2/aclk0] + + # Create instance: dcmac_axis_noc_3, and set properties + set dcmac_axis_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_3/aclk0] + + # Create instance: dcmac_axis_noc_4, and set properties + set dcmac_axis_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_4/aclk0] + + # Create instance: dcmac_axis_noc_5, and set properties + set dcmac_axis_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_5/aclk0] + + # Create instance: dcmac_axis_noc_6, and set properties + set dcmac_axis_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_6/aclk0] + + # Create instance: dcmac_axis_noc_7, and set properties + set dcmac_axis_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_7/aclk0] + + # Create instance: dcmac_axis_noc_s_0, and set properties + set dcmac_axis_noc_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_0/aclk0] + + # Create instance: dcmac_axis_noc_s_1, and set properties + set dcmac_axis_noc_s_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_1/aclk0] + + # Create instance: dcmac_axis_noc_s_2, and set properties + set dcmac_axis_noc_s_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_2/aclk0] + + # Create instance: dcmac_axis_noc_s_3, and set properties + set dcmac_axis_noc_s_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_3/aclk0] + + # Create instance: dcmac_axis_noc_s_4, and set properties + set dcmac_axis_noc_s_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_4/aclk0] + + # Create instance: dcmac_axis_noc_s_5, and set properties + set dcmac_axis_noc_s_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_5/aclk0] + + # Create instance: dcmac_axis_noc_s_6, and set properties + set dcmac_axis_noc_s_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_6/aclk0] + + # Create instance: dcmac_axis_noc_s_7, and set properties + set dcmac_axis_noc_s_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_7/aclk0] + + # Create instance: traffic_producer_0, and set properties + set traffic_producer_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_0 ] + + # Create instance: traffic_producer_1, and set properties + set traffic_producer_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_1 ] + + # Create instance: traffic_producer_2, and set properties + set traffic_producer_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_2 ] + + # Create instance: traffic_producer_3, and set properties + set traffic_producer_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_3 ] + + # Create instance: traffic_producer_4, and set properties + set traffic_producer_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_4 ] + + # Create instance: traffic_producer_5, and set properties + set traffic_producer_5 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_5 ] + + # Create instance: traffic_producer_6, and set properties + set traffic_producer_6 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_6 ] + + # Create instance: traffic_producer_7, and set properties + set traffic_producer_7 [ create_bd_cell -type ip -vlnv xilinx.com:hls:traffic_producer:1.0 traffic_producer_7 ] + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + + # Create instance: traffic_virt_0, and set properties + set traffic_virt_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_0 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_0 + + + # Create instance: traffic_virt_1, and set properties + set traffic_virt_1 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_1 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_1 + + + # Create instance: traffic_virt_2, and set properties + set traffic_virt_2 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_2 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_2 + + + # Create instance: traffic_virt_3, and set properties + set traffic_virt_3 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_3 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {512} $traffic_virt_3 + + + # Create instance: traffic_virt_4, and set properties + set traffic_virt_4 [ create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 traffic_virt_4 ] + set_property CONFIG.C_M_AXI_GMEM0_DATA_WIDTH {128} $traffic_virt_4 + + + # Create instance: smartconnect_1, and set properties + set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_1 + + + # Create instance: smartconnect_2, and set properties + set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_2 + + + # Create instance: smartconnect_3, and set properties + set smartconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_3 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_3 + + + # Create instance: smartconnect_4, and set properties + set smartconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_4 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {16} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_4 + + + # Create instance: smartconnect_5, and set properties + set smartconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_5 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {14} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_5 + + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x202_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_0/aclk0] + + # Create instance: hbm_sc_00, and set properties + set hbm_sc_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_00 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_00 + + + # Create instance: hbm_sc_01, and set properties + set hbm_sc_01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_01 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_01 + + + # Create instance: hbm_sc_02, and set properties + set hbm_sc_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_02 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_02 + + + # Create instance: hbm_sc_03, and set properties + set hbm_sc_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_03 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_03 + + + # Create instance: hbm_sc_04, and set properties + set hbm_sc_04 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_04 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_04 + + + # Create instance: hbm_sc_05, and set properties + set hbm_sc_05 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_05 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_05 + + + # Create instance: hbm_sc_06, and set properties + set hbm_sc_06 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_06 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_06 + + + # Create instance: hbm_sc_07, and set properties + set hbm_sc_07 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_07 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_07 + + + # Create instance: hbm_sc_08, and set properties + set hbm_sc_08 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_08 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_08 + + + # Create instance: hbm_sc_09, and set properties + set hbm_sc_09 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_09 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_09 + + + # Create instance: hbm_sc_10, and set properties + set hbm_sc_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_10 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_10 + + + # Create instance: hbm_sc_11, and set properties + set hbm_sc_11 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_11 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_11 + + + # Create instance: hbm_sc_12, and set properties + set hbm_sc_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_12 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_12 + + + # Create instance: hbm_sc_13, and set properties + set hbm_sc_13 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_13 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_13 + + + # Create instance: hbm_sc_14, and set properties + set hbm_sc_14 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_14 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_14 + + + # Create instance: hbm_sc_15, and set properties + set hbm_sc_15 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_15 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_15 + + + # Create instance: hbm_sc_16, and set properties + set hbm_sc_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_16 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_16 + + + # Create instance: hbm_sc_17, and set properties + set hbm_sc_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_17 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_17 + + + # Create instance: hbm_sc_18, and set properties + set hbm_sc_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_18 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_18 + + + # Create instance: hbm_sc_19, and set properties + set hbm_sc_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_19 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_19 + + + # Create instance: hbm_sc_20, and set properties + set hbm_sc_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_20 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_20 + + + # Create instance: hbm_sc_21, and set properties + set hbm_sc_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_21 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_21 + + + # Create instance: hbm_sc_22, and set properties + set hbm_sc_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_22 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_22 + + + # Create instance: hbm_sc_23, and set properties + set hbm_sc_23 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_23 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_23 + + + # Create instance: hbm_sc_24, and set properties + set hbm_sc_24 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_24 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_24 + + + # Create instance: hbm_sc_25, and set properties + set hbm_sc_25 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_25 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_25 + + + # Create instance: hbm_sc_26, and set properties + set hbm_sc_26 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_26 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_26 + + + # Create instance: hbm_sc_27, and set properties + set hbm_sc_27 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_27 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_27 + + + # Create instance: hbm_sc_28, and set properties + set hbm_sc_28 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_28 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_28 + + + # Create instance: hbm_sc_29, and set properties + set hbm_sc_29 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_29 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_29 + + + # Create instance: hbm_sc_30, and set properties + set hbm_sc_30 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_30 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_30 + + + # Create instance: hbm_sc_31, and set properties + set hbm_sc_31 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_31 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_31 + + + # Create instance: hbm_sc_32, and set properties + set hbm_sc_32 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_32 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_32 + + + # Create instance: hbm_sc_33, and set properties + set hbm_sc_33 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_33 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_33 + + + # Create instance: hbm_sc_34, and set properties + set hbm_sc_34 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_34 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_34 + + + # Create instance: hbm_sc_35, and set properties + set hbm_sc_35 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_35 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_35 + + + # Create instance: hbm_sc_36, and set properties + set hbm_sc_36 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_36 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_36 + + + # Create instance: hbm_sc_37, and set properties + set hbm_sc_37 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_37 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_37 + + + # Create instance: hbm_sc_38, and set properties + set hbm_sc_38 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_38 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_38 + + + # Create instance: hbm_sc_39, and set properties + set hbm_sc_39 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_39 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_39 + + + # Create instance: hbm_sc_40, and set properties + set hbm_sc_40 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_40 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_40 + + + # Create instance: hbm_sc_41, and set properties + set hbm_sc_41 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_41 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_41 + + + # Create instance: hbm_sc_42, and set properties + set hbm_sc_42 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_42 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_42 + + + # Create instance: hbm_sc_43, and set properties + set hbm_sc_43 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_43 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_43 + + + # Create instance: hbm_sc_44, and set properties + set hbm_sc_44 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_44 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_44 + + + # Create instance: hbm_sc_45, and set properties + set hbm_sc_45 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_45 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_45 + + + # Create instance: hbm_sc_46, and set properties + set hbm_sc_46 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_46 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_46 + + + # Create instance: hbm_sc_47, and set properties + set hbm_sc_47 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_47 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_47 + + + # Create instance: hbm_sc_48, and set properties + set hbm_sc_48 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_48 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_48 + + + # Create instance: hbm_sc_49, and set properties + set hbm_sc_49 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_49 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_49 + + + # Create instance: hbm_sc_50, and set properties + set hbm_sc_50 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_50 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_50 + + + # Create instance: hbm_sc_51, and set properties + set hbm_sc_51 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_51 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_51 + + + # Create instance: hbm_sc_52, and set properties + set hbm_sc_52 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_52 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_52 + + + # Create instance: hbm_sc_53, and set properties + set hbm_sc_53 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_53 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_53 + + + # Create instance: hbm_sc_54, and set properties + set hbm_sc_54 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_54 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_54 + + + # Create instance: hbm_sc_55, and set properties + set hbm_sc_55 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_55 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_55 + + + # Create instance: hbm_sc_56, and set properties + set hbm_sc_56 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_56 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_56 + + + # Create instance: hbm_sc_57, and set properties + set hbm_sc_57 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_57 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_57 + + + # Create instance: hbm_sc_58, and set properties + set hbm_sc_58 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_58 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_58 + + + # Create instance: hbm_sc_59, and set properties + set hbm_sc_59 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_59 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_59 + + + # Create instance: hbm_sc_60, and set properties + set hbm_sc_60 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_60 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_60 + + + # Create instance: hbm_sc_61, and set properties + set hbm_sc_61 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_61 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_61 + + + # Create instance: hbm_sc_62, and set properties + set hbm_sc_62 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_62 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_62 + + + # Create instance: hbm_sc_63, and set properties + set hbm_sc_63 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 hbm_sc_63 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $hbm_sc_63 + + + # Create instance: noc_virt_00, and set properties + set noc_virt_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 noc_virt_00 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_00 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_00/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_00/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_00/aclk0] + + # Create instance: qdma_slave_bridge_noc, and set properties + set qdma_slave_bridge_noc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 qdma_slave_bridge_noc ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $qdma_slave_bridge_noc + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /qdma_slave_bridge_noc/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /qdma_slave_bridge_noc/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /qdma_slave_bridge_noc/aclk0] + + # Create instance: noc_virt_02, and set properties + set noc_virt_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 noc_virt_02 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_02 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_02/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_02/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_02/aclk0] + + # Create instance: noc_virt_03, and set properties + set noc_virt_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 noc_virt_03 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_03 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_03/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_03/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_03/aclk0] + + # Create instance: axi_noc_1, and set properties + set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $axi_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /axi_noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /axi_noc_1/aclk0] + + # Create instance: c_shift_ram_0, and set properties + set c_shift_ram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 c_shift_ram_0 ] + set_property -dict [list \ + CONFIG.Depth {1} \ + CONFIG.Width {1} \ + ] $c_shift_ram_0 + + + # Create instance: ilreduced_logic_0, and set properties + set ilreduced_logic_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic:1.0 ilreduced_logic_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $ilreduced_logic_0 + + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {BUFG_FABRIC} $util_ds_buf_0 + + + # Create interface connections + connect_bd_intf_net -intf_net S00_INIS_0_1 [get_bd_intf_ports S_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_s_0/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_1_1 [get_bd_intf_ports S_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_s_1/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_2_1 [get_bd_intf_ports S_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_s_2/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_3_1 [get_bd_intf_ports S_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_s_3/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_4_1 [get_bd_intf_ports S_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_s_4/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_5_1 [get_bd_intf_ports S_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_s_5/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_6_1 [get_bd_intf_ports S_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_s_6/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_7_1 [get_bd_intf_ports S_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_s_7/S00_INIS] + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net axi_noc_0_M00_AXI [get_bd_intf_pins axi_noc_0/M00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_noc_1_M00_INI [get_bd_intf_ports QDMA_SLAVE_BRIDGE_0] [get_bd_intf_pins axi_noc_1/M00_INI] + connect_bd_intf_net -intf_net dcmac_axis_noc_0_M00_INIS [get_bd_intf_ports M_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_0/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_1_M00_INIS [get_bd_intf_ports M_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_1/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_2_M00_INIS [get_bd_intf_ports M_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_2/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_3_M00_INIS [get_bd_intf_ports M_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_3/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_4_M00_INIS [get_bd_intf_ports M_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_4/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_5_M00_INIS [get_bd_intf_ports M_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_5/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_6_M00_INIS [get_bd_intf_ports M_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_6/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_7_M00_INIS [get_bd_intf_ports M_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_7/M00_INIS] + connect_bd_intf_net -intf_net ddr_bandwidth_64_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_64/m_axi_gmem0] [get_bd_intf_pins ddr_noc_0/S00_AXI] + connect_bd_intf_net -intf_net ddr_bandwidth_65_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_65/m_axi_gmem0] [get_bd_intf_pins ddr_noc_1/S00_AXI] + connect_bd_intf_net -intf_net ddr_bandwidth_66_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_66/m_axi_gmem0] [get_bd_intf_pins ddr_noc_2/S00_AXI] + connect_bd_intf_net -intf_net ddr_bandwidth_67_m_axi_gmem0 [get_bd_intf_pins ddr_bandwidth_67/m_axi_gmem0] [get_bd_intf_pins ddr_noc_3/S00_AXI] + connect_bd_intf_net -intf_net ddr_noc_0_M00_INI [get_bd_intf_ports M00_INI] [get_bd_intf_pins ddr_noc_0/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_1_M00_INI [get_bd_intf_ports M01_INI] [get_bd_intf_pins ddr_noc_1/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_2_M00_INI [get_bd_intf_ports M02_INI] [get_bd_intf_pins ddr_noc_2/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_3_M00_INI [get_bd_intf_ports M03_INI] [get_bd_intf_pins ddr_noc_3/M00_INI] + connect_bd_intf_net -intf_net hbm_bandwidth_0_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_0/m_axi_gmem0] [get_bd_intf_pins hbm_sc_00/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_10_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_10/m_axi_gmem0] [get_bd_intf_pins hbm_sc_10/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_11_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_11/m_axi_gmem0] [get_bd_intf_pins hbm_sc_11/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_12_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_12/m_axi_gmem0] [get_bd_intf_pins hbm_sc_12/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_13_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_13/m_axi_gmem0] [get_bd_intf_pins hbm_sc_13/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_14_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_14/m_axi_gmem0] [get_bd_intf_pins hbm_sc_14/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_15_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_15/m_axi_gmem0] [get_bd_intf_pins hbm_sc_15/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_16_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_16/m_axi_gmem0] [get_bd_intf_pins hbm_sc_16/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_17_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_17/m_axi_gmem0] [get_bd_intf_pins hbm_sc_17/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_18_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_18/m_axi_gmem0] [get_bd_intf_pins hbm_sc_18/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_19_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_19/m_axi_gmem0] [get_bd_intf_pins hbm_sc_19/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_1_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_1/m_axi_gmem0] [get_bd_intf_pins hbm_sc_01/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_20_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_20/m_axi_gmem0] [get_bd_intf_pins hbm_sc_20/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_21_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_21/m_axi_gmem0] [get_bd_intf_pins hbm_sc_21/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_22_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_22/m_axi_gmem0] [get_bd_intf_pins hbm_sc_22/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_23_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_23/m_axi_gmem0] [get_bd_intf_pins hbm_sc_23/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_24_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_24/m_axi_gmem0] [get_bd_intf_pins hbm_sc_24/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_25_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_25/m_axi_gmem0] [get_bd_intf_pins hbm_sc_25/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_26_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_26/m_axi_gmem0] [get_bd_intf_pins hbm_sc_26/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_27_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_27/m_axi_gmem0] [get_bd_intf_pins hbm_sc_27/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_28_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_28/m_axi_gmem0] [get_bd_intf_pins hbm_sc_28/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_29_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_29/m_axi_gmem0] [get_bd_intf_pins hbm_sc_29/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_2_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_2/m_axi_gmem0] [get_bd_intf_pins hbm_sc_02/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_30_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_30/m_axi_gmem0] [get_bd_intf_pins hbm_sc_30/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_31_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_31/m_axi_gmem0] [get_bd_intf_pins hbm_sc_31/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_32_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_32/m_axi_gmem0] [get_bd_intf_pins hbm_sc_32/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_33_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_33/m_axi_gmem0] [get_bd_intf_pins hbm_sc_33/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_34_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_34/m_axi_gmem0] [get_bd_intf_pins hbm_sc_34/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_35_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_35/m_axi_gmem0] [get_bd_intf_pins hbm_sc_35/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_36_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_36/m_axi_gmem0] [get_bd_intf_pins hbm_sc_36/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_37_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_37/m_axi_gmem0] [get_bd_intf_pins hbm_sc_37/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_38_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_38/m_axi_gmem0] [get_bd_intf_pins hbm_sc_38/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_39_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_39/m_axi_gmem0] [get_bd_intf_pins hbm_sc_39/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_3_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_3/m_axi_gmem0] [get_bd_intf_pins hbm_sc_03/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_40_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_40/m_axi_gmem0] [get_bd_intf_pins hbm_sc_40/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_41_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_41/m_axi_gmem0] [get_bd_intf_pins hbm_sc_41/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_42_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_42/m_axi_gmem0] [get_bd_intf_pins hbm_sc_42/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_43_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_43/m_axi_gmem0] [get_bd_intf_pins hbm_sc_43/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_44_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_44/m_axi_gmem0] [get_bd_intf_pins hbm_sc_44/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_45_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_45/m_axi_gmem0] [get_bd_intf_pins hbm_sc_45/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_46_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_46/m_axi_gmem0] [get_bd_intf_pins hbm_sc_46/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_47_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_47/m_axi_gmem0] [get_bd_intf_pins hbm_sc_47/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_48_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_48/m_axi_gmem0] [get_bd_intf_pins hbm_sc_48/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_49_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_49/m_axi_gmem0] [get_bd_intf_pins hbm_sc_49/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_4_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_4/m_axi_gmem0] [get_bd_intf_pins hbm_sc_04/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_50_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_50/m_axi_gmem0] [get_bd_intf_pins hbm_sc_50/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_51_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_51/m_axi_gmem0] [get_bd_intf_pins hbm_sc_51/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_52_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_52/m_axi_gmem0] [get_bd_intf_pins hbm_sc_52/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_53_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_53/m_axi_gmem0] [get_bd_intf_pins hbm_sc_53/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_54_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_54/m_axi_gmem0] [get_bd_intf_pins hbm_sc_54/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_55_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_55/m_axi_gmem0] [get_bd_intf_pins hbm_sc_55/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_56_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_56/m_axi_gmem0] [get_bd_intf_pins hbm_sc_56/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_57_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_57/m_axi_gmem0] [get_bd_intf_pins hbm_sc_57/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_58_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_58/m_axi_gmem0] [get_bd_intf_pins hbm_sc_58/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_59_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_59/m_axi_gmem0] [get_bd_intf_pins hbm_sc_59/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_5_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_5/m_axi_gmem0] [get_bd_intf_pins hbm_sc_05/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_60_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_60/m_axi_gmem0] [get_bd_intf_pins hbm_sc_60/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_61_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_61/m_axi_gmem0] [get_bd_intf_pins hbm_sc_61/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_62_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_62/m_axi_gmem0] [get_bd_intf_pins hbm_sc_62/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_63_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_63/m_axi_gmem0] [get_bd_intf_pins hbm_sc_63/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_64_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_64/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_00/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_65_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_65/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_01/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_66_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_66/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_02/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_67_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_67/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_03/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_68_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_68/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_04/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_69_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_69/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_05/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_6_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_6/m_axi_gmem0] [get_bd_intf_pins hbm_sc_06/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_70_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_70/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_06/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_71_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_71/m_axi_gmem0] [get_bd_intf_pins hbm_vnoc_07/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_7_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_7/m_axi_gmem0] [get_bd_intf_pins hbm_sc_07/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_8_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_8/m_axi_gmem0] [get_bd_intf_pins hbm_sc_08/S00_AXI] + connect_bd_intf_net -intf_net hbm_bandwidth_9_m_axi_gmem0 [get_bd_intf_pins hbm_bandwidth_9/m_axi_gmem0] [get_bd_intf_pins hbm_sc_09/S00_AXI] + connect_bd_intf_net -intf_net hbm_sc_01_M00_AXI [get_bd_intf_ports HBM_AXI_01] [get_bd_intf_pins hbm_sc_01/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_02_M00_AXI [get_bd_intf_ports HBM_AXI_02] [get_bd_intf_pins hbm_sc_02/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_03_M00_AXI [get_bd_intf_ports HBM_AXI_03] [get_bd_intf_pins hbm_sc_03/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_04_M00_AXI [get_bd_intf_ports HBM_AXI_04] [get_bd_intf_pins hbm_sc_04/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_05_M00_AXI [get_bd_intf_ports HBM_AXI_05] [get_bd_intf_pins hbm_sc_05/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_06_M00_AXI [get_bd_intf_ports HBM_AXI_06] [get_bd_intf_pins hbm_sc_06/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_07_M00_AXI [get_bd_intf_ports HBM_AXI_07] [get_bd_intf_pins hbm_sc_07/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_08_M00_AXI [get_bd_intf_ports HBM_AXI_08] [get_bd_intf_pins hbm_sc_08/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_09_M00_AXI [get_bd_intf_ports HBM_AXI_09] [get_bd_intf_pins hbm_sc_09/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_0_M00_AXI [get_bd_intf_ports HBM_AXI_00] [get_bd_intf_pins hbm_sc_00/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_10_M00_AXI [get_bd_intf_ports HBM_AXI_10] [get_bd_intf_pins hbm_sc_10/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_11_M00_AXI [get_bd_intf_ports HBM_AXI_11] [get_bd_intf_pins hbm_sc_11/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_12_M00_AXI [get_bd_intf_ports HBM_AXI_12] [get_bd_intf_pins hbm_sc_12/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_13_M00_AXI [get_bd_intf_ports HBM_AXI_13] [get_bd_intf_pins hbm_sc_13/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_14_M00_AXI [get_bd_intf_ports HBM_AXI_14] [get_bd_intf_pins hbm_sc_14/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_15_M00_AXI [get_bd_intf_ports HBM_AXI_15] [get_bd_intf_pins hbm_sc_15/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_16_M00_AXI [get_bd_intf_ports HBM_AXI_16] [get_bd_intf_pins hbm_sc_16/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_17_M00_AXI [get_bd_intf_ports HBM_AXI_17] [get_bd_intf_pins hbm_sc_17/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_18_M00_AXI [get_bd_intf_ports HBM_AXI_18] [get_bd_intf_pins hbm_sc_18/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_19_M00_AXI [get_bd_intf_ports HBM_AXI_19] [get_bd_intf_pins hbm_sc_19/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_20_M00_AXI [get_bd_intf_ports HBM_AXI_20] [get_bd_intf_pins hbm_sc_20/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_21_M00_AXI [get_bd_intf_ports HBM_AXI_21] [get_bd_intf_pins hbm_sc_21/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_22_M00_AXI [get_bd_intf_ports HBM_AXI_22] [get_bd_intf_pins hbm_sc_22/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_23_M00_AXI [get_bd_intf_ports HBM_AXI_23] [get_bd_intf_pins hbm_sc_23/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_24_M00_AXI [get_bd_intf_ports HBM_AXI_24] [get_bd_intf_pins hbm_sc_24/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_25_M00_AXI [get_bd_intf_ports HBM_AXI_25] [get_bd_intf_pins hbm_sc_25/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_26_M00_AXI [get_bd_intf_ports HBM_AXI_26] [get_bd_intf_pins hbm_sc_26/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_27_M00_AXI [get_bd_intf_ports HBM_AXI_27] [get_bd_intf_pins hbm_sc_27/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_28_M00_AXI [get_bd_intf_ports HBM_AXI_28] [get_bd_intf_pins hbm_sc_28/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_29_M00_AXI [get_bd_intf_ports HBM_AXI_29] [get_bd_intf_pins hbm_sc_29/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_30_M00_AXI [get_bd_intf_ports HBM_AXI_30] [get_bd_intf_pins hbm_sc_30/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_31_M00_AXI [get_bd_intf_ports HBM_AXI_31] [get_bd_intf_pins hbm_sc_31/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_32_M00_AXI [get_bd_intf_ports HBM_AXI_32] [get_bd_intf_pins hbm_sc_32/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_33_M00_AXI [get_bd_intf_ports HBM_AXI_33] [get_bd_intf_pins hbm_sc_33/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_34_M00_AXI [get_bd_intf_ports HBM_AXI_34] [get_bd_intf_pins hbm_sc_34/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_35_M00_AXI [get_bd_intf_ports HBM_AXI_35] [get_bd_intf_pins hbm_sc_35/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_36_M00_AXI [get_bd_intf_ports HBM_AXI_36] [get_bd_intf_pins hbm_sc_36/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_37_M00_AXI [get_bd_intf_ports HBM_AXI_37] [get_bd_intf_pins hbm_sc_37/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_38_M00_AXI [get_bd_intf_ports HBM_AXI_38] [get_bd_intf_pins hbm_sc_38/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_39_M00_AXI [get_bd_intf_ports HBM_AXI_39] [get_bd_intf_pins hbm_sc_39/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_40_M00_AXI [get_bd_intf_ports HBM_AXI_40] [get_bd_intf_pins hbm_sc_40/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_41_M00_AXI [get_bd_intf_ports HBM_AXI_41] [get_bd_intf_pins hbm_sc_41/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_42_M00_AXI [get_bd_intf_ports HBM_AXI_42] [get_bd_intf_pins hbm_sc_42/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_43_M00_AXI [get_bd_intf_ports HBM_AXI_43] [get_bd_intf_pins hbm_sc_43/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_44_M00_AXI [get_bd_intf_ports HBM_AXI_44] [get_bd_intf_pins hbm_sc_44/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_45_M00_AXI [get_bd_intf_ports HBM_AXI_45] [get_bd_intf_pins hbm_sc_45/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_46_M00_AXI [get_bd_intf_ports HBM_AXI_46] [get_bd_intf_pins hbm_sc_46/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_47_M00_AXI [get_bd_intf_ports HBM_AXI_47] [get_bd_intf_pins hbm_sc_47/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_48_M00_AXI [get_bd_intf_ports HBM_AXI_48] [get_bd_intf_pins hbm_sc_48/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_49_M00_AXI [get_bd_intf_ports HBM_AXI_49] [get_bd_intf_pins hbm_sc_49/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_50_M00_AXI [get_bd_intf_ports HBM_AXI_50] [get_bd_intf_pins hbm_sc_50/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_51_M00_AXI [get_bd_intf_ports HBM_AXI_51] [get_bd_intf_pins hbm_sc_51/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_52_M00_AXI [get_bd_intf_ports HBM_AXI_52] [get_bd_intf_pins hbm_sc_52/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_53_M00_AXI [get_bd_intf_ports HBM_AXI_53] [get_bd_intf_pins hbm_sc_53/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_54_M00_AXI [get_bd_intf_ports HBM_AXI_54] [get_bd_intf_pins hbm_sc_54/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_55_M00_AXI [get_bd_intf_ports HBM_AXI_55] [get_bd_intf_pins hbm_sc_55/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_56_M00_AXI [get_bd_intf_ports HBM_AXI_56] [get_bd_intf_pins hbm_sc_56/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_57_M00_AXI [get_bd_intf_ports HBM_AXI_57] [get_bd_intf_pins hbm_sc_57/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_58_M00_AXI [get_bd_intf_ports HBM_AXI_58] [get_bd_intf_pins hbm_sc_58/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_59_M00_AXI [get_bd_intf_ports HBM_AXI_59] [get_bd_intf_pins hbm_sc_59/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_60_M00_AXI [get_bd_intf_ports HBM_AXI_60] [get_bd_intf_pins hbm_sc_60/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_61_M00_AXI [get_bd_intf_ports HBM_AXI_61] [get_bd_intf_pins hbm_sc_61/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_62_M00_AXI [get_bd_intf_ports HBM_AXI_62] [get_bd_intf_pins hbm_sc_62/M00_AXI] + connect_bd_intf_net -intf_net hbm_sc_63_M00_AXI [get_bd_intf_ports HBM_AXI_63] [get_bd_intf_pins hbm_sc_63/M00_AXI] + connect_bd_intf_net -intf_net hbm_vnoc_00_M00_INI [get_bd_intf_ports HBM_VNOC_INI_00] [get_bd_intf_pins hbm_vnoc_00/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_01_M00_INI [get_bd_intf_ports HBM_VNOC_INI_01] [get_bd_intf_pins hbm_vnoc_01/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_02_M00_INI [get_bd_intf_ports HBM_VNOC_INI_02] [get_bd_intf_pins hbm_vnoc_02/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_03_M00_INI [get_bd_intf_ports HBM_VNOC_INI_03] [get_bd_intf_pins hbm_vnoc_03/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_04_M00_INI [get_bd_intf_ports HBM_VNOC_INI_04] [get_bd_intf_pins hbm_vnoc_04/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_05_M00_INI [get_bd_intf_ports HBM_VNOC_INI_05] [get_bd_intf_pins hbm_vnoc_05/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_06_M00_INI [get_bd_intf_ports HBM_VNOC_INI_06] [get_bd_intf_pins hbm_vnoc_06/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_07_M00_INI [get_bd_intf_ports HBM_VNOC_INI_07] [get_bd_intf_pins hbm_vnoc_07/M00_INI] + connect_bd_intf_net -intf_net noc_virt_00_M00_INI [get_bd_intf_ports SL_VIRT_00] [get_bd_intf_pins noc_virt_00/M00_INI] + connect_bd_intf_net -intf_net noc_virt_01_M00_INI [get_bd_intf_ports SL_VIRT_01] [get_bd_intf_pins qdma_slave_bridge_noc/M00_INI] + connect_bd_intf_net -intf_net noc_virt_02_M00_INI [get_bd_intf_ports SL_VIRT_02] [get_bd_intf_pins noc_virt_02/M00_INI] + connect_bd_intf_net -intf_net noc_virt_03_M00_INI [get_bd_intf_ports SL_VIRT_03] [get_bd_intf_pins noc_virt_03/M00_INI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins hbm_bandwidth_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins hbm_bandwidth_1/s_axi_control] [get_bd_intf_pins smartconnect_0/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins hbm_bandwidth_2/s_axi_control] [get_bd_intf_pins smartconnect_0/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins hbm_bandwidth_3/s_axi_control] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins hbm_bandwidth_4/s_axi_control] [get_bd_intf_pins smartconnect_0/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins hbm_bandwidth_5/s_axi_control] [get_bd_intf_pins smartconnect_0/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins hbm_bandwidth_6/s_axi_control] [get_bd_intf_pins smartconnect_0/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins hbm_bandwidth_7/s_axi_control] [get_bd_intf_pins smartconnect_0/M07_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M08_AXI [get_bd_intf_pins hbm_bandwidth_8/s_axi_control] [get_bd_intf_pins smartconnect_0/M08_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M09_AXI [get_bd_intf_pins hbm_bandwidth_9/s_axi_control] [get_bd_intf_pins smartconnect_0/M09_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M10_AXI [get_bd_intf_pins hbm_bandwidth_10/s_axi_control] [get_bd_intf_pins smartconnect_0/M10_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M11_AXI [get_bd_intf_pins hbm_bandwidth_11/s_axi_control] [get_bd_intf_pins smartconnect_0/M11_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M12_AXI [get_bd_intf_pins hbm_bandwidth_12/s_axi_control] [get_bd_intf_pins smartconnect_0/M12_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M13_AXI [get_bd_intf_pins hbm_bandwidth_13/s_axi_control] [get_bd_intf_pins smartconnect_0/M13_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M14_AXI [get_bd_intf_pins hbm_bandwidth_14/s_axi_control] [get_bd_intf_pins smartconnect_0/M14_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M15_AXI [get_bd_intf_pins smartconnect_0/M15_AXI] [get_bd_intf_pins smartconnect_1/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins smartconnect_1/M00_AXI] [get_bd_intf_pins hbm_bandwidth_15/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M01_AXI [get_bd_intf_pins smartconnect_1/M01_AXI] [get_bd_intf_pins hbm_bandwidth_16/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M02_AXI [get_bd_intf_pins smartconnect_1/M02_AXI] [get_bd_intf_pins hbm_bandwidth_17/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M03_AXI [get_bd_intf_pins smartconnect_1/M03_AXI] [get_bd_intf_pins hbm_bandwidth_18/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M04_AXI [get_bd_intf_pins smartconnect_1/M04_AXI] [get_bd_intf_pins hbm_bandwidth_19/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M05_AXI [get_bd_intf_pins smartconnect_1/M05_AXI] [get_bd_intf_pins hbm_bandwidth_20/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M06_AXI [get_bd_intf_pins smartconnect_1/M06_AXI] [get_bd_intf_pins hbm_bandwidth_21/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M07_AXI [get_bd_intf_pins smartconnect_1/M07_AXI] [get_bd_intf_pins hbm_bandwidth_22/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M08_AXI [get_bd_intf_pins smartconnect_1/M08_AXI] [get_bd_intf_pins hbm_bandwidth_23/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M09_AXI [get_bd_intf_pins smartconnect_1/M09_AXI] [get_bd_intf_pins hbm_bandwidth_24/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M10_AXI [get_bd_intf_pins smartconnect_1/M10_AXI] [get_bd_intf_pins hbm_bandwidth_25/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M11_AXI [get_bd_intf_pins smartconnect_1/M11_AXI] [get_bd_intf_pins hbm_bandwidth_26/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M12_AXI [get_bd_intf_pins smartconnect_1/M12_AXI] [get_bd_intf_pins hbm_bandwidth_27/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M13_AXI [get_bd_intf_pins smartconnect_1/M13_AXI] [get_bd_intf_pins hbm_bandwidth_28/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M14_AXI [get_bd_intf_pins smartconnect_1/M14_AXI] [get_bd_intf_pins hbm_bandwidth_29/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_2_M15_AXI [get_bd_intf_pins smartconnect_1/M15_AXI] [get_bd_intf_pins smartconnect_2/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_3_M00_AXI [get_bd_intf_pins smartconnect_2/M00_AXI] [get_bd_intf_pins hbm_bandwidth_30/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M01_AXI [get_bd_intf_pins smartconnect_2/M01_AXI] [get_bd_intf_pins hbm_bandwidth_31/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M02_AXI [get_bd_intf_pins smartconnect_2/M02_AXI] [get_bd_intf_pins hbm_bandwidth_32/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M03_AXI [get_bd_intf_pins smartconnect_2/M03_AXI] [get_bd_intf_pins hbm_bandwidth_33/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M04_AXI [get_bd_intf_pins smartconnect_2/M04_AXI] [get_bd_intf_pins hbm_bandwidth_34/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M05_AXI [get_bd_intf_pins smartconnect_2/M05_AXI] [get_bd_intf_pins hbm_bandwidth_35/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M06_AXI [get_bd_intf_pins smartconnect_2/M06_AXI] [get_bd_intf_pins hbm_bandwidth_36/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M07_AXI [get_bd_intf_pins smartconnect_2/M07_AXI] [get_bd_intf_pins hbm_bandwidth_37/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M08_AXI [get_bd_intf_pins smartconnect_2/M08_AXI] [get_bd_intf_pins hbm_bandwidth_38/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M09_AXI [get_bd_intf_pins smartconnect_2/M09_AXI] [get_bd_intf_pins hbm_bandwidth_39/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M10_AXI [get_bd_intf_pins smartconnect_2/M10_AXI] [get_bd_intf_pins hbm_bandwidth_40/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M11_AXI [get_bd_intf_pins smartconnect_2/M11_AXI] [get_bd_intf_pins hbm_bandwidth_41/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M12_AXI [get_bd_intf_pins smartconnect_2/M12_AXI] [get_bd_intf_pins hbm_bandwidth_42/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M13_AXI [get_bd_intf_pins smartconnect_2/M13_AXI] [get_bd_intf_pins hbm_bandwidth_43/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M14_AXI [get_bd_intf_pins smartconnect_2/M14_AXI] [get_bd_intf_pins hbm_bandwidth_44/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_3_M15_AXI [get_bd_intf_pins smartconnect_3/S00_AXI] [get_bd_intf_pins smartconnect_2/M15_AXI] + connect_bd_intf_net -intf_net smartconnect_3_M15_AXI1 [get_bd_intf_pins smartconnect_3/M15_AXI] [get_bd_intf_pins smartconnect_4/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_4_M00_AXI [get_bd_intf_pins smartconnect_3/M00_AXI] [get_bd_intf_pins hbm_bandwidth_45/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M00_AXI1 [get_bd_intf_pins smartconnect_4/M00_AXI] [get_bd_intf_pins hbm_bandwidth_60/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M01_AXI [get_bd_intf_pins smartconnect_3/M01_AXI] [get_bd_intf_pins hbm_bandwidth_46/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M01_AXI1 [get_bd_intf_pins smartconnect_4/M01_AXI] [get_bd_intf_pins hbm_bandwidth_61/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M02_AXI [get_bd_intf_pins smartconnect_3/M02_AXI] [get_bd_intf_pins hbm_bandwidth_47/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M02_AXI1 [get_bd_intf_pins smartconnect_4/M02_AXI] [get_bd_intf_pins hbm_bandwidth_62/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M03_AXI [get_bd_intf_pins smartconnect_3/M03_AXI] [get_bd_intf_pins hbm_bandwidth_48/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M03_AXI1 [get_bd_intf_pins smartconnect_4/M03_AXI] [get_bd_intf_pins hbm_bandwidth_63/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M04_AXI [get_bd_intf_pins smartconnect_3/M04_AXI] [get_bd_intf_pins hbm_bandwidth_49/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M04_AXI1 [get_bd_intf_pins smartconnect_4/M04_AXI] [get_bd_intf_pins hbm_bandwidth_64/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M05_AXI [get_bd_intf_pins smartconnect_3/M05_AXI] [get_bd_intf_pins hbm_bandwidth_50/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M05_AXI1 [get_bd_intf_pins smartconnect_4/M05_AXI] [get_bd_intf_pins hbm_bandwidth_65/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M06_AXI [get_bd_intf_pins smartconnect_3/M06_AXI] [get_bd_intf_pins hbm_bandwidth_51/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M06_AXI1 [get_bd_intf_pins smartconnect_4/M06_AXI] [get_bd_intf_pins hbm_bandwidth_66/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M07_AXI [get_bd_intf_pins smartconnect_3/M07_AXI] [get_bd_intf_pins hbm_bandwidth_52/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M07_AXI1 [get_bd_intf_pins smartconnect_4/M07_AXI] [get_bd_intf_pins hbm_bandwidth_67/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M08_AXI [get_bd_intf_pins smartconnect_3/M08_AXI] [get_bd_intf_pins hbm_bandwidth_53/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M08_AXI1 [get_bd_intf_pins smartconnect_4/M08_AXI] [get_bd_intf_pins hbm_bandwidth_68/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M09_AXI [get_bd_intf_pins smartconnect_3/M09_AXI] [get_bd_intf_pins hbm_bandwidth_54/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M09_AXI1 [get_bd_intf_pins smartconnect_4/M09_AXI] [get_bd_intf_pins hbm_bandwidth_69/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M10_AXI [get_bd_intf_pins smartconnect_3/M10_AXI] [get_bd_intf_pins hbm_bandwidth_55/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M10_AXI1 [get_bd_intf_pins smartconnect_4/M10_AXI] [get_bd_intf_pins hbm_bandwidth_70/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M11_AXI [get_bd_intf_pins smartconnect_3/M11_AXI] [get_bd_intf_pins hbm_bandwidth_56/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M11_AXI1 [get_bd_intf_pins smartconnect_4/M11_AXI] [get_bd_intf_pins hbm_bandwidth_71/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M12_AXI [get_bd_intf_pins smartconnect_3/M12_AXI] [get_bd_intf_pins hbm_bandwidth_57/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M12_AXI1 [get_bd_intf_pins smartconnect_4/M12_AXI] [get_bd_intf_pins ddr_bandwidth_64/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M13_AXI [get_bd_intf_pins smartconnect_3/M13_AXI] [get_bd_intf_pins hbm_bandwidth_58/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M13_AXI1 [get_bd_intf_pins smartconnect_4/M13_AXI] [get_bd_intf_pins ddr_bandwidth_65/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M14_AXI [get_bd_intf_pins smartconnect_3/M14_AXI] [get_bd_intf_pins hbm_bandwidth_59/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M14_AXI1 [get_bd_intf_pins smartconnect_4/M14_AXI] [get_bd_intf_pins ddr_bandwidth_66/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_4_M15_AXI [get_bd_intf_pins smartconnect_5/S00_AXI] [get_bd_intf_pins smartconnect_4/M15_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M00_AXI [get_bd_intf_pins smartconnect_5/M00_AXI] [get_bd_intf_pins ddr_bandwidth_67/s_axi_control] + connect_bd_intf_net -intf_net smartconnect_5_M01_AXI [get_bd_intf_pins traffic_producer_0/s_axi_control] [get_bd_intf_pins smartconnect_5/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M02_AXI [get_bd_intf_pins traffic_producer_1/s_axi_control] [get_bd_intf_pins smartconnect_5/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M03_AXI [get_bd_intf_pins traffic_producer_2/s_axi_control] [get_bd_intf_pins smartconnect_5/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M04_AXI [get_bd_intf_pins traffic_producer_3/s_axi_control] [get_bd_intf_pins smartconnect_5/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M05_AXI [get_bd_intf_pins traffic_producer_4/s_axi_control] [get_bd_intf_pins smartconnect_5/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M06_AXI [get_bd_intf_pins traffic_producer_5/s_axi_control] [get_bd_intf_pins smartconnect_5/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M07_AXI [get_bd_intf_pins traffic_producer_6/s_axi_control] [get_bd_intf_pins smartconnect_5/M07_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M08_AXI [get_bd_intf_pins traffic_producer_7/s_axi_control] [get_bd_intf_pins smartconnect_5/M08_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M09_AXI [get_bd_intf_pins traffic_virt_0/s_axi_control] [get_bd_intf_pins smartconnect_5/M09_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M10_AXI [get_bd_intf_pins traffic_virt_1/s_axi_control] [get_bd_intf_pins smartconnect_5/M10_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M11_AXI [get_bd_intf_pins traffic_virt_2/s_axi_control] [get_bd_intf_pins smartconnect_5/M11_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M12_AXI [get_bd_intf_pins traffic_virt_3/s_axi_control] [get_bd_intf_pins smartconnect_5/M12_AXI] + connect_bd_intf_net -intf_net smartconnect_5_M13_AXI [get_bd_intf_pins traffic_virt_4/s_axi_control] [get_bd_intf_pins smartconnect_5/M13_AXI] + connect_bd_intf_net -intf_net traffic_producer_0_axis_out [get_bd_intf_pins traffic_producer_0/axis_out] [get_bd_intf_pins dcmac_axis_noc_0/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_1_axis_out [get_bd_intf_pins traffic_producer_1/axis_out] [get_bd_intf_pins dcmac_axis_noc_1/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_2_axis_out [get_bd_intf_pins traffic_producer_2/axis_out] [get_bd_intf_pins dcmac_axis_noc_2/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_3_axis_out [get_bd_intf_pins traffic_producer_3/axis_out] [get_bd_intf_pins dcmac_axis_noc_3/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_4_axis_out [get_bd_intf_pins traffic_producer_4/axis_out] [get_bd_intf_pins dcmac_axis_noc_4/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_5_axis_out [get_bd_intf_pins traffic_producer_5/axis_out] [get_bd_intf_pins dcmac_axis_noc_5/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_6_axis_out [get_bd_intf_pins traffic_producer_6/axis_out] [get_bd_intf_pins dcmac_axis_noc_6/S00_AXIS] + connect_bd_intf_net -intf_net traffic_producer_7_axis_out [get_bd_intf_pins traffic_producer_7/axis_out] [get_bd_intf_pins dcmac_axis_noc_7/S00_AXIS] + connect_bd_intf_net -intf_net traffic_virt_0_m_axi_gmem0 [get_bd_intf_pins noc_virt_00/S00_AXI] [get_bd_intf_pins traffic_virt_0/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_1_m_axi_gmem0 [get_bd_intf_pins qdma_slave_bridge_noc/S00_AXI] [get_bd_intf_pins traffic_virt_1/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_2_m_axi_gmem0 [get_bd_intf_pins noc_virt_02/S00_AXI] [get_bd_intf_pins traffic_virt_2/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_3_m_axi_gmem0 [get_bd_intf_pins noc_virt_03/S00_AXI] [get_bd_intf_pins traffic_virt_3/m_axi_gmem0] + connect_bd_intf_net -intf_net traffic_virt_4_m_axi_gmem0 [get_bd_intf_pins axi_noc_1/S00_AXI] [get_bd_intf_pins traffic_virt_4/m_axi_gmem0] + + # Create port connections + connect_bd_net -net arstn_1 [get_bd_ports arstn] \ + [get_bd_pins c_shift_ram_0/D] + connect_bd_net -net c_shift_ram_0_Q [get_bd_pins c_shift_ram_0/Q] \ + [get_bd_pins util_ds_buf_0/BUFG_FABRIC_I] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_ports user_clk] \ + [get_bd_pins ddr_noc_0/aclk0] \ + [get_bd_pins ddr_noc_3/aclk0] \ + [get_bd_pins ddr_noc_2/aclk0] \ + [get_bd_pins ddr_noc_1/aclk0] \ + [get_bd_pins hbm_vnoc_00/aclk0] \ + [get_bd_pins hbm_vnoc_01/aclk0] \ + [get_bd_pins hbm_vnoc_02/aclk0] \ + [get_bd_pins hbm_vnoc_03/aclk0] \ + [get_bd_pins hbm_vnoc_04/aclk0] \ + [get_bd_pins hbm_vnoc_05/aclk0] \ + [get_bd_pins hbm_vnoc_06/aclk0] \ + [get_bd_pins hbm_vnoc_07/aclk0] \ + [get_bd_pins dcmac_axis_noc_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_7/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_7/aclk0] \ + [get_bd_pins traffic_producer_0/ap_clk] \ + [get_bd_pins traffic_producer_1/ap_clk] \ + [get_bd_pins traffic_producer_2/ap_clk] \ + [get_bd_pins traffic_producer_3/ap_clk] \ + [get_bd_pins traffic_producer_4/ap_clk] \ + [get_bd_pins traffic_producer_5/ap_clk] \ + [get_bd_pins traffic_producer_6/ap_clk] \ + [get_bd_pins traffic_producer_7/ap_clk] \ + [get_bd_pins ddr_bandwidth_64/ap_clk] \ + [get_bd_pins ddr_bandwidth_65/ap_clk] \ + [get_bd_pins ddr_bandwidth_66/ap_clk] \ + [get_bd_pins ddr_bandwidth_67/ap_clk] \ + [get_bd_pins hbm_bandwidth_0/ap_clk] \ + [get_bd_pins hbm_bandwidth_10/ap_clk] \ + [get_bd_pins hbm_bandwidth_11/ap_clk] \ + [get_bd_pins hbm_bandwidth_12/ap_clk] \ + [get_bd_pins hbm_bandwidth_13/ap_clk] \ + [get_bd_pins hbm_bandwidth_14/ap_clk] \ + [get_bd_pins hbm_bandwidth_15/ap_clk] \ + [get_bd_pins hbm_bandwidth_16/ap_clk] \ + [get_bd_pins hbm_bandwidth_17/ap_clk] \ + [get_bd_pins hbm_bandwidth_18/ap_clk] \ + [get_bd_pins hbm_bandwidth_19/ap_clk] \ + [get_bd_pins hbm_bandwidth_1/ap_clk] \ + [get_bd_pins hbm_bandwidth_20/ap_clk] \ + [get_bd_pins hbm_bandwidth_21/ap_clk] \ + [get_bd_pins hbm_bandwidth_22/ap_clk] \ + [get_bd_pins hbm_bandwidth_23/ap_clk] \ + [get_bd_pins hbm_bandwidth_24/ap_clk] \ + [get_bd_pins hbm_bandwidth_25/ap_clk] \ + [get_bd_pins hbm_bandwidth_26/ap_clk] \ + [get_bd_pins hbm_bandwidth_27/ap_clk] \ + [get_bd_pins hbm_bandwidth_28/ap_clk] \ + [get_bd_pins hbm_bandwidth_29/ap_clk] \ + [get_bd_pins hbm_bandwidth_2/ap_clk] \ + [get_bd_pins hbm_bandwidth_30/ap_clk] \ + [get_bd_pins hbm_bandwidth_31/ap_clk] \ + [get_bd_pins hbm_bandwidth_32/ap_clk] \ + [get_bd_pins hbm_bandwidth_33/ap_clk] \ + [get_bd_pins hbm_bandwidth_34/ap_clk] \ + [get_bd_pins hbm_bandwidth_35/ap_clk] \ + [get_bd_pins hbm_bandwidth_36/ap_clk] \ + [get_bd_pins hbm_bandwidth_37/ap_clk] \ + [get_bd_pins hbm_bandwidth_38/ap_clk] \ + [get_bd_pins hbm_bandwidth_39/ap_clk] \ + [get_bd_pins hbm_bandwidth_3/ap_clk] \ + [get_bd_pins hbm_bandwidth_40/ap_clk] \ + [get_bd_pins hbm_bandwidth_41/ap_clk] \ + [get_bd_pins hbm_bandwidth_42/ap_clk] \ + [get_bd_pins hbm_bandwidth_43/ap_clk] \ + [get_bd_pins hbm_bandwidth_44/ap_clk] \ + [get_bd_pins hbm_bandwidth_45/ap_clk] \ + [get_bd_pins hbm_bandwidth_46/ap_clk] \ + [get_bd_pins hbm_bandwidth_47/ap_clk] \ + [get_bd_pins hbm_bandwidth_48/ap_clk] \ + [get_bd_pins hbm_bandwidth_49/ap_clk] \ + [get_bd_pins hbm_bandwidth_4/ap_clk] \ + [get_bd_pins hbm_bandwidth_50/ap_clk] \ + [get_bd_pins hbm_bandwidth_51/ap_clk] \ + [get_bd_pins hbm_bandwidth_52/ap_clk] \ + [get_bd_pins hbm_bandwidth_53/ap_clk] \ + [get_bd_pins hbm_bandwidth_54/ap_clk] \ + [get_bd_pins hbm_bandwidth_55/ap_clk] \ + [get_bd_pins hbm_bandwidth_56/ap_clk] \ + [get_bd_pins hbm_bandwidth_57/ap_clk] \ + [get_bd_pins hbm_bandwidth_58/ap_clk] \ + [get_bd_pins hbm_bandwidth_59/ap_clk] \ + [get_bd_pins hbm_bandwidth_5/ap_clk] \ + [get_bd_pins hbm_bandwidth_60/ap_clk] \ + [get_bd_pins hbm_bandwidth_61/ap_clk] \ + [get_bd_pins hbm_bandwidth_62/ap_clk] \ + [get_bd_pins hbm_bandwidth_63/ap_clk] \ + [get_bd_pins hbm_bandwidth_64/ap_clk] \ + [get_bd_pins hbm_bandwidth_65/ap_clk] \ + [get_bd_pins hbm_bandwidth_66/ap_clk] \ + [get_bd_pins hbm_bandwidth_67/ap_clk] \ + [get_bd_pins hbm_bandwidth_68/ap_clk] \ + [get_bd_pins hbm_bandwidth_69/ap_clk] \ + [get_bd_pins hbm_bandwidth_6/ap_clk] \ + [get_bd_pins hbm_bandwidth_70/ap_clk] \ + [get_bd_pins hbm_bandwidth_71/ap_clk] \ + [get_bd_pins hbm_bandwidth_7/ap_clk] \ + [get_bd_pins hbm_bandwidth_8/ap_clk] \ + [get_bd_pins hbm_bandwidth_9/ap_clk] \ + [get_bd_pins traffic_virt_0/ap_clk] \ + [get_bd_pins traffic_virt_1/ap_clk] \ + [get_bd_pins traffic_virt_2/ap_clk] \ + [get_bd_pins traffic_virt_3/ap_clk] \ + [get_bd_pins traffic_virt_4/ap_clk] \ + [get_bd_pins smartconnect_1/aclk1] \ + [get_bd_pins smartconnect_0/aclk] \ + [get_bd_pins smartconnect_1/aclk] \ + [get_bd_pins smartconnect_2/aclk] \ + [get_bd_pins smartconnect_3/aclk] \ + [get_bd_pins smartconnect_4/aclk] \ + [get_bd_pins smartconnect_5/aclk] \ + [get_bd_pins hbm_sc_00/aclk] \ + [get_bd_pins hbm_sc_01/aclk] \ + [get_bd_pins hbm_sc_02/aclk] \ + [get_bd_pins hbm_sc_03/aclk] \ + [get_bd_pins hbm_sc_04/aclk] \ + [get_bd_pins hbm_sc_05/aclk] \ + [get_bd_pins hbm_sc_06/aclk] \ + [get_bd_pins hbm_sc_07/aclk] \ + [get_bd_pins hbm_sc_08/aclk] \ + [get_bd_pins hbm_sc_09/aclk] \ + [get_bd_pins hbm_sc_10/aclk] \ + [get_bd_pins hbm_sc_11/aclk] \ + [get_bd_pins hbm_sc_12/aclk] \ + [get_bd_pins hbm_sc_13/aclk] \ + [get_bd_pins hbm_sc_14/aclk] \ + [get_bd_pins hbm_sc_15/aclk] \ + [get_bd_pins hbm_sc_16/aclk] \ + [get_bd_pins hbm_sc_17/aclk] \ + [get_bd_pins hbm_sc_18/aclk] \ + [get_bd_pins hbm_sc_19/aclk] \ + [get_bd_pins hbm_sc_20/aclk] \ + [get_bd_pins hbm_sc_21/aclk] \ + [get_bd_pins hbm_sc_22/aclk] \ + [get_bd_pins hbm_sc_23/aclk] \ + [get_bd_pins hbm_sc_24/aclk] \ + [get_bd_pins hbm_sc_25/aclk] \ + [get_bd_pins hbm_sc_26/aclk] \ + [get_bd_pins hbm_sc_27/aclk] \ + [get_bd_pins hbm_sc_28/aclk] \ + [get_bd_pins hbm_sc_29/aclk] \ + [get_bd_pins hbm_sc_30/aclk] \ + [get_bd_pins hbm_sc_31/aclk] \ + [get_bd_pins hbm_sc_32/aclk] \ + [get_bd_pins hbm_sc_33/aclk] \ + [get_bd_pins hbm_sc_34/aclk] \ + [get_bd_pins hbm_sc_35/aclk] \ + [get_bd_pins hbm_sc_36/aclk] \ + [get_bd_pins hbm_sc_37/aclk] \ + [get_bd_pins hbm_sc_38/aclk] \ + [get_bd_pins hbm_sc_39/aclk] \ + [get_bd_pins hbm_sc_40/aclk] \ + [get_bd_pins hbm_sc_41/aclk] \ + [get_bd_pins hbm_sc_42/aclk] \ + [get_bd_pins hbm_sc_43/aclk] \ + [get_bd_pins hbm_sc_44/aclk] \ + [get_bd_pins hbm_sc_45/aclk] \ + [get_bd_pins hbm_sc_46/aclk] \ + [get_bd_pins hbm_sc_47/aclk] \ + [get_bd_pins hbm_sc_48/aclk] \ + [get_bd_pins hbm_sc_49/aclk] \ + [get_bd_pins hbm_sc_50/aclk] \ + [get_bd_pins hbm_sc_51/aclk] \ + [get_bd_pins hbm_sc_52/aclk] \ + [get_bd_pins hbm_sc_53/aclk] \ + [get_bd_pins hbm_sc_54/aclk] \ + [get_bd_pins hbm_sc_55/aclk] \ + [get_bd_pins hbm_sc_56/aclk] \ + [get_bd_pins hbm_sc_57/aclk] \ + [get_bd_pins hbm_sc_58/aclk] \ + [get_bd_pins hbm_sc_59/aclk] \ + [get_bd_pins hbm_sc_60/aclk] \ + [get_bd_pins hbm_sc_61/aclk] \ + [get_bd_pins hbm_sc_62/aclk] \ + [get_bd_pins hbm_sc_63/aclk] \ + [get_bd_pins noc_virt_00/aclk0] \ + [get_bd_pins qdma_slave_bridge_noc/aclk0] \ + [get_bd_pins noc_virt_02/aclk0] \ + [get_bd_pins noc_virt_03/aclk0] \ + [get_bd_pins axi_noc_1/aclk0] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins c_shift_ram_0/CLK] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ilreduced_logic_0/Res] \ + [get_bd_pins smartconnect_0/aresetn] \ + [get_bd_pins smartconnect_1/aresetn] \ + [get_bd_pins smartconnect_2/aresetn] \ + [get_bd_pins smartconnect_3/aresetn] \ + [get_bd_pins smartconnect_4/aresetn] \ + [get_bd_pins smartconnect_5/aresetn] \ + [get_bd_pins traffic_producer_0/ap_rst_n] \ + [get_bd_pins traffic_producer_1/ap_rst_n] \ + [get_bd_pins traffic_producer_2/ap_rst_n] \ + [get_bd_pins traffic_producer_3/ap_rst_n] \ + [get_bd_pins traffic_producer_4/ap_rst_n] \ + [get_bd_pins traffic_producer_5/ap_rst_n] \ + [get_bd_pins traffic_producer_6/ap_rst_n] \ + [get_bd_pins traffic_producer_7/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_64/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_65/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_66/ap_rst_n] \ + [get_bd_pins ddr_bandwidth_67/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_0/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_10/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_11/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_12/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_13/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_14/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_15/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_16/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_17/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_18/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_19/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_1/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_20/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_21/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_22/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_23/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_24/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_25/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_26/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_27/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_28/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_29/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_2/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_30/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_31/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_32/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_33/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_34/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_35/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_36/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_37/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_38/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_39/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_3/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_40/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_41/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_42/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_43/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_44/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_45/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_46/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_47/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_48/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_49/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_4/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_50/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_51/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_52/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_53/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_54/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_55/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_56/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_57/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_58/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_59/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_5/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_60/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_61/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_62/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_63/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_64/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_65/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_66/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_67/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_68/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_69/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_6/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_70/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_71/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_7/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_8/ap_rst_n] \ + [get_bd_pins hbm_bandwidth_9/ap_rst_n] \ + [get_bd_pins traffic_virt_0/ap_rst_n] \ + [get_bd_pins traffic_virt_1/ap_rst_n] \ + [get_bd_pins traffic_virt_2/ap_rst_n] \ + [get_bd_pins traffic_virt_3/ap_rst_n] \ + [get_bd_pins traffic_virt_4/ap_rst_n] \ + [get_bd_pins hbm_sc_00/aresetn] \ + [get_bd_pins hbm_sc_01/aresetn] \ + [get_bd_pins hbm_sc_02/aresetn] \ + [get_bd_pins hbm_sc_03/aresetn] \ + [get_bd_pins hbm_sc_04/aresetn] \ + [get_bd_pins hbm_sc_05/aresetn] \ + [get_bd_pins hbm_sc_06/aresetn] \ + [get_bd_pins hbm_sc_07/aresetn] \ + [get_bd_pins hbm_sc_08/aresetn] \ + [get_bd_pins hbm_sc_09/aresetn] \ + [get_bd_pins hbm_sc_10/aresetn] \ + [get_bd_pins hbm_sc_11/aresetn] \ + [get_bd_pins hbm_sc_12/aresetn] \ + [get_bd_pins hbm_sc_13/aresetn] \ + [get_bd_pins hbm_sc_14/aresetn] \ + [get_bd_pins hbm_sc_15/aresetn] \ + [get_bd_pins hbm_sc_16/aresetn] \ + [get_bd_pins hbm_sc_17/aresetn] \ + [get_bd_pins hbm_sc_18/aresetn] \ + [get_bd_pins hbm_sc_19/aresetn] \ + [get_bd_pins hbm_sc_20/aresetn] \ + [get_bd_pins hbm_sc_21/aresetn] \ + [get_bd_pins hbm_sc_22/aresetn] \ + [get_bd_pins hbm_sc_23/aresetn] \ + [get_bd_pins hbm_sc_24/aresetn] \ + [get_bd_pins hbm_sc_25/aresetn] \ + [get_bd_pins hbm_sc_26/aresetn] \ + [get_bd_pins hbm_sc_27/aresetn] \ + [get_bd_pins hbm_sc_28/aresetn] \ + [get_bd_pins hbm_sc_29/aresetn] \ + [get_bd_pins hbm_sc_30/aresetn] \ + [get_bd_pins hbm_sc_31/aresetn] \ + [get_bd_pins hbm_sc_32/aresetn] \ + [get_bd_pins hbm_sc_33/aresetn] \ + [get_bd_pins hbm_sc_34/aresetn] \ + [get_bd_pins hbm_sc_35/aresetn] \ + [get_bd_pins hbm_sc_36/aresetn] \ + [get_bd_pins hbm_sc_37/aresetn] \ + [get_bd_pins hbm_sc_38/aresetn] \ + [get_bd_pins hbm_sc_39/aresetn] \ + [get_bd_pins hbm_sc_40/aresetn] \ + [get_bd_pins hbm_sc_41/aresetn] \ + [get_bd_pins hbm_sc_42/aresetn] \ + [get_bd_pins hbm_sc_43/aresetn] \ + [get_bd_pins hbm_sc_44/aresetn] \ + [get_bd_pins hbm_sc_45/aresetn] \ + [get_bd_pins hbm_sc_46/aresetn] \ + [get_bd_pins hbm_sc_47/aresetn] \ + [get_bd_pins hbm_sc_48/aresetn] \ + [get_bd_pins hbm_sc_49/aresetn] \ + [get_bd_pins hbm_sc_50/aresetn] \ + [get_bd_pins hbm_sc_51/aresetn] \ + [get_bd_pins hbm_sc_52/aresetn] \ + [get_bd_pins hbm_sc_53/aresetn] \ + [get_bd_pins hbm_sc_54/aresetn] \ + [get_bd_pins hbm_sc_55/aresetn] \ + [get_bd_pins hbm_sc_56/aresetn] \ + [get_bd_pins hbm_sc_57/aresetn] \ + [get_bd_pins hbm_sc_58/aresetn] \ + [get_bd_pins hbm_sc_59/aresetn] \ + [get_bd_pins hbm_sc_60/aresetn] \ + [get_bd_pins hbm_sc_61/aresetn] \ + [get_bd_pins hbm_sc_62/aresetn] \ + [get_bd_pins hbm_sc_63/aresetn] + connect_bd_net -net static_region_clk_1 [get_bd_ports static_region_clk] \ + [get_bd_pins hbm_sc_00/aclk1] \ + [get_bd_pins hbm_sc_01/aclk1] \ + [get_bd_pins hbm_sc_02/aclk1] \ + [get_bd_pins hbm_sc_03/aclk1] \ + [get_bd_pins hbm_sc_04/aclk1] \ + [get_bd_pins hbm_sc_05/aclk1] \ + [get_bd_pins hbm_sc_06/aclk1] \ + [get_bd_pins hbm_sc_07/aclk1] \ + [get_bd_pins hbm_sc_08/aclk1] \ + [get_bd_pins hbm_sc_09/aclk1] \ + [get_bd_pins hbm_sc_10/aclk1] \ + [get_bd_pins hbm_sc_11/aclk1] \ + [get_bd_pins hbm_sc_12/aclk1] \ + [get_bd_pins hbm_sc_13/aclk1] \ + [get_bd_pins hbm_sc_14/aclk1] \ + [get_bd_pins hbm_sc_15/aclk1] \ + [get_bd_pins hbm_sc_16/aclk1] \ + [get_bd_pins hbm_sc_17/aclk1] \ + [get_bd_pins hbm_sc_18/aclk1] \ + [get_bd_pins hbm_sc_19/aclk1] \ + [get_bd_pins hbm_sc_20/aclk1] \ + [get_bd_pins hbm_sc_21/aclk1] \ + [get_bd_pins hbm_sc_22/aclk1] \ + [get_bd_pins hbm_sc_23/aclk1] \ + [get_bd_pins hbm_sc_24/aclk1] \ + [get_bd_pins hbm_sc_25/aclk1] \ + [get_bd_pins hbm_sc_26/aclk1] \ + [get_bd_pins hbm_sc_27/aclk1] \ + [get_bd_pins hbm_sc_28/aclk1] \ + [get_bd_pins hbm_sc_29/aclk1] \ + [get_bd_pins hbm_sc_30/aclk1] \ + [get_bd_pins hbm_sc_31/aclk1] \ + [get_bd_pins hbm_sc_32/aclk1] \ + [get_bd_pins hbm_sc_33/aclk1] \ + [get_bd_pins hbm_sc_34/aclk1] \ + [get_bd_pins hbm_sc_35/aclk1] \ + [get_bd_pins hbm_sc_36/aclk1] \ + [get_bd_pins hbm_sc_37/aclk1] \ + [get_bd_pins hbm_sc_38/aclk1] \ + [get_bd_pins hbm_sc_39/aclk1] \ + [get_bd_pins hbm_sc_40/aclk1] \ + [get_bd_pins hbm_sc_41/aclk1] \ + [get_bd_pins hbm_sc_42/aclk1] \ + [get_bd_pins hbm_sc_43/aclk1] \ + [get_bd_pins hbm_sc_44/aclk1] \ + [get_bd_pins hbm_sc_45/aclk1] \ + [get_bd_pins hbm_sc_46/aclk1] \ + [get_bd_pins hbm_sc_47/aclk1] \ + [get_bd_pins hbm_sc_48/aclk1] \ + [get_bd_pins hbm_sc_49/aclk1] \ + [get_bd_pins hbm_sc_50/aclk1] \ + [get_bd_pins hbm_sc_51/aclk1] \ + [get_bd_pins hbm_sc_52/aclk1] \ + [get_bd_pins hbm_sc_53/aclk1] \ + [get_bd_pins hbm_sc_54/aclk1] \ + [get_bd_pins hbm_sc_55/aclk1] \ + [get_bd_pins hbm_sc_56/aclk1] \ + [get_bd_pins hbm_sc_57/aclk1] \ + [get_bd_pins hbm_sc_58/aclk1] \ + [get_bd_pins hbm_sc_59/aclk1] \ + [get_bd_pins hbm_sc_60/aclk1] \ + [get_bd_pins hbm_sc_61/aclk1] \ + [get_bd_pins hbm_sc_62/aclk1] \ + [get_bd_pins hbm_sc_63/aclk1] + connect_bd_net -net util_ds_buf_0_BUFG_FABRIC_O [get_bd_pins util_ds_buf_0/BUFG_FABRIC_O] \ + [get_bd_pins ilreduced_logic_0/Op1] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] \ + [get_bd_pins dcmac_axis_noc_s_0/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_1/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_2/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_3/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_4/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_5/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_6/M00_AXIS_tready] \ + [get_bd_pins dcmac_axis_noc_s_7/M00_AXIS_tready] + + # Create address segments + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs M00_INI/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs M01_INI/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs M02_INI/Reg] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs M03_INI/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_0/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_00/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_1/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_01/Reg] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_10/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_10/Reg] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_11/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_11/Reg] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_12/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_12/Reg] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_13/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_13/Reg] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_14/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_14/Reg] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM3_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_15/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_15/Reg] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_16/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_16/Reg] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_17/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_17/Reg] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_18/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_18/Reg] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM4_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_19/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_19/Reg] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_2/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_02/Reg] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_20/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_20/Reg] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_21/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_21/Reg] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_22/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_22/Reg] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM5_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_23/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_23/Reg] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_24/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_24/Reg] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_25/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_25/Reg] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_26/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_26/Reg] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM6_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_27/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_27/Reg] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_28/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_28/Reg] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_29/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_29/Reg] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM0_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_3/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_03/Reg] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_30/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_30/Reg] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM7_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_31/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_31/Reg] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_32/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_32/Reg] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_33/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_33/Reg] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_34/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_34/Reg] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM8_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_35/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_35/Reg] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_36/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_36/Reg] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_37/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_37/Reg] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_38/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_38/Reg] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM9_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_39/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_39/Reg] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_4/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_04/Reg] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_40/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_40/Reg] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_41/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_41/Reg] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_42/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_42/Reg] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM10_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_43/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_43/Reg] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_44/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_44/Reg] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_45/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_45/Reg] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_46/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_46/Reg] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM11_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_47/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_47/Reg] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_48/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_48/Reg] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_49/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_49/Reg] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_5/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_05/Reg] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_50/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_50/Reg] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM12_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_51/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_51/Reg] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_52/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_52/Reg] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_53/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_53/Reg] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_54/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_54/Reg] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM13_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_55/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_55/Reg] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_56/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_56/Reg] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_57/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_57/Reg] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_58/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_58/Reg] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM14_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_59/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_59/Reg] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_6/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_06/Reg] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_60/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_60/Reg] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_61/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_61/Reg] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_62/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_62/Reg] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM15_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_63/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_63/Reg] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM1_PC1 -target_address_space [get_bd_addr_spaces hbm_bandwidth_7/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_07/Reg] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_8/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_08/Reg] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -with_name SEG_axi_noc_cips_HBM2_PC0 -target_address_space [get_bd_addr_spaces hbm_bandwidth_9/Data_m_axi_gmem0] [get_bd_addr_segs HBM_AXI_09/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_00/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_01/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_02/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_03/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_04/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_05/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_06/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs HBM_VNOC_INI_07/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_VIRT_0_Reg -target_address_space [get_bd_addr_spaces traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_00/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_VIRT_1_Reg -target_address_space [get_bd_addr_spaces traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_01/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_VIRT_2_Reg -target_address_space [get_bd_addr_spaces traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_02/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_SL_VIRT_3_Reg -target_address_space [get_bd_addr_spaces traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs SL_VIRT_03/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -with_name SEG_QDMA_SLAVE_BRIDGE_Reg -target_address_space [get_bd_addr_spaces traffic_virt_4/Data_m_axi_gmem0] [get_bd_addr_segs QDMA_SLAVE_BRIDGE_0/Reg] -force + assign_bd_address -offset 0x020200480000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200490000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ddr_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_10/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_11/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_12/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_13/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_14/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_15/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_16/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_17/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_18/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_19/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_20/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_21/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_22/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200170000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_23/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200180000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_24/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_25/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_26/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_27/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_28/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_29/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_30/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_31/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_32/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_33/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_34/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_35/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_36/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_37/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_38/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200270000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_39/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200280000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_40/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200290000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_41/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_42/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_43/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_44/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_45/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_46/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_47/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_48/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_49/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_50/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200330000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_51/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200340000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_52/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200350000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_53/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_54/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_55/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_56/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_57/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_58/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_59/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_60/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_61/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_62/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_63/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200410000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200420000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200430000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_68/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_69/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200460000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_70/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200470000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_71/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_8/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs hbm_bandwidth_9/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200510000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200520000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200530000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200540000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200550000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200560000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200570000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200580000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs traffic_virt_4/s_axi_control/Reg] -force + + set_property USAGE memory [get_bd_addr_segs HBM_AXI_00/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_01/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_10/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_11/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_12/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_13/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_14/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_15/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_16/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_17/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_18/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_19/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_02/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_20/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_21/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_22/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_23/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_24/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_25/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_26/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_27/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_28/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_29/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_03/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_30/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_31/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_32/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_33/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_34/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_35/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_36/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_37/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_38/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_39/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_04/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_40/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_41/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_42/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_43/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_44/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_45/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_46/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_47/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_48/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_49/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_05/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_50/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_51/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_52/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_53/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_54/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_55/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_56/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_57/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_58/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_59/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_06/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_60/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_61/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_62/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_63/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_07/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_08/Reg] + set_property USAGE memory [get_bd_addr_segs HBM_AXI_09/Reg] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/linker/slashkit/resources/base/scripts/slash_project_build.tcl b/linker/slashkit/resources/base/scripts/slash_project_build.tcl new file mode 100644 index 00000000..e0ab1d92 --- /dev/null +++ b/linker/slashkit/resources/base/scripts/slash_project_build.tcl @@ -0,0 +1,172 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +proc _slash_usage {} { + return "Expected -tclargs: --project-name --ip-repo --static-shell-dcp --base-bd --linker-results-dir --rm-work-dir --artifact-out-dir --util-report-file --jobs --pre-synth-tcl ..." +} + +proc _require_file {path label} { + if {![file exists $path]} { + error "Missing ${label}: $path" + } +} + +proc _require_dir {path label} { + if {![file isdirectory $path]} { + error "Missing ${label}: $path" + } +} + +array set opts { + --project-name "" + --ip-repo "" + --static-shell-dcp "" + --base-bd "" + --linker-results-dir "" + --rm-work-dir "" + --artifact-out-dir "" + --util-report-file "" + --jobs 8 +} + +set pre_synth_tcls [list] + +set idx 0 +while {$idx < [llength $argv]} { + set key [lindex $argv $idx] + if {$key eq "--pre-synth-tcl"} { + incr idx + if {$idx >= [llength $argv]} { + error "Missing value for '$key'. [_slash_usage]" + } + set pre_synth_tcl [lindex $argv $idx] + if {$pre_synth_tcl eq ""} { + error "Empty value for '$key'. [_slash_usage]" + } + lappend pre_synth_tcls [file normalize $pre_synth_tcl] + incr idx + continue + } + if {![info exists opts($key)]} { + error "Unknown argument '$key'. [_slash_usage]" + } + incr idx + if {$idx >= [llength $argv]} { + error "Missing value for '$key'. [_slash_usage]" + } + set opts($key) [lindex $argv $idx] + incr idx +} + +foreach req {--project-name --ip-repo --static-shell-dcp --base-bd --linker-results-dir --rm-work-dir --artifact-out-dir --util-report-file} { + if {$opts($req) eq ""} { + error "Missing required argument '$req'. [_slash_usage]" + } +} + +set proj_name $opts(--project-name) +set ip_repo [file normalize $opts(--ip-repo)] +set static_shell_dcp [file normalize $opts(--static-shell-dcp)] +set base_bd [file normalize $opts(--base-bd)] +set linker_results_dir [file normalize $opts(--linker-results-dir)] +set rm_work_dir $opts(--rm-work-dir) +set artifact_out_dir $opts(--artifact-out-dir) +set util_report_file $opts(--util-report-file) +set jobs $opts(--jobs) + +file mkdir $rm_work_dir +file mkdir $artifact_out_dir +file mkdir [file dirname $util_report_file] +set rm_work_dir [file normalize $rm_work_dir] +set artifact_out_dir [file normalize $artifact_out_dir] +set util_report_file [file normalize $util_report_file] +set timing_report_file [file join $rm_work_dir "report_timing_${proj_name}.txt"] +set ltx_file [file join $artifact_out_dir "top_i_slash_slash_${proj_name}_inst_0_hw_probes.ltx"] + +set generated_bd_tcl [file join $linker_results_dir "slash.tcl"] + +_require_file $ip_repo "IP repository directory" +_require_file $static_shell_dcp "static shell DCP" +_require_file $base_bd "installed slash_base BD" +_require_file $generated_bd_tcl "generated slash BD Tcl" +foreach pre_synth_tcl $pre_synth_tcls { + _require_file $pre_synth_tcl "pre-synth Tcl" +} + +puts "PROJECT NAME: $proj_name" +puts "IP REPO: $ip_repo" +puts "LINKER RESULTS: $linker_results_dir" +puts "RM WORK DIR: $rm_work_dir" +puts "ARTIFACT OUT DIR: $artifact_out_dir" +puts "UTIL REPORT FILE: $util_report_file" +puts "TIMING REPORT: $timing_report_file" +puts "HW PROBES LTX: $ltx_file" +puts "JOBS: $jobs" +puts "PRE-SYNTH TCLS: $pre_synth_tcls" + +set slash_proj_name "slash_${proj_name}" +set slash_rm_name "${slash_proj_name}_rm" + +create_project $slash_proj_name $rm_work_dir -part xcv80-lsva4737-2MHP-e-S -force + +set_property ip_repo_paths [list $ip_repo] [current_project] +update_ip_catalog +add_files $static_shell_dcp +import_files $base_bd +set_property PR_FLOW 1 [current_project] +set_property DESIGN_MODE GateLvl [current_fileset] +set_property top top_wrapper [current_fileset] + +create_partition_def -name $slash_proj_name -module slash_base +create_reconfig_module -name $slash_rm_name -partition_def [get_partition_defs $slash_proj_name] -define_from slash_base + +create_pr_configuration -name config_1 -partitions [list top_i/slash:$slash_rm_name] +set_property USE_BLACKBOX 0 [get_pr_configuration config_1] +set_property PR_CONFIGURATION config_1 [get_runs impl_1] + +set imported_bd [file join $rm_work_dir "${slash_proj_name}.srcs" "sources_1" "bd" "slash_base" "slash_base.bd"] +open_bd_design $imported_bd +foreach p [get_bd_intf_ports] { + set_property HDL_ATTRIBUTE.LOCKED {TRUE} $p +} +source $generated_bd_tcl +foreach pre_synth_tcl $pre_synth_tcls { + puts "Sourcing pre-synth Tcl: $pre_synth_tcl" + source $pre_synth_tcl +} + +launch_runs "${slash_rm_name}_synth_1" -jobs $jobs +wait_on_run "${slash_rm_name}_synth_1" + +set rm_synth_dcp [file join $rm_work_dir "${slash_proj_name}.runs" "${slash_rm_name}_synth_1" "slash_base.dcp"] +add_files $rm_synth_dcp +set_property SCOPED_TO_CELLS {top_i/slash} [get_files $rm_synth_dcp] +set_property strategy Congestion_SSI_SpreadLogic_high [get_runs impl_1] + +launch_runs impl_1 -jobs $jobs +wait_on_run impl_1 +open_run impl_1 + +report_timing_summary -delay_type min_max -check_timing_verbose -max_paths 1 -input_pins -routable_nets -file $timing_report_file + +set partial_pdi [file join $artifact_out_dir "top_i_slash_slash_${proj_name}_inst_0_partial.pdi"] +write_device_image -cell top_i/slash -force $partial_pdi +write_debug_probes -cell top_i/slash -force $ltx_file +report_utilization -hierarchical -hierarchical_percentages -file $util_report_file diff --git a/linker/slashkit/resources/base/scripts/top.tcl b/linker/slashkit/resources/base/scripts/top.tcl new file mode 100644 index 00000000..87efb9e9 --- /dev/null +++ b/linker/slashkit/resources/base/scripts/top.tcl @@ -0,0 +1,5475 @@ + +################################################################ +# This is a generated script based on design: top +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2025.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source top_script.tcl + + +# The design that will be created by this Tcl script contains the following +# block design container source references: +# slash_base, slash_vadd, service_layer, service_layer_vadd + +# Please add the sources before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcv80-lsva4737-2MHP-e-S +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name top + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:clk_wizard:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:axi_noc:1.1\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:dfx_decoupler:1.0\ +xilinx.com:ip:versal_cips:3.4\ +xilinx.com:ip:axis_noc:1.0\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:inline_hdl:ilreduced_logic:1.0\ +xilinx.com:ip:c_shift_ram:12.0\ +xilinx.com:ip:hw_discovery:1.0\ +xilinx.com:ip:shell_utils_uuid_rom:2.0\ +xilinx.com:ip:smbus:1.1\ +xilinx.com:ip:cmd_queue:2.0\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:util_reduced_logic:2.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Block Design Container Sources +################################################################## +set bCheckSources 1 +set list_bdc_active "slash_base, service_layer" + +array set map_bdc_missing {} +set map_bdc_missing(ACTIVE) "" +set map_bdc_missing(DFX) "" +set map_bdc_missing(BDC) "" + +if { $bCheckSources == 1 } { + set list_check_srcs "\ +slash_base \ +service_layer \ +" + + common::send_gid_msg -ssname BD::TCL -id 2056 -severity "INFO" "Checking if the following sources for block design container exist in the project: $list_check_srcs .\n\n" + + foreach src $list_check_srcs { + if { [can_resolve_reference $src] == 0 } { + if { [lsearch $list_bdc_active $src] != -1 } { + set map_bdc_missing(ACTIVE) "$map_bdc_missing(ACTIVE) $src" + } else { + set map_bdc_missing(BDC) "$map_bdc_missing(BDC) $src" + } + } + } + + if { [llength $map_bdc_missing(ACTIVE)] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2057 -severity "ERROR" "The following source(s) of Active variants are not found in the project: $map_bdc_missing(ACTIVE)" } + common::send_gid_msg -ssname BD::TCL -id 2060 -severity "INFO" "Please add source files for the missing source(s) above." + set bCheckIPsPassed 0 + } + if { [llength $map_bdc_missing(DFX)] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2058 -severity "ERROR" "The following source(s) of DFX variants are not found in the project: $map_bdc_missing(DFX)" } + common::send_gid_msg -ssname BD::TCL -id 2060 -severity "INFO" "Please add source files for the missing source(s) above." + set bCheckIPsPassed 0 + } + if { [llength $map_bdc_missing(BDC)] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2059 -severity "WARNING" "The following source(s) of variants are not found in the project: $map_bdc_missing(BDC)" } + common::send_gid_msg -ssname BD::TCL -id 2060 -severity "INFO" "Please add source files for the missing source(s) above." + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: pcie_mgmt_pdi_reset +proc create_hier_cell_pcie_mgmt_pdi_reset { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_pcie_mgmt_pdi_reset() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir I -type rst resetn_in + + # Create instance: pcie_mgmt_pdi_reset_gpio, and set properties + set pcie_mgmt_pdi_reset_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 pcie_mgmt_pdi_reset_gpio ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $pcie_mgmt_pdi_reset_gpio + + + # Create instance: inv, and set properties + set inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 inv ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $inv + + + # Create instance: ccat, and set properties + set ccat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 ccat ] + + # Create instance: and_0, and set properties + set and_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 and_0 ] + set_property CONFIG.C_SIZE {2} $and_0 + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins pcie_mgmt_pdi_reset_gpio/S_AXI] + + # Create port connections + connect_bd_net -net and_0_Res [get_bd_pins and_0/Res] \ + [get_bd_pins pcie_mgmt_pdi_reset_gpio/gpio2_io_i] + connect_bd_net -net ccat_dout [get_bd_pins ccat/dout] \ + [get_bd_pins and_0/Op1] + connect_bd_net -net clk_1 [get_bd_pins clk] \ + [get_bd_pins pcie_mgmt_pdi_reset_gpio/s_axi_aclk] + connect_bd_net -net inv_Res [get_bd_pins inv/Res] \ + [get_bd_pins ccat/In1] + connect_bd_net -net pcie_mgmt_pdi_reset_gpio_gpio_io_o [get_bd_pins pcie_mgmt_pdi_reset_gpio/gpio_io_o] \ + [get_bd_pins ccat/In0] + connect_bd_net -net resetn_1 [get_bd_pins resetn] \ + [get_bd_pins pcie_mgmt_pdi_reset_gpio/s_axi_aresetn] + connect_bd_net -net resetn_in_1 [get_bd_pins resetn_in] \ + [get_bd_pins inv/Op1] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: base_logic +proc create_hier_cell_base_logic { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_base_logic() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_pcie_mgmt_slr0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rpu + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:pcie3_cfg_ext_rtl:1.0 pcie_cfg_ext + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_rpu + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pcie_mgmt_pdi_reset + + + # Create pins + create_bd_pin -dir I -type clk clk_pcie + create_bd_pin -dir I -type clk clk_pl + create_bd_pin -dir I -type rst resetn_pcie_periph + create_bd_pin -dir I -type rst resetn_pl_periph + create_bd_pin -dir I -type rst resetn_pl_ic + create_bd_pin -dir O -type intr irq_gcq_m2r + create_bd_pin -dir O -type intr irq_axi_smbus_rpu + + # Create instance: pcie_slr0_mgmt_sc, and set properties + set pcie_slr0_mgmt_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 pcie_slr0_mgmt_sc ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {4} \ + CONFIG.NUM_SI {1} \ + ] $pcie_slr0_mgmt_sc + + + # Create instance: rpu_sc, and set properties + set rpu_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 rpu_sc ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $rpu_sc + + + # Create instance: hw_discovery, and set properties + set hw_discovery [ create_bd_cell -type ip -vlnv xilinx.com:ip:hw_discovery:1.0 hw_discovery ] + set_property -dict [list \ + CONFIG.C_CAP_BASE_ADDR {0x600} \ + CONFIG.C_INJECT_ENDPOINTS {0} \ + CONFIG.C_MANUAL {1} \ + CONFIG.C_NEXT_CAP_ADDR {0x000} \ + CONFIG.C_NUM_PFS {1} \ + CONFIG.C_PF0_BAR_INDEX {0} \ + CONFIG.C_PF0_ENDPOINT_NAMES {0} \ + CONFIG.C_PF0_ENTRY_ADDR_0 {0x000001001000} \ + CONFIG.C_PF0_ENTRY_ADDR_1 {0x000001010000} \ + CONFIG.C_PF0_ENTRY_ADDR_2 {0x000008000000} \ + CONFIG.C_PF0_ENTRY_BAR_0 {0} \ + CONFIG.C_PF0_ENTRY_BAR_1 {0} \ + CONFIG.C_PF0_ENTRY_BAR_2 {0} \ + CONFIG.C_PF0_ENTRY_MAJOR_VERSION_0 {1} \ + CONFIG.C_PF0_ENTRY_MAJOR_VERSION_1 {1} \ + CONFIG.C_PF0_ENTRY_MAJOR_VERSION_2 {1} \ + CONFIG.C_PF0_ENTRY_MINOR_VERSION_0 {0} \ + CONFIG.C_PF0_ENTRY_MINOR_VERSION_1 {2} \ + CONFIG.C_PF0_ENTRY_MINOR_VERSION_2 {0} \ + CONFIG.C_PF0_ENTRY_RSVD0_0 {0x0} \ + CONFIG.C_PF0_ENTRY_RSVD0_1 {0x0} \ + CONFIG.C_PF0_ENTRY_RSVD0_2 {0x0} \ + CONFIG.C_PF0_ENTRY_TYPE_0 {0x50} \ + CONFIG.C_PF0_ENTRY_TYPE_1 {0x54} \ + CONFIG.C_PF0_ENTRY_TYPE_2 {0x55} \ + CONFIG.C_PF0_ENTRY_VERSION_TYPE_0 {0x01} \ + CONFIG.C_PF0_ENTRY_VERSION_TYPE_1 {0x01} \ + CONFIG.C_PF0_ENTRY_VERSION_TYPE_2 {0x01} \ + CONFIG.C_PF0_HIGH_OFFSET {0x00000000} \ + CONFIG.C_PF0_LOW_OFFSET {0x0100000} \ + CONFIG.C_PF0_NUM_SLOTS_BAR_LAYOUT_TABLE {3} \ + CONFIG.C_PF0_S_AXI_ADDR_WIDTH {32} \ + ] $hw_discovery + + + # Create instance: uuid_rom, and set properties + set uuid_rom [ create_bd_cell -type ip -vlnv xilinx.com:ip:shell_utils_uuid_rom:2.0 uuid_rom ] + set_property CONFIG.C_INITIAL_UUID {00000000000000000000000000000000} $uuid_rom + + + # Create instance: axi_smbus_rpu, and set properties + set axi_smbus_rpu [ create_bd_cell -type ip -vlnv xilinx.com:ip:smbus:1.1 axi_smbus_rpu ] + set_property -dict [list \ + CONFIG.NUM_TARGET_DEVICES {8} \ + CONFIG.SMBUS_DEV_CLASS {0} \ + ] $axi_smbus_rpu + + + # Create instance: gcq_m2r, and set properties + set gcq_m2r [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmd_queue:2.0 gcq_m2r ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smbus_rpu_SMBUS [get_bd_intf_pins axi_smbus_rpu/SMBUS] [get_bd_intf_pins smbus_rpu] + connect_bd_intf_net -intf_net pcie_cfg_ext_1 [get_bd_intf_pins pcie_cfg_ext] [get_bd_intf_pins hw_discovery/s_pcie4_cfg_ext] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M00_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M00_AXI] [get_bd_intf_pins hw_discovery/s_axi_ctrl_pf0] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M01_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M01_AXI] [get_bd_intf_pins uuid_rom/S_AXI] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M02_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M02_AXI] [get_bd_intf_pins gcq_m2r/S00_AXI] + connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M03_AXI [get_bd_intf_pins pcie_slr0_mgmt_sc/M03_AXI] [get_bd_intf_pins m_axi_pcie_mgmt_pdi_reset] + connect_bd_intf_net -intf_net rpu_sc_M00_AXI [get_bd_intf_pins rpu_sc/M00_AXI] [get_bd_intf_pins gcq_m2r/S01_AXI] + connect_bd_intf_net -intf_net rpu_sc_M01_AXI [get_bd_intf_pins axi_smbus_rpu/S_AXI] [get_bd_intf_pins rpu_sc/M01_AXI] + connect_bd_intf_net -intf_net s_axi_pcie_mgmt_slr0_1 [get_bd_intf_pins s_axi_pcie_mgmt_slr0] [get_bd_intf_pins pcie_slr0_mgmt_sc/S00_AXI] + connect_bd_intf_net -intf_net s_axi_rpu_1 [get_bd_intf_pins s_axi_rpu] [get_bd_intf_pins rpu_sc/S00_AXI] + + # Create port connections + connect_bd_net -net axi_smbus_rpu_ip2intc_irpt [get_bd_pins axi_smbus_rpu/ip2intc_irpt] \ + [get_bd_pins irq_axi_smbus_rpu] + connect_bd_net -net clk_pcie_1 [get_bd_pins clk_pcie] \ + [get_bd_pins hw_discovery/aclk_pcie] + connect_bd_net -net clk_pl_1 [get_bd_pins clk_pl] \ + [get_bd_pins pcie_slr0_mgmt_sc/aclk] \ + [get_bd_pins rpu_sc/aclk] \ + [get_bd_pins hw_discovery/aclk_ctrl] \ + [get_bd_pins uuid_rom/S_AXI_ACLK] \ + [get_bd_pins gcq_m2r/aclk] \ + [get_bd_pins axi_smbus_rpu/s_axi_aclk] + connect_bd_net -net gcq_m2r_irq_sq [get_bd_pins gcq_m2r/irq_sq] \ + [get_bd_pins irq_gcq_m2r] + connect_bd_net -net resetn_pcie_periph_1 [get_bd_pins resetn_pcie_periph] \ + [get_bd_pins hw_discovery/aresetn_pcie] + connect_bd_net -net resetn_pl_ic_1 [get_bd_pins resetn_pl_ic] \ + [get_bd_pins pcie_slr0_mgmt_sc/aresetn] \ + [get_bd_pins rpu_sc/aresetn] + connect_bd_net -net resetn_pl_periph_1 [get_bd_pins resetn_pl_periph] \ + [get_bd_pins hw_discovery/aresetn_ctrl] \ + [get_bd_pins uuid_rom/S_AXI_ARESETN] \ + [get_bd_pins gcq_m2r/aresetn] \ + [get_bd_pins axi_smbus_rpu/s_axi_aresetn] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: clock_reset +proc create_hier_cell_clock_reset { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_clock_reset() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_pcie_mgmt_pdi_reset + + + # Create pins + create_bd_pin -dir I -type clk clk_pl + create_bd_pin -dir I -type clk clk_freerun + create_bd_pin -dir I -type clk clk_pcie + create_bd_pin -dir I -type rst dma_axi_aresetn + create_bd_pin -dir I -type rst resetn_pl_axi + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pcie_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pcie_periph + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_periph + create_bd_pin -dir O -type clk clk_usr_0 + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_0_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_0_periph + create_bd_pin -dir O -type clk clk_usr_1 + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_1_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_usr_1_periph + + # Create instance: pcie_psr, and set properties + set pcie_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 pcie_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $pcie_psr + + + # Create instance: pl_psr, and set properties + set pl_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 pl_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $pl_psr + + + # Create instance: usr_clk_wiz, and set properties + set usr_clk_wiz [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 usr_clk_wiz ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {No_buffer,No_buffer} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {300,500} \ + CONFIG.CLKOUT_USED {true,true} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.USE_DYN_RECONFIG {false} \ + CONFIG.USE_LOCKED {true} \ + CONFIG.USE_POWER_DOWN {false} \ + CONFIG.USE_RESET {false} \ + ] $usr_clk_wiz + + + # Create instance: usr_0_psr, and set properties + set usr_0_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 usr_0_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $usr_0_psr + + + # Create instance: usr_1_psr, and set properties + set usr_1_psr [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 usr_1_psr ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $usr_1_psr + + + # Create instance: pcie_mgmt_pdi_reset + create_hier_cell_pcie_mgmt_pdi_reset $hier_obj pcie_mgmt_pdi_reset + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_pcie_mgmt_pdi_reset_1 [get_bd_intf_pins s_axi_pcie_mgmt_pdi_reset] [get_bd_intf_pins pcie_mgmt_pdi_reset/s_axi] + + # Create port connections + connect_bd_net -net clk_freerun_1 [get_bd_pins clk_freerun] \ + [get_bd_pins usr_clk_wiz/clk_in1] + connect_bd_net -net clk_pcie_1 [get_bd_pins clk_pcie] \ + [get_bd_pins pcie_psr/slowest_sync_clk] + connect_bd_net -net clk_pl_1 [get_bd_pins clk_pl] \ + [get_bd_pins pl_psr/slowest_sync_clk] \ + [get_bd_pins pcie_mgmt_pdi_reset/clk] + connect_bd_net -net dma_axi_aresetn_1 [get_bd_pins dma_axi_aresetn] \ + [get_bd_pins pcie_mgmt_pdi_reset/resetn_in] + connect_bd_net -net pcie_psr_interconnect_aresetn [get_bd_pins pcie_psr/interconnect_aresetn] \ + [get_bd_pins resetn_pcie_ic] + connect_bd_net -net pcie_psr_peripheral_aresetn [get_bd_pins pcie_psr/peripheral_aresetn] \ + [get_bd_pins resetn_pcie_periph] + connect_bd_net -net pl_psr_interconnect_aresetn [get_bd_pins pl_psr/interconnect_aresetn] \ + [get_bd_pins resetn_pl_ic] \ + [get_bd_pins pcie_psr/ext_reset_in] \ + [get_bd_pins usr_0_psr/ext_reset_in] \ + [get_bd_pins usr_1_psr/ext_reset_in] + connect_bd_net -net pl_psr_peripheral_aresetn [get_bd_pins pl_psr/peripheral_aresetn] \ + [get_bd_pins resetn_pl_periph] \ + [get_bd_pins pcie_mgmt_pdi_reset/resetn] + connect_bd_net -net resetn_pl_axi_1 [get_bd_pins resetn_pl_axi] \ + [get_bd_pins pl_psr/ext_reset_in] + connect_bd_net -net usr_0_psr_interconnect_aresetn [get_bd_pins usr_0_psr/interconnect_aresetn] \ + [get_bd_pins resetn_usr_0_ic] + connect_bd_net -net usr_0_psr_peripheral_aresetn [get_bd_pins usr_0_psr/peripheral_aresetn] \ + [get_bd_pins resetn_usr_0_periph] + connect_bd_net -net usr_1_psr_interconnect_aresetn [get_bd_pins usr_1_psr/interconnect_aresetn] \ + [get_bd_pins resetn_usr_1_ic] + connect_bd_net -net usr_1_psr_peripheral_aresetn [get_bd_pins usr_1_psr/peripheral_aresetn] \ + [get_bd_pins resetn_usr_1_periph] + connect_bd_net -net usr_clk_wiz_clk_out1 [get_bd_pins usr_clk_wiz/clk_out1] \ + [get_bd_pins clk_usr_0] \ + [get_bd_pins usr_0_psr/slowest_sync_clk] + connect_bd_net -net usr_clk_wiz_clk_out2 [get_bd_pins usr_clk_wiz/clk_out2] \ + [get_bd_pins clk_usr_1] \ + [get_bd_pins usr_1_psr/slowest_sync_clk] + connect_bd_net -net usr_clk_wiz_locked [get_bd_pins usr_clk_wiz/locked] \ + [get_bd_pins usr_0_psr/dcm_locked] \ + [get_bd_pins usr_1_psr/dcm_locked] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: clk_rst_shell +proc create_hier_cell_clk_rst_shell { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_clk_rst_shell() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI + + + # Create pins + create_bd_pin -dir I -type clk pl0_ref_clk + create_bd_pin -dir I -type rst aresetn + create_bd_pin -dir I -type clk refclk + create_bd_pin -dir O -type clk service_clk + create_bd_pin -dir O -from 0 -to 0 -type rst service_arstn + create_bd_pin -dir O -type clk slash_clk + create_bd_pin -dir O -from 0 -to 0 -type rst slash_arstn + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.APERTURES {{0x204_0000_0000 512K}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/clk_rst_shell/axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/clk_rst_shell/axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /static_region/clk_rst_shell/axi_noc_0/aclk0] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + + # Create instance: clk_wizard_slash, and set properties + set clk_wizard_slash [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_slash ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {200.000,100.000,100.000,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \ + CONFIG.USE_DYN_RECONFIG {true} \ + ] $clk_wizard_slash + + + # Create instance: clk_wizard_service, and set properties + set clk_wizard_service [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_service ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {300.000,100.000,100.000,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \ + CONFIG.USE_DYN_RECONFIG {true} \ + ] $clk_wizard_service + + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: slash_rst_conv_in, and set properties + set slash_rst_conv_in [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic:1.0 slash_rst_conv_in ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $slash_rst_conv_in + + + # Create instance: service_rst_conv_in, and set properties + set service_rst_conv_in [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic:1.0 service_rst_conv_in ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $service_rst_conv_in + + + # Create instance: slash_rst_pipe_slr0, and set properties + set slash_rst_pipe_slr0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 slash_rst_pipe_slr0 ] + set_property -dict [list \ + CONFIG.Depth {1} \ + CONFIG.Width {1} \ + ] $slash_rst_pipe_slr0 + + + # Create instance: service_rst_pipe_slr0, and set properties + set service_rst_pipe_slr0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 service_rst_pipe_slr0 ] + set_property -dict [list \ + CONFIG.Depth {1} \ + CONFIG.Width {1} \ + ] $service_rst_pipe_slr0 + + + # Create interface connections + connect_bd_intf_net -intf_net S00_INI_1 [get_bd_intf_pins S00_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net axi_noc_0_M00_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins axi_noc_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins clk_wizard_slash/s_axi_lite] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins clk_wizard_service/s_axi_lite] [get_bd_intf_pins smartconnect_0/M01_AXI] + + # Create port connections + connect_bd_net -net aresetn_1 [get_bd_pins aresetn] \ + [get_bd_pins smartconnect_0/aresetn] \ + [get_bd_pins clk_wizard_slash/s_axi_aresetn] \ + [get_bd_pins clk_wizard_service/s_axi_aresetn] \ + [get_bd_pins proc_sys_reset_0/ext_reset_in] \ + [get_bd_pins proc_sys_reset_1/ext_reset_in] + connect_bd_net -net clk_wizard_service_clk_out1 [get_bd_pins clk_wizard_service/clk_out1] \ + [get_bd_pins proc_sys_reset_1/slowest_sync_clk] \ + [get_bd_pins service_clk] \ + [get_bd_pins service_rst_pipe_slr0/CLK] + connect_bd_net -net clk_wizard_service_locked [get_bd_pins clk_wizard_service/locked] \ + [get_bd_pins proc_sys_reset_1/dcm_locked] + connect_bd_net -net clk_wizard_slash_clk_out1 [get_bd_pins clk_wizard_slash/clk_out1] \ + [get_bd_pins proc_sys_reset_0/slowest_sync_clk] \ + [get_bd_pins slash_clk] \ + [get_bd_pins slash_rst_pipe_slr0/CLK] + connect_bd_net -net clk_wizard_slash_locked [get_bd_pins clk_wizard_slash/locked] \ + [get_bd_pins proc_sys_reset_0/dcm_locked] + connect_bd_net -net pl0_ref_clk_1 [get_bd_pins pl0_ref_clk] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins smartconnect_0/aclk] \ + [get_bd_pins clk_wizard_slash/s_axi_aclk] \ + [get_bd_pins clk_wizard_service/s_axi_aclk] + connect_bd_net -net pl3_ref_clk_1 [get_bd_pins refclk] \ + [get_bd_pins clk_wizard_slash/clk_in1] \ + [get_bd_pins clk_wizard_service/clk_in1] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] \ + [get_bd_pins slash_rst_conv_in/Op1] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] \ + [get_bd_pins service_rst_conv_in/Op1] + connect_bd_net -net service_rst_conv_in_Res [get_bd_pins service_rst_conv_in/Res] \ + [get_bd_pins service_rst_pipe_slr0/D] + connect_bd_net -net service_rst_pipe_slr0_Q [get_bd_pins service_rst_pipe_slr0/Q] \ + [get_bd_pins service_arstn] + connect_bd_net -net slash_rst_conv_in_Res [get_bd_pins slash_rst_conv_in/Res] \ + [get_bd_pins slash_rst_pipe_slr0/D] + connect_bd_net -net slash_rst_pipe_slr0_Q [get_bd_pins slash_rst_pipe_slr0/Q] \ + [get_bd_pins slash_arstn] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: virt_noc +proc create_hier_cell_virt_noc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_virt_noc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI4 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI4 + + + # Create pins + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_0/S00_INI] + + # Create instance: axi_noc_1, and set properties + set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_1/S00_INI] + + # Create instance: axi_noc_2, and set properties + set axi_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_2/S00_INI] + + # Create instance: axi_noc_3, and set properties + set axi_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_3/S00_INI] + + # Create instance: axi_noc_4, and set properties + set axi_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_4/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + ] [get_bd_intf_pins /static_region/virt_noc/axi_noc_4/S00_INI] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_noc_0/M00_INI] [get_bd_intf_pins M00_INI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_noc_0/S00_INI] [get_bd_intf_pins S00_INI] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_noc_1/S00_INI] [get_bd_intf_pins S00_INI1] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_noc_2/S00_INI] [get_bd_intf_pins S00_INI2] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_noc_3/S00_INI] [get_bd_intf_pins S00_INI3] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins axi_noc_4/S00_INI] [get_bd_intf_pins S00_INI4] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins axi_noc_1/M00_INI] [get_bd_intf_pins M00_INI1] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins axi_noc_2/M00_INI] [get_bd_intf_pins M00_INI2] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins axi_noc_3/M00_INI] [get_bd_intf_pins M00_INI3] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins axi_noc_4/M00_INI] [get_bd_intf_pins M00_INI4] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: dcmac_noc +proc create_hier_cell_dcmac_noc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dcmac_noc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS4 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS5 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS6 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS6 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS7 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS7 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS8 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS8 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS9 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS9 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS10 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS10 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS11 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS11 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS12 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS12 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS13 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS13 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS14 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS14 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS15 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS15 + + + # Create pins + + # Create instance: dcmac_service2slash_0, and set properties + set dcmac_service2slash_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_0/S00_INIS] + + # Create instance: dcmac_service2slash_1, and set properties + set dcmac_service2slash_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_1/S00_INIS] + + # Create instance: dcmac_service2slash_2, and set properties + set dcmac_service2slash_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_2/S00_INIS] + + # Create instance: dcmac_service2slash_3, and set properties + set dcmac_service2slash_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_3/S00_INIS] + + # Create instance: dcmac_service2slash_4, and set properties + set dcmac_service2slash_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_4/S00_INIS] + + # Create instance: dcmac_service2slash_5, and set properties + set dcmac_service2slash_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_5/S00_INIS] + + # Create instance: dcmac_service2slash_6, and set properties + set dcmac_service2slash_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_6/S00_INIS] + + # Create instance: dcmac_service2slash_7, and set properties + set dcmac_service2slash_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_service2slash_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_service2slash_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_service2slash_7/S00_INIS] + + # Create instance: dcmac_slash2service_0, and set properties + set dcmac_slash2service_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_0/S00_INIS] + + # Create instance: dcmac_slash2service_1, and set properties + set dcmac_slash2service_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_1/S00_INIS] + + # Create instance: dcmac_slash2service_2, and set properties + set dcmac_slash2service_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_2/S00_INIS] + + # Create instance: dcmac_slash2service_3, and set properties + set dcmac_slash2service_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_3/S00_INIS] + + # Create instance: dcmac_slash2service_4, and set properties + set dcmac_slash2service_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_4/S00_INIS] + + # Create instance: dcmac_slash2service_5, and set properties + set dcmac_slash2service_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_5/S00_INIS] + + # Create instance: dcmac_slash2service_6, and set properties + set dcmac_slash2service_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_6/S00_INIS] + + # Create instance: dcmac_slash2service_7, and set properties + set dcmac_slash2service_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_slash2service_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_slash2service_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {100}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /static_region/dcmac_noc/dcmac_slash2service_7/S00_INIS] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins dcmac_slash2service_0/S00_INIS] [get_bd_intf_pins S00_INIS] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dcmac_slash2service_0/M00_INIS] [get_bd_intf_pins M00_INIS] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dcmac_slash2service_1/S00_INIS] [get_bd_intf_pins S00_INIS1] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dcmac_slash2service_1/M00_INIS] [get_bd_intf_pins M00_INIS1] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dcmac_slash2service_2/S00_INIS] [get_bd_intf_pins S00_INIS2] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dcmac_slash2service_2/M00_INIS] [get_bd_intf_pins M00_INIS2] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dcmac_slash2service_3/S00_INIS] [get_bd_intf_pins S00_INIS3] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dcmac_slash2service_3/M00_INIS] [get_bd_intf_pins M00_INIS3] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins dcmac_slash2service_4/S00_INIS] [get_bd_intf_pins S00_INIS4] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dcmac_slash2service_4/M00_INIS] [get_bd_intf_pins M00_INIS4] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dcmac_slash2service_5/S00_INIS] [get_bd_intf_pins S00_INIS5] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dcmac_slash2service_5/M00_INIS] [get_bd_intf_pins M00_INIS5] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dcmac_slash2service_6/S00_INIS] [get_bd_intf_pins S00_INIS6] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dcmac_slash2service_6/M00_INIS] [get_bd_intf_pins M00_INIS6] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dcmac_slash2service_7/S00_INIS] [get_bd_intf_pins S00_INIS7] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dcmac_slash2service_7/M00_INIS] [get_bd_intf_pins M00_INIS7] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins dcmac_service2slash_0/S00_INIS] [get_bd_intf_pins S00_INIS8] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins dcmac_service2slash_0/M00_INIS] [get_bd_intf_pins M00_INIS8] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins dcmac_service2slash_1/S00_INIS] [get_bd_intf_pins S00_INIS9] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins dcmac_service2slash_1/M00_INIS] [get_bd_intf_pins M00_INIS9] + connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins dcmac_service2slash_2/S00_INIS] [get_bd_intf_pins S00_INIS10] + connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins dcmac_service2slash_2/M00_INIS] [get_bd_intf_pins M00_INIS10] + connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins dcmac_service2slash_3/S00_INIS] [get_bd_intf_pins S00_INIS11] + connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins dcmac_service2slash_3/M00_INIS] [get_bd_intf_pins M00_INIS11] + connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins dcmac_service2slash_4/S00_INIS] [get_bd_intf_pins S00_INIS12] + connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins dcmac_service2slash_4/M00_INIS] [get_bd_intf_pins M00_INIS12] + connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins dcmac_service2slash_5/S00_INIS] [get_bd_intf_pins S00_INIS13] + connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins dcmac_service2slash_5/M00_INIS] [get_bd_intf_pins M00_INIS13] + connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins dcmac_service2slash_6/S00_INIS] [get_bd_intf_pins S00_INIS14] + connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins dcmac_service2slash_6/M00_INIS] [get_bd_intf_pins M00_INIS14] + connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins dcmac_service2slash_7/S00_INIS] [get_bd_intf_pins S00_INIS15] + connect_bd_intf_net -intf_net Conn32 [get_bd_intf_pins dcmac_service2slash_7/M00_INIS] [get_bd_intf_pins M00_INIS15] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: aved +proc create_hier_cell_aved { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_aved() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_pcie_refclk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_pciea1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 CPM_PCIE_NOC_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 CPM_PCIE_NOC_1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 PMC_NOC_AXI_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 LPD_AXI_NOC_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_pcie_mgmt_slr0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 NOC_PMC_AXI_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 NOC_CPM_PCIE_0 + + + # Create pins + create_bd_pin -dir O -type clk pl0_ref_clk + create_bd_pin -dir O -type clk lpd_axi_noc_clk + create_bd_pin -dir O -type clk pmc_axi_noc_axi0_clk + create_bd_pin -dir O -type clk cpm_pcie_noc_axi1_clk + create_bd_pin -dir O -type clk cpm_pcie_noc_axi0_clk + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_periph + create_bd_pin -dir O -type clk noc_pmc_axi_axi0_clk + create_bd_pin -dir O -type clk pl3_ref_clk + create_bd_pin -dir O -type rst pl3_resetn + create_bd_pin -dir O -type clk noc_cpm_pcie_axi0_clk + create_bd_pin -dir O eos + create_bd_pin -dir O -type rst pl0_resetn + + # Create instance: clock_reset + create_hier_cell_clock_reset $hier_obj clock_reset + + # Create instance: base_logic + create_hier_cell_base_logic $hier_obj base_logic + + # Create instance: cips, and set properties + set cips [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips:3.4 cips ] + set_property -dict [list \ + CONFIG.CPM_CONFIG { \ + CPM_PCIE0_MODES {None} \ + CPM_PCIE0_TANDEM {None} \ + CPM_PCIE1_ACS_CAP_ON {0} \ + CPM_PCIE1_ARI_CAP_ENABLED {1} \ + CPM_PCIE1_BRIDGE_AXI_SLAVE_IF {1} \ + CPM_PCIE1_CFG_EXT_IF {1} \ + CPM_PCIE1_CFG_VEND_ID {10ee} \ + CPM_PCIE1_COPY_PF0_QDMA_ENABLED {0} \ + CPM_PCIE1_EXT_PCIE_CFG_SPACE_ENABLED {Extended_Large} \ + CPM_PCIE1_FUNCTIONAL_MODE {QDMA} \ + CPM_PCIE1_MAX_LINK_SPEED {32.0_GT/s} \ + CPM_PCIE1_MODES {DMA} \ + CPM_PCIE1_MODE_SELECTION {Advanced} \ + CPM_PCIE1_MSI_X_OPTIONS {MSI-X_Internal} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_0 {0x0000008000000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_1 {0x0000008040000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_2 {0x0000008080000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_3 {0x00000080C0000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_4 {0x0000008100000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_5 {0x0000008140000000} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_0 {0x000000803FFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_1 {0x000000807FFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_2 {0x00000080BFFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_3 {0x00000080FFFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_4 {0x000000813FFFFFFFF} \ + CPM_PCIE1_PF0_AXIBAR2PCIE_HIGHADDR_5 {0x000000817FFFFFFFF} \ + CPM_PCIE1_PF0_BAR0_QDMA_64BIT {1} \ + CPM_PCIE1_PF0_BAR0_QDMA_ENABLED {1} \ + CPM_PCIE1_PF0_BAR0_QDMA_PREFETCHABLE {1} \ + CPM_PCIE1_PF0_BAR0_QDMA_SCALE {Megabytes} \ + CPM_PCIE1_PF0_BAR0_QDMA_SIZE {256} \ + CPM_PCIE1_PF0_BAR0_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF0_BAR2_QDMA_64BIT {0} \ + CPM_PCIE1_PF0_BAR2_QDMA_ENABLED {0} \ + CPM_PCIE1_PF0_BAR2_QDMA_PREFETCHABLE {0} \ + CPM_PCIE1_PF0_BAR2_QDMA_SCALE {Kilobytes} \ + CPM_PCIE1_PF0_BAR2_QDMA_SIZE {4} \ + CPM_PCIE1_PF0_BAR2_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF0_BASE_CLASS_VALUE {12} \ + CPM_PCIE1_PF0_CFG_DEV_ID {50b4} \ + CPM_PCIE1_PF0_CFG_SUBSYS_ID {000e} \ + CPM_PCIE1_PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE {0} \ + CPM_PCIE1_PF0_MSIX_CAP_TABLE_OFFSET {40} \ + CPM_PCIE1_PF0_MSIX_CAP_TABLE_SIZE {1} \ + CPM_PCIE1_PF0_MSIX_ENABLED {0} \ + CPM_PCIE1_PF0_PCIEBAR2AXIBAR_QDMA_0 {0x0000020100000000} \ + CPM_PCIE1_PF0_SUB_CLASS_VALUE {00} \ + CPM_PCIE1_PF1_BAR0_QDMA_64BIT {1} \ + CPM_PCIE1_PF1_BAR0_QDMA_ENABLED {1} \ + CPM_PCIE1_PF1_BAR0_QDMA_PREFETCHABLE {1} \ + CPM_PCIE1_PF1_BAR0_QDMA_SCALE {Kilobytes} \ + CPM_PCIE1_PF1_BAR0_QDMA_SIZE {512} \ + CPM_PCIE1_PF1_BAR0_QDMA_TYPE {DMA} \ + CPM_PCIE1_PF1_BAR2_QDMA_64BIT {0} \ + CPM_PCIE1_PF1_BAR2_QDMA_ENABLED {0} \ + CPM_PCIE1_PF1_BAR2_QDMA_PREFETCHABLE {0} \ + CPM_PCIE1_PF1_BAR2_QDMA_SCALE {Kilobytes} \ + CPM_PCIE1_PF1_BAR2_QDMA_SIZE {4} \ + CPM_PCIE1_PF1_BAR2_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF1_BASE_CLASS_VALUE {12} \ + CPM_PCIE1_PF1_CFG_DEV_ID {50b5} \ + CPM_PCIE1_PF1_CFG_SUBSYS_ID {000e} \ + CPM_PCIE1_PF1_CFG_SUBSYS_VEND_ID {10EE} \ + CPM_PCIE1_PF1_MSIX_CAP_TABLE_OFFSET {50000} \ + CPM_PCIE1_PF1_MSIX_CAP_TABLE_SIZE {8} \ + CPM_PCIE1_PF1_MSIX_ENABLED {1} \ + CPM_PCIE1_PF1_PCIEBAR2AXIBAR_QDMA_2 {0x0000020200000000} \ + CPM_PCIE1_PF1_SUB_CLASS_VALUE {00} \ + CPM_PCIE1_PF2_BAR0_QDMA_64BIT {1} \ + CPM_PCIE1_PF2_BAR0_QDMA_SCALE {Megabytes} \ + CPM_PCIE1_PF2_BAR0_QDMA_SIZE {128} \ + CPM_PCIE1_PF2_BAR0_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF2_BAR2_QDMA_64BIT {1} \ + CPM_PCIE1_PF2_BAR2_QDMA_ENABLED {1} \ + CPM_PCIE1_PF2_BAR2_QDMA_SCALE {Megabytes} \ + CPM_PCIE1_PF2_BAR2_QDMA_SIZE {128} \ + CPM_PCIE1_PF2_BAR2_QDMA_TYPE {AXI_Bridge_Master} \ + CPM_PCIE1_PF2_BAR3_QDMA_ENABLED {0} \ + CPM_PCIE1_PF2_BAR3_QDMA_SIZE {4} \ + CPM_PCIE1_PF2_BAR4_QDMA_64BIT {1} \ + CPM_PCIE1_PF2_BAR4_QDMA_ENABLED {1} \ + CPM_PCIE1_PF2_BAR4_QDMA_SIZE {512} \ + CPM_PCIE1_PF2_BASE_CLASS_VALUE {12} \ + CPM_PCIE1_PF2_CFG_DEV_ID {50b6} \ + CPM_PCIE1_PF2_CFG_SUBSYS_ID {000e} \ + CPM_PCIE1_PF2_CFG_SUBSYS_VEND_ID {10EE} \ + CPM_PCIE1_PF2_PCIEBAR2AXIBAR_QDMA_0 {0x0000020200000000} \ + CPM_PCIE1_PF2_PCIEBAR2AXIBAR_QDMA_2 {0x0000020300000000} \ + CPM_PCIE1_PF2_PCIEBAR2AXIBAR_QDMA_4 {0x0000020400000000} \ + CPM_PCIE1_PF2_USE_CLASS_CODE_LOOKUP_ASSISTANT {0} \ + CPM_PCIE1_PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CPM_PCIE1_TL_PF_ENABLE_REG {3} \ + } \ + CONFIG.PS_PMC_CONFIG { \ + BOOT_MODE {Custom} \ + CLOCK_MODE {Custom} \ + DDR_MEMORY_MODE {Custom} \ + DESIGN_MODE {1} \ + DEVICE_INTEGRITY_MODE {Custom} \ + IO_CONFIG_MODE {Custom} \ + PCIE_APERTURES_DUAL_ENABLE {0} \ + PCIE_APERTURES_SINGLE_ENABLE {1} \ + PMC_BANK_1_IO_STANDARD {LVCMOS3.3} \ + PMC_CRP_OSPI_REF_CTRL_FREQMHZ {200} \ + PMC_CRP_PL0_REF_CTRL_FREQMHZ {100} \ + PMC_CRP_PL1_REF_CTRL_FREQMHZ {33.3333333} \ + PMC_CRP_PL2_REF_CTRL_FREQMHZ {250} \ + PMC_CRP_PL3_REF_CTRL_FREQMHZ {100} \ + PMC_GLITCH_CONFIG {{DEPTH_SENSITIVITY 1} {MIN_PULSE_WIDTH 0.5} {TYPE CUSTOM} {VCC_PMC_VALUE 0.88}} \ + PMC_GLITCH_CONFIG_1 {{DEPTH_SENSITIVITY 1} {MIN_PULSE_WIDTH 0.5} {TYPE CUSTOM} {VCC_PMC_VALUE 0.88}} \ + PMC_GLITCH_CONFIG_2 {{DEPTH_SENSITIVITY 1} {MIN_PULSE_WIDTH 0.5} {TYPE CUSTOM} {VCC_PMC_VALUE 0.88}} \ + PMC_GPIO_EMIO_PERIPHERAL_ENABLE {0} \ + PMC_MIO11 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO12 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO13 {{AUX_IO 0} {DIRECTION inout} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ + PMC_MIO17 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO26 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO27 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO28 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO29 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO30 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO31 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO32 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO33 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO34 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO35 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO36 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO37 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO38 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO39 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO40 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO41 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO42 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO43 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO44 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO48 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO49 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO50 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO51 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PMC_MIO_EN_FOR_PL_PCIE {0} \ + PMC_OSPI_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 0 .. 11}} {MODE Single}} \ + PMC_REF_CLK_FREQMHZ {33.333333} \ + PMC_SD0_DATA_TRANSFER_MODE {8Bit} \ + PMC_SD0_PERIPHERAL {{CLK_100_SDR_OTAP_DLY 0x00} {CLK_200_SDR_OTAP_DLY 0x2} {CLK_50_DDR_ITAP_DLY 0x1E} {CLK_50_DDR_OTAP_DLY 0x5} {CLK_50_SDR_ITAP_DLY 0x2C} {CLK_50_SDR_OTAP_DLY 0x5} {ENABLE 1} {IO\ +{PMC_MIO 13 .. 25}}} \ + PMC_SD0_SLOT_TYPE {eMMC} \ + PMC_USE_NOC_PMC_AXI0 {1} \ + PMC_USE_PMC_NOC_AXI0 {1} \ + PS_BANK_2_IO_STANDARD {LVCMOS3.3} \ + PS_BOARD_INTERFACE {Custom} \ + PS_CRL_CPM_TOPSW_REF_CTRL_FREQMHZ {1000} \ + PS_GEN_IPI0_ENABLE {0} \ + PS_GEN_IPI1_ENABLE {0} \ + PS_GEN_IPI2_ENABLE {0} \ + PS_GEN_IPI3_ENABLE {1} \ + PS_GEN_IPI3_MASTER {R5_0} \ + PS_GEN_IPI4_ENABLE {1} \ + PS_GEN_IPI4_MASTER {R5_0} \ + PS_GEN_IPI5_ENABLE {1} \ + PS_GEN_IPI5_MASTER {R5_1} \ + PS_GEN_IPI6_ENABLE {1} \ + PS_GEN_IPI6_MASTER {R5_1} \ + PS_GPIO_EMIO_PERIPHERAL_ENABLE {0} \ + PS_I2C0_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 2 .. 3}}} \ + PS_I2C1_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 0 .. 1}}} \ + PS_IRQ_USAGE {{CH0 1} {CH1 1} {CH10 0} {CH11 0} {CH12 0} {CH13 0} {CH14 0} {CH15 0} {CH2 0} {CH3 0} {CH4 0} {CH5 0} {CH6 0} {CH7 0} {CH8 0} {CH9 0}} \ + PS_KAT_ENABLE {0} \ + PS_KAT_ENABLE_1 {0} \ + PS_KAT_ENABLE_2 {0} \ + PS_MIO10 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO11 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO12 {{AUX_IO 0} {DIRECTION inout} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ + PS_MIO13 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO14 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO18 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO19 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO22 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO23 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO24 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO25 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO4 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO5 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO6 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO7 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \ + PS_MIO8 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ + PS_MIO9 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 1} {SLEW slow} {USAGE Reserved}} \ + PS_M_AXI_LPD_DATA_WIDTH {32} \ + PS_NUM_FABRIC_RESETS {4} \ + PS_PCIE1_PERIPHERAL_ENABLE {0} \ + PS_PCIE2_PERIPHERAL_ENABLE {1} \ + PS_PCIE_EP_RESET1_IO {PMC_MIO 24} \ + PS_PCIE_EP_RESET2_IO {PMC_MIO 25} \ + PS_PCIE_RESET {ENABLE 1} \ + PS_PL_CONNECTIVITY_MODE {Custom} \ + PS_SPI0 {{GRP_SS0_ENABLE 1} {GRP_SS0_IO {PS_MIO 15}} {GRP_SS1_ENABLE 0} {GRP_SS1_IO {PMC_MIO 14}} {GRP_SS2_ENABLE 0} {GRP_SS2_IO {PMC_MIO 13}} {PERIPHERAL_ENABLE 1} {PERIPHERAL_IO {PS_MIO 12 .. 17}}}\ +\ + PS_SPI1 {{GRP_SS0_ENABLE 0} {GRP_SS0_IO {PS_MIO 9}} {GRP_SS1_ENABLE 0} {GRP_SS1_IO {PS_MIO 8}} {GRP_SS2_ENABLE 0} {GRP_SS2_IO {PS_MIO 7}} {PERIPHERAL_ENABLE 0} {PERIPHERAL_IO {PS_MIO 6 .. 11}}} \ + PS_TTC0_PERIPHERAL_ENABLE {1} \ + PS_TTC1_PERIPHERAL_ENABLE {1} \ + PS_TTC2_PERIPHERAL_ENABLE {1} \ + PS_TTC3_PERIPHERAL_ENABLE {1} \ + PS_UART0_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 8 .. 9}}} \ + PS_UART1_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 20 .. 21}}} \ + PS_USE_FPD_CCI_NOC {0} \ + PS_USE_M_AXI_FPD {0} \ + PS_USE_M_AXI_LPD {1} \ + PS_USE_NOC_LPD_AXI0 {1} \ + PS_USE_PMCPL_CLK0 {1} \ + PS_USE_PMCPL_CLK1 {1} \ + PS_USE_PMCPL_CLK2 {1} \ + PS_USE_PMCPL_CLK3 {1} \ + PS_USE_STARTUP {1} \ + PS_USE_S_AXI_LPD {0} \ + SMON_ALARMS {Set_Alarms_On} \ + SMON_ENABLE_TEMP_AVERAGING {0} \ + SMON_MEAS100 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_500} {SUPPLY_NUM 9}} \ + SMON_MEAS101 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_501} {SUPPLY_NUM 10}} \ + SMON_MEAS102 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_502} {SUPPLY_NUM 11}} \ + SMON_MEAS103 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 4.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {4 V unipolar}} {NAME VCCO_503} {SUPPLY_NUM 12}} \ + SMON_MEAS104 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCO_700} {SUPPLY_NUM 13}} \ + SMON_MEAS105 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCO_701} {SUPPLY_NUM 14}} \ + SMON_MEAS106 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCO_702} {SUPPLY_NUM 15}} \ + SMON_MEAS118 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_PMC} {SUPPLY_NUM 0}} \ + SMON_MEAS119 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_PSFP} {SUPPLY_NUM 1}} \ + SMON_MEAS120 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_PSLP} {SUPPLY_NUM 2}} \ + SMON_MEAS121 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_RAM} {SUPPLY_NUM 3}} \ + SMON_MEAS122 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCC_SOC} {SUPPLY_NUM 4}} \ + SMON_MEAS47 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCCAUX_104} {SUPPLY_NUM 20}} \ + SMON_MEAS48 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCCAUX_105} {SUPPLY_NUM 21}} \ + SMON_MEAS64 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCC_104} {SUPPLY_NUM 18}} \ + SMON_MEAS65 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVCC_105} {SUPPLY_NUM 19}} \ + SMON_MEAS81 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVTT_104} {SUPPLY_NUM 22}} \ + SMON_MEAS82 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME GTYP_AVTT_105} {SUPPLY_NUM 23}} \ + SMON_MEAS96 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCAUX} {SUPPLY_NUM 6}} \ + SMON_MEAS97 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCAUX_PMC} {SUPPLY_NUM 7}} \ + SMON_MEAS98 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCAUX_SMON} {SUPPLY_NUM 8}} \ + SMON_MEAS99 {{ALARM_ENABLE 1} {ALARM_LOWER 0.00} {ALARM_UPPER 2.00} {AVERAGE_EN 0} {ENABLE 1} {MODE {2 V unipolar}} {NAME VCCINT} {SUPPLY_NUM 5}} \ + SMON_TEMP_AVERAGING_SAMPLES {0} \ + SMON_VOLTAGE_AVERAGING_SAMPLES {8} \ + } \ + CONFIG.PS_PMC_CONFIG_APPLIED {1} \ + ] $cips + + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins cips/gt_refclk1] [get_bd_intf_pins gt_pcie_refclk] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins cips/PCIE1_GT] [get_bd_intf_pins gt_pciea1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins base_logic/smbus_rpu] [get_bd_intf_pins smbus_0] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins cips/CPM_PCIE_NOC_0] [get_bd_intf_pins CPM_PCIE_NOC_0] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins cips/CPM_PCIE_NOC_1] [get_bd_intf_pins CPM_PCIE_NOC_1] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins cips/PMC_NOC_AXI_0] [get_bd_intf_pins PMC_NOC_AXI_0] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins cips/LPD_AXI_NOC_0] [get_bd_intf_pins LPD_AXI_NOC_0] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins base_logic/s_axi_pcie_mgmt_slr0] [get_bd_intf_pins s_axi_pcie_mgmt_slr0] + connect_bd_intf_net -intf_net NOC_CPM_PCIE_0_1 [get_bd_intf_pins NOC_CPM_PCIE_0] [get_bd_intf_pins cips/NOC_CPM_PCIE_0] + connect_bd_intf_net -intf_net NOC_PMC_AXI_0_1 [get_bd_intf_pins NOC_PMC_AXI_0] [get_bd_intf_pins cips/NOC_PMC_AXI_0] + connect_bd_intf_net -intf_net base_logic_m_axi_pcie_mgmt_pdi_reset [get_bd_intf_pins base_logic/m_axi_pcie_mgmt_pdi_reset] [get_bd_intf_pins clock_reset/s_axi_pcie_mgmt_pdi_reset] + connect_bd_intf_net -intf_net cips_M_AXI_LPD [get_bd_intf_pins cips/M_AXI_LPD] [get_bd_intf_pins base_logic/s_axi_rpu] + connect_bd_intf_net -intf_net cips_pcie1_cfg_ext [get_bd_intf_pins cips/pcie1_cfg_ext] [get_bd_intf_pins base_logic/pcie_cfg_ext] + + # Create port connections + connect_bd_net -net base_logic_irq_axi_smbus_rpu [get_bd_pins base_logic/irq_axi_smbus_rpu] \ + [get_bd_pins cips/pl_ps_irq1] + connect_bd_net -net base_logic_irq_gcq_m2r [get_bd_pins base_logic/irq_gcq_m2r] \ + [get_bd_pins cips/pl_ps_irq0] + connect_bd_net -net cips_cpm_pcie_noc_axi0_clk [get_bd_pins cips/cpm_pcie_noc_axi0_clk] \ + [get_bd_pins cpm_pcie_noc_axi0_clk] + connect_bd_net -net cips_cpm_pcie_noc_axi1_clk [get_bd_pins cips/cpm_pcie_noc_axi1_clk] \ + [get_bd_pins cpm_pcie_noc_axi1_clk] + connect_bd_net -net cips_dma1_axi_aresetn [get_bd_pins cips/dma1_axi_aresetn] \ + [get_bd_pins clock_reset/dma_axi_aresetn] + connect_bd_net -net cips_eos [get_bd_pins cips/eos] \ + [get_bd_pins eos] + connect_bd_net -net cips_lpd_axi_noc_clk [get_bd_pins cips/lpd_axi_noc_clk] \ + [get_bd_pins lpd_axi_noc_clk] + connect_bd_net -net cips_noc_cpm_pcie_axi0_clk [get_bd_pins cips/noc_cpm_pcie_axi0_clk] \ + [get_bd_pins noc_cpm_pcie_axi0_clk] + connect_bd_net -net cips_noc_pmc_axi_axi0_clk [get_bd_pins cips/noc_pmc_axi_axi0_clk] \ + [get_bd_pins noc_pmc_axi_axi0_clk] + connect_bd_net -net cips_pl0_ref_clk [get_bd_pins cips/pl0_ref_clk] \ + [get_bd_pins pl0_ref_clk] \ + [get_bd_pins cips/m_axi_lpd_aclk] \ + [get_bd_pins base_logic/clk_pl] \ + [get_bd_pins clock_reset/clk_pl] + connect_bd_net -net cips_pl0_resetn [get_bd_pins cips/pl0_resetn] \ + [get_bd_pins clock_reset/resetn_pl_axi] \ + [get_bd_pins pl0_resetn] + connect_bd_net -net cips_pl1_ref_clk [get_bd_pins cips/pl1_ref_clk] \ + [get_bd_pins clock_reset/clk_freerun] + connect_bd_net -net cips_pl2_ref_clk [get_bd_pins cips/pl2_ref_clk] \ + [get_bd_pins cips/dma1_intrfc_clk] \ + [get_bd_pins base_logic/clk_pcie] \ + [get_bd_pins clock_reset/clk_pcie] + connect_bd_net -net cips_pl3_ref_clk [get_bd_pins cips/pl3_ref_clk] \ + [get_bd_pins pl3_ref_clk] + connect_bd_net -net cips_pl3_resetn [get_bd_pins cips/pl3_resetn] \ + [get_bd_pins pl3_resetn] + connect_bd_net -net cips_pmc_axi_noc_axi0_clk [get_bd_pins cips/pmc_axi_noc_axi0_clk] \ + [get_bd_pins pmc_axi_noc_axi0_clk] + connect_bd_net -net clock_reset_resetn_pcie_ic [get_bd_pins clock_reset/resetn_pcie_ic] \ + [get_bd_pins cips/dma1_intrfc_resetn] + connect_bd_net -net clock_reset_resetn_pcie_periph [get_bd_pins clock_reset/resetn_pcie_periph] \ + [get_bd_pins base_logic/resetn_pcie_periph] + connect_bd_net -net clock_reset_resetn_pl_ic [get_bd_pins clock_reset/resetn_pl_ic] \ + [get_bd_pins base_logic/resetn_pl_ic] + connect_bd_net -net clock_reset_resetn_pl_periph [get_bd_pins clock_reset/resetn_pl_periph] \ + [get_bd_pins base_logic/resetn_pl_periph] \ + [get_bd_pins resetn_pl_periph] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: noc +proc create_hier_cell_noc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_noc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S03_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM63_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S01_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S02_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S03_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S04_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S05_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S06_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S07_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S08_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S09_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S10_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S11_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S12_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S13_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S14_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S15_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S16_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S17_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S18_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S19_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S20_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S21_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S22_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S23_INI1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M05_INI + set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_pins /static_region/noc/M05_INI] + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M04_INI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M06_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM00_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM01_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM02_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM03_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM04_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM05_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM06_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM07_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM08_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM09_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM10_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM11_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM12_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM13_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM14_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM15_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM16_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM17_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM18_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM19_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM20_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM21_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM22_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM23_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM24_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM25_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM26_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM27_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM28_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM29_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM30_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM31_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM32_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM33_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM34_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM35_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM36_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM37_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM38_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM39_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM40_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM41_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM42_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM43_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM44_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM45_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM46_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM47_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM48_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM49_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM50_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM51_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM52_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM53_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM54_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM55_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM56_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM57_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM58_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM59_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM60_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM61_AXI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 HBM62_AXI + + + # Create pins + create_bd_pin -dir I -type clk aclk0 + create_bd_pin -dir I -type clk aclk3 + create_bd_pin -dir I -type clk aclk1 + create_bd_pin -dir I -type clk aclk2 + create_bd_pin -dir I -type clk aclk4 + create_bd_pin -dir I -type clk aclk5 + create_bd_pin -dir I -type clk aclk6 + + # Create instance: axi_noc_mc_ddr4_0, and set properties + set axi_noc_mc_ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_mc_ddr4_0 ] + set_property -dict [list \ + CONFIG.CONTROLLERTYPE {DDR4_SDRAM} \ + CONFIG.MC_CHAN_REGION1 {DDR_CH1} \ + CONFIG.MC_COMPONENT_WIDTH {x16} \ + CONFIG.MC_DATAWIDTH {72} \ + CONFIG.MC_DM_WIDTH {9} \ + CONFIG.MC_DQS_WIDTH {9} \ + CONFIG.MC_DQ_WIDTH {72} \ + CONFIG.MC_INIT_MEM_USING_ECC_SCRUB {true} \ + CONFIG.MC_INPUTCLK0_PERIOD {5000} \ + CONFIG.MC_MEMORY_DEVICETYPE {Components} \ + CONFIG.MC_MEMORY_SPEEDGRADE {DDR4-3200AA(22-22-22)} \ + CONFIG.MC_NO_CHANNELS {Single} \ + CONFIG.MC_RANK {1} \ + CONFIG.MC_ROWADDRESSWIDTH {16} \ + CONFIG.MC_STACKHEIGHT {1} \ + CONFIG.MC_SYSTEM_CLOCK {Differential} \ + CONFIG.NUM_CLKS {0} \ + CONFIG.NUM_MC {1} \ + CONFIG.NUM_MCP {4} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {0} \ + CONFIG.NUM_NSI {2} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_mc_ddr4_0 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_0 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_0/S00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_1 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_0/S01_INI] + + # Create instance: axi_noc_cips, and set properties + set axi_noc_cips [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_cips ] + set_property -dict [list \ + CONFIG.HBM_CHNL0_CONFIG {HBM_REORDER_EN FALSE HBM_MAINTAIN_COHERENCY TRUE HBM_Q_AGE_LIMIT 0x7F HBM_CLOSE_PAGE_REORDER FALSE HBM_LOOKAHEAD_PCH TRUE HBM_COMMAND_PARITY FALSE HBM_DQ_WR_PARITY FALSE HBM_DQ_RD_PARITY\ +FALSE HBM_RD_DBI TRUE HBM_WR_DBI TRUE HBM_REFRESH_MODE SINGLE_BANK_REFRESH HBM_PC0_PRE_DEFINED_ADDRESS_MAP USER_DEFINED_ADDRESS_MAP HBM_PC1_PRE_DEFINED_ADDRESS_MAP USER_DEFINED_ADDRESS_MAP HBM_PC0_USER_DEFINED_ADDRESS_MAP\ +1BG-15RA-1SID-2BA-5CA-1BG HBM_PC1_USER_DEFINED_ADDRESS_MAP 1BG-15RA-1SID-2BA-5CA-1BG HBM_PC0_ADDRESS_MAP BA3,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,SID,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BA2,NC,NA,NA,NA,NA\ +HBM_PC1_ADDRESS_MAP BA3,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,SID,BA1,BA0,CA5,CA4,CA3,CA2,CA1,BA2,NC,NA,NA,NA,NA HBM_PWR_DWN_IDLE_TIMEOUT_ENTRY FALSE HBM_SELF_REF_IDLE_TIMEOUT_ENTRY\ +FALSE HBM_IDLE_TIME_TO_ENTER_PWR_DWN_MODE 0x0001000 HBM_IDLE_TIME_TO_ENTER_SELF_REF_MODE 1X HBM_ECC_CORRECTION_EN FALSE HBM_WRITE_BACK_CORRECTED_DATA TRUE HBM_ECC_SCRUBBING FALSE HBM_ECC_INITIALIZE_EN\ +FALSE HBM_ECC_SCRUB_SIZE 1092 HBM_WRITE_DATA_MASK TRUE HBM_REF_PERIOD_TEMP_COMP FALSE HBM_PARITY_LATENCY 3 HBM_PC0_PAGE_HIT 100.000 HBM_PC1_PAGE_HIT 100.000 HBM_PC0_READ_RATE 25.000 HBM_PC1_READ_RATE 25.000\ +HBM_PC0_WRITE_RATE 25.000 HBM_PC1_WRITE_RATE 25.000 HBM_PC0_PHY_ACTIVE ENABLED HBM_PC1_PHY_ACTIVE ENABLED HBM_PC0_SCRUB_START_ADDRESS 0x0000000 HBM_PC0_SCRUB_END_ADDRESS 0x3FFFBFF HBM_PC0_SCRUB_INTERVAL\ +24.000 HBM_PC1_SCRUB_START_ADDRESS 0x0000000 HBM_PC1_SCRUB_END_ADDRESS 0x3FFFBFF HBM_PC1_SCRUB_INTERVAL 24.000} \ + CONFIG.HBM_NUM_CHNL {16} \ + CONFIG.HBM_REF_CLK_FREQ0 {200.000} \ + CONFIG.HBM_REF_CLK_FREQ1 {200.000} \ + CONFIG.HBM_REF_CLK_SELECTION {External} \ + CONFIG.NUM_CLKS {7} \ + CONFIG.NUM_HBM_BLI {64} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_NMI {7} \ + CONFIG.NUM_NSI {24} \ + CONFIG.NUM_SI {4} \ + CONFIG.SI_SIDEBAND_PINS { ,0,0,0} \ + ] $axi_noc_cips + + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X2Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM00_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X3Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM01_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X1Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM02_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X0Y0} \ + CONFIG.CONNECTIONS {HBM0_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM03_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X4Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM04_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X5Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM05_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X6Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM06_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X7Y0} \ + CONFIG.CONNECTIONS {HBM1_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM07_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X10Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM08_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X11Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM09_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X8Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM10_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X9Y0} \ + CONFIG.CONNECTIONS {HBM2_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM11_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X12Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM12_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X13Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM13_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X15Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM14_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X14Y0} \ + CONFIG.CONNECTIONS {HBM3_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM15_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X19Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM16_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X18Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM17_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X17Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM18_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X16Y0} \ + CONFIG.CONNECTIONS {HBM4_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM19_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X20Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM20_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X21Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM21_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X22Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM22_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X23Y0} \ + CONFIG.CONNECTIONS {HBM5_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM23_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X27Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM24_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X26Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM25_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X24Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM26_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X25Y0} \ + CONFIG.CONNECTIONS {HBM6_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM27_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X29Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM28_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X28Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM29_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X31Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM30_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X30Y0} \ + CONFIG.CONNECTIONS {HBM7_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM31_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X35Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM32_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X34Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM33_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X33Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM34_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X32Y0} \ + CONFIG.CONNECTIONS {HBM8_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM35_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X37Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM36_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X36Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM37_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X39Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM38_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X38Y0} \ + CONFIG.CONNECTIONS {HBM9_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM39_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X43Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM40_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X42Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM41_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X41Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM42_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X40Y0} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM43_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X44Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM44_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X45Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM45_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X47Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM46_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X46Y0} \ + CONFIG.CONNECTIONS {HBM11_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM47_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X51Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM48_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X50Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM49_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X48Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM50_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X49Y0} \ + CONFIG.CONNECTIONS {HBM12_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM51_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X52Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM52_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X53Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM53_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X55Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM54_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X54Y0} \ + CONFIG.CONNECTIONS {HBM13_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM55_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X58Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM56_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X59Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM57_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X57Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM58_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X56Y0} \ + CONFIG.CONNECTIONS {HBM14_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM59_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X61Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT0 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM60_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X60Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT1 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM61_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X63Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT2 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM62_AXI] + + set_property -dict [ list \ + CONFIG.PHYSICAL_LOC {NOC_NMU_HBM2E_X62Y0} \ + CONFIG.CONNECTIONS {HBM15_PORT3 {read_bw {2000} write_bw {2000} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl_hbm} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/HBM63_AXI] + + set_property -dict [ list \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.APERTURES {{0x201_0000_0000 0x200_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M00_AXI] + + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.CATEGORY {ps_pmc} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M01_AXI] + + set_property -dict [ list \ + CONFIG.APERTURES {{0x202_0000_0000 0x100_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M04_INI] + + set_property -dict [ list \ + CONFIG.APERTURES {{0x203_0000_0000 0x40_0000}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/M05_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M02_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_AXI {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M06_INI {read_bw {500} write_bw {500}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M04_INI {read_bw {500} write_bw {500}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M05_INI {read_bw {500} write_bw {500}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}}} \ + CONFIG.DEST_IDS {M01_AXI:0x1:M00_AXI:0xd00} \ + CONFIG.REMAPS {M00_INI {{0x20108000000 0x00038000000 0x08000000}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_pcie} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800}} M00_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_AXI {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M01_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M06_INI {read_bw {500} write_bw {500}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M04_INI {read_bw {500} write_bw {500}} M05_INI {read_bw {500} write_bw {500}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M03_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {M01_AXI:0x1:M00_AXI:0xd00} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_pcie} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S01_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M01_INI {read_bw {800} write_bw {800}} M03_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S01_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_pmc} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S02_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800}} M00_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S02_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {ps_rpu} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S03_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {M01_INI {read_bw {800} write_bw {800}} M03_INI {read_bw {800} write_bw {800}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S03_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S04_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S05_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S06_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S07_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S08_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S09_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT0 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT2 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S10_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {auto} \ + CONFIG.CONNECTIONS {HBM10_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM10_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM15_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM5_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM1_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM0_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM6_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM12_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM8_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM14_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM3_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM4_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM9_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM11_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM7_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM2_PORT1 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}} HBM13_PORT3 {read_bw {50} write_bw {50} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S11_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S12_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S13_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S14_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S15_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S16_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S17_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S18_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S19_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S20_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S21_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M02_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S22_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M03_INI {read_bw {50} write_bw {50}}} \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_cips/S23_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk0] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S01_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk1] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S02_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk2] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S03_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk3] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk4] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {HBM00_AXI:HBM01_AXI:HBM02_AXI:HBM03_AXI:HBM04_AXI:HBM05_AXI:HBM06_AXI:HBM07_AXI:HBM08_AXI:HBM09_AXI:HBM10_AXI:HBM11_AXI:HBM12_AXI:HBM13_AXI:HBM14_AXI:HBM15_AXI:HBM16_AXI:HBM17_AXI:HBM18_AXI:HBM19_AXI:HBM20_AXI:HBM21_AXI:HBM22_AXI:HBM23_AXI:HBM24_AXI:HBM25_AXI:HBM26_AXI:HBM27_AXI:HBM28_AXI:HBM29_AXI:HBM30_AXI:HBM31_AXI:HBM32_AXI:HBM33_AXI:HBM34_AXI:HBM35_AXI:HBM36_AXI:HBM37_AXI:HBM38_AXI:HBM39_AXI:HBM40_AXI:HBM41_AXI:HBM42_AXI:HBM43_AXI:HBM44_AXI:HBM45_AXI:HBM46_AXI:HBM47_AXI:HBM48_AXI:HBM49_AXI:HBM50_AXI:HBM51_AXI:HBM52_AXI:HBM53_AXI:HBM54_AXI:HBM55_AXI:HBM56_AXI:HBM57_AXI:HBM58_AXI:HBM59_AXI:HBM60_AXI:HBM61_AXI:HBM62_AXI:HBM63_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk5] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M01_AXI} \ + ] [get_bd_pins /static_region/noc/axi_noc_cips/aclk6] + + # Create instance: axi_noc_mc_ddr4_1, and set properties + set axi_noc_mc_ddr4_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_mc_ddr4_1 ] + set_property -dict [list \ + CONFIG.CONTROLLERTYPE {DDR4_SDRAM} \ + CONFIG.MC0_CONFIG_NUM {config21} \ + CONFIG.MC0_FLIPPED_PINOUT {false} \ + CONFIG.MC_CHAN_REGION0 {DDR_CH2} \ + CONFIG.MC_COMPONENT_WIDTH {x4} \ + CONFIG.MC_DATAWIDTH {72} \ + CONFIG.MC_INIT_MEM_USING_ECC_SCRUB {true} \ + CONFIG.MC_INPUTCLK0_PERIOD {5000} \ + CONFIG.MC_MEMORY_DEVICETYPE {RDIMMs} \ + CONFIG.MC_MEMORY_SPEEDGRADE {DDR4-3200AA(22-22-22)} \ + CONFIG.MC_NO_CHANNELS {Single} \ + CONFIG.MC_PARITY {true} \ + CONFIG.MC_RANK {1} \ + CONFIG.MC_ROWADDRESSWIDTH {18} \ + CONFIG.MC_STACKHEIGHT {1} \ + CONFIG.MC_SYSTEM_CLOCK {Differential} \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MC {1} \ + CONFIG.NUM_MCP {4} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {0} \ + CONFIG.NUM_NSI {2} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_mc_ddr4_1 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_0 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_1/S00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS { MC_1 {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} } } \ + ] [get_bd_intf_pins /static_region/noc/axi_noc_mc_ddr4_1/S01_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {} \ + ] [get_bd_pins /static_region/noc/axi_noc_mc_ddr4_1/aclk0] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_noc_mc_ddr4_1/CH0_DDR4_0] [get_bd_intf_pins CH0_DDR4_0_1] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_noc_mc_ddr4_1/sys_clk0] [get_bd_intf_pins sys_clk0_1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_noc_mc_ddr4_0/sys_clk0] [get_bd_intf_pins sys_clk0_0] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_noc_mc_ddr4_0/CH0_DDR4_0] [get_bd_intf_pins CH0_DDR4_0_0] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_noc_cips/S03_AXI] [get_bd_intf_pins S03_AXI] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins axi_noc_cips/hbm_ref_clk0] [get_bd_intf_pins hbm_ref_clk_0] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins axi_noc_cips/hbm_ref_clk1] [get_bd_intf_pins hbm_ref_clk_1] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins axi_noc_cips/S01_AXI] [get_bd_intf_pins S01_AXI] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins axi_noc_cips/S00_AXI] [get_bd_intf_pins S00_AXI] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins axi_noc_cips/S02_AXI] [get_bd_intf_pins S02_AXI] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins axi_noc_cips/M00_AXI] [get_bd_intf_pins M00_AXI] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins axi_noc_cips/HBM00_AXI] [get_bd_intf_pins HBM00_AXI] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins axi_noc_cips/HBM01_AXI] [get_bd_intf_pins HBM01_AXI] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins axi_noc_cips/HBM02_AXI] [get_bd_intf_pins HBM02_AXI] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins axi_noc_cips/HBM03_AXI] [get_bd_intf_pins HBM03_AXI] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins axi_noc_cips/HBM04_AXI] [get_bd_intf_pins HBM04_AXI] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins axi_noc_cips/HBM05_AXI] [get_bd_intf_pins HBM05_AXI] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins axi_noc_cips/HBM06_AXI] [get_bd_intf_pins HBM06_AXI] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins axi_noc_cips/HBM07_AXI] [get_bd_intf_pins HBM07_AXI] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins axi_noc_cips/HBM08_AXI] [get_bd_intf_pins HBM08_AXI] + connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins axi_noc_cips/HBM09_AXI] [get_bd_intf_pins HBM09_AXI] + connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins axi_noc_cips/HBM10_AXI] [get_bd_intf_pins HBM10_AXI] + connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins axi_noc_cips/HBM11_AXI] [get_bd_intf_pins HBM11_AXI] + connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins axi_noc_cips/HBM12_AXI] [get_bd_intf_pins HBM12_AXI] + connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins axi_noc_cips/HBM13_AXI] [get_bd_intf_pins HBM13_AXI] + connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins axi_noc_cips/HBM14_AXI] [get_bd_intf_pins HBM14_AXI] + connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins axi_noc_cips/HBM15_AXI] [get_bd_intf_pins HBM15_AXI] + connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins axi_noc_cips/HBM16_AXI] [get_bd_intf_pins HBM16_AXI] + connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins axi_noc_cips/HBM17_AXI] [get_bd_intf_pins HBM17_AXI] + connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins axi_noc_cips/HBM18_AXI] [get_bd_intf_pins HBM18_AXI] + connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins axi_noc_cips/HBM19_AXI] [get_bd_intf_pins HBM19_AXI] + connect_bd_intf_net -intf_net Conn32 [get_bd_intf_pins axi_noc_cips/HBM20_AXI] [get_bd_intf_pins HBM20_AXI] + connect_bd_intf_net -intf_net Conn33 [get_bd_intf_pins axi_noc_cips/HBM21_AXI] [get_bd_intf_pins HBM21_AXI] + connect_bd_intf_net -intf_net Conn34 [get_bd_intf_pins axi_noc_cips/HBM22_AXI] [get_bd_intf_pins HBM22_AXI] + connect_bd_intf_net -intf_net Conn35 [get_bd_intf_pins axi_noc_cips/HBM23_AXI] [get_bd_intf_pins HBM23_AXI] + connect_bd_intf_net -intf_net Conn36 [get_bd_intf_pins axi_noc_cips/HBM24_AXI] [get_bd_intf_pins HBM24_AXI] + connect_bd_intf_net -intf_net Conn37 [get_bd_intf_pins axi_noc_cips/HBM25_AXI] [get_bd_intf_pins HBM25_AXI] + connect_bd_intf_net -intf_net Conn38 [get_bd_intf_pins axi_noc_cips/HBM26_AXI] [get_bd_intf_pins HBM26_AXI] + connect_bd_intf_net -intf_net Conn39 [get_bd_intf_pins axi_noc_cips/HBM27_AXI] [get_bd_intf_pins HBM27_AXI] + connect_bd_intf_net -intf_net Conn40 [get_bd_intf_pins axi_noc_cips/HBM28_AXI] [get_bd_intf_pins HBM28_AXI] + connect_bd_intf_net -intf_net Conn41 [get_bd_intf_pins axi_noc_cips/HBM29_AXI] [get_bd_intf_pins HBM29_AXI] + connect_bd_intf_net -intf_net Conn42 [get_bd_intf_pins axi_noc_cips/HBM30_AXI] [get_bd_intf_pins HBM30_AXI] + connect_bd_intf_net -intf_net Conn43 [get_bd_intf_pins axi_noc_cips/HBM31_AXI] [get_bd_intf_pins HBM31_AXI] + connect_bd_intf_net -intf_net Conn44 [get_bd_intf_pins axi_noc_cips/HBM32_AXI] [get_bd_intf_pins HBM32_AXI] + connect_bd_intf_net -intf_net Conn45 [get_bd_intf_pins axi_noc_cips/HBM33_AXI] [get_bd_intf_pins HBM33_AXI] + connect_bd_intf_net -intf_net Conn46 [get_bd_intf_pins axi_noc_cips/HBM34_AXI] [get_bd_intf_pins HBM34_AXI] + connect_bd_intf_net -intf_net Conn47 [get_bd_intf_pins axi_noc_cips/HBM35_AXI] [get_bd_intf_pins HBM35_AXI] + connect_bd_intf_net -intf_net Conn48 [get_bd_intf_pins axi_noc_cips/HBM36_AXI] [get_bd_intf_pins HBM36_AXI] + connect_bd_intf_net -intf_net Conn49 [get_bd_intf_pins axi_noc_cips/HBM37_AXI] [get_bd_intf_pins HBM37_AXI] + connect_bd_intf_net -intf_net Conn50 [get_bd_intf_pins axi_noc_cips/HBM38_AXI] [get_bd_intf_pins HBM38_AXI] + connect_bd_intf_net -intf_net Conn51 [get_bd_intf_pins axi_noc_cips/HBM39_AXI] [get_bd_intf_pins HBM39_AXI] + connect_bd_intf_net -intf_net Conn52 [get_bd_intf_pins axi_noc_cips/HBM40_AXI] [get_bd_intf_pins HBM40_AXI] + connect_bd_intf_net -intf_net Conn53 [get_bd_intf_pins axi_noc_cips/HBM41_AXI] [get_bd_intf_pins HBM41_AXI] + connect_bd_intf_net -intf_net Conn54 [get_bd_intf_pins axi_noc_cips/HBM42_AXI] [get_bd_intf_pins HBM42_AXI] + connect_bd_intf_net -intf_net Conn55 [get_bd_intf_pins axi_noc_cips/HBM43_AXI] [get_bd_intf_pins HBM43_AXI] + connect_bd_intf_net -intf_net Conn56 [get_bd_intf_pins axi_noc_cips/HBM44_AXI] [get_bd_intf_pins HBM44_AXI] + connect_bd_intf_net -intf_net Conn57 [get_bd_intf_pins axi_noc_cips/HBM45_AXI] [get_bd_intf_pins HBM45_AXI] + connect_bd_intf_net -intf_net Conn58 [get_bd_intf_pins axi_noc_cips/HBM46_AXI] [get_bd_intf_pins HBM46_AXI] + connect_bd_intf_net -intf_net Conn59 [get_bd_intf_pins axi_noc_cips/HBM47_AXI] [get_bd_intf_pins HBM47_AXI] + connect_bd_intf_net -intf_net Conn60 [get_bd_intf_pins axi_noc_cips/HBM48_AXI] [get_bd_intf_pins HBM48_AXI] + connect_bd_intf_net -intf_net Conn61 [get_bd_intf_pins axi_noc_cips/HBM49_AXI] [get_bd_intf_pins HBM49_AXI] + connect_bd_intf_net -intf_net Conn62 [get_bd_intf_pins axi_noc_cips/HBM50_AXI] [get_bd_intf_pins HBM50_AXI] + connect_bd_intf_net -intf_net Conn63 [get_bd_intf_pins axi_noc_cips/HBM51_AXI] [get_bd_intf_pins HBM51_AXI] + connect_bd_intf_net -intf_net Conn64 [get_bd_intf_pins axi_noc_cips/HBM52_AXI] [get_bd_intf_pins HBM52_AXI] + connect_bd_intf_net -intf_net Conn65 [get_bd_intf_pins axi_noc_cips/HBM53_AXI] [get_bd_intf_pins HBM53_AXI] + connect_bd_intf_net -intf_net Conn66 [get_bd_intf_pins axi_noc_cips/HBM54_AXI] [get_bd_intf_pins HBM54_AXI] + connect_bd_intf_net -intf_net Conn67 [get_bd_intf_pins axi_noc_cips/HBM55_AXI] [get_bd_intf_pins HBM55_AXI] + connect_bd_intf_net -intf_net Conn68 [get_bd_intf_pins axi_noc_cips/HBM56_AXI] [get_bd_intf_pins HBM56_AXI] + connect_bd_intf_net -intf_net Conn69 [get_bd_intf_pins axi_noc_cips/HBM57_AXI] [get_bd_intf_pins HBM57_AXI] + connect_bd_intf_net -intf_net Conn70 [get_bd_intf_pins axi_noc_cips/HBM58_AXI] [get_bd_intf_pins HBM58_AXI] + connect_bd_intf_net -intf_net Conn71 [get_bd_intf_pins axi_noc_cips/HBM59_AXI] [get_bd_intf_pins HBM59_AXI] + connect_bd_intf_net -intf_net Conn72 [get_bd_intf_pins axi_noc_cips/HBM60_AXI] [get_bd_intf_pins HBM60_AXI] + connect_bd_intf_net -intf_net Conn73 [get_bd_intf_pins axi_noc_cips/HBM61_AXI] [get_bd_intf_pins HBM61_AXI] + connect_bd_intf_net -intf_net Conn74 [get_bd_intf_pins axi_noc_cips/HBM63_AXI] [get_bd_intf_pins HBM63_AXI] + connect_bd_intf_net -intf_net Conn75 [get_bd_intf_pins axi_noc_cips/HBM62_AXI] [get_bd_intf_pins HBM62_AXI] + connect_bd_intf_net -intf_net Conn79 [get_bd_intf_pins axi_noc_cips/S00_INI] [get_bd_intf_pins S00_INI] + connect_bd_intf_net -intf_net Conn80 [get_bd_intf_pins axi_noc_cips/S01_INI] [get_bd_intf_pins S01_INI] + connect_bd_intf_net -intf_net Conn81 [get_bd_intf_pins axi_noc_cips/S02_INI] [get_bd_intf_pins S02_INI] + connect_bd_intf_net -intf_net Conn82 [get_bd_intf_pins axi_noc_cips/S03_INI] [get_bd_intf_pins S03_INI] + connect_bd_intf_net -intf_net Conn83 [get_bd_intf_pins axi_noc_cips/S04_INI] [get_bd_intf_pins S04_INI] + connect_bd_intf_net -intf_net Conn84 [get_bd_intf_pins axi_noc_cips/S05_INI] [get_bd_intf_pins S05_INI] + connect_bd_intf_net -intf_net Conn85 [get_bd_intf_pins axi_noc_cips/S06_INI] [get_bd_intf_pins S06_INI] + connect_bd_intf_net -intf_net Conn86 [get_bd_intf_pins axi_noc_cips/S07_INI] [get_bd_intf_pins S07_INI] + connect_bd_intf_net -intf_net Conn87 [get_bd_intf_pins axi_noc_cips/S08_INI] [get_bd_intf_pins S08_INI] + connect_bd_intf_net -intf_net Conn88 [get_bd_intf_pins axi_noc_cips/S09_INI] [get_bd_intf_pins S09_INI] + connect_bd_intf_net -intf_net Conn89 [get_bd_intf_pins axi_noc_cips/S10_INI] [get_bd_intf_pins S10_INI] + connect_bd_intf_net -intf_net Conn90 [get_bd_intf_pins axi_noc_cips/S11_INI] [get_bd_intf_pins S11_INI] + connect_bd_intf_net -intf_net Conn91 [get_bd_intf_pins axi_noc_cips/S12_INI] [get_bd_intf_pins S12_INI] + connect_bd_intf_net -intf_net Conn92 [get_bd_intf_pins axi_noc_cips/S13_INI] [get_bd_intf_pins S13_INI] + connect_bd_intf_net -intf_net Conn93 [get_bd_intf_pins axi_noc_cips/S14_INI] [get_bd_intf_pins S14_INI] + connect_bd_intf_net -intf_net Conn94 [get_bd_intf_pins axi_noc_cips/S15_INI] [get_bd_intf_pins S15_INI] + connect_bd_intf_net -intf_net Conn95 [get_bd_intf_pins axi_noc_cips/S16_INI] [get_bd_intf_pins S16_INI] + connect_bd_intf_net -intf_net Conn96 [get_bd_intf_pins axi_noc_cips/S17_INI] [get_bd_intf_pins S17_INI] + connect_bd_intf_net -intf_net Conn97 [get_bd_intf_pins axi_noc_cips/S18_INI] [get_bd_intf_pins S18_INI] + connect_bd_intf_net -intf_net Conn98 [get_bd_intf_pins axi_noc_cips/S19_INI] [get_bd_intf_pins S19_INI] + connect_bd_intf_net -intf_net Conn99 [get_bd_intf_pins axi_noc_cips/S20_INI] [get_bd_intf_pins S20_INI1] + connect_bd_intf_net -intf_net Conn100 [get_bd_intf_pins axi_noc_cips/S21_INI] [get_bd_intf_pins S21_INI1] + connect_bd_intf_net -intf_net Conn101 [get_bd_intf_pins axi_noc_cips/S22_INI] [get_bd_intf_pins S22_INI1] + connect_bd_intf_net -intf_net Conn102 [get_bd_intf_pins axi_noc_cips/S23_INI] [get_bd_intf_pins S23_INI1] + connect_bd_intf_net -intf_net Conn103 [get_bd_intf_pins axi_noc_cips/M05_INI] [get_bd_intf_pins M05_INI] + connect_bd_intf_net -intf_net Conn104 [get_bd_intf_pins axi_noc_cips/M04_INI] [get_bd_intf_pins M04_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M00_INI [get_bd_intf_pins axi_noc_cips/M00_INI] [get_bd_intf_pins axi_noc_mc_ddr4_0/S00_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M01_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_noc_cips/M01_AXI] + connect_bd_intf_net -intf_net axi_noc_cips_M01_INI [get_bd_intf_pins axi_noc_cips/M01_INI] [get_bd_intf_pins axi_noc_mc_ddr4_0/S01_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M02_INI [get_bd_intf_pins axi_noc_cips/M02_INI] [get_bd_intf_pins axi_noc_mc_ddr4_1/S00_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M03_INI [get_bd_intf_pins axi_noc_cips/M03_INI] [get_bd_intf_pins axi_noc_mc_ddr4_1/S01_INI] + connect_bd_intf_net -intf_net axi_noc_cips_M06_INI [get_bd_intf_pins M06_INI] [get_bd_intf_pins axi_noc_cips/M06_INI] + + # Create port connections + connect_bd_net -net aclk0_1 [get_bd_pins aclk0] \ + [get_bd_pins axi_noc_mc_ddr4_1/aclk0] \ + [get_bd_pins axi_noc_cips/aclk4] + connect_bd_net -net aclk1_1 [get_bd_pins aclk1] \ + [get_bd_pins axi_noc_cips/aclk1] + connect_bd_net -net aclk2_1 [get_bd_pins aclk2] \ + [get_bd_pins axi_noc_cips/aclk2] + connect_bd_net -net aclk3_1 [get_bd_pins aclk3] \ + [get_bd_pins axi_noc_cips/aclk3] + connect_bd_net -net aclk4_1 [get_bd_pins aclk4] \ + [get_bd_pins axi_noc_cips/aclk0] + connect_bd_net -net aclk5_1 [get_bd_pins aclk5] \ + [get_bd_pins axi_noc_cips/aclk5] + connect_bd_net -net aclk6_1 [get_bd_pins aclk6] \ + [get_bd_pins axi_noc_cips/aclk6] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: static_region +proc create_hier_cell_static_region { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_static_region() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_pcie_refclk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_pciea1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S01_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S02_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S03_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S04_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S05_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S06_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S07_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S08_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S09_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S10_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S11_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S12_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S13_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S14_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S15_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S16_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S17_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S18_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S19_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S20_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S21_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S22_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S23_INI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M05_INI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M04_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS4 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS5 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS6 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS6 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS7 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS7 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS8 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS8 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS9 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS9 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS10 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS10 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS11 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS11 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS12 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS12 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS13 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS13 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS14 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS14 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inis_rtl:1.0 S00_INIS15 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inis_rtl:1.0 M00_INIS15 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI6 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 S00_INI5 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI3 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 M00_INI4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_6 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_7 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_8 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_9 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_10 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_11 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_12 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_13 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_14 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_15 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_16 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_17 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_18 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_19 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_20 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_21 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_22 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_23 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_24 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_25 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_26 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_27 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_28 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_29 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_30 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_31 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_32 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_33 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_34 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_35 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_36 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_37 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_38 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_39 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_40 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_41 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_42 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_43 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_44 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_45 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_46 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_47 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_48 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_49 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_50 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_51 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_52 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_53 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_54 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_55 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_56 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_57 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_58 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_59 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_60 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_61 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_62 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 rp_intf_63 + + + # Create pins + create_bd_pin -dir O -type clk pl0_ref_clk + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_periph + create_bd_pin -dir O -type clk clk_out1 + create_bd_pin -dir O -type clk pl3_ref_clk + create_bd_pin -dir O -type rst pl3_resetn + create_bd_pin -dir O -type clk clk_out2 + create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn1 + create_bd_pin -dir O -type clk clk_out3 + create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn2 + + # Create instance: noc + create_hier_cell_noc $hier_obj noc + + # Create instance: aved + create_hier_cell_aved $hier_obj aved + + # Create instance: clk_wizard_0, and set properties + set clk_wizard_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_0 ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {No_buffer,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {400,100.000,100.000,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.USE_DYN_RECONFIG {false} \ + ] $clk_wizard_0 + + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: dcmac_noc + create_hier_cell_dcmac_noc $hier_obj dcmac_noc + + # Create instance: axi_noc_1, and set properties + set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.1 axi_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_1 + + + set_property -dict [ list \ + CONFIG.CATEGORY {ps_pcie} \ + ] [get_bd_intf_pins /static_region/axi_noc_1/M00_AXI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /static_region/axi_noc_1/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {} \ + ] [get_bd_pins /static_region/axi_noc_1/aclk0] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /static_region/axi_noc_1/aclk1] + + # Create instance: util_vector_logic_0, and set properties + set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $util_vector_logic_0 + + + # Create instance: virt_noc + create_hier_cell_virt_noc $hier_obj virt_noc + + # Create instance: clk_rst_shell + create_hier_cell_clk_rst_shell $hier_obj clk_rst_shell + + # Create instance: dfx_decoupler_0, and set properties + set dfx_decoupler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:dfx_decoupler:1.0 dfx_decoupler_0 ] + set_property -dict [list \ + CONFIG.ALL_PARAMS {INTF {intf_0 {ID 0 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH\ +1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR\ +{WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4\ +PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH\ +0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK\ +{WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT\ +1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_1 {ID 1 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH\ +1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT\ +1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH\ +4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1}\ +WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT\ +1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER\ +{WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_2 {ID 2 VLNV xilinx.com:interface:aximm_rtl:1.0\ +PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH\ +1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST\ +{WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT\ +0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_3 {ID 3 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_4 {ID 4 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID\ +{WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT\ +1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH\ +3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER\ +{WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1}\ +ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH\ +0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_5 {ID 5 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID\ +{WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1\ +PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK\ +{WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT\ +1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT\ +1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS\ +{WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_6 {ID 6 VLNV xilinx.com:interface:aximm_rtl:1.0\ +PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH\ +1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST\ +{WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT\ +0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_7 {ID 7 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_8 {ID 8 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID\ +{WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT\ +1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH\ +3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER\ +{WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1}\ +ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH\ +0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_9 {ID 9 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID\ +{WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1\ +PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK\ +{WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT\ +1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT\ +1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS\ +{WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_10 {ID 10 VLNV xilinx.com:interface:aximm_rtl:1.0\ +PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH\ +1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST\ +{WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT\ +0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_11 {ID 11 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_12 {ID 12 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_13 {ID 13 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_14 {ID 14 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_15 {ID 15 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_16 {ID 16 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_17 {ID 17 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_18 {ID 18 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_19 {ID 19 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_20 {ID 20 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_21 {ID 21 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_22 {ID 22 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_23 {ID 23 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_24 {ID 24 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_25 {ID 25 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_26 {ID 26 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_27 {ID 27 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_28 {ID 28 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_29 {ID 29 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_30 {ID 30 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_31 {ID 31 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_32 {ID 32 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_33 {ID 33 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_34 {ID 34 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_35 {ID 35 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_36 {ID 36 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_37 {ID 37 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_38 {ID 38 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_39 {ID 39 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_40 {ID 40 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_41 {ID 41 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_42 {ID 42 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_43 {ID 43 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_44 {ID 44 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_45 {ID 45 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_46 {ID 46 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_47 {ID 47 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_48 {ID 48 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_49 {ID 49 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_50 {ID 50 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_51 {ID 51 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_52 {ID 52 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_53 {ID 53 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_54 {ID 54 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_55 {ID 55 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_56 {ID 56 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_57 {ID 57 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_58 {ID 58 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_59 {ID 59 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_60 {ID 60 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_61 {ID 61 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL\ +AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT\ +1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH\ +2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0}\ +WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT\ +0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION\ +{WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}\ +intf_62 {ID 62 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1} AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH\ +1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH 1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1}\ +AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1} AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH\ +4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH 1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP\ +{WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE {WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT\ +1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0 PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH\ +2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}} intf_63 {ID 63 VLNV xilinx.com:interface:aximm_rtl:1.0 PROTOCOL AXI4 SIGNALS {ARVALID {WIDTH 1 PRESENT 1} ARREADY {WIDTH 1 PRESENT 1}\ +AWVALID {WIDTH 1 PRESENT 1} AWREADY {WIDTH 1 PRESENT 1} BVALID {WIDTH 1 PRESENT 1} BREADY {WIDTH 1 PRESENT 1} RVALID {WIDTH 1 PRESENT 1} RREADY {WIDTH 1 PRESENT 1} WVALID {WIDTH 1 PRESENT 1} WREADY {WIDTH\ +1 PRESENT 1} AWID {WIDTH 0 PRESENT 0} AWADDR {WIDTH 64 PRESENT 1} AWLEN {WIDTH 8 PRESENT 1} AWSIZE {WIDTH 3 PRESENT 1} AWBURST {WIDTH 2 PRESENT 1} AWLOCK {WIDTH 1 PRESENT 1} AWCACHE {WIDTH 4 PRESENT 1}\ +AWPROT {WIDTH 3 PRESENT 1} AWREGION {WIDTH 4 PRESENT 0} AWQOS {WIDTH 4 PRESENT 1} AWUSER {WIDTH 0 PRESENT 0} WID {WIDTH 0 PRESENT 0} WDATA {WIDTH 256 PRESENT 1} WSTRB {WIDTH 32 PRESENT 1} WLAST {WIDTH\ +1 PRESENT 1} WUSER {WIDTH 0 PRESENT 0} BID {WIDTH 0 PRESENT 0} BRESP {WIDTH 2 PRESENT 1} BUSER {WIDTH 0 PRESENT 0} ARID {WIDTH 0 PRESENT 0} ARADDR {WIDTH 64 PRESENT 1} ARLEN {WIDTH 8 PRESENT 1} ARSIZE\ +{WIDTH 3 PRESENT 1} ARBURST {WIDTH 2 PRESENT 1} ARLOCK {WIDTH 1 PRESENT 1} ARCACHE {WIDTH 4 PRESENT 1} ARPROT {WIDTH 3 PRESENT 1} ARREGION {WIDTH 4 PRESENT 0} ARQOS {WIDTH 4 PRESENT 1} ARUSER {WIDTH 0\ +PRESENT 0} RID {WIDTH 0 PRESENT 0} RDATA {WIDTH 256 PRESENT 1} RRESP {WIDTH 2 PRESENT 0} RLAST {WIDTH 1 PRESENT 1} RUSER {WIDTH 0 PRESENT 0}}}}} \ + CONFIG.GUI_SELECT_VLNV {xilinx.com:interface:aximm_rtl:1.0} \ + ] $dfx_decoupler_0 + + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins virt_noc/M00_INI] [get_bd_intf_pins M00_INI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dfx_decoupler_0/rp_intf_0] [get_bd_intf_pins rp_intf_0] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dfx_decoupler_0/rp_intf_1] [get_bd_intf_pins rp_intf_1] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dfx_decoupler_0/rp_intf_2] [get_bd_intf_pins rp_intf_2] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins noc/sys_clk0_0] [get_bd_intf_pins sys_clk0_0] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins noc/CH0_DDR4_0_0] [get_bd_intf_pins CH0_DDR4_0_0] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins noc/CH0_DDR4_0_1] [get_bd_intf_pins CH0_DDR4_0_1] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins noc/hbm_ref_clk_0] [get_bd_intf_pins hbm_ref_clk_0] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins noc/sys_clk0_1] [get_bd_intf_pins sys_clk0_1] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dfx_decoupler_0/rp_intf_3] [get_bd_intf_pins rp_intf_3] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dfx_decoupler_0/rp_intf_4] [get_bd_intf_pins rp_intf_4] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dfx_decoupler_0/rp_intf_5] [get_bd_intf_pins rp_intf_5] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dfx_decoupler_0/rp_intf_6] [get_bd_intf_pins rp_intf_6] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dfx_decoupler_0/rp_intf_7] [get_bd_intf_pins rp_intf_7] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dfx_decoupler_0/rp_intf_8] [get_bd_intf_pins rp_intf_8] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dfx_decoupler_0/rp_intf_9] [get_bd_intf_pins rp_intf_9] + connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins dfx_decoupler_0/rp_intf_10] [get_bd_intf_pins rp_intf_10] + connect_bd_intf_net -intf_net Conn18 [get_bd_intf_pins dfx_decoupler_0/rp_intf_11] [get_bd_intf_pins rp_intf_11] + connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins dfx_decoupler_0/rp_intf_12] [get_bd_intf_pins rp_intf_12] + connect_bd_intf_net -intf_net Conn20 [get_bd_intf_pins dfx_decoupler_0/rp_intf_13] [get_bd_intf_pins rp_intf_13] + connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins dfx_decoupler_0/rp_intf_14] [get_bd_intf_pins rp_intf_14] + connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins dfx_decoupler_0/rp_intf_15] [get_bd_intf_pins rp_intf_15] + connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins dfx_decoupler_0/rp_intf_16] [get_bd_intf_pins rp_intf_16] + connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins dfx_decoupler_0/rp_intf_17] [get_bd_intf_pins rp_intf_17] + connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins dfx_decoupler_0/rp_intf_18] [get_bd_intf_pins rp_intf_18] + connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins dfx_decoupler_0/rp_intf_19] [get_bd_intf_pins rp_intf_19] + connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins dfx_decoupler_0/rp_intf_20] [get_bd_intf_pins rp_intf_20] + connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins dfx_decoupler_0/rp_intf_21] [get_bd_intf_pins rp_intf_21] + connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins dfx_decoupler_0/rp_intf_22] [get_bd_intf_pins rp_intf_22] + connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins dfx_decoupler_0/rp_intf_23] [get_bd_intf_pins rp_intf_23] + connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins dfx_decoupler_0/rp_intf_24] [get_bd_intf_pins rp_intf_24] + connect_bd_intf_net -intf_net Conn32 [get_bd_intf_pins dfx_decoupler_0/rp_intf_25] [get_bd_intf_pins rp_intf_25] + connect_bd_intf_net -intf_net Conn33 [get_bd_intf_pins dfx_decoupler_0/rp_intf_26] [get_bd_intf_pins rp_intf_26] + connect_bd_intf_net -intf_net Conn34 [get_bd_intf_pins dfx_decoupler_0/rp_intf_27] [get_bd_intf_pins rp_intf_27] + connect_bd_intf_net -intf_net Conn35 [get_bd_intf_pins dfx_decoupler_0/rp_intf_28] [get_bd_intf_pins rp_intf_28] + connect_bd_intf_net -intf_net Conn36 [get_bd_intf_pins dfx_decoupler_0/rp_intf_29] [get_bd_intf_pins rp_intf_29] + connect_bd_intf_net -intf_net Conn37 [get_bd_intf_pins dfx_decoupler_0/rp_intf_30] [get_bd_intf_pins rp_intf_30] + connect_bd_intf_net -intf_net Conn38 [get_bd_intf_pins dfx_decoupler_0/rp_intf_31] [get_bd_intf_pins rp_intf_31] + connect_bd_intf_net -intf_net Conn39 [get_bd_intf_pins dfx_decoupler_0/rp_intf_32] [get_bd_intf_pins rp_intf_32] + connect_bd_intf_net -intf_net Conn40 [get_bd_intf_pins dfx_decoupler_0/rp_intf_33] [get_bd_intf_pins rp_intf_33] + connect_bd_intf_net -intf_net Conn41 [get_bd_intf_pins dfx_decoupler_0/rp_intf_34] [get_bd_intf_pins rp_intf_34] + connect_bd_intf_net -intf_net Conn42 [get_bd_intf_pins dfx_decoupler_0/rp_intf_35] [get_bd_intf_pins rp_intf_35] + connect_bd_intf_net -intf_net Conn43 [get_bd_intf_pins dfx_decoupler_0/rp_intf_36] [get_bd_intf_pins rp_intf_36] + connect_bd_intf_net -intf_net Conn44 [get_bd_intf_pins dfx_decoupler_0/rp_intf_37] [get_bd_intf_pins rp_intf_37] + connect_bd_intf_net -intf_net Conn45 [get_bd_intf_pins dfx_decoupler_0/rp_intf_38] [get_bd_intf_pins rp_intf_38] + connect_bd_intf_net -intf_net Conn46 [get_bd_intf_pins dfx_decoupler_0/rp_intf_39] [get_bd_intf_pins rp_intf_39] + connect_bd_intf_net -intf_net Conn47 [get_bd_intf_pins dfx_decoupler_0/rp_intf_40] [get_bd_intf_pins rp_intf_40] + connect_bd_intf_net -intf_net Conn48 [get_bd_intf_pins dfx_decoupler_0/rp_intf_41] [get_bd_intf_pins rp_intf_41] + connect_bd_intf_net -intf_net Conn49 [get_bd_intf_pins dfx_decoupler_0/rp_intf_42] [get_bd_intf_pins rp_intf_42] + connect_bd_intf_net -intf_net Conn50 [get_bd_intf_pins dfx_decoupler_0/rp_intf_43] [get_bd_intf_pins rp_intf_43] + connect_bd_intf_net -intf_net Conn51 [get_bd_intf_pins dfx_decoupler_0/rp_intf_44] [get_bd_intf_pins rp_intf_44] + connect_bd_intf_net -intf_net Conn52 [get_bd_intf_pins dfx_decoupler_0/rp_intf_45] [get_bd_intf_pins rp_intf_45] + connect_bd_intf_net -intf_net Conn53 [get_bd_intf_pins dfx_decoupler_0/rp_intf_46] [get_bd_intf_pins rp_intf_46] + connect_bd_intf_net -intf_net Conn54 [get_bd_intf_pins dfx_decoupler_0/rp_intf_47] [get_bd_intf_pins rp_intf_47] + connect_bd_intf_net -intf_net Conn55 [get_bd_intf_pins dfx_decoupler_0/rp_intf_48] [get_bd_intf_pins rp_intf_48] + connect_bd_intf_net -intf_net Conn56 [get_bd_intf_pins dfx_decoupler_0/rp_intf_49] [get_bd_intf_pins rp_intf_49] + connect_bd_intf_net -intf_net Conn57 [get_bd_intf_pins dfx_decoupler_0/rp_intf_50] [get_bd_intf_pins rp_intf_50] + connect_bd_intf_net -intf_net Conn58 [get_bd_intf_pins dfx_decoupler_0/rp_intf_51] [get_bd_intf_pins rp_intf_51] + connect_bd_intf_net -intf_net Conn59 [get_bd_intf_pins dfx_decoupler_0/rp_intf_52] [get_bd_intf_pins rp_intf_52] + connect_bd_intf_net -intf_net Conn60 [get_bd_intf_pins dfx_decoupler_0/rp_intf_53] [get_bd_intf_pins rp_intf_53] + connect_bd_intf_net -intf_net Conn61 [get_bd_intf_pins dfx_decoupler_0/rp_intf_54] [get_bd_intf_pins rp_intf_54] + connect_bd_intf_net -intf_net Conn62 [get_bd_intf_pins dfx_decoupler_0/rp_intf_55] [get_bd_intf_pins rp_intf_55] + connect_bd_intf_net -intf_net Conn63 [get_bd_intf_pins dfx_decoupler_0/rp_intf_56] [get_bd_intf_pins rp_intf_56] + connect_bd_intf_net -intf_net Conn64 [get_bd_intf_pins dfx_decoupler_0/rp_intf_57] [get_bd_intf_pins rp_intf_57] + connect_bd_intf_net -intf_net Conn65 [get_bd_intf_pins dfx_decoupler_0/rp_intf_58] [get_bd_intf_pins rp_intf_58] + connect_bd_intf_net -intf_net Conn66 [get_bd_intf_pins dfx_decoupler_0/rp_intf_59] [get_bd_intf_pins rp_intf_59] + connect_bd_intf_net -intf_net Conn67 [get_bd_intf_pins dfx_decoupler_0/rp_intf_60] [get_bd_intf_pins rp_intf_60] + connect_bd_intf_net -intf_net Conn68 [get_bd_intf_pins dfx_decoupler_0/rp_intf_61] [get_bd_intf_pins rp_intf_61] + connect_bd_intf_net -intf_net Conn69 [get_bd_intf_pins dfx_decoupler_0/rp_intf_62] [get_bd_intf_pins rp_intf_62] + connect_bd_intf_net -intf_net Conn70 [get_bd_intf_pins dfx_decoupler_0/rp_intf_63] [get_bd_intf_pins rp_intf_63] + connect_bd_intf_net -intf_net Conn71 [get_bd_intf_pins noc/hbm_ref_clk_1] [get_bd_intf_pins hbm_ref_clk_1] + connect_bd_intf_net -intf_net Conn72 [get_bd_intf_pins aved/gt_pcie_refclk] [get_bd_intf_pins gt_pcie_refclk] + connect_bd_intf_net -intf_net Conn73 [get_bd_intf_pins aved/smbus_0] [get_bd_intf_pins smbus_0] + connect_bd_intf_net -intf_net Conn74 [get_bd_intf_pins aved/gt_pciea1] [get_bd_intf_pins gt_pciea1] + connect_bd_intf_net -intf_net Conn75 [get_bd_intf_pins noc/S00_INI] [get_bd_intf_pins S00_INI] + connect_bd_intf_net -intf_net Conn76 [get_bd_intf_pins noc/S01_INI] [get_bd_intf_pins S01_INI] + connect_bd_intf_net -intf_net Conn77 [get_bd_intf_pins noc/S02_INI] [get_bd_intf_pins S02_INI] + connect_bd_intf_net -intf_net Conn78 [get_bd_intf_pins noc/S03_INI] [get_bd_intf_pins S03_INI] + connect_bd_intf_net -intf_net Conn79 [get_bd_intf_pins noc/S04_INI] [get_bd_intf_pins S04_INI] + connect_bd_intf_net -intf_net Conn80 [get_bd_intf_pins noc/S05_INI] [get_bd_intf_pins S05_INI] + connect_bd_intf_net -intf_net Conn81 [get_bd_intf_pins noc/S06_INI] [get_bd_intf_pins S06_INI] + connect_bd_intf_net -intf_net Conn82 [get_bd_intf_pins noc/S07_INI] [get_bd_intf_pins S07_INI] + connect_bd_intf_net -intf_net Conn83 [get_bd_intf_pins noc/S08_INI] [get_bd_intf_pins S08_INI] + connect_bd_intf_net -intf_net Conn84 [get_bd_intf_pins noc/S09_INI] [get_bd_intf_pins S09_INI] + connect_bd_intf_net -intf_net Conn85 [get_bd_intf_pins noc/S10_INI] [get_bd_intf_pins S10_INI] + connect_bd_intf_net -intf_net Conn86 [get_bd_intf_pins noc/S11_INI] [get_bd_intf_pins S11_INI] + connect_bd_intf_net -intf_net Conn87 [get_bd_intf_pins dcmac_noc/S00_INIS] [get_bd_intf_pins S00_INIS] + connect_bd_intf_net -intf_net Conn88 [get_bd_intf_pins virt_noc/S00_INI] [get_bd_intf_pins S00_INI1] + connect_bd_intf_net -intf_net Conn89 [get_bd_intf_pins noc/M05_INI] [get_bd_intf_pins M05_INI] + connect_bd_intf_net -intf_net Conn90 [get_bd_intf_pins noc/M04_INI] [get_bd_intf_pins M04_INI] + connect_bd_intf_net -intf_net Conn91 [get_bd_intf_pins dcmac_noc/M00_INIS] [get_bd_intf_pins M00_INIS] + connect_bd_intf_net -intf_net Conn92 [get_bd_intf_pins dcmac_noc/S00_INIS1] [get_bd_intf_pins S00_INIS1] + connect_bd_intf_net -intf_net Conn93 [get_bd_intf_pins dcmac_noc/M00_INIS1] [get_bd_intf_pins M00_INIS1] + connect_bd_intf_net -intf_net Conn94 [get_bd_intf_pins dcmac_noc/S00_INIS2] [get_bd_intf_pins S00_INIS2] + connect_bd_intf_net -intf_net Conn95 [get_bd_intf_pins dcmac_noc/M00_INIS2] [get_bd_intf_pins M00_INIS2] + connect_bd_intf_net -intf_net Conn96 [get_bd_intf_pins dcmac_noc/S00_INIS3] [get_bd_intf_pins S00_INIS3] + connect_bd_intf_net -intf_net Conn97 [get_bd_intf_pins dcmac_noc/M00_INIS3] [get_bd_intf_pins M00_INIS3] + connect_bd_intf_net -intf_net Conn98 [get_bd_intf_pins dcmac_noc/S00_INIS4] [get_bd_intf_pins S00_INIS4] + connect_bd_intf_net -intf_net Conn99 [get_bd_intf_pins dcmac_noc/M00_INIS4] [get_bd_intf_pins M00_INIS4] + connect_bd_intf_net -intf_net Conn100 [get_bd_intf_pins dcmac_noc/S00_INIS5] [get_bd_intf_pins S00_INIS5] + connect_bd_intf_net -intf_net Conn101 [get_bd_intf_pins dcmac_noc/M00_INIS5] [get_bd_intf_pins M00_INIS5] + connect_bd_intf_net -intf_net Conn102 [get_bd_intf_pins dcmac_noc/S00_INIS6] [get_bd_intf_pins S00_INIS6] + connect_bd_intf_net -intf_net Conn103 [get_bd_intf_pins dcmac_noc/M00_INIS6] [get_bd_intf_pins M00_INIS6] + connect_bd_intf_net -intf_net Conn104 [get_bd_intf_pins dcmac_noc/S00_INIS7] [get_bd_intf_pins S00_INIS7] + connect_bd_intf_net -intf_net Conn105 [get_bd_intf_pins dcmac_noc/M00_INIS7] [get_bd_intf_pins M00_INIS7] + connect_bd_intf_net -intf_net Conn106 [get_bd_intf_pins dcmac_noc/S00_INIS8] [get_bd_intf_pins S00_INIS8] + connect_bd_intf_net -intf_net Conn107 [get_bd_intf_pins dcmac_noc/M00_INIS8] [get_bd_intf_pins M00_INIS8] + connect_bd_intf_net -intf_net Conn108 [get_bd_intf_pins dcmac_noc/S00_INIS9] [get_bd_intf_pins S00_INIS9] + connect_bd_intf_net -intf_net Conn109 [get_bd_intf_pins dcmac_noc/M00_INIS9] [get_bd_intf_pins M00_INIS9] + connect_bd_intf_net -intf_net Conn110 [get_bd_intf_pins dcmac_noc/S00_INIS10] [get_bd_intf_pins S00_INIS10] + connect_bd_intf_net -intf_net Conn111 [get_bd_intf_pins dcmac_noc/M00_INIS10] [get_bd_intf_pins M00_INIS10] + connect_bd_intf_net -intf_net Conn112 [get_bd_intf_pins dcmac_noc/S00_INIS11] [get_bd_intf_pins S00_INIS11] + connect_bd_intf_net -intf_net Conn113 [get_bd_intf_pins dcmac_noc/M00_INIS11] [get_bd_intf_pins M00_INIS11] + connect_bd_intf_net -intf_net Conn114 [get_bd_intf_pins dcmac_noc/S00_INIS12] [get_bd_intf_pins S00_INIS12] + connect_bd_intf_net -intf_net Conn115 [get_bd_intf_pins dcmac_noc/M00_INIS12] [get_bd_intf_pins M00_INIS12] + connect_bd_intf_net -intf_net Conn116 [get_bd_intf_pins dcmac_noc/S00_INIS13] [get_bd_intf_pins S00_INIS13] + connect_bd_intf_net -intf_net Conn117 [get_bd_intf_pins dcmac_noc/M00_INIS13] [get_bd_intf_pins M00_INIS13] + connect_bd_intf_net -intf_net Conn118 [get_bd_intf_pins dcmac_noc/S00_INIS14] [get_bd_intf_pins S00_INIS14] + connect_bd_intf_net -intf_net Conn119 [get_bd_intf_pins dcmac_noc/M00_INIS14] [get_bd_intf_pins M00_INIS14] + connect_bd_intf_net -intf_net Conn120 [get_bd_intf_pins dcmac_noc/S00_INIS15] [get_bd_intf_pins S00_INIS15] + connect_bd_intf_net -intf_net Conn121 [get_bd_intf_pins dcmac_noc/M00_INIS15] [get_bd_intf_pins M00_INIS15] + connect_bd_intf_net -intf_net Conn122 [get_bd_intf_pins virt_noc/S00_INI1] [get_bd_intf_pins S00_INI2] + connect_bd_intf_net -intf_net Conn123 [get_bd_intf_pins virt_noc/S00_INI2] [get_bd_intf_pins S00_INI3] + connect_bd_intf_net -intf_net Conn124 [get_bd_intf_pins virt_noc/S00_INI3] [get_bd_intf_pins S00_INI4] + connect_bd_intf_net -intf_net Conn125 [get_bd_intf_pins virt_noc/S00_INI4] [get_bd_intf_pins S00_INI5] + connect_bd_intf_net -intf_net Conn126 [get_bd_intf_pins virt_noc/M00_INI1] [get_bd_intf_pins M00_INI1] + connect_bd_intf_net -intf_net Conn127 [get_bd_intf_pins virt_noc/M00_INI2] [get_bd_intf_pins M00_INI2] + connect_bd_intf_net -intf_net Conn128 [get_bd_intf_pins virt_noc/M00_INI3] [get_bd_intf_pins M00_INI3] + connect_bd_intf_net -intf_net Conn129 [get_bd_intf_pins virt_noc/M00_INI4] [get_bd_intf_pins M00_INI4] + connect_bd_intf_net -intf_net Conn130 [get_bd_intf_pins axi_noc_1/S00_INI] [get_bd_intf_pins S00_INI6] + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins noc/S00_AXI] [get_bd_intf_pins aved/CPM_PCIE_NOC_0] + connect_bd_intf_net -intf_net S00_INI_1 [get_bd_intf_pins clk_rst_shell/S00_INI] [get_bd_intf_pins noc/M06_INI] + connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_pins noc/S01_AXI] [get_bd_intf_pins aved/CPM_PCIE_NOC_1] + connect_bd_intf_net -intf_net S02_AXI_1 [get_bd_intf_pins noc/S02_AXI] [get_bd_intf_pins aved/PMC_NOC_AXI_0] + connect_bd_intf_net -intf_net S03_AXI_1 [get_bd_intf_pins noc/S03_AXI] [get_bd_intf_pins aved/LPD_AXI_NOC_0] + connect_bd_intf_net -intf_net S12_INI_1 [get_bd_intf_pins S12_INI] [get_bd_intf_pins noc/S12_INI] + connect_bd_intf_net -intf_net S13_INI_1 [get_bd_intf_pins S13_INI] [get_bd_intf_pins noc/S13_INI] + connect_bd_intf_net -intf_net S14_INI_1 [get_bd_intf_pins S14_INI] [get_bd_intf_pins noc/S14_INI] + connect_bd_intf_net -intf_net S15_INI_1 [get_bd_intf_pins S15_INI] [get_bd_intf_pins noc/S15_INI] + connect_bd_intf_net -intf_net S16_INI_1 [get_bd_intf_pins S16_INI] [get_bd_intf_pins noc/S16_INI] + connect_bd_intf_net -intf_net S17_INI_1 [get_bd_intf_pins S17_INI] [get_bd_intf_pins noc/S17_INI] + connect_bd_intf_net -intf_net S18_INI_1 [get_bd_intf_pins S18_INI] [get_bd_intf_pins noc/S18_INI] + connect_bd_intf_net -intf_net S19_INI_1 [get_bd_intf_pins S19_INI] [get_bd_intf_pins noc/S19_INI] + connect_bd_intf_net -intf_net S20_INI1_1 [get_bd_intf_pins S20_INI] [get_bd_intf_pins noc/S20_INI1] + connect_bd_intf_net -intf_net S21_INI1_1 [get_bd_intf_pins S21_INI] [get_bd_intf_pins noc/S21_INI1] + connect_bd_intf_net -intf_net S22_INI1_1 [get_bd_intf_pins S22_INI] [get_bd_intf_pins noc/S22_INI1] + connect_bd_intf_net -intf_net S23_INI1_1 [get_bd_intf_pins S23_INI] [get_bd_intf_pins noc/S23_INI1] + connect_bd_intf_net -intf_net axi_noc_1_M00_AXI [get_bd_intf_pins axi_noc_1/M00_AXI] [get_bd_intf_pins aved/NOC_CPM_PCIE_0] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_0 [get_bd_intf_pins dfx_decoupler_0/s_intf_0] [get_bd_intf_pins noc/HBM00_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_1 [get_bd_intf_pins dfx_decoupler_0/s_intf_1] [get_bd_intf_pins noc/HBM01_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_2 [get_bd_intf_pins dfx_decoupler_0/s_intf_2] [get_bd_intf_pins noc/HBM02_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_3 [get_bd_intf_pins dfx_decoupler_0/s_intf_3] [get_bd_intf_pins noc/HBM03_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_4 [get_bd_intf_pins dfx_decoupler_0/s_intf_4] [get_bd_intf_pins noc/HBM04_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_5 [get_bd_intf_pins dfx_decoupler_0/s_intf_5] [get_bd_intf_pins noc/HBM05_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_6 [get_bd_intf_pins dfx_decoupler_0/s_intf_6] [get_bd_intf_pins noc/HBM06_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_7 [get_bd_intf_pins dfx_decoupler_0/s_intf_7] [get_bd_intf_pins noc/HBM07_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_8 [get_bd_intf_pins dfx_decoupler_0/s_intf_8] [get_bd_intf_pins noc/HBM08_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_9 [get_bd_intf_pins dfx_decoupler_0/s_intf_9] [get_bd_intf_pins noc/HBM09_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_10 [get_bd_intf_pins dfx_decoupler_0/s_intf_10] [get_bd_intf_pins noc/HBM10_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_11 [get_bd_intf_pins dfx_decoupler_0/s_intf_11] [get_bd_intf_pins noc/HBM11_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_12 [get_bd_intf_pins dfx_decoupler_0/s_intf_12] [get_bd_intf_pins noc/HBM12_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_13 [get_bd_intf_pins dfx_decoupler_0/s_intf_13] [get_bd_intf_pins noc/HBM13_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_14 [get_bd_intf_pins dfx_decoupler_0/s_intf_14] [get_bd_intf_pins noc/HBM14_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_15 [get_bd_intf_pins dfx_decoupler_0/s_intf_15] [get_bd_intf_pins noc/HBM15_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_16 [get_bd_intf_pins dfx_decoupler_0/s_intf_16] [get_bd_intf_pins noc/HBM16_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_17 [get_bd_intf_pins dfx_decoupler_0/s_intf_17] [get_bd_intf_pins noc/HBM17_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_18 [get_bd_intf_pins dfx_decoupler_0/s_intf_18] [get_bd_intf_pins noc/HBM18_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_19 [get_bd_intf_pins dfx_decoupler_0/s_intf_19] [get_bd_intf_pins noc/HBM19_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_20 [get_bd_intf_pins dfx_decoupler_0/s_intf_20] [get_bd_intf_pins noc/HBM20_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_21 [get_bd_intf_pins dfx_decoupler_0/s_intf_21] [get_bd_intf_pins noc/HBM21_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_22 [get_bd_intf_pins dfx_decoupler_0/s_intf_22] [get_bd_intf_pins noc/HBM22_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_23 [get_bd_intf_pins dfx_decoupler_0/s_intf_23] [get_bd_intf_pins noc/HBM23_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_24 [get_bd_intf_pins dfx_decoupler_0/s_intf_24] [get_bd_intf_pins noc/HBM24_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_25 [get_bd_intf_pins dfx_decoupler_0/s_intf_25] [get_bd_intf_pins noc/HBM25_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_26 [get_bd_intf_pins dfx_decoupler_0/s_intf_26] [get_bd_intf_pins noc/HBM26_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_27 [get_bd_intf_pins dfx_decoupler_0/s_intf_27] [get_bd_intf_pins noc/HBM27_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_28 [get_bd_intf_pins dfx_decoupler_0/s_intf_28] [get_bd_intf_pins noc/HBM28_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_29 [get_bd_intf_pins dfx_decoupler_0/s_intf_29] [get_bd_intf_pins noc/HBM29_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_30 [get_bd_intf_pins dfx_decoupler_0/s_intf_30] [get_bd_intf_pins noc/HBM30_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_31 [get_bd_intf_pins dfx_decoupler_0/s_intf_31] [get_bd_intf_pins noc/HBM31_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_32 [get_bd_intf_pins dfx_decoupler_0/s_intf_32] [get_bd_intf_pins noc/HBM32_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_33 [get_bd_intf_pins dfx_decoupler_0/s_intf_33] [get_bd_intf_pins noc/HBM33_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_34 [get_bd_intf_pins dfx_decoupler_0/s_intf_34] [get_bd_intf_pins noc/HBM34_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_35 [get_bd_intf_pins dfx_decoupler_0/s_intf_35] [get_bd_intf_pins noc/HBM35_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_36 [get_bd_intf_pins dfx_decoupler_0/s_intf_36] [get_bd_intf_pins noc/HBM36_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_37 [get_bd_intf_pins dfx_decoupler_0/s_intf_37] [get_bd_intf_pins noc/HBM37_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_38 [get_bd_intf_pins dfx_decoupler_0/s_intf_38] [get_bd_intf_pins noc/HBM38_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_39 [get_bd_intf_pins dfx_decoupler_0/s_intf_39] [get_bd_intf_pins noc/HBM39_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_40 [get_bd_intf_pins dfx_decoupler_0/s_intf_40] [get_bd_intf_pins noc/HBM40_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_41 [get_bd_intf_pins dfx_decoupler_0/s_intf_41] [get_bd_intf_pins noc/HBM41_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_42 [get_bd_intf_pins dfx_decoupler_0/s_intf_42] [get_bd_intf_pins noc/HBM42_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_43 [get_bd_intf_pins dfx_decoupler_0/s_intf_43] [get_bd_intf_pins noc/HBM43_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_44 [get_bd_intf_pins dfx_decoupler_0/s_intf_44] [get_bd_intf_pins noc/HBM44_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_45 [get_bd_intf_pins dfx_decoupler_0/s_intf_45] [get_bd_intf_pins noc/HBM45_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_46 [get_bd_intf_pins dfx_decoupler_0/s_intf_46] [get_bd_intf_pins noc/HBM46_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_47 [get_bd_intf_pins dfx_decoupler_0/s_intf_47] [get_bd_intf_pins noc/HBM47_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_48 [get_bd_intf_pins dfx_decoupler_0/s_intf_48] [get_bd_intf_pins noc/HBM48_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_49 [get_bd_intf_pins dfx_decoupler_0/s_intf_49] [get_bd_intf_pins noc/HBM49_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_50 [get_bd_intf_pins dfx_decoupler_0/s_intf_50] [get_bd_intf_pins noc/HBM50_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_51 [get_bd_intf_pins dfx_decoupler_0/s_intf_51] [get_bd_intf_pins noc/HBM51_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_52 [get_bd_intf_pins dfx_decoupler_0/s_intf_52] [get_bd_intf_pins noc/HBM52_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_53 [get_bd_intf_pins dfx_decoupler_0/s_intf_53] [get_bd_intf_pins noc/HBM53_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_54 [get_bd_intf_pins dfx_decoupler_0/s_intf_54] [get_bd_intf_pins noc/HBM54_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_55 [get_bd_intf_pins dfx_decoupler_0/s_intf_55] [get_bd_intf_pins noc/HBM55_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_56 [get_bd_intf_pins dfx_decoupler_0/s_intf_56] [get_bd_intf_pins noc/HBM56_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_57 [get_bd_intf_pins dfx_decoupler_0/s_intf_57] [get_bd_intf_pins noc/HBM57_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_58 [get_bd_intf_pins dfx_decoupler_0/s_intf_58] [get_bd_intf_pins noc/HBM58_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_59 [get_bd_intf_pins dfx_decoupler_0/s_intf_59] [get_bd_intf_pins noc/HBM59_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_60 [get_bd_intf_pins dfx_decoupler_0/s_intf_60] [get_bd_intf_pins noc/HBM60_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_61 [get_bd_intf_pins dfx_decoupler_0/s_intf_61] [get_bd_intf_pins noc/HBM61_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_62 [get_bd_intf_pins dfx_decoupler_0/s_intf_62] [get_bd_intf_pins noc/HBM62_AXI] + connect_bd_intf_net -intf_net dfx_decoupler_0_s_intf_63 [get_bd_intf_pins dfx_decoupler_0/s_intf_63] [get_bd_intf_pins noc/HBM63_AXI] + connect_bd_intf_net -intf_net noc_M00_AXI [get_bd_intf_pins noc/M00_AXI] [get_bd_intf_pins aved/s_axi_pcie_mgmt_slr0] + connect_bd_intf_net -intf_net noc_M02_AXI [get_bd_intf_pins noc/M02_AXI] [get_bd_intf_pins aved/NOC_PMC_AXI_0] + + # Create port connections + connect_bd_net -net aclk0_1 [get_bd_pins aved/pl0_ref_clk] \ + [get_bd_pins noc/aclk0] \ + [get_bd_pins pl0_ref_clk] \ + [get_bd_pins clk_rst_shell/pl0_ref_clk] + connect_bd_net -net aclk1_1 [get_bd_pins aved/cpm_pcie_noc_axi1_clk] \ + [get_bd_pins noc/aclk1] + connect_bd_net -net aclk2_1 [get_bd_pins aved/pmc_axi_noc_axi0_clk] \ + [get_bd_pins noc/aclk2] + connect_bd_net -net aclk3_1 [get_bd_pins aved/lpd_axi_noc_clk] \ + [get_bd_pins noc/aclk3] + connect_bd_net -net aclk4_1 [get_bd_pins aved/cpm_pcie_noc_axi0_clk] \ + [get_bd_pins noc/aclk4] \ + [get_bd_pins axi_noc_1/aclk0] + connect_bd_net -net aclk6_1 [get_bd_pins aved/noc_pmc_axi_axi0_clk] \ + [get_bd_pins noc/aclk6] + connect_bd_net -net aresetn_1 [get_bd_pins aved/pl0_resetn] \ + [get_bd_pins clk_rst_shell/aresetn] + connect_bd_net -net aved_eos [get_bd_pins aved/eos] \ + [get_bd_pins util_vector_logic_0/Op1] + connect_bd_net -net aved_noc_cpm_pcie_axi0_clk [get_bd_pins aved/noc_cpm_pcie_axi0_clk] \ + [get_bd_pins axi_noc_1/aclk1] + connect_bd_net -net aved_pl3_ref_clk [get_bd_pins aved/pl3_ref_clk] \ + [get_bd_pins clk_wizard_0/clk_in1] \ + [get_bd_pins pl3_ref_clk] \ + [get_bd_pins clk_rst_shell/refclk] + connect_bd_net -net aved_pl3_resetn [get_bd_pins aved/pl3_resetn] \ + [get_bd_pins pl3_resetn] + connect_bd_net -net aved_resetn_pl_periph [get_bd_pins aved/resetn_pl_periph] \ + [get_bd_pins resetn_pl_periph] \ + [get_bd_pins proc_sys_reset_1/ext_reset_in] + connect_bd_net -net clk_rst_shell_clk_out1 [get_bd_pins clk_rst_shell/service_clk] \ + [get_bd_pins clk_out2] + connect_bd_net -net clk_rst_shell_clk_out2 [get_bd_pins clk_rst_shell/slash_clk] \ + [get_bd_pins clk_out3] + connect_bd_net -net clk_rst_shell_peripheral_aresetn [get_bd_pins clk_rst_shell/service_arstn] \ + [get_bd_pins peripheral_aresetn1] + connect_bd_net -net clk_rst_shell_peripheral_aresetn1 [get_bd_pins clk_rst_shell/slash_arstn] \ + [get_bd_pins peripheral_aresetn2] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_wizard_0/clk_out1] \ + [get_bd_pins clk_out1] \ + [get_bd_pins noc/aclk5] \ + [get_bd_pins proc_sys_reset_1/slowest_sync_clk] \ + [get_bd_pins dfx_decoupler_0/intf_0_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_1_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_2_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_3_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_4_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_5_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_6_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_7_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_8_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_9_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_10_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_11_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_12_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_13_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_14_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_15_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_16_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_17_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_18_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_19_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_20_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_21_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_22_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_23_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_24_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_25_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_26_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_27_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_28_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_29_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_30_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_31_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_32_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_33_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_34_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_35_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_36_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_37_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_38_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_39_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_40_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_41_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_42_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_43_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_44_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_45_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_46_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_47_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_48_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_49_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_50_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_51_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_52_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_53_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_54_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_55_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_56_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_57_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_58_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_59_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_60_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_61_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_62_aclk] \ + [get_bd_pins dfx_decoupler_0/intf_63_aclk] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] \ + [get_bd_pins dfx_decoupler_0/intf_0_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_1_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_2_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_3_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_4_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_5_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_6_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_7_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_8_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_9_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_10_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_11_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_12_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_13_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_14_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_15_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_16_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_17_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_18_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_19_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_20_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_21_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_22_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_23_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_24_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_25_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_26_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_27_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_28_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_29_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_30_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_31_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_32_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_33_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_34_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_35_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_36_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_37_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_38_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_39_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_40_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_41_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_42_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_43_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_44_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_45_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_46_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_47_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_48_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_49_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_50_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_51_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_52_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_53_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_54_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_55_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_56_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_57_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_58_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_59_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_60_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_61_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_62_arstn] \ + [get_bd_pins dfx_decoupler_0/intf_63_arstn] + connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] \ + [get_bd_pins dfx_decoupler_0/decouple] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + set_property -dict [list \ + SRC_RM_MAP./service_layer.service_layer {service_layer_inst_0} \ + SRC_RM_MAP./slash.slash_base {slash_base_inst_0} \ +] [get_bd_designs $design_name] + + + # Create interface ports + set CH0_DDR4_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_0 ] + + set sys_clk0_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $sys_clk0_0 + + set CH0_DDR4_0_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 CH0_DDR4_0_1 ] + + set sys_clk0_1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk0_1 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $sys_clk0_1 + + set hbm_ref_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $hbm_ref_clk_0 + + set hbm_ref_clk_1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 hbm_ref_clk_1 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $hbm_ref_clk_1 + + set gt_pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $gt_pcie_refclk + + set gt_pciea1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_pciea1 ] + + set smbus_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 smbus_0 ] + + set qsfp0_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_322mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp0_322mhz + + set qsfp2_322mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp2_322mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $qsfp2_322mhz + + set qsfp0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0_4x ] + + set qsfp2_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp2_4x ] + + set qsfp1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1_4x ] + + set qsfp3_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp3_4x ] + + + # Create ports + + # Create instance: static_region + create_hier_cell_static_region [current_bd_instance .] static_region + + # Create instance: slash, and set properties + set slash [ create_bd_cell -type container -reference slash_base slash ] + set_property -dict [list \ + CONFIG.ACTIVE_SIM_BD {slash_base.bd} \ + CONFIG.ACTIVE_SYNTH_BD {slash_base.bd} \ + CONFIG.ENABLE_DFX {false} \ + CONFIG.LIST_SIM_BD {slash_base.bd} \ + CONFIG.LIST_SYNTH_BD {slash_base.bd} \ + CONFIG.LOCK_PROPAGATE {false} \ + ] $slash + + + set_property SELECTED_SIM_MODEL rtl $slash + set_property APERTURES {{0x40_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_00] + set_property APERTURES {{0x40_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_01] + set_property APERTURES {{0x40_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_02] + set_property APERTURES {{0x40_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_03] + set_property APERTURES {{0x40_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_04] + set_property APERTURES {{0x40_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_05] + set_property APERTURES {{0x40_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_06] + set_property APERTURES {{0x40_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_07] + set_property APERTURES {{0x41_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_08] + set_property APERTURES {{0x41_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_09] + set_property APERTURES {{0x41_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_10] + set_property APERTURES {{0x41_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_11] + set_property APERTURES {{0x41_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_12] + set_property APERTURES {{0x41_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_13] + set_property APERTURES {{0x41_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_14] + set_property APERTURES {{0x41_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_15] + set_property APERTURES {{0x42_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_16] + set_property APERTURES {{0x42_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_17] + set_property APERTURES {{0x42_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_18] + set_property APERTURES {{0x42_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_19] + set_property APERTURES {{0x42_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_20] + set_property APERTURES {{0x42_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_21] + set_property APERTURES {{0x42_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_22] + set_property APERTURES {{0x42_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_23] + set_property APERTURES {{0x43_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_24] + set_property APERTURES {{0x43_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_25] + set_property APERTURES {{0x43_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_26] + set_property APERTURES {{0x43_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_27] + set_property APERTURES {{0x43_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_28] + set_property APERTURES {{0x43_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_29] + set_property APERTURES {{0x43_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_30] + set_property APERTURES {{0x43_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_31] + set_property APERTURES {{0x44_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_32] + set_property APERTURES {{0x44_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_33] + set_property APERTURES {{0x44_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_34] + set_property APERTURES {{0x44_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_35] + set_property APERTURES {{0x44_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_36] + set_property APERTURES {{0x44_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_37] + set_property APERTURES {{0x44_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_38] + set_property APERTURES {{0x44_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_39] + set_property APERTURES {{0x45_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_40] + set_property APERTURES {{0x45_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_41] + set_property APERTURES {{0x45_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_42] + set_property APERTURES {{0x45_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_43] + set_property APERTURES {{0x45_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_44] + set_property APERTURES {{0x45_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_45] + set_property APERTURES {{0x45_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_46] + set_property APERTURES {{0x45_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_47] + set_property APERTURES {{0x46_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_48] + set_property APERTURES {{0x46_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_49] + set_property APERTURES {{0x46_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_50] + set_property APERTURES {{0x46_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_51] + set_property APERTURES {{0x46_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_52] + set_property APERTURES {{0x46_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_53] + set_property APERTURES {{0x46_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_54] + set_property APERTURES {{0x46_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_55] + set_property APERTURES {{0x47_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_56] + set_property APERTURES {{0x47_0000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_57] + set_property APERTURES {{0x47_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_58] + set_property APERTURES {{0x47_4000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_59] + set_property APERTURES {{0x47_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_60] + set_property APERTURES {{0x47_8000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_61] + set_property APERTURES {{0x47_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_62] + set_property APERTURES {{0x47_C000_0000 1G}} [get_bd_intf_pins /slash/HBM_AXI_63] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_00] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_01] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_02] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_03] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_04] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_05] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_06] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/HBM_VNOC_INI_07] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M00_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M01_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M02_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_pins /slash/M03_INI] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /slash/QDMA_SLAVE_BRIDGE_0] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_00] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_01] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_02] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /slash/SL_VIRT_03] + set_property APERTURES {{0x202_0000_0000 128M}} [get_bd_intf_pins /slash/S_AXILITE_INI] + + # Create instance: service_layer, and set properties + set service_layer [ create_bd_cell -type container -reference service_layer service_layer ] + set_property -dict [list \ + CONFIG.ACTIVE_SIM_BD {service_layer.bd} \ + CONFIG.ACTIVE_SYNTH_BD {service_layer.bd} \ + CONFIG.ENABLE_DFX {false} \ + CONFIG.LIST_SIM_BD {service_layer.bd} \ + CONFIG.LIST_SYNTH_BD {service_layer.bd} \ + CONFIG.LOCK_PROPAGATE {false} \ + ] $service_layer + + + set_property SELECTED_SIM_MODEL rtl $service_layer + set_property APERTURES {{0xE000_0000 256M}} [get_bd_intf_pins /service_layer/M_QDMA_SLV_BRIDGE] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/M_VIRT_0] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/M_VIRT_1] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/M_VIRT_2] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/M_VIRT_3] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_0] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_1] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_2] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_3] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_4] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_5] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_6] + set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_pins /service_layer/SL2NOC_7] + set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_pins /service_layer/S_AXILITE_INI] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_QDMA_SLV_BRIDGE] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_00] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_01] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_02] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_pins /service_layer/S_VIRT_03] + + # Create interface connections + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_pins service_layer/S_AXILITE_INI] [get_bd_intf_pins static_region/M05_INI] + connect_bd_intf_net -intf_net S_AXILITE_INI_2 [get_bd_intf_pins slash/S_AXILITE_INI] [get_bd_intf_pins static_region/M04_INI] + connect_bd_intf_net -intf_net S_DCMAC_INIS0_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS0] [get_bd_intf_pins static_region/M00_INIS] + connect_bd_intf_net -intf_net S_DCMAC_INIS0_2 [get_bd_intf_pins slash/S_DCMAC_INIS0] [get_bd_intf_pins static_region/M00_INIS8] + connect_bd_intf_net -intf_net S_DCMAC_INIS1_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS1] [get_bd_intf_pins static_region/M00_INIS1] + connect_bd_intf_net -intf_net S_DCMAC_INIS1_2 [get_bd_intf_pins slash/S_DCMAC_INIS1] [get_bd_intf_pins static_region/M00_INIS9] + connect_bd_intf_net -intf_net S_DCMAC_INIS2_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS2] [get_bd_intf_pins static_region/M00_INIS2] + connect_bd_intf_net -intf_net S_DCMAC_INIS2_2 [get_bd_intf_pins slash/S_DCMAC_INIS2] [get_bd_intf_pins static_region/M00_INIS10] + connect_bd_intf_net -intf_net S_DCMAC_INIS3_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS3] [get_bd_intf_pins static_region/M00_INIS3] + connect_bd_intf_net -intf_net S_DCMAC_INIS3_2 [get_bd_intf_pins slash/S_DCMAC_INIS3] [get_bd_intf_pins static_region/M00_INIS11] + connect_bd_intf_net -intf_net S_DCMAC_INIS4_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS4] [get_bd_intf_pins static_region/M00_INIS4] + connect_bd_intf_net -intf_net S_DCMAC_INIS4_2 [get_bd_intf_pins slash/S_DCMAC_INIS4] [get_bd_intf_pins static_region/M00_INIS12] + connect_bd_intf_net -intf_net S_DCMAC_INIS5_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS5] [get_bd_intf_pins static_region/M00_INIS5] + connect_bd_intf_net -intf_net S_DCMAC_INIS5_2 [get_bd_intf_pins slash/S_DCMAC_INIS5] [get_bd_intf_pins static_region/M00_INIS13] + connect_bd_intf_net -intf_net S_DCMAC_INIS6_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS6] [get_bd_intf_pins static_region/M00_INIS6] + connect_bd_intf_net -intf_net S_DCMAC_INIS6_2 [get_bd_intf_pins slash/S_DCMAC_INIS6] [get_bd_intf_pins static_region/M00_INIS14] + connect_bd_intf_net -intf_net S_DCMAC_INIS7_1 [get_bd_intf_pins service_layer/S_DCMAC_INIS7] [get_bd_intf_pins static_region/M00_INIS7] + connect_bd_intf_net -intf_net S_DCMAC_INIS7_2 [get_bd_intf_pins slash/S_DCMAC_INIS7] [get_bd_intf_pins static_region/M00_INIS15] + connect_bd_intf_net -intf_net S_QDMA_SLV_BRIDGE_1 [get_bd_intf_pins service_layer/S_QDMA_SLV_BRIDGE] [get_bd_intf_pins static_region/M00_INI4] + connect_bd_intf_net -intf_net S_VIRT_00_1 [get_bd_intf_pins service_layer/S_VIRT_00] [get_bd_intf_pins static_region/M00_INI] + connect_bd_intf_net -intf_net S_VIRT_01_1 [get_bd_intf_pins service_layer/S_VIRT_01] [get_bd_intf_pins static_region/M00_INI1] + connect_bd_intf_net -intf_net S_VIRT_02_1 [get_bd_intf_pins service_layer/S_VIRT_02] [get_bd_intf_pins static_region/M00_INI2] + connect_bd_intf_net -intf_net S_VIRT_03_1 [get_bd_intf_pins service_layer/S_VIRT_03] [get_bd_intf_pins static_region/M00_INI3] + connect_bd_intf_net -intf_net gt_pcie_refclk_1 [get_bd_intf_ports gt_pcie_refclk] [get_bd_intf_pins static_region/gt_pcie_refclk] + connect_bd_intf_net -intf_net hbm_ref_clk_0_1 [get_bd_intf_ports hbm_ref_clk_0] [get_bd_intf_pins static_region/hbm_ref_clk_0] + connect_bd_intf_net -intf_net hbm_ref_clk_1_1 [get_bd_intf_ports hbm_ref_clk_1] [get_bd_intf_pins static_region/hbm_ref_clk_1] + connect_bd_intf_net -intf_net qsfp0_322mhz_0_1 [get_bd_intf_ports qsfp0_322mhz] [get_bd_intf_pins service_layer/qsfp0_322mhz] + connect_bd_intf_net -intf_net qsfp2_322mhz_0_1 [get_bd_intf_ports qsfp2_322mhz] [get_bd_intf_pins service_layer/qsfp2_322mhz] + connect_bd_intf_net -intf_net service_layer_M00_INI [get_bd_intf_pins service_layer/SL2NOC_0] [get_bd_intf_pins static_region/S12_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI1 [get_bd_intf_pins service_layer/SL2NOC_1] [get_bd_intf_pins static_region/S13_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI2 [get_bd_intf_pins service_layer/SL2NOC_2] [get_bd_intf_pins static_region/S14_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI3 [get_bd_intf_pins service_layer/SL2NOC_3] [get_bd_intf_pins static_region/S15_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI4 [get_bd_intf_pins service_layer/SL2NOC_4] [get_bd_intf_pins static_region/S16_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI5 [get_bd_intf_pins service_layer/SL2NOC_5] [get_bd_intf_pins static_region/S17_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI6 [get_bd_intf_pins service_layer/SL2NOC_6] [get_bd_intf_pins static_region/S18_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI7 [get_bd_intf_pins service_layer/SL2NOC_7] [get_bd_intf_pins static_region/S19_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI12 [get_bd_intf_pins service_layer/M_VIRT_0] [get_bd_intf_pins static_region/S20_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI13 [get_bd_intf_pins service_layer/M_VIRT_1] [get_bd_intf_pins static_region/S21_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI14 [get_bd_intf_pins service_layer/M_VIRT_2] [get_bd_intf_pins static_region/S22_INI] + connect_bd_intf_net -intf_net service_layer_M00_INI15 [get_bd_intf_pins service_layer/M_VIRT_3] [get_bd_intf_pins static_region/S23_INI] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS0 [get_bd_intf_pins service_layer/M_DCMAC_INIS0] [get_bd_intf_pins static_region/S00_INIS8] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS1 [get_bd_intf_pins service_layer/M_DCMAC_INIS1] [get_bd_intf_pins static_region/S00_INIS9] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS2 [get_bd_intf_pins service_layer/M_DCMAC_INIS2] [get_bd_intf_pins static_region/S00_INIS10] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS3 [get_bd_intf_pins service_layer/M_DCMAC_INIS3] [get_bd_intf_pins static_region/S00_INIS11] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS4 [get_bd_intf_pins service_layer/M_DCMAC_INIS4] [get_bd_intf_pins static_region/S00_INIS12] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS5 [get_bd_intf_pins service_layer/M_DCMAC_INIS5] [get_bd_intf_pins static_region/S00_INIS13] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS6 [get_bd_intf_pins service_layer/M_DCMAC_INIS6] [get_bd_intf_pins static_region/S00_INIS14] + connect_bd_intf_net -intf_net service_layer_M_DCMAC_INIS7 [get_bd_intf_pins service_layer/M_DCMAC_INIS7] [get_bd_intf_pins static_region/S00_INIS15] + connect_bd_intf_net -intf_net service_layer_M_QDMA_SLV_BRIDGE [get_bd_intf_pins service_layer/M_QDMA_SLV_BRIDGE] [get_bd_intf_pins static_region/S00_INI6] + connect_bd_intf_net -intf_net service_layer_qsfp0_4x [get_bd_intf_ports qsfp0_4x] [get_bd_intf_pins service_layer/qsfp0_4x] + connect_bd_intf_net -intf_net service_layer_qsfp1_4x [get_bd_intf_ports qsfp1_4x] [get_bd_intf_pins service_layer/qsfp1_4x] + connect_bd_intf_net -intf_net service_layer_qsfp2_4x [get_bd_intf_ports qsfp2_4x] [get_bd_intf_pins service_layer/qsfp2_4x] + connect_bd_intf_net -intf_net service_layer_qsfp3_4x [get_bd_intf_ports qsfp3_4x] [get_bd_intf_pins service_layer/qsfp3_4x] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_00 [get_bd_intf_pins slash/HBM_VNOC_INI_00] [get_bd_intf_pins static_region/S04_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_01 [get_bd_intf_pins slash/HBM_VNOC_INI_01] [get_bd_intf_pins static_region/S05_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_02 [get_bd_intf_pins slash/HBM_VNOC_INI_02] [get_bd_intf_pins static_region/S06_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_03 [get_bd_intf_pins slash/HBM_VNOC_INI_03] [get_bd_intf_pins static_region/S07_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_04 [get_bd_intf_pins slash/HBM_VNOC_INI_04] [get_bd_intf_pins static_region/S08_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_05 [get_bd_intf_pins slash/HBM_VNOC_INI_05] [get_bd_intf_pins static_region/S09_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_06 [get_bd_intf_pins slash/HBM_VNOC_INI_06] [get_bd_intf_pins static_region/S10_INI] + connect_bd_intf_net -intf_net slash_HBM_VNOC_INI_07 [get_bd_intf_pins slash/HBM_VNOC_INI_07] [get_bd_intf_pins static_region/S11_INI] + connect_bd_intf_net -intf_net slash_M00_INI [get_bd_intf_pins slash/M00_INI] [get_bd_intf_pins static_region/S00_INI] + connect_bd_intf_net -intf_net slash_M01_INI [get_bd_intf_pins slash/M01_INI] [get_bd_intf_pins static_region/S01_INI] + connect_bd_intf_net -intf_net slash_M02_INI [get_bd_intf_pins slash/M02_INI] [get_bd_intf_pins static_region/S02_INI] + connect_bd_intf_net -intf_net slash_M03_INI [get_bd_intf_pins slash/M03_INI] [get_bd_intf_pins static_region/S03_INI] + connect_bd_intf_net -intf_net slash_M_AXI0 [get_bd_intf_pins slash/HBM_AXI_00] [get_bd_intf_pins static_region/rp_intf_0] + connect_bd_intf_net -intf_net slash_M_AXI1 [get_bd_intf_pins slash/HBM_AXI_01] [get_bd_intf_pins static_region/rp_intf_1] + connect_bd_intf_net -intf_net slash_M_AXI2 [get_bd_intf_pins slash/HBM_AXI_02] [get_bd_intf_pins static_region/rp_intf_2] + connect_bd_intf_net -intf_net slash_M_AXI3 [get_bd_intf_pins slash/HBM_AXI_03] [get_bd_intf_pins static_region/rp_intf_3] + connect_bd_intf_net -intf_net slash_M_AXI4 [get_bd_intf_pins slash/HBM_AXI_04] [get_bd_intf_pins static_region/rp_intf_4] + connect_bd_intf_net -intf_net slash_M_AXI5 [get_bd_intf_pins slash/HBM_AXI_05] [get_bd_intf_pins static_region/rp_intf_5] + connect_bd_intf_net -intf_net slash_M_AXI6 [get_bd_intf_pins slash/HBM_AXI_06] [get_bd_intf_pins static_region/rp_intf_6] + connect_bd_intf_net -intf_net slash_M_AXI7 [get_bd_intf_pins slash/HBM_AXI_07] [get_bd_intf_pins static_region/rp_intf_7] + connect_bd_intf_net -intf_net slash_M_AXI8 [get_bd_intf_pins slash/HBM_AXI_08] [get_bd_intf_pins static_region/rp_intf_8] + connect_bd_intf_net -intf_net slash_M_AXI9 [get_bd_intf_pins slash/HBM_AXI_09] [get_bd_intf_pins static_region/rp_intf_9] + connect_bd_intf_net -intf_net slash_M_AXI10 [get_bd_intf_pins slash/HBM_AXI_10] [get_bd_intf_pins static_region/rp_intf_10] + connect_bd_intf_net -intf_net slash_M_AXI11 [get_bd_intf_pins slash/HBM_AXI_11] [get_bd_intf_pins static_region/rp_intf_11] + connect_bd_intf_net -intf_net slash_M_AXI12 [get_bd_intf_pins slash/HBM_AXI_12] [get_bd_intf_pins static_region/rp_intf_12] + connect_bd_intf_net -intf_net slash_M_AXI13 [get_bd_intf_pins slash/HBM_AXI_13] [get_bd_intf_pins static_region/rp_intf_13] + connect_bd_intf_net -intf_net slash_M_AXI14 [get_bd_intf_pins slash/HBM_AXI_14] [get_bd_intf_pins static_region/rp_intf_14] + connect_bd_intf_net -intf_net slash_M_AXI15 [get_bd_intf_pins slash/HBM_AXI_15] [get_bd_intf_pins static_region/rp_intf_15] + connect_bd_intf_net -intf_net slash_M_AXI16 [get_bd_intf_pins slash/HBM_AXI_16] [get_bd_intf_pins static_region/rp_intf_16] + connect_bd_intf_net -intf_net slash_M_AXI17 [get_bd_intf_pins slash/HBM_AXI_17] [get_bd_intf_pins static_region/rp_intf_17] + connect_bd_intf_net -intf_net slash_M_AXI18 [get_bd_intf_pins slash/HBM_AXI_18] [get_bd_intf_pins static_region/rp_intf_18] + connect_bd_intf_net -intf_net slash_M_AXI19 [get_bd_intf_pins slash/HBM_AXI_19] [get_bd_intf_pins static_region/rp_intf_19] + connect_bd_intf_net -intf_net slash_M_AXI20 [get_bd_intf_pins slash/HBM_AXI_20] [get_bd_intf_pins static_region/rp_intf_20] + connect_bd_intf_net -intf_net slash_M_AXI21 [get_bd_intf_pins slash/HBM_AXI_21] [get_bd_intf_pins static_region/rp_intf_21] + connect_bd_intf_net -intf_net slash_M_AXI22 [get_bd_intf_pins slash/HBM_AXI_22] [get_bd_intf_pins static_region/rp_intf_22] + connect_bd_intf_net -intf_net slash_M_AXI23 [get_bd_intf_pins slash/HBM_AXI_23] [get_bd_intf_pins static_region/rp_intf_23] + connect_bd_intf_net -intf_net slash_M_AXI24 [get_bd_intf_pins slash/HBM_AXI_24] [get_bd_intf_pins static_region/rp_intf_24] + connect_bd_intf_net -intf_net slash_M_AXI25 [get_bd_intf_pins slash/HBM_AXI_25] [get_bd_intf_pins static_region/rp_intf_25] + connect_bd_intf_net -intf_net slash_M_AXI26 [get_bd_intf_pins slash/HBM_AXI_26] [get_bd_intf_pins static_region/rp_intf_26] + connect_bd_intf_net -intf_net slash_M_AXI27 [get_bd_intf_pins slash/HBM_AXI_27] [get_bd_intf_pins static_region/rp_intf_27] + connect_bd_intf_net -intf_net slash_M_AXI28 [get_bd_intf_pins slash/HBM_AXI_28] [get_bd_intf_pins static_region/rp_intf_28] + connect_bd_intf_net -intf_net slash_M_AXI29 [get_bd_intf_pins slash/HBM_AXI_29] [get_bd_intf_pins static_region/rp_intf_29] + connect_bd_intf_net -intf_net slash_M_AXI30 [get_bd_intf_pins slash/HBM_AXI_30] [get_bd_intf_pins static_region/rp_intf_30] + connect_bd_intf_net -intf_net slash_M_AXI31 [get_bd_intf_pins slash/HBM_AXI_31] [get_bd_intf_pins static_region/rp_intf_31] + connect_bd_intf_net -intf_net slash_M_AXI32 [get_bd_intf_pins slash/HBM_AXI_32] [get_bd_intf_pins static_region/rp_intf_32] + connect_bd_intf_net -intf_net slash_M_AXI33 [get_bd_intf_pins slash/HBM_AXI_33] [get_bd_intf_pins static_region/rp_intf_33] + connect_bd_intf_net -intf_net slash_M_AXI34 [get_bd_intf_pins slash/HBM_AXI_34] [get_bd_intf_pins static_region/rp_intf_34] + connect_bd_intf_net -intf_net slash_M_AXI35 [get_bd_intf_pins slash/HBM_AXI_35] [get_bd_intf_pins static_region/rp_intf_35] + connect_bd_intf_net -intf_net slash_M_AXI36 [get_bd_intf_pins slash/HBM_AXI_36] [get_bd_intf_pins static_region/rp_intf_36] + connect_bd_intf_net -intf_net slash_M_AXI37 [get_bd_intf_pins slash/HBM_AXI_37] [get_bd_intf_pins static_region/rp_intf_37] + connect_bd_intf_net -intf_net slash_M_AXI38 [get_bd_intf_pins slash/HBM_AXI_38] [get_bd_intf_pins static_region/rp_intf_38] + connect_bd_intf_net -intf_net slash_M_AXI39 [get_bd_intf_pins slash/HBM_AXI_39] [get_bd_intf_pins static_region/rp_intf_39] + connect_bd_intf_net -intf_net slash_M_AXI40 [get_bd_intf_pins slash/HBM_AXI_40] [get_bd_intf_pins static_region/rp_intf_40] + connect_bd_intf_net -intf_net slash_M_AXI41 [get_bd_intf_pins slash/HBM_AXI_41] [get_bd_intf_pins static_region/rp_intf_41] + connect_bd_intf_net -intf_net slash_M_AXI42 [get_bd_intf_pins slash/HBM_AXI_42] [get_bd_intf_pins static_region/rp_intf_42] + connect_bd_intf_net -intf_net slash_M_AXI43 [get_bd_intf_pins slash/HBM_AXI_43] [get_bd_intf_pins static_region/rp_intf_43] + connect_bd_intf_net -intf_net slash_M_AXI44 [get_bd_intf_pins slash/HBM_AXI_44] [get_bd_intf_pins static_region/rp_intf_44] + connect_bd_intf_net -intf_net slash_M_AXI45 [get_bd_intf_pins slash/HBM_AXI_45] [get_bd_intf_pins static_region/rp_intf_45] + connect_bd_intf_net -intf_net slash_M_AXI46 [get_bd_intf_pins slash/HBM_AXI_46] [get_bd_intf_pins static_region/rp_intf_46] + connect_bd_intf_net -intf_net slash_M_AXI47 [get_bd_intf_pins slash/HBM_AXI_47] [get_bd_intf_pins static_region/rp_intf_47] + connect_bd_intf_net -intf_net slash_M_AXI48 [get_bd_intf_pins slash/HBM_AXI_48] [get_bd_intf_pins static_region/rp_intf_48] + connect_bd_intf_net -intf_net slash_M_AXI49 [get_bd_intf_pins slash/HBM_AXI_49] [get_bd_intf_pins static_region/rp_intf_49] + connect_bd_intf_net -intf_net slash_M_AXI50 [get_bd_intf_pins slash/HBM_AXI_50] [get_bd_intf_pins static_region/rp_intf_50] + connect_bd_intf_net -intf_net slash_M_AXI51 [get_bd_intf_pins slash/HBM_AXI_51] [get_bd_intf_pins static_region/rp_intf_51] + connect_bd_intf_net -intf_net slash_M_AXI52 [get_bd_intf_pins slash/HBM_AXI_52] [get_bd_intf_pins static_region/rp_intf_52] + connect_bd_intf_net -intf_net slash_M_AXI53 [get_bd_intf_pins slash/HBM_AXI_53] [get_bd_intf_pins static_region/rp_intf_53] + connect_bd_intf_net -intf_net slash_M_AXI54 [get_bd_intf_pins slash/HBM_AXI_54] [get_bd_intf_pins static_region/rp_intf_54] + connect_bd_intf_net -intf_net slash_M_AXI55 [get_bd_intf_pins slash/HBM_AXI_55] [get_bd_intf_pins static_region/rp_intf_55] + connect_bd_intf_net -intf_net slash_M_AXI56 [get_bd_intf_pins slash/HBM_AXI_56] [get_bd_intf_pins static_region/rp_intf_56] + connect_bd_intf_net -intf_net slash_M_AXI57 [get_bd_intf_pins slash/HBM_AXI_57] [get_bd_intf_pins static_region/rp_intf_57] + connect_bd_intf_net -intf_net slash_M_AXI58 [get_bd_intf_pins slash/HBM_AXI_58] [get_bd_intf_pins static_region/rp_intf_58] + connect_bd_intf_net -intf_net slash_M_AXI59 [get_bd_intf_pins slash/HBM_AXI_59] [get_bd_intf_pins static_region/rp_intf_59] + connect_bd_intf_net -intf_net slash_M_AXI60 [get_bd_intf_pins slash/HBM_AXI_60] [get_bd_intf_pins static_region/rp_intf_60] + connect_bd_intf_net -intf_net slash_M_AXI61 [get_bd_intf_pins slash/HBM_AXI_61] [get_bd_intf_pins static_region/rp_intf_61] + connect_bd_intf_net -intf_net slash_M_AXI62 [get_bd_intf_pins slash/HBM_AXI_62] [get_bd_intf_pins static_region/rp_intf_62] + connect_bd_intf_net -intf_net slash_M_AXI63 [get_bd_intf_pins slash/HBM_AXI_63] [get_bd_intf_pins static_region/rp_intf_63] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS0 [get_bd_intf_pins slash/M_DCMAC_INIS0] [get_bd_intf_pins static_region/S00_INIS] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS1 [get_bd_intf_pins slash/M_DCMAC_INIS1] [get_bd_intf_pins static_region/S00_INIS1] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS2 [get_bd_intf_pins slash/M_DCMAC_INIS2] [get_bd_intf_pins static_region/S00_INIS2] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS3 [get_bd_intf_pins slash/M_DCMAC_INIS3] [get_bd_intf_pins static_region/S00_INIS3] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS4 [get_bd_intf_pins slash/M_DCMAC_INIS4] [get_bd_intf_pins static_region/S00_INIS4] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS5 [get_bd_intf_pins slash/M_DCMAC_INIS5] [get_bd_intf_pins static_region/S00_INIS5] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS6 [get_bd_intf_pins slash/M_DCMAC_INIS6] [get_bd_intf_pins static_region/S00_INIS6] + connect_bd_intf_net -intf_net slash_M_DCMAC_INIS7 [get_bd_intf_pins slash/M_DCMAC_INIS7] [get_bd_intf_pins static_region/S00_INIS7] + connect_bd_intf_net -intf_net slash_QDMA_SLAVE_BRIDGE_0 [get_bd_intf_pins slash/QDMA_SLAVE_BRIDGE_0] [get_bd_intf_pins static_region/S00_INI5] + connect_bd_intf_net -intf_net slash_SL_VIRT_00 [get_bd_intf_pins slash/SL_VIRT_00] [get_bd_intf_pins static_region/S00_INI1] + connect_bd_intf_net -intf_net slash_SL_VIRT_01 [get_bd_intf_pins slash/SL_VIRT_01] [get_bd_intf_pins static_region/S00_INI2] + connect_bd_intf_net -intf_net slash_SL_VIRT_02 [get_bd_intf_pins slash/SL_VIRT_02] [get_bd_intf_pins static_region/S00_INI3] + connect_bd_intf_net -intf_net slash_SL_VIRT_03 [get_bd_intf_pins slash/SL_VIRT_03] [get_bd_intf_pins static_region/S00_INI4] + connect_bd_intf_net -intf_net static_region_CH0_DDR4_0_0 [get_bd_intf_ports CH0_DDR4_0_0] [get_bd_intf_pins static_region/CH0_DDR4_0_0] + connect_bd_intf_net -intf_net static_region_CH0_DDR4_0_1 [get_bd_intf_ports CH0_DDR4_0_1] [get_bd_intf_pins static_region/CH0_DDR4_0_1] + connect_bd_intf_net -intf_net static_region_gt_pciea1 [get_bd_intf_ports gt_pciea1] [get_bd_intf_pins static_region/gt_pciea1] + connect_bd_intf_net -intf_net static_region_smbus_0 [get_bd_intf_ports smbus_0] [get_bd_intf_pins static_region/smbus_0] + connect_bd_intf_net -intf_net sys_clk0_0_1 [get_bd_intf_ports sys_clk0_0] [get_bd_intf_pins static_region/sys_clk0_0] + connect_bd_intf_net -intf_net sys_clk0_1_1 [get_bd_intf_ports sys_clk0_1] [get_bd_intf_pins static_region/sys_clk0_1] + + # Create port connections + connect_bd_net -net arstn_1 [get_bd_pins static_region/peripheral_aresetn1] \ + [get_bd_pins service_layer/arstn] + connect_bd_net -net arstn_2 [get_bd_pins static_region/peripheral_aresetn2] \ + [get_bd_pins slash/arstn] + connect_bd_net -net aved_pl0_ref_clk -boundary_type upper [get_bd_pins static_region/pl0_ref_clk] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins static_region/clk_out1] \ + [get_bd_pins slash/static_region_clk] + connect_bd_net -net service_clk_1 [get_bd_pins static_region/clk_out2] \ + [get_bd_pins service_layer/service_clk] + connect_bd_net -net static_region_clk_1 -boundary_type upper [get_bd_pins static_region/pl3_ref_clk] + connect_bd_net -net user_clk_1 [get_bd_pins static_region/clk_out3] \ + [get_bd_pins slash/user_clk] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM00_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM01_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_10/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM10_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_11/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM11_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_12/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM12_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_13/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM13_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_14/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM14_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_15/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM15_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_16/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM16_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_17/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM17_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_18/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM18_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_19/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM19_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM02_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_20/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM20_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_21/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM21_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_22/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM22_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_23/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM23_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_24/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM24_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_25/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM25_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_26/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM26_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_27/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM27_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_28/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM28_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_29/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM29_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM03_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_30/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM30_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_31/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM31_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_32/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM32_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_33/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM33_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_34/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM34_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_35/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM35_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_36/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM36_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_37/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM37_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_38/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM38_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_39/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM39_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM04_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_40/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM40_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_41/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM41_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_42/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM42_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_43/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM43_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_44/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM44_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_45/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM45_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_46/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM46_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_47/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM47_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_48/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM48_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_49/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM49_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_5/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM05_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_50/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM50_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_51/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM51_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_52/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM52_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_53/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM53_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_54/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM54_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_55/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM55_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_56/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM56_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_57/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM57_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_58/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM58_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_59/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM59_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_6/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM06_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_60/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM60_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_61/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM61_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_62/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM62_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_63/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM63_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S04_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S05_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S06_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S07_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_68/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S08_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_69/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S09_INI/HBM9_PC1] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_7/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM07_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_70/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S10_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_71/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S11_INI/HBM9_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_8/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM08_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces slash/hbm_bandwidth_9/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_cips/HBM09_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_0/Data_m_axi_gmem0] [get_bd_addr_segs service_layer/axi4_full_passthrough_0/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_1/Data_m_axi_gmem0] [get_bd_addr_segs service_layer/axi4_full_passthrough_1/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_2/Data_m_axi_gmem0] [get_bd_addr_segs service_layer/axi4_full_passthrough_2/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_3/Data_m_axi_gmem0] [get_bd_addr_segs service_layer/axi4_full_passthrough_3/s_axi/reg0] -force + assign_bd_address -offset 0x020800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces slash/traffic_virt_4/Data_m_axi_gmem0] [get_bd_addr_segs service_layer/axi4_full_passthrough_4/s_axi/reg0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_0/m_axi] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -with_name SEG_M_VIRT_1_Reg -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_1/m_axi] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -with_name SEG_M_VIRT_2_Reg -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_2/m_axi] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -with_name SEG_M_VIRT_3_Reg -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_3/m_axi] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_4/m_axi] [get_bd_addr_segs static_region/aved/cips/NOC_CPM_PCIE_0/pspmc_0_psv_noc_pcie_0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_0/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_1/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_2/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_3/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_4/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_5/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_6/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces service_layer/eth_7/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x020302040400 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040400 -range 0x00000100 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040000 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020300160000 -range 0x00000100 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040200 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040200 -range 0x00000100 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040600 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040600 -range 0x00000100 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_cips/S00_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + assign_bd_address -offset 0x000101220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot] -force + assign_bd_address -offset 0x000102100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot_stream] -force + assign_bd_address -offset 0x020400010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/clk_rst_shell/clk_wizard_service/s_axi_lite/Reg] -force + assign_bd_address -offset 0x020400000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/clk_rst_shell/clk_wizard_slash/s_axi_lite/Reg] -force + assign_bd_address -offset 0x020302000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + assign_bd_address -offset 0x020303000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + assign_bd_address -offset 0x020200480000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200490000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/ddr_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/eth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/base_logic/gcq_m2r/S00_AXI/S00_AXI_Reg] -force + assign_bd_address -offset 0x020200000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_10/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_11/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_12/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_13/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_14/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_15/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_16/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_17/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_18/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_19/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_20/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_21/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_22/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200170000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_23/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200180000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_24/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_25/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_26/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_27/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_28/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_29/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_30/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_31/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_32/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_33/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_34/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_35/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_36/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_37/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_38/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200270000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_39/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200280000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_40/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200290000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_41/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_42/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_43/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_44/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_45/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_46/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_47/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_48/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_49/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_50/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200330000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_51/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200340000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_52/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200350000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_53/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_54/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_55/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_56/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_57/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_58/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_59/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_60/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_61/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_62/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_63/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200410000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200420000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200430000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_68/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_69/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200460000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_70/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200470000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_71/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_8/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/hbm_bandwidth_9/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/base_logic/hw_discovery/s_axi_ctrl_pf0/reg0] -force + assign_bd_address -offset 0x020101040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/clock_reset/pcie_mgmt_pdi_reset/pcie_mgmt_pdi_reset_gpio/S_AXI/Reg] -force + assign_bd_address -offset 0x0202004C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300090000 -range 0x00010000 -with_name SEG_traffic_producer_1_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000A0000 -range 0x00010000 -with_name SEG_traffic_producer_2_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000B0000 -range 0x00010000 -with_name SEG_traffic_producer_3_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200510000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000D0000 -range 0x00010000 -with_name SEG_traffic_producer_5_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200530000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000E0000 -range 0x00010000 -with_name SEG_traffic_producer_6_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200520000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000F0000 -range 0x00010000 -with_name SEG_traffic_producer_7_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs service_layer/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200540000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200550000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200560000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200570000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200580000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs slash/traffic_virt_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/base_logic/uuid_rom/S_AXI/reg0] -force + assign_bd_address -offset 0x020303040400 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040400 -range 0x00000100 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020300160000 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040000 -range 0x00000100 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040200 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040200 -range 0x00000100 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040600 -range 0x00000100 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040600 -range 0x00000100 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x004000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM0_PC0] -force + assign_bd_address -offset 0x004040000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM0_PC1] -force + assign_bd_address -offset 0x004500000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM10_PC0] -force + assign_bd_address -offset 0x004540000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM10_PC1] -force + assign_bd_address -offset 0x004580000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM11_PC0] -force + assign_bd_address -offset 0x0045C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM11_PC1] -force + assign_bd_address -offset 0x004600000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM12_PC0] -force + assign_bd_address -offset 0x004640000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM12_PC1] -force + assign_bd_address -offset 0x004680000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM13_PC0] -force + assign_bd_address -offset 0x0046C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM13_PC1] -force + assign_bd_address -offset 0x004700000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM14_PC0] -force + assign_bd_address -offset 0x004740000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM14_PC1] -force + assign_bd_address -offset 0x004780000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM15_PC0] -force + assign_bd_address -offset 0x0047C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM15_PC1] -force + assign_bd_address -offset 0x004080000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM1_PC0] -force + assign_bd_address -offset 0x0040C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM1_PC1] -force + assign_bd_address -offset 0x004100000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM2_PC0] -force + assign_bd_address -offset 0x004140000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM2_PC1] -force + assign_bd_address -offset 0x004180000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM3_PC0] -force + assign_bd_address -offset 0x0041C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM3_PC1] -force + assign_bd_address -offset 0x004200000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM4_PC0] -force + assign_bd_address -offset 0x004240000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM4_PC1] -force + assign_bd_address -offset 0x004280000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM5_PC0] -force + assign_bd_address -offset 0x0042C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM5_PC1] -force + assign_bd_address -offset 0x004300000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM6_PC0] -force + assign_bd_address -offset 0x004340000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM6_PC1] -force + assign_bd_address -offset 0x004380000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM7_PC0] -force + assign_bd_address -offset 0x0043C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM7_PC1] -force + assign_bd_address -offset 0x004400000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM8_PC0] -force + assign_bd_address -offset 0x004440000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM8_PC1] -force + assign_bd_address -offset 0x004480000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM9_PC0] -force + assign_bd_address -offset 0x0044C0000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_cips/S01_AXI/HBM9_PC1] -force + assign_bd_address -offset 0x050080000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S01_INI/C1_DDR_CH2] -force + assign_bd_address -offset 0x000101220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot] -force + assign_bd_address -offset 0x000102100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_slave_boot_stream] -force + assign_bd_address -offset 0x020400010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/clk_rst_shell/clk_wizard_service/s_axi_lite/Reg] -force + assign_bd_address -offset 0x020400000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/clk_rst_shell/clk_wizard_slash/s_axi_lite/Reg] -force + assign_bd_address -offset 0x020302000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + assign_bd_address -offset 0x020303000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + assign_bd_address -offset 0x020200480000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200490000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/ddr_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/eth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/base_logic/gcq_m2r/S00_AXI/S00_AXI_Reg] -force + assign_bd_address -offset 0x020200000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_10/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_11/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_12/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_13/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_14/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202000F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_15/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_16/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_17/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_18/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_19/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_20/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200150000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_21/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200160000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_22/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200170000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_23/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200180000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_24/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200190000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_25/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_26/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_27/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_28/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_29/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_30/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202001F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_31/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_32/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_33/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_34/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_35/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_36/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_37/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_38/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200270000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_39/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200280000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_40/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200290000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_41/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_42/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_43/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_44/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_45/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_46/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202002F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_47/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_48/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_49/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_50/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200330000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_51/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200340000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_52/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200350000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_53/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_54/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_55/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_56/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_57/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_58/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_59/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_60/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_61/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_62/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202003F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_63/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_64/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200410000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_65/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200420000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_66/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200430000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_67/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_68/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_69/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200460000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_70/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200470000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_71/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_8/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/hbm_bandwidth_9/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/base_logic/hw_discovery/s_axi_ctrl_pf0/reg0] -force + assign_bd_address -offset 0x020101040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/clock_reset/pcie_mgmt_pdi_reset/pcie_mgmt_pdi_reset_gpio/S_AXI/Reg] -force + assign_bd_address -offset 0x0202004C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020300090000 -range 0x00010000 -with_name SEG_traffic_producer_1_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000A0000 -range 0x00010000 -with_name SEG_traffic_producer_2_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000B0000 -range 0x00010000 -with_name SEG_traffic_producer_3_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x0202004F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200510000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000D0000 -range 0x00010000 -with_name SEG_traffic_producer_5_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_5/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200530000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000E0000 -range 0x00010000 -with_name SEG_traffic_producer_6_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_6/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200520000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x0203000F0000 -range 0x00010000 -with_name SEG_traffic_producer_7_Reg_1 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs service_layer/traffic_producer_7/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200540000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_0/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200550000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_1/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200560000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_2/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200570000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_3/s_axi_control/Reg] -force + assign_bd_address -offset 0x020200580000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs slash/traffic_virt_4/s_axi_control/Reg] -force + assign_bd_address -offset 0x020101001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/base_logic/uuid_rom/S_AXI/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/LPD_AXI_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x80044000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/M_AXI_LPD] [get_bd_addr_segs static_region/aved/base_logic/axi_smbus_rpu/S_AXI/Reg] -force + assign_bd_address -offset 0x80010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/M_AXI_LPD] [get_bd_addr_segs static_region/aved/base_logic/gcq_m2r/S01_AXI/S01_AXI_Reg] -force + assign_bd_address -offset 0x050080000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/PMC_NOC_AXI_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/PMC_NOC_AXI_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] -force + assign_bd_address -offset 0x060000000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/PMC_NOC_AXI_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_1/S00_INI/C0_DDR_CH2] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x000600000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_4/m_axi] [get_bd_addr_segs static_region/aved/cips/NOC_CPM_PCIE_0/pspmc_0_psv_noc_pcie_1] + exclude_bd_addr_seg -offset 0x008000000000 -range 0x004000000000 -target_address_space [get_bd_addr_spaces service_layer/axi4_full_passthrough_4/m_axi] [get_bd_addr_segs static_region/aved/cips/NOC_CPM_PCIE_0/pspmc_0_psv_noc_pcie_2] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_64/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_65/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_66/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces slash/ddr_bandwidth_67/Data_m_axi_gmem0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S01_INI/C1_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_LOW0] + exclude_bd_addr_seg -offset 0xFFA80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_0] + exclude_bd_addr_seg -offset 0xFFA90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_1] + exclude_bd_addr_seg -offset 0xFFAA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_2] + exclude_bd_addr_seg -offset 0xFFAB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_3] + exclude_bd_addr_seg -offset 0xFFAC0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_4] + exclude_bd_addr_seg -offset 0xFFAD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_5] + exclude_bd_addr_seg -offset 0xFFAE0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_6] + exclude_bd_addr_seg -offset 0xFFAF0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_7] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_apu_0] + exclude_bd_addr_seg -offset 0x000100800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_0] + exclude_bd_addr_seg -offset 0x000100D10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_cti] + exclude_bd_addr_seg -offset 0x000100D00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_dbg] + exclude_bd_addr_seg -offset 0x000100D30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_etm] + exclude_bd_addr_seg -offset 0x000100D20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_pmu] + exclude_bd_addr_seg -offset 0x000100D50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_cti] + exclude_bd_addr_seg -offset 0x000100D40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_dbg] + exclude_bd_addr_seg -offset 0x000100D70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_etm] + exclude_bd_addr_seg -offset 0x000100D60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_pmu] + exclude_bd_addr_seg -offset 0x000100CA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_cti] + exclude_bd_addr_seg -offset 0x000100C60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_ela] + exclude_bd_addr_seg -offset 0x000100C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_etf] + exclude_bd_addr_seg -offset 0x000100C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_fun] + exclude_bd_addr_seg -offset 0x000100F80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_atm] + exclude_bd_addr_seg -offset 0x000100FA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2a] + exclude_bd_addr_seg -offset 0x000100FD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2d] + exclude_bd_addr_seg -offset 0x000100F40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2a] + exclude_bd_addr_seg -offset 0x000100F50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2b] + exclude_bd_addr_seg -offset 0x000100F60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2c] + exclude_bd_addr_seg -offset 0x000100F70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2d] + exclude_bd_addr_seg -offset 0x000100F20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_fun] + exclude_bd_addr_seg -offset 0x000100F00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_rom] + exclude_bd_addr_seg -offset 0x000100B80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_atm] + exclude_bd_addr_seg -offset 0x000100B70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_stm] + exclude_bd_addr_seg -offset 0x000100980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_lpd_atm] + exclude_bd_addr_seg -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_cpm] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crf_0] + exclude_bd_addr_seg -offset 0xFF5E0000 -range 0x00300000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crl_0] + exclude_bd_addr_seg -offset 0x000101260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crp_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_2] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_cci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_gpv_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_maincci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slave_xmpu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_secure_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmutcu_0] + exclude_bd_addr_seg -offset 0xFF0B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_gpio_2] + exclude_bd_addr_seg -offset 0xFF020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_0] + exclude_bd_addr_seg -offset 0xFF030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_1] + exclude_bd_addr_seg -offset 0xFF360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_3] + exclude_bd_addr_seg -offset 0xFF370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_4] + exclude_bd_addr_seg -offset 0xFF380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_5] + exclude_bd_addr_seg -offset 0xFF3A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_6] + exclude_bd_addr_seg -offset 0xFF320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc] + exclude_bd_addr_seg -offset 0xFF390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc_nobuf] + exclude_bd_addr_seg -offset 0xFF310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_psm] + exclude_bd_addr_seg -offset 0xFF9B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_afi_0] + exclude_bd_addr_seg -offset 0xFF0A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_secure_slcr_0] + exclude_bd_addr_seg -offset 0xFF080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_slcr_0] + exclude_bd_addr_seg -offset 0xFF410000 -range 0x00100000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_0] + exclude_bd_addr_seg -offset 0xFF510000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_secure_0] + exclude_bd_addr_seg -offset 0xFF990000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_xppu_0] + exclude_bd_addr_seg -offset 0xFF960000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ctrl] + exclude_bd_addr_seg -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ram_0] + exclude_bd_addr_seg -offset 0xFF980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_xmpu_0] + exclude_bd_addr_seg -offset 0x0001011E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_aes] + exclude_bd_addr_seg -offset 0x0001011F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_bbram_ctrl] + exclude_bd_addr_seg -offset 0x0001012D0000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfi_cframe_0] + exclude_bd_addr_seg -offset 0x0001012B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfu_apb_0] + exclude_bd_addr_seg -offset 0x0001011C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_0] + exclude_bd_addr_seg -offset 0x0001011D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_1] + exclude_bd_addr_seg -offset 0x000101250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_cache] + exclude_bd_addr_seg -offset 0x000101240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_ctrl] + exclude_bd_addr_seg -offset 0x000101110000 -range 0x00050000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_global_0] + exclude_bd_addr_seg -offset 0x000101020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_gpio_0] + exclude_bd_addr_seg -offset 0x000100280000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_iomodule_0] + exclude_bd_addr_seg -offset 0x000101010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ospi_0] + exclude_bd_addr_seg -offset 0x000100310000 -range 0x00008000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ppu1_mdm_0] + exclude_bd_addr_seg -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_qspi_ospi_flash_0] + exclude_bd_addr_seg -offset 0x000102000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram] + exclude_bd_addr_seg -offset 0x000100240000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_data_cntlr] + exclude_bd_addr_seg -offset 0x000100200000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_instr_cntlr] + exclude_bd_addr_seg -offset 0x000106000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_npi] + exclude_bd_addr_seg -offset 0x000101200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rsa] + exclude_bd_addr_seg -offset 0x0001012A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rtc_0] + exclude_bd_addr_seg -offset 0x000101040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sd_0] + exclude_bd_addr_seg -offset 0x000101210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sha] + exclude_bd_addr_seg -offset 0x000101270000 -range 0x00030000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sysmon_0] + exclude_bd_addr_seg -offset 0x000100083000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_inject_0] + exclude_bd_addr_seg -offset 0x000100283000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_manager_0] + exclude_bd_addr_seg -offset 0x000101230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_trng] + exclude_bd_addr_seg -offset 0x0001012F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xmpu_0] + exclude_bd_addr_seg -offset 0x000101310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_0] + exclude_bd_addr_seg -offset 0x000101300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_npi_0] + exclude_bd_addr_seg -offset 0xFFC90000 -range 0x0000F000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_psm_global_reg] + exclude_bd_addr_seg -offset 0xFFE90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_atcm_global] + exclude_bd_addr_seg -offset 0xFFEB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_btcm_global] + exclude_bd_addr_seg -offset 0xFFE00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_tcm_ram_global] + exclude_bd_addr_seg -offset 0xFF9A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_rpu_0] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_0] + exclude_bd_addr_seg -offset 0xFF010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_1] + exclude_bd_addr_seg -offset 0xFF130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntr_0] + exclude_bd_addr_seg -offset 0xFF140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntrs_0] + exclude_bd_addr_seg -offset 0xFF040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_spi_0] + exclude_bd_addr_seg -offset 0xFF0E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_0] + exclude_bd_addr_seg -offset 0xFF0F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_1] + exclude_bd_addr_seg -offset 0xFF100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_2] + exclude_bd_addr_seg -offset 0xFF110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_0] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_3] + exclude_bd_addr_seg -offset 0xFFA80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_0] + exclude_bd_addr_seg -offset 0xFFA90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_1] + exclude_bd_addr_seg -offset 0xFFAA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_2] + exclude_bd_addr_seg -offset 0xFFAB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_3] + exclude_bd_addr_seg -offset 0xFFAC0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_4] + exclude_bd_addr_seg -offset 0xFFAD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_5] + exclude_bd_addr_seg -offset 0xFFAE0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_6] + exclude_bd_addr_seg -offset 0xFFAF0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_adma_7] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_apu_0] + exclude_bd_addr_seg -offset 0x000100800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_0] + exclude_bd_addr_seg -offset 0x000100D10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_cti] + exclude_bd_addr_seg -offset 0x000100D00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_dbg] + exclude_bd_addr_seg -offset 0x000100D30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_etm] + exclude_bd_addr_seg -offset 0x000100D20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a720_pmu] + exclude_bd_addr_seg -offset 0x000100D50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_cti] + exclude_bd_addr_seg -offset 0x000100D40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_dbg] + exclude_bd_addr_seg -offset 0x000100D70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_etm] + exclude_bd_addr_seg -offset 0x000100D60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_a721_pmu] + exclude_bd_addr_seg -offset 0x000100CA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_cti] + exclude_bd_addr_seg -offset 0x000100C60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_ela] + exclude_bd_addr_seg -offset 0x000100C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_etf] + exclude_bd_addr_seg -offset 0x000100C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_apu_fun] + exclude_bd_addr_seg -offset 0x000100F80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_atm] + exclude_bd_addr_seg -offset 0x000100FA0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2a] + exclude_bd_addr_seg -offset 0x000100FD0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_cti2d] + exclude_bd_addr_seg -offset 0x000100F40000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2a] + exclude_bd_addr_seg -offset 0x000100F50000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2b] + exclude_bd_addr_seg -offset 0x000100F60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2c] + exclude_bd_addr_seg -offset 0x000100F70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_ela2d] + exclude_bd_addr_seg -offset 0x000100F20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_fun] + exclude_bd_addr_seg -offset 0x000100F00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_cpm_rom] + exclude_bd_addr_seg -offset 0x000100B80000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_atm] + exclude_bd_addr_seg -offset 0x000100B70000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_fpd_stm] + exclude_bd_addr_seg -offset 0x000100980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_coresight_lpd_atm] + exclude_bd_addr_seg -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_cpm] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crf_0] + exclude_bd_addr_seg -offset 0xFF5E0000 -range 0x00300000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crl_0] + exclude_bd_addr_seg -offset 0x000101260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_crp_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_afi_2] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_cci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_gpv_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_maincci_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slave_xmpu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_slcr_secure_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmu_0] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_fpd_smmutcu_0] + exclude_bd_addr_seg -offset 0xFF0B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_gpio_2] + exclude_bd_addr_seg -offset 0xFF020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_0] + exclude_bd_addr_seg -offset 0xFF030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_i2c_1] + exclude_bd_addr_seg -offset 0xFF360000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_3] + exclude_bd_addr_seg -offset 0xFF370000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_4] + exclude_bd_addr_seg -offset 0xFF380000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_5] + exclude_bd_addr_seg -offset 0xFF3A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_6] + exclude_bd_addr_seg -offset 0xFF320000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc] + exclude_bd_addr_seg -offset 0xFF390000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_pmc_nobuf] + exclude_bd_addr_seg -offset 0xFF310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ipi_psm] + exclude_bd_addr_seg -offset 0xFF9B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_afi_0] + exclude_bd_addr_seg -offset 0xFF0A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_secure_slcr_0] + exclude_bd_addr_seg -offset 0xFF080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_iou_slcr_0] + exclude_bd_addr_seg -offset 0xFF410000 -range 0x00100000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_0] + exclude_bd_addr_seg -offset 0xFF510000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_slcr_secure_0] + exclude_bd_addr_seg -offset 0xFF990000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_lpd_xppu_0] + exclude_bd_addr_seg -offset 0xFF960000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ctrl] + exclude_bd_addr_seg -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_ram_0] + exclude_bd_addr_seg -offset 0xFF980000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ocm_xmpu_0] + exclude_bd_addr_seg -offset 0x0001011E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_aes] + exclude_bd_addr_seg -offset 0x0001011F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_bbram_ctrl] + exclude_bd_addr_seg -offset 0x0001012D0000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfi_cframe_0] + exclude_bd_addr_seg -offset 0x0001012B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_cfu_apb_0] + exclude_bd_addr_seg -offset 0x0001011C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_0] + exclude_bd_addr_seg -offset 0x0001011D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_dma_1] + exclude_bd_addr_seg -offset 0x000101250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_cache] + exclude_bd_addr_seg -offset 0x000101240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_efuse_ctrl] + exclude_bd_addr_seg -offset 0x000101110000 -range 0x00050000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_global_0] + exclude_bd_addr_seg -offset 0x000101020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_gpio_0] + exclude_bd_addr_seg -offset 0x000100280000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_iomodule_0] + exclude_bd_addr_seg -offset 0x000101010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ospi_0] + exclude_bd_addr_seg -offset 0x000100310000 -range 0x00008000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ppu1_mdm_0] + exclude_bd_addr_seg -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_qspi_ospi_flash_0] + exclude_bd_addr_seg -offset 0x000102000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram] + exclude_bd_addr_seg -offset 0x000100240000 -range 0x00020000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_data_cntlr] + exclude_bd_addr_seg -offset 0x000100200000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_instr_cntlr] + exclude_bd_addr_seg -offset 0x000106000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_ram_npi] + exclude_bd_addr_seg -offset 0x000101200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rsa] + exclude_bd_addr_seg -offset 0x0001012A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_rtc_0] + exclude_bd_addr_seg -offset 0x000101040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sd_0] + exclude_bd_addr_seg -offset 0x000101210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sha] + exclude_bd_addr_seg -offset 0x000101270000 -range 0x00030000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_sysmon_0] + exclude_bd_addr_seg -offset 0x000100083000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_inject_0] + exclude_bd_addr_seg -offset 0x000100283000 -range 0x00001000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_tmr_manager_0] + exclude_bd_addr_seg -offset 0x000101230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_trng] + exclude_bd_addr_seg -offset 0x0001012F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xmpu_0] + exclude_bd_addr_seg -offset 0x000101310000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_0] + exclude_bd_addr_seg -offset 0x000101300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_pmc_xppu_npi_0] + exclude_bd_addr_seg -offset 0xFFC90000 -range 0x0000F000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_psm_global_reg] + exclude_bd_addr_seg -offset 0xFFE90000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_atcm_global] + exclude_bd_addr_seg -offset 0xFFEB0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_1_btcm_global] + exclude_bd_addr_seg -offset 0xFFE00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_r5_tcm_ram_global] + exclude_bd_addr_seg -offset 0xFF9A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_rpu_0] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_0] + exclude_bd_addr_seg -offset 0xFF010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_sbsauart_1] + exclude_bd_addr_seg -offset 0xFF130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntr_0] + exclude_bd_addr_seg -offset 0xFF140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_scntrs_0] + exclude_bd_addr_seg -offset 0xFF040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_spi_0] + exclude_bd_addr_seg -offset 0xFF0E0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_0] + exclude_bd_addr_seg -offset 0xFF0F0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_1] + exclude_bd_addr_seg -offset 0xFF100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_2] + exclude_bd_addr_seg -offset 0xFF110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/CPM_PCIE_NOC_1] [get_bd_addr_segs static_region/aved/cips/NOC_PMC_AXI_0/pspmc_0_psv_ttc_3] + exclude_bd_addr_seg -offset 0x050080000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces static_region/aved/cips/LPD_AXI_NOC_0] [get_bd_addr_segs static_region/noc/axi_noc_mc_ddr4_0/S00_INI/C0_DDR_CH1] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/linker/slashkit/resources/bd_ports.txt b/linker/slashkit/resources/bd_ports.txt new file mode 100644 index 00000000..e67976ec --- /dev/null +++ b/linker/slashkit/resources/bd_ports.txt @@ -0,0 +1,88 @@ +HBM0:HBM_AXI_00 AXI4FULL +HBM1:HBM_AXI_01 AXI4FULL +HBM2:HBM_AXI_02 AXI4FULL +HBM3:HBM_AXI_03 AXI4FULL +HBM4:HBM_AXI_04 AXI4FULL +HBM5:HBM_AXI_05 AXI4FULL +HBM6:HBM_AXI_06 AXI4FULL +HBM7:HBM_AXI_07 AXI4FULL +HBM8:HBM_AXI_08 AXI4FULL +HBM9:HBM_AXI_09 AXI4FULL +HBM10:HBM_AXI_10 AXI4FULL +HBM11:HBM_AXI_11 AXI4FULL +HBM12:HBM_AXI_12 AXI4FULL +HBM13:HBM_AXI_13 AXI4FULL +HBM14:HBM_AXI_14 AXI4FULL +HBM15:HBM_AXI_15 AXI4FULL +HBM16:HBM_AXI_16 AXI4FULL +HBM17:HBM_AXI_17 AXI4FULL +HBM18:HBM_AXI_18 AXI4FULL +HBM19:HBM_AXI_19 AXI4FULL +HBM20:HBM_AXI_20 AXI4FULL +HBM21:HBM_AXI_21 AXI4FULL +HBM22:HBM_AXI_22 AXI4FULL +HBM23:HBM_AXI_23 AXI4FULL +HBM24:HBM_AXI_24 AXI4FULL +HBM25:HBM_AXI_25 AXI4FULL +HBM26:HBM_AXI_26 AXI4FULL +HBM27:HBM_AXI_27 AXI4FULL +HBM28:HBM_AXI_28 AXI4FULL +HBM29:HBM_AXI_29 AXI4FULL +HBM30:HBM_AXI_30 AXI4FULL +HBM31:HBM_AXI_31 AXI4FULL +HBM32:HBM_AXI_32 AXI4FULL +HBM33:HBM_AXI_33 AXI4FULL +HBM34:HBM_AXI_34 AXI4FULL +HBM35:HBM_AXI_35 AXI4FULL +HBM36:HBM_AXI_36 AXI4FULL +HBM37:HBM_AXI_37 AXI4FULL +HBM38:HBM_AXI_38 AXI4FULL +HBM39:HBM_AXI_39 AXI4FULL +HBM40:HBM_AXI_40 AXI4FULL +HBM41:HBM_AXI_41 AXI4FULL +HBM42:HBM_AXI_42 AXI4FULL +HBM43:HBM_AXI_43 AXI4FULL +HBM44:HBM_AXI_44 AXI4FULL +HBM45:HBM_AXI_45 AXI4FULL +HBM46:HBM_AXI_46 AXI4FULL +HBM47:HBM_AXI_47 AXI4FULL +HBM48:HBM_AXI_48 AXI4FULL +HBM49:HBM_AXI_49 AXI4FULL +HBM50:HBM_AXI_50 AXI4FULL +HBM51:HBM_AXI_51 AXI4FULL +HBM52:HBM_AXI_52 AXI4FULL +HBM53:HBM_AXI_53 AXI4FULL +HBM54:HBM_AXI_54 AXI4FULL +HBM55:HBM_AXI_55 AXI4FULL +HBM56:HBM_AXI_56 AXI4FULL +HBM57:HBM_AXI_57 AXI4FULL +HBM58:HBM_AXI_58 AXI4FULL +HBM59:HBM_AXI_59 AXI4FULL +HBM60:HBM_AXI_60 AXI4FULL +HBM61:HBM_AXI_61 AXI4FULL +HBM62:HBM_AXI_62 AXI4FULL +HBM63:HBM_AXI_63 AXI4FULL + +DDR0:M00_INI AXI4FULL +DDR1:M01_INI AXI4FULL +DDR2:M02_INI AXI4FULL +DDR3:M03_INI AXI4FULL + +MEM:HBM_VNOC_INI_00 AXI4FULL +MEM:HBM_VNOC_INI_01 AXI4FULL +MEM:HBM_VNOC_INI_02 AXI4FULL +MEM:HBM_VNOC_INI_03 AXI4FULL +MEM:HBM_VNOC_INI_04 AXI4FULL +MEM:HBM_VNOC_INI_05 AXI4FULL +MEM:HBM_VNOC_INI_06 AXI4FULL +MEM:HBM_VNOC_INI_07 AXI4FULL + +VIRT0:SL_VIRT_0 AXI4FULL +VIRT1:SL_VIRT_1 AXI4FULL +VIRT2:SL_VIRT_2 AXI4FULL +VIRT3:SL_VIRT_3 AXI4FULL + +HOST:QDMA_SLAVE_BRIDGE AXI4FULL + +clock:aclk1 CLOCK +reset:ap_rst_n RESET diff --git a/linker/slashkit/resources/dcmac/__init__.py b/linker/slashkit/resources/dcmac/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/dcmac/driver/axi_gt_controller.py b/linker/slashkit/resources/dcmac/driver/axi_gt_controller.py new file mode 100644 index 00000000..62a1a190 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/axi_gt_controller.py @@ -0,0 +1,121 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + + +import argparse +import numpy as np +import time +from axigpio_mmio import AxiGpioMMIO +from generic_mmio import hex_or_int, int_types +from utils import add_common_args, get_ip_offset + + +shift_map = { + 'gt_reset': {'shift': 0, 'bits': 1}, + 'gt_line_rate': {'shift': 1, 'bits': 8}, + 'loopback': {'shift': 9, 'bits': 3}, + 'txprecursor': {'shift': 12, 'bits': 6}, + 'txpostcursor': {'shift': 18, 'bits': 6}, + 'txmaincursor': {'shift': 24, 'bits': 6}, + 'rxcdrhold': {'shift': 31, 'bits': 1}, +} + + +def _get_shift_and_mask(key: str) -> tuple[int, int]: + """Return the shift and mask give the key""" + map = shift_map[key] + return map['shift'], (1 << map['bits']) - 1 + + +def _get_updated_value(key: str, cval: int, nval: int) -> int: + """Generate the updated 32-bit value applying a shift and mask""" + + shift, mask = _get_shift_and_mask(key) + shiftedmask = np.uint32(mask << shift & 0xFFFF_FFFF) + cval_cleared = np.uint32(cval & ~shiftedmask) + shiftedval = np.uint32(((nval & mask) << shift) & 0xFFFF_FFFF) + + return np.uint32(shiftedval | cval_cleared) + + +class AxiGTController(AxiGpioMMIO): + + def __init__(self, device: str = 'e2', resource: int = 2, + base_offset: int = 0x0, gpio_index: int = 0): + self._gpio_index = gpio_index + super().__init__(device, resource, base_offset) + + def _get(self, key: str, gpio: int = 0): + shift, mask = _get_shift_and_mask(key) + return (self.read(gpio) >> shift) & mask + + def _set(self, key: str, gpio: int, val: int): + if not isinstance(val, int_types): + raise ValueError(f"'{val=}' is not a '{int_types}' type") + + cval = self.read(gpio) + uval = _get_updated_value(key, cval, val) + self.write(gpio, uval) + + def _create_property(key: str, gpio: int = 0): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key, gpio), + lambda self, val: self._set(key, gpio, val) + ) + + gt_reset = _create_property('gt_reset') + gt_line_rate = _create_property('gt_line_rate') + loopback = _create_property('loopback') + txprecursor = _create_property('txprecursor') + txpostcursor = _create_property('txpostcursor') + txmaincursor = _create_property('txmaincursor') + rxcdrhold = _create_property('rxcdrhold') + + +def main(args): + offset = get_ip_offset(0x204_0000, args.dcmac) + obj = AxiGTController(args.dev, base_offset=offset, gpio_index=0) + + if args.reset: + print('Resetting GT') + obj.gt_reset = 1 + time.sleep(0.1) + obj.gt_reset = 0 + return + + if args.loopback is not None: + obj.loopback = args.loopback + time.sleep(0.1) + print(f'Loopback mode set to: {obj.loopback}') + return + + if args.linerate: + obj.gt_line_rate = args.linerate + time.sleep(0.1) + print(f'Line rate mode set to: {obj.gt_line_rate}') + return + + print(f'{obj.gt_reset=}') + print(f'{obj.gt_line_rate=}') + print(f'{obj.loopback=}') + print(f'{obj.txprecursor=}') + print(f'{obj.txpostcursor=}') + print(f'{obj.txmaincursor=}') + print(f'{obj.rxcdrhold=}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-l', '--loopback', type=hex_or_int, help="Loopback " + f" mode, a {shift_map['loopback']['bits']}-bit value", + default=None) + parser.add_argument('-r', '--reset', action='store_true', + help='Reset GT') + parser.add_argument('-s', '--linerate', help="Line-rate mode a " + f"{shift_map['gt_line_rate']['bits']}-bit value", + type=hex_or_int) + parser = add_common_args(parser) + + main(parser.parse_args()) diff --git a/linker/slashkit/resources/dcmac/driver/axigpio_mmio.py b/linker/slashkit/resources/dcmac/driver/axigpio_mmio.py new file mode 100644 index 00000000..a6d42705 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/axigpio_mmio.py @@ -0,0 +1,96 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + + +import argparse +from generic_mmio import GenericMMIO, int_types +from utils import add_common_args, get_ip_offset + + +key_map_offset = { + 'gpio_tri': 0x4, + 'gpio2_tri': 0xc, + 'gier': 0x11C, + 'ip_ier': 0x128, + 'ip_isr': 0x120, +} + + +class AxiGpioMMIO(GenericMMIO): + """Driver to work with AXI GPIO""" + + _data_off = 0 + _tri_off = 4 + + def write(self, gpio: int = 0, value: int = 0): + """Write to """ + offset = self._data_off + 0x8 * gpio + super().write(offset, value) + + def read(self, gpio: int = 0): + offset = self._data_off + 0x8 * gpio + return super().read(offset) + + def _get(self, key: str): + offset = key_map_offset[key] + return super().read(offset) + + def _set(self, key: str, val: int): + if not isinstance(val, int_types): + raise ValueError(f"'{val=}' is not a '{int_types}' type") + offset = key_map_offset[key] + super().write(offset, val) + + def _create_property(key: str): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key), + lambda self, val: self._set(key, val) + ) + + gpio_tri = _create_property('gpio_tri') + gpio2_tri = _create_property('gpio2_tri') + gier = _create_property('gier') + ip_ier = _create_property('ip_ier') + ip_isr = _create_property('ip_isr') + + +def main(args): + value = 0 + if args.reset: + value = (2**32) - 1 + + offset0 = get_ip_offset(0x204_0000, args.dcmac) + obj = AxiGpioMMIO(args.dev, base_offset=offset0) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + offset1 = get_ip_offset(0x204_0100, args.dcmac) + obj = AxiGpioMMIO(args.dev, base_offset=offset1) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + offset2 = get_ip_offset(0x204_0300, args.dcmac) + obj = AxiGpioMMIO(args.dev, base_offset=offset2) + obj.write(0, value) + print(f'GPIO1: 0x{obj.base_address:X}, value={obj.read(0)}') + obj.write(1, value) + print(f'GPIO2: 0x{obj.base_address:X}, value={obj.read(1)}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-r', '--reset', action='store_true', + help='Reset Logic') + parser = add_common_args(parser) + + args = parser.parse_args() + + main(args) diff --git a/linker/slashkit/resources/dcmac/driver/dcmac_init.py b/linker/slashkit/resources/dcmac/driver/dcmac_init.py new file mode 100644 index 00000000..58a788bd --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/dcmac_init.py @@ -0,0 +1,164 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import time +from axi_gt_controller import AxiGTController +from dcmac_mmio import DCMAC +from generic_mmio import hex_or_int +from gpio_monitor import AxiGPIOMonitor +from axigpio_mmio import AxiGpioMMIO +from utils import add_common_args, get_ip_offset + +def dcmac_reset_procedure(reset_tx: bool = True, dcmac_idx: int = 0): + """Reset DCMAC and GTs""" + global intf_id, dcmac, gt_gpio, monitor, gtdatapath + print(f'Working with {dcmac_idx=}') + # 1: reset GTs + if reset_tx: + print(" Resetting Tx GTs ", end= "", flush=True) + gt_gpio.gt_reset = 1 + time.sleep(0.001) + gt_gpio.gt_reset = 0 + else: + print(" Resetting only GTs RX datapath ", end= "", flush=True) + gtdatapath.write(0x0, 0xF) + time.sleep(0.01) + gtdatapath.write(0x0, 0x0) + + # 2: Wait for GT reset to finish + for _ in range(20): + signed_to_check = [f'gt{intf_id}_tx_reset_done',f'gt{intf_id}_rx_reset_done'] + ready = True + for signal in signed_to_check: + ready &= getattr(monitor, signal) == 0xF + if ready: + print(f"Done -> ", end= "", flush=True) + break + print(".", end= "", flush=True) + time.sleep(0.1) + else: + print(f"GTs not comming out of reset after 2 sec. Exiting...") + print(f" Debug info: {monitor.gt0_tx_reset_done=}, {monitor.gt1_tx_reset_done=}") + print(f" {monitor.gtpowergood=}") + time.sleep(0.1) + # time.sleep(0.5) + + # 3: reset DCMAC Tx + tx_rst_success = None + if reset_tx: + print("Resetting DCMAC Tx -> ", end= "", flush=True) + # status will be cleared after Rx reset, if successful + tx_rst_success = dcmac.reset_tx(clear_status_history= False) + + # 4: reset DCMAC Rx + print("Resetting DCMAC Rx ", end= "", flush=True) + rx_rst_success = dcmac.reset_rx(clear_status_history= True) + return tx_rst_success, rx_rst_success + +def dcmac_logic_init(args): + global intf_id, dcmac, gt_gpio, monitor, gtdatapath + + intf_id = 0 # TODO: in the future, we'll have 2 interfaces per DCMAC + dcmac = DCMAC(args.dev, base_offset=get_ip_offset(0x200_0000, args.dcmac)) + gt_gpio = AxiGTController(args.dev, base_offset=get_ip_offset(0x204_0000, args.dcmac), + gpio_index=0) + monitor = AxiGPIOMonitor(args.dev, base_offset=get_ip_offset(0x204_0200, args.dcmac), gpio_index=0) + gtdatapath = AxiGpioMMIO(args.dev, base_offset=get_ip_offset(0x204_0400, args.dcmac)) + + # Set GT Tx analog front-end swing and pre/post-emphasis: + # TODO: Fine-tune the following configuration. In general, this achieves alignment, + # 24 dB SNR and seems to stay aligned for a couple of days + # These values are now set by default in the GPIO + #gt_gpio.txprecursor = 6 + #gt_gpio.txmaincursor = 52 + #gt_gpio.txpostcursor = 6 + + if args.verbose > 0: + print(f'{dcmac._base_offset=:#x}') + print(f'{gt_gpio._base_offset=:#x}') + print(f'{monitor._base_offset=:#x}') + print(f'{gtdatapath._base_offset=:#x}') + print(f'{monitor.dual_dcmac=}') + print(f'{gt_gpio.txprecursor=}') + print(f'{gt_gpio.txmaincursor=}') + print(f'{gt_gpio.txpostcursor=}') + + if args.loopback is not None: + if args.loopback != args.loopback: + gt_gpio.loopback = args.loopback + time.sleep(0.1) + print(f'Loopback mode set to: {gt_gpio.loopback}') + args.init = True + + if args.keep_alive: + print('Keep ALIVE path') + iters = 0 + init_time = time.time() + prev_link_up = dcmac.link_up + while True: + iters += 1 + if dcmac.link_up: + if iters % 100 == 0: + print(f"\rDCMAC {args.dcmac} link still up after {time.time() - init_time:.1f} s", end="", flush=True) + else: + if prev_link_up: + print(f" | Link Down |") + dcmac_reset_procedure(not dcmac.tx_aligned, args.dcmac) + if dcmac.link_up: + print(" | Link up again") + init_time = time.time() + prev_link_up = dcmac.link_up + time.sleep(0.05) + + # TODO, we need an independent reset TX code + if args.init or args.align_rx: + print(f'INIT or ALIGN RX. {args.init=} {args.align_rx=}') + if args.verbose > 1: + dcmac.print_config(False) + print(f"{gt_gpio.loopback=}") + print(f"{gt_gpio.txprecursor=}") + print(f"{gt_gpio.txmaincursor=}") + print(f"{gt_gpio.txpostcursor=}") + print('\nResetting GT -> DCMAC Tx -> DCMAC Rx') + + NUM_OF_RETRIES = 10 + reset_tx = args.init + # Iterate through reset routine until MAC is ready or we run out of retries + for retry_id in range(NUM_OF_RETRIES): + tx_rst_success, rx_rst_success = dcmac_reset_procedure(reset_tx, args.dcmac) + tx_rst_success = tx_rst_success if reset_tx else True + reset_tx = tx_rst_success + if tx_rst_success and rx_rst_success: + print(f"DCMAC initialization successful after {retry_id} retries") + break + else: + print(f"DCMAC initialization failed after {NUM_OF_RETRIES} retries. DCMAC state:") + dcmac.print_status(only_modified_fields=True) + print(f"Exiting...") + exit(1) + + if args.verbose > 0: + dcmac.print_status(only_modified_fields=args.verbose < 2) + + dcmac.tx_stats(0, True, verbose=args.verbose) + dcmac.rx_stats(0, True, verbose=args.verbose) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-i', '--init', action='store_true', + help='Initialize system') + parser.add_argument('-a', '--align_rx', action='store_true',help='Align RX') + parser.add_argument('-k', '--keep_alive', action='store_true',help='Keep link alive') + parser.add_argument('-l', '--loopback', type=hex_or_int, + help="Set GT Loopback", default=None) + parser.add_argument('-t', '--traffic_test', action='store_true', + help='Run traffic test') + # default only status + parser.add_argument('-p', '--print', action='store_true', + help='Print stats') + parser = add_common_args(parser, verbose=True) + + args = parser.parse_args() + dcmac_logic_init(args) diff --git a/linker/slashkit/resources/dcmac/driver/dcmac_mmio.py b/linker/slashkit/resources/dcmac/driver/dcmac_mmio.py new file mode 100644 index 00000000..c0842929 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/dcmac_mmio.py @@ -0,0 +1,438 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import pprint +import time +from tabulate import tabulate +from generic_mmio import GenericMMIO +from dcmac_reg import registers, tx_stats_base_reg, rx_stats_base_reg +from utils import rshift, add_common_args, get_ip_offset + +class DCMAC(GenericMMIO): + """"DCMAC MMIO Driver""" + + def __init__(self, device: str = 'e2', resource: int = 2, + base_offset: int = 0x0): + super().__init__(device, resource, base_offset) + self.set_pm_tick_trigger() + + def write(self, offset, value): + if isinstance(offset, str): + offset = registers[offset]['offset'] + super().write(offset, value) + + def read(self, offset): + if isinstance(offset, str): + offset = registers[offset]['offset'] + return super().read(offset) + + #TODO: __getattr__ and __setattr__ need more validation + def __getattr__(self, name): + """Get the value of a register""" + if name in registers: + val = self.read(name) + if registers[name].get('fields'): + field_dict = dict() + for k, v in registers[name]['fields'].items(): + field_dict[k] = rshift(val, v['start'], v['length']) + return field_dict + else: + return val + else: + raise AttributeError(f"'{self.__class__.__name__}' object has " + f"no attribute '{name}'") + + #TODO: validate + def __setattr__(self, name, value): + """Set the value of a register""" + if name in registers: + # TODO: accept value as a dictionary to set individual fields + if isinstance(value, dict): + values_dict = value + value = self.read(name) + reg_fields = registers[name].get('fields', {}) + for field_name, field_value in values_dict.items(): + if field_name in reg_fields: + field = registers[name]['fields'][field_name] + start, length = field['start'], field['length'] + mask = ((1 << length) - 1) << start + value &= ~ mask # clear the bits + value |= (field_value << start) & mask # set the bits + else: + raise ValueError(f"Field '{field_name}' not found " + f"in register '{name}'") + + self.write(name, value) + else: + super().__setattr__(name, value) + + # TODO: implement functions to read and write channel registers without + # having to specify the channel offset, just the channel number + # def read_chn_reg(self, chn_reg_name, channel): + # offset = registers['C0_' + chn_reg_name]['offset'] + # return self._pciemmio.read(self._offset + offset) + + def read_reg_field(self, reg_name: str, field: str): + """Read a field from reg'""" + field = registers[reg_name]['fields'][field] + val = self.read(reg_name) + return rshift(val, field['start'], field['length']) + + def read_long(self, offset) -> int: + """Read 8 bytes from BAR 'offset'""" + if isinstance(offset, str): + offset = registers[offset]['offset'] + val_low = self.read(offset) + val_high = self.read(offset + 4) + return int((val_high << 32) + val_low) + + @property + def revision(self): + return self.read('CONFIGURATION_REVISION') + + @property + def ip_dict(self): + vals = {} + for k, v in registers.items(): + readval = self.read(v['offset']) + vals[k] = {'value': readval} + if v.get('fields'): + vals[k]['fields'] = {} + for k1, v1 in v['fields'].items(): + vals[k]['fields'][k1] = rshift(readval, v1['start'], v1['length']) + + return vals + + @property + def status(self): + status_dict = {} + for reg_name, spec in registers.items(): + if "STATUS" in reg_name: + fields = spec.get('fields', False) + readval = self.read(reg_name) + subkey = "real-time" if "_RT_" in reg_name else "latched" + entry_name = reg_name if "_RT_" not in reg_name else reg_name.replace("_RT", "") + if entry_name not in status_dict: + if fields: + status_dict[entry_name] = {} + for f in fields: + + status_dict[entry_name][f] = {"latched": "-", "real-time": "-", "default": fields[f]['default']} + else: + status_dict[entry_name] = {"latched": "-", "real-time": "-", "default": "-"} + + if fields: + for f_name, f_spec in fields.items(): + status_dict[entry_name][f_name][subkey] = rshift(readval, f_spec['start'], f_spec['length']) + else: + status_dict[entry_name][subkey] = readval + return status_dict + + def print_status(self, only_modified_fields: bool = False): + status_dict = self.status + table = [] + table += [["Register", "Field", "Latched", "Real-Time", "Default"]] + for reg_name, fields in status_dict.items(): + row_count = 0 + for field_name, field in fields.items(): + default_val = field["default"] + if only_modified_fields: + if field["latched"] == default_val and field["real-time"] == default_val: + continue + table += [[reg_name if row_count == 0 else "", field_name, field["latched"], field["real-time"], default_val]] + row_count += 1 + if row_count > 0: + table += [["--------------------", "--------------------", "--------", "--------", "--------"]] + if only_modified_fields: + if len(table) == 1: + print("All status Registers have default values") + return + print("Status Registers with non-default values") + else: + print("Status Registers") + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + @property + def config(self): + config_dict = {} + config_regs = ['GLOBAL_MODE', 'C0_TX_MODE_REG', 'C0_RX_MODE_REG'] + for reg_name in config_regs: + spec = registers[reg_name] + fields = spec.get('fields', False) + readval = self.read(spec['offset']) + config_dict[reg_name] = {} + for f_name, f_spec in fields.items(): + val = rshift(readval, f_spec['start'], f_spec['length']) + config_dict[reg_name][f_name] = {"value": val, "default": fields[f_name]['default']} + + return config_dict + + def print_config(self, only_modified_fields: bool = False): + config_dict = self.config + table = [] + table += [["Register", "Field", "Value", "Default"]] + for reg_name, fields in config_dict.items(): + row_count = 0 + for field_name, field in fields.items(): + default_val = field["default"] + if only_modified_fields: + if field["value"] == default_val: + continue + table += [[reg_name if row_count == 0 else "", field_name, field["value"], default_val]] + row_count += 1 + if row_count > 0: + table += [["--------------------", "--------------------", "--------", "--------", "--------"]] + if only_modified_fields: + print("Configuration Registers with non-default values") + else: + print("Configuration Registers") + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def tx_stats(self, port: int = 0, debug: bool = False, + verbose: int = 0): + """Reads and print TX stats for the given port""" + + if isinstance(port, int) and not 0 <= port < 1: + raise ValueError("'port' must be either 0 or 1") + + baseoffset = 0x1000 * (port + 1) + 0x0200 + + # Sets pm tick to be triggered by registers + value = self.read(baseoffset - 0x200 + 0x40) + pm_tick_bit = registers['C0_TX_MODE_REG']['fields']['c0_ctl_tx_tick_reg_mode_sel']['start'] + value |= (1 * (2**pm_tick_bit)) + self.write(baseoffset - 0x200 + 0x40, value) + + # trigger ALL_CHANNEL_MAC_TICK_REG_TX + #offset = registers['ALL_CHANNEL_MAC_TICK_REG_TX']['offset'] + #self.write(offset, 0) + #self.write(offset, 1) + #self.write(offset, 0) + + # trigger pm tick + self.write(baseoffset - 0x200 + 0xFC, 0) + self.write(baseoffset - 0x200 + 0xFC, 1) + + for i in range(10): + val = self.read(baseoffset - 0x200 + 0x808) + if val != 0: + break + + heading = [[f"TX Stats {port=}", "Value"]] + if debug: + heading[0].append('Offset Address') + table = self._stats(baseoffset, 'tx', heading, debug, verbose) + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def rx_stats(self, port: int = 0, debug: bool = False, + verbose: int = 0): + """Reads and print RX stats for the given port""" + + if isinstance(port, int) and not 0 <= port < 1: + raise ValueError("'port' must be either 0 or 1") + + baseoffset = 0x1000 * (port + 1) + 0x0400 + + # Sets pm tick to be triggered by registers + value = self.read(baseoffset - 0x400 + 0x44) + pm_tick_bit = registers['C0_RX_MODE_REG']['fields']['c0_ctl_rx_tick_reg_mode_sel']['start'] + value |= (1 * (2**pm_tick_bit)) + self.write(baseoffset - 0x400 + 0x44, value) + + # trigger ALL_CHANNEL_MAC_TICK_REG_RX + #offset = registers['ALL_CHANNEL_MAC_TICK_REG_RX']['offset'] + #self.write(offset, 0) + #self.write(offset, 1) + #self.write(offset, 0) + + # trigger pm tick + self.write(baseoffset - 0x400 + 0xF4, 0) + self.write(baseoffset - 0x400 + 0xF4, 1) + + for i in range(10): + val = self.read(baseoffset - 0x400 + 0xC08) + if val != 0: + break + + heading = [[f"RX Stats {port=}", "Value"]] + if debug: + heading[0].append('Offset Address') + table = self._stats(baseoffset, 'rx', heading, debug, verbose) + print(tabulate(table, headers="firstrow", tablefmt="pretty")) + + def _stats(self, baseoffset: int, dir: str, tableheading: str, + debug: bool, verbose: int = 0): + + table = tableheading + stats_base_reg = tx_stats_base_reg if dir == 'tx' else rx_stats_base_reg + for k, v in stats_base_reg.items(): + if 'LSB' in k: + readval = self.read_long(baseoffset + v['offset']) + elif 'MSB' in k: + continue + else: + readval = self.read(baseoffset + v['offset']) + + if readval == 0 and verbose < 1: + continue + key = k.replace('_LSB', '') + ltable = [key, readval] + if debug: + ltable.append(f"0x{(baseoffset + v['offset']):X}") + table.append(ltable) + + return table + + def clear_latched_flags(self): + MASK = (1 << 32) - 1 + for reg_name, spec in registers.items(): + if "STATUS" in reg_name: + self.write(spec['offset'], MASK) + + def set_pm_tick_trigger(self) -> int: + """Sets pm tick to be triggered by registers""" + value = self.read(registers['GLOBAL_MODE']['offset']) + tx_reg_bit = registers['GLOBAL_MODE']['fields']['ctl_tx_all_ch_tick_reg_mode_sel']['start'] + rx_reg_bit = registers['GLOBAL_MODE']['fields']['ctl_rx_all_ch_tick_reg_mode_sel']['start'] + + val_tx = 1 * (2**tx_reg_bit) + val_rx = 1 * (2**rx_reg_bit) + val_tx += val_rx + + value |= val_tx + self.write(registers['GLOBAL_MODE']['offset'], value) + return self.read(registers['GLOBAL_MODE']['offset']) + + def reset_tx(self, clear_status_history: bool = True): + """Forces a resets on the transmitting DCMAC core + It Follows the reset procedure outlined in the DCMAC user guide pg369, + page 161 ("Transmit Fixed Ethernet Startup Procedure when Using tx_core_reset") + """ + rst_successful = True + offset = lambda x: registers[x]['offset'] + rst_core_regs = [offset('GLOBAL_CONTROL_REG_TX')] + rst_serdes_regs = [offset('C0_PORT_CONTROL_REG_TX') + 0x1000 * i for i in range(6)] + rst_flush_regs = [offset('C0_CHANNEL_CONTROL_REG_TX') + 0x1000 * i for i in range(6)] + for reg in rst_core_regs + rst_serdes_regs + rst_flush_regs: + self.write(reg, 2**32-1) + time.sleep(0.1) + # first release port RSTs, then core reset + for reg in rst_serdes_regs + rst_core_regs: + self.write(reg, 0x0) + + # wait for tx_local_fault + for _ in range(10): + if self.tx_aligned: + # print('TX status: OK') + break + time.sleep(0.2) + else: + print('TX status: local fault') + rst_successful = False + + # release flush + for reg in rst_flush_regs: + self.write(reg, 0x0) + + if clear_status_history: + self.clear_latched_flags() + return rst_successful + + def reset_rx(self, clear_status_history: bool = True): + """Forces a resets on the receiving DCMAC core + It Follows the reset procedure outlined in the DCMAC user guide pg369, + page 162 ("Receive Fixed Ethernet Startup Procedure when Using rx_core_reset") + """ + ACTIVE_PORTS = 6 # TODO: this should be set by the user + offset = lambda x: registers[x]['offset'] + rst_core_regs = [(offset('GLOBAL_CONTROL_REG_RX'), 7)] + rst_serdes_regs = [(offset('C0_PORT_CONTROL_REG_RX') + 0x1000 * i, 2) for i in range(6)] + rst_flush_regs = [(offset('C0_CHANNEL_CONTROL_REG_RX') + 0x1000 * i, 1) for i in range(6)] + for reg,reset_code in rst_core_regs + rst_serdes_regs + rst_flush_regs: + self.write(reg, reset_code) + + time.sleep(0.5) + # first release core resets, then flush and finally serdes resets + for reg,_ in rst_core_regs + rst_flush_regs[:ACTIVE_PORTS] + rst_serdes_regs[:ACTIVE_PORTS]: + self.write(reg, 0) + + # check Rx alignment + rst_successful = True + for i in range(10): + if self.rx_aligned: + break + print(".", end= "", flush=True) + time.sleep(0.25) + else: + print('WARN: Chn 0 RX failed to achieve alignment') + rst_successful = False + + if clear_status_history: + self.clear_latched_flags() + return rst_successful + + @property + def tx_aligned(self): + # TODO: this should take the channel number as an argument and + # return the corresponding channel status + return self.C0_STAT_CHAN_TX_MAC_RT_STATUS_REG['c0_stat_tx_local_fault'] == 0 + + @property + def rx_aligned(self): + # TODO: this should take the channel number as an argument and + # return the corresponding channel status + chn_status_dict = self.C0_STAT_PORT_RX_PHY_RT_STATUS_REG + return chn_status_dict['c0_stat_rx_status'] == 1 and \ + chn_status_dict['c0_stat_rx_aligned'] == 1 + + @property + def link_up(self): + return self.rx_aligned and self.tx_aligned + +def main(args): + offset = get_ip_offset(0x200_0000, args.dcmac) + obj = DCMAC(args.dev, base_offset=offset) + + if args.tx: + obj.reset_tx() + + if args.rx: + obj.reset_rx() + + if args.rx or args.tx or args.clear: + time.sleep(0.5) + obj.clear_latched_flags() + + if args.status or not (args.rx or args.tx or args.print or args.show_config): + obj.print_status(only_modified_fields=args.verbose < 1) + + if args.show_config: + obj.print_config(only_modified_fields=args.verbose < 1) + + if args.print: + # pprint.pp(obj.ip_dict) + obj.tx_stats(0, True, verbose=args.verbose) + obj.rx_stats(0, True, verbose=args.verbose) + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-r', '--rx', action='store_true', + help='Reset RX') + parser.add_argument('-t', '--tx', action='store_true', + help='Reset TX') + parser.add_argument('-s', '--status', action='store_true', + help='Print status') + # default only status + parser.add_argument('-p', '--print', action='store_true', + help='Print stats') + parser.add_argument('-c', '--clear', action='store_true', + help='Clear latched flags') + parser.add_argument('-C', '--show-config', action='store_true', + help='Show configuration') + parser = add_common_args(parser, verbose=True) + + args = parser.parse_args() + main(args) \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/driver/dcmac_reg.py b/linker/slashkit/resources/dcmac/driver/dcmac_reg.py new file mode 100644 index 00000000..cdcb2bb0 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/dcmac_reg.py @@ -0,0 +1,623 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +registers = { + 'CONFIGURATION_REVISION': {'offset': 0x0, 'type': 'ro'}, + 'GLOBAL_MODE': { + 'offset': 0x4, 'type': 'rw', + 'fields': { + 'ctl_tx_independent_tsmac_and_phy_mode': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_all_ch_tick_reg_mode_sel': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_independent_tsmac_and_phy_mode': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_all_ch_tick_reg_mode_sel': {'start': 5, 'length': 1, 'default': '0', 'type': 'rw'}, + 'ctl_tx_axis_cfg': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_rx_axis_cfg': {'start': 12, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_pcs_active_ports': {'start': 16, 'length': 3, 'default': 5, 'type': 'rw'}, + 'ctl_rx_pcs_active_ports': {'start': 20, 'length': 3, 'default': 5, 'type': 'rw'}, + 'ctl_rx_fec_errind_mode': {'start': 24, 'length': 1, 'default': 1, 'type': 'rw'}, + 'ctl_tx_fec_ck_unique_flip': {'start': 25, 'length': 1, 'default': 1, 'type': 'rw'}, + 'ctl_rx_fec_ck_unique_flip': {'start': 26, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'TEST_DEBUG': { + 'offset': 0x8, 'type': 'rw', + 'fields': { + 'ctl_test_mode_pin_char': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_test_mode_memcel': {'start': 4, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_rx_phy_debug_select': {'start': 8, 'length': 5, 'default': 0, 'type': 'rw'}, + 'ctl_rx_mac_debug_select': {'start': 13, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_tx_phy_debug_select': {'start': 17, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_tx_mac_debug_select': {'start': 21, 'length': 4, 'default': 0, 'type': 'rw'}, + 'ctl_rx_ecc_err_clear': {'start': 25, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_ecc_err_clear': {'start': 26, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_tx_ecc_err_count_tick': {'start': 27, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_axi_af_thresh_override': {'start': 28, 'length': 4, 'default': 8, 'type': 'rw'} + } + }, + 'EMA_CONFIGURATION': { + 'offset': 0xC, 'type': 'rw', + 'fields': { + 'ctl_mem_ctrl': {'start': 0, 'length': 10, 'default': 0x11b, 'type': 'rw'}, + 'emaa': {'start': 0, 'length': 3, 'default': 0x3, 'type': 'rw'}, + 'emab': {'start': 3, 'length': 3, 'default': 0x3, 'type': 'rw'}, + 'emasa': {'start': 6, 'length': 1, 'default': 0x0, 'type': 'rw'}, + 'stov': {'start': 7, 'length': 1, 'default': 0x0, 'type': 'rw'}, + 'mc_mem_ctrl_enable': {'start': 8, 'length': 1, 'default': 0x1, 'type': 'rw'} + } + }, + 'CLOCK_DISABLE': { + 'offset': 0x10, 'type': 'rw', + 'fields': { + 'ctl_mem_disable_rx_axi_clk': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_axi_clk': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_macif_clk': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_macif_clk': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_core_clk': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_core_clk': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_flexif_clk': {'start': 6, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_flexif_clk': {'start': 12, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_serdes_clk': {'start': 18, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_serdes_clk': {'start': 24, 'length': 6, 'default': 0, 'type': 'rw'} + } + }, + 'BLOCK_DISABLE': { + 'offset': 0x14, 'type': 'rw', + 'fields': { + 'ctl_mem_disable_rx_pcs_cpcs': {'start': 0, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_pcs_align_buffer': {'start': 6, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_rx_pcs_decoder': {'start': 12, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_pcs_cpcs': {'start': 16, 'length': 6, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_ts2phy': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ctl_mem_disable_tx_pcs_encoder': {'start': 23, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY0': { + 'offset': 0x18, 'type': 'rw', + 'fields': { + 'ctl_rsvd0': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY1': { + 'offset': 0x1C, 'type': 'rw', + 'fields': { + 'ctl_rsvd1': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY2': { + 'offset': 0x20, 'type': 'rw', + 'fields': { + 'ctl_rsvd2': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY3': { + 'offset': 0x24, 'type': 'rw', + 'fields': { + 'ctl_rsvd3': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY4': { + 'offset': 0x28, 'type': 'rw', + 'fields': { + 'ctl_rsvd4': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY5': { + 'offset': 0x2C, 'type': 'rw', + 'fields': { + 'ctl_rsvd5': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY6': { + 'offset': 0x30, 'type': 'rw', + 'fields': { + 'ctl_rsvd6': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'CONFIGURATION_EMPTY7': { + 'offset': 0x34, 'type': 'rw', + 'fields': { + 'ctl_rsvd7': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'MAC_CONFIG_REG_TX_WR': { + 'offset': 0x38, 'type': 'rw', + 'fields': { + 'mac_tx_cfg_data': {'start': 0, 'length': 8, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_index': {'start': 8, 'length': 5, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_channel': {'start': 16, 'length': 6, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_wr': {'start': 24, 'length': 1, 'default': 0, 'type': 'rw'}, + 'mac_tx_cfg_enable': {'start': 28, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'MAC_CONFIG_REG_TX_RD': { + 'offset': 0x3C, 'type': 'rw', + 'fields': { + 'mac_tx_cfg_data_rd': {'start': 0, 'length': 8, 'default': 0, 'type': 'rw'} + } + }, + 'GLOBAL_CONTROL_REG_RX': { + 'offset': 0xF0, 'type': 'rw', + 'fields': { + 'soft_rx_core_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_rx_macif_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_rx_axi_reset': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + }, + }, + 'ALL_CHANNEL_MAC_TICK_REG_RX': { + 'offset': 0xF4, 'type': 'rw', + 'fields': { + 'rx_all_channel_mac_soft_pm_tick': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'GLOBAL_CONTROL_REG_TX': { + 'offset': 0xF8, 'type': 'rw', + 'fields': { + 'soft_tx_core_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_tx_macif_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'}, + 'soft_tx_axi_reset': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'ALL_CHANNEL_MAC_TICK_REG_TX': { + 'offset': 0xFC, 'type': 'rw', + 'fields': { + 'rx_all_channel_mac_soft_pm_tick': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + }, + }, + 'STAT_TX_ECC_ERR_REG': { + 'offset': 0x1B0, 'type': 'ro', + 'fields': { + 'stat_tx_ecc0_err0': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc0_err1': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc1_err0': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc1_err1': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc2_err0': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'stat_tx_ecc2_err1': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + }, + }, + 'C0_CHANNEL_CONFIGURATION_TX': { + 'offset': 0x1000, 'type': 'rw', + 'fields': { + 'c0_ctl_tx_fcs_ins_enable': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_ignore_fcs': {'start': 1, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_send_lfi': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_send_rfi': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_send_idle': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_custom_preamble_enable': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_ipg_value': {'start': 8, 'length': 4, 'default': 0xC, 'type': 'rw'}, + 'c0_ctl_tx_corrupt_fcs_on_err': {'start': 16, 'length': 2, 'default': 0, 'type': 'rw'}, + } + }, + 'C0_CHANNEL_CONFIGURATION_RX': { + 'offset': 0x1004, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_is_clause_49': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_delete_fcs': {'start': 1, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_ignore_fcs': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_process_lfi': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_check_sfd': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_check_preamble': {'start': 5, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_ignore_inrange': {'start': 6, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_max_packet_len': {'start': 16, 'length': 14, 'default': 0x2580, 'type': 'rw'}, + } + }, + 'C0_CHANNEL_CONTROL_REG_RX': { + 'offset': 0x1030, 'type': 'rw', + 'fields': { + 'c0_soft_rx_mac_channel_flush': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_CHANNEL_CONTROL_REG_TX': { + 'offset': 0x1038, 'type': 'rw', + 'fields': { + 'c0_soft_tx_mac_channel_flush': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_TX_MODE_REG': { + 'offset': 0x1040, 'type': 'rw', + 'fields': { + 'c0_ctl_tx_data_rate': {'start': 0, 'length': 2, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_use_custom_vl_length_minus1': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_use_custom_vl_marker_ids': {'start': 3, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_tick_reg_mode_sel': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_flexif_select': {'start': 5, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_flexif_am_mode': {'start': 7, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_flexif_pcs_wide_mode': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_pma_lane_mux': {'start': 9, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_tx_alt_serdes_clk_mux_disable': {'start': 11, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_fec_mode': {'start': 16, 'length': 5, 'default': 4, 'type': 'rw'}, + 'c0_ctl_tx_fec_transcode_bypass': {'start': 21, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_tx_fec_four_lane_pmd': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_MODE_REG': { + 'offset': 0x1044, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_data_rate': {'start': 0, 'length': 2, 'default': 0, 'type': 'rw'}, + 'c0_ctl_pcs_rx_ts_en': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_test_pattern': {'start': 8, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_use_custom_vl_length_minus1': {'start': 9, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_use_custom_vl_marker_ids': {'start': 10, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_tick_reg_mode_sel': {'start': 11, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_pma_lane_mux': {'start': 12, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_fec_mode': {'start': 16, 'length': 4, 'default': 4, 'type': 'rw'}, + 'c0_ctl_rx_fec_bypass_indication': {'start': 21, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_bypass_correction': {'start': 22, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_transcode_clause49': {'start': 23, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_alignment_bypass': {'start': 24, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_transcode_bypass': {'start': 25, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_degrade_enable': {'start': 26, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_ctl_rx_fec_ext_align_buff_enable': {'start': 27, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION1': { + 'offset': 0x1048, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_interval': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION2': { + 'offset': 0x104C, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_act_thresh': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_RX_FEC_SLICE_CONFIGURATION3': { + 'offset': 0x1050, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_degrade_deact_thresh': {'start': 0, 'length': 32, 'default': 0, 'type': 'rw'} + } + }, + 'C0_CONFIGURATION_RX': { + 'offset': 0x10A0, 'type': 'rw', + 'fields': { + 'c0_ctl_rx_flexif_select': {'start': 0, 'length': 2, 'default': 1, 'type': 'rw'}, + 'c0_ctl_rx_flexif_pcs_wide_mode': {'start': 2, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_CONTROL_REG_RX': { + 'offset': 0x10F0, 'type': 'rw', + 'fields': { + 'c0_soft_rx_flexif_reset': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'c0_soft_rx_serdes_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_TICK_REG_RX': { + 'offset': 0x10F4, 'type': 'rw', + 'fields': { + 'c0_rx_port_soft_pm_tick': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'C0_PORT_CONTROL_REG_TX': { + 'offset': 0x10F8, 'type': 'rw', + 'fields': { + 'c0_soft_tx_flexif_reset': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'}, + 'c0_soft_tx_serdes_reset': {'start': 1, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + 'C0_PORT_TICK_REG_TX': { + 'offset': 0x10FC, 'type': 'rw', + 'fields': { + 'c0_tx_port_soft_pm_tick': {'start': 0, 'length': 1, 'default': 1, 'type': 'rw'} + } + }, + 'C0_STAT_CHAN_TX_MAC_STATUS_REG': { + 'offset': 0x1100, 'type': 'ro', + 'fields': { + 'c0_stat_tx_local_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_ovf': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_unf': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_packet_small': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_sic_overflow': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_TX_MAC_RT_STATUS_REG': { + 'offset': 0x1104, 'type': 'ro', + 'fields': { + 'c0_stat_tx_local_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_ovf': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_tsmac_unf': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_packet_small': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_sic_overflow': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_TX_STATISTICS_READY': { + 'offset': 0x1108, 'type': 'ro', + 'fields': { + 'c0_stat_tx_channel_mac_statistics_ready': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_CHAN_RX_MAC_STATUS_REG': { + 'offset': 0x1140, 'type': 'ro', + 'fields': { + 'c0_stat_rx_remote_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_local_fault': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_internal_local_fault': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_received_local_fault': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_preamble': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_sfd': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_got_signal_os': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_invalid_start': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_code': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_CHAN_RX_MAC_RT_STATUS_REG': { + 'offset': 0x1144, 'type': 'ro', + 'fields': { + 'c0_stat_rx_remote_fault': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_local_fault': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_internal_local_fault': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_received_local_fault': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_preamble': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_sfd': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_got_signal_os': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_invalid_start': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bad_code': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_CHAN_RX_STATISTICS_READY': { + 'offset': 0x1148, 'type': 'ro', + 'fields': { + 'c0_stat_tx_channel_mac_statistics_ready': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + + 'C0_STAT_PORT_TX_MAC_STATUS_REG': { + 'offset': 0x1180, 'type': 'ro', + 'fields': { + 'c0_stat_tx_axis_unf': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_axis_err': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_MAC_RT_STATUS_REG': { + 'offset': 0x1184, 'type': 'ro', + 'fields': { + 'c0_stat_tx_axis_unf': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_axis_err': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_MAC_STATUS_REG': { + 'offset': 0x11C0, 'type': 'ro', + 'fields': { + 'c0_stat_rx_axis_fifo_overflow': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_axis_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_phy2ts_buf_err': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_macif_fifo_ovf': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_MAC_RT_STATUS_REG': { + 'offset': 0x11C4, 'type': 'ro', + 'fields': { + 'c0_stat_rx_axis_fifo_overflow': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_axis_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_phy2ts_buf_err': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_macif_fifo_ovf': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_PHY_STATUS_REG': { + 'offset': 0x1800, 'type': 'ro', + 'fields': { + 'c0_stat_tx_pcs_bad_code': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_fifo_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_coa': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_PHY_RT_STATUS_REG': { + 'offset': 0x1804, 'type': 'ro', + 'fields': { + 'c0_stat_tx_pcs_bad_code': {'start': 0, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_fifo_err': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_tx_flex_coa': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_STATISTICS_READY': { + 'offset': 0x1808, 'type': 'ro' + }, + 'C0_STAT_PORT_TX_FEC_STATUS_REG': { + 'offset': 0x180C, 'type': 'ro', + 'fields': { + 'c0_stat_tx_fec_pcs_lane_align': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_block_lock': {'start': 1, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_am_lock': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_TX_FEC_RT_STATUS_REG': { + 'offset': 0x1810, 'type': 'ro', + 'fields': { + 'c0_stat_tx_fec_pcs_lane_align': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_block_lock': {'start': 1, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_tx_fec_pcs_am_lock': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_PHY_STATUS_REG': { + 'offset': 0x1C00, 'type': 'ro', + 'fields': { + 'c0_stat_rx_status': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_block_lock': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_misaligned': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned_err': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_hi_ber': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_framing_err': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_pcs_bad_code': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced_err': {'start': 9, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bip_err': {'start': 10, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_flex_fifo_err': {'start': 11, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_PORT_RX_PHY_RT_STATUS_REG': { + 'offset': 0x1C04, 'type': 'ro', + 'fields': { + 'c0_stat_rx_status': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_block_lock': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned': {'start': 2, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_misaligned': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_aligned_err': {'start': 4, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_hi_ber': {'start': 5, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_framing_err': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_pcs_bad_code': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced': {'start': 8, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_synced_err': {'start': 9, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_bip_err': {'start': 10, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_flex_fifo_err': {'start': 11, 'length': 1, 'default': 0, 'type': 'ro'}, + } + }, + 'C0_STAT_PORT_RX_STATISTICS_READY': { + 'offset': 0x1C08, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_BLOCK_LOCK_REG': { + 'offset': 0x1C0C, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_LANE_SYNC_REG': { + 'offset': 0x1C10, 'type': 'ro' + }, + 'C0_STAT_PORT_RX_LANE_SYNC_ERR_REG': { + 'offset': 0x1C14, 'type': 'ro' + }, + + 'C0_STAT_PORT_RX_FEC_STATUS_REG': { + 'offset': 0x1C34, 'type': 'ro', + 'fields': { + 'c0_stat_rx_fec_aligned': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_fec_hi_ser': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_lane_lock': {'start': 2, 'length': 4, 'default': 15, 'type': 'ro'}, + 'c0_stat_rx_fec_degraded_ser': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_rm_degraded': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, + 'C0_STAT_PORT_RX_FEC_RT_STATUS_REG': { + 'offset': 0x1C38, 'type': 'ro', + 'fields': { + 'c0_stat_rx_fec_aligned': {'start': 0, 'length': 1, 'default': 1, 'type': 'ro'}, + 'c0_stat_rx_fec_hi_ser': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_lane_lock': {'start': 2, 'length': 4, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_degraded_ser': {'start': 6, 'length': 1, 'default': 0, 'type': 'ro'}, + 'c0_stat_rx_fec_rm_degraded': {'start': 7, 'length': 1, 'default': 0, 'type': 'ro'} + } + }, +} + + +tx_stats_base_reg = { + 'TOTAL_BYTES_LSB': {'offset': 0x00, 'type': 'ro'}, + 'TOTAL_BYTES_MSB': {'offset': 0x04, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_LSB': {'offset': 0x08, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_MSB': {'offset': 0x0C, 'type': 'ro'}, + 'TOTAL_PACKETS_LSB': {'offset': 0x10, 'type': 'ro'}, + 'TOTAL_PACKETS_MSB': {'offset': 0x14, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_LSB': {'offset': 0x18, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_MSB': {'offset': 0x1C, 'type': 'ro'}, + 'FRAME_ERROR_LSB': {'offset': 0x20, 'type': 'ro'}, + 'FRAME_ERROR_MSB': {'offset': 0x24, 'type': 'ro'}, + 'BAD_FCS_LSB': {'offset': 0x28, 'type': 'ro'}, + 'BAD_FCS_MSB': {'offset': 0x2C, 'type': 'ro'}, + 'PACKET_64_BYTES_LSB': {'offset': 0x30, 'type': 'ro'}, + 'PACKET_64_BYTES_MSB': {'offset': 0x34, 'type': 'ro'}, + 'PACKET_65_127_BYTES_LSB': {'offset': 0x38, 'type': 'ro'}, + 'PACKET_65_127_BYTES_MSB': {'offset': 0x3C, 'type': 'ro'}, + 'PACKET_128_255_BYTES_LSB': {'offset': 0x40, 'type': 'ro'}, + 'PACKET_128_255_BYTES_MSB': {'offset': 0x44, 'type': 'ro'}, + 'PACKET_256_511_BYTES_LSB': {'offset': 0x48, 'type': 'ro'}, + 'PACKET_256_511_BYTES_MSB': {'offset': 0x4C, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_LSB': {'offset': 0x50, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_MSB': {'offset': 0x54, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_LSB': {'offset': 0x58, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_MSB': {'offset': 0x5C, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_LSB': {'offset': 0x60, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_MSB': {'offset': 0x64, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_LSB': {'offset': 0x68, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_MSB': {'offset': 0x6C, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_LSB': {'offset': 0x70, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_MSB': {'offset': 0x74, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_LSB': {'offset': 0x78, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_MSB': {'offset': 0x7C, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_LSB': {'offset': 0x80, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_MSB': {'offset': 0x84, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_LSB': {'offset': 0x88, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_MSB': {'offset': 0x8C, 'type': 'ro'}, + 'PACKET_LARGE': {'offset': 0x90, 'type': 'ro'}, + 'UNICAST_LSB': {'offset': 0x98, 'type': 'ro'}, + 'UNICAST_MSB': {'offset': 0x9C, 'type': 'ro'}, + 'MULTICAST_LSB': {'offset': 0xA0, 'type': 'ro'}, + 'MULTICAST_MSB': {'offset': 0xA4, 'type': 'ro'}, + 'BROADCAST_LSB': {'offset': 0xA8, 'type': 'ro'}, + 'BROADCAST_MSB': {'offset': 0xAC, 'type': 'ro'}, + 'VLAN_LSB': {'offset': 0xB0, 'type': 'ro'}, + 'VLAN_MSB': {'offset': 0xB4, 'type': 'ro'}, + 'PAUSE_LSB': {'offset': 0xB8, 'type': 'ro'}, + 'PAUSE_MSB': {'offset': 0xBC, 'type': 'ro'}, + 'USER_PAUSE_LSB': {'offset': 0xC0, 'type': 'ro'}, + 'USER_PAUSE_MSB': {'offset': 0xC4, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_LSB': {'offset': 0xC8, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_MSB': {'offset': 0xCC, 'type': 'ro'}, + 'ECC_CORRECTABLE_COUNT': {'offset': 0xD0, 'type': 'ro'}, + 'ECC_UNCORRECTABLE_COUNT': {'offset': 0xD8, 'type': 'ro'}, +} + + +rx_stats_base_reg = { + 'TOTAL_BYTES_LSB': {'offset': 0x00, 'type': 'ro'}, + 'TOTAL_BYTES_MSB': {'offset': 0x04, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_LSB': {'offset': 0x08, 'type': 'ro'}, + 'TOTAL_GOOD_BYTES_MSB': {'offset': 0x0C, 'type': 'ro'}, + 'TOTAL_PACKETS_LSB': {'offset': 0x10, 'type': 'ro'}, + 'TOTAL_PACKETS_MSB': {'offset': 0x14, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_LSB': {'offset': 0x18, 'type': 'ro'}, + 'TOTAL_GOOD_PACKETS_MSB': {'offset': 0x1C, 'type': 'ro'}, + 'PACKET_SMALL_LSB': {'offset': 0x20, 'type': 'ro'}, + 'PACKET_SMALL_MSB': {'offset': 0x24, 'type': 'ro'}, + 'BAD_CODE_COUNT_LSB': {'offset': 0x28, 'type': 'ro'}, + 'BAD_CODE_COUNT_MSB': {'offset': 0x2C, 'type': 'ro'}, + 'BAD_FCS_LSB': {'offset': 0x30, 'type': 'ro'}, + 'BAD_FCS_MSB': {'offset': 0x34, 'type': 'ro'}, + 'PACKET_BAD_FCS_LSB': {'offset': 0x38, 'type': 'ro'}, + 'PACKET_BAD_FCS_MSB': {'offset': 0x3C, 'type': 'ro'}, + 'STOMPED_FCS_LSB': {'offset': 0x40, 'type': 'ro'}, + 'STOMPED_FCS_MSB': {'offset': 0x44, 'type': 'ro'}, + 'TRUNCATED_LSB': {'offset': 0x48, 'type': 'ro'}, + 'TRUNCATED_MSB': {'offset': 0x4C, 'type': 'ro'}, + 'PACKET_64_BYTES_LSB': {'offset': 0x50, 'type': 'ro'}, + 'PACKET_64_BYTES_MSB': {'offset': 0x54, 'type': 'ro'}, + 'PACKET_65_127_BYTES_LSB': {'offset': 0x58, 'type': 'ro'}, + 'PACKET_65_127_BYTES_MSB': {'offset': 0x5C, 'type': 'ro'}, + 'PACKET_128_255_BYTES_LSB': {'offset': 0x60, 'type': 'ro'}, + 'PACKET_128_255_BYTES_MSB': {'offset': 0x64, 'type': 'ro'}, + 'PACKET_256_511_BYTES_LSB': {'offset': 0x68, 'type': 'ro'}, + 'PACKET_256_511_BYTES_MSB': {'offset': 0x6C, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_LSB': {'offset': 0x70, 'type': 'ro'}, + 'PACKET_512_1023_BYTES_MSB': {'offset': 0x74, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_LSB': {'offset': 0x78, 'type': 'ro'}, + 'PACKET_1024_1518_BYTES_MSB': {'offset': 0x7C, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_LSB': {'offset': 0x80, 'type': 'ro'}, + 'PACKET_1519_1522_BYTES_MSB': {'offset': 0x84, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_LSB': {'offset': 0x88, 'type': 'ro'}, + 'PACKET_1523_1548_BYTES_MSB': {'offset': 0x8C, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_LSB': {'offset': 0x90, 'type': 'ro'}, + 'PACKET_1549_2047_BYTES_MSB': {'offset': 0x94, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_LSB': {'offset': 0x98, 'type': 'ro'}, + 'PACKET_2048_4095_BYTES_MSB': {'offset': 0x9C, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_LSB': {'offset': 0xA0, 'type': 'ro'}, + 'PACKET_4096_8191_BYTES_MSB': {'offset': 0xA4, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_LSB': {'offset': 0xA8, 'type': 'ro'}, + 'PACKET_8192_9215_BYTES_MSB': {'offset': 0xAC, 'type': 'ro'}, + 'TOOLONG': {'offset': 0xB0, 'type': 'ro'}, + 'PACKET_LARGE': {'offset': 0xB8, 'type': 'ro'}, + 'JABBER': {'offset': 0xC0, 'type': 'ro'}, + 'OVERSIZE': {'offset': 0xC8, 'type': 'ro'}, + 'UNICAST_LSB': {'offset': 0xD0, 'type': 'ro'}, + 'UNICAST_MSB': {'offset': 0xD4, 'type': 'ro'}, + 'MULTICAST_LSB': {'offset': 0xD8, 'type': 'ro'}, + 'MULTICAST_MSB': {'offset': 0xDC, 'type': 'ro'}, + 'BROADCAST_LSB': {'offset': 0xE0, 'type': 'ro'}, + 'BROADCAST_MSB': {'offset': 0xE4, 'type': 'ro'}, + 'VLAN_LSB': {'offset': 0xE8, 'type': 'ro'}, + 'VLAN_MSB': {'offset': 0xEC, 'type': 'ro'}, + 'PAUSE_LSB': {'offset': 0xF0, 'type': 'ro'}, + 'PAUSE_MSB': {'offset': 0xF4, 'type': 'ro'}, + 'USER_PAUSE_LSB': {'offset': 0xF8, 'type': 'ro'}, + 'USER_PAUSE_MSB': {'offset': 0xFC, 'type': 'ro'}, + 'INRANGEERR_LSB': {'offset': 0x100, 'type': 'ro'}, + 'INRANGEERR_MSB': {'offset': 0x104, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_LSB': {'offset': 0x108, 'type': 'ro'}, + 'MAC_CYCLE_COUNT_MSB': {'offset': 0x10C, 'type': 'ro'}, +} diff --git a/linker/slashkit/resources/dcmac/driver/default_ip.py b/linker/slashkit/resources/dcmac/driver/default_ip.py new file mode 100644 index 00000000..5cc6bded --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/default_ip.py @@ -0,0 +1,77 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +from generic_mmio import GenericMMIO +from utils import rshift + + +def decode_control_register(value: int) -> dict: + cregister = {} + cregister['ap_start': bool(rshift(value))] + cregister['ap_done': bool(rshift(value, 1))] + cregister['ap_idle': bool(rshift(value, 2))] + cregister['ap_ready': bool(rshift(value, 3))] + cregister['ap_continue': bool(rshift(value, 4))] + cregister['auto_restart': bool(rshift(value, 7))] + return cregister + +cregs = { + "controlreg": {'offset': 0x0, 'type': 'rw', + 'fields': {'ap_start': {'start': 0, 'length': 1, 'default': 0, 'type': 'rw'}, + 'ap_done': {'start': 1, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_idle': {'start': 2, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_ready': {'start': 3, 'length': 1, 'default': 0, 'type': 'ro'}, + 'ap_continue': {'start': 4, 'length': 1, 'default': 0, 'type': 'rw'}, + 'auto_restart': {'start': 7, 'length': 1, 'default': 0, 'type': 'rw'} + } + }, + "globalintreg": {'offset': 0x4, 'type': 'rw'}, + "intenable": {'offset': 0x8, 'type': 'rw'}, + "intstatus": {'offset': 0x10, 'type': 'rw'}, +} + + +class DefaultIP(GenericMMIO): + """Generic IP Driver""" + _controlreg = 0x00 + _globalintreg = 0x04 + _intenable = 0x08 + _intstatus = 0x10 + + def __init__(self, device: str = 'e2', resource: int = 2, + base_offset: int = 0x0, debug: bool = False, + regs: dict = None): + super().__init__(device, resource, base_offset, debug) + self.registers = cregs if regs is None else regs + + def start(self, value: int = 1): + """Start IP once""" + self.write(self._controlreg, value) + + def autostart(self): + """Autostart IP""" + self.start(0x81) + + def controlreg(self) -> dict: + value = self.read(self._controlreg) + cregisters = decode_control_register(value) + print(cregisters) + return cregisters + + def global_interrupt(self): + value = self.read(self._globalintreg) + gintenable = {'global_interrupt_enable': bool(rshift(value))} + print(gintenable) + return gintenable + + def interrupt_enable(self): + value = self.read(self._intenable) + intenable = {'interrupt_enable': bool(rshift(value))} + print(intenable) + return intenable + + def interrupt_status(self): + value = self.read(self._intstatus) + intstatus = {'interrupt_status': bool(rshift(value))} + print(intstatus) + return intstatus diff --git a/linker/slashkit/resources/dcmac/driver/generic_mmio.py b/linker/slashkit/resources/dcmac/driver/generic_mmio.py new file mode 100644 index 00000000..8c94f53f --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/generic_mmio.py @@ -0,0 +1,70 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from pcie_bar import PCIeMapBar +from utils import int_types, hex_or_int, add_common_args + + +class GenericMMIO: + def __init__(self, device: str = 'e2', resource: int = 2, + base_offset: int = 0x0, debug: bool = False): + self._base_offset = base_offset + self._pciemmio = PCIeMapBar(device, resource, debug=debug) + self._pciemmio.open() + if debug: + print(f"Base address: {hex(self._base_offset)}") + + def write(self, reg_offset: int = 0, value: int = 0): + if not isinstance(value, int_types): + raise ValueError(f"'{value=}' is not a {int_types} type") + self._pciemmio.write(self._base_offset + reg_offset, value) + + def read(self, reg_offset: int = 0): + return self._pciemmio.read(self._base_offset + reg_offset) + + def read_long(self, offset) -> int: + """Read 8 bytes from BAR 'offset'""" + val_low = self.read(offset) + val_high = self.read(offset + 4) + return int((val_high << 32) + val_low) + + def __del__(self): + self._pciemmio.close() + + @property + def base_address(self): + return self._base_offset + + +def main(args): + obj = GenericMMIO(args.dev, base_offset=args.baseoffset) + + if args.write: + obj.write(args.offset, args.value) + + if args.read: + val = obj.read(args.offset) + print(f'Offset: 0x{obj._base_offset + args.offset:X}, value=0x{val:X}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + + parser.add_argument('-b', '--baseoffset', type=hex_or_int, + help='Base Offset', required=True) + + parser.add_argument('-o', '--offset', type=hex_or_int, + help='Offset', required=True) + + parser.add_argument('-r', '--read', action='store_true', + help='Read') + parser.add_argument('-w', '--write', action='store_true', + help='Write') + parser.add_argument('-v', '--value', type=hex_or_int, + help='Value to be written', default=0) + + parser = add_common_args(parser, False) + args = parser.parse_args() + main(args) diff --git a/linker/slashkit/resources/dcmac/driver/gpio_monitor.py b/linker/slashkit/resources/dcmac/driver/gpio_monitor.py new file mode 100644 index 00000000..4aceecdc --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/gpio_monitor.py @@ -0,0 +1,66 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from axigpio_mmio import AxiGpioMMIO +from utils import add_common_args, get_ip_offset + + +shift_map = { + 'gt0_tx_reset_done': {'shift': 0, 'bits': 4}, + 'gt1_tx_reset_done': {'shift': 4, 'bits': 4}, + 'gt0_rx_reset_done': {'shift': 8, 'bits': 4}, + 'gt1_rx_reset_done': {'shift': 12, 'bits': 4}, + 'gtpowergood': {'shift': 16, 'bits': 1}, + 'dual_dcmac': {'shift': 18, 'bits': 1}, +} + + +def _get_shift_and_mask(key: str) -> tuple[int, int]: + """Return the shift and mask give the key""" + map = shift_map[key] + return map['shift'], (1 << map['bits']) - 1 + + +class AxiGPIOMonitor(AxiGpioMMIO): + + def __init__(self, device: str = 'e2', resource: int = 2, + base_offset: int = 0x0, gpio_index: int = 0): + self._gpio_index = gpio_index + super().__init__(device, resource, base_offset) + + def _get(self, key: str, gpio: int = 0): + shift, mask = _get_shift_and_mask(key) + return (self.read(gpio) >> shift) & mask + + def _create_property(key: str, gpio: int = 0): + """Create property getter and setter for given key.""" + return property( + lambda self: self._get(key, gpio) + ) + + gt0_tx_reset_done = _create_property('gt0_tx_reset_done') + gt1_tx_reset_done = _create_property('gt1_tx_reset_done') + gt0_rx_reset_done = _create_property('gt0_rx_reset_done') + gt1_rx_reset_done = _create_property('gt1_rx_reset_done') + gtpowergood = _create_property('gtpowergood') + dual_dcmac = _create_property('dual_dcmac') + + +def main(args): + offset = get_ip_offset(0x204_0200, args.dcmac) + obj = AxiGPIOMonitor(args.dev, base_offset=offset, gpio_index=0) + + print(f'{obj.gt0_tx_reset_done=}') + print(f'{obj.gt0_rx_reset_done=}') + print(f'{obj.gt1_tx_reset_done=}') + print(f'{obj.gt1_rx_reset_done=}') + print(f'{obj.gtpowergood=}') + del obj + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser = add_common_args(parser) + + main(parser.parse_args()) diff --git a/linker/slashkit/resources/dcmac/driver/netlayer_regs.py b/linker/slashkit/resources/dcmac/driver/netlayer_regs.py new file mode 100644 index 00000000..9a94003a --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/netlayer_regs.py @@ -0,0 +1,58 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +nl_regs = { + "mac_address": {'offset': 0x0010, 'size': 8, 'type': 'rw'}, + "ip_address": {'offset': 0x0018, 'size': 4, 'type': 'rw'}, + "gateway": {'offset': 0x001C, 'size': 4, 'type': 'rw'}, + "ip_mask": {'offset': 0x0020, 'size': 4, 'type': 'rw'}, + "eth_in_cycles": {'offset': 0x0400, 'size': 8, 'type': 'ro'}, + "eth_in_bytes": {'offset': 0x0408, 'size': 8, 'type': 'ro'}, + "eth_in_packets": {'offset': 0x0410, 'size': 8, 'type': 'ro'}, + "pkth_in_cycles": {'offset': 0x0418, 'size': 8, 'type': 'ro'}, + "pkth_in_bytes": {'offset': 0x0420, 'size': 8, 'type': 'ro'}, + "pkth_in_packets": {'offset': 0x0428, 'size': 8, 'type': 'ro'}, + "arp_in_cycles": {'offset': 0x0430, 'size': 8, 'type': 'ro'}, + "arp_in_bytes": {'offset': 0x0438, 'size': 8, 'type': 'ro'}, + "arp_in_packets": {'offset': 0x0440, 'size': 8, 'type': 'ro'}, + "arp_out_cycles": {'offset': 0x0448, 'size': 8, 'type': 'ro'}, + "arp_out_bytes": {'offset': 0x0450, 'size': 8, 'type': 'ro'}, + "arp_out_packets": {'offset': 0x0458, 'size': 8, 'type': 'ro'}, + "icmp_in_cycles": {'offset': 0x0460, 'size': 8, 'type': 'ro'}, + "icmp_in_bytes": {'offset': 0x0468, 'size': 8, 'type': 'ro'}, + "icmp_in_packets": {'offset': 0x0470, 'size': 8, 'type': 'ro'}, + "icmp_out_cycles": {'offset': 0x0478, 'size': 8, 'type': 'ro'}, + "icmp_out_bytes": {'offset': 0x0480, 'size': 8, 'type': 'ro'}, + "icmp_out_packets": {'offset': 0x0488, 'size': 8, 'type': 'ro'}, + "ethhi_out_cycles": {'offset': 0x0490, 'size': 8, 'type': 'ro'}, + "ethhi_out_bytes": {'offset': 0x0498, 'size': 8, 'type': 'ro'}, + "ethhi_out_packets": {'offset': 0x04A0, 'size': 8, 'type': 'ro'}, + "eth_out_cycles": {'offset': 0x04A8, 'size': 8, 'type': 'ro'}, + "eth_out_bytes": {'offset': 0x04B0, 'size': 8, 'type': 'ro'}, + "eth_out_packets": {'offset': 0x04B8, 'size': 8, 'type': 'ro'}, + "udp_in_cycles": {'offset': 0x04C0, 'size': 8, 'type': 'ro'}, + "udp_in_bytes": {'offset': 0x04C8, 'size': 8, 'type': 'ro'}, + "udp_in_packets": {'offset': 0x04D0, 'size': 8, 'type': 'ro'}, + "app_out_cycles": {'offset': 0x04D8, 'size': 8, 'type': 'ro'}, + "app_out_bytes": {'offset': 0x04E0, 'size': 8, 'type': 'ro'}, + "app_out_packets": {'offset': 0x04E8, 'size': 8, 'type': 'ro'}, + "udp_out_cycles": {'offset': 0x04F0, 'size': 8, 'type': 'ro'}, + "udp_out_bytes": {'offset': 0x04F8, 'size': 8, 'type': 'ro'}, + "udp_out_packets": {'offset': 0x0500, 'size': 8, 'type': 'ro'}, + "app_in_cycles": {'offset': 0x0508, 'size': 8, 'type': 'ro'}, + "app_in_bytes": {'offset': 0x0510, 'size': 8, 'type': 'ro'}, + "app_in_packets": {'offset': 0x0518, 'size': 8, 'type': 'ro'}, + "debug_reset_counters": {'offset': 0x05F0, 'size': 4, 'type': 'rw'}, + "frequency": {'offset': 0x05F4, 'size': 4, 'type': 'ro'}, + "probes_ports": {'offset': 0x05F8, 'size': 4, 'type': 'ro'}, + "probes_mode": {'offset': 0x05FC, 'size': 4, 'type': 'ro'}, + "udp_number_sockets": {'offset': 0x0810, 'size': 4, 'type': 'ro'}, + "udp_theirIP_offset": {'offset': 0x0820, 'size': 4, 'type': 'rw'}, + "udp_theirPort_offset": {'offset': 0x08A0, 'size': 4, 'type': 'rw'}, + "udp_myPort_offset": {'offset': 0x0920, 'size': 4, 'type': 'rw'}, + "udp_valid_offset": {'offset': 0x09A0, 'size': 4, 'type': 'rw'}, + "arp_discovery": {'offset': 0x1010, 'size': 4, 'type': 'rw'}, + "arp_valid_offset": {'offset': 0x1100, 'size': 4, 'type': 'rw'}, + "arp_ip_addr_offset": {'offset': 0x1400, 'size': 4, 'type': 'rw'}, + "arp_mac_addr_offset": {'offset': 0x1800, 'size': 4, 'type': 'rw'}, +} \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/driver/network_end2end_test.py b/linker/slashkit/resources/dcmac/driver/network_end2end_test.py new file mode 100644 index 00000000..6c56e872 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/network_end2end_test.py @@ -0,0 +1,128 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import time +from dcmac_init import dcmac_logic_init +from dcmac_mmio import DCMAC +from utils import add_common_args, get_ip_offset +from udp_utils import NetworkLayer +from trafficgen import TrafficGenerator + +"""This file aims at doing a test of the Ethernet or UDP layer between two interfaces in +board, interface 0 and 2. It will initialize the DCMAC and then setup the +interfaces IP, MAC addresses as well as the UDP socket table. +""" + +DCMAC_BASEADDR = 0x200_0000 +TRAFFICGEN_BASEADDR = 0x400_2000 +NL_BASEADDR = 0x400_0000 + + +class ArgsClass: + dcmac = 0 + init = False + print = 1 + dev = None + verbose = 1 + loopback = None + keep_alive = 0 + align_rx = 1 + traffic_test = 0 + + +def main(args): + """Initialize DCMAC in each interface""" + init_args = ArgsClass() + init_args.dev = args.dev + """Init DCMAC 0""" + dcmac_logic_init(init_args) + + """Init DCMAC 0""" + init_args.dcmac = 1 + dcmac_logic_init(init_args) + + # reset TX first then RX + if args.udp: + """Basic network layer config""" + nl0 = NetworkLayer(args.dev, base_offset=get_ip_offset(NL_BASEADDR, 0)) + nl1 = NetworkLayer(args.dev, base_offset=get_ip_offset(NL_BASEADDR, 2)) + + print(f'nl0._base_offset=0x{nl0._base_offset:0X}') + print(f'nl1._base_offset=0x{nl1._base_offset:0X}') + + ip_if0 = '192.168.10.5' + ip_if1 = '192.168.10.6' + nl0.set_ip_address(ip_if0) + nl1.set_ip_address(ip_if1) + nl0.set_mac_address('b8:3f:d2:24:51:c0') + nl1.set_mac_address('b8:3f:d2:24:51:c1') + + print(f'NL0: {nl0.get_network_info()}') + print(f'NL1: {nl1.get_network_info()}') + + """Reset debug stats""" + nl0.reset_debug_stats() + nl1.reset_debug_stats() + + """Start ARP Discovery""" + nl0.arp_discovery() + time.sleep(1) + nl1.arp_discovery() + time.sleep(1) + + print(f'NL0 ARP Table: {nl0.get_arp_table(12, verbose=1)}') + print(f'NL1 ARP Table: {nl1.get_arp_table(12, verbose=1)}') + + """Populate socket table""" + port_tx = 50446 + port_rx = 60133 + nl0.sockets[0] = (ip_if1, port_tx, port_rx, True) + nl0.populate_socket_table(debug=True) + nl1.sockets[0] = (ip_if0, port_rx, port_tx, True) + nl1.populate_socket_table(debug=True) + + """Now we can generate some traffic""" + + tgen0 = TrafficGenerator(args.dev, resource=0, base_offset=0x004C_0000) + tgen1 = TrafficGenerator(args.dev, resource=0, base_offset=0x0050_0000) + + tgen0.flits = 22 + tgen0.dest = 0 + tgen0.start() + time.sleep(1) + + tgen1.flits = 22 + tgen1.dest = 0 + tgen1.start() + time.sleep(1) + + if args.udp: + """Get Statistics""" + print('\n') + nl0.get_debug_stats(True) + print('\n') + nl1.get_debug_stats(True) + print('\n') + + dcmac0 = DCMAC(args.dev, base_offset=get_ip_offset(DCMAC_BASEADDR, 0)) + dcmac1 = DCMAC(args.dev, base_offset=get_ip_offset(DCMAC_BASEADDR, 1)) + + print(f'{dcmac0.tx_stats(verbose=1)=}') + print(f'{dcmac0.rx_stats(verbose=1)=}') + + print(f'{dcmac1.tx_stats(verbose=1)=}') + print(f'{dcmac1.rx_stats(verbose=1)=}') + + if args.udp: + print(f'{nl0.get_freq=}') + print(f'{nl1.get_freq=}') + + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument('-u', '--udp', action='store_true', + help='Use UDP logic') + parser = add_common_args(parser, verbose=True) + args = parser.parse_args() + main(args) diff --git a/linker/slashkit/resources/dcmac/driver/pcie_bar.py b/linker/slashkit/resources/dcmac/driver/pcie_bar.py new file mode 100644 index 00000000..6eb23090 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/pcie_bar.py @@ -0,0 +1,62 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import mmap +from warnings import warn +import numpy as np +BAR_SIZE = 128 * 1024 * 1024 # 256 MB + + +def _get_bar_path(dev, resource: int = 2, debug=True): + """Generate BAR path based on the PCIe Bus ID""" + dev_path = f"/sys/bus/pci/devices/0000:{dev}:00.2/resource{resource}" + if debug: + print(f"Using BDF: {dev_path}") + return dev_path + + +class PCIeMapBar: + """Wrapper class to allows MMIO read and write operations from PCIe BAR""" + def __init__(self, device: str = 'e2', resource: int = 2, + barsize: int = BAR_SIZE, debug: bool = True): + self._bar = None + self._barpath = _get_bar_path(device, resource, debug) + self._barsize = barsize + + def open(self): + """Open BAR""" + with open(self._barpath, "r+b") as f: + self._bar = mmap.mmap(f.fileno(), self._barsize, mmap.MAP_SHARED, + mmap.PROT_READ | mmap.PROT_WRITE) + self.mem = np.frombuffer(self._bar, np.uint32, (self._barsize+3) >> 2) + + def close(self): + """Close BAR""" + if self._bar is not None: + del self.mem + self._bar.close() + self._bar = None + + def read(self, byte_offset: int) -> int: + """Read 4 bytes from BAR 'byte_offset'""" + if byte_offset & 0x3: + warn(f"Byte offset {byte_offset} is not aligned to 32-bit words." + + "Aligning to previous 32-bit boundary") + if self._bar is None: + raise RuntimeError('BAR is not opened') + + return int(self.mem[byte_offset >> 2]) + + def write(self, byte_offset: int, value: int): + """Write 4 bytes to BAR 'byte_offset'""" + if byte_offset & 0x3: + warn(f"Byte offset {byte_offset} is not aligned to 32-bit words." + + "Aligning to previous 32-bit boundary") + if self._bar is None: + raise RuntimeError('BAR is not opened') + value_32 = value & 0xFFFFFFFF + if value_32 != value: + warn("Trying to write a value larger than 32 bits to the PCIe " + + "device, truncating to 32 bits") + + self.mem[byte_offset >> 2] = value_32 diff --git a/linker/slashkit/resources/dcmac/driver/requirements.txt b/linker/slashkit/resources/dcmac/driver/requirements.txt new file mode 100644 index 00000000..8b48365f --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/requirements.txt @@ -0,0 +1,3 @@ +numpy +tabulate +IPython diff --git a/linker/slashkit/resources/dcmac/driver/trafficgen.py b/linker/slashkit/resources/dcmac/driver/trafficgen.py new file mode 100644 index 00000000..32fc0539 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/trafficgen.py @@ -0,0 +1,63 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +from default_ip import DefaultIP +from utils import add_common_args, get_ip_offset + + +class TrafficGenerator(DefaultIP): + """Specialization to support TrafficGenerator IP""" + + _flits_offset = 0x10 + _dest_offset = 0x18 + + @property + def dest(self): + value = self.read(self._dest_offset) + return value + + @dest.setter + def dest(self, value: int): + if not isinstance(value, int): + raise ValueError(f"{value=} must be an integer") + elif value < 0: + raise ValueError(f"{value=} must be a positive integer") + + self.write(self._dest_offset, value) + + @property + def flits(self): + value = self.read(self._flits_offset) + return value + + @flits.setter + def flits(self, value: int): + if not isinstance(value, int): + raise ValueError(f"{value=} must be an integer") + elif value < 1: + raise ValueError(f"{value=} must be bigger than 0") + + self.write(self._flits_offset, value) + + +def main(args): + intf = 0 + offset = get_ip_offset(0x400_0000, args.dcmac*2 +intf) + tgen = TrafficGenerator(args.dev, base_offset=offset) + + tgen.flits = args.flits + tgen.dest = 0 + tgen.start() + del tgen + + +if __name__ == '__main__': + parser = argparse.ArgumentParser() + parser.add_argument('-f', '--flits', type=int, default=10, + help='Number of 64-Byte flits', required=False) + + parser = add_common_args(parser) + args = parser.parse_args() + + main(args) diff --git a/linker/slashkit/resources/dcmac/driver/udp_utils.py b/linker/slashkit/resources/dcmac/driver/udp_utils.py new file mode 100644 index 00000000..6556acdf --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/udp_utils.py @@ -0,0 +1,637 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import ipaddress +import numpy as np +from enum import Enum +from tabulate import tabulate +from IPython.display import JSON +from default_ip import DefaultIP +from netlayer_regs import nl_regs + + +def _byte_ordering_endianess(num, length=4): + """ + Convert from little endian to big endian and vice versa + + Parameters + ---------- + num: int + input number + + length: + number of bytes of the input number + + Returns + ------- + An integer with the endianness changed with respect to input number + + """ + if not isinstance(num, int): + raise ValueError("num must be an integer") + + if not isinstance(length, int): + raise ValueError("length must be an positive integer") + elif length < 0: + raise ValueError("length cannot be negative") + + aux = 0 + for i in range(length): + byte_index = num >> ((length - 1 - i) * 8) & 0xFF + aux += byte_index << (i * 8) + return aux + + +class NetworkLayer(DefaultIP): + """This class wraps the common function of the Network Layer IP + + """ + + bindto = ["xilinx.com:kernel:networklayer:1.0"] + + _socketType = np.dtype( + [ + ("theirIP", str, 16), + ("theirPort", np.uint16), + ("myPort", np.uint16), + ("valid", bool), + ] + ) + + def __init__(self, device: str = 'e2', resource: int = 2, + base_offset: int = 0x0, debug: bool = False): + super().__init__(device, resource, base_offset, debug) + self.registers = nl_regs + self.sockets = np.zeros(16, dtype=self._socketType) + self.freq = None + + def populate_socket_table(self, debug: bool = False): + """ + Populate a socket table + + Optionals + --------- + debug: bool + If enables read the current status of the UDP Table + + Returns + ------- + If debug is enable read the current status of the UDP Table + + """ + + theirIP_offset = self.registers['udp_theirIP_offset']['offset'] + theirPort_offset = self.registers['udp_theirPort_offset']['offset'] + udp_myPort_offset = self.registers['udp_myPort_offset']['offset'] + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.read(self.registers['udp_number_sockets']['offset'])) + + if numSocketsHW < len(self.sockets): + raise Exception(f"Socket list length ({len(self.sockets)}) is " + "bigger than the number of sockets in hardware " + f"({numSocketsHW})") + + # Iterate over the socket object + for i in range(numSocketsHW): + ti_offset = theirIP_offset + i * 8 + tp_offset = theirPort_offset + i * 8 + mp_offset = udp_myPort_offset + i * 8 + v_offset = udp_valid_offset + i * 8 + + theirIP = 0 + if self.sockets[i]["theirIP"]: + theirIP = int(ipaddress.IPv4Address(self.sockets[i] + ["theirIP"])) + + self.write(ti_offset, theirIP) + self.write(tp_offset, int(self.sockets[i]["theirPort"])) + self.write(mp_offset, int(self.sockets[i]["myPort"])) + self.write(v_offset, int(self.sockets[i]["valid"])) + + if debug: + return self.get_socket_table() + + def get_socket_table(self) -> dict: + """ Reads the socket table + + Returns + ------- + Returns socket table + """ + + theirIP_offset = self.registers['udp_theirIP_offset']['offset'] + theirPort_offset = self.registers['udp_theirPort_offset']['offset'] + udp_myPort_offset = self.registers['udp_myPort_offset']['offset'] + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.read(self.registers['udp_number_sockets']['offset'])) + + socket_dict = dict() + socket_dict['Number of Sockets'] = numSocketsHW + socket_dict['socket'] = dict() + # Iterate over all the UDP table + for i in range(numSocketsHW): + ti_offset = theirIP_offset + i * 8 + tp_offset = theirPort_offset + i * 8 + mp_offset = udp_myPort_offset + i * 8 + v_offset = udp_valid_offset + i * 8 + isvalid = self.read(v_offset) + if isvalid: + ti = self.read(ti_offset) + tp = self.read(tp_offset) + mp = self.read(mp_offset) + socket_dict['socket'][i] = dict() + socket_dict['socket'][i]['theirIP'] = \ + str(ipaddress.IPv4Address(ti)) + socket_dict['socket'][i]['theirPort'] = tp + socket_dict['socket'][i]['myPort'] = mp + + print(f'{socket_dict=}') + return JSON(socket_dict, rootname='socket_table') + + def invalidate_socket_table(self): + """ Clear the Socket table """ + + udp_valid_offset = self.registers['udp_valid_offset']['offset'] + numSocketsHW = int(self.registers['udp_number_sockets']) + for i in range(numSocketsHW): + self.write(int(udp_valid_offset + i * 8), 0) + + def get_arp_table(self, num_entries: int=256, verbose: int=0) -> dict: + """Read the ARP table from the FPGA return a dict + + Parameters + ---------- + Optionals + --------- + num_entries: int + number of entries in the table to be consider when printing + + Returns + ------- + Prints the content of valid entries in the ARP in a friendly way + """ + + if not isinstance(num_entries, int): + raise ValueError("Number of entries must be integer.") + elif num_entries < 0: + raise ValueError("Number of entries cannot be negative.") + elif num_entries > 256: + raise ValueError("Number of entries cannot be bigger than 256.") + + mac_addr_offset = self.registers['arp_mac_addr_offset']['offset'] + ip_addr_offset = self.registers['arp_ip_addr_offset']['offset'] + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + arptable = dict() + + valid_entry = None + for i in range(num_entries): + if (i % 4) == 0: + valid_entry = self.read(valid_addr_offset + (i // 4) * 4) + + isvalid = (valid_entry >> ((i % 4) * 8)) & 0x1 + if isvalid or verbose > 0: + mac_lsb = self.read(mac_addr_offset + (i * 2 * 4)) + mac_msb = self.read(mac_addr_offset + ((i * 2 + 1) * 4)) + ip_addr = self.read(ip_addr_offset + (i * 4)) + mac_addr = (2 ** 32) * mac_msb + mac_lsb + mac_hex = "{:012x}".format( + _byte_ordering_endianess(mac_addr, 6)) + mac_str = ":".join( + mac_hex[i: i + 2] for i in range(0, len(mac_hex), 2) + ) + ip_addr_print = _byte_ordering_endianess(ip_addr) + arptable[i] = { + "MAC address": mac_str, + "IP address": str(ipaddress.IPv4Address(ip_addr_print)) + } + + headers = ["Index", "MAC Address", "IP Address"] + table_data = [] + for key, value in arptable.items(): + mac_address = value["MAC address"] + ip_address = value["IP address"] + table_data.append([key, mac_address, ip_address]) + + print(tabulate(table_data, headers=headers, tablefmt="pretty")) + #return JSON(arptable, rootname='ARP Table') + + def write_arp_entry(self, mac: str, ip: str): + """ + Add an entry to the ARP table + + Parameters + ---------- + mac: str + MAC address in the format XX:XX:XX:XX:XX:XX + ip: str + IP address in the format XXX.XXX.XXX.XXX + + Note, VNx requires all IPs in the ARP table to be in the same + /24 subnet (mask 255.255.255.0) as the IP assigned to the FPGA port. + + There are 256 entries in the ARP table, one for each possible IP + in the subnet, the least significant 8 bits of the IP are used to + index into the ARP table. + """ + + if not isinstance(mac, str): + raise ValueError("MAC address must be a string.") + elif not isinstance(ip, str): + raise ValueError("IP address must be a string.") + + mac_int = int("0x{}".format(mac.replace(":", "")), 16) + big_mac_int = _byte_ordering_endianess(mac_int, 6) + mac_msb = (big_mac_int >> 32) & 0xFFFFFFFF + mac_lsb = big_mac_int & 0xFFFFFFFF + + ip_int = int(ipaddress.IPv4Address(ip)) + big_ip_int = _byte_ordering_endianess(ip_int, 4) + + mac_addr_offset = self.registers['arp_mac_addr_offset']['offset'] + ip_addr_offset = self.registers['arp_ip_addr_offset']['offset'] + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + i = ip_int % 256 + self.write(ip_addr_offset + (i * 4), big_ip_int) + self.write(mac_addr_offset + (i * 2 * 4), mac_lsb) + self.write(mac_addr_offset + ((i * 2 + 1) * 4), mac_msb) + + # Valid + old_valid_entry = self.read(valid_addr_offset + (i // 4) * 4) + this_valid = 1 << ((i % 4) * 8) + self.write(valid_addr_offset + (i // 4) * 4, + old_valid_entry | this_valid) + + def invalidate_arp_table(self): + """ + Clear the ARP table + """ + valid_addr_offset = self.registers['arp_valid_offset']['offset'] + + for i in range(0, 256//4, 4): + self.write(valid_addr_offset + i, 0) + + def arp_discovery(self): + """ + Launch ARP discovery + """ + + # The ARP discovery is trigger with the rising edge + self.write(self.registers['arp_discovery']['offset'], 0) + self.write(self.registers['arp_discovery']['offset'], 1) + self.write(self.registers['arp_discovery']['offset'], 0) + + def get_network_info(self) -> dict: + """Returns a dictionary with the current configuration + """ + mac_addr = int(self.read_long(self.registers['mac_address']['offset'])) + ip_addr = int(self.read(self.registers['ip_address']['offset'])) + ip_gw = int(self.read(self.registers['gateway']['offset'])) + ip_mask = int(self.read(self.registers['ip_mask']['offset'])) + + mac_hex = "{:012x}".format(mac_addr) + mac_str = ":".join(mac_hex[i: i + 2] + for i in range(0, len(mac_hex), 2)) + + config = { + "HWaddr": mac_str, + "inet addr": str(ipaddress.IPv4Address(ip_addr)), + "gateway addr": str(ipaddress.IPv4Address(ip_gw)), + "Mask": str(ipaddress.IPv4Address(ip_mask)), + } + print(f'{config=}') + return JSON(config, rootname='Network Information') + + def set_ip_address(self, ipaddrsrt, gwaddr="None", debug=False): + """ + Update IP address as well as least significant octet of the + MAC address with the least significant octet of the IP address + + Parameters + ---------- + ipaddrsrt : string + New IP address + + gwaddr : string + New IP gateway address, if not defined a default gateway is used + debug: bool + if enable it will return the current configuration + + Returns + ------- + Current interface configuration only if debug == True + + """ + + if not isinstance(ipaddrsrt, str): + raise ValueError("ipaddrsrt must be an string type") + + if not isinstance(gwaddr, str): + raise ValueError("gwaddr must be an string type") + + if not isinstance(debug, bool): + raise ValueError("debug must be a bool type") + + ipaddr = int(ipaddress.IPv4Address(ipaddrsrt)) + self.write(self.registers['ip_address']['offset'], ipaddr) + if gwaddr == "None": + self.write(self.registers['gateway']['offset'], (ipaddr & 0xFFFFFF00) + 1) + else: + self.write(self.registers['gateway']['offset'], int(ipaddress.IPv4Address(gwaddr))) + + + #currentMAC = int(self.read(self.registers['mac_address']['offset'])) + #newMAC = (currentMAC & 0xFFFFFFFFF00) + (ipaddr & 0xFF) + #self.write(self.registers['mac_address']['offset'], newMAC) + + if debug: + return self.get_network_info() + + def set_mac_address(self, mac_addr: str): + """ Update the MAC address of the interface + + Parameters + ---------- + mac_addr : str + MAC address in the format XX:XX:XX:XX:XX:XX + """ + if not isinstance(mac_addr, str): + raise ValueError("MAC address must be a string.") + + mac_int = int("0x{}".format(mac_addr.replace(":", "")), 16) + mac_low = mac_int & 0xFFFFFFFF + mac_high = (mac_int >> 32) & 0xFFFFFFFF + self.write(self.registers['mac_address']['offset'], mac_low) + self.write(self.registers['mac_address']['offset'] + 4, mac_high) + + def reset_debug_stats(self) -> None: + """Reset debug probes + """ + + self.write(self.registers['debug_reset_counters']['offset'], 1) + + def get_debug_stats(self, debug: bool=True) -> dict: + """Return a dictionary with the value of the Network Layer probes""" + + rmap = self.registers + probes = dict() + probes["tx_path"] = dict() + probes["rx_path"] = dict() + + probes["rx_path"] = { + "ethernet": { + "packets": int(self.read(rmap['eth_in_packets']['offset'])), + "bytes": int(self.read(rmap['eth_in_bytes']['offset'])), + "cycles": int(self.read(rmap['eth_in_cycles']['offset'])) + }, + "packet_handler": { + "packets": int(self.read(rmap['pkth_in_packets']['offset'])), + "bytes": int(self.read(rmap['pkth_in_bytes']['offset'])), + "cycles": int(self.read(rmap['pkth_in_cycles']['offset'])) + }, + "arp": { + "packets": int(self.read(rmap['arp_in_packets']['offset'])), + "bytes": int(self.read(rmap['arp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['arp_in_cycles']['offset'])) + }, + "icmp": { + "packets": int(self.read(rmap['icmp_in_packets']['offset'])), + "bytes": int(self.read(rmap['icmp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['icmp_in_cycles']['offset'])) + }, + "udp": { + "packets": int(self.read(rmap['udp_in_packets']['offset'])), + "bytes": int(self.read(rmap['udp_in_bytes']['offset'])), + "cycles": int(self.read(rmap['udp_in_cycles']['offset'])) + }, + "app": { + "packets": int(self.read(rmap['app_in_packets']['offset'])), + "bytes": int(self.read(rmap['app_in_bytes']['offset'])), + "cycles": int(self.read(rmap['app_in_cycles']['offset'])) + } + } + + probes['tx_path'] = { + "arp": { + "packets": int(self.read(rmap['arp_out_packets']['offset'])), + "bytes": int(self.read(rmap['arp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['arp_out_cycles']['offset'])) + }, + "icmp": { + "packets": int(self.read(rmap['icmp_out_packets']['offset'])), + "bytes": int(self.read(rmap['icmp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['icmp_out_cycles']['offset'])) + }, + "ethernet_header_inserter": { + "packets": int(self.read(rmap['ethhi_out_packets']['offset'])), + "bytes": int(self.read(rmap['ethhi_out_bytes']['offset'])), + "cycles": int(self.read(rmap['ethhi_out_cycles']['offset'])) + }, + "ethernet": { + "packets": int(self.read(rmap['eth_out_packets']['offset'])), + "bytes": int(self.read(rmap['eth_out_bytes']['offset'])), + "cycles": int(self.read(rmap['eth_out_cycles']['offset'])) + }, + "udp": { + "packets": int(self.read(rmap['udp_out_packets']['offset'])), + "bytes": int(self.read(rmap['udp_out_bytes']['offset'])), + "cycles": int(self.read(rmap['udp_out_cycles']['offset'])) + }, + "app": { + "packets": int(self.read(rmap['app_out_packets']['offset'])), + "bytes": int(self.read(rmap['app_out_bytes']['offset'])), + "cycles": int(self.read(rmap['app_out_cycles']['offset'])) + } + } + + for path, stats in probes.items(): + table_data = [] + for protocol, v in stats.items(): + tot_bytes = v['bytes'] + tot_cycles = v['cycles'] + thr_bs = 0 + if tot_cycles != 0: + tot_time = (1 / (390.625 * 10 ** 6)) * tot_cycles + thr_bs = (tot_bytes * 8) / tot_time + table_data.append([protocol, v['packets'], tot_bytes, tot_cycles, f'{thr_bs/10**6:.2f}']) + + print(f"Debug {path} probes") + print(tabulate(table_data, headers=[f'Probe {path}', 'Packets', 'Bytes', 'Cycles', 'BW (Mb/s)'], tablefmt='pretty')) + + return JSON(probes, rootname='debug_probes') + + @property + def get_freq(self): + return int(self.read(self.registers['frequency']['offset'])) + + +class TgMode(Enum): + """Supported Traffic generator Modes""" + PRODUCER = 0 + LATENCY = 1 + LOOPBACK = 2 + CONSUMER = 3 + + +class TrafficGenerator(DefaultIP): + """ This class wraps the common function of the Traffic Generator IP + """ + + bindto = ["xilinx.com:kernel:traffic_generator:1.0"] + + def __init__(self, description): + super().__init__(description=description) + self.start = self._call = self._start_sw = self.start_sw = self.call = self._start_ert + self.freq = None + + def _start_ert(self, mode: TgMode, dest: int=0, packets: int=None, + beats: int=None, tbwp: int=None): + """Starts the Traffic generator + + Parameters + ---------- + mode: TgMode + Operation mode + dest: int + Index in the socket table + + Optional + -------- + packets: int + Number of packets + num_beats: int + Number of transactions per piece of payload + tbwp: + Clock ticks between two consecutive payload packets + """ + if mode == TgMode.PRODUCER or mode == TgMode.LATENCY: + if packets is None: + raise RuntimeError("packets must be specified when mode is {}" + .format(mode)) + elif beats is None: + raise RuntimeError("beats must be specified when mode is {}" + .format(mode)) + elif tbwp is None: + raise RuntimeError("tbwp must be specified when mode is {}" + .format(mode)) + + self.register_map.number_packets = packets + self.register_map.number_beats = beats + self.register_map.time_between_packets = tbwp + + self.register_map.mode = int(mode.value) + self.register_map.dest_id = dest + self.register_map.CTRL.AP_START = 1 + + def reset_fsm(self): + """Reset internal FSM""" + self.register_map.reset_fsm = 1 + + def compute_app_throughput(self, direction: str="rx") -> float: + """ + Read the application monitoring registers and compute + throughput, it also returns other useful information + + Parameters + ---------- + direction: string + 'rx' or 'tx' + + Returns + ------- + Total number of packets seen by the monitoring probe, + throughput and total time + """ + + if direction not in ["rx", "tx"]: + raise ValueError( + "Only 'rx' and 'tx' strings are supported \ + on direction argument" + ) + + if direction == "rx": + tot_bytes = int(self.register_map.in_traffic_bytes) + tot_cycles = int(self.register_map.in_traffic_cycles) + tot_pkts = int(self.register_map.in_traffic_packets) + else: + tot_bytes = int(self.register_map.out_traffic_bytes) + tot_cycles = int(self.register_map.out_traffic_cycles) + tot_pkts = int(self.register_map.out_traffic_packets) + + tot_time = (1 / (self.freq * 10 ** 6)) * tot_cycles + thr_bs = (tot_bytes * 8) / tot_time + + return tot_pkts, thr_bs / (10 ** 9), tot_time + + def reset_stats(self): + """ + Reset embedded probes + """ + self.register_map.debug_reset = 1 + + +class CounterIP(DefaultIP): + """ This class wraps the common function of counter IP + + """ + + bindto = ["xilinx.com:hls:krnl_counters:1.0"] + + def __init__(self, description): + super().__init__(description=description) + self._fullpath = description['fullpath'] + self.start = self.start_sw = self.start_none = \ + self.start_ert = self.call + + def _setup_packet_prototype(self): + pass + + def call(self, *args, **kwargs): + raise RuntimeError("{} is a free running kernel and cannot be " + "starter or called".format(self._fullpath)) + + @property + def counters(self): + """ Return counters + + """ + + counters = { + 'packets': int(self.register_map.packets), + 'beats': int(self.register_map.beats), + 'bytes': int(self.register_map.bytes), + } + + return counters + + def reset_counters(self): + """ Reset internal counters + + """ + + self.register_map.reset = 0 + self.register_map.reset = 1 + self.register_map.reset = 0 + + +class CollectorIP(DefaultIP): + """ This class wraps the common function the collector Kernel + + """ + + bindto = ["xilinx.com:hls:collector:1.0"] + + def __init__(self, description): + super().__init__(description=description) + + @property + def received_packets(self): + # When a register is written by the kernel for non free running kernels + # the default offset refers to the value that the kernel reads + # the actual register where the kernel writes is not exposed in the + # signature, so we need to compute the offset and use mmio to read it + + rx_pkts_offset = self.register_map.received_packets.address + \ + self.register_map.received_packets.width//8 + 4 + return self.read(rx_pkts_offset) \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/driver/utils.py b/linker/slashkit/resources/dcmac/driver/utils.py new file mode 100644 index 00000000..15fe50d7 --- /dev/null +++ b/linker/slashkit/resources/dcmac/driver/utils.py @@ -0,0 +1,47 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +import argparse +import numpy as np +import os + +int_types = (int, np.int8, np.int16, np.int32, np.uint8, np.uint16, np.uint32) + + +def hex_or_int(value): + try: + if value.startswith(('0x', '0X')): + return int(value, 16) + return int(value) + except ValueError: + raise argparse.ArgumentTypeError(f"Invalid value: {value}. Must be an " + "integer or hexadecimal.") + + +def rshift(value: int, shift: int = 0, bitwidth: int = 1): + """Right shift value and mask with 'bitwidth'""" + value = value >> shift + mask = (2**bitwidth)-1 + return int(value & mask) + + +def get_ip_offset(baseoffset: int, mac_id: int): + """Get IP offset based on 'baseoffset' and 'mac_id'""" + + return baseoffset + (0x100_0000 * mac_id) + + +def add_common_args(parser, enable_mac: bool = True, verbose: bool = False): + """Add common arguments to the parser""" + default_dev = os.environ['V80_DEV'] if 'V80_DEV' in os.environ else 'e2' + parser.add_argument('-d', '--dev', help=f"PCIe device Bus ID, e.g., '{default_dev}'", + default=default_dev) + if enable_mac: + default_dcmac_id = os.environ['V80_DCMAC_ID'] if 'V80_DCMAC_ID' in os.environ else '0' + parser.add_argument('-m', '--dcmac', help="DCMAC ID either 0 or 1", + default=default_dcmac_id, choices=[0, 1], type=int) + if verbose: + parser.add_argument('-v', '--verbose', type=int, default=0, + choices=[0, 1], help='Verbosity mode') + + return parser diff --git a/linker/slashkit/resources/dcmac/hdl/axis_seg_to_unseg_converter.v b/linker/slashkit/resources/dcmac/hdl/axis_seg_to_unseg_converter.v new file mode 100644 index 00000000..0a4c1585 --- /dev/null +++ b/linker/slashkit/resources/dcmac/hdl/axis_seg_to_unseg_converter.v @@ -0,0 +1,5438 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright © 2015-2025 Advanced Micro Devices, Inc. All rights reserved. + +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), +// to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +// IN THE SOFTWARE. +////////////////////////////////////////////////////////////////////////////// +// +// DO NOT MODIFY THIS FILE. +////////////////////////////////////////////////////////////////////////////// +// +// Company : Advanced Micro Devices +// +// Create Date : 13/02/2024 10:36:53 AM +// Design Name : AXIS segmented <=> unsegmented interface converter +// Module Name : axis_seg_and_unseg_converter +// Project Name : +// Target Devices : +// Tool Versions : +// Description : Segmented AXI stream <-> unsegmented AXI stream converter for DCMAC +// : Supported mode - Coupled MAC+PHY mode (FixedE) +// : Supported data rates - 100 or 200 or 400Gbps +// : Data width of each segment of segmented axis interface is considered as 128bits +// : Unsegmented AXIS interface configuration as below, +// : 100G - 1x256b @ >=450MHz, higher clock is needed to accomodate packet rate (considering 65Byte packets) +// : 200G - 1x1024b @391MHz, data width is doubled to accomodate packet rate (considering 65Byte packets) +// : 400G - 2x1024b @391MHz, two ports are used to accomodate packet rate (considering 129Byte packets) +// +// Revision : 1.00 - Initial version +// : 1.01 - Critical path optimization and design improvements +// : 1.02 - Added error transfer between seg & unseg interfaces( seg err <-> unseg tuser ) +// +// Additional Notes : +// : 1. Backpressure is not supported by DCMAC at the segmented interface of RX side. Data must be consumed +// : when the rx_tvalid signal is available. User need to consider required buffering at the input/output +// : of the seg to unseg converter. Overflow of the input buffer in the seg to unseg converter will lead +// : to packet loss and/or data corruption. To avoid this, input packets will be dropped when the packet +// : buffer of the seg to unseg converter becomes full(tail drop performed). This feature can be disabled +// : when using with other traffic masters which support back pressure. +// +// : 2. At the TX side of the DCMAC, packets should not be sent with broken Valid signal (seg_val should +// : not go low in between a SoP and EoP. seg_val deassertion should aligned with an EoP and seg_val +// : assertion should aligned with SoP). Violation of this leads to packet loss and corruption at the +// : DCMAC. To overcome this limitation and also to improve segment packing efficiency, packets are processed as a +// : block(of packets) and sent to DCMAC when tx_tready signal of DCMAC segmented is available. +// : This makes the unsegmented to segmented converter bulky and uses deep FIFOs aligned with the +// : block size used. For optimal performance, preferred block size is 512 +// +// : 3. For 100G mode, the 2x128 segments are mapped to 1x256 bit AXI Stream interface. To accomodate the Packet +// : rate, considering the worst case packet size of 65Bytes, the converter is designed to run at a +// : higher clock than the DCMAC segmented interface clock(>=450MHz is preferred, least minimum is 425 MHz). +// +// : 4. For 200G mode, the 4x128 segments are mapped to 1x1024 bit AXI Stream interface. Direct mapping of 4x128 +// : segments to 1x512 bit AXIS would need atleast 562MHz for the converter to accomodate the packet rate +// : considering the worst case packet size of 65Bytes. Timing closure would be difficult for such high clocks +// : and most of the AXIS based IPs would not support such high clocks. To accomodate the packet rate, +// : 4x128 segments are mapped to 1x1024 bit AXI stream. The converter can run at the same DCMAC clock of the +// : segmented interface +// +// : 5. For 400G operation 8x128 segments are mapped to 2x1024 bit AXI Stream interfaces to accomodate the packet +// : rate considering the worst case packet size of 129Bytes. Direct mapping of 8x128 segments to 1x1024 bit +// : AXIS would need atleast 654MHz for the converter. To overcome the similar limitations mentioned +// : for the 200G case, 8x128 segments are mapped to 2x1024 bit AXI Streams and the converter is designed to run +// : at the same DCMAC clock of the segmented interface(391MHz).The first packet received from the DCMAC +// : segmented interface is sent to the first AXIS port and next packet to the second AXIS port and so on +// : in a Round Robin fashion. At the unsegmented to segmented side, packets are taken from the AXIS ports based +// : on the availabily of packets and follow round robin arbitration. +// +// : 6. Array based mechanism is implemented for packing and unpacking of segments in the converter. The design +// : consumes considerable logic for the 200G and 400G configuration and also have timing closure challenges. +// +// : 7. Critical path optimizations done and timing improved for all the configurations (with the DCMAC example design). +// : however 400G & 200G configuration may have timing closure challenges when integrating with large designs. +// +// : 8. Debug logic and statistic counters are included in the converter but it is recommened to disable them for +// : synthesis/implementation to avoid timing violations. They were added only for simulation/verification purpose. +// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// User configuration defines; please refer IP documentation for more details + +`define data_rate_200 // data rate of DCMAC port (update the suffix as per the requirement; 100,200 or 400) +`define en_seg_to_unseg_cnv // Enable/disable segmented to unsegmented axi stream converter +`define en_unseg_to_seg_cnv // Enable/disable unsegmented to segmented axi stream converter +`define max_packet_size 9216 // Maximum packet size expeted/to be supported +`define max_pkt_size_above_1k // Comment off if max packet size is less than 1024Bytes +`define en_flow_control // Enable/Disable flow control at the seg to unseg converter. + // Enable if backpressure is not supported by the traffic source. Incomimg packets are dropped when + // downstream ports backpressures and buffers become full. Disable if backpressure is supported by + // the traffic master + +// Enabling bleow defines is not recommended (shall be enabled for simulation) + +//`define statistics_en // Enable Input & output port statistic (packet & byte counters) +//`define debug_en // Enable error checks in the design + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Do not change the below derived defines except "independant_clk" + +// derived Converter defines + +`define segment_width 128 // data width of each segment of segmented axis interface +`ifdef data_rate_100 + `define num_segments 2 // number of segments of input segmented axis interface + `define num_axis_ports 1 // number of ports of output unsegmented axis interface + `define unseg_axis_w 256 // data width of output unsegmented axis interface + `define pktarray_depth 4 // depth of the segment array used to unpack/pack the segments + `define independant_clk // if defined segmented and the unsegmented interface runs at different clocks. + // for applications other than DCMAC and data rate less then 100Gbps user can run the interfaces + // at the desired clock frequency, either single clock or dual clock as per the need. Same applies for + // 200G and 400G configurations also +`elsif data_rate_200 + `define num_segments 4 + `define en_port1 + `define num_axis_ports 1 + `define unseg_axis_w 1024 + `define pktarray_depth 16 +`elsif data_rate_400 + `define num_segments 8 + `define num_axis_ports 2 + `define en_port1 + `define en_port2 + `define en_port3 + `define en_axis1 + `define pktarray_depth 16 + `define unseg_axis_w 1024 +`else + `define invalid_config // only 100, 200 or 400 data rate with the above configurations allowed + // For other rates user can choose the nearest configuration and drive the clocks as needed + // to meet the data rate +`endif + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +`ifndef invalid_config + +module axis_seg_and_unseg_converter + ( + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + + `ifdef en_seg_to_unseg_cnv + // AXIS Segment to Unsegment converter ports + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_rx_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_rx_seg_in" *) + input aclk_rx_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_rx_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_rx_seg_in, + + // Input Segmented stream interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 input + input Seg2UnSegEna0_in, + input [`segment_width-1:0] Seg2UnSegDat0_in, + input Seg2UnSegSop0_in, + input Seg2UnSegEop0_in, + input Seg2UnSegErr0_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty0_in, + // Segment 1 input + input Seg2UnSegEna1_in, + input [`segment_width-1:0] Seg2UnSegDat1_in, + input Seg2UnSegSop1_in, + input Seg2UnSegEop1_in, + input Seg2UnSegErr1_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty1_in, + `ifdef en_port1 + // Segment 2 input + input Seg2UnSegEna2_in, + input [`segment_width-1:0] Seg2UnSegDat2_in, + input Seg2UnSegSop2_in, + input Seg2UnSegEop2_in, + input Seg2UnSegErr2_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty2_in, + // Segment 3 input + input Seg2UnSegEna3_in, + input [`segment_width-1:0] Seg2UnSegDat3_in, + input Seg2UnSegSop3_in, + input Seg2UnSegEop3_in, + input Seg2UnSegErr3_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty3_in, + `endif + `ifdef en_port2 + // Segment 4 input + input Seg2UnSegEna4_in, + input [`segment_width-1:0] Seg2UnSegDat4_in, + input Seg2UnSegSop4_in, + input Seg2UnSegEop4_in, + input Seg2UnSegErr4_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty4_in, + // Segment 5 input + input Seg2UnSegEna5_in, + input [`segment_width-1:0] Seg2UnSegDat5_in, + input Seg2UnSegSop5_in, + input Seg2UnSegEop5_in, + input Seg2UnSegErr5_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty5_in, + `endif + `ifdef en_port3 + // Segment 6 input + input Seg2UnSegEna6_in, + input [`segment_width-1:0] Seg2UnSegDat6_in, + input Seg2UnSegSop6_in, + input Seg2UnSegEop6_in, + input Seg2UnSegErr6_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty6_in, + // Segment 7 input + input Seg2UnSegEna7_in, + input [`segment_width-1:0] Seg2UnSegDat7_in, + input Seg2UnSegSop7_in, + input Seg2UnSegEop7_in, + input Seg2UnSegErr7_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty7_in, + `endif + input wire Seg2UnSeg_tvalid_in, + + // Packet output interface - Unsegmented AXI Stream + // AXIS-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TLAST" *) + output m_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TVALID" *) + output m_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TUSER" *) + output m_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TREADY" *) + input m_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TLAST" *) + output m_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TVALID" *) + output m_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TUSER" *) + output m_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TREADY" *) + input m_axis1_tready, + `endif + + `ifdef en_flow_control + output wire seg2unseg_buff_full, + `else + output wire seg2unseg_inbuff_overflow, + output wire seg2unseg_inbuff_afull, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] stat_rx_p1_pkt_out_cnt, + output wire [63: 0] stat_rx_p1_err_pkt_out_cnt, + output wire [63: 0] stat_rx_p1_pkt_out_byte_cnt, + output wire [63: 0] stat_rx_p0_pkt_out_cnt, + output wire [63: 0] stat_rx_p0_err_pkt_out_cnt, + output wire [63: 0] stat_rx_p0_pkt_out_byte_cnt, + `endif + output wire [63: 0] stat_rx_total_pkt_in_cnt, + output wire [63: 0] stat_rx_total_err_pkt_in_cnt, + output wire [63: 0] stat_rx_total_pkt_in_byte_cnt, + output wire [63: 0] stat_rx_total_pkt_out_cnt, + output wire [63: 0] stat_rx_total_err_pkt_out_cnt, + output wire [63: 0] stat_rx_total_pkt_out_byte_cnt, + `endif + `endif + + `ifdef debug_en + output wire seg2unseg_broken_packet_out_error, + output wire seg2unseg_rx_packet_error, + `endif + + `ifdef en_unseg_to_seg_cnv + // AXIS Segment to Unsegment converter ports + + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_tx_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_tx_seg_in" *) + input aclk_tx_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_tx_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_tx_seg_in, + + // Output Segmented stream interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 output + output Unseg2SegEna0_out, + output [`segment_width-1:0] Unseg2SegDat0_out, + output Unseg2SegSop0_out, + output Unseg2SegEop0_out, + output Unseg2SegErr0_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty0_out, + // Segment 1 output + output Unseg2SegEna1_out, + output [`segment_width-1:0] Unseg2SegDat1_out, + output Unseg2SegSop1_out, + output Unseg2SegEop1_out, + output Unseg2SegErr1_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty1_out, + `ifdef en_port1 + // Segment 2 output + output Unseg2SegEna2_out, + output [`segment_width-1:0] Unseg2SegDat2_out, + output Unseg2SegSop2_out, + output Unseg2SegEop2_out, + output Unseg2SegErr2_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty2_out, + // Segment 3 output + output Unseg2SegEna3_out, + output [`segment_width-1:0] Unseg2SegDat3_out, + output Unseg2SegSop3_out, + output Unseg2SegEop3_out, + output Unseg2SegErr3_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty3_out, + `endif + `ifdef en_port2 + // Segment 4 output + output Unseg2SegEna4_out, + output [`segment_width-1:0] Unseg2SegDat4_out, + output Unseg2SegSop4_out, + output Unseg2SegEop4_out, + output Unseg2SegErr4_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty4_out, + // Segment 5 output + output Unseg2SegEna5_out, + output [`segment_width-1:0] Unseg2SegDat5_out, + output Unseg2SegSop5_out, + output Unseg2SegEop5_out, + output Unseg2SegErr5_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty5_out, + `endif + `ifdef en_port3 + // Segment 6 output + output Unseg2SegEna6_out, + output [`segment_width-1:0] Unseg2SegDat6_out, + output Unseg2SegSop6_out, + output Unseg2SegEop6_out, + output Unseg2SegErr6_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty6_out, + // Segment 7 output + output Unseg2SegEna7_out, + output [`segment_width-1:0] Unseg2SegDat7_out, + output Unseg2SegSop7_out, + output Unseg2SegEop7_out, + output Unseg2SegErr7_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty7_out, + `endif + + // Packet input interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TLAST" *) + input s_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TVALID" *) + input s_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TUSER" *) + input s_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TREADY" *) + output s_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TLAST" *) + input s_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TVALID" *) + input s_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TUSER" *) + input s_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TREADY" *) + output s_axis1_tready, + `endif + + `ifdef debug_en + output wire unseg2seg_missing_sop_error, + output wire unseg2seg_broken_pkt_out_error, + output wire unseg2seg_broken_pkt_in_error, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] stat_tx_p1_pkt_in_cnt, + output wire [63: 0] stat_tx_p1_err_pkt_in_cnt, + output wire [63: 0] stat_tx_p1_pkt_in_byte_cnt, + output wire [63: 0] stat_tx_p0_pkt_in_cnt, + output wire [63: 0] stat_tx_p0_err_pkt_in_cnt, + output wire [63: 0] stat_tx_p0_pkt_in_byte_cnt, + `endif + output wire [63: 0] stat_tx_total_pkt_in_cnt, + output wire [63: 0] stat_tx_total_err_pkt_in_cnt, + output wire [63: 0] stat_tx_total_pkt_in_byte_cnt, + output wire [63: 0] stat_tx_total_pkt_out_cnt, + output wire [63: 0] stat_tx_total_err_pkt_out_cnt, + output wire [63: 0] stat_tx_total_pkt_out_byte_cnt, + `endif + + input wire Unseg2Seg_tready_in, + output wire Unseg2Seg_tvalid_out + `endif + ); + +//----------------------------------------------------------------------------------------------------------------------- + +//------------------- AXIS Segment to Unsegment Converter + +`ifdef en_seg_to_unseg_cnv + +axis_seg_to_unseg_converter u_axis_seg_to_unseg_converter + ( + // Clock & Resets + .aclk_axis_seg_in(aclk_rx_seg_in), + .aresetn_axis_seg_in(aresetn_rx_seg_in), + `ifdef independant_clk + .aclk_axis_unseg_in(aclk_axis_unseg_in), + .aresetn_axis_unseg_in(aresetn_axis_unseg_in), + `endif + // Segmented interface + // Port0 (segments 0 & 1) is active for all valid configurations + // Segment 0 input + .Seg2UnSegEna0_in(Seg2UnSegEna0_in), + .Seg2UnSegDat0_in(Seg2UnSegDat0_in), + .Seg2UnSegSop0_in(Seg2UnSegSop0_in), + .Seg2UnSegEop0_in(Seg2UnSegEop0_in), + .Seg2UnSegErr0_in(Seg2UnSegErr0_in), + .Seg2UnSegMty0_in(Seg2UnSegMty0_in), + // Segment 1 input + .Seg2UnSegEna1_in(Seg2UnSegEna1_in), + .Seg2UnSegDat1_in(Seg2UnSegDat1_in), + .Seg2UnSegSop1_in(Seg2UnSegSop1_in), + .Seg2UnSegEop1_in(Seg2UnSegEop1_in), + .Seg2UnSegErr1_in(Seg2UnSegErr1_in), + .Seg2UnSegMty1_in(Seg2UnSegMty1_in), + `ifdef en_port1 + // Segment 2 input + .Seg2UnSegEna2_in(Seg2UnSegEna2_in), + .Seg2UnSegDat2_in(Seg2UnSegDat2_in), + .Seg2UnSegSop2_in(Seg2UnSegSop2_in), + .Seg2UnSegEop2_in(Seg2UnSegEop2_in), + .Seg2UnSegErr2_in(Seg2UnSegErr2_in), + .Seg2UnSegMty2_in(Seg2UnSegMty2_in), + // Segment 3 input + .Seg2UnSegEna3_in(Seg2UnSegEna3_in), + .Seg2UnSegDat3_in(Seg2UnSegDat3_in), + .Seg2UnSegSop3_in(Seg2UnSegSop3_in), + .Seg2UnSegEop3_in(Seg2UnSegEop3_in), + .Seg2UnSegErr3_in(Seg2UnSegErr3_in), + .Seg2UnSegMty3_in(Seg2UnSegMty3_in), + `endif + `ifdef en_port2 + // Segment 4 input + .Seg2UnSegEna4_in(Seg2UnSegEna4_in), + .Seg2UnSegDat4_in(Seg2UnSegDat4_in), + .Seg2UnSegSop4_in(Seg2UnSegSop4_in), + .Seg2UnSegEop4_in(Seg2UnSegEop4_in), + .Seg2UnSegErr4_in(Seg2UnSegErr4_in), + .Seg2UnSegMty4_in(Seg2UnSegMty4_in), + // Segment 5 input + .Seg2UnSegEna5_in(Seg2UnSegEna5_in), + .Seg2UnSegDat5_in(Seg2UnSegDat5_in), + .Seg2UnSegSop5_in(Seg2UnSegSop5_in), + .Seg2UnSegEop5_in(Seg2UnSegEop5_in), + .Seg2UnSegErr5_in(Seg2UnSegErr5_in), + .Seg2UnSegMty5_in(Seg2UnSegMty5_in), + `endif + `ifdef en_port3 + // Segment 6 input + .Seg2UnSegEna6_in(Seg2UnSegEna6_in), + .Seg2UnSegDat6_in(Seg2UnSegDat6_in), + .Seg2UnSegSop6_in(Seg2UnSegSop6_in), + .Seg2UnSegEop6_in(Seg2UnSegEop6_in), + .Seg2UnSegErr6_in(Seg2UnSegErr6_in), + .Seg2UnSegMty6_in(Seg2UnSegMty6_in), + // Segment 7 input + .Seg2UnSegEna7_in(Seg2UnSegEna7_in), + .Seg2UnSegDat7_in(Seg2UnSegDat7_in), + .Seg2UnSegSop7_in(Seg2UnSegSop7_in), + .Seg2UnSegEop7_in(Seg2UnSegEop7_in), + .Seg2UnSegErr7_in(Seg2UnSegErr7_in), + .Seg2UnSegMty7_in(Seg2UnSegMty7_in), + `endif + // Packet output interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + .m_axis0_tdata(m_axis0_tdata), + .m_axis0_tkeep(m_axis0_tkeep), + .m_axis0_tlast(m_axis0_tlast), + .m_axis0_tvalid(m_axis0_tvalid), + .m_axis0_tuser(m_axis0_tuser), + .m_axis0_tready(m_axis0_tready), + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + .m_axis1_tdata(m_axis1_tdata), + .m_axis1_tkeep(m_axis1_tkeep), + .m_axis1_tlast(m_axis1_tlast), + .m_axis1_tvalid(m_axis1_tvalid), + .m_axis1_tuser(m_axis1_tuser), + .m_axis1_tready(m_axis1_tready), + `endif + + `ifdef en_flow_control + .buff_full(seg2unseg_buff_full), + `else + .inbuff_overflow(seg2unseg_inbuff_overflow), + .inbuff_afull(seg2unseg_inbuff_afull), + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + .p1_pkt_out_cnt(stat_rx_p1_pkt_out_cnt), + .p1_err_pkt_out_cnt(stat_rx_p1_err_pkt_out_cnt), + .p1_pkt_out_byte_cnt(stat_rx_p1_pkt_out_byte_cnt), + .p0_pkt_out_cnt(stat_rx_p0_pkt_out_cnt), + .p0_err_pkt_out_cnt(stat_rx_p0_err_pkt_out_cnt), + .p0_pkt_out_byte_cnt(stat_rx_p0_pkt_out_byte_cnt), + `endif + .total_pkt_in_cnt(stat_rx_total_pkt_in_cnt), + .total_err_pkt_in_cnt(stat_rx_total_err_pkt_in_cnt), + .total_pkt_in_byte_cnt(stat_rx_total_pkt_in_byte_cnt), + .total_pkt_out_cnt(stat_rx_total_pkt_out_cnt), + .total_err_pkt_out_cnt(stat_rx_total_err_pkt_out_cnt), + .total_pkt_out_byte_cnt(stat_rx_total_pkt_out_byte_cnt), + `endif + + `ifdef debug_en + .error_broken_packet_out(seg2unseg_broken_packet_out_error), + .seg_rx_err_packet(seg2unseg_rx_packet_error), + `endif + + .rx_axis_tvalid_i(Seg2UnSeg_tvalid_in) + ); + `endif + +`ifdef en_unseg_to_seg_cnv + +axis_unseg_to_seg_converter u_axis_unseg_to_seg_converter + ( + // AXIS Segment to Unsegment converter ports + // Clock & Resets + .aclk_axis_seg_in(aclk_tx_seg_in), + .aresetn_axis_seg_in(aresetn_tx_seg_in), + `ifdef independant_clk + .aclk_axis_unseg_in(aclk_axis_unseg_in), + .aresetn_axis_unseg_in(aresetn_axis_unseg_in), + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + .Unseg2SegEna0_out(Unseg2SegEna0_out), + .Unseg2SegDat0_out(Unseg2SegDat0_out), + .Unseg2SegSop0_out(Unseg2SegSop0_out), + .Unseg2SegEop0_out(Unseg2SegEop0_out), + .Unseg2SegErr0_out(Unseg2SegErr0_out), + .Unseg2SegMty0_out(Unseg2SegMty0_out), + // Segment 1 input + .Unseg2SegEna1_out(Unseg2SegEna1_out), + .Unseg2SegDat1_out(Unseg2SegDat1_out), + .Unseg2SegSop1_out(Unseg2SegSop1_out), + .Unseg2SegEop1_out(Unseg2SegEop1_out), + .Unseg2SegErr1_out(Unseg2SegErr1_out), + .Unseg2SegMty1_out(Unseg2SegMty1_out), + `ifdef en_port1 + // Segment 2 input + .Unseg2SegEna2_out(Unseg2SegEna2_out), + .Unseg2SegDat2_out(Unseg2SegDat2_out), + .Unseg2SegSop2_out(Unseg2SegSop2_out), + .Unseg2SegEop2_out(Unseg2SegEop2_out), + .Unseg2SegErr2_out(Unseg2SegErr2_out), + .Unseg2SegMty2_out(Unseg2SegMty2_out), + // Segment 3 input + .Unseg2SegEna3_out(Unseg2SegEna3_out), + .Unseg2SegDat3_out(Unseg2SegDat3_out), + .Unseg2SegSop3_out(Unseg2SegSop3_out), + .Unseg2SegEop3_out(Unseg2SegEop3_out), + .Unseg2SegErr3_out(Unseg2SegErr3_out), + .Unseg2SegMty3_out(Unseg2SegMty3_out), + `endif + `ifdef en_port2 + // Segment 4 input + .Unseg2SegEna4_out(Unseg2SegEna4_out), + .Unseg2SegDat4_out(Unseg2SegDat4_out), + .Unseg2SegSop4_out(Unseg2SegSop4_out), + .Unseg2SegEop4_out(Unseg2SegEop4_out), + .Unseg2SegErr4_out(Unseg2SegErr4_out), + .Unseg2SegMty4_out(Unseg2SegMty4_out), + // Segment 5 input + .Unseg2SegEna5_out(Unseg2SegEna5_out), + .Unseg2SegDat5_out(Unseg2SegDat5_out), + .Unseg2SegSop5_out(Unseg2SegSop5_out), + .Unseg2SegEop5_out(Unseg2SegEop5_out), + .Unseg2SegErr5_out(Unseg2SegErr5_out), + .Unseg2SegMty5_out(Unseg2SegMty5_out), + `endif + `ifdef en_port3 + // Segment 6 input + .Unseg2SegEna6_out(Unseg2SegEna6_out), + .Unseg2SegDat6_out(Unseg2SegDat6_out), + .Unseg2SegSop6_out(Unseg2SegSop6_out), + .Unseg2SegEop6_out(Unseg2SegEop6_out), + .Unseg2SegErr6_out(Unseg2SegErr6_out), + .Unseg2SegMty6_out(Unseg2SegMty6_out), + // Segment 7 input + .Unseg2SegEna7_out(Unseg2SegEna7_out), + .Unseg2SegDat7_out(Unseg2SegDat7_out), + .Unseg2SegSop7_out(Unseg2SegSop7_out), + .Unseg2SegEop7_out(Unseg2SegEop7_out), + .Unseg2SegErr7_out(Unseg2SegErr7_out), + .Unseg2SegMty7_out(Unseg2SegMty7_out), + `endif + + // Packet input interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + .s_axis0_tdata(s_axis0_tdata), + .s_axis0_tkeep(s_axis0_tkeep), + .s_axis0_tlast(s_axis0_tlast), + .s_axis0_tvalid(s_axis0_tvalid), + .s_axis0_tuser(s_axis0_tuser), + .s_axis0_tready(s_axis0_tready), + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + .s_axis1_tdata(s_axis1_tdata), + .s_axis1_tkeep(s_axis1_tkeep), + .s_axis1_tlast(s_axis1_tlast), + .s_axis1_tvalid(s_axis1_tvalid), + .s_axis1_tuser(s_axis1_tuser), + .s_axis1_tready(s_axis1_tready), + `endif + + `ifdef debug_en + .error_missing_sop(unseg2seg_missing_sop_error), + .error_broken_pkt_out(unseg2seg_broken_pkt_out_error), + .error_broken_pkt_in(unseg2seg_broken_pkt_in_error), + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + .p1_pkt_in_cnt(stat_tx_p1_pkt_in_cnt), + .p1_err_pkt_in_cnt(stat_tx_p1_err_pkt_in_cnt), + .p1_pkt_in_byte_cnt(stat_tx_p1_pkt_in_byte_cnt), + .p0_pkt_in_cnt(stat_tx_p0_pkt_in_cnt), + .p0_err_pkt_in_cnt(stat_tx_p0_err_pkt_in_cnt), + .p0_pkt_in_byte_cnt(stat_tx_p0_pkt_in_byte_cnt), + `endif + .total_pkt_in_cnt(stat_tx_total_pkt_in_cnt), + .total_err_pkt_in_cnt(stat_tx_total_err_pkt_in_cnt), + .total_pkt_in_byte_cnt(stat_tx_total_pkt_in_byte_cnt), + .total_pkt_out_cnt(stat_tx_total_pkt_out_cnt), + .total_err_pkt_out_cnt(stat_tx_total_err_pkt_out_cnt), + .total_pkt_out_byte_cnt(stat_tx_total_pkt_out_byte_cnt), + `endif + + .tx_axis_tready_in(Unseg2Seg_tready_in), + .tx_axis_tvalid_out(Unseg2Seg_tvalid_out) + ); + +`endif + +endmodule + +`endif + +//######################################################################################################################## + +//------------------------------------ AXIS Segmented to Unsegmented Stream Converter ------------------------------------ + +module axis_seg_to_unseg_converter + ( + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_axis_seg_in" *) + input aclk_axis_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_seg_in, + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + input Seg2UnSegEna0_in, + input [`segment_width-1:0] Seg2UnSegDat0_in, + input Seg2UnSegSop0_in, + input Seg2UnSegEop0_in, + input Seg2UnSegErr0_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty0_in, + // Segment 1 input + input Seg2UnSegEna1_in, + input [`segment_width-1:0] Seg2UnSegDat1_in, + input Seg2UnSegSop1_in, + input Seg2UnSegEop1_in, + input Seg2UnSegErr1_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty1_in, + `ifdef en_port1 + // Segment 2 input + input Seg2UnSegEna2_in, + input [`segment_width-1:0] Seg2UnSegDat2_in, + input Seg2UnSegSop2_in, + input Seg2UnSegEop2_in, + input Seg2UnSegErr2_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty2_in, + // Segment 3 input + input Seg2UnSegEna3_in, + input [`segment_width-1:0] Seg2UnSegDat3_in, + input Seg2UnSegSop3_in, + input Seg2UnSegEop3_in, + input Seg2UnSegErr3_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty3_in, + `endif + `ifdef en_port2 + // Segment 4 input + input Seg2UnSegEna4_in, + input [`segment_width-1:0] Seg2UnSegDat4_in, + input Seg2UnSegSop4_in, + input Seg2UnSegEop4_in, + input Seg2UnSegErr4_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty4_in, + // Segment 5 input + input Seg2UnSegEna5_in, + input [`segment_width-1:0] Seg2UnSegDat5_in, + input Seg2UnSegSop5_in, + input Seg2UnSegEop5_in, + input Seg2UnSegErr5_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty5_in, + `endif + `ifdef en_port3 + // Segment 6 input + input Seg2UnSegEna6_in, + input [`segment_width-1:0] Seg2UnSegDat6_in, + input Seg2UnSegSop6_in, + input Seg2UnSegEop6_in, + input Seg2UnSegErr6_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty6_in, + // Segment 7 input + input Seg2UnSegEna7_in, + input [`segment_width-1:0] Seg2UnSegDat7_in, + input Seg2UnSegSop7_in, + input Seg2UnSegEop7_in, + input Seg2UnSegErr7_in, + input [($clog2(`segment_width/8))-1:0] Seg2UnSegMty7_in, + `endif + + // Packet output interface - Unsegmented AXI Stream + // AXI-0 is active for all valid configurations + // Unsegmented AXIS-0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TLAST" *) + output m_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TVALID" *) + output m_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TUSER" *) + output m_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis0_pkt_out TREADY" *) + input m_axis0_tready, + + `ifdef en_axis1 + // Unsegmented AXIS-1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TDATA" *) + output [`unseg_axis_w-1:0] m_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TKEEP" *) + output [(`unseg_axis_w/8)-1:0] m_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TLAST" *) + output m_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TVALID" *) + output m_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TUSER" *) + output m_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis1_pkt_out TREADY" *) + input m_axis1_tready, + `endif + + `ifdef en_flow_control + output wire buff_full, + `else + output wire inbuff_overflow, + output wire inbuff_afull, + `endif + + // Statistics + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] p1_pkt_out_cnt, + output wire [63: 0] p1_err_pkt_out_cnt, + output wire [63: 0] p1_pkt_out_byte_cnt, + output wire [63: 0] p0_pkt_out_cnt, + output wire [63: 0] p0_err_pkt_out_cnt, + output wire [63: 0] p0_pkt_out_byte_cnt, + `endif + output wire [63: 0] total_pkt_in_cnt, + output wire [63: 0] total_err_pkt_in_cnt, + output wire [63: 0] total_pkt_in_byte_cnt, + output wire [63: 0] total_pkt_out_cnt, + output wire [63: 0] total_err_pkt_out_cnt, + output wire [63: 0] total_pkt_out_byte_cnt, + `endif + + `ifdef debug_en + output wire error_broken_packet_out, + output reg seg_rx_err_packet, + `endif + + input wire rx_axis_tvalid_i + ); + +//----------------------------------------------------------------------------------------------------------------------- + +localparam P_MARK_DEBUG = "false"; + +// Derive local parameters + +localparam seg_mty_w = $clog2(`segment_width/8); +localparam pkt_array_depth = `pktarray_depth; +localparam local_buff_depth = 32; +localparam max_pkt_burst_size = $ceil(`max_packet_size/((`pktarray_depth/2)*(`segment_width/8))); +localparam max_pkt_burst_size_p2 = $ceil($clog2(`max_packet_size)); + +`ifdef max_pkt_size_above_1k + localparam pktarry_buff_depth = $ceil((2**(max_pkt_burst_size_p2+1))/((`pktarray_depth/2)*(`segment_width/8))); + localparam pktarry_buff_pfull_thresh = pktarry_buff_depth - max_pkt_burst_size; +`else + localparam pktarry_buff_depth = 32; + localparam pktarry_buff_pfull_thresh = pktarry_buff_depth-7; +`endif + +localparam in_buff_depth = pktarry_buff_depth/2; +localparam out_buff_depth = pktarry_buff_depth*4; +localparam out_buff_pfull_thresh = out_buff_depth - max_pkt_burst_size; + +//----------------------------------------------------------------------------------------------------------------------- + +wire [`num_segments-1:0] seg2unseg_val; +wire [`num_segments-1:0] seg2unseg_sop; +wire [`num_segments-1:0] seg2unseg_eop; +wire [`num_segments-1:0] seg2unseg_err; +wire [`segment_width-1:0] seg2unseg_dat [`num_segments-1:0]; +wire [seg_mty_w-1:0] seg2unseg_mty [`num_segments-1:0]; + +assign seg2unseg_val[0] = Seg2UnSegEna0_in & rx_axis_tvalid_i; assign seg2unseg_sop[0] = Seg2UnSegSop0_in; assign seg2unseg_eop[0] = Seg2UnSegEop0_in; assign seg2unseg_err[0] = Seg2UnSegErr0_in; assign seg2unseg_dat[0] = Seg2UnSegDat0_in; assign seg2unseg_mty[0] = Seg2UnSegMty0_in; +assign seg2unseg_val[1] = Seg2UnSegEna1_in & rx_axis_tvalid_i; assign seg2unseg_sop[1] = Seg2UnSegSop1_in; assign seg2unseg_eop[1] = Seg2UnSegEop1_in; assign seg2unseg_err[1] = Seg2UnSegErr1_in; assign seg2unseg_dat[1] = Seg2UnSegDat1_in; assign seg2unseg_mty[1] = Seg2UnSegMty1_in; +`ifdef en_port1 +assign seg2unseg_val[2] = Seg2UnSegEna2_in & rx_axis_tvalid_i; assign seg2unseg_sop[2] = Seg2UnSegSop2_in; assign seg2unseg_eop[2] = Seg2UnSegEop2_in; assign seg2unseg_err[2] = Seg2UnSegErr2_in; assign seg2unseg_dat[2] = Seg2UnSegDat2_in; assign seg2unseg_mty[2] = Seg2UnSegMty2_in; +assign seg2unseg_val[3] = Seg2UnSegEna3_in & rx_axis_tvalid_i; assign seg2unseg_sop[3] = Seg2UnSegSop3_in; assign seg2unseg_eop[3] = Seg2UnSegEop3_in; assign seg2unseg_err[3] = Seg2UnSegErr3_in; assign seg2unseg_dat[3] = Seg2UnSegDat3_in; assign seg2unseg_mty[3] = Seg2UnSegMty3_in; +`endif +`ifdef en_port2 +assign seg2unseg_val[4] = Seg2UnSegEna4_in & rx_axis_tvalid_i; assign seg2unseg_sop[4] = Seg2UnSegSop4_in; assign seg2unseg_eop[4] = Seg2UnSegEop4_in; assign seg2unseg_err[4] = Seg2UnSegErr4_in; assign seg2unseg_dat[4] = Seg2UnSegDat4_in; assign seg2unseg_mty[4] = Seg2UnSegMty4_in; +assign seg2unseg_val[5] = Seg2UnSegEna5_in & rx_axis_tvalid_i; assign seg2unseg_sop[5] = Seg2UnSegSop5_in; assign seg2unseg_eop[5] = Seg2UnSegEop5_in; assign seg2unseg_err[5] = Seg2UnSegErr5_in; assign seg2unseg_dat[5] = Seg2UnSegDat5_in; assign seg2unseg_mty[5] = Seg2UnSegMty5_in; +`endif +`ifdef en_port3 +assign seg2unseg_val[6] = Seg2UnSegEna6_in & rx_axis_tvalid_i; assign seg2unseg_sop[6] = Seg2UnSegSop6_in; assign seg2unseg_eop[6] = Seg2UnSegEop6_in; assign seg2unseg_err[6] = Seg2UnSegErr6_in; assign seg2unseg_dat[6] = Seg2UnSegDat6_in; assign seg2unseg_mty[6] = Seg2UnSegMty6_in; +assign seg2unseg_val[7] = Seg2UnSegEna7_in & rx_axis_tvalid_i; assign seg2unseg_sop[7] = Seg2UnSegSop7_in; assign seg2unseg_eop[7] = Seg2UnSegEop7_in; assign seg2unseg_err[7] = Seg2UnSegErr7_in; assign seg2unseg_dat[7] = Seg2UnSegDat7_in; assign seg2unseg_mty[7] = Seg2UnSegMty7_in; +`endif + +wire aclk_axis_unseg; +wire aresetn_axis_unseg; + +`ifdef independant_clk + assign aclk_axis_unseg = aclk_axis_unseg_in; + assign aresetn_axis_unseg = aresetn_axis_unseg_in; +`else + assign aclk_axis_unseg = aclk_axis_seg_in; + assign aresetn_axis_unseg = aresetn_axis_seg_in; +`endif + +`ifdef debug_en + + always @ (posedge aclk_axis_unseg) begin + seg_rx_err_packet <= |(seg2unseg_err & seg2unseg_val); + end + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Input buffer + +reg [`num_segments-1:0] seg2unseg_val_1; +reg [`num_segments-1:0] seg2unseg_sop_1; +reg [`num_segments-1:0] seg2unseg_eop_1; +reg [`num_segments-1:0] seg2unseg_err_1; +reg [`segment_width-1:0] seg2unseg_dat_1 [`num_segments-1:0]; +reg [seg_mty_w-1:0] seg2unseg_mty_1 [`num_segments-1:0]; + +wire [`num_segments-1:0] seg2unseg_val_c; +wire [`num_segments-1:0] seg2unseg_sop_c; +wire [`num_segments-1:0] seg2unseg_eop_c; +wire [`num_segments-1:0] seg2unseg_err_c; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_c; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_c; + +genvar a0; +generate + for (a0=0; a0<`num_segments; a0=a0+1) begin + assign seg2unseg_val_c[a0] = seg2unseg_val[a0]; + assign seg2unseg_sop_c[a0] = seg2unseg_sop[a0]; + assign seg2unseg_eop_c[a0] = seg2unseg_eop[a0]; + assign seg2unseg_err_c[a0] = seg2unseg_err[a0]; + assign seg2unseg_dat_c[((a0+1)*`segment_width)-1:a0*`segment_width] = seg2unseg_dat[a0]; + assign seg2unseg_mty_c[((a0+1)*seg_mty_w)-1:a0*seg_mty_w] = seg2unseg_mty[a0]; + end +endgenerate + +wire wr_rst_busy; +wire rd_rst_busy; +wire seg_in_aempty; +wire seg_in_empty; +wire data_valid; +wire seg_inbuff_afull; +wire seg_inbuff_overflow; + +wire ports_not_rdy; +wire [`num_axis_ports-1:0] port_unseg_out_pfull; + +`ifdef independant_clk // Input segmented intreface stream clock domain to unsegmented axis clock domain + +wire [`num_segments-1:0] seg2unseg_val_cdc; +wire [`num_segments-1:0] seg2unseg_sop_cdc; +wire [`num_segments-1:0] seg2unseg_eop_cdc; +wire [`num_segments-1:0] seg2unseg_err_cdc; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_cdc; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_cdc; + +xpm_fifo_async #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(2), + .FIFO_WRITE_DEPTH(in_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(in_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .READ_MODE("std"), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1009"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .WR_DATA_COUNT_WIDTH(1) + ) +xpm_fifo_async_seg_in ( + .almost_empty(seg_in_aempty), + .almost_full(seg_inbuff_afull), + .data_valid(data_valid), + .dbiterr(), + .dout({seg2unseg_val_cdc,seg2unseg_sop_cdc,seg2unseg_eop_cdc,seg2unseg_err_cdc,seg2unseg_mty_cdc,seg2unseg_dat_cdc}), + .empty(seg_in_empty), + .full(), + .overflow(seg_inbuff_overflow), + .prog_empty(), + .prog_full(), + .rd_data_count(), + .rd_rst_busy(rd_rst_busy), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(wr_rst_busy), + .din({seg2unseg_val_c,seg2unseg_sop_c,seg2unseg_eop_c,seg2unseg_err_c,seg2unseg_mty_c,seg2unseg_dat_c}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_clk(aclk_axis_unseg), + `ifdef en_flow_control + .rd_en(!seg_in_empty & !rd_rst_busy), + `else + .rd_en(!ports_not_rdy & !seg_in_empty & !rd_rst_busy), + `endif + .rst(!aresetn_axis_seg_in), + .sleep(1'b0), + .wr_clk(aclk_axis_seg_in), + .wr_en(|seg2unseg_val_c & !wr_rst_busy) + ); + +genvar i; +generate + for (i=0; i<`num_segments; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + seg2unseg_val_1[i] <= seg2unseg_val_cdc[i] & data_valid; + seg2unseg_sop_1[i] <= seg2unseg_sop_cdc[i]; + seg2unseg_eop_1[i] <= seg2unseg_eop_cdc[i]; + seg2unseg_err_1[i] <= seg2unseg_err_cdc[i]; + seg2unseg_dat_1[i] <= seg2unseg_dat_cdc[((i+1)*`segment_width)-1:i*`segment_width]; + seg2unseg_mty_1[i] <= seg2unseg_mty_cdc[((i+1)*seg_mty_w)-1:i*seg_mty_w]; + end + end +endgenerate + +`else // Input segmented stream intreface and unsegmented axis interface runs at same clock domain + +wire [`num_segments-1:0] seg2unseg_val_ibuf; +wire [`num_segments-1:0] seg2unseg_sop_ibuf; +wire [`num_segments-1:0] seg2unseg_eop_ibuf; +wire [`num_segments-1:0] seg2unseg_err_ibuf; +wire [(`segment_width*`num_segments)-1:0] seg2unseg_dat_ibuf; +wire [(seg_mty_w*`num_segments)-1:0] seg2unseg_mty_ibuf; + +xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(2), + .FIFO_WRITE_DEPTH(in_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(in_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1009"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH((`segment_width+seg_mty_w+4)*`num_segments), + .WR_DATA_COUNT_WIDTH(1) + ) +xpm_fifo_sync_seg_in ( + .almost_empty(seg_in_aempty), + .almost_full(seg_inbuff_afull), + .data_valid(data_valid), + .dbiterr(), + .dout({seg2unseg_val_ibuf,seg2unseg_sop_ibuf,seg2unseg_eop_ibuf,seg2unseg_err_ibuf,seg2unseg_mty_ibuf,seg2unseg_dat_ibuf}), + .empty(seg_in_empty), + .full(), + .overflow(seg_inbuff_overflow), + .prog_empty(), + .prog_full(), + .rd_data_count(), + .rd_rst_busy(rd_rst_busy), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(wr_rst_busy), + .din({seg2unseg_val_c,seg2unseg_sop_c,seg2unseg_eop_c,seg2unseg_err_c,seg2unseg_mty_c,seg2unseg_dat_c}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + `ifdef en_flow_control + .rd_en(!seg_in_empty & !rd_rst_busy), + `else + .rd_en(!ports_not_rdy & !seg_in_empty & !rd_rst_busy), + `endif + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(|seg2unseg_val_c & !wr_rst_busy) +); + +genvar j; +generate + for (j=0; j < `num_segments; j = j+1) begin + always @ (posedge aclk_axis_unseg) begin + seg2unseg_val_1[j] <= seg2unseg_val_ibuf[j] & data_valid; + seg2unseg_sop_1[j] <= seg2unseg_sop_ibuf[j]; + seg2unseg_eop_1[j] <= seg2unseg_eop_ibuf[j]; + seg2unseg_err_1[j] <= seg2unseg_err_ibuf[j]; + seg2unseg_dat_1[j] <= seg2unseg_dat_ibuf[((j+1)*`segment_width)-1:j*`segment_width]; + seg2unseg_mty_1[j] <= seg2unseg_mty_ibuf[((j+1)*seg_mty_w)-1:j*seg_mty_w]; + end + end +endgenerate + +`endif + +assign inbuff_overflow = seg_inbuff_overflow; +assign inbuff_afull = seg_inbuff_afull; + +//----------------------------------------------------------------------------------------------------------------------- + +// Arbitrate packets to different channels based on number of output axis ports (applicable for 400G with 2 AXIS ports) + +reg [`segment_width-1:0] pkt_data [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err [`num_axis_ports-1:0]; + +`ifdef data_rate_400 // two output AXI stream ports available for 400G + +genvar k, l; +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + end + end +end +endgenerate + +// Probe output AXI ports (after power ON / system reset), to initialize the port pointer for port arbiter + +reg [12:0] cnt_port_init; +reg port_init_q, port_init_qq; +wire port_init_rp; + +reg [11:0] out_port_idle_cnt [`num_axis_ports-1:0]; +reg [11:0] out_port_active_cnt [`num_axis_ports-1:0]; +reg [`num_axis_ports-1:0] out_port_active_q; +reg [`num_axis_ports-1:0] out_port_idle_q; +wire [`num_axis_ports-1:0] out_port_active_rp; +wire [`num_axis_ports-1:0] out_port_idle_rp; +wire [`num_axis_ports-1:0] out_port_rdy; +reg [`num_axis_ports-1:0] out_port_not_active; + +assign out_port_rdy[0] = m_axis0_tready; +`ifdef en_axis1 +assign out_port_rdy[1] = m_axis1_tready; +`endif + +reg only_port1_active, only_port0_active; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + cnt_port_init <= 'd0; + else if (cnt_port_init[12]) + cnt_port_init <= cnt_port_init; + else + cnt_port_init <= cnt_port_init + 1; +end + +always @ (posedge aclk_axis_unseg) begin + port_init_q <= cnt_port_init[12]; + port_init_qq <= port_init_q; +end + +assign port_init_rp = port_init_q & ~port_init_qq; + +genvar kk; + +generate + for (kk=0; kk < `num_axis_ports; kk = kk+1) begin + always @ (posedge aclk_axis_unseg) begin + out_port_active_q[kk] <= out_port_active_cnt[kk][11]; + if (!aresetn_axis_unseg) + out_port_active_cnt[kk] <= 'd0; + else if (out_port_idle_rp[kk]) + out_port_active_cnt[kk] <= 'd0; + else if (!out_port_rdy[kk]) + out_port_active_cnt[kk] <= 'd0; + else if (out_port_active_q[kk]) + out_port_active_cnt[kk] <= out_port_active_cnt[kk]; + else + out_port_active_cnt[kk] <= out_port_active_cnt[kk] + 1; + end + + assign out_port_active_rp[kk] = out_port_active_cnt[kk][11] & ~out_port_active_q[kk]; + + always @ (posedge aclk_axis_unseg) begin + out_port_not_active[kk] <= out_port_idle_cnt[kk][11]; + out_port_idle_q[kk] <= out_port_idle_cnt[kk][11]; + if (!aresetn_axis_unseg) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_active_rp[kk]) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_rdy[kk]) + out_port_idle_cnt[kk] <= 'd0; + else if (out_port_idle_q[kk]) + out_port_idle_cnt[kk] <= out_port_idle_cnt[kk]; + else + out_port_idle_cnt[kk] <= out_port_idle_cnt[kk] + 1; + end + + assign out_port_idle_rp[kk] = out_port_idle_cnt[kk][11] & ~out_port_idle_q[kk]; + end +endgenerate + +always @ (posedge aclk_axis_unseg) begin // Update port status when input stream is not active + if (!seg2unseg_val_1[0]) + if (out_port_not_active == 2'b01) + only_port1_active <= 1'b1; + else + only_port1_active <= 1'b0; + else + only_port1_active <= only_port1_active; +end + +always @ (posedge aclk_axis_unseg) begin + if (!seg2unseg_val_1[0]) + if (out_port_not_active == 2'b10) + only_port0_active <= 1'b1; + else + only_port0_active <= 1'b0; + else + only_port0_active <= only_port0_active; +end + +integer m, n; + +reg [$clog2(`num_axis_ports)-1:0] cur_port; +reg nxt_pkt_vld; + +`ifdef en_flow_control // port arbitration with flow control + +generate + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + cur_port = 1'b0; + nxt_pkt_vld = 1'b1; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + end else if (port_init_rp) begin // Initialize with the active port after power On/systen reset + if (only_port1_active) + cur_port = 1'b1; + else + cur_port = 1'b0; + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [cur_port][n] <= 1'b0; + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= nxt_pkt_vld; + if (seg2unseg_eop_1[n]) begin // Arbitrate at current packet end + if (only_port1_active) begin // Only out port1 is active + cur_port = 1'b1; + if (port_unseg_out_pfull[1]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else if (only_port0_active) begin // Only out port0 is active + cur_port = 1'b0; + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin // Both output ports are active + if (cur_port == (`num_axis_ports-1)) begin + if (port_unseg_out_pfull[0]) begin + cur_port = 1'b1; + if (port_unseg_out_pfull[1]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin + cur_port = 1'b0; + nxt_pkt_vld = 1'b1; + end + end else begin + if (port_unseg_out_pfull[1]) begin + cur_port = 1'b0; + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end else begin + cur_port = 1'b1; + nxt_pkt_vld = 1'b1; + end + end + end + end + end + end + end +end +endgenerate + +assign buff_full = |port_unseg_out_pfull; + +`else // port arbitration without flow control + +generate + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + cur_port = 1'b0; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + end else if (port_init_rp) begin // Initialize with the active port after power On/systen reset + if (only_port1_active) + cur_port = 1'b1; + else + cur_port = 1'b0; + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [cur_port][n] <= 1'b0; + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= 1'b1; + if (seg2unseg_eop_1[n]) begin + if (only_port1_active) begin + cur_port = 1'b1; + end else if (only_port0_active) begin + cur_port = 1'b0; + end else begin + if (cur_port == (`num_axis_ports-1)) begin + if (port_unseg_out_pfull[0]) begin + cur_port = 1'b1; + end else + cur_port = 1'b0; + end else begin + if (port_unseg_out_pfull[1]) begin + cur_port = 1'b0; + end else + cur_port = 1'b1; + end + end + end + end + end + end +end +endgenerate + +`endif + +`else // data rate 100 or 200 Gbps, only one output AXI stream port is available + +`ifdef en_flow_control + +genvar k, l; +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + end + end +end +endgenerate + +reg [$clog2(`num_axis_ports)-1:0] cur_port; +reg nxt_pkt_vld; + +integer m, n; + +generate + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + nxt_pkt_vld = 1'b1; + cur_port <= 1'b0; + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + cur_port <= 1'b0; + end + end + end else begin + for (m=0; m < `num_axis_ports; m = m+1) begin + for(n=0; n < `num_segments; n = n+1) begin + pkt_val [m][n] <= 1'b0; + end + end + for(n=0; n < `num_segments; n = n+1) begin + if(seg2unseg_val_1[n]) begin + pkt_val [cur_port][n] <= nxt_pkt_vld; + if (seg2unseg_eop_1[n]) + if (port_unseg_out_pfull[0]) // tail drop; drop input packets when segment buffer is full + nxt_pkt_vld = 1'b0; + else + nxt_pkt_vld = 1'b1; + end + end + end + end +endgenerate + +assign buff_full = port_unseg_out_pfull[0]; + +`else + +genvar k,l; + +generate +for (k=0; k < `num_axis_ports; k = k+1) begin + for(l=0; l < `num_segments; l = l+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data [k][l] <= seg2unseg_dat_1[l]; + pkt_mty [k][l] <= seg2unseg_mty_1[l]; + pkt_eop [k][l] <= seg2unseg_eop_1[l]; + pkt_err [k][l] <= seg2unseg_err_1[l]; + pkt_val [k][l] <= seg2unseg_val_1[l]; + end + end +end +endgenerate + +`endif + +`endif + +reg [`segment_width-1:0] pkt_data1 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty1 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val1 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop1 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err1 [`num_axis_ports-1:0]; + +reg [`segment_width-1:0] pkt_data2 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [seg_mty_w-1:0] pkt_mty2 [`num_axis_ports-1:0] [`num_segments-1:0]; +reg [`num_segments-1:0] pkt_val2 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_eop2 [`num_axis_ports-1:0]; +reg [`num_segments-1:0] pkt_err2 [`num_axis_ports-1:0]; + +genvar o, p; +generate +for (o=0; o < `num_axis_ports; o = o+1) begin + for(p=0; p < `num_segments; p = p+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_data1[o][p] <= pkt_data [o][p]; + pkt_mty1 [o][p] <= pkt_mty [o][p]; + pkt_eop1 [o][p] <= pkt_eop [o][p]; + pkt_err1 [o][p] <= pkt_err [o][p]; + pkt_val1 [o][p] <= pkt_val [o][p]; + end + always @ (posedge aclk_axis_unseg) begin + pkt_data2[o][p] <= pkt_data1 [o][p]; + pkt_mty2 [o][p] <= pkt_mty1 [o][p]; + pkt_eop2 [o][p] <= pkt_eop1 [o][p]; + pkt_err2 [o][p] <= pkt_err1 [o][p]; + pkt_val2 [o][p] <= pkt_val1 [o][p]; + end + end +end +endgenerate + +reg [`segment_width-1:0] pkt_tdata [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(`segment_width/8)-1:0] pkt_tkeep [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tvalid [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tuser [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_tlast [`num_axis_ports-1:0]; +reg [(`segment_width*(pkt_array_depth/2))-1:0] axis_tdata_buf_in [`num_axis_ports-1:0]; +reg [((`segment_width/8)*(pkt_array_depth/2))-1:0] axis_tkeep_buf_in [`num_axis_ports-1:0]; +reg [`num_axis_ports-1:0] axis_tvalid_buf_in; +reg [`num_axis_ports-1:0] axis_tlast_buf_in; +reg [`num_axis_ports-1:0] axis_tuser_buf_in; +wire [`num_axis_ports-1:0] axis_tready_buf_in; +reg [`segment_width-1:0] pkt_data_out_0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_out_0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_out_0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_out_0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_out_0 [`num_axis_ports-1:0]; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment array + +// pack the packet segments in array (to align with unsegmented axis stream data width) + +wire [`num_axis_ports-1:0] outbuff_pfull; + +`ifdef data_rate_400 + +reg [`segment_width-1:0] pkt_data_array [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [seg_mty_w-1:0] pkt_mty_array [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array0 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array00 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array1 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array2 [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_val_array [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_eop_array [`num_axis_ports-1:0]; +reg [pkt_array_depth-1:0] pkt_err_array [`num_axis_ports-1:0]; + +reg [$clog2(pkt_array_depth)-1:0] pkt_array_ptr [`num_axis_ports-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pkt_seg_sel_reg [`num_axis_ports-1:0] [pkt_array_depth-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pkt_seg_sel_reg1 [`num_axis_ports-1:0] [pkt_array_depth-1:0]; + +wire [`num_axis_ports-1:0] wr_en_c0; +wire [`num_axis_ports-1:0] wr_en_c1; + +reg [`num_axis_ports-1:0] wr_en_0; +reg [`num_axis_ports-1:0] wr_en_1; + +genvar q; +integer r, rr; +generate +for (q=0; q < `num_axis_ports; q = q+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_array_ptr[q] = 0; + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pkt_val_array0 [q][r] <= 1'b0; + pkt_val_array1 [q][r] <= 1'b0; + pkt_seg_sel_reg[q][r] <= 'd0; + end + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array0 [q][rr] <= 1'b0; + pkt_val_array1 [q][rr] <= 1'b0; + pkt_seg_sel_reg[q][rr] <= 'd0; + end + end else begin + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pkt_val_array0 [q][r] <= 1'b0; + end + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array0 [q][rr] <= 1'b0; + end + if (wr_en_c0[q]) begin + for(rr=0; rr < pkt_array_depth/2; rr = rr+1) begin + pkt_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c1[q]) begin + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pkt_val_array1 [q][rr] <= 1'b0; + end + end + for(r=0; r < `num_segments; r = r+1) begin + if (pkt_val[q][r]) begin + pkt_val_array0 [q][pkt_array_ptr[q]] <= 1'b1; + pkt_val_array1 [q][pkt_array_ptr[q]] <= 1'b1; + pkt_seg_sel_reg[q][pkt_array_ptr[q]] <= r; + if (pkt_eop[q][r]) begin + if (pkt_array_ptr[q][$clog2(pkt_array_depth)-1] == 1) + pkt_array_ptr[q] = 0; + else + pkt_array_ptr[q] = pkt_array_depth/2; + end else + pkt_array_ptr[q] = pkt_array_ptr[q] + 1; + end + end + end + end +end +endgenerate + +genvar s, array_depth; +generate +for (s=0; s < `num_axis_ports; s = s+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_val_array2[s] <= pkt_val_array1[s]; + pkt_val_array[s] <= pkt_val_array2[s]; + pkt_val_array00[s] <= pkt_val_array0[s]; + end + for (array_depth=0; array_depth < pkt_array_depth; array_depth = array_depth+1) begin + always @ (posedge aclk_axis_unseg) begin + pkt_seg_sel_reg1[s][array_depth] <= pkt_seg_sel_reg[s][array_depth]; + end + end + for (array_depth=0; array_depth < pkt_array_depth; array_depth = array_depth+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_eop_array[s][array_depth] <= 1'b0; + pkt_err_array[s][array_depth] <= 1'b0; + pkt_mty_array[s][array_depth] <= 'd0; + pkt_data_array[s][array_depth] <= 'd0; + end else begin + if (pkt_val_array00[s][array_depth]) begin + pkt_eop_array[s][array_depth] <= pkt_eop2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_err_array[s][array_depth] <= pkt_err2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_mty_array[s][array_depth] <= pkt_mty2 [s][pkt_seg_sel_reg1[s][array_depth]]; + pkt_data_array[s][array_depth] <= pkt_data2[s][pkt_seg_sel_reg1[s][array_depth]]; + end else begin + pkt_eop_array[s][array_depth] <= 1'b0; + pkt_err_array[s][array_depth] <= 1'b0; + end + end + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Buffering packed segments + +reg [`num_axis_ports-1:0] rd_en_0; +reg [`num_axis_ports-1:0] rd_en_1; + +genvar t; + +generate +for (t=0; t<`num_axis_ports; t=t+1) begin + assign wr_en_c0[t] = pkt_val_array1[t][(pkt_array_depth/2)-1] | (|pkt_eop_array[t][(pkt_array_depth/2)-1:0]); + assign wr_en_c1[t] = pkt_val_array1[t][pkt_array_depth-1] | (|pkt_eop_array[t][pkt_array_depth-1:(pkt_array_depth/2)]); + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + wr_en_0[t] <= 1'b0; + wr_en_1[t] <= 1'b0; + end else begin + wr_en_0[t] <= pkt_val_array[t][(pkt_array_depth/2)-1] | (|pkt_eop_array[t][(pkt_array_depth/2)-1:0]); + wr_en_1[t] <= pkt_val_array[t][pkt_array_depth-1] | (|pkt_eop_array[t][pkt_array_depth-1:(pkt_array_depth/2)]); + end + end +end +endgenerate + +reg [`segment_width-1:0] pkt_data_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_buf_in_p0 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pkt_data_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_val_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_eop_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pkt_err_buf_in_p1 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_buf1_aempty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_aempty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_empty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_buf1_empty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_data_valid_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_data_valid_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_rd_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_rd_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_wr_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_wr_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_1 [`num_axis_ports-1:0]; + +wire [`segment_width-1:0] pkt_data_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pkt_mty_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_val_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_eop_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_err_buf_out_p0 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pkt_data_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pkt_mty_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_val_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_eop_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pkt_err_buf_out_p1 [`num_axis_ports-1:0]; + +genvar u,v; + +generate +for (u=0; u<`num_axis_ports; u=u+1) begin + for (v=0; v<(pkt_array_depth/2); v=v+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_buf_in_p0[u][v] <= 1'b0; + pkt_eop_buf_in_p0[u][v] <= 1'b0; + pkt_err_buf_in_p0[u][v] <= 1'b0; + pkt_val_buf_in_p1[u][v] <= 1'b0; + pkt_eop_buf_in_p1[u][v] <= 1'b0; + pkt_err_buf_in_p1[u][v] <= 1'b0; + end else begin + pkt_val_buf_in_p0[u][v] <= pkt_val_array[u][v]; + pkt_data_buf_in_p0[u][v] <= pkt_data_array[u][v]; + pkt_mty_buf_in_p0[u][v] <= pkt_mty_array[u][v]; + pkt_eop_buf_in_p0[u][v] <= pkt_eop_array[u][v]; + pkt_err_buf_in_p0[u][v] <= pkt_err_array[u][v]; + pkt_val_buf_in_p1[u][v] <= pkt_val_array[u][v+(pkt_array_depth/2)]; + pkt_data_buf_in_p1[u][v] <= pkt_data_array[u][v+(pkt_array_depth/2)]; + pkt_mty_buf_in_p1[u][v] <= pkt_mty_array[u][v+(pkt_array_depth/2)]; + pkt_eop_buf_in_p1[u][v] <= pkt_eop_array[u][v+(pkt_array_depth/2)]; + pkt_err_buf_in_p1[u][v] <= pkt_err_array[u][v+(pkt_array_depth/2)]; + end + end + end +end +endgenerate + +genvar w,x; +generate +for (w=0; w<`num_axis_ports; w=w+1) begin + for (x=0; x<(pkt_array_depth/2); x=x+1) begin + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1002"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_stage1_p0 ( + .almost_empty(unseg_buf1_aempty_0[w][x]), + .almost_full(), + .data_valid(unseg_data_valid_0[w][x]), + .dbiterr(), + .dout({pkt_mty_buf_out_p0[w][x],pkt_err_buf_out_p0[w][x],pkt_eop_buf_out_p0[w][x],pkt_val_buf_out_p0[w][x],pkt_data_buf_out_p0[w][x]}), + .empty(unseg_buf1_empty_0[w][x]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_0[w][x]), + .rd_data_count(), + .rd_rst_busy(unseg_rd_rst_busy_0[w][x]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_wr_rst_busy_0[w][x]), + .din({pkt_mty_buf_in_p0[w][x],pkt_err_buf_in_p0[w][x],pkt_eop_buf_in_p0[w][x],pkt_val_buf_in_p0[w][x],pkt_data_buf_in_p0[w][x]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en_0[w] & !outbuff_pfull[w] & !unseg_data_valid_0[w][x]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en_0[w] & !unseg_wr_rst_busy_0[w][x]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("1002"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_stage1_p1 ( + .almost_empty(unseg_buf1_aempty_1[w][x]), + .almost_full(), + .data_valid(unseg_data_valid_1[w][x]), + .dbiterr(), + .dout({pkt_mty_buf_out_p1[w][x],pkt_err_buf_out_p1[w][x],pkt_eop_buf_out_p1[w][x],pkt_val_buf_out_p1[w][x],pkt_data_buf_out_p1[w][x]}), + .empty(unseg_buf1_empty_1[w][x]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_1[w][x]), + .rd_data_count(), + .rd_rst_busy(unseg_rd_rst_busy_1[w][x]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_wr_rst_busy_1[w][x]), + .din({pkt_mty_buf_in_p1[w][x],pkt_err_buf_in_p1[w][x],pkt_eop_buf_in_p1[w][x],pkt_val_buf_in_p1[w][x],pkt_data_buf_in_p1[w][x]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en_1[w] & !outbuff_pfull[w] & !unseg_data_valid_1[w][x]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en_1[w] & !unseg_wr_rst_busy_1[w][x]) + ); + end + assign port_unseg_out_pfull[w] = (|unseg_out_buf1_pfull_0[w]) | (|unseg_out_buf1_pfull_1[w]); +end +endgenerate + +assign ports_not_rdy = &port_unseg_out_pfull; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet readout / array port arbitration + +reg [`num_axis_ports-1:0] port_sel; +reg [`num_axis_ports-1:0] port_sel_1; + +genvar y; + +generate +for (y=0; y<`num_axis_ports; y=y+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + rd_en_0[y] <= 1'b0; + rd_en_1[y] <= 1'b0; + port_sel[y] <= 1'b0; + port_sel_1[y] <= 1'b0; + end else if (!outbuff_pfull[y]) begin + rd_en_0[y] <= 1'b0; + rd_en_1[y] <= 1'b0; + port_sel_1[y] <= port_sel[y]; + if (port_sel[y]) begin + rd_en_0[y] <= 1'b0; + if (!(|unseg_buf1_empty_1[y]) && !(|unseg_rd_rst_busy_1[y])) begin + rd_en_1[y] <= 1'b1; + port_sel[y] <= 1'b0; + end else begin + rd_en_1[y] <= 1'b0; + port_sel[y] <= port_sel[y]; + end + end else begin + rd_en_1[y] <= 1'b0; + if (!(|unseg_buf1_empty_0[y]) && !(|unseg_rd_rst_busy_0[y])) begin + rd_en_0[y] <= 1'b1; + port_sel[y] <= 1'b1; + end else begin + rd_en_0[y] <= 1'b0; + port_sel[y] <= port_sel[y]; + end + end + end + end +end +endgenerate + +genvar z, zz; + +generate +for (z=0; z<`num_axis_ports; z=z+1) begin :packet_out_mux + for (zz=0; zz<(pkt_array_depth/2); zz=zz+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_out_0[z][zz] <= 1'b0; + pkt_mty_out_0[z][zz] <= {seg_mty_w{1'b1}}; + pkt_eop_out_0[z][zz] <= 1'b0; + pkt_err_out_0[z][zz] <= 1'b0; + end else begin + pkt_val_out_0[z][zz] <= 1'b0; + if (port_sel_1[z]) begin + pkt_val_out_0[z][zz] <= pkt_val_buf_out_p0[z][zz] & unseg_data_valid_0[z][zz]; + pkt_mty_out_0[z][zz] <= pkt_mty_buf_out_p0[z][zz]; + pkt_eop_out_0[z][zz] <= pkt_eop_buf_out_p0[z][zz]; + pkt_err_out_0[z][zz] <= pkt_err_buf_out_p0[z][zz]; + pkt_data_out_0[z][zz] <= pkt_data_buf_out_p0[z][zz]; + end else begin + pkt_val_out_0[z][zz] <= pkt_val_buf_out_p1[z][zz] & unseg_data_valid_1[z][zz]; + pkt_mty_out_0[z][zz] <= pkt_mty_buf_out_p1[z][zz]; + pkt_eop_out_0[z][zz] <= pkt_eop_buf_out_p1[z][zz]; + pkt_err_out_0[z][zz] <= pkt_err_buf_out_p1[z][zz]; + pkt_data_out_0[z][zz] <= pkt_data_buf_out_p1[z][zz]; + end + end + end + end +end +endgenerate + +`else // 100G or 200G + +reg [`segment_width-1:0] pktout_data_array [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [seg_mty_w-1:0] pktout_mty_array [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array0 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array00 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array1 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array2 [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_val_array [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_eop_array [`num_axis_ports-1:0]; +reg [pkt_array_depth*2-1:0] pktout_err_array [`num_axis_ports-1:0]; + +reg [$clog2(pkt_array_depth*2)-1:0] pktout_array_ptr [`num_axis_ports-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pktout_seg_sel_reg [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; +reg [$clog2(pkt_array_depth)-1:0] pktout_seg_sel_reg1 [`num_axis_ports-1:0] [pkt_array_depth*2-1:0]; + +wire [`num_axis_ports-1:0] wr_en_c0; +wire [`num_axis_ports-1:0] wr_en_c1; +wire [`num_axis_ports-1:0] wr_en_c2; +wire [`num_axis_ports-1:0] wr_en_c3; + +reg [`num_axis_ports-1:0] wr_en0; +reg [`num_axis_ports-1:0] wr_en1; +reg [`num_axis_ports-1:0] wr_en2; +reg [`num_axis_ports-1:0] wr_en3; + +genvar q; +integer r, rr; +generate +for (q=0; q < `num_axis_ports; q = q+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_array_ptr[q] = 0; + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pktout_val_array0 [q][r] <= 1'b0; + pktout_val_array1 [q][r] <= 1'b0; + pktout_seg_sel_reg[q][r] <= 'd0; + pktout_val_array0 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_val_array1 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_seg_sel_reg[q][r+pkt_array_depth/2] <= 'd0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_val_array1 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_seg_sel_reg[q][r+(pkt_array_depth/2)*2] <= 'd0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + pktout_val_array1 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + pktout_seg_sel_reg[q][r+(pkt_array_depth/2)*3] <= 'd0; + end + end else begin + for(r=0; r < pkt_array_depth/2; r = r+1) begin + pktout_val_array0 [q][r] <= 1'b0; + pktout_val_array0 [q][r+pkt_array_depth/2] <= 1'b0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*2] <= 1'b0; + pktout_val_array0 [q][r+(pkt_array_depth/2)*3] <= 1'b0; + end + if (wr_en_c0[q]) begin + for(rr=0; rr < pkt_array_depth/2; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c1[q]) begin + for(rr=pkt_array_depth/2; rr < pkt_array_depth; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c2[q]) begin + for(rr=pkt_array_depth; rr < (pkt_array_depth/2)*3; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + if (wr_en_c3[q]) begin + for(rr=(pkt_array_depth/2)*3; rr < (pkt_array_depth/2)*4; rr = rr+1) begin + pktout_val_array1 [q][rr] <= 1'b0; + end + end + for(r=0; r < `num_segments; r = r+1) begin + if (pkt_val[q][r]) begin + pktout_val_array0 [q][pktout_array_ptr[q]] <= 1'b1; + pktout_val_array1 [q][pktout_array_ptr[q]] <= 1'b1; + pktout_seg_sel_reg[q][pktout_array_ptr[q]] <= r; + if (pkt_eop[q][r]) begin + if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b11) + pktout_array_ptr[q] = 0; + else if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b10) + pktout_array_ptr[q] = (pkt_array_depth/2)*3; + else if (pktout_array_ptr[q][$clog2(pkt_array_depth*2)-1:$clog2(pkt_array_depth*2)-2] == 2'b01) + pktout_array_ptr[q] = pkt_array_depth; + else + pktout_array_ptr[q] = pkt_array_depth/2; + end else + pktout_array_ptr[q] = pktout_array_ptr[q] + 1; + end + end + end + end +end +endgenerate + +genvar s, array_depth0; +generate +for (s=0; s < `num_axis_ports; s = s+1) begin + always @ (posedge aclk_axis_unseg) begin + pktout_val_array2[s] <= pktout_val_array1[s]; + pktout_val_array[s] <= pktout_val_array2[s]; + pktout_val_array00[s] <= pktout_val_array0[s]; + end + for (array_depth0=0; array_depth0 < pkt_array_depth*2; array_depth0 = array_depth0+1) begin + always @ (posedge aclk_axis_unseg) begin + pktout_seg_sel_reg1[s][array_depth0] <= pktout_seg_sel_reg[s][array_depth0]; + end + end + for (array_depth0=0; array_depth0 < pkt_array_depth*2; array_depth0 = array_depth0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_eop_array[s][array_depth0] <= 1'b0; + pktout_err_array[s][array_depth0] <= 1'b0; + pktout_mty_array[s][array_depth0] <= 'd0; + pktout_data_array[s][array_depth0] <= 'd0; + end else begin + if (pktout_val_array00[s][array_depth0]) begin + pktout_eop_array[s][array_depth0] <= pkt_eop2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_err_array[s][array_depth0] <= pkt_err2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_mty_array[s][array_depth0] <= pkt_mty2 [s][pktout_seg_sel_reg1[s][array_depth0]]; + pktout_data_array[s][array_depth0] <= pkt_data2[s][pktout_seg_sel_reg1[s][array_depth0]]; + end else begin + pktout_eop_array[s][array_depth0] <= 1'b0; + pktout_err_array[s][array_depth0] <= 1'b0; + end + end + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Buffering packed segments + +reg rd_en0; +reg rd_en1; +reg rd_en2; +reg rd_en3; + +genvar t; + +generate +for (t=0; t<`num_axis_ports; t=t+1) begin + assign wr_en_c0[t] = pktout_val_array1[t][(pkt_array_depth/2)-1] | (|pktout_eop_array[t][(pkt_array_depth/2)-1:0]); + assign wr_en_c1[t] = pktout_val_array1[t][((pkt_array_depth/2)*2)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)]); + assign wr_en_c2[t] = pktout_val_array1[t][((pkt_array_depth/2)*3)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*3)-1:((pkt_array_depth/2)*2)]); + assign wr_en_c3[t] = pktout_val_array1[t][(pkt_array_depth*2)-1] | (|pktout_eop_array[t][(pkt_array_depth*2)-1:((pkt_array_depth/2)*3)]); + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + wr_en0[t] <= 1'b0; + wr_en1[t] <= 1'b0; + wr_en2[t] <= 1'b0; + wr_en3[t] <= 1'b0; + end else begin + wr_en0[t] <= pktout_val_array[t][(pkt_array_depth/2)-1] | (|pktout_eop_array[t][(pkt_array_depth/2)-1:0]); + wr_en1[t] <= pktout_val_array[t][((pkt_array_depth/2)*2)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)]); + wr_en2[t] <= pktout_val_array[t][((pkt_array_depth/2)*3)-1] | (|pktout_eop_array[t][((pkt_array_depth/2)*3)-1:((pkt_array_depth/2)*2)]); + wr_en3[t] <= pktout_val_array[t][(pkt_array_depth*2)-1] | (|pktout_eop_array[t][(pkt_array_depth*2)-1:((pkt_array_depth/2)*3)]); + end + end +end +endgenerate + +reg [`segment_width-1:0] pktout_data_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p0 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p0 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p1 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p1 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p2 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p2 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p2 [`num_axis_ports-1:0]; +reg [`segment_width-1:0] pktout_data_buf_in_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [seg_mty_w-1:0] pktout_mty_buf_in_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_val_buf_in_p3 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_eop_buf_in_p3 [`num_axis_ports-1:0]; +reg [(pkt_array_depth/2)-1:0] pktout_err_buf_in_p3 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_aempty_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_empty_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_data_valid_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_rd_rst_busy_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_wr_rst_busy_3 [`num_axis_ports-1:0]; + +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_afull_3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] unseg_out_buf1_pfull_3 [`num_axis_ports-1:0]; + +wire [`segment_width-1:0] pktout_data_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p0 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p0 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p0 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p1 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p1 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p1 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p2 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_eop_buf_out_p2 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_err_buf_out_p2 [`num_axis_ports-1:0]; +wire [`segment_width-1:0] pktout_data_buf_out_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [seg_mty_w-1:0] pktout_mty_buf_out_p3 [`num_axis_ports-1:0] [(pkt_array_depth/2)-1:0]; +wire [(pkt_array_depth/2)-1:0] pktout_val_buf_out_p3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1: 0] pktout_eop_buf_out_p3 [`num_axis_ports-1:0]; +wire [(pkt_array_depth/2)-1: 0] pktout_err_buf_out_p3 [`num_axis_ports-1:0]; + +genvar u1,v1; + +generate +for (u1=0; u1<`num_axis_ports; u1=u1+1) begin + for (v1=0; v1<(pkt_array_depth/2); v1=v1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pktout_val_buf_in_p0[u1][v1] <= 1'b0; + pktout_eop_buf_in_p0[u1][v1] <= 1'b0; + pktout_err_buf_in_p0[u1][v1] <= 1'b0; + pktout_val_buf_in_p1[u1][v1] <= 1'b0; + pktout_eop_buf_in_p1[u1][v1] <= 1'b0; + pktout_err_buf_in_p1[u1][v1] <= 1'b0; + pktout_val_buf_in_p2[u1][v1] <= 1'b0; + pktout_eop_buf_in_p2[u1][v1] <= 1'b0; + pktout_err_buf_in_p2[u1][v1] <= 1'b0; + pktout_val_buf_in_p3[u1][v1] <= 1'b0; + pktout_eop_buf_in_p3[u1][v1] <= 1'b0; + pktout_err_buf_in_p3[u1][v1] <= 1'b0; + end else begin + pktout_val_buf_in_p0[u1][v1] <= pktout_val_array[u1][v1]; + pktout_data_buf_in_p0[u1][v1] <= pktout_data_array[u1][v1]; + pktout_mty_buf_in_p0[u1][v1] <= pktout_mty_array[u1][v1]; + pktout_eop_buf_in_p0[u1][v1] <= pktout_eop_array[u1][v1]; + pktout_err_buf_in_p0[u1][v1] <= pktout_err_array[u1][v1]; + pktout_val_buf_in_p1[u1][v1] <= pktout_val_array[u1][v1+(pkt_array_depth/2)]; + pktout_data_buf_in_p1[u1][v1] <= pktout_data_array[u1][v1+(pkt_array_depth/2)]; + pktout_mty_buf_in_p1[u1][v1] <= pktout_mty_array[u1][v1+(pkt_array_depth/2)]; + pktout_eop_buf_in_p1[u1][v1] <= pktout_eop_array[u1][v1+(pkt_array_depth/2)]; + pktout_err_buf_in_p1[u1][v1] <= pktout_err_array[u1][v1+(pkt_array_depth/2)]; + pktout_val_buf_in_p2[u1][v1] <= pktout_val_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_data_buf_in_p2[u1][v1] <= pktout_data_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_mty_buf_in_p2[u1][v1] <= pktout_mty_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_eop_buf_in_p2[u1][v1] <= pktout_eop_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_err_buf_in_p2[u1][v1] <= pktout_err_array[u1][v1+((pkt_array_depth/2)*2)]; + pktout_val_buf_in_p3[u1][v1] <= pktout_val_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_data_buf_in_p3[u1][v1] <= pktout_data_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_mty_buf_in_p3[u1][v1] <= pktout_mty_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_eop_buf_in_p3[u1][v1] <= pktout_eop_array[u1][v1+((pkt_array_depth/2)*3)]; + pktout_err_buf_in_p3[u1][v1] <= pktout_err_array[u1][v1+((pkt_array_depth/2)*3)]; + end + end + end +end +endgenerate + +genvar w1,x1; +generate +for (w1=0; w1<`num_axis_ports; w1=w1+1) begin + for (x1=0; x1<(pkt_array_depth/2); x1=x1+1) begin + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p0 ( + .almost_empty(unseg_out_buf1_aempty_0[w1][x1]), + .almost_full(unseg_out_buf1_afull_0[w1][x1]), + .data_valid(unseg_out_data_valid_0[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p0[w1][x1],pktout_err_buf_out_p0[w1][x1],pktout_eop_buf_out_p0[w1][x1],pktout_val_buf_out_p0[w1][x1],pktout_data_buf_out_p0[w1][x1]}), + .empty(unseg_out_buf1_empty_0[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_0[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_0[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_0[w1][x1]), + .din({pktout_mty_buf_in_p0[w1][x1],pktout_err_buf_in_p0[w1][x1],pktout_eop_buf_in_p0[w1][x1],pktout_val_buf_in_p0[w1][x1],pktout_data_buf_in_p0[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en0 & !outbuff_pfull & !unseg_out_data_valid_0[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en0[w1] & !unseg_out_wr_rst_busy_0[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p1 ( + .almost_empty(unseg_out_buf1_aempty_1[w1][x1]), + .almost_full(unseg_out_buf1_afull_1[w1][x1]), + .data_valid(unseg_out_data_valid_1[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p1[w1][x1],pktout_err_buf_out_p1[w1][x1],pktout_eop_buf_out_p1[w1][x1],pktout_val_buf_out_p1[w1][x1],pktout_data_buf_out_p1[w1][x1]}), + .empty(unseg_out_buf1_empty_1[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_1[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_1[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_1[w1][x1]), + .din({pktout_mty_buf_in_p1[w1][x1],pktout_err_buf_in_p1[w1][x1],pktout_eop_buf_in_p1[w1][x1],pktout_val_buf_in_p1[w1][x1],pktout_data_buf_in_p1[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en1 & !outbuff_pfull & !unseg_out_data_valid_1[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en1[w1] & !unseg_out_wr_rst_busy_1[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p2 ( + .almost_empty(unseg_out_buf1_aempty_2[w1][x1]), + .almost_full(unseg_out_buf1_afull_2[w1][x1]), + .data_valid(unseg_out_data_valid_2[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p2[w1][x1],pktout_err_buf_out_p2[w1][x1],pktout_eop_buf_out_p2[w1][x1],pktout_val_buf_out_p2[w1][x1],pktout_data_buf_out_p2[w1][x1]}), + .empty(unseg_out_buf1_empty_2[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_2[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_2[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_2[w1][x1]), + .din({pktout_mty_buf_in_p2[w1][x1],pktout_err_buf_in_p2[w1][x1],pktout_eop_buf_in_p2[w1][x1],pktout_val_buf_in_p2[w1][x1],pktout_data_buf_in_p2[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en2 & !outbuff_pfull & !unseg_out_data_valid_2[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en2[w1] & !unseg_out_wr_rst_busy_2[w1][x1]) + ); + + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(pktarry_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(3), + .PROG_FULL_THRESH(pktarry_buff_pfull_thresh), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+3), + .READ_MODE("std"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+3), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_out_stage1_p3 ( + .almost_empty(unseg_out_buf1_aempty_3[w1][x1]), + .almost_full(unseg_out_buf1_afull_3[w1][x1]), + .data_valid(unseg_out_data_valid_3[w1][x1]), + .dbiterr(), + .dout({pktout_mty_buf_out_p3[w1][x1],pktout_err_buf_out_p3[w1][x1],pktout_eop_buf_out_p3[w1][x1],pktout_val_buf_out_p3[w1][x1],pktout_data_buf_out_p3[w1][x1]}), + .empty(unseg_out_buf1_empty_3[w1][x1]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_out_buf1_pfull_3[w1][x1]), + .rd_data_count(), + .rd_rst_busy(unseg_out_rd_rst_busy_3[w1][x1]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_out_wr_rst_busy_3[w1][x1]), + .din({pktout_mty_buf_in_p3[w1][x1],pktout_err_buf_in_p3[w1][x1],pktout_eop_buf_in_p3[w1][x1],pktout_val_buf_in_p3[w1][x1],pktout_data_buf_in_p3[w1][x1]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(rd_en3 & !outbuff_pfull & !unseg_out_data_valid_3[w1][x1]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(wr_en3[w1] & !unseg_out_wr_rst_busy_3[w1][x1]) + ); + + end + assign port_unseg_out_pfull[w1] = (|unseg_out_buf1_pfull_0[w1]) | (|unseg_out_buf1_pfull_1[w1]) | (|unseg_out_buf1_pfull_2[w1]) | (|unseg_out_buf1_pfull_3[w1]); +end +endgenerate + +assign ports_not_rdy = &port_unseg_out_pfull; + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet readout / array port arbitration + +reg [1:0] outport_sel; +reg [1:0] outport_sel_1; +reg [1:0] outport_sel_2; + +wire pktout_buff_rdy; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + outport_sel <= 2'b00; + outport_sel_1 <= 2'b00; + outport_sel_2 <= 2'b00; + end else if (!outbuff_pfull) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + outport_sel_1 <= outport_sel; + outport_sel_2 <= outport_sel_1; + if (outport_sel == 2'b11) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + if (!(|unseg_out_buf1_empty_3[0]) && !(|unseg_out_rd_rst_busy_3[0])) begin + rd_en3 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en3 <= 1'b0; + outport_sel <= outport_sel; + end + end else if (outport_sel == 2'b10) begin + rd_en0 <= 1'b0; + rd_en1 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_2[0]) && !(|unseg_out_rd_rst_busy_2[0])) begin + rd_en2 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en2 <= 1'b0; + outport_sel <= outport_sel; + end + end else if (outport_sel == 2'b01) begin + rd_en0 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_1[0]) && !(|unseg_out_rd_rst_busy_1[0])) begin + rd_en1 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en1 <= 1'b0; + outport_sel <= outport_sel; + end + end else begin + rd_en1 <= 1'b0; + rd_en2 <= 1'b0; + rd_en3 <= 1'b0; + if (!(|unseg_out_buf1_empty_0[0]) && !(|unseg_out_rd_rst_busy_0[0])) begin + rd_en0 <= 1'b1; + outport_sel <= outport_sel+1; + end else begin + rd_en0 <= 1'b0; + outport_sel <= outport_sel; + end + end + end +end + +genvar z1, z2; + +generate +for (z1=0; z1<`num_axis_ports; z1=z1+1) begin : packetout_mux + for (z2=0; z2<(pkt_array_depth/2); z2=z2+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_val_out_0[z1][z2] <= 1'b0; + pkt_mty_out_0[z1][z2] <= {seg_mty_w{1'b1}}; + pkt_eop_out_0[z1][z2] <= 1'b0; + pkt_err_out_0[z1][z2] <= 1'b0; + end else begin + pkt_val_out_0[z1][z2] <= 1'b0; + if (outport_sel_2 == 2'b11) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p3[z1][z2] & unseg_out_data_valid_3[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p3[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p3[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p3[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p3[z1][z2]; + end else if (outport_sel_2 == 2'b10) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p2[z1][z2] & unseg_out_data_valid_2[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p2[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p2[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p2[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p2[z1][z2]; + end else if (outport_sel_2 == 2'b01) begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p1[z1][z2] & unseg_out_data_valid_1[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p1[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p1[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p1[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p1[z1][z2]; + end else begin + pkt_val_out_0[z1][z2] <= pktout_val_buf_out_p0[z1][z2] & unseg_out_data_valid_0[z1][z2]; + pkt_mty_out_0[z1][z2] <= pktout_mty_buf_out_p0[z1][z2]; + pkt_eop_out_0[z1][z2] <= pktout_eop_buf_out_p0[z1][z2]; + pkt_err_out_0[z1][z2] <= pktout_err_buf_out_p0[z1][z2]; + pkt_data_out_0[z1][z2] <= pktout_data_buf_out_p0[z1][z2]; + end + end + end + end +end +endgenerate + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Packet segments to axi stream conversion (each segments as independant streams) + +integer a, b; +reg [`num_axis_ports-1:0] eop_flag; + +generate +always @ (posedge aclk_axis_unseg) begin : packet_to_axi_stream + if (!aresetn_axis_unseg) begin + for (a=0; a<`num_axis_ports; a=a+1) begin + eop_flag[a] = 0; + for (b=0; b<(pkt_array_depth/2); b=b+1) begin + pkt_tvalid[a][b] <= 1'b0; + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + pkt_tlast[a][b] <= 1'b0; + pkt_tuser[a][b] <= 1'b0; + end + end + end else begin + for (a=0; a<`num_axis_ports; a=a+1) begin + eop_flag[a] = 0; + for (b=0; b<(pkt_array_depth/2); b=b+1) begin + pkt_tvalid[a][b] <= pkt_val_out_0[a][b]; + pkt_tdata[a][b] <= pkt_data_out_0[a][b]; + pkt_tlast[a][b] <= pkt_eop_out_0[a][b]; + pkt_tuser[a][b] <= pkt_err_out_0[a][b]; + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + if (eop_flag[a]) + pkt_tkeep[a][b] <= {(`segment_width/8){1'b0}}; + else begin + pkt_tkeep[a][b] <= (2**((2**(seg_mty_w)) - pkt_mty_out_0[a][b]))-1; + if (pkt_eop_out_0[a][b]) + eop_flag[a] = 1; + else + eop_flag[a] = 0; + end + end + end + end +end +endgenerate + +//----------------- Combine to single axi stream + +genvar c, d; +generate +for (c=0; c<`num_axis_ports; c=c+1) begin : axi_stream_combine + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + axis_tvalid_buf_in[c] <= 1'b0; + axis_tlast_buf_in[c] <= 1'b0; + axis_tuser_buf_in[c] <= 1'b0; + end else begin + if (axis_tready_buf_in[c]) begin + axis_tvalid_buf_in[c] <= | pkt_tvalid[c]; + axis_tlast_buf_in[c] <= | pkt_tlast[c]; + axis_tuser_buf_in[c] <= | pkt_tuser[c]; + end + end + end + for (d=0; d<(pkt_array_depth/2); d=d+1) begin + always @ (posedge aclk_axis_unseg) begin + axis_tdata_buf_in[c][(`segment_width+(`segment_width*d))-1:(`segment_width*d)] <= pkt_tdata[c][d]; + axis_tkeep_buf_in[c][((`segment_width/8)+((`segment_width/8)*d))-1:((`segment_width/8)*d)] <= pkt_tkeep[c][d]; + end + end +end +endgenerate + +//----------------- Output buffer + +wire [(`segment_width*(pkt_array_depth/2))-1:0] axis_tdata_buf_out [`num_axis_ports-1:0]; +wire [((`segment_width/8)*(pkt_array_depth/2))-1:0] axis_tkeep_buf_out [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_buf_out; +wire [`num_axis_ports-1:0] axis_tlast_buf_out; +wire [`num_axis_ports-1:0] axis_tuser_buf_out; +wire [`num_axis_ports-1:0] axis_tready_buf_out; +wire [`num_axis_ports-1:0] axis_out_buff_pfull; + +genvar e; + +generate +for (e=0; e<`num_axis_ports; e=e+1) begin : axis_out_buffer + xpm_fifo_axis #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .CLOCKING_MODE("common_clock"), + .ECC_MODE("no_ecc"), + .FIFO_DEPTH(out_buff_depth), + .FIFO_MEMORY_TYPE("auto"), + .PACKET_FIFO("true"), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(out_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .TDATA_WIDTH((pkt_array_depth/2)*`segment_width), + .TDEST_WIDTH(1), + .TID_WIDTH(1), + .TUSER_WIDTH(1), + .USE_ADV_FEATURES("0003"), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_axis_unseg_out ( + .m_aclk(aclk_axis_unseg), + .m_axis_tready(axis_tready_buf_out[e]), + .m_axis_tdata(axis_tdata_buf_out[e]), + .m_axis_tkeep(axis_tkeep_buf_out[e]), + .m_axis_tlast(axis_tlast_buf_out[e]), + .m_axis_tuser(axis_tuser_buf_out[e]), + .m_axis_tvalid(axis_tvalid_buf_out[e]), + .s_aclk(aclk_axis_unseg), + .s_aresetn(aresetn_axis_unseg), + .prog_full_axis(axis_out_buff_pfull[e]), + .injectdbiterr_axis(1'b0), + .injectsbiterr_axis(1'b0), + .s_axis_tready(axis_tready_buf_in[e]), + .s_axis_tdata(axis_tdata_buf_in[e]), + .s_axis_tkeep(axis_tkeep_buf_in[e]), + .s_axis_tlast(axis_tlast_buf_in[e]), + .s_axis_tuser(axis_tuser_buf_in[e]), + .s_axis_tvalid(axis_tvalid_buf_in[e]) + ); +end +endgenerate + +assign outbuff_pfull = axis_out_buff_pfull; + +assign m_axis0_tdata = axis_tdata_buf_out[0]; +assign m_axis0_tkeep = axis_tkeep_buf_out[0]; +assign m_axis0_tlast = axis_tlast_buf_out[0]; +assign m_axis0_tuser = axis_tuser_buf_out[0]; +assign m_axis0_tvalid = axis_tvalid_buf_out[0]; +assign axis_tready_buf_out[0] = m_axis0_tready; + +`ifdef en_axis1 +assign m_axis1_tdata = axis_tdata_buf_out[1]; +assign m_axis1_tkeep = axis_tkeep_buf_out[1]; +assign m_axis1_tlast = axis_tlast_buf_out[1]; +assign m_axis1_tuser = axis_tuser_buf_out[1]; +assign m_axis1_tvalid = axis_tvalid_buf_out[1]; +assign axis_tready_buf_out[1] = m_axis1_tready; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Port Statistics + +`ifdef statistics_en + localparam statistics_en = 1; +`else + localparam statistics_en = 0; +`endif + +generate + +if (statistics_en) begin + +//----------------- Input packet count + +reg [63:0] segment_pkt_cnt [`num_segments-1:0]; +reg [63:0] segment_err_cnt [`num_segments-1:0]; +reg [63:0] segment_byte_cnt [`num_segments-1:0]; +wire [($clog2(`segment_width/8)):0] segment_validbytes [`num_segments-1:0]; +reg [63:0] total_pktin_cnt; +reg [63:0] total_err_pktin_cnt; +reg [63:0] total_pktin_byte_cnt; + +genvar ab; + +for (ab=0; ab<`num_segments; ab=ab+1) begin + mty_to_validbytes u_mty_to_valbytes + ( + .mty_in(seg2unseg_mty[ab]), + .valid_bytes_out(segment_validbytes[ab]) + ); +end + +genvar cd; + +for (cd=0; cd<`num_segments; cd=cd+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_byte_cnt[cd] <= 'd0; + else if (seg2unseg_val[cd]) + segment_byte_cnt[cd] <= segment_byte_cnt[cd] + segment_validbytes[cd]; + end +end + +integer ef; + +always @ (*) begin + total_pktin_byte_cnt = 'd0; + for (ef=0; ef<`num_segments; ef=ef+1) begin + total_pktin_byte_cnt = total_pktin_byte_cnt + segment_byte_cnt[ef]; + end +end + +genvar gh; + +for (gh=0; gh<`num_segments; gh=gh+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_pkt_cnt[gh] <= 'd0; + else if (seg2unseg_val[gh] && seg2unseg_eop[gh]) + segment_pkt_cnt[gh] <= segment_pkt_cnt[gh] + 1; + end + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_err_cnt[gh] <= 'd0; + else if (seg2unseg_val[gh] && seg2unseg_eop[gh] && seg2unseg_err[gh]) + segment_err_cnt[gh] <= segment_err_cnt[gh] + 1; + end +end + +integer ij; + +always @ (*) begin + total_pktin_cnt = 'd0; + total_err_pktin_cnt = 'd0; + for (ij=0; ij<`num_segments; ij=ij+1) begin + total_pktin_cnt = total_pktin_cnt + segment_pkt_cnt[ij]; + total_err_pktin_cnt = total_err_pktin_cnt + segment_err_cnt[ij]; + end +end + +//----------------- Output packet count + +reg [63:0] port_pkt_out_cnt [`num_axis_ports-1:0]; +reg [63:0] port_err_out_cnt [`num_axis_ports-1:0]; +reg [63:0] port_pkt_byte_cnt [`num_axis_ports-1:0]; +reg [63:0] total_pktout_cnt; +reg [63:0] total_err_pktout_cnt; +reg [63:0] total_pktout_byte_cnt; + +wire [($clog2(`unseg_axis_w/8)):0] port_valid_bytes [`num_axis_ports-1:0]; + +genvar g; +for (g=0; g<`num_axis_ports; g=g+1) begin + tkeep_to_validbytes u_tkeep_to_valbytes + ( + .tkeep_in(axis_tkeep_buf_out[g]), + .valid_bytes_out(port_valid_bytes[g]) + ); +end + +genvar i; +for (i=0; i<`num_axis_ports; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_out_cnt[i] <= 'd0; + else + if (axis_tvalid_buf_out[i] && axis_tready_buf_out[i] && axis_tlast_buf_out[i]) + port_pkt_out_cnt[i] <= port_pkt_out_cnt[i] + 'd1; + end + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_err_out_cnt[i] <= 'd0; + else + if (axis_tvalid_buf_out[i] && axis_tready_buf_out[i] && axis_tlast_buf_out[i] && axis_tuser_buf_out[i]) + port_err_out_cnt[i] <= port_err_out_cnt[i] + 'd1; + end +end + +genvar j; +for (j=0; j<`num_axis_ports; j=j+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_byte_cnt[j] <= 'd0; + else + if (axis_tvalid_buf_out[j] && axis_tready_buf_out[j]) + port_pkt_byte_cnt[j] <= port_pkt_byte_cnt[j] + port_valid_bytes[j]; + end +end + +integer k; +always @ (*) begin + total_pktout_cnt = 'd0; + total_err_pktout_cnt = 'd0; + total_pktout_byte_cnt = 'd0; + for (k=0; k<`num_axis_ports; k=k+1) begin + total_pktout_cnt = total_pktout_cnt + port_pkt_out_cnt[k]; + total_err_pktout_cnt = total_err_pktout_cnt + port_err_out_cnt[k]; + total_pktout_byte_cnt = total_pktout_byte_cnt + port_pkt_byte_cnt[k]; + end +end + +assign total_pkt_in_cnt = total_pktin_cnt; +assign total_err_pkt_in_cnt = total_err_pktin_cnt; +assign total_pkt_in_byte_cnt = total_pktin_byte_cnt; +assign total_pkt_out_cnt = total_pktout_cnt; +assign total_err_pkt_out_cnt = total_err_pktout_cnt; +assign total_pkt_out_byte_cnt = total_pktout_byte_cnt; +`ifdef en_axis1 +assign p1_pkt_out_cnt = port_pkt_out_cnt[1]; +assign p1_err_pkt_out_cnt = port_err_out_cnt[1]; +assign p1_pkt_out_byte_cnt = port_pkt_byte_cnt[1]; +assign p0_pkt_out_cnt = port_pkt_out_cnt[0]; +assign p0_err_pkt_out_cnt = port_err_out_cnt[0]; +assign p0_pkt_out_byte_cnt = port_pkt_byte_cnt[0]; +`endif + +end + +endgenerate + +`ifdef debug_en + +reg [`num_axis_ports-1:0] err_boken_pkt, err_boken_pkt_tlst; + +genvar k0; +integer k1; + +generate + +for (k0=0; k0<`num_axis_ports; k0=k0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt[k0] <= 1'b0; + else + err_boken_pkt[k0] <= axis_tvalid_buf_out[k0] & axis_tready_buf_out[k0] & ~axis_tlast_buf_out[k0] & ~(&axis_tkeep_buf_out[k0]); + end +end + +for (k0=0; k0<`num_axis_ports; k0=k0+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt_tlst[k0] = 1'b0; + else begin + err_boken_pkt_tlst[k0] = 1'b0; + if (axis_tlast_buf_out[k0]) begin + if (!err_boken_pkt_tlst[k0]) begin + for (k1=0; k1<(`unseg_axis_w/8)-2; k1=k1+1) begin + if (axis_tkeep_buf_out[k0][k1+1] && !axis_tkeep_buf_out[k0][k1]) + err_boken_pkt_tlst[k0] = 1'b1; + else + err_boken_pkt_tlst[k0] = 1'b0; + end + end + end else + err_boken_pkt_tlst[k0] = 1'b0; + end + end +end + + +endgenerate + +assign error_broken_packet_out = (|err_boken_pkt) | (|(err_boken_pkt_tlst & axis_tlast_buf_out & axis_tvalid_buf_out & axis_tready_buf_out)); + +`endif + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module tkeep_to_validbytes + ( + input [(`unseg_axis_w/8)-1:0] tkeep_in, + output wire [($clog2(`unseg_axis_w/8)):0] valid_bytes_out + ); + +integer i; + +reg [($clog2(`unseg_axis_w/8)):0] valid_bytes; + +always @ (tkeep_in) begin + valid_bytes = 0; + for (i=0; i<(`unseg_axis_w/8); i=i+1) + valid_bytes = valid_bytes + tkeep_in[i]; +end + +assign valid_bytes_out = valid_bytes; + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module mty_to_validbytes + ( + input [($clog2(`segment_width/8))-1:0] mty_in, + output wire [($clog2(`segment_width/8)):0] valid_bytes_out + ); + +integer i; + +reg [($clog2(`segment_width/8)):0] valid_bytes; + +always @ (mty_in) begin + valid_bytes <= (2**($clog2(`segment_width/8))) - mty_in; +end + +assign valid_bytes_out = valid_bytes; + +endmodule + + +//######################################################################################################################## + +//------------------------------------ AXIS Unsegmented to Segmented stream Converter ------------------------------------ + +module axis_unseg_to_seg_converter + ( + // AXIS Segment to Unsegment converter ports + // Clock & Resets + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_seg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET aresetn_axis_seg_in" *) + input aclk_axis_seg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_seg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_seg_in, + `ifdef independant_clk + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_axis_unseg_in CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_pktout, ASSOCIATED_RESET aresetn_axis_unseg_in" *) + input aclk_axis_unseg_in, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_axis_unseg_in RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input aresetn_axis_unseg_in, + `endif + // Segmented interface + // port0 is active for all valid configurations + // Segment 0 input + output Unseg2SegEna0_out, + output [`segment_width-1:0] Unseg2SegDat0_out, + output Unseg2SegSop0_out, + output Unseg2SegEop0_out, + output Unseg2SegErr0_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty0_out, + // Segment 1 input + output Unseg2SegEna1_out, + output [`segment_width-1:0] Unseg2SegDat1_out, + output Unseg2SegSop1_out, + output Unseg2SegEop1_out, + output Unseg2SegErr1_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty1_out, + `ifdef en_port1 + // Segment 2 input + output Unseg2SegEna2_out, + output [`segment_width-1:0] Unseg2SegDat2_out, + output Unseg2SegSop2_out, + output Unseg2SegEop2_out, + output Unseg2SegErr2_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty2_out, + // Segment 3 input + output Unseg2SegEna3_out, + output [`segment_width-1:0] Unseg2SegDat3_out, + output Unseg2SegSop3_out, + output Unseg2SegEop3_out, + output Unseg2SegErr3_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty3_out, + `endif + `ifdef en_port2 + // Segment 4 input + output Unseg2SegEna4_out, + output [`segment_width-1:0] Unseg2SegDat4_out, + output Unseg2SegSop4_out, + output Unseg2SegEop4_out, + output Unseg2SegErr4_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty4_out, + // Segment 5 input + output Unseg2SegEna5_out, + output [`segment_width-1:0] Unseg2SegDat5_out, + output Unseg2SegSop5_out, + output Unseg2SegEop5_out, + output Unseg2SegErr5_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty5_out, + `endif + `ifdef en_port3 + // Segment 6 input + output Unseg2SegEna6_out, + output [`segment_width-1:0] Unseg2SegDat6_out, + output Unseg2SegSop6_out, + output Unseg2SegEop6_out, + output Unseg2SegErr6_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty6_out, + // Segment 7 input + output Unseg2SegEna7_out, + output [`segment_width-1:0] Unseg2SegDat7_out, + output Unseg2SegSop7_out, + output Unseg2SegEop7_out, + output Unseg2SegErr7_out, + output [($clog2(`segment_width/8))-1:0] Unseg2SegMty7_out, + `endif + + // Packet output interface - Unsegmented AXI Stream + // axis0 is active for all valid configurations + // unsegmented AXIS0 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis0_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis0_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TLAST" *) + input s_axis0_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TUSER" *) + input s_axis0_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TVALID" *) + input s_axis0_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis0_pkt_in TREADY" *) + output s_axis0_tready, + + `ifdef en_axis1 + // unsegmented AXIS1 interface + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TDATA" *) + input [`unseg_axis_w-1:0] s_axis1_tdata, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TKEEP" *) + input [(`unseg_axis_w/8)-1:0] s_axis1_tkeep, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TLAST" *) + input s_axis1_tlast, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TUSER" *) + input s_axis1_tuser, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TVALID" *) + input s_axis1_tvalid, + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis1_pkt_in TREADY" *) + output s_axis1_tready, + `endif + + // Statistics + `ifdef debug_en + output wire error_missing_sop, + output wire error_broken_pkt_out, + output wire error_broken_pkt_in, + `endif + `ifdef statistics_en + `ifdef en_axis1 + output wire [63: 0] p1_pkt_in_cnt, + output wire [63: 0] p1_err_pkt_in_cnt, + output wire [63: 0] p1_pkt_in_byte_cnt, + output wire [63: 0] p0_pkt_in_cnt, + output wire [63: 0] p0_err_pkt_in_cnt, + output wire [63: 0] p0_pkt_in_byte_cnt, + `endif + output wire [63: 0] total_pkt_in_cnt, + output wire [63: 0] total_err_pkt_in_cnt, + output wire [63: 0] total_pkt_in_byte_cnt, + output wire [63: 0] total_pkt_out_cnt, + output wire [63: 0] total_err_pkt_out_cnt, + output wire [63: 0] total_pkt_out_byte_cnt, + `endif + input wire tx_axis_tready_in, + output wire tx_axis_tvalid_out + ); + +//----------------------------------------------------------------------------------------------------------------------- + +localparam P_MARK_DEBUG = "false"; + +localparam seg_mty_w = $clog2(`segment_width/8); +`ifdef data_rate_200 +localparam pkt_array_depth = `pktarray_depth/2; +`else +localparam pkt_array_depth = `pktarray_depth; +`endif +localparam local_buff_depth = 16; +localparam io_buff_depth = 32; + +// Packet block size +// Block size should be sufficient to hold atleast one complete packet of the maximum expected size. +// Also block size should be a power of 2 + +`ifdef data_rate_200 +localparam pkt_blk_depth = 512; +localparam input_buffer_depth = pkt_blk_depth; +localparam output_buffer_depth = input_buffer_depth*8*`num_axis_ports; +`else +localparam pkt_blk_depth = 512; +localparam input_buffer_depth = pkt_blk_depth; +localparam output_buffer_depth = input_buffer_depth*4*`num_axis_ports; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +wire aclk_axis_unseg; +wire aresetn_axis_unseg; + +`ifdef independant_clk + assign aclk_axis_unseg = aclk_axis_unseg_in; + assign aresetn_axis_unseg = aresetn_axis_unseg_in; +`else + assign aclk_axis_unseg = aclk_axis_seg_in; + assign aresetn_axis_unseg = aresetn_axis_seg_in; +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Input Stream buffer + +wire [`unseg_axis_w-1:0] s_axis_tdata_in [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/8)-1:0] s_axis_tkeep_in [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] s_axis_tvalid_in; +wire [`num_axis_ports-1:0] s_axis_tlast_in; +wire [`num_axis_ports-1:0] s_axis_tuser_in; +wire [`num_axis_ports-1:0] s_axis_tready_in; + +wire axis_pkt_blk_rdy_flg; +wire axis_pkt_blk_rdy_p; +reg axis_pkt_blk_rdy_flg_clr; + +assign s_axis_tdata_in[0] = s_axis0_tdata; +assign s_axis_tkeep_in[0] = s_axis0_tkeep; +assign s_axis_tvalid_in[0] = s_axis0_tvalid & (~axis_pkt_blk_rdy_flg); +assign s_axis_tlast_in[0] = s_axis0_tlast; +assign s_axis_tuser_in[0] = s_axis0_tuser; +assign s_axis0_tready = s_axis_tready_in[0] & (~axis_pkt_blk_rdy_flg); + +`ifdef en_axis1 +assign s_axis_tdata_in[1] = s_axis1_tdata; +assign s_axis_tkeep_in[1] = s_axis1_tkeep; +assign s_axis_tvalid_in[1] = s_axis1_tvalid & (~axis_pkt_blk_rdy_flg); +assign s_axis_tlast_in[1] = s_axis1_tlast; +assign s_axis_tuser_in[1] = s_axis1_tuser; +assign s_axis1_tready = s_axis_tready_in[1] & (~axis_pkt_blk_rdy_flg); +`endif + +wire [`unseg_axis_w-1:0] axis_tdata_c [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/8)-1:0] axis_tkeep_c [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_c; +wire [`num_axis_ports-1:0] axis_tlast_c; +wire [`num_axis_ports-1:0] axis_tuser_c; +wire [`num_axis_ports-1:0] axis_tready_c; + +wire [`num_axis_ports-1:0] axis_in_buff_pfull; +wire [`num_axis_ports-1:0] axis_in_buff_pempty; +wire [`num_axis_ports-1:0] almost_full_axis; +wire [`num_axis_ports-1:0] almost_empty_axis; + +wire [`num_axis_ports-1:0] axis_inbuff_pfull; +wire [`num_axis_ports-1:0] axis_inbuff_aempty; + +wire [$clog2(input_buffer_depth):0] axis_inbuff_wrcnt [`num_axis_ports-1:0]; + +`ifdef debug_en + +reg [`num_axis_ports-1:0] err_boken_pkt, err_boken_pkt_tlst; + +genvar a1; +integer a2; + +generate + +for (a1=0; a1<`num_axis_ports; a1=a1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt[a1] <= 1'b0; + else + err_boken_pkt[a1] <= s_axis_tvalid_in[a1] & s_axis_tready_in[a1] & ~axis_pkt_blk_rdy_flg & ~s_axis_tlast_in[a1] & ~(&s_axis_tkeep_in[a1]); + end +end + +for (a1=0; a1<`num_axis_ports; a1=a1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + err_boken_pkt_tlst[a1] = 1'b0; + else begin + err_boken_pkt_tlst[a1] = 1'b0; + if (s_axis_tlast_in[a1]) begin + if (!err_boken_pkt_tlst[a1]) begin + for (a2=0; a2<(`unseg_axis_w/8)-2; a2=a2+1) begin + if (s_axis_tkeep_in[a1][a2+1] && !s_axis_tkeep_in[a1][a2]) + err_boken_pkt_tlst[a1] = 1'b1; + else + err_boken_pkt_tlst[a1] = 1'b0; + end + end + end else + err_boken_pkt_tlst[a1] = 1'b0; + end + end +end + + +endgenerate + +assign error_broken_pkt_in = (|err_boken_pkt) | (|(err_boken_pkt_tlst & s_axis_tvalid_in & s_axis_tready_in & ~axis_pkt_blk_rdy_flg)); + +`endif + +genvar a; +generate + for (a=0; a<`num_axis_ports; a=a+1) begin + assign axis_inbuff_pfull[a] = axis_in_buff_pfull[a]; + assign axis_inbuff_aempty[a] = almost_empty_axis[a]; + xpm_fifo_axis #( + .CASCADE_HEIGHT(0), + .CDC_SYNC_STAGES(3), + .CLOCKING_MODE("common_clock"), + .ECC_MODE("no_ecc"), + .FIFO_DEPTH(input_buffer_depth), + .FIFO_MEMORY_TYPE("auto"), + .PACKET_FIFO("true"), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(input_buffer_depth-5), + .RD_DATA_COUNT_WIDTH($clog2(input_buffer_depth)+1), + .RELATED_CLOCKS(0), + .SIM_ASSERT_CHK(0), + .TDATA_WIDTH(`unseg_axis_w), + .TDEST_WIDTH(1), + .TID_WIDTH(1), + .TUSER_WIDTH(1), + .USE_ADV_FEATURES("0803"), + .WR_DATA_COUNT_WIDTH($clog2(input_buffer_depth)+1) + ) + xpm_fifo_axis_unseg_in ( + .m_aclk(aclk_axis_unseg), + .m_axis_tready(axis_tready_c[a]), + .m_axis_tdata(axis_tdata_c[a]), + .m_axis_tkeep(axis_tkeep_c[a]), + .m_axis_tlast(axis_tlast_c[a]), + .m_axis_tuser(axis_tuser_c[a]), + .m_axis_tvalid(axis_tvalid_c[a]), + .s_aclk(aclk_axis_unseg), + .s_aresetn(aresetn_axis_unseg), + .prog_full_axis(axis_in_buff_pfull[a]), + .prog_empty_axis(axis_in_buff_pempty[a]), + .almost_full_axis(almost_full_axis[a]), + .almost_empty_axis(almost_empty_axis[a]), + .s_axis_tready(s_axis_tready_in[a]), + .s_axis_tdata(s_axis_tdata_in[a]), + .s_axis_tkeep(s_axis_tkeep_in[a]), + .s_axis_tlast(s_axis_tlast_in[a]), + .s_axis_tuser(s_axis_tuser_in[a]), + .s_axis_tvalid(s_axis_tvalid_in[a]), + .wr_data_count_axis(axis_inbuff_wrcnt[a]) + ); + end +endgenerate + +wire [`segment_width-1:0] axis_tdata_buff [`num_axis_ports-1:0][(`unseg_axis_w/`segment_width)-1:0]; +wire [(`segment_width/8)-1:0] axis_tkeep_buff [`num_axis_ports-1:0][(`unseg_axis_w/`segment_width)-1:0]; +wire [`num_axis_ports-1:0] axis_tvalid_buff; +wire [`num_axis_ports-1:0] axis_tlast_buff; +wire [`num_axis_ports-1:0] axis_tuser_buff; +wire [`num_axis_ports-1:0] axis_tready_buff; + +genvar aa, ab; +generate + for (aa=0; aa<`num_axis_ports; aa=aa+1) begin + assign axis_tready_c[aa] = axis_tready_buff[aa]; + assign axis_tvalid_buff[aa] = axis_tvalid_c[aa]; + assign axis_tlast_buff[aa] = axis_tlast_c[aa]; + assign axis_tuser_buff[aa] = axis_tuser_c[aa]; + for (ab=0; ab<(`unseg_axis_w/`segment_width); ab=ab+1) begin + assign axis_tdata_buff[aa][ab] = axis_tdata_c[aa][((ab+1)*`segment_width)-1:(ab*`segment_width)]; + assign axis_tkeep_buff[aa][ab] = axis_tkeep_c[aa][((ab+1)*(`segment_width/8))-1:(ab*(`segment_width/8))]; + end + end +endgenerate + +//----------------- Read packets as a block + +reg [$clog2(input_buffer_depth):0] axis_pkt_in_cnt [`num_axis_ports-1:0]; +reg [$clog2(input_buffer_depth)+1:0] num_pkt_to_rd_reg [`num_axis_ports-1:0]; +reg axis_in_buff_pfull_q, axis_in_buff_pfull_qq; + +wire out_buff_afull; +wire out_buff_pfull; + +genvar b; +for (b=0; b<`num_axis_ports; b=b+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_in_cnt[b] <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_in_cnt[b] <= 'd0; + else if (s_axis_tvalid_in[b] && s_axis_tready_in[b] && s_axis_tlast_in[b]) + axis_pkt_in_cnt[b] <= axis_pkt_in_cnt[b] + 'd1; + end +end + +reg [$clog2(pkt_blk_depth*4):0] axis_pkt_flush_cnt; + +`ifdef en_axis1 + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_flush_cnt <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_flush_cnt <= 'd0; + else if ((|axis_pkt_in_cnt[1] || |axis_pkt_in_cnt[0]) && !out_buff_pfull) + axis_pkt_flush_cnt <= axis_pkt_flush_cnt + 1; + else + axis_pkt_flush_cnt <= 'd0; +end + +`else + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_flush_cnt <= 'd0; + else if (axis_pkt_blk_rdy_p) + axis_pkt_flush_cnt <= 'd0; + else if (|axis_pkt_in_cnt[0] && !out_buff_pfull) + axis_pkt_flush_cnt <= axis_pkt_flush_cnt + 1; + else + axis_pkt_flush_cnt <= 'd0; +end + +`endif + +reg [`num_axis_ports-1:0] axis_pkt_blk_rd; +reg unseg_pkt_blk_rd; + +assign axis_pkt_blk_rdy_flg = axis_in_buff_pfull_q; + +wire [`num_axis_ports-1:0] unseg_buff_empty; + +always @ (posedge aclk_axis_unseg) begin + axis_pkt_blk_rdy_flg_clr <= axis_pkt_blk_rdy_p; + axis_in_buff_pfull_qq <= axis_in_buff_pfull_q; + if (!aresetn_axis_unseg) + axis_in_buff_pfull_q <= 1'b0; + else if (axis_pkt_blk_rdy_flg_clr | (|axis_pkt_blk_rd)) + axis_in_buff_pfull_q <= 1'b0; + else + axis_in_buff_pfull_q <= ((~(&axis_inbuff_aempty) & |axis_inbuff_pfull) | axis_pkt_flush_cnt[$clog2(pkt_blk_depth*4)]) & ~out_buff_pfull & (&unseg_buff_empty); +end + +assign axis_pkt_blk_rdy_p = axis_in_buff_pfull_q & ~axis_in_buff_pfull_qq; + +reg axis_pkt_blk_rdy_rp_q; + +always @ (posedge aclk_axis_unseg) begin + axis_pkt_blk_rdy_rp_q <= axis_pkt_blk_rdy_p; +end + +reg [$clog2(input_buffer_depth):0] axis_pkt_rd_cnt [`num_axis_ports-1:0]; +wire [`num_axis_ports-1:0] axis_pkt_blk_rd_end; + +genvar b0; +generate +for (b0=0; b0<`num_axis_ports; b0=b0+1) begin +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + num_pkt_to_rd_reg[b0] <= 'd0; + axis_pkt_blk_rd[b0] <= 1'b0; + end else if (axis_pkt_blk_rdy_p) begin + num_pkt_to_rd_reg[b0] <= axis_pkt_in_cnt[b0]; + axis_pkt_blk_rd[b0] <= |axis_pkt_in_cnt[b0]; + end else begin + num_pkt_to_rd_reg[b0] <= num_pkt_to_rd_reg[b0]; + if (axis_pkt_blk_rd_end[b0]) + axis_pkt_blk_rd[b0] <= 1'b0; + else + axis_pkt_blk_rd[b0] <= axis_pkt_blk_rd[b0]; + end +end +end +endgenerate + +genvar b1; +generate +for (b1=0; b1<`num_axis_ports; b1=b1+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + axis_pkt_rd_cnt[b1] <= 'd0; + else if (axis_pkt_blk_rd_end[b1]) + axis_pkt_rd_cnt[b1] <= 'd0; + else if (axis_tvalid_buff[b1] && axis_tready_buff[b1] && axis_tlast_buff[b1]) + axis_pkt_rd_cnt[b1] <= axis_pkt_rd_cnt[b1] + 'd1; + end +end +endgenerate + +genvar b3; +generate +for (b3=0; b3<`num_axis_ports; b3=b3+1) begin + assign axis_pkt_blk_rd_end[b3] = (axis_pkt_blk_rd[b3] && axis_pkt_rd_cnt[b3] >= num_pkt_to_rd_reg[b3]) ? 1'b1 : 1'b0; +end + +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Stream to segment conversion + +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_sop [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_eop [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_err [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_val [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end [`num_axis_ports-1:0]; +wire [seg_mty_w-1:0] unseg_mty_c [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] unseg_mty [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [`segment_width-1:0] unseg_dat [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +reg [`num_axis_ports-1:0] pkt_start; + +genvar c, cc; +generate +for (c=0; c<`num_axis_ports; c=c+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + pkt_start[c] <= 1'b1; + else begin + if(axis_tvalid_buff[c] & !axis_tlast_buff[c] & axis_tready_buff[c]) + pkt_start[c] <= 1'b0; + else if (axis_tvalid_buff[c] & axis_tlast_buff[c] & axis_tready_buff[c]) + pkt_start[c] <= 1'b1; + end + unseg_sop[c][0] <= (axis_tready_buff[c] & pkt_start[c] & axis_tvalid_buff[c]); + end + for (cc=0; cc<((`unseg_axis_w/`segment_width)-1); cc=cc+1) begin + always @ (posedge aclk_axis_unseg) + unseg_sop[c][cc+1] <= 1'b0; + end +end +endgenerate + +wire tdata_available [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +genvar d, dd; +generate +for (d=0; d<`num_axis_ports; d=d+1) begin + for (dd=0; dd<(`unseg_axis_w/`segment_width); dd=dd+1) begin + assign tdata_available[d][dd] = |axis_tkeep_buff[d][dd] & axis_tvalid_buff[d]; + end +end +endgenerate + +genvar e, ee; +generate +for (e=0; e<`num_axis_ports; e=e+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_eop[e][(`unseg_axis_w/`segment_width)-1] <= tdata_available[e][(`unseg_axis_w/`segment_width)-1] & axis_tlast_buff[e]; + unseg_err[e][(`unseg_axis_w/`segment_width)-1] <= tdata_available[e][(`unseg_axis_w/`segment_width)-1] & axis_tlast_buff[e] & axis_tuser_buff[e]; + end + for (ee=0; ee<((`unseg_axis_w/`segment_width)-1); ee=ee+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_eop[e][ee] <= tdata_available[e][ee] & ~tdata_available[e][ee+1] & axis_tlast_buff[e]; + unseg_err[e][ee] <= tdata_available[e][ee] & ~tdata_available[e][ee+1] & axis_tlast_buff[e] & axis_tuser_buff[e]; + end + end +end +endgenerate + +genvar f, ff; +generate +for (f=0; f<`num_axis_ports; f=f+1) begin + for (ff=0; ff<((`unseg_axis_w/`segment_width)); ff=ff+1) begin + tkeep_to_mty u_tkeep_to_mty + ( + .tkeep_in(axis_tkeep_buff[f][ff]), + .mty_out(unseg_mty_c[f][ff]) + ); + always @ (posedge aclk_axis_unseg) begin + unseg_dat[f][ff] <= axis_tdata_buff[f][ff]; + unseg_val[f][ff] <= tdata_available[f][ff] & axis_tvalid_buff[f] & axis_tready_buff[f]; + unseg_mty[f][ff] <= unseg_mty_c[f][ff]; + end + end +end +endgenerate + +genvar f1, f2; +generate +for (f1=0; f1<`num_axis_ports; f1=f1+1) begin + for (f2=0; f2<((`unseg_axis_w/`segment_width)); f2=f2+1) begin + assign unseg_blk_end[f1][f2] = unseg_eop[f1][f2] & axis_pkt_blk_rd_end[f1]; + end +end +endgenerate + +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_sop_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_eop_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_err_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_val_q [`num_axis_ports-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end_q [`num_axis_ports-1:0]; +reg [`segment_width-1:0] unseg_dat_q [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] unseg_mty_q [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +genvar f3, f4; +generate +for (f3=0; f3<`num_axis_ports; f3=f3+1) begin + for (f4=0; f4<((`unseg_axis_w/`segment_width)); f4=f4+1) begin + always @ (posedge aclk_axis_unseg) begin + unseg_sop_q[f3][f4] <= unseg_sop[f3][f4]; + unseg_eop_q[f3][f4] <= unseg_eop[f3][f4]; + unseg_err_q[f3][f4] <= unseg_err[f3][f4]; + unseg_dat_q[f3][f4] <= unseg_dat[f3][f4]; + unseg_val_q[f3][f4] <= unseg_val[f3][f4]; + unseg_mty_q[f3][f4] <= unseg_mty[f3][f4]; + unseg_blk_end_q[f3][f4] <= unseg_eop[f3][f4] & axis_pkt_blk_rd_end[f3]; + end + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment Buffer + +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_aempty [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_afull [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_pfull [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_empty [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_data_valid [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_rd_rst_busy [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_buf_wr_rst_busy [`num_axis_ports-1:0]; + +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_sop_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_eop_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_err_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_val_buf_c [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_val_buf [`num_axis_ports-1:0]; +wire [(`unseg_axis_w/`segment_width)-1:0] unseg_blk_end_buf [`num_axis_ports-1:0]; +wire [seg_mty_w-1:0] unseg_mty_buf [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; +wire [`segment_width-1:0] unseg_dat_buf [`num_axis_ports-1:0] [(`unseg_axis_w/`segment_width)-1:0]; + +wire [`num_axis_ports-1:0] unseg_buf_wr_en; +reg [`num_axis_ports-1:0] unseg_buf_rd_en; + +wire pkt_array_buf_pfull; + +wire [`num_axis_ports-1:0] unseg_buf_rd_en_c; + +reg axis_blk_rd_q, axis_blk_rd_qq; +wire axis_blk_rd_rp; +wire unseg_pkt_blk_end; + +always @ (posedge aclk_axis_unseg) begin + axis_blk_rd_q <= |axis_pkt_blk_rd; + axis_blk_rd_qq <= axis_blk_rd_q; +end + +assign axis_blk_rd_rp = axis_blk_rd_q & ~axis_blk_rd_qq; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + unseg_pkt_blk_rd <= 1'b0; + else if (unseg_pkt_blk_end) + unseg_pkt_blk_rd <= 1'b0; + else if (axis_blk_rd_rp) + unseg_pkt_blk_rd <= 1'b1; + else + unseg_pkt_blk_rd <= unseg_pkt_blk_rd; +end + +genvar g, gg; +generate +for (g=0; g<`num_axis_ports; g=g+1) begin + assign unseg_buf_wr_en[g] = unseg_val_q[g][0]; + assign axis_tready_buff[g] = axis_pkt_blk_rd[g] & ~axis_pkt_blk_rd_end[g] & ~(|unseg_buf_pfull[g]); + assign unseg_buff_empty[g] = &unseg_buf_empty[g]; + for (gg=0; gg<((`unseg_axis_w/`segment_width)); gg=gg+1) begin + assign unseg_val_buf[g][gg] = unseg_val_buf_c[g][gg] & unseg_buf_data_valid[g][gg]; + xpm_fifo_sync #( + .CASCADE_HEIGHT(0), + .DOUT_RESET_VALUE("0"), + .ECC_MODE("no_ecc"), + .FIFO_MEMORY_TYPE("auto"), + .FIFO_READ_LATENCY(1), + .FIFO_WRITE_DEPTH(local_buff_depth), + .FULL_RESET_VALUE(0), + .PROG_EMPTY_THRESH(10), + .PROG_FULL_THRESH(local_buff_depth-5), + .RD_DATA_COUNT_WIDTH(1), + .READ_DATA_WIDTH(`segment_width+seg_mty_w+5), + .READ_MODE("fwft"), + .SIM_ASSERT_CHK(0), + .USE_ADV_FEATURES("100A"), + .WAKEUP_TIME(0), + .WRITE_DATA_WIDTH(`segment_width+seg_mty_w+5), + .WR_DATA_COUNT_WIDTH(1) + ) + xpm_fifo_sync_unseg_seg_buff ( + .almost_empty(unseg_buf_aempty[g][gg]), + .almost_full(unseg_buf_afull[g][gg]), + .data_valid(unseg_buf_data_valid[g][gg]), + .dbiterr(), + .dout({unseg_blk_end_buf[g][gg],unseg_err_buf[g][gg],unseg_eop_buf[g][gg],unseg_sop_buf[g][gg],unseg_mty_buf[g][gg],unseg_val_buf_c[g][gg],unseg_dat_buf[g][gg]}), + .empty(unseg_buf_empty[g][gg]), + .full(), + .overflow(), + .prog_empty(), + .prog_full(unseg_buf_pfull[g][gg]), + .rd_data_count(), + .rd_rst_busy(unseg_buf_rd_rst_busy[g][gg]), + .sbiterr(), + .underflow(), + .wr_ack(), + .wr_data_count(), + .wr_rst_busy(unseg_buf_wr_rst_busy[g][gg]), + .din({unseg_blk_end_q[g][gg],unseg_err_q[g][gg],unseg_eop_q[g][gg],unseg_sop_q[g][gg],unseg_mty_q[g][gg],unseg_val_q[g][gg],unseg_dat_q[g][gg]}), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .rd_en(unseg_buf_rd_en_c[g]), + .rst(!aresetn_axis_unseg), + .sleep(1'b0), + .wr_clk(aclk_axis_unseg), + .wr_en(unseg_buf_wr_en[g]) + ); + end +end +endgenerate + +//----------------------------------------------------------------------------------------------------------------------- + +//----- Packet read enable generation, (read arbitration, based on packet availability in input ports) + +reg only_port1_active, only_port0_active; + +`ifdef en_axis1 // Below logic assumes max no of ports is 2 (applicable for 400G) + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + only_port0_active <= 1'b0; + else if (axis_pkt_blk_rdy_p) + if (axis_inbuff_aempty[1]) + only_port0_active <= 1'b1; + else + only_port0_active <= 1'b0; + else + only_port0_active <= only_port0_active; +end + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + only_port1_active <= 1'b0; + else if (axis_pkt_blk_rdy_p) + if (axis_inbuff_aempty[0]) + only_port1_active <= 1'b1; + else + only_port1_active <= 1'b0; + else + only_port1_active <= only_port1_active; +end + +reg pkt_port_sel; + +assign unseg_buf_rd_en_c[0] = (unseg_buf_rd_en[0] | ((|unseg_eop_buf[1] & (|unseg_val_buf[1])) & !(|unseg_buf_empty[0])) & ~pkt_array_buf_pfull); +assign unseg_buf_rd_en_c[1] = (unseg_buf_rd_en[1] | ((|unseg_eop_buf[0] & (|unseg_val_buf[0])) & !(|unseg_buf_empty[1])) & ~pkt_array_buf_pfull); + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) begin + pkt_port_sel <= 1'b0; + unseg_buf_rd_en[0] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else if (axis_pkt_blk_rdy_rp_q) begin + if (only_port1_active) begin + pkt_port_sel <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else if (only_port0_active) begin + pkt_port_sel <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + unseg_buf_rd_en[1] <= 1'b0; + end else + pkt_port_sel <= pkt_port_sel; + end else if (!pkt_array_buf_pfull) begin + if (pkt_port_sel) begin + unseg_buf_rd_en[0] <= 1'b0; + if (|unseg_eop_buf[1] && |unseg_val_buf[1]) begin + if (|unseg_buf_empty[1]) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else if (!(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else + unseg_buf_rd_en[1] <= 1'b1; + end else if (|unseg_eop_buf[1] && !(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + unseg_buf_rd_en[1] <= 1'b0; + pkt_port_sel <= 1'b0; + end else if(!(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + end else begin + unseg_buf_rd_en[1] <= 1'b0; + end + end else begin + unseg_buf_rd_en[1] <= 1'b0; + if (|unseg_eop_buf[0] && |unseg_val_buf[0]) begin + if (|unseg_buf_empty[0]) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else if (!(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else + unseg_buf_rd_en[0] <= 1'b1; + end else if (|unseg_eop_buf[0] && !(|unseg_buf_empty[1])) begin + unseg_buf_rd_en[1] <= 1'b1; + unseg_buf_rd_en[0] <= 1'b0; + pkt_port_sel <= 1'b1; + end else if(!(|unseg_buf_empty[0])) begin + unseg_buf_rd_en[0] <= 1'b1; + end else begin + unseg_buf_rd_en[0] <= 1'b0; + end + end + end +end + +`else // only one port available + +assign unseg_buf_rd_en_c[0] = unseg_buf_rd_en[0] & ~pkt_array_buf_pfull; + +always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + unseg_buf_rd_en[0] <= 1'b0; + else if (!pkt_array_buf_pfull) begin + if (|unseg_buf_empty[0]) + unseg_buf_rd_en[0] <= 1'b0; + else + unseg_buf_rd_en[0] <= 1'b1; + end +end + +`endif + +`ifdef en_axis1 + +reg [`segment_width-1:0] seg_data_array [pkt_array_depth-1:0]; +reg [seg_mty_w-1:0] seg_mty_array [pkt_array_depth-1:0]; +reg [pkt_array_depth-1:0] seg_val_array; +reg [pkt_array_depth-1:0] seg_sop_array; +reg [pkt_array_depth-1:0] seg_eop_array; +reg [pkt_array_depth-1:0] seg_err_array; +reg [pkt_array_depth-1:0] seg_blk_end_array; + +`else + +reg [`segment_width-1:0] seg_data_array [(`unseg_axis_w/`segment_width)-1:0]; +reg [seg_mty_w-1:0] seg_mty_array [(`unseg_axis_w/`segment_width)-1:0]; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_val_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_sop_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_eop_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_err_array; +reg [(`unseg_axis_w/`segment_width)-1:0] seg_blk_end_array; + +`endif + +// Generate a flag indicate the end of a block(aligned with the eop of the last packet in the block) + +wire [`num_axis_ports-1:0] unseg_blk_end_buf_val; + +`ifdef en_axis1 + +reg [`num_axis_ports-1:0] unseg_blk_end_flg; + +genvar h; +generate +for (h=0; h<`num_axis_ports; h=h+1) begin + if (h == 0) + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg | unseg_pkt_blk_end) + unseg_blk_end_flg[h] <= 1'b0; + else if (only_port1_active) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h]) + if (|unseg_blk_end_buf[h+1] && |unseg_val_buf[h+1] && unseg_buf_rd_en_c[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + else if (|unseg_blk_end_buf[h] && |unseg_val_buf[h] && unseg_buf_rd_en_c[h]) + if (|unseg_blk_end_buf[h+1] && |unseg_val_buf[h+1] && unseg_buf_rd_en_c[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h+1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= 1'b1; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + end + else + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg | unseg_pkt_blk_end) + unseg_blk_end_flg[h] <= 1'b0; + else if (only_port0_active) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h]) + if (|unseg_blk_end_buf[h-1] && |unseg_val_buf[h-1] && unseg_buf_rd_en_c[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + else if (|unseg_blk_end_buf[h] && |unseg_val_buf[h] && unseg_buf_rd_en_c[h]) + if (|unseg_blk_end_buf[h-1] && |unseg_val_buf[h-1] && unseg_buf_rd_en_c[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else if (unseg_blk_end_flg[h-1]) + unseg_blk_end_flg[h] <= 1'b0; + else + unseg_blk_end_flg[h] <= 1'b1; + else + unseg_blk_end_flg[h] <= unseg_blk_end_flg[h]; + end +end +endgenerate + +`endif + +`ifdef en_axis1 + +genvar h0; +generate +for (h0=0; h0<`num_axis_ports; h0=h0+1) begin + if (h0 == 0) + assign unseg_blk_end_buf_val[h0] = (unseg_blk_end_flg[h0+1] && (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0])) ? 1'b1 : (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0] && !(|unseg_val_buf[h0+1])) ? 1'b1 : (|unseg_blk_end_buf[h0] & unseg_buf_rd_en_c[h0] & |unseg_val_buf[h0]) & (|unseg_blk_end_buf[h0+1] & unseg_buf_rd_en_c[h0+1] & |unseg_val_buf[h0+1]); + else + assign unseg_blk_end_buf_val[h0] = (unseg_blk_end_flg[h0-1] && (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0])) ? 1'b1 : (|unseg_blk_end_buf[h0] && unseg_buf_rd_en_c[h0] && |unseg_val_buf[h0] && !(|unseg_val_buf[h0-1])) ? 1'b1 : (|unseg_blk_end_buf[h0] & unseg_buf_rd_en_c[h0] & |unseg_val_buf[h0]) & (|unseg_blk_end_buf[h0-1] & unseg_buf_rd_en_c[h0-1] & |unseg_val_buf[h0-1]); +end +endgenerate + +`else + assign unseg_blk_end_buf_val[0] = (|unseg_blk_end_buf[0] & |unseg_val_buf[0]); +`endif + +assign unseg_pkt_blk_end = |unseg_blk_end_buf_val; + +genvar hh; + +`ifdef en_axis1 + +generate +for (hh=0; hh < (pkt_array_depth/2); hh = hh+1) begin + always @ (posedge aclk_axis_unseg) begin + if (pkt_port_sel) begin + seg_data_array[hh] <= unseg_dat_buf[1][hh]; + seg_mty_array[hh] <= unseg_mty_buf[1][hh]; + seg_val_array[hh] <= unseg_val_buf[1][hh] & unseg_buf_rd_en_c[1]; + seg_sop_array[hh] <= unseg_sop_buf[1][hh]; + seg_eop_array[hh] <= unseg_eop_buf[1][hh]; + seg_err_array[hh] <= unseg_err_buf[1][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[1][hh] & unseg_blk_end_buf_val[1]; + seg_data_array[hh+(pkt_array_depth/2)] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh+(pkt_array_depth/2)] <= unseg_mty_buf[0][hh]; + seg_val_array[hh+(pkt_array_depth/2)] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh+(pkt_array_depth/2)] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh+(pkt_array_depth/2)] <= unseg_eop_buf[0][hh]; + seg_err_array[hh+(pkt_array_depth/2)] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh+(pkt_array_depth/2)] <= unseg_blk_end_buf[0][hh] & unseg_blk_end_buf_val[0]; + end else begin + seg_data_array[hh] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh] <= unseg_mty_buf[0][hh]; + seg_val_array[hh] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh] <= unseg_eop_buf[0][hh]; + seg_err_array[hh] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[0][hh] & unseg_blk_end_buf_val[0]; + seg_data_array[hh+(pkt_array_depth/2)] <= unseg_dat_buf[1][hh]; + seg_mty_array[hh+(pkt_array_depth/2)] <= unseg_mty_buf[1][hh]; + seg_val_array[hh+(pkt_array_depth/2)] <= unseg_val_buf[1][hh] & unseg_buf_rd_en_c[1]; + seg_sop_array[hh+(pkt_array_depth/2)] <= unseg_sop_buf[1][hh]; + seg_eop_array[hh+(pkt_array_depth/2)] <= unseg_eop_buf[1][hh]; + seg_err_array[hh+(pkt_array_depth/2)] <= unseg_err_buf[1][hh]; + seg_blk_end_array[hh+(pkt_array_depth/2)] <= unseg_blk_end_buf[1][hh] & unseg_blk_end_buf_val[1]; + end + end +end +endgenerate + +`else + +generate +for (hh=0; hh < pkt_array_depth; hh = hh+1) begin + always @ (posedge aclk_axis_unseg) begin + seg_data_array[hh] <= unseg_dat_buf[0][hh]; + seg_mty_array[hh] <= unseg_mty_buf[0][hh]; + seg_val_array[hh] <= unseg_val_buf[0][hh] & unseg_buf_rd_en_c[0]; + seg_sop_array[hh] <= unseg_sop_buf[0][hh]; + seg_eop_array[hh] <= unseg_eop_buf[0][hh]; + seg_err_array[hh] <= unseg_err_buf[0][hh]; + seg_blk_end_array[hh] <= unseg_blk_end_buf[0][hh]; + end +end +endgenerate + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Segment array + +// Pack the segments + +reg [`segment_width-1:0] pkt_data_array [(pkt_array_depth*2)-1:0]; +reg [seg_mty_w-1:0] pkt_mty_array [(pkt_array_depth*2)-1:0]; +reg [(pkt_array_depth*2)-1:0] pkt_val_array0; +reg [(pkt_array_depth*2)-1:0] pkt_val_array00; +reg [(pkt_array_depth*2)-1:0] pkt_val_array1; +reg [(pkt_array_depth*2)-1:0] pkt_val_array2; +reg [(pkt_array_depth*2)-1:0] pkt_val_array; +reg [(pkt_array_depth*2)-1:0] pkt_sop_array; +reg [(pkt_array_depth*2)-1:0] pkt_eop_array; +reg [(pkt_array_depth*2)-1:0] pkt_err_array; +reg [(pkt_array_depth*2)-1:0] pkt_blk_end_array; +reg [(pkt_array_depth*2)-1:0] pkt_blk_end_array1; + +reg [$clog2((pkt_array_depth*2))-1:0] pkt_seg_sel_reg [(pkt_array_depth*2)-1:0]; +reg [$clog2((pkt_array_depth*2))-1:0] pkt_seg_sel_reg1 [(pkt_array_depth*2)-1:0]; + +wire pkt_arry_clr_p0; +wire pkt_arry_clr_p1; +wire pkt_arry_clr_p2; +wire pkt_arry_clr_p3; + +reg [$clog2((pkt_array_depth*2))-1:0] pkt_array_ptr1; +reg [$clog2((pkt_array_depth*2))-1:0] pkt_array_ptr2; + +wire p0_flushout_c; +wire p1_flushout_c; +wire p2_flushout_c; +wire p3_flushout_c; + +assign p0_flushout_c = pkt_val_array1[0] & |(pkt_blk_end_array1[((pkt_array_depth/2)*1)-1:0]); +assign p1_flushout_c = pkt_val_array1[((pkt_array_depth/2)*1)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)*1]); +assign p2_flushout_c = pkt_val_array1[((pkt_array_depth/2)*2)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*3)-1:(pkt_array_depth/2)*2]); +assign p3_flushout_c = pkt_val_array1[((pkt_array_depth/2)*3)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*4)-1:(pkt_array_depth/2)*3]); + +assign pkt_arry_clr_p0 = pkt_val_array1[((pkt_array_depth/2)*1)-1] | (pkt_val_array1[0] & |(pkt_blk_end_array1[((pkt_array_depth/2)*1)-1:0])); +assign pkt_arry_clr_p1 = pkt_val_array1[((pkt_array_depth/2)*2)-1] | (pkt_val_array1[((pkt_array_depth/2)*1)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*2)-1:(pkt_array_depth/2)*1])); +assign pkt_arry_clr_p2 = pkt_val_array1[((pkt_array_depth/2)*3)-1] | (pkt_val_array1[((pkt_array_depth/2)*2)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*3)-1:(pkt_array_depth/2)*2])); +assign pkt_arry_clr_p3 = pkt_val_array1[((pkt_array_depth/2)*4)-1] | (pkt_val_array1[((pkt_array_depth/2)*3)] & |(pkt_blk_end_array1[((pkt_array_depth/2)*4)-1:(pkt_array_depth/2)*3])); + +wire pkt_array_rst; +wire pkt_seg_sel_reg_rst; + +assign pkt_array_rst = !aresetn_axis_unseg | p0_flushout_c | p1_flushout_c | p2_flushout_c | p3_flushout_c; +assign pkt_seg_sel_reg_rst = !aresetn_axis_unseg | p0_flushout_c | p1_flushout_c | p2_flushout_c | p3_flushout_c; + +integer i, ii; +generate + always @ (posedge aclk_axis_unseg) begin + if (pkt_array_rst) begin + pkt_array_ptr1 = 0; + for(i=0; i < pkt_array_depth*2; i = i+1) begin + pkt_val_array0 [i] <= 1'b0; + pkt_val_array1 [i] <= 1'b0; + pkt_blk_end_array1 [i] <= 1'b0; + end + end else begin + for(i=0; i eop_cnt) + pkt_open <= 1'b1; + else + pkt_open <= 1'b0; + else + pkt_open <= pkt_open; +end + +assign error_broken_pkt0 = pkt_open & ~unseg_val0_q; // Indicates a missing eop + +integer z0; + +reg error_broken_pkt1; + +reg last_seg_eop; + +always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) begin + error_broken_pkt1 <= 1'b0; + last_seg_eop = 1'b1; + end else begin + for (z0=0; z0<`num_segments; z0=z0+1) begin + if (unseg2seg_out_Val[z0] & seg_buf_out_rd_en) begin + if (unseg2seg_out_Sop[z0] && !last_seg_eop) begin // indicates a gap between eop & next sop within valid segments + error_broken_pkt1 = 1'b1; // packet get corrupted + end else if (unseg2seg_out_Sop[z0] && last_seg_eop) begin // next valid packet boundary detected + error_broken_pkt1 = 1'b0; + end else begin + error_broken_pkt1 = error_broken_pkt1; + end + last_seg_eop = unseg2seg_out_Eop[z0]; + end + end + end +end + +// #3 Corrupted data/mty values + +reg err_data_mismatch; +reg [15:0] seg_last_data; +reg err_mty_nonzero; + +integer z1; + +always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) begin + err_data_mismatch = 1'b0; + seg_last_data = 'd0; + err_mty_nonzero = 1'b0; + end else begin + for (z1=0; z1<`num_segments; z1=z1+1) begin + if (unseg2seg_out_Val[z1] & seg_buf_out_rd_en) begin + if(unseg2seg_out_Dat[z1][15:0] - seg_last_data != 15'h0001) begin + err_data_mismatch = 1'b1; + end else begin + err_data_mismatch = 1'b0; + end + seg_last_data = unseg2seg_out_Dat[z1][15:0]; + if(!unseg2seg_out_Eop[z1] && |unseg2seg_out_Mty[z1]) begin + err_mty_nonzero = 1'b1; + end else begin + err_mty_nonzero = 1'b0; + end + end + end + end +end + +// in the below assignment "err_data_mismatch" could be included only when checking with incrementing/counter data as packet input and at less rate(flow_control disabled) + +assign error_broken_pkt_out = error_broken_pkt0 | error_broken_pkt1 | err_mty_nonzero; // | err_data_mismatch; + +`endif + +//----------------------------------------------------------------------------------------------------------------------- + +//----------------- Port Statistics + +`ifdef statistics_en + localparam statistics_en = 1; +`else + localparam statistics_en = 0; +`endif + +generate + +if (statistics_en) begin + +//----------------- Ouput packet count + +reg [63:0] segment_pkt_cnt [`num_segments-1:0]; +reg [63:0] segment_err_cnt [`num_segments-1:0]; +reg [63:0] segment_pkt_sop_cnt [`num_segments-1:0]; +reg [63:0] segment_byte_cnt [`num_segments-1:0]; +wire [($clog2(`segment_width/8)):0] segment_validbytes [`num_segments-1:0]; +reg [63:0] total_pktout_cnt; +reg [63:0] total_err_pktout_cnt; +reg [63:0] total_pktout_byte_cnt; + +genvar ab; + +for (ab=0; ab<`num_segments; ab=ab+1) begin + mty_to_validbytes u_mty_to_valbytes + ( + .mty_in(unseg2seg_out_Mty[ab]), + .valid_bytes_out(segment_validbytes[ab]) + ); +end + +genvar cd; + +for (cd=0; cd<`num_segments; cd=cd+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_byte_cnt[cd] <= 'd0; + else if (unseg2seg_out_Val[cd] & seg_data_out_valid & seg_buf_out_rd_en) + segment_byte_cnt[cd] <= segment_byte_cnt[cd] + segment_validbytes[cd]; + end +end + +integer ef; + +always @ (*) begin + total_pktout_byte_cnt = 'd0; + for (ef=0; ef<`num_segments; ef=ef+1) begin + total_pktout_byte_cnt = total_pktout_byte_cnt + segment_byte_cnt[ef]; + end +end + +genvar gh; + +for (gh=0; gh<`num_segments; gh=gh+1) begin + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_pkt_cnt[gh] <= 'd0; + else if (unseg2seg_out_Val[gh] && seg_data_out_valid && unseg2seg_out_Eop[gh] && seg_buf_out_rd_en) + segment_pkt_cnt[gh] <= segment_pkt_cnt[gh] + 1; + end + always @ (posedge aclk_axis_seg_in) begin + if (!aresetn_axis_seg_in) + segment_err_cnt[gh] <= 'd0; + else if (unseg2seg_out_Val[gh] && seg_data_out_valid && unseg2seg_out_Eop[gh] && unseg2seg_out_Err[gh] && seg_buf_out_rd_en) + segment_err_cnt[gh] <= segment_err_cnt[gh] + 1; + end +end + +integer ij; + +always @ (*) begin + total_pktout_cnt = 'd0; + total_err_pktout_cnt = 'd0; + for (ij=0; ij<`num_segments; ij=ij+1) begin + total_pktout_cnt = total_pktout_cnt + segment_pkt_cnt[ij]; + total_err_pktout_cnt = total_err_pktout_cnt + segment_err_cnt[ij]; + end +end + +//----------------- Input packet count + +reg [63:0] port_pkt_in_cnt [`num_axis_ports-1:0]; +reg [63:0] port_err_pkt_in_cnt [`num_axis_ports-1:0]; +reg [63:0] port_pkt_in_byte_cnt [`num_axis_ports-1:0]; +reg [63:0] total_pktin_cnt; +reg [63:0] total_err_pktin_cnt; +reg [63:0] total_pktin_byte_cnt; + +wire [($clog2(`unseg_axis_w/8)):0] port_valid_bytes [`num_axis_ports-1:0]; + +genvar g; +for (g=0; g<`num_axis_ports; g=g+1) begin + tkeep_to_validbytes u_tkeep_to_valbytes + ( + .tkeep_in(s_axis_tkeep_in[g]), + .valid_bytes_out(port_valid_bytes[g]) + ); +end + +genvar i; +for (i=0; i<`num_axis_ports; i=i+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_in_cnt[i] <= 'd0; + else if (s_axis_tvalid_in[i] && (s_axis_tready_in[i] && !axis_pkt_blk_rdy_flg) && s_axis_tlast_in[i]) + port_pkt_in_cnt[i] <= port_pkt_in_cnt[i] + 'd1; + end + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_err_pkt_in_cnt[i] <= 'd0; + else if (s_axis_tvalid_in[i] && (s_axis_tready_in[i] && !axis_pkt_blk_rdy_flg) && s_axis_tlast_in[i] && s_axis_tuser_in[i]) + port_err_pkt_in_cnt[i] <= port_err_pkt_in_cnt[i] + 'd1; + end +end + +genvar j; +for (j=0; j<`num_axis_ports; j=j+1) begin + always @ (posedge aclk_axis_unseg) begin + if (!aresetn_axis_unseg) + port_pkt_in_byte_cnt[j] <= 'd0; + else if (s_axis_tvalid_in[j] && (s_axis_tready_in[j] && !axis_pkt_blk_rdy_flg)) + port_pkt_in_byte_cnt[j] <= port_pkt_in_byte_cnt[j] + port_valid_bytes[j]; + end +end + +integer k; +always @ (*) begin + total_pktin_cnt = 'd0; + total_err_pktin_cnt = 'd0; + total_pktin_byte_cnt = 'd0; + for (k=0; k<`num_axis_ports; k=k+1) begin + total_pktin_cnt = total_pktin_cnt + port_pkt_in_cnt[k]; + total_err_pktin_cnt = total_err_pktin_cnt + port_err_pkt_in_cnt[k]; + total_pktin_byte_cnt = total_pktin_byte_cnt + port_pkt_in_byte_cnt[k]; + end +end + +assign total_pkt_in_cnt = total_pktin_cnt; +assign total_err_pkt_in_cnt = total_err_pktin_cnt; +assign total_pkt_in_byte_cnt = total_pktin_byte_cnt; +assign total_pkt_out_cnt = total_pktout_cnt; +assign total_err_pkt_out_cnt = total_err_pktout_cnt; +assign total_pkt_out_byte_cnt = total_pktout_byte_cnt; +`ifdef en_axis1 +assign p1_pkt_in_cnt = port_pkt_in_cnt[1]; +assign p1_err_pkt_in_cnt = port_err_pkt_in_cnt[1]; +assign p1_pkt_in_byte_cnt = port_pkt_in_byte_cnt[1]; +assign p0_pkt_in_cnt = port_pkt_in_cnt[0]; +assign p0_err_pkt_in_cnt = port_err_pkt_in_cnt[0]; +assign p0_pkt_in_byte_cnt = port_pkt_in_byte_cnt[0]; +`endif + +end +endgenerate + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- + +module tkeep_to_mty + ( + input [(`segment_width/8)-1:0] tkeep_in, + output wire [($clog2(`segment_width/8))-1:0] mty_out + ); + +integer i; +reg [($clog2(`segment_width/8)):0] valid; + +always @ (tkeep_in) begin + valid = 0; + for (i=0; i<(`segment_width/8); i=i+1) + valid = valid + tkeep_in[i]; +end + +assign mty_out = (`segment_width/8) - valid; + +endmodule + +//----------------------------------------------------------------------------------------------------------------------- +//----------------------------------------------------------------------------------------------------------------------- + diff --git a/linker/slashkit/resources/dcmac/hdl/clock_to_clock_bus.v b/linker/slashkit/resources/dcmac/hdl/clock_to_clock_bus.v new file mode 100644 index 00000000..3410398d --- /dev/null +++ b/linker/slashkit/resources/dcmac/hdl/clock_to_clock_bus.v @@ -0,0 +1,14 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ns / 1ps + +module clock_to_clock_bus ( + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) + input clk, + output wire [5:0] clockbus + ); + + assign clockbus = {6{clk}}; + +endmodule \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/hdl/dcmac200g_ctl_port.v b/linker/slashkit/resources/dcmac/hdl/dcmac200g_ctl_port.v new file mode 100644 index 00000000..8cc38c77 --- /dev/null +++ b/linker/slashkit/resources/dcmac/hdl/dcmac200g_ctl_port.v @@ -0,0 +1,54 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ps/1ps + +module dcmac200g_ctl_port ( + output wire [15:0] default_vl_length_100GE, + output wire [15:0] default_vl_length_200GE_or_400GE, + output wire [63:0] ctl_tx_vl_marker_id0, + output wire [63:0] ctl_tx_vl_marker_id1, + output wire [63:0] ctl_tx_vl_marker_id2, + output wire [63:0] ctl_tx_vl_marker_id3, + output wire [63:0] ctl_tx_vl_marker_id4, + output wire [63:0] ctl_tx_vl_marker_id5, + output wire [63:0] ctl_tx_vl_marker_id6, + output wire [63:0] ctl_tx_vl_marker_id7, + output wire [63:0] ctl_tx_vl_marker_id8, + output wire [63:0] ctl_tx_vl_marker_id9, + output wire [63:0] ctl_tx_vl_marker_id10, + output wire [63:0] ctl_tx_vl_marker_id11, + output wire [63:0] ctl_tx_vl_marker_id12, + output wire [63:0] ctl_tx_vl_marker_id13, + output wire [63:0] ctl_tx_vl_marker_id14, + output wire [63:0] ctl_tx_vl_marker_id15, + output wire [63:0] ctl_tx_vl_marker_id16, + output wire [63:0] ctl_tx_vl_marker_id17, + output wire [63:0] ctl_tx_vl_marker_id18, + output wire [63:0] ctl_tx_vl_marker_id19 +); + + assign default_vl_length_100GE = 16'd255; + assign default_vl_length_200GE_or_400GE = 16'd256; + assign ctl_tx_vl_marker_id0 = 64'hc16821003e97de00; + assign ctl_tx_vl_marker_id1 = 64'h9d718e00628e7100; + assign ctl_tx_vl_marker_id2 = 64'h594be800a6b41700; + assign ctl_tx_vl_marker_id3 = 64'h4d957b00b26a8400; + assign ctl_tx_vl_marker_id4 = 64'hf50709000af8f600; + assign ctl_tx_vl_marker_id5 = 64'hdd14c20022eb3d00; + assign ctl_tx_vl_marker_id6 = 64'h9a4a260065b5d900; + assign ctl_tx_vl_marker_id7 = 64'h7b45660084ba9900; + assign ctl_tx_vl_marker_id8 = 64'ha02476005fdb8900; + assign ctl_tx_vl_marker_id9 = 64'h68c9fb0097360400; + assign ctl_tx_vl_marker_id10 = 64'hfd6c990002936600; + assign ctl_tx_vl_marker_id11 = 64'hb9915500466eaa00; + assign ctl_tx_vl_marker_id12 = 64'h5cb9b200a3464d00; + assign ctl_tx_vl_marker_id13 = 64'h1af8bd00e5074200; + assign ctl_tx_vl_marker_id14 = 64'h83c7ca007c383500; + assign ctl_tx_vl_marker_id15 = 64'h3536cd00cac93200; + assign ctl_tx_vl_marker_id16 = 64'hc4314c003bceb300; + assign ctl_tx_vl_marker_id17 = 64'hadd6b70052294800; + assign ctl_tx_vl_marker_id18 = 64'h5f662a00a099d500; + assign ctl_tx_vl_marker_id19 = 64'hc0f0e5003f0f1a00; + +endmodule \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/hdl/serdes_clock.v b/linker/slashkit/resources/dcmac/hdl/serdes_clock.v new file mode 100644 index 00000000..3d1eec10 --- /dev/null +++ b/linker/slashkit/resources/dcmac/hdl/serdes_clock.v @@ -0,0 +1,14 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ns / 1ps + +module clock_to_serdes ( + input usrclk, + (* X_INTERFACE_INFO = "xilinx.com:signal:gt_usrclk:1.0 GT_USRCLK.RX_ALT_SERDES_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME GT_USRCLK.RX_ALT_SERDES_CLK, CLK_DOMAIN dcmac_200g_exdes_support_rx_alt_serdes_clk, FREQ_HZ 156250000, PARENT_ID undef, PHASE 0.0" *) + output wire [5:0] serdes_clk + ); + + assign serdes_clk = {1'b0, 1'b0, 1'b0, 1'b0, usrclk, usrclk}; + +endmodule \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/hdl/syncer_reset.v b/linker/slashkit/resources/dcmac/hdl/syncer_reset.v new file mode 100644 index 00000000..1b0e5933 --- /dev/null +++ b/linker/slashkit/resources/dcmac/hdl/syncer_reset.v @@ -0,0 +1,37 @@ +// Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: MIT + +`timescale 1ps/1ps + +module dcmac_syncer_reset #( + parameter RESET_PIPE_LEN = 3 +) +( + input wire clk, + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 clk_wizard_lock,resetn_async RST" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input wire clk_wizard_lock, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input wire resetn_async, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + output wire resetn +); + + (* ASYNC_REG = "TRUE" *) reg [RESET_PIPE_LEN-1:0] reset_pipe_retime; + reg reset_pipe_out = 1'b0; + assign resetn_async_inv = resetn_async & clk_wizard_lock; + + always @(posedge clk or negedge resetn_async_inv) begin + if (resetn_async_inv == 1'b0) begin + reset_pipe_retime <= {RESET_PIPE_LEN{1'b0}}; + reset_pipe_out <= 1'b0; + end + else begin + reset_pipe_retime <= {reset_pipe_retime[RESET_PIPE_LEN-2:0], 1'b1}; + reset_pipe_out <= reset_pipe_retime[RESET_PIPE_LEN-1]; + end + end + + assign resetn = reset_pipe_out; + +endmodule \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/tcl/dcmac.tcl b/linker/slashkit/resources/dcmac/tcl/dcmac.tcl new file mode 100644 index 00000000..5ed8590e --- /dev/null +++ b/linker/slashkit/resources/dcmac/tcl/dcmac.tcl @@ -0,0 +1,1387 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# hdl files from resources will be available in this script when running at "$src_dir/dcmac/hdl/..." + + +# Hierarchical cell: dcmac_gt_wrapper +proc create_hier_cell_dcmac_gt_wrapper { parentCell nameHier dcmac_index dual_dcmac } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_dcmac_gt_wrapper() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX0_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX1_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX2_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX3_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX0_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX1_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX2_GT0_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX3_GT0_IP_Interface + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT0_Serial + + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX0_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX1_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX2_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_tx_interface_rtl:1.0 TX3_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX0_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX1_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX2_GT1_IP_Interface + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:gt_rx_interface_rtl:1.0 RX3_GT1_IP_Interface + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT1_Serial + } + + # Create pins + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLR + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLRB_LEAF + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_rx_usr_clk_664mhz + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_rx_usr_clk_332mhz + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLR1 + create_bd_pin -dir I -from 0 -to 0 MBUFG_GT_CLRB_LEAF1 + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_tx_usr_clk_664mhz + create_bd_pin -dir O -from 0 -to 0 -type gt_usrclk qsfp0_tx_usr_clk_332mhz + create_bd_pin -dir I -type rst hsclk_pllreset0 + create_bd_pin -dir O hsclk_plllock0 + create_bd_pin -dir O gtpowergood_0 + create_bd_pin -dir I -type rst gt0_ch0_iloreset + create_bd_pin -dir I -type rst gt0_ch1_iloreset + create_bd_pin -dir I -type rst gt0_ch2_iloreset + create_bd_pin -dir I -type rst gt0_ch3_iloreset + create_bd_pin -dir O gt0_ch0_iloresetdone + create_bd_pin -dir O gt0_ch1_iloresetdone + create_bd_pin -dir O gt0_ch2_iloresetdone + create_bd_pin -dir O gt0_ch3_iloresetdone + create_bd_pin -dir I -type clk apb3clk_quad + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -type gt_usrclk GT0_ref_clk + create_bd_pin -dir I -from 31 -to 0 gt_control_pins + + if { ${dual_dcmac} == "1" } { + create_bd_pin -dir I -type rst hsclk_pllreset1 + create_bd_pin -dir O hsclk_plllock1 + create_bd_pin -dir I -type rst gt1_ch0_iloreset + create_bd_pin -dir I -type rst gt1_ch1_iloreset + create_bd_pin -dir I -type rst gt1_ch2_iloreset + create_bd_pin -dir I -type rst gt1_ch3_iloreset + create_bd_pin -dir O gt1_ch0_iloresetdone + create_bd_pin -dir O gt1_ch1_iloresetdone + create_bd_pin -dir O gt1_ch2_iloresetdone + create_bd_pin -dir O gt1_ch3_iloresetdone + create_bd_pin -dir O gtpowergood_1 + } + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {IBUFDS_GTME5} $util_ds_buf_0 + + set top_dcmac_name "top_dcmac_${dcmac_index}_core_0" + set dcmac_name "dcmac_${dcmac_index}_core" + + set list_quad_index { 0 } + if { ${dual_dcmac} == "1" } { + lappend list_quad_index 1 + } + + foreach idx ${list_quad_index} { + # Create instance: gt0_quad, and set properties + set quad_name "gt${idx}_quad" + set gt_quad [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_quad_base ${quad_name} ] + + set channel_ordering {} + foreach dirid {TX RX} { + for {set lane 0} {$lane < 4} {incr lane} { + set new_idx ${lane} + if { ${idx} == "1" } { + set new_idx "[expr {$lane + 4}]" + } + + set ord " ${oldCurInst}/${quad_name}/${dirid}${lane}_GT_IP_Interface top_dcmac_${idx}_core_0.${oldCurInst}/dcmac_${idx}_core/gtm_tx_serdes_interface_${new_idx}.${new_idx}" + append channel_ordering ${ord} + } + } + + set quad_usage {} + foreach dirid {TX_QUAD_CH RX_QUAD_CH} { + set list_quad_index_ii { 0 } + if { ${dual_dcmac} == "1" } { + lappend list_quad_index_ii 1 + } + append quad_usage " ${dirid} {" + foreach idxii ${list_quad_index_ii} { + set quad_name_ii "gt${idxii}_quad" + set q0 [expr {${idx} == ${idxii}}] + #set q1 [expr {!$q0}] + if { ${idxii} == "0" } { + set conf " ${oldCurInst}/dcmac_gt${idxii}_wrapper/${quad_name_ii} {${oldCurInst}/dcmac_gt${dcmac_index}_wrapper/${quad_name_ii}\ + top_dcmac_${dcmac_index}_core_0.IP_CH0,top_dcmac_${dcmac_index}_core_0.IP_CH1,top_dcmac_${dcmac_index}_core_0.IP_CH2,top_dcmac_${dcmac_index}_core_0.IP_CH3 MSTRCLK 1,0,0,0 IS_CURRENT_QUAD ${q0}}" + } else { + set conf " ${oldCurInst}/dcmac_gt${idxii}_wrapper/${quad_name_ii} {${oldCurInst}/dcmac_gt${dcmac_index}_wrapper/${quad_name_ii}\ + top_dcmac_${dcmac_index}_core_0.IP_CH4,top_dcmac_${dcmac_index}_core_0.IP_CH5,top_dcmac_${dcmac_index}_core_0.IP_CH6,top_dcmac_${dcmac_index}_core_0.IP_CH7 MSTRCLK 1,0,0,0 IS_CURRENT_QUAD ${q0}}" + } + append quad_usage "${conf}" + } + append quad_usage "}" + } + + set_property -dict [list \ + CONFIG.APB3_CLK_FREQUENCY {100.0} \ + CONFIG.CHANNEL_ORDERING {${channel_ordering}} \ + CONFIG.GT_TYPE {GTM} \ + CONFIG.PORTS_INFO_DICT {LANE_SEL_DICT {PROT0 {RX0 RX1 RX2 RX3 TX0 TX1 TX2 TX3}} GT_TYPE GTM REG_CONF_INTF APB3_INTF BOARD_PARAMETER { }} \ + CONFIG.PROT0_ENABLE {true} \ + CONFIG.PROT0_GT_DIRECTION {DUPLEX} \ + CONFIG.PROT0_LR0_SETTINGS {GT_DIRECTION DUPLEX TX_PAM_SEL PAM4 TX_HD_EN 0 TX_GRAY_BYP false TX_GRAY_LITTLEENDIAN false TX_PRECODE_BYP true TX_PRECODE_LITTLEENDIAN false TX_LINE_RATE 53.125 TX_PLL_TYPE\ +LCPLL TX_REFCLK_FREQUENCY 322.265625 TX_ACTUAL_REFCLK_FREQUENCY 322.265625183611 TX_FRACN_ENABLED true TX_FRACN_OVRD false TX_FRACN_NUMERATOR 0 TX_REFCLK_SOURCE R0 TX_DATA_ENCODING RAW TX_USER_DATA_WIDTH\ +160 TX_INT_DATA_WIDTH 128 TX_BUFFER_MODE 1 TX_BUFFER_BYPASS_MODE Fast_Sync TX_PIPM_ENABLE false TX_OUTCLK_SOURCE TXPROGDIVCLK TXPROGDIV_FREQ_ENABLE true TXPROGDIV_FREQ_SOURCE LCPLL TXPROGDIV_FREQ_VAL 664.062\ +TX_DIFF_SWING_EMPH_MODE CUSTOM TX_64B66B_SCRAMBLER false TX_64B66B_ENCODER false TX_64B66B_CRC false TX_RATE_GROUP A TX_LANE_DESKEW_HDMI_ENABLE false TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE PRESET GTM-PAM4_Ethernet_53G\ +RX_PAM_SEL PAM4 RX_HD_EN 0 RX_GRAY_BYP false RX_GRAY_LITTLEENDIAN false RX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false INTERNAL_PRESET PAM4_Ethernet_53G RX_LINE_RATE 53.125 RX_PLL_TYPE LCPLL RX_REFCLK_FREQUENCY\ +322.265625 RX_ACTUAL_REFCLK_FREQUENCY 322.265625183611 RX_FRACN_ENABLED true RX_FRACN_OVRD false RX_FRACN_NUMERATOR 0 RX_REFCLK_SOURCE R0 RX_DATA_DECODING RAW RX_USER_DATA_WIDTH 160 RX_INT_DATA_WIDTH 128\ +RX_BUFFER_MODE 1 RX_OUTCLK_SOURCE RXPROGDIVCLK RXPROGDIV_FREQ_ENABLE true RXPROGDIV_FREQ_SOURCE LCPLL RXPROGDIV_FREQ_VAL 664.062 RXRECCLK_FREQ_ENABLE false RXRECCLK_FREQ_VAL 0 INS_LOSS_NYQ 20 RX_EQ_MODE\ +AUTO RX_COUPLING AC RX_TERMINATION VCOM_VREF RX_RATE_GROUP A RX_TERMINATION_PROG_VALUE 800 RX_PPM_OFFSET 200 RX_64B66B_DESCRAMBLER false RX_64B66B_DECODER false RX_64B66B_CRC false OOB_ENABLE false RX_COMMA_ALIGN_WORD\ +1 RX_COMMA_SHOW_REALIGN_ENABLE true PCIE_ENABLE false RX_COMMA_P_ENABLE false RX_COMMA_M_ENABLE false RX_COMMA_DOUBLE_ENABLE false RX_COMMA_P_VAL 0101111100 RX_COMMA_M_VAL 1010000011 RX_COMMA_MASK 0000000000\ +RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_CB_NUM_SEQ 0 RX_CB_LEN_SEQ 1 RX_CB_MAX_SKEW 1 RX_CB_MAX_LEVEL 1 RX_CB_MASK 00000000 RX_CB_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000\ +RX_CB_K 00000000 RX_CB_DISP 00000000 RX_CB_MASK_0_0 false RX_CB_VAL_0_0 0000000000 RX_CB_K_0_0 false RX_CB_DISP_0_0 false RX_CB_MASK_0_1 false RX_CB_VAL_0_1 0000000000 RX_CB_K_0_1 false RX_CB_DISP_0_1\ +false RX_CB_MASK_0_2 false RX_CB_VAL_0_2 0000000000 RX_CB_K_0_2 false RX_CB_DISP_0_2 false RX_CB_MASK_0_3 false RX_CB_VAL_0_3 0000000000 RX_CB_K_0_3 false RX_CB_DISP_0_3 false RX_CB_MASK_1_0 false RX_CB_VAL_1_0\ +0000000000 RX_CB_K_1_0 false RX_CB_DISP_1_0 false RX_CB_MASK_1_1 false RX_CB_VAL_1_1 0000000000 RX_CB_K_1_1 false RX_CB_DISP_1_1 false RX_CB_MASK_1_2 false RX_CB_VAL_1_2 0000000000 RX_CB_K_1_2 false RX_CB_DISP_1_2\ +false RX_CB_MASK_1_3 false RX_CB_VAL_1_3 0000000000 RX_CB_K_1_3 false RX_CB_DISP_1_3 false RX_CC_NUM_SEQ 0 RX_CC_LEN_SEQ 1 RX_CC_PERIODICITY 5000 RX_CC_KEEP_IDLE DISABLE RX_CC_PRECEDENCE ENABLE RX_CC_REPEAT_WAIT\ +0 RX_CC_MASK 00000000 RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 RX_CC_K 00000000 RX_CC_DISP 00000000 RX_CC_MASK_0_0 false RX_CC_VAL_0_0 0000000000 RX_CC_K_0_0\ +false RX_CC_DISP_0_0 false RX_CC_MASK_0_1 false RX_CC_VAL_0_1 0000000000 RX_CC_K_0_1 false RX_CC_DISP_0_1 false RX_CC_MASK_0_2 false RX_CC_VAL_0_2 0000000000 RX_CC_K_0_2 false RX_CC_DISP_0_2 false RX_CC_MASK_0_3\ +false RX_CC_VAL_0_3 0000000000 RX_CC_K_0_3 false RX_CC_DISP_0_3 false RX_CC_MASK_1_0 false RX_CC_VAL_1_0 0000000000 RX_CC_K_1_0 false RX_CC_DISP_1_0 false RX_CC_MASK_1_1 false RX_CC_VAL_1_1 0000000000\ +RX_CC_K_1_1 false RX_CC_DISP_1_1 false RX_CC_MASK_1_2 false RX_CC_VAL_1_2 0000000000 RX_CC_K_1_2 false RX_CC_DISP_1_2 false RX_CC_MASK_1_3 false RX_CC_VAL_1_3 0000000000 RX_CC_K_1_3 false RX_CC_DISP_1_3\ +false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 RX_JTOL_FC 10 RX_JTOL_LF_SLOPE -20 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE MULTI RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN\ +DISABLE RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE RESET_SEQUENCE_INTERVAL 0 RX_COMMA_PRESET NONE RX_COMMA_VALID_ONLY 0 GT_TYPE GTM} \ + CONFIG.PROT0_LR10_SETTINGS {NA NA} \ + CONFIG.PROT0_LR11_SETTINGS {NA NA} \ + CONFIG.PROT0_LR12_SETTINGS {NA NA} \ + CONFIG.PROT0_LR13_SETTINGS {NA NA} \ + CONFIG.PROT0_LR14_SETTINGS {NA NA} \ + CONFIG.PROT0_LR15_SETTINGS {NA NA} \ + CONFIG.PROT0_LR1_SETTINGS {NA NA} \ + CONFIG.PROT0_LR2_SETTINGS {NA NA} \ + CONFIG.PROT0_LR3_SETTINGS {NA NA} \ + CONFIG.PROT0_LR4_SETTINGS {NA NA} \ + CONFIG.PROT0_LR5_SETTINGS {NA NA} \ + CONFIG.PROT0_LR6_SETTINGS {NA NA} \ + CONFIG.PROT0_LR7_SETTINGS {NA NA} \ + CONFIG.PROT0_LR8_SETTINGS {NA NA} \ + CONFIG.PROT0_LR9_SETTINGS {NA NA} \ + CONFIG.PROT0_NO_OF_LANES {4} \ + CONFIG.PROT0_RX_MASTERCLK_SRC {RX0} \ + CONFIG.PROT0_TX_MASTERCLK_SRC {TX0} \ + CONFIG.REFCLK_LIST {{/qsfp0_322mhz_clk_p[0]}} \ + CONFIG.REFCLK_STRING {HSCLK0_LCPLLGTREFCLK0 refclk_PROT0_R0_322.265625183611_MHz_unique1} \ + CONFIG.RX0_LANE_SEL {PROT0} \ + CONFIG.RX1_LANE_SEL {PROT0} \ + CONFIG.RX2_LANE_SEL {PROT0} \ + CONFIG.RX3_LANE_SEL {PROT0} \ + CONFIG.TX0_LANE_SEL {PROT0} \ + CONFIG.TX1_LANE_SEL {PROT0} \ + CONFIG.TX2_LANE_SEL {PROT0} \ + CONFIG.TX3_LANE_SEL {PROT0} \ + ] $gt_quad + + #CONFIG.QUAD_USAGE {${quad_usage}} \ + + set_property -dict [list \ + CONFIG.APB3_CLK_FREQUENCY.VALUE_MODE {auto} \ + CONFIG.CHANNEL_ORDERING.VALUE_MODE {auto} \ + CONFIG.GT_TYPE.VALUE_MODE {auto} \ + CONFIG.PROT0_ENABLE.VALUE_MODE {auto} \ + CONFIG.PROT0_GT_DIRECTION.VALUE_MODE {auto} \ + CONFIG.PROT0_LR0_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR10_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR11_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR12_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR13_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR14_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR15_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR1_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR2_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR3_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR4_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR5_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR6_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR7_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR8_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_LR9_SETTINGS.VALUE_MODE {auto} \ + CONFIG.PROT0_NO_OF_LANES.VALUE_MODE {auto} \ + CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE {auto} \ + CONFIG.PROT0_TX_MASTERCLK_SRC.VALUE_MODE {auto} \ + CONFIG.QUAD_USAGE.VALUE_MODE {auto} \ + CONFIG.REFCLK_LIST.VALUE_MODE {auto} \ + CONFIG.RX0_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX1_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX2_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.RX3_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX0_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX1_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX2_LANE_SEL.VALUE_MODE {auto} \ + CONFIG.TX3_LANE_SEL.VALUE_MODE {auto} \ + ] $gt_quad + + } + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant xlconstant_0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_0 + + # Create instance: bufg_gt_odiv2, and set properties + set bufg_gt_odiv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:bufg_gt bufg_gt_odiv2 ] + + # Create instance: util_ds_buf_mbufg_rx_0, and set properties + set util_ds_buf_mbufg_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_mbufg_rx_0 ] + set_property -dict [list \ + CONFIG.C_BUFG_GT_SYNC {true} \ + CONFIG.C_BUF_TYPE {MBUFG_GT} \ + ] $util_ds_buf_mbufg_rx_0 + + + # Create instance: util_ds_buf_mbufg_tx_0, and set properties + set util_ds_buf_mbufg_tx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_mbufg_tx_0 ] + set_property -dict [list \ + CONFIG.C_BUFGCE_DIV {1} \ + CONFIG.C_BUFG_GT_SYNC {true} \ + CONFIG.C_BUF_TYPE {MBUFG_GT} \ + ] $util_ds_buf_mbufg_tx_0 + + + # Create instance: xlslice_gt_txpostcursor, and set properties + set xlslice_gt_txpostcursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txpostcursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {23} \ + CONFIG.DIN_TO {18} \ + ] $xlslice_gt_txpostcursor + + + # Create instance: xlslice_gt_txprecursor, and set properties + set xlslice_gt_txprecursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txprecursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {17} \ + CONFIG.DIN_TO {12} \ + ] $xlslice_gt_txprecursor + + + # Create instance: xlslice_gt_txmaincursor, and set properties + set xlslice_gt_txmaincursor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_txmaincursor ] + set_property -dict [list \ + CONFIG.DIN_FROM {30} \ + CONFIG.DIN_TO {24} \ + ] $xlslice_gt_txmaincursor + + + # Create instance: xlslice_gt_line_rate, and set properties + set xlslice_gt_line_rate [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_line_rate ] + set_property -dict [list \ + CONFIG.DIN_FROM {8} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_gt_line_rate + + + # Create instance: xlslice_gt_rxcdrhold, and set properties + set xlslice_gt_rxcdrhold [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice: xlslice_gt_rxcdrhold ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {31} \ + ] $xlslice_gt_rxcdrhold + + + # Create instance: xlslice_gt_loopback, and set properties + set xlslice_gt_loopback [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_loopback ] + set_property -dict [list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {9} \ + ] $xlslice_gt_loopback + + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins qsfp_clk_322mhz] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D1] + + # Create port connections + connect_bd_net [get_bd_pins gt_control_pins] [get_bd_pins xlslice_gt_txpostcursor/Din] [get_bd_pins xlslice_gt_txprecursor/Din] [get_bd_pins xlslice_gt_txmaincursor/Din] [get_bd_pins xlslice_gt_line_rate/Din] [get_bd_pins xlslice_gt_rxcdrhold/Din] [get_bd_pins xlslice_gt_loopback/Din] + connect_bd_net [get_bd_pins bufg_gt_odiv2/usrclk] [get_bd_pins GT0_ref_clk] + connect_bd_net [get_bd_pins MBUFG_GT_CLR] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins MBUFG_GT_CLRB_LEAF] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins MBUFG_GT_CLR1] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins MBUFG_GT_CLRB_LEAF1] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins gt0_quad/ch0_rxoutclk] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_I] + connect_bd_net [get_bd_pins gt0_quad/ch0_txoutclk] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_I] + connect_bd_net [get_bd_pins util_ds_buf_0/IBUFDS_GTME5_ODIV2] [get_bd_pins bufg_gt_odiv2/outclk] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O1] [get_bd_pins qsfp0_rx_usr_clk_664mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O2] [get_bd_pins qsfp0_rx_usr_clk_332mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O1] [get_bd_pins qsfp0_tx_usr_clk_664mhz] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O2] [get_bd_pins qsfp0_tx_usr_clk_332mhz] + connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_CE] [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_CE] + + foreach idx ${list_quad_index} { + connect_bd_net [get_bd_pins apb3clk_quad] [get_bd_pins gt${idx}_quad/apb3clk] + connect_bd_net [get_bd_pins gt${idx}_ch0_iloreset] [get_bd_pins gt${idx}_quad/ch0_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch1_iloreset] [get_bd_pins gt${idx}_quad/ch1_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch2_iloreset] [get_bd_pins gt${idx}_quad/ch2_iloreset] + connect_bd_net [get_bd_pins gt${idx}_ch3_iloreset] [get_bd_pins gt${idx}_quad/ch3_iloreset] + connect_bd_net [get_bd_pins hsclk_pllreset${idx}] [get_bd_pins gt${idx}_quad/hsclk1_lcpllreset] [get_bd_pins gt${idx}_quad/hsclk0_rpllreset] [get_bd_pins gt${idx}_quad/hsclk1_rpllreset] [get_bd_pins gt${idx}_quad/hsclk0_lcpllreset] + + connect_bd_net [get_bd_pins gt${idx}_quad/ch0_iloresetdone] [get_bd_pins gt${idx}_ch0_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch1_iloresetdone] [get_bd_pins gt${idx}_ch1_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch2_iloresetdone] [get_bd_pins gt${idx}_ch2_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/ch3_iloresetdone] [get_bd_pins gt${idx}_ch3_iloresetdone] + connect_bd_net [get_bd_pins gt${idx}_quad/gtpowergood] [get_bd_pins gtpowergood_${idx}] + connect_bd_net [get_bd_pins gt${idx}_quad/hsclk0_lcplllock] [get_bd_pins hsclk_plllock${idx}] + connect_bd_net [get_bd_pins xlslice_gt_rxcdrhold/Dout] [get_bd_pins gt${idx}_quad/ch1_rxcdrhold] [get_bd_pins gt${idx}_quad/ch2_rxcdrhold] [get_bd_pins gt${idx}_quad/ch3_rxcdrhold] [get_bd_pins gt${idx}_quad/ch0_rxcdrhold] + connect_bd_net [get_bd_pins xlslice_gt_txmaincursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txmaincursor] [get_bd_pins gt${idx}_quad/ch2_txmaincursor] [get_bd_pins gt${idx}_quad/ch3_txmaincursor] [get_bd_pins gt${idx}_quad/ch0_txmaincursor] + connect_bd_net [get_bd_pins xlslice_gt_txpostcursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txpostcursor] [get_bd_pins gt${idx}_quad/ch2_txpostcursor] [get_bd_pins gt${idx}_quad/ch3_txpostcursor] [get_bd_pins gt${idx}_quad/ch0_txpostcursor] + connect_bd_net [get_bd_pins xlslice_gt_txprecursor/Dout] [get_bd_pins gt${idx}_quad/ch1_txprecursor] [get_bd_pins gt${idx}_quad/ch2_txprecursor] [get_bd_pins gt${idx}_quad/ch3_txprecursor] [get_bd_pins gt${idx}_quad/ch0_txprecursor] + connect_bd_net [get_bd_pins s_axi_aresetn] [get_bd_pins gt${idx}_quad/apb3presetn] + connect_bd_net [get_bd_pins xlslice_gt_line_rate/Dout] [get_bd_pins gt${idx}_quad/ch0_rxrate] [get_bd_pins gt${idx}_quad/ch3_txrate] [get_bd_pins gt${idx}_quad/ch3_rxrate] [get_bd_pins gt${idx}_quad/ch2_txrate] [get_bd_pins gt${idx}_quad/ch2_rxrate] [get_bd_pins gt${idx}_quad/ch1_txrate] [get_bd_pins gt${idx}_quad/ch1_rxrate] [get_bd_pins gt${idx}_quad/ch0_txrate] + connect_bd_net [get_bd_pins xlslice_gt_loopback/Dout] [get_bd_pins gt${idx}_quad/ch3_loopback] [get_bd_pins gt${idx}_quad/ch2_loopback] [get_bd_pins gt${idx}_quad/ch1_loopback] [get_bd_pins gt${idx}_quad/ch0_loopback] + + connect_bd_net [get_bd_pins util_ds_buf_mbufg_tx_0/MBUFG_GT_O2] [get_bd_pins gt${idx}_quad/ch0_txusrclk] [get_bd_pins gt${idx}_quad/ch1_txusrclk] [get_bd_pins gt${idx}_quad/ch2_txusrclk] [get_bd_pins gt${idx}_quad/ch3_txusrclk] + connect_bd_net [get_bd_pins util_ds_buf_mbufg_rx_0/MBUFG_GT_O2] [get_bd_pins gt${idx}_quad/ch0_rxusrclk] [get_bd_pins gt${idx}_quad/ch1_rxusrclk] [get_bd_pins gt${idx}_quad/ch2_rxusrclk] [get_bd_pins gt${idx}_quad/ch3_rxusrclk] + connect_bd_net [get_bd_pins util_ds_buf_0/IBUFDS_GTME5_O] [get_bd_pins gt${idx}_quad/GT_REFCLK0] + + connect_bd_intf_net [get_bd_intf_pins RX0_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX0_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX1_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX1_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX2_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX2_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins RX3_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/RX3_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX0_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX0_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX1_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX1_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX2_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX2_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins TX3_GT${idx}_IP_Interface] [get_bd_intf_pins gt${idx}_quad/TX3_GT_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins GT${idx}_Serial] [get_bd_intf_pins gt${idx}_quad/GT_Serial] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Hierarchical cell: control_intf +proc create_hier_cell_control_intf { parentCell nameHier dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_control_intf() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DCMAC + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type clk clk_out_390 + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 31 -to 0 control_gt_rst + create_bd_pin -dir O -from 31 -to 0 tx_datapath_ctrl + create_bd_pin -dir O -from 31 -to 0 rx_datapath_ctrl + create_bd_pin -dir O -from 31 -to 0 reset_txrx_path + create_bd_pin -dir I -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir I -from 1 -to 0 gt0powergood + + # Create instance: smartconnect, and set properties + set smartconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect smartconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {5} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect + + # GT dynamic configuration parameters, setting up sensible values + set txmaincursor 52 + set txprecursor 6 + set txpostcursor 6 + + set gt_conf_value [format 0x%X [expr {(${txmaincursor} << 24) + (${txpostcursor} << 18) + (${txprecursor} << 12)}]] + + # Create instance: axi_gpio_gt_control, and set properties + set axi_gpio_gt_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_gt_control ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT ${gt_conf_value} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_gt_control + + # Create instance: axi_gpio_datapath, and set properties + set axi_gpio_datapath [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_datapath ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_DOUT_DEFAULT_2 {0x00000000} \ + ] $axi_gpio_datapath + + # Create instance: axi_gpio_monitor, and set properties + set axi_gpio_monitor [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_monitor ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS {1} + ] $axi_gpio_monitor + + # Create instance: axi_gpio_reset_txrx, and set properties + set axi_gpio_reset_txrx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_reset_txrx ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000000} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_reset_txrx + + set xlconcat_monitor [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_monitor ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.IN1_WIDTH {8} \ + CONFIG.IN2_WIDTH {2} \ + CONFIG.IN3_WIDTH {1} \ + CONFIG.NUM_PORTS {4} \ + ] $xlconcat_monitor + + set dualdcmac [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant dualdcmac ] + set_property CONFIG.CONST_VAL {0} $dualdcmac + + if { ${dual_dcmac} == "1" } { + set_property CONFIG.CONST_VAL {1} $dualdcmac + } + + # Create interface connections + connect_bd_intf_net -intf_net m_axi_0 [get_bd_intf_pins M_AXI_DCMAC] [get_bd_intf_pins smartconnect/M00_AXI] + connect_bd_intf_net -intf_net m_axi_1 [get_bd_intf_pins smartconnect/M01_AXI] [get_bd_intf_pins axi_gpio_datapath/S_AXI] + connect_bd_intf_net -intf_net m_axi_2 [get_bd_intf_pins smartconnect/M02_AXI] [get_bd_intf_pins axi_gpio_gt_control/S_AXI] + connect_bd_intf_net -intf_net m_axi_3 [get_bd_intf_pins smartconnect/M03_AXI] [get_bd_intf_pins axi_gpio_monitor/S_AXI] + connect_bd_intf_net -intf_net m_axi_4 [get_bd_intf_pins smartconnect/M04_AXI] [get_bd_intf_pins axi_gpio_reset_txrx/S_AXI] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins smartconnect/S00_AXI] + + # Create port connections + connect_bd_net -net control_gt_rst_gpio_io_o [get_bd_pins axi_gpio_gt_control/gpio_io_o] [get_bd_pins control_gt_rst] + connect_bd_net -net axi_gpio_datapath_gpio_io_o [get_bd_pins axi_gpio_datapath/gpio_io_o] [get_bd_pins rx_datapath_ctrl] + connect_bd_net -net axi_gpio_datapath_gpio2_io_o [get_bd_pins axi_gpio_datapath/gpio2_io_o] [get_bd_pins tx_datapath_ctrl] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_out_390] [get_bd_pins smartconnect/aclk1] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins smartconnect/aclk] [get_bd_pins axi_gpio_datapath/s_axi_aclk] [get_bd_pins axi_gpio_monitor/s_axi_aclk] [get_bd_pins axi_gpio_gt_control/s_axi_aclk] [get_bd_pins axi_gpio_reset_txrx/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins smartconnect/aresetn] [get_bd_pins axi_gpio_datapath/s_axi_aresetn] [get_bd_pins axi_gpio_monitor/s_axi_aresetn] [get_bd_pins axi_gpio_gt_control/s_axi_aresetn] [get_bd_pins axi_gpio_reset_txrx/s_axi_aresetn] + connect_bd_net -net qsfp_leds_gpio_io_o [get_bd_pins axi_gpio_reset_txrx/gpio_io_o] [get_bd_pins reset_txrx_path] + + connect_bd_net [get_bd_pins gt0_tx_reset_done] [get_bd_pins xlconcat_monitor/In0] + connect_bd_net [get_bd_pins gt0_rx_reset_done] [get_bd_pins xlconcat_monitor/In1] + connect_bd_net [get_bd_pins gt0powergood] [get_bd_pins xlconcat_monitor/In2] + connect_bd_net [get_bd_pins xlconcat_monitor/dout] [get_bd_pins axi_gpio_monitor/gpio_io_i] + connect_bd_net [get_bd_pins dualdcmac/dout] [get_bd_pins xlconcat_monitor/In3] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: DCMAC_subsys +proc create_hier_cell_DCMAC_subsys { parentCell nameHier dcmac_index dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_DCMAC_subsys() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0 + + # Additional interfaces for dual DCMAC + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_1 + } + + # Create pins + create_bd_pin -dir I -from 31 -to 0 control_gt_rst + create_bd_pin -dir I -from 31 -to 0 control_rx_datapath + create_bd_pin -dir I -type clk axi_clk_390mhz + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk core_clk_782mhz + create_bd_pin -dir I -from 5 -to 0 -type clk ts_clk_bus_350mhz + create_bd_pin -dir I -from 31 -to 0 control_tx_datapath + create_bd_pin -dir O -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir O -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -type rst aresetn_rx_390mhz + create_bd_pin -dir I -type rst aresetn_tx_390mhz + create_bd_pin -dir O -type gt_usrclk GT0_ref_clk + create_bd_pin -dir O -from 1 -to 0 gt0powergood + + # Create instance: xlslice_gt_reset, and set properties + set xlslice_gt_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_gt_reset ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_gt_reset + + # Create instance: rx_alt_serdes, and set properties + set rx_alt_serdes [create_bd_cell -type module -reference clock_to_serdes rx_alt_serdes] + + # Create instance: xlslice_rx_datapath_2, and set properties + set xlslice_rx_datapath_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_rx_datapath_2 + + # Create instance: rx_flexif_clk_clock_bus, and set properties + set rx_flexif_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus rx_flexif_clk_clock_bus] + + # Create instance: tx_alt_serdes, and set properties + set tx_alt_serdes [create_bd_cell -type module -reference clock_to_serdes tx_alt_serdes] + + # Create instance: tx_serdes, and set properties + set tx_serdes [create_bd_cell -type module -reference clock_to_serdes tx_serdes] + + set dcmac_name "dcmac_${dcmac_index}_core" + + if { ${dcmac_index} == "1" } { + set dcmac_loc "DCMAC_X0Y2" + } else { + set dcmac_loc "DCMAC_X1Y1" + } + + # Get the DCMAC version + set dcmac_version [get_property VERSION [get_ipdefs xilinx.com:ip:dcmac*]] + # Extract major version number + set dcmac_major_version [lindex [split ${dcmac_version} "."] 0] + + # Create instance: dcmac_core, and set properties + set dcmac_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:dcmac ${dcmac_name} ] + + set_property -dict [list \ + CONFIG.DCMAC_CONFIGURATION_TYPE {Static Configuration} \ + CONFIG.DCMAC_DATA_PATH_INTERFACE_C0 {391MHz Upto 6 Ports} \ + CONFIG.DCMAC_LOCATION_C0 $dcmac_loc \ + CONFIG.DCMAC_MODE_C0 {Coupled MAC+PCS} \ + CONFIG.FAST_SIM_MODE {0} \ + CONFIG.FEC_SLICE0_CFG_C0 {RS(544) CL119} \ + CONFIG.GT_PIPELINE_STAGES {7} \ + CONFIG.GT_REF_CLK_FREQ_C0 {322.265625} \ + CONFIG.GT_TYPE_C0 {GTM} \ + CONFIG.MAC_PORT0_CONFIG_C0 {200GAUI-4} \ + CONFIG.MAC_PORT0_ENABLE_C0 {1} \ + CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C0 {0} \ + CONFIG.MAC_PORT0_RX_FLOW_C0 {0} \ + CONFIG.MAC_PORT0_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT0_TX_FLOW_C0 {0} \ + CONFIG.MAC_PORT0_TX_INSERT_C0 {1} \ + CONFIG.MAC_PORT1_ENABLE_C0 {1} \ + CONFIG.MAC_PORT1_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT2_ENABLE_C0 {0} \ + CONFIG.MAC_PORT3_ENABLE_C0 {0} \ + CONFIG.MAC_PORT4_ENABLE_C0 {0} \ + CONFIG.MAC_PORT5_ENABLE_C0 {0} \ + CONFIG.NUM_GT_CHANNELS {4} \ + CONFIG.PHY_OPERATING_MODE_C0 {N/A} \ + CONFIG.PORT0_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT0_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT1_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT1_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT2_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT2_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT3_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT3_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT4_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT4_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.PORT5_1588v2_Clocking_C0 {Ordinary/Boundary Clock} \ + CONFIG.PORT5_1588v2_Operation_MODE_C0 {No operation} \ + CONFIG.TIMESTAMP_CLK_PERIOD_NS {4.0000} \ + ] $dcmac_core + + if { ${dual_dcmac} == "1" } { + set_property -dict [list \ + CONFIG.MAC_PORT2_ENABLE_C0 {1} \ + CONFIG.MAC_PORT2_RX_STRIP_C0 {1} \ + CONFIG.MAC_PORT3_ENABLE_C0 {1} \ + CONFIG.MAC_PORT3_RX_STRIP_C0 {1} \ + ] $dcmac_core + } + + #if get dcmac_core older than 2.5 + if {${dcmac_major_version} >= 3} { + set_property -dict [list \ + CONFIG.IS_GT_WIZ_OLD {1} \ + ] $dcmac_core + } + + # Create instance: dcmac200g_ctl_port + set dcmac200g_ctl_port [create_bd_cell -type module -reference dcmac200g_ctl_port dcmac200g_ctl_port] + + # Create instance: xlslice_tx_datapath_0, and set properties + set xlslice_tx_datapath_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_tx_datapath_0 + + # Create instance: xlslice_tx_datapath_1, and set properties + set xlslice_tx_datapath_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_tx_datapath_1 + + # Create instance: xlslice_tx_datapath_2, and set properties + set xlslice_tx_datapath_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_tx_datapath_2 + + # Create instance: xlslice_rx_datapath_0, and set properties + set xlslice_rx_datapath_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_rx_datapath_0 + + # Create instance: tx_flexif_clk_clock_bus, and set properties + set tx_flexif_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus tx_flexif_clk_clock_bus] + + # Create instance: xlslice_tx_datapath_3, and set properties + set xlslice_tx_datapath_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_tx_datapath_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_tx_datapath_3 + + # Create instance: rx_serdes, and set properties + set rx_serdes [create_bd_cell -type module -reference clock_to_serdes rx_serdes] + + # Create instance: xlslice_rx_datapath_1, and set properties + set xlslice_rx_datapath_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_rx_datapath_1 + + # Create instance: xlslice_rx_datapath_3, and set properties + set xlslice_rx_datapath_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_rx_datapath_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_rx_datapath_3 + + # Create instance: gt0_rx_reset_done, and set properties + set gt0_rx_reset_done [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat gt0_rx_reset_done ] + set_property CONFIG.NUM_PORTS {4} $gt0_rx_reset_done + + # Create instance: gt0_tx_reset_done, and set properties + set gt0_tx_reset_done [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat gt0_tx_reset_done ] + set_property CONFIG.NUM_PORTS {4} $gt0_tx_reset_done + + set num_loops [expr {$dual_dcmac}] + + for {set i 0} {$i <= $num_loops} {incr i} { + # Create instance: seg_to_axis, and set properties + create_bd_cell -type module -reference axis_seg_to_unseg_converter "seg_to_axis${i}" + # Create instance: axis_to_seg, and set properties + create_bd_cell -type module -reference axis_unseg_to_seg_converter "axis_to_seg${i}" + + set_property CONFIG.FREQ_HZ 390998840 [get_bd_intf_pins "seg_to_axis${i}/m_axis0_pkt_out"] + set_property CONFIG.FREQ_HZ 390998840 [get_bd_intf_pins "axis_to_seg${i}/s_axis0_pkt_in"] + } + + # Create instance: dcmac_gt0_wrapper + set dcmac_wrapper_name "dcmac_gt${dcmac_index}_wrapper" + create_hier_cell_dcmac_gt_wrapper $hier_obj ${dcmac_wrapper_name} ${dcmac_index} ${dual_dcmac} + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/qsfp_clk_322mhz] [get_bd_intf_pins qsfp_clk_322mhz] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_0] [get_bd_intf_pins ${dcmac_wrapper_name}/RX0_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_1] [get_bd_intf_pins ${dcmac_wrapper_name}/RX1_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_2] [get_bd_intf_pins ${dcmac_wrapper_name}/RX2_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_3] [get_bd_intf_pins ${dcmac_wrapper_name}/RX3_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_0] [get_bd_intf_pins ${dcmac_wrapper_name}/TX0_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_1] [get_bd_intf_pins ${dcmac_wrapper_name}/TX1_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_2] [get_bd_intf_pins ${dcmac_wrapper_name}/TX2_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_3] [get_bd_intf_pins ${dcmac_wrapper_name}/TX3_GT0_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins s_axi] [get_bd_intf_pins ${dcmac_name}/s_axi] + + if { ${dual_dcmac} == "1" } { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_4] [get_bd_intf_pins ${dcmac_wrapper_name}/RX0_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_5] [get_bd_intf_pins ${dcmac_wrapper_name}/RX1_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_6] [get_bd_intf_pins ${dcmac_wrapper_name}/RX2_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_rx_serdes_interface_7] [get_bd_intf_pins ${dcmac_wrapper_name}/RX3_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_4] [get_bd_intf_pins ${dcmac_wrapper_name}/TX0_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_5] [get_bd_intf_pins ${dcmac_wrapper_name}/TX1_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_6] [get_bd_intf_pins ${dcmac_wrapper_name}/TX2_GT1_IP_Interface] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_name}/gtm_tx_serdes_interface_7] [get_bd_intf_pins ${dcmac_wrapper_name}/TX3_GT1_IP_Interface] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/hsclk_plllock1] [get_bd_pins ${dcmac_name}/plllock_in_1] + connect_bd_net [get_bd_pins ${dcmac_name}/pllreset_out_1] [get_bd_pins ${dcmac_wrapper_name}/hsclk_pllreset1] + + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_4] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch0_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_5] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch1_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_6] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch2_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_7] [get_bd_pins ${dcmac_wrapper_name}/gt1_ch3_iloreset] + + # We need to swap the GT connections for DCMAC1 to make sure the GT aligment is correct + if { ${dcmac_index} == "1" } { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT1_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt1] + + connect_bd_intf_net [get_bd_intf_pins seg_to_axis1/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg1/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_1] + } else { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT1_Serial] [get_bd_intf_pins qsfp_gt1] + + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis1/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg1/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_1] + } + } else { + connect_bd_intf_net [get_bd_intf_pins ${dcmac_wrapper_name}/GT0_Serial] [get_bd_intf_pins qsfp_gt0] + connect_bd_intf_net [get_bd_intf_pins seg_to_axis0/m_axis0_pkt_out] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net [get_bd_intf_pins axis_to_seg0/s_axis0_pkt_in] [get_bd_intf_pins S_AXIS_0] + } + save_bd_design + # Create port connections + connect_bd_net -net aresetn_axis_seg_in1_1 [get_bd_pins aresetn_tx_390mhz] [get_bd_pins axis_to_seg0/aresetn_axis_seg_in] + connect_bd_net -net aresetn_axis_seg_in_1 [get_bd_pins aresetn_rx_390mhz] [get_bd_pins seg_to_axis0/aresetn_axis_seg_in] + connect_bd_net -net axi_gpio_gt_control_gpio_io_o [get_bd_pins control_gt_rst] [get_bd_pins xlslice_gt_reset/Din] [get_bd_pins ${dcmac_wrapper_name}/gt_control_pins] + connect_bd_net -net axi_gpio_rx_datapath_gpio_io_o [get_bd_pins control_rx_datapath] [get_bd_pins xlslice_rx_datapath_0/Din] [get_bd_pins xlslice_rx_datapath_1/Din] [get_bd_pins xlslice_rx_datapath_3/Din] [get_bd_pins xlslice_rx_datapath_2/Din] + connect_bd_net -net axi_gpio_tx_datapath_gpio_io_o [get_bd_pins control_tx_datapath] [get_bd_pins xlslice_tx_datapath_1/Din] [get_bd_pins xlslice_tx_datapath_2/Din] [get_bd_pins xlslice_tx_datapath_3/Din] [get_bd_pins xlslice_tx_datapath_0/Din] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins core_clk_782mhz] [get_bd_pins ${dcmac_name}/tx_core_clk] [get_bd_pins ${dcmac_name}/rx_core_clk] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins axi_clk_390mhz] [get_bd_pins ${dcmac_name}/rx_axi_clk] [get_bd_pins ${dcmac_name}/tx_axi_clk] [get_bd_pins tx_flexif_clk_clock_bus/clk] [get_bd_pins ${dcmac_name}/rx_macif_clk] [get_bd_pins ${dcmac_name}/tx_macif_clk] [get_bd_pins rx_flexif_clk_clock_bus/clk] [get_bd_pins seg_to_axis0/aclk_axis_seg_in] [get_bd_pins axis_to_seg0/aclk_axis_seg_in] + save_bd_design + #if get dcmac_core older than 3.0 + if {${dcmac_major_version} < 3} { + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_0] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch0_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_1] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch1_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_2] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch2_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/iloreset_out_3] [get_bd_pins ${dcmac_wrapper_name}/gt0_ch3_iloreset] + connect_bd_net [get_bd_pins ${dcmac_name}/pllreset_out_0] [get_bd_pins ${dcmac_wrapper_name}/hsclk_pllreset0] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/hsclk_plllock0] [get_bd_pins ${dcmac_name}/plllock_in_0] + } + connect_bd_net [get_bd_pins ${dcmac_name}/rx_clr_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLR] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_clrb_leaf_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLRB_LEAF] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_clr_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLR1] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_clrb_leaf_out_0] [get_bd_pins ${dcmac_wrapper_name}/MBUFG_GT_CLRB_LEAF1] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/GT0_ref_clk] [get_bd_pins GT0_ref_clk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_rx_usr_clk_332mhz] [get_bd_pins rx_alt_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_rx_usr_clk_664mhz] [get_bd_pins rx_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_tx_usr_clk_332mhz] [get_bd_pins tx_alt_serdes/usrclk] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/qsfp0_tx_usr_clk_664mhz] [get_bd_pins tx_serdes/usrclk] + connect_bd_net -net gt_reset_rx_datapath_in_0_1 [get_bd_pins xlslice_rx_datapath_0/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_0] + connect_bd_net -net gt_reset_rx_datapath_in_1_1 [get_bd_pins xlslice_rx_datapath_1/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_1] + connect_bd_net -net gt_reset_rx_datapath_in_2_1 [get_bd_pins xlslice_rx_datapath_2/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_2] + connect_bd_net -net gt_reset_rx_datapath_in_3_1 [get_bd_pins xlslice_rx_datapath_3/Dout] [get_bd_pins ${dcmac_name}/gt_reset_rx_datapath_in_3] + connect_bd_net -net gt_reset_tx_datapath_in_0_1 [get_bd_pins xlslice_tx_datapath_0/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_0] + connect_bd_net -net gt_reset_tx_datapath_in_1_1 [get_bd_pins xlslice_tx_datapath_1/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_1] + connect_bd_net -net gt_reset_tx_datapath_in_2_1 [get_bd_pins xlslice_tx_datapath_2/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_2] + connect_bd_net -net gt_reset_tx_datapath_in_3_1 [get_bd_pins xlslice_tx_datapath_3/Dout] [get_bd_pins ${dcmac_name}/gt_reset_tx_datapath_in_3] + connect_bd_net -net gt0_rx_reset_done_dout [get_bd_pins gt0_rx_reset_done/dout] [get_bd_pins gt0_rx_reset_done] + connect_bd_net -net gt0_tx_reset_done_dout [get_bd_pins gt0_tx_reset_done/dout] [get_bd_pins gt0_tx_reset_done] + connect_bd_net -net rx_flexif_clk_clock_bus_clockbus [get_bd_pins rx_flexif_clk_clock_bus/clockbus] [get_bd_pins ${dcmac_name}/rx_flexif_clk] + connect_bd_net -net rx_serdes_clk2_1 [get_bd_pins rx_alt_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/rx_alt_serdes_clk] + connect_bd_net -net rx_serdes_clk_1 [get_bd_pins rx_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/rx_serdes_clk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins ${dcmac_name}/s_axi_aresetn] [get_bd_pins ${dcmac_wrapper_name}/s_axi_aresetn] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins ts_clk_bus_350mhz] [get_bd_pins ${dcmac_name}/ts_clk] + connect_bd_net -net tx_flexif_clk_clock_bus_clockbus [get_bd_pins tx_flexif_clk_clock_bus/clockbus] [get_bd_pins ${dcmac_name}/tx_flexif_clk] + connect_bd_net -net tx_serdes_clk2_1 [get_bd_pins tx_alt_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/tx_alt_serdes_clk] + connect_bd_net -net tx_serdes_clk_1 [get_bd_pins tx_serdes/serdes_clk] [get_bd_pins ${dcmac_name}/tx_serdes_clk] + + for {set i 0} {$i <= $num_loops} {incr i} { + # AXI4 stream converter connections + for {set lane 0} {$lane <= 3} {incr lane} { + set lane_dcmac ${lane} + if { ${i} == "1" } { + set lane_dcmac "[expr {$lane + 4}]" + + } + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegEna${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_ena${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegDat${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tdata${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegSop${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_sop${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegEop${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_eop${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegErr${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_err${lane_dcmac}] + connect_bd_net [get_bd_pins axis_to_seg${i}/Unseg2SegMty${lane}_out] [get_bd_pins ${dcmac_name}/tx_axis_tuser_mty${lane_dcmac}] + + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tdata${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegDat${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_ena${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegEna${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_eop${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegEop${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_err${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegErr${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_mty${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegMty${lane}_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tuser_sop${lane_dcmac}] [get_bd_pins seg_to_axis${i}/Seg2UnSegSop${lane}_in] + save_bd_design + } + } + + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tvalid_0] [get_bd_pins seg_to_axis0/rx_axis_tvalid_i] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_axis_tready_0] [get_bd_pins axis_to_seg0/tx_axis_tready_in] + connect_bd_net [get_bd_pins axis_to_seg0/tx_axis_tvalid_out] [get_bd_pins ${dcmac_name}/tx_axis_tvalid_0] + + for {set lane 0} {$lane <= 3} {incr lane} { + connect_bd_net [get_bd_pins ${dcmac_name}/gt_tx_reset_done_out_${lane}] [get_bd_pins gt0_tx_reset_done/In${lane}] + connect_bd_net [get_bd_pins ${dcmac_name}/gt_rx_reset_done_out_${lane}] [get_bd_pins gt0_rx_reset_done/In${lane}] + } + + for {set id 0} {$id <= 19} {incr id} { + connect_bd_net [get_bd_pins dcmac200g_ctl_port/ctl_tx_vl_marker_id${id}] [get_bd_pins ${dcmac_name}/ctl_vl_marker_id${id}] + } + + if { ${dual_dcmac} == "1" } { + connect_bd_net [get_bd_pins aresetn_tx_390mhz] [get_bd_pins axis_to_seg1/aresetn_axis_seg_in] + connect_bd_net [get_bd_pins aresetn_rx_390mhz] [get_bd_pins seg_to_axis1/aresetn_axis_seg_in] + connect_bd_net [get_bd_pins axi_clk_390mhz] [get_bd_pins seg_to_axis1/aclk_axis_seg_in] [get_bd_pins axis_to_seg1/aclk_axis_seg_in] + connect_bd_net [get_bd_pins ${dcmac_name}/rx_axis_tvalid_2] [get_bd_pins seg_to_axis1/rx_axis_tvalid_i] + connect_bd_net [get_bd_pins ${dcmac_name}/tx_axis_tready_2] [get_bd_pins axis_to_seg1/tx_axis_tready_in] + connect_bd_net [get_bd_pins axis_to_seg1/tx_axis_tvalid_out] [get_bd_pins ${dcmac_name}/tx_axis_tvalid_2] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch0_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_4] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch1_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_5] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch2_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_6] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt1_ch3_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_7] + } + + connect_bd_net [get_bd_pins dcmac200g_ctl_port/default_vl_length_200GE_or_400GE] [get_bd_pins ${dcmac_name}/ctl_rx_custom_vl_length_minus1] [get_bd_pins ${dcmac_name}/ctl_tx_custom_vl_length_minus1] + + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gtpowergood_0] [get_bd_pins ${dcmac_name}/gtpowergood_in] [get_bd_pins gt0powergood] + connect_bd_net [get_bd_pins xlslice_gt_reset/Dout] [get_bd_pins ${dcmac_name}/gt_reset_all_in] + save_bd_design + #if get dcmac_core older than 3.0 + if {${dcmac_major_version} < 3} { + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch0_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_0] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch1_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_1] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch2_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_2] + connect_bd_net [get_bd_pins ${dcmac_wrapper_name}/gt0_ch3_iloresetdone] [get_bd_pins ${dcmac_name}/ilo_reset_done_3] + } + + connect_bd_net [get_bd_pins s_axi_aclk] [get_bd_pins ${dcmac_name}/s_axi_aclk] [get_bd_pins ${dcmac_wrapper_name}/apb3clk_quad] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: clk_n_resets +proc create_hier_cell_clk_n_resets { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_clk_n_resets() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir O -type clk clk_out_390 + create_bd_pin -dir I -from 7 -to 0 gt0_tx_reset_done + create_bd_pin -dir I -type clk gt_ref_clk_322mhz + create_bd_pin -dir O -type clk clk_out_782 + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 0 -to 0 -type rst aresetn_tx_390mhz + create_bd_pin -dir O -from 0 -to 0 -type rst aresetn_rx_390mhz + create_bd_pin -dir I -from 7 -to 0 gt0_rx_reset_done + create_bd_pin -dir O -from 5 -to 0 clockbus_350 + create_bd_pin -dir I -from 31 -to 0 reset_txrx_path + + # Create instance: syncer_tx_reset, and set properties + set syncer_tx_reset [create_bd_cell -type module -reference dcmac_syncer_reset syncer_tx_reset] + + # Create instance: clk_wizard_0, and set properties + set clk_wizard_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard clk_wizard_0 ] + set_property -dict [list \ + CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ + CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ + CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \ + CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \ + CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ + CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ + CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {782,390.625,350,100.000,100.000,100.000,100.000} \ + CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ + CONFIG.CLKOUT_USED {true,true,true,false,false,false,false} \ + CONFIG.OVERRIDE_PRIMITIVE {false} \ + CONFIG.PRIM_IN_FREQ {322.265625} \ + CONFIG.PRIM_SOURCE {Global_buffer} \ + CONFIG.USE_LOCKED {true} \ + ] $clk_wizard_0 + + + # Create instance: sys_reset_tx, and set properties + set sys_reset_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_tx ] + + # Create instance: sys_reset_rx, and set properties + set sys_reset_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_rx ] + + # Create instance: syncer_rx_reset, and set properties + set syncer_rx_reset [create_bd_cell -type module -reference dcmac_syncer_reset syncer_rx_reset] + + # Create instance: ts_clk_clk_clock_bus, and set properties + set ts_clk_clk_clock_bus [create_bd_cell -type module -reference clock_to_clock_bus ts_clk_clk_clock_bus] + + # Create instance: util_vector_logic_not, and set properties + set util_vector_logic_not [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic util_vector_logic_not] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {32} \ + ] $util_vector_logic_not + + set xlslice_reset_rx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_rx0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + ] $xlslice_reset_rx0 + + set xlslice_reset_tx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_tx0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + ] $xlslice_reset_tx0 + + set xlslice_reset_rx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_rx1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + ] $xlslice_reset_rx1 + + set xlslice_reset_tx1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice xlslice_reset_tx1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + ] $xlslice_reset_tx1 + + set xlconcat_rx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_rx0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH.VALUE_SRC USER \ + CONFIG.IN1_WIDTH.VALUE_SRC USER \ + CONFIG.IN0_WIDTH {4} \ + CONFIG.IN1_WIDTH {1} \ + ] $xlconcat_rx0 + + set xlconcat_tx0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_tx0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH.VALUE_SRC USER \ + CONFIG.IN1_WIDTH.VALUE_SRC USER \ + CONFIG.IN0_WIDTH {4} \ + CONFIG.IN1_WIDTH {1} \ + ] $xlconcat_tx0 + + + set and_reduced_rx [create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic and_reduced_rx] + set_property -dict [list \ + CONFIG.C_SIZE {5} \ + ] $and_reduced_rx + + set and_reduced_tx [create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic and_reduced_tx] + set_property -dict [list \ + CONFIG.C_SIZE {5} \ + ] $and_reduced_tx + + # Create port connections + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_wizard_0/clk_out1] [get_bd_pins clk_out_782] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_wizard_0/clk_out2] [get_bd_pins clk_out_390] [get_bd_pins sys_reset_tx/slowest_sync_clk] [get_bd_pins sys_reset_rx/slowest_sync_clk] [get_bd_pins syncer_rx_reset/clk] [get_bd_pins syncer_tx_reset/clk] + connect_bd_net -net clk_wizard_0_clk_out3 [get_bd_pins clk_wizard_0/clk_out3] [get_bd_pins ts_clk_clk_clock_bus/clk] + connect_bd_net -net clk_wizard_0_locked [get_bd_pins clk_wizard_0/locked] [get_bd_pins syncer_rx_reset/clk_wizard_lock] [get_bd_pins syncer_tx_reset/clk_wizard_lock] + connect_bd_net -net dcmac_0_gt_wrapper_IBUFDS_ODIV2 [get_bd_pins gt_ref_clk_322mhz] [get_bd_pins clk_wizard_0/clk_in1] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins sys_reset_rx/aux_reset_in] [get_bd_pins sys_reset_tx/aux_reset_in] + connect_bd_net -net syncer_rx_reset_resetn [get_bd_pins syncer_rx_reset/resetn] [get_bd_pins sys_reset_rx/ext_reset_in] + connect_bd_net -net syncer_tx_reset_resetn [get_bd_pins syncer_tx_reset/resetn] [get_bd_pins sys_reset_tx/ext_reset_in] + connect_bd_net -net sys_reset_rx_peripheral_aresetn [get_bd_pins sys_reset_rx/peripheral_aresetn] [get_bd_pins aresetn_rx_390mhz] + connect_bd_net -net sys_reset_tx_peripheral_aresetn [get_bd_pins sys_reset_tx/peripheral_aresetn] [get_bd_pins aresetn_tx_390mhz] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins ts_clk_clk_clock_bus/clockbus] [get_bd_pins clockbus_350] + + connect_bd_net [get_bd_pins gt0_rx_reset_done] [get_bd_pins xlconcat_rx0/In0] + connect_bd_net [get_bd_pins xlslice_reset_rx0/Dout] [get_bd_pins xlconcat_rx0/In1] + connect_bd_net [get_bd_pins xlconcat_rx0/dout] [get_bd_pins and_reduced_rx/Op1] + connect_bd_net [get_bd_pins and_reduced_rx/Res] [get_bd_pins syncer_rx_reset/resetn_async] + connect_bd_net [get_bd_pins gt0_tx_reset_done] [get_bd_pins xlconcat_tx0/In0] + connect_bd_net [get_bd_pins xlslice_reset_tx0/Dout] [get_bd_pins xlconcat_tx0/In1] + connect_bd_net [get_bd_pins xlconcat_tx0/dout] [get_bd_pins and_reduced_tx/Op1] + connect_bd_net [get_bd_pins and_reduced_tx/Res] [get_bd_pins syncer_tx_reset/resetn_async] + connect_bd_net [get_bd_pins reset_txrx_path] [get_bd_pins util_vector_logic_not/Op1] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_rx0/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_rx1/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_tx0/Din] + connect_bd_net [get_bd_pins util_vector_logic_not/Res] [get_bd_pins xlslice_reset_tx1/Din] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: qsfp_0_n_1 +proc create_hier_cell_qsfp { parentCell nameHier dcmac_index dual_dcmac} { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_qsfp() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp_clk_322mhz + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0 + + # Additional port for dual DCMAC + if { ${dual_dcmac} == "1" } { + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp_gt1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_1 + } + + # Create pins + create_bd_pin -dir I -type clk ap_clk + #create_bd_pin -dir I -type clk ap_clk_eth0 + create_bd_pin -dir I -type rst ap_rst_n + + set num_loops [expr {$dual_dcmac}] + + for {set i 0} {$i <= $num_loops} {incr i} { + # Create instance: adwc0_512_1024, and set properties + set adwc_512_1024 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter "adwc${i}_512_1024" ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {128} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.TUSER_BITS_PER_BYTE {1} \ + ] $adwc_512_1024 + + # Create instance: adwc0_1024_512, and set properties + set adwc_1024_512 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter "adwc${i}_1024_512" ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDATA_NUM_BYTES {128} \ + CONFIG.TUSER_BITS_PER_BYTE {1} \ + ] $adwc_1024_512 + + # Create instance: tx_packet_fifo_cdc, and set properties + set tx_packet_fifo_cdc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo "tx${i}_packet_fifo_cdc" ] + set_property -dict [list \ + CONFIG.HAS_TLAST.VALUE_SRC USER \ + CONFIG.FIFO_DEPTH {512} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.IS_ACLK_ASYNC {1} \ + ] $tx_packet_fifo_cdc + + # Create instance: rx_fifo_cdc, and set properties + set rx_fifo_cdc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo "rx${i}_fifo_cdc" ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {128} \ + CONFIG.FIFO_MODE {1} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.IS_ACLK_ASYNC {1} \ + ] $rx_fifo_cdc + } + # Create instance: clk_n_resets + create_hier_cell_clk_n_resets $hier_obj clk_n_resets + + # Create instance: DCMAC_subsys + create_hier_cell_DCMAC_subsys $hier_obj DCMAC_subsys ${dcmac_index} ${dual_dcmac} + + # Create instance: control_intf + create_hier_cell_control_intf $hier_obj control_intf ${dual_dcmac} + + # Create interface connections + connect_bd_intf_net -intf_net DCMAC_subsys_M_AXIS_0 [get_bd_intf_pins adwc0_1024_512/S_AXIS] [get_bd_intf_pins DCMAC_subsys/M_AXIS_0] + connect_bd_intf_net -intf_net DCMAC_subsys_qsfp_gt [get_bd_intf_pins qsfp_gt0] [get_bd_intf_pins DCMAC_subsys/qsfp_gt0] + connect_bd_intf_net -intf_net adwc0_1024_512_M_AXIS [get_bd_intf_pins adwc0_1024_512/M_AXIS] [get_bd_intf_pins rx0_fifo_cdc/S_AXIS] + connect_bd_intf_net -intf_net rx0_fifo_cdc_M_AXIS [get_bd_intf_pins rx0_fifo_cdc/M_AXIS] [get_bd_intf_pins M_AXIS_0] + connect_bd_intf_net -intf_net adwc0_512_1024_M_AXIS [get_bd_intf_pins adwc0_512_1024/M_AXIS] [get_bd_intf_pins DCMAC_subsys/S_AXIS_0] + connect_bd_intf_net -intf_net m_axi_0 [get_bd_intf_pins control_intf/M_AXI_DCMAC] [get_bd_intf_pins DCMAC_subsys/s_axi] + connect_bd_intf_net -intf_net packet_fifo_M_AXIS [get_bd_intf_pins tx0_packet_fifo_cdc/M_AXIS] [get_bd_intf_pins adwc0_512_1024/S_AXIS] + connect_bd_intf_net -intf_net qsfp_clk_322mhz_1 [get_bd_intf_pins qsfp_clk_322mhz] [get_bd_intf_pins DCMAC_subsys/qsfp_clk_322mhz] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins control_intf/S_AXI] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins control_intf/S_AXI] + connect_bd_intf_net [get_bd_intf_pins S_AXIS_0] [get_bd_intf_pins tx0_packet_fifo_cdc/S_AXIS] + + # Create port connections + connect_bd_net -net axi_gpio_gt_control_gpio_io_o [get_bd_pins control_intf/control_gt_rst] [get_bd_pins DCMAC_subsys/control_gt_rst] + connect_bd_net -net axi_gpio_rx_datapath_gpio_io_o [get_bd_pins control_intf/rx_datapath_ctrl] [get_bd_pins DCMAC_subsys/control_rx_datapath] + connect_bd_net -net axi_gpio_tx_datapath_gpio_io_o [get_bd_pins control_intf/tx_datapath_ctrl] [get_bd_pins DCMAC_subsys/control_tx_datapath] + connect_bd_net [get_bd_pins control_intf/gt0powergood] [get_bd_pins DCMAC_subsys/gt0powergood] + connect_bd_net [get_bd_pins control_intf/reset_txrx_path] [get_bd_pins clk_n_resets/reset_txrx_path] + + connect_bd_net -net gt_ref_clk_322mhz_1 [get_bd_pins DCMAC_subsys/GT0_ref_clk] [get_bd_pins clk_n_resets/gt_ref_clk_322mhz] + connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins clk_n_resets/clk_out_782] [get_bd_pins DCMAC_subsys/core_clk_782mhz] + connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_n_resets/clk_out_390] [get_bd_pins adwc0_512_1024/aclk] [get_bd_pins adwc0_1024_512/aclk] [get_bd_pins tx0_packet_fifo_cdc/m_axis_aclk] [get_bd_pins DCMAC_subsys/axi_clk_390mhz] [get_bd_pins control_intf/clk_out_390] [get_bd_pins rx0_fifo_cdc/s_axis_aclk] + connect_bd_net -net gt0_rx_reset_done_dout [get_bd_pins DCMAC_subsys/gt0_rx_reset_done] [get_bd_pins clk_n_resets/gt0_rx_reset_done] [get_bd_pins control_intf/gt0_rx_reset_done] + connect_bd_net -net gt0_tx_reset_done_dout [get_bd_pins DCMAC_subsys/gt0_tx_reset_done] [get_bd_pins clk_n_resets/gt0_tx_reset_done] [get_bd_pins control_intf/gt0_tx_reset_done] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins ap_clk] [get_bd_pins DCMAC_subsys/s_axi_aclk] [get_bd_pins control_intf/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins ap_rst_n] [get_bd_pins clk_n_resets/s_axi_aresetn] [get_bd_pins DCMAC_subsys/s_axi_aresetn] [get_bd_pins control_intf/s_axi_aresetn] + connect_bd_net -net sys_reset_rx_peripheral_aresetn [get_bd_pins clk_n_resets/aresetn_rx_390mhz] [get_bd_pins DCMAC_subsys/aresetn_rx_390mhz] [get_bd_pins adwc0_1024_512/aresetn] [get_bd_pins rx0_fifo_cdc/s_axis_aresetn] + connect_bd_net -net sys_reset_tx_peripheral_aresetn [get_bd_pins clk_n_resets/aresetn_tx_390mhz] [get_bd_pins adwc0_512_1024/aresetn] [get_bd_pins tx0_packet_fifo_cdc/s_axis_aresetn] [get_bd_pins DCMAC_subsys/aresetn_tx_390mhz] + connect_bd_net -net ts_clk_clk_clock_bus_clockbus [get_bd_pins clk_n_resets/clockbus_350] [get_bd_pins DCMAC_subsys/ts_clk_bus_350mhz] + + connect_bd_net [get_bd_pins ap_clk] [get_bd_pins tx0_packet_fifo_cdc/s_axis_aclk] [get_bd_pins rx0_fifo_cdc/m_axis_aclk] + + if { ${dual_dcmac} == "1" } { + connect_bd_intf_net [get_bd_intf_pins qsfp_gt1] [get_bd_intf_pins DCMAC_subsys/qsfp_gt1] + connect_bd_intf_net [get_bd_intf_pins adwc1_1024_512/S_AXIS] [get_bd_intf_pins DCMAC_subsys/M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins adwc1_512_1024/M_AXIS] [get_bd_intf_pins DCMAC_subsys/S_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins rx1_fifo_cdc/M_AXIS] [get_bd_intf_pins M_AXIS_1] + connect_bd_intf_net [get_bd_intf_pins tx1_packet_fifo_cdc/M_AXIS] [get_bd_intf_pins adwc1_512_1024/S_AXIS] + connect_bd_intf_net [get_bd_intf_pins adwc1_1024_512/M_AXIS] [get_bd_intf_pins rx1_fifo_cdc/S_AXIS] + connect_bd_intf_net [get_bd_intf_pins S_AXIS_1] [get_bd_intf_pins tx1_packet_fifo_cdc/S_AXIS] + + connect_bd_net [get_bd_pins clk_n_resets/clk_out_390] [get_bd_pins adwc1_512_1024/aclk] [get_bd_pins adwc1_1024_512/aclk] [get_bd_pins tx1_packet_fifo_cdc/m_axis_aclk] [get_bd_pins rx1_fifo_cdc/s_axis_aclk] + connect_bd_net [get_bd_pins ap_clk] [get_bd_pins tx1_packet_fifo_cdc/s_axis_aclk] [get_bd_pins rx1_fifo_cdc/m_axis_aclk] + connect_bd_net [get_bd_pins clk_n_resets/aresetn_tx_390mhz] [get_bd_pins adwc1_512_1024/aresetn] [get_bd_pins tx1_packet_fifo_cdc/s_axis_aresetn] + connect_bd_net [get_bd_pins clk_n_resets/aresetn_rx_390mhz] [get_bd_pins adwc1_1024_512/aresetn] [get_bd_pins rx1_fifo_cdc/s_axis_aresetn] + } + + save_bd_design + # Restore current instance + current_bd_instance $oldCurInst +} + +# Generic function that creates the qsfp block +proc create_qsfp_hierarchy { dcmac_index dual_dcmac} { + + if {![string is integer -strict $dcmac_index] || !($dcmac_index == 0 || $dcmac_index == 1)} { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "dcmac_index (with value $dcmac_index) is not correct. Valid values are 0 and 1"} + return + } + + if {![string is integer -strict $dual_dcmac] || !($dual_dcmac == 0 || $dual_dcmac == 1)} { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "dual_dcmac (with value $dual_dcmac) is not correct. Valid values are 0 or 1"} + return + } + + # TODO use dual_dcmac + if { ${dcmac_index} == "0" } { + set new_index $dcmac_index + set offset_increment 0 + } else { + set new_index "[expr {$dcmac_index + 1}]" + set offset_increment 0x1000000 + } + + set qsfp_hier_name "qsfp_${new_index}_n_[expr {$new_index + 1}]" + + create_hier_cell_qsfp [current_bd_instance .] ${qsfp_hier_name} ${dcmac_index} ${dual_dcmac} + save_bd_design + +proc get_or_create_bd_intf_port {name mode vlnv} { + set p [get_bd_intf_ports -quiet $name] + if {[llength $p] == 0} { + return [create_bd_intf_port -mode $mode -vlnv $vlnv $name] + } + return [lindex $p 0] +} + +# ----------------------------- +# qsfp${new_index}_4x (GT) +# ----------------------------- +set qsfp_gt0_name "qsfp${new_index}_4x" +set qsfp_gt0_4x [get_or_create_bd_intf_port $qsfp_gt0_name Master "xilinx.com:interface:gt_rtl:1.0"] + +# ----------------------------- +# qsfp${new_index}_322mhz (diff clock) +# ----------------------------- +set qsfp_gt_clk_port_name "qsfp${new_index}_322mhz" +set qsfp_gt_clk_name [get_or_create_bd_intf_port $qsfp_gt_clk_port_name Slave "xilinx.com:interface:diff_clock_rtl:1.0"] + +# Apply the clock property +set_property -dict [list CONFIG.FREQ_HZ {322265625}] $qsfp_gt_clk_name + +save_bd_design + +# Connect using the *object handles* you already have +connect_bd_intf_net $qsfp_gt0_4x [get_bd_intf_pins ${qsfp_hier_name}/qsfp_gt0] + +if { $dual_dcmac == "1" } { + set qsfp_gt1_name "qsfp[expr {$new_index + 1}]_4x" + set qsfp_gt1_4x [get_or_create_bd_intf_port $qsfp_gt1_name Master "xilinx.com:interface:gt_rtl:1.0"] + connect_bd_intf_net $qsfp_gt1_4x [get_bd_intf_pins ${qsfp_hier_name}/qsfp_gt1] +} + +connect_bd_intf_net $qsfp_gt_clk_name [get_bd_intf_pins ${qsfp_hier_name}/qsfp_clk_322mhz] +save_bd_design + + + assign_bd_address -offset [expr {0x020302000000 + ${offset_increment}}] -range 256K -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/DCMAC_subsys/dcmac_${dcmac_index}_core/s_axi/Reg] -force + assign_bd_address -offset [expr {0x020302040000 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020302040200 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020302040400 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset [expr {0x020302040600 + ${offset_increment}}] -range 256 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs ${qsfp_hier_name}/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + save_bd_design +} + +# proc add_dcmac {} { +# source "src/dcmac/tcl/dcmac_config.tcl" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/axis_seg_to_unseg_converter.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/clock_to_clock_bus.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/dcmac200g_ctl_port.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/serdes_clock.v" +# import_files -fileset sources_1 -norecurse "src/dcmac/hdl/syncer_reset.v" + +# # Create network hierarchy +# if { ${DCMAC0_ENABLED} == "1" } { +# create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} +# } +# if { ${DCMAC1_ENABLED} == "1" } { +# create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} +# } +# } + +#add_dcmac \ No newline at end of file diff --git a/linker/slashkit/resources/dcmac/tcl/dcmac_config.tcl b/linker/slashkit/resources/dcmac/tcl/dcmac_config.tcl new file mode 100644 index 00000000..82b0afea --- /dev/null +++ b/linker/slashkit/resources/dcmac/tcl/dcmac_config.tcl @@ -0,0 +1,27 @@ +# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT + +# A front view of the V80 and QSFP56 index and associated DCMAC +# Use this diagram to guide the configuration +# +# _________________________ +# | 0 | 1 | 2 | 3 | +# ----------------------------> PCIe +# +# \___________/\__________/ +# | | +# DCMAC0 DCMAC1 + + +### Enable the DCMAC core(s) that you wish to use +set DCMAC0_ENABLED 1 +set DCMAC1_ENABLED 1 + +## Each DCMAC can support 2 QSFP56 interfaces +## select how many QSFP56 you want for each DCMAC, provided they are enabled + +## Setup number of QSFP56 interfaces for DCMAC0 +set DUAL_QSFP_DCMAC0 0 + +## Setup number of QSFP56 interfaces for DCMAC1 +set DUAL_QSFP_DCMAC1 0 diff --git a/submodules/v80-vitis-flow/sim/CMakeLists.txt b/linker/slashkit/resources/sim/CMakeLists.txt similarity index 100% rename from submodules/v80-vitis-flow/sim/CMakeLists.txt rename to linker/slashkit/resources/sim/CMakeLists.txt diff --git a/linker/slashkit/resources/sim/__init__.py b/linker/slashkit/resources/sim/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/submodules/v80-vitis-flow/sim/sim.cpp b/linker/slashkit/resources/sim/sim.cpp similarity index 90% rename from submodules/v80-vitis-flow/sim/sim.cpp rename to linker/slashkit/resources/sim/sim.cpp index 074da562..57edf418 100644 --- a/submodules/v80-vitis-flow/sim/sim.cpp +++ b/linker/slashkit/resources/sim/sim.cpp @@ -33,6 +33,7 @@ #include #include +#include "sim_exec_log.hpp" #include "xsi_dut.hpp" #include "xsi_loader.hpp" @@ -195,8 +196,9 @@ void mem_read_fsm(XSI_DUT* dut, std::queue>& addr, std::queuewrite(mem.arsize(), 3); // set size to 8B dut->write(mem.arlen(), nbeats - 1); // set len to nbeats - 1 dut->write(mem.arburst(), 1); // set burst to incr @@ -216,8 +218,9 @@ void mem_read_fsm(XSI_DUT* dut, std::queue>& addr, std::queuewrite(mem.arsize(), 3); // set size to 8B dut->write(mem.arlen(), nbeats - 1); // set len to nbeats - 1 dut->write(mem.arburst(), 1); // set burst to incr @@ -289,8 +292,9 @@ void mem_write_fsm(XSI_DUT* dut, std::queue>& addr, std::queuewrite(mem.awsize(), 3); // 64B width dut->write(mem.awlen(), nbeats - 1); dut->write(mem.awburst(), 1); // INCR @@ -309,8 +313,9 @@ void mem_write_fsm(XSI_DUT* dut, std::queue>& addr, std::queuewrite(mem.awsize(), 3); // 64B width dut->write(mem.awlen(), nbeats - 1); dut->write(mem.awburst(), 1); // INCR @@ -483,7 +488,8 @@ void fetchBuffer(ap_uint<64> addr, uint64_t len, std::vector& data) { memReadAddr.push(addr); memReadLen.push(len); } - std::cout << std::hex << "Reading from address: " << addr << " length: " << len << std::endl; + SIM_EXEC_LOG(std::cout << std::hex << "Reading from address: " << addr << " length: " << len + << std::endl); { std::unique_lock lock(mtx); cv_mem_read.wait(lock, [] { return !mem_read_busy; }); @@ -491,7 +497,8 @@ void fetchBuffer(ap_uint<64> addr, uint64_t len, std::vector& data) { while (data.size() < len && !memReadVal.empty()) { uint64_t temp = memReadVal.front(); memReadVal.pop(); - std::cout << std::showbase << std::hex << "Read value: " << temp << std::dec << std::endl; + SIM_EXEC_LOG(std::cout << std::showbase << std::hex << "Read value: " << temp << std::dec + << std::endl); for (int i = 0; i < 8 && data.size() < len; ++i) { data.push_back(static_cast((temp >> (i * 8)) & 0xFF)); } @@ -524,7 +531,7 @@ void zmq_ctx_setup_and_run() { while (!stop) { zmq::message_t request; - socket.recv(&request); + (void)socket.recv(request, zmq::recv_flags::none); std::string req_str(static_cast(request.data()), request.size()); Json::Value root; Json::Reader reader; @@ -535,14 +542,14 @@ void zmq_ctx_setup_and_run() { uint64_t addr = root["addr"].asUInt64(); uint64_t bufferSize = root["size"].asUInt64(); zmq::message_t data; - socket.recv(&data); + (void)socket.recv(data, zmq::recv_flags::none); void* buffer = new uint8_t[bufferSize]; std::memcpy(buffer, data.data(), bufferSize); std::vector vec(static_cast(buffer), static_cast(buffer) + bufferSize); socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); - std::cout << "Received data of size: " << std::hex << bufferSize - << " at address: " << addr << std::endl; + SIM_EXEC_LOG(std::cout << "Received data of size: " << std::hex << bufferSize + << " at address: " << addr << std::endl); { writeBuffer(addr, vec); } } else if (command == "fetch") { @@ -551,8 +558,8 @@ void zmq_ctx_setup_and_run() { if (type == "buffer") { uint64_t addr = root["addr"].asUInt64(); uint64_t bufferSize = root["size"].asUInt64(); // sent as no of bytes - std::cout << "Fetching buffer of size: " << std::dec << bufferSize - << " from address: " << std::hex << addr << std::endl; + SIM_EXEC_LOG(std::cout << "Fetching buffer of size: " << std::dec << bufferSize + << " from address: " << std::hex << addr << std::endl); std::vector vec; { fetchBuffer(addr, bufferSize, vec); } response = createJsonBuffer(vec.data(), vec.size()); @@ -576,8 +583,8 @@ void zmq_ctx_setup_and_run() { } else if (command == "reg") { uint64_t addr = root["addr"].asUInt64(); uint32_t val = root["val"].asUInt(); - std::cout << "Writing value: " << std::hex << val << " to address: " << addr - << std::endl; + SIM_EXEC_LOG(std::cout << "Writing value: " << std::hex << "0x" << val + << " to address: " << addr << std::endl); { std::unique_lock lock(mtx); cv_control_write.wait(lock, [] { return !control_write_busy; }); @@ -602,14 +609,14 @@ void zmq_ctx_setup_and_run() { int main() { std::string simengine_libname = "libxv_simulator_kernel.so"; std::string design_libname = "xsim.dir/top_wrapper_behav/xsimk.so"; - std::cout << "Sim Engine DLL: " << simengine_libname << std::endl; - std::cout << "Design DLL: " << design_libname << std::endl; + SIM_EXEC_LOG(std::cout << "Sim Engine DLL: " << simengine_libname << std::endl); + SIM_EXEC_LOG(std::cout << "Design DLL: " << design_libname << std::endl); XSI_DUT dut(design_libname, simengine_libname, "rst", true, "clk", 4, "test.wdb", true); - std::cout << "DUT initialized"; - std::cout << "Initial cycle count: " << dut.get_cycle_count() << std::endl; + SIM_EXEC_LOG(std::cout << "DUT initialized"); + SIM_EXEC_LOG(std::cout << "Initial cycle count: " << dut.get_cycle_count() << std::endl); dut.reset_design(); - std::cout << "Cycle count after reset: " << dut.get_cycle_count() << std::endl; + SIM_EXEC_LOG(std::cout << "Cycle count after reset: " << dut.get_cycle_count() << std::endl); signal(SIGINT, finish); std::thread worker(zmq_ctx_setup_and_run); diff --git a/submodules/v80-vitis-flow/sim/sim.hpp b/linker/slashkit/resources/sim/sim.hpp similarity index 100% rename from submodules/v80-vitis-flow/sim/sim.hpp rename to linker/slashkit/resources/sim/sim.hpp diff --git a/linker/slashkit/resources/sim/sim_exec_log.hpp b/linker/slashkit/resources/sim/sim_exec_log.hpp new file mode 100644 index 00000000..9edbe72d --- /dev/null +++ b/linker/slashkit/resources/sim/sim_exec_log.hpp @@ -0,0 +1,35 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + */ + +#ifndef SIM_EXEC_LOG_HPP +#define SIM_EXEC_LOG_HPP + +#include +#include + +inline bool sim_exec_verbose_enabled() { + static const bool enabled = []() { + const char* raw = std::getenv("SIM_EXEC_VERBOSE"); + if (raw == nullptr) return false; + std::string v(raw); + for (char& c : v) { + if (c >= 'A' && c <= 'Z') c = static_cast(c - 'A' + 'a'); + } + if (v.empty() || v == "0" || v == "false" || v == "off" || v == "no") { + return false; + } + return true; + }(); + return enabled; +} + +#define SIM_EXEC_LOG(stmt) \ + do { \ + if (sim_exec_verbose_enabled()) { \ + stmt; \ + } \ + } while (0) + +#endif // SIM_EXEC_LOG_HPP diff --git a/submodules/v80-vitis-flow/resources/sim_mem.v b/linker/slashkit/resources/sim/sim_mem.v similarity index 97% rename from submodules/v80-vitis-flow/resources/sim_mem.v rename to linker/slashkit/resources/sim/sim_mem.v index bb817090..8b3126b5 100644 --- a/submodules/v80-vitis-flow/resources/sim_mem.v +++ b/linker/slashkit/resources/sim/sim_mem.v @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -23,7 +23,7 @@ module sim_mem #( parameter MEM_WIDTH = 64, - parameter MEM_DEPTH_LOG = 24, + parameter MEM_DEPTH_LOG = 26, parameter READ_LATENCY = 50 )( @@ -102,4 +102,4 @@ endgenerate assign dout_a = delayline_a[READ_LATENCY-1]; assign dout_b = delayline_b[READ_LATENCY-1]; -endmodule \ No newline at end of file +endmodule diff --git a/submodules/v80-vitis-flow/sim/xsi_dut.cpp b/linker/slashkit/resources/sim/xsi_dut.cpp similarity index 88% rename from submodules/v80-vitis-flow/sim/xsi_dut.cpp rename to linker/slashkit/resources/sim/xsi_dut.cpp index d0b198cc..bf3dcaa8 100644 --- a/submodules/v80-vitis-flow/sim/xsi_dut.cpp +++ b/linker/slashkit/resources/sim/xsi_dut.cpp @@ -28,6 +28,8 @@ #include #include +#include "sim_exec_log.hpp" + using namespace std; XSI_DUT::XSI_DUT(const string& design_libname, const string& simkernel_libname, @@ -39,9 +41,9 @@ XSI_DUT::XSI_DUT(const string& design_libname, const string& simkernel_libname, info.logFileName = NULL; info.wdbFileName = const_cast(wdbName.c_str()); xsi.open(&info); - std::cout << "XSI opened" << std::endl; + SIM_EXEC_LOG(std::cout << "XSI opened" << std::endl); if (trace) { - std::cout << "Waveform enabled" << std::endl; + SIM_EXEC_LOG(std::cout << "Waveform enabled" << std::endl); xsi.trace_all(); } for (int i = 0; i < xsi.get_num_ports(); i++) { @@ -62,10 +64,11 @@ XSI_DUT::XSI_DUT(const string& design_libname, const string& simkernel_libname, clk = clock_name; clk_half_period = (unsigned int)(clock_period_ns * pow(10, -9) / xsi.get_time_precision() / 2); if (clk_half_period == 0) throw invalid_argument("Calculated half period is zero"); - std::cout << "Using " << rst << " as " << (rst_active_low ? "active-low" : "active-high") - << " reset" << endl; - std::cout << "Using " << clk << " as clock with half-period of " << clk_half_period - << " simulation steps" << endl; + SIM_EXEC_LOG(std::cout << "Using " << rst << " as " + << (rst_active_low ? "active-low" : "active-high") << " reset" + << endl); + SIM_EXEC_LOG(std::cout << "Using " << clk << " as clock with half-period of " + << clk_half_period << " simulation steps" << endl); cycle_count = 0; } @@ -88,8 +91,9 @@ uint64_t XSI_DUT::get_cycle_count() { return cycle_count; } void XSI_DUT::list_ports() { map::iterator it = port_map.begin(); while (it != port_map.end()) { - std::cout << it->first << " (ID: " << it->second.port_id << ", " << it->second.port_bits - << "b, " << (it->second.is_input ? "I)" : "O)") << endl; + SIM_EXEC_LOG(std::cout << it->first << " (ID: " << it->second.port_id << ", " + << it->second.port_bits << "b, " + << (it->second.is_input ? "I)" : "O)") << endl); it++; } } @@ -157,4 +161,4 @@ bool XSI_DUT::test(const string& port_name) { } unsigned int ret = read(port_name); return (ret == 1); -} \ No newline at end of file +} diff --git a/submodules/v80-vitis-flow/sim/xsi_dut.hpp b/linker/slashkit/resources/sim/xsi_dut.hpp similarity index 100% rename from submodules/v80-vitis-flow/sim/xsi_dut.hpp rename to linker/slashkit/resources/sim/xsi_dut.hpp diff --git a/submodules/v80-vitis-flow/sim/xsi_loader.cpp b/linker/slashkit/resources/sim/xsi_loader.cpp similarity index 98% rename from submodules/v80-vitis-flow/sim/xsi_loader.cpp rename to linker/slashkit/resources/sim/xsi_loader.cpp index 4a3c27f5..8a983c6a 100644 --- a/submodules/v80-vitis-flow/sim/xsi_loader.cpp +++ b/linker/slashkit/resources/sim/xsi_loader.cpp @@ -23,6 +23,8 @@ #include #include +#include "sim_exec_log.hpp" + using namespace Xsi; Loader::Loader(const std::string& design_libname, const std::string& simkernel_libname) @@ -50,7 +52,7 @@ Loader::~Loader() { close(); } bool Loader::isopen() const { return (_design_handle != NULL); } void Loader::open(p_xsi_setup_info setup_info) { - std::cout << "Before open\n"; + SIM_EXEC_LOG(std::cout << "Before open\n"); _design_handle = _xsi_open(setup_info); } diff --git a/submodules/v80-vitis-flow/sim/xsi_loader.hpp b/linker/slashkit/resources/sim/xsi_loader.hpp similarity index 100% rename from submodules/v80-vitis-flow/sim/xsi_loader.hpp rename to linker/slashkit/resources/sim/xsi_loader.hpp diff --git a/linker/slashkit/resources/templates/__init__.py b/linker/slashkit/resources/templates/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/slashkit/resources/templates/service_layer.tcl b/linker/slashkit/resources/templates/service_layer.tcl new file mode 100644 index 00000000..ba8afaf7 --- /dev/null +++ b/linker/slashkit/resources/templates/service_layer.tcl @@ -0,0 +1,1306 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +delete_bd_objs [get_bd_cells ] +delete_bd_objs [get_bd_intf_nets] +delete_bd_objs [get_bd_nets] +update_compile_order -fileset sources_1 +{% raw %} +set_property APERTURES {{0xE000_0000 256M}} [get_bd_intf_ports M_QDMA_SLV_BRIDGE] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports M_VIRT_0] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports M_VIRT_1] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports M_VIRT_2] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports M_VIRT_3] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_0] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_1] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_2] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_3] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_4] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_5] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_6] +set_property APERTURES {{0x600_0000_0000 32G}} [get_bd_intf_ports SL2NOC_7] +set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_ports S_AXILITE_INI] +set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports S_QDMA_SLV_BRIDGE] +set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports S_VIRT_00] +set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports S_VIRT_01] +set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports S_VIRT_02] +set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports S_VIRT_03] +{% endraw %} + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x203_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI:S_QDMA_SLV_BRIDGE:M_QDMA_SLV_BRIDGE:S_VIRT_3:S_VIRT_2:S_VIRT_1:S_VIRT_0} \ + ] [get_bd_pins /axi_noc_0/aclk0] + set_property APERTURES {{0x203_0000_0000 128M}} [get_bd_intf_ports S_AXILITE_INI] + {% endraw %} + + # Create instance: dummy_noc_0, and set properties + set dummy_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_0/aclk0] + + # Create instance: dummy_noc_1, and set properties + set dummy_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_1/aclk0] + + # Create instance: dummy_noc_2, and set properties + set dummy_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_2/aclk0] + + # Create instance: dummy_noc_3, and set properties + set dummy_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_3/aclk0] + + # Create instance: dummy_noc_4, and set properties + set dummy_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_4/aclk0] + + # Create instance: dummy_noc_5, and set properties + set dummy_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_5/aclk0] + + # Create instance: dummy_noc_6, and set properties + set dummy_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_6/aclk0] + + # Create instance: dummy_noc_7, and set properties + set dummy_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dummy_noc_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dummy_noc_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dummy_noc_7/aclk0] + + # Create instance: dummy_noc_m_0, and set properties + set dummy_noc_m_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_0/aclk0] + + # Create instance: dummy_noc_m_1, and set properties + set dummy_noc_m_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_1/aclk0] + + # Create instance: dummy_noc_m_2, and set properties + set dummy_noc_m_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_2/aclk0] + + # Create instance: dummy_noc_m_3, and set properties + set dummy_noc_m_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_3/aclk0] + + # Create instance: dummy_noc_m_4, and set properties + set dummy_noc_m_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_4 + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_4/aclk0] + + # Create instance: dummy_noc_m_5, and set properties + set dummy_noc_m_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_5/aclk0] + + # Create instance: dummy_noc_m_6, and set properties + set dummy_noc_m_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_6/aclk0] + + # Create instance: dummy_noc_m_7, and set properties + set dummy_noc_m_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dummy_noc_m_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dummy_noc_m_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dummy_noc_m_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dummy_noc_m_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dummy_noc_m_7/aclk0] + +# Create instance: sl2noc_0, and set properties + set sl2noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_0 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_0/aclk0] + + # Create instance: sl2noc_1, and set properties + set sl2noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_1 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_1/aclk0] + + # Create instance: sl2noc_2, and set properties + set sl2noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_2 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_2/aclk0] + + # Create instance: sl2noc_3, and set properties + set sl2noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_3 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_3/aclk0] + + # Create instance: sl2noc_4, and set properties + set sl2noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_4 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_4/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_4/aclk0] + + # Create instance: sl2noc_5, and set properties + set sl2noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_5 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_5/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_5/aclk0] + + # Create instance: sl2noc_6, and set properties + set sl2noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_6 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_6/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_6/aclk0] + + # Create instance: sl2noc_7, and set properties + set sl2noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc sl2noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $sl2noc_7 + + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /sl2noc_7/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /sl2noc_7/aclk0] + + + # Create instance: noc_virt_0, and set properties + set noc_virt_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_0/aclk0] + + # Create instance: noc_virt_1, and set properties + set noc_virt_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_1 + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_1/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_1/aclk0] + + # Create instance: noc_virt_2, and set properties + set noc_virt_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_2 + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_2/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_2/aclk0] + + # Create instance: noc_virt_3, and set properties + set noc_virt_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_3 + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_3/aclk0] + + # Create instance: noc_virt_4, and set properties + set noc_virt_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $noc_virt_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_4/M00_INI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_3/aclk0] + + # Create instance: axi_noc_1, and set properties + set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_1 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_1 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_1/M00_AXI] +{% endraw %} + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_1/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_1/aclk0] + + # Create instance: axi4_full_passthrough_0, and set properties + set axi4_full_passthrough_0 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_0 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_0 + + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + + # Create instance: axi_register_slice_1, and set properties + set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ] + + # Create instance: axi_noc_2, and set properties + set axi_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_2 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_2 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_2/M00_AXI] +{% endraw %} + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_2/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_2/aclk0] + + # Create instance: axi_noc_3, and set properties + set axi_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_3 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_3 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_3/M00_AXI] +{% endraw %} + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_3/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_3/aclk0] + + # Create instance: axi_noc_4, and set properties + set axi_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_4 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_4 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_4/M00_AXI] +{% endraw %} + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_4/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_4/aclk0] + + # Create instance: axi_noc_5, and set properties + set axi_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_5 ] + set_property -dict [list \ + CONFIG.MI_SIDEBAND_PINS {} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_5 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x208_0000_0000 32G}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_5/M00_AXI] +{% endraw %} + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_5/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_5/aclk0] + + # Create instance: axi4_full_passthrough_1, and set properties + set axi4_full_passthrough_1 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_1 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_1 + + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + + # Create instance: axi_register_slice_3, and set properties + set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ] + + # Create instance: axi4_full_passthrough_2, and set properties + set axi4_full_passthrough_2 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_2 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_2 + + + # Create instance: axi_register_slice_4, and set properties + set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ] + + # Create instance: axi_register_slice_5, and set properties + set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ] + + # Create instance: axi4_full_passthrough_3, and set properties + set axi4_full_passthrough_3 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_3 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_3 + + + # Create instance: axi_register_slice_6, and set properties + set axi_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_6 ] + + # Create instance: axi_register_slice_7, and set properties + set axi_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_7 ] + + # Create instance: axi4_full_passthrough_4, and set properties + set axi4_full_passthrough_4 [ create_bd_cell -type ip -vlnv user.org:user:axi4_full_passthrough:1.0 axi4_full_passthrough_4 ] + set_property CONFIG.AXI_DATA_WIDTH {128} $axi4_full_passthrough_4 + + + # Create instance: axi_register_slice_8, and set properties + set axi_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_8 ] + + # Create instance: axi_register_slice_9, and set properties + set axi_register_slice_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_9 ] + + # Create instance: c_shift_ram_0, and set properties + set c_shift_ram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 c_shift_ram_0 ] + set_property -dict [list \ + CONFIG.Depth {1} \ + CONFIG.Width {1} \ + ] $c_shift_ram_0 + + + # Create instance: ilreduced_logic_0, and set properties + set ilreduced_logic_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic:1.0 ilreduced_logic_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $ilreduced_logic_0 + + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {BUFG_FABRIC} $util_ds_buf_0 + + connect_bd_net -net util_ds_buf_0_BUFG_FABRIC_O [get_bd_pins util_ds_buf_0/BUFG_FABRIC_O] \ + [get_bd_pins ilreduced_logic_0/Op1] + + connect_bd_net -net arstn_1 [get_bd_ports arstn] \ + [get_bd_pins c_shift_ram_0/D] + + connect_bd_net -net c_shift_ram_0_Q [get_bd_pins c_shift_ram_0/Q] \ + [get_bd_pins util_ds_buf_0/BUFG_FABRIC_I] + + + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_0/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_0/S00_AXI] + + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_1/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_1/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_2/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_2/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_3/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_3/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_4/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_4/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_5/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_5/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_6/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_6/S00_AXI] + set_property -dict [list CONFIG.INI_STRATEGY {driver}] [get_bd_intf_pins /sl2noc_7/M00_INI] + set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}}] [get_bd_intf_pins /sl2noc_7/S00_AXI] + + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins dummy_noc_m_0/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins dummy_noc_m_1/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins dummy_noc_m_2/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins dummy_noc_m_3/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dummy_noc_m_4/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dummy_noc_m_5/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dummy_noc_m_6/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dummy_noc_m_7/M00_INIS] [get_bd_intf_ports M_DCMAC_INIS7] + connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins dummy_noc_0/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS0] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins dummy_noc_1/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS1] + connect_bd_intf_net -intf_net Conn11 [get_bd_intf_pins dummy_noc_2/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS2] + connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins dummy_noc_3/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS3] + connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins dummy_noc_4/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS4] + connect_bd_intf_net -intf_net Conn14 [get_bd_intf_pins dummy_noc_5/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS5] + connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins dummy_noc_6/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS6] + connect_bd_intf_net -intf_net Conn16 [get_bd_intf_pins dummy_noc_7/S00_INIS] [get_bd_intf_ports S_DCMAC_INIS7] + + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + + # Slave bridge connections + connect_bd_intf_net -intf_net S_QDMA_SLV_BRIDGE_1 [get_bd_intf_ports S_QDMA_SLV_BRIDGE] [get_bd_intf_pins axi_noc_5/S00_INI] + connect_bd_intf_net -intf_net axi_noc_5_M00_AXI [get_bd_intf_pins axi_register_slice_8/S_AXI] [get_bd_intf_pins axi_noc_5/M00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI3 [get_bd_intf_pins axi_register_slice_8/M_AXI] [get_bd_intf_pins axi4_full_passthrough_4/s_axi] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi3 [get_bd_intf_pins axi4_full_passthrough_4/m_axi] [get_bd_intf_pins axi_register_slice_9/S_AXI] + connect_bd_intf_net -intf_net axi_register_slice_9_M_AXI [get_bd_intf_pins axi_register_slice_9/M_AXI] [get_bd_intf_pins noc_virt_4/S00_AXI] + connect_bd_intf_net -intf_net noc_virt_5_M00_INI [get_bd_intf_ports M_QDMA_SLV_BRIDGE] [get_bd_intf_pins noc_virt_4/M00_INI] + + # Virtual NOC connections + connect_bd_intf_net -intf_net S_VIRT_00_1 [get_bd_intf_ports S_VIRT_00] [get_bd_intf_pins axi_noc_1/S00_INI] + connect_bd_intf_net -intf_net axi_noc_1_M00_AXI [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_noc_1/M00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_register_slice_0/M_AXI] [get_bd_intf_pins axi4_full_passthrough_0/s_axi] + connect_bd_intf_net -intf_net axi4_full_passthrough_0_m_axi [get_bd_intf_pins axi_register_slice_1/S_AXI] [get_bd_intf_pins axi4_full_passthrough_0/m_axi] + connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_register_slice_1/M_AXI] [get_bd_intf_pins noc_virt_0/S00_AXI] + connect_bd_intf_net -intf_net axi_noc_1_M00_INI [get_bd_intf_ports M_VIRT_0] [get_bd_intf_pins noc_virt_0/M00_INI] + + connect_bd_intf_net -intf_net S_VIRT_01_1 [get_bd_intf_ports S_VIRT_01] [get_bd_intf_pins axi_noc_2/S00_INI] + connect_bd_intf_net -intf_net axi_noc_2_M00_AXI [get_bd_intf_pins axi_register_slice_2/S_AXI] [get_bd_intf_pins axi_noc_2/M00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_register_slice_2/M_AXI] [get_bd_intf_pins axi4_full_passthrough_1/s_axi] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi [get_bd_intf_pins axi4_full_passthrough_1/m_axi] [get_bd_intf_pins axi_register_slice_3/S_AXI] + connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins noc_virt_1/S00_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI] + connect_bd_intf_net -intf_net axi_noc_2_M00_INI [get_bd_intf_ports M_VIRT_1] [get_bd_intf_pins noc_virt_1/M00_INI] + + connect_bd_intf_net -intf_net S_VIRT_02_1 [get_bd_intf_ports S_VIRT_02] [get_bd_intf_pins axi_noc_3/S00_INI] + connect_bd_intf_net -intf_net axi_noc_3_M00_AXI [get_bd_intf_pins axi_register_slice_4/S_AXI] [get_bd_intf_pins axi_noc_3/M00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI1 [get_bd_intf_pins axi_register_slice_4/M_AXI] [get_bd_intf_pins axi4_full_passthrough_2/s_axi] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi1 [get_bd_intf_pins axi4_full_passthrough_2/m_axi] [get_bd_intf_pins axi_register_slice_5/S_AXI] + connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_pins axi_register_slice_5/M_AXI] [get_bd_intf_pins noc_virt_2/S00_AXI] + connect_bd_intf_net -intf_net axi_noc_3_M00_INI [get_bd_intf_ports M_VIRT_2] [get_bd_intf_pins noc_virt_2/M00_INI] + + + connect_bd_intf_net -intf_net S_VIRT_03_1 [get_bd_intf_ports S_VIRT_03] [get_bd_intf_pins axi_noc_4/S00_INI] + connect_bd_intf_net -intf_net axi_noc_4_M00_AXI [get_bd_intf_pins axi_register_slice_6/S_AXI] [get_bd_intf_pins axi_noc_4/M00_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI2 [get_bd_intf_pins axi_register_slice_6/M_AXI] [get_bd_intf_pins axi4_full_passthrough_3/s_axi] + connect_bd_intf_net -intf_net axi4_full_passthrough_1_m_axi2 [get_bd_intf_pins axi4_full_passthrough_3/m_axi] [get_bd_intf_pins axi_register_slice_7/S_AXI] + connect_bd_intf_net -intf_net axi_register_slice_7_M_AXI [get_bd_intf_pins axi_register_slice_7/M_AXI] [get_bd_intf_pins noc_virt_3/S00_AXI] + connect_bd_intf_net -intf_net axi_noc_4_M00_INI [get_bd_intf_ports M_VIRT_3] [get_bd_intf_pins noc_virt_3/M00_INI] + + + + + connect_bd_intf_net -intf_net sl2noc_0_M00_INI [get_bd_intf_ports SL2NOC_0] [get_bd_intf_pins sl2noc_0/M00_INI] + connect_bd_intf_net -intf_net sl2noc_1_M00_INI [get_bd_intf_ports SL2NOC_1] [get_bd_intf_pins sl2noc_1/M00_INI] + connect_bd_intf_net -intf_net sl2noc_2_M00_INI [get_bd_intf_ports SL2NOC_2] [get_bd_intf_pins sl2noc_2/M00_INI] + connect_bd_intf_net -intf_net sl2noc_3_M00_INI [get_bd_intf_ports SL2NOC_3] [get_bd_intf_pins sl2noc_3/M00_INI] + connect_bd_intf_net -intf_net sl2noc_4_M00_INI [get_bd_intf_ports SL2NOC_4] [get_bd_intf_pins sl2noc_4/M00_INI] + connect_bd_intf_net -intf_net sl2noc_5_M00_INI [get_bd_intf_ports SL2NOC_5] [get_bd_intf_pins sl2noc_5/M00_INI] + connect_bd_intf_net -intf_net sl2noc_6_M00_INI [get_bd_intf_ports SL2NOC_6] [get_bd_intf_pins sl2noc_6/M00_INI] + connect_bd_intf_net -intf_net sl2noc_7_M00_INI [get_bd_intf_ports SL2NOC_7] [get_bd_intf_pins sl2noc_7/M00_INI] + + + connect_bd_net -net service_clk_1 [get_bd_pins service_clk] \ + [get_bd_pins dummy_noc_0/aclk0] \ + [get_bd_pins dummy_noc_1/aclk0] \ + [get_bd_pins dummy_noc_2/aclk0] \ + [get_bd_pins dummy_noc_3/aclk0] \ + [get_bd_pins dummy_noc_4/aclk0] \ + [get_bd_pins dummy_noc_5/aclk0] \ + [get_bd_pins dummy_noc_6/aclk0] \ + [get_bd_pins dummy_noc_7/aclk0] \ + [get_bd_pins dummy_noc_m_0/aclk0] \ + [get_bd_pins dummy_noc_m_1/aclk0] \ + [get_bd_pins dummy_noc_m_2/aclk0] \ + [get_bd_pins dummy_noc_m_3/aclk0] \ + [get_bd_pins dummy_noc_m_4/aclk0] \ + [get_bd_pins dummy_noc_m_5/aclk0] \ + [get_bd_pins dummy_noc_m_6/aclk0] \ + [get_bd_pins dummy_noc_m_7/aclk0] \ + [get_bd_pins sl2noc_0/aclk0] \ + [get_bd_pins sl2noc_1/aclk0] \ + [get_bd_pins sl2noc_2/aclk0] \ + [get_bd_pins sl2noc_3/aclk0] \ + [get_bd_pins sl2noc_4/aclk0] \ + [get_bd_pins sl2noc_5/aclk0] \ + [get_bd_pins sl2noc_6/aclk0] \ + [get_bd_pins sl2noc_7/aclk0] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins noc_virt_0/aclk0] \ + [get_bd_pins axi_noc_1/aclk0] \ + [get_bd_pins axi4_full_passthrough_0/aclk] \ + [get_bd_pins axi_register_slice_0/aclk] \ + [get_bd_pins axi_register_slice_1/aclk] \ + [get_bd_pins axi_noc_5/aclk0] \ + [get_bd_pins axi_noc_4/aclk0] \ + [get_bd_pins axi_noc_3/aclk0] \ + [get_bd_pins axi_noc_2/aclk0] \ + [get_bd_pins axi_register_slice_3/aclk] \ + [get_bd_pins axi4_full_passthrough_1/aclk] \ + [get_bd_pins axi_register_slice_2/aclk] \ + [get_bd_pins noc_virt_1/aclk0] \ + [get_bd_pins axi4_full_passthrough_2/aclk] \ + [get_bd_pins axi_register_slice_5/aclk] \ + [get_bd_pins axi_register_slice_4/aclk] \ + [get_bd_pins axi4_full_passthrough_3/aclk] \ + [get_bd_pins axi_register_slice_7/aclk] \ + [get_bd_pins axi_register_slice_6/aclk] \ + [get_bd_pins axi4_full_passthrough_4/aclk] \ + [get_bd_pins axi_register_slice_9/aclk] \ + [get_bd_pins axi_register_slice_8/aclk] \ + [get_bd_pins noc_virt_3/aclk0] \ + [get_bd_pins noc_virt_2/aclk0] \ + [get_bd_pins noc_virt_4/aclk0] \ + [get_bd_pins c_shift_ram_0/CLK] + + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins ilreduced_logic_0/Res] \ + [get_bd_pins axi4_full_passthrough_0/aresetn] \ + [get_bd_pins axi_register_slice_0/aresetn] \ + [get_bd_pins axi_register_slice_1/aresetn] \ + [get_bd_pins axi_register_slice_3/aresetn] \ + [get_bd_pins axi4_full_passthrough_1/aresetn] \ + [get_bd_pins axi_register_slice_2/aresetn] \ + [get_bd_pins axi_register_slice_5/aresetn] \ + [get_bd_pins axi4_full_passthrough_2/aresetn] \ + [get_bd_pins axi_register_slice_4/aresetn] \ + [get_bd_pins axi_register_slice_7/aresetn] \ + [get_bd_pins axi4_full_passthrough_3/aresetn] \ + [get_bd_pins axi_register_slice_6/aresetn] \ + [get_bd_pins axi_register_slice_9/aresetn] \ + [get_bd_pins axi4_full_passthrough_4/aresetn] \ + [get_bd_pins axi_register_slice_8/aresetn] + + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] \ + [get_bd_pins dummy_noc_1/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_2/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_3/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_5/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_6/M00_AXIS_tready] \ + [get_bd_pins dummy_noc_7/M00_AXIS_tready] + + +proc add_dcmac_inst {} { + + set DCMAC0_ENABLED 1 + set DCMAC1_ENABLED 1 + + ## Each DCMAC can support 2 QSFP56 interfaces + ## select how many QSFP56 you want for each DCMAC, provided they are enabled + + ## Setup number of QSFP56 interfaces for DCMAC0 + set DUAL_QSFP_DCMAC0 0 + + ## Setup number of QSFP56 interfaces for DCMAC1 + set DUAL_QSFP_DCMAC1 0 + + # Create network hierarchy + if { ${DCMAC0_ENABLED} == "1" } { + create_qsfp_hierarchy 0 ${DUAL_QSFP_DCMAC0} + } + if { ${DCMAC1_ENABLED} == "1" } { + create_qsfp_hierarchy 1 ${DUAL_QSFP_DCMAC1} + } +} +# ===== Service Layer (generated) ===== +# create_service_layer "" + +# Absolute paths (normalized) +set ::slash_dcmac_tcl [file normalize "{{ dcmac_tcl }}"] +set ::slash_dcmac_hdl [file normalize "{{ dcmac_hdl_dir }}"] + +# Source the DCMAC Tcl helpers +source $::slash_dcmac_tcl + +{% for vf in dcmac_hdl_files %} +import_files -fileset sources_1 -norecurse [file normalize "{{ vf }}"] +{% endfor %} + +# --- Drive DCMAC creation based on config --- +{% if needs_dcmac %} + set DCMAC0_ENABLED {{ dc_enable_0 }} + set DCMAC1_ENABLED {{ dc_enable_1 }} + set DUAL_QSFP_DCMAC0 {{ dual_qsfp_0 }} + set DUAL_QSFP_DCMAC1 {{ dual_qsfp_1 }} + + # Calls proc add_dcmac_inst which expects the above variables + add_dcmac_inst +{% else %} + set DCMAC0_ENABLED 0 + set DCMAC1_ENABLED 0 + set DUAL_QSFP_DCMAC0 0 + set DUAL_QSFP_DCMAC1 0 + # Ethernet disabled; no DCMAC hierarchy created. +{% endif %} + +# === AXI-Lite SmartConnect for service_layer control === +# === AXI-Lite SmartConnect for service_layer control === +{% if sl_have_xbar %} + current_bd_design service_layer_user + + # Create SmartConnect inside the service_layer BD with a local name + create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 + set_property -dict [list \ + CONFIG.NUM_CLKS {{ "{" ~ sl_num_clks ~ "}" }} \ + CONFIG.NUM_MI {{ "{" ~ sl_num_mi ~ "}" }} \ + CONFIG.NUM_SI {{ "{" ~ sl_num_si ~ "}" }} \ + ] [get_bd_cells smartconnect_0] + # Rename for convenience + set_property name {{ sl_smartconnect_name }} [get_bd_cells smartconnect_0] + + # Clocks & reset (design pins to SC pins) + connect_bd_net [get_bd_pins {{ sl_clk0 }}] [get_bd_pins {{ sl_smartconnect_name }}/aclk] + connect_bd_net [get_bd_pins {{ sl_rstn }}] [get_bd_pins {{ sl_smartconnect_name }}/aresetn] + + # SI: service_layer design's S_AXILITE -> SmartConnect S00_AXI + connect_bd_intf_net \ + [get_bd_intf_pins {{ sl_si_src_if }}] \ + [get_bd_intf_pins {{ sl_smartconnect_name }}/S00_AXI] + + # MI: fan-out to DCMAC hierarchies' s_axi + {% for tgt in sl_mi_targets %} + {% set idx = "%02d"|format(loop.index0) %} + connect_bd_intf_net \ + [get_bd_intf_pins {{ sl_smartconnect_name }}/M{{ idx }}_AXI] \ + [get_bd_intf_pins {{ tgt }}] + {% endfor %} + + # Tie QSFP block clocks/resets + {% for q in sl_qsfp_blocks %} + connect_bd_net [get_bd_pins {{ sl_clk0 }}] [get_bd_pins {{ q }}/ap_clk] + connect_bd_net [get_bd_pins {{ sl_rstn }}] [get_bd_pins {{ q }}/ap_rst_n] + {% endfor %} + +{% else %} + # No AXI-Lite users: create a dummy SmartConnect with clocks+reset, + # connect S_AXILITE -> S00_AXI, but leave the single M00_AXI unconnected. + # current_bd_design service_layer_user + + # create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 + # create_bd_cell -type ip -vlnv xilinx.com:hls:hbm_bandwidth:1.0 hbm_bandwidth_0 + # set_property -dict [list \ + # CONFIG.NUM_CLKS {1} \ + # CONFIG.NUM_MI {1} \ + # CONFIG.NUM_SI {1} \ + # ] [get_bd_cells smartconnect_0] + # set_property name {{ sl_smartconnect_name }} [get_bd_cells smartconnect_0] + + # # Clocks & reset + # connect_bd_net [get_bd_pins service_clk] [get_bd_pins {{ sl_smartconnect_name }}/aclk] + # connect_bd_net [get_bd_pins arstn] [get_bd_pins {{ sl_smartconnect_name }}/aresetn] + + # # SI: service_layer design's S_AXILITE -> SmartConnect S00_AXI + # connect_bd_intf_net \ + # [get_bd_intf_pins axi_noc_0/M00_AXI] \ + # [get_bd_intf_pins {{ sl_smartconnect_name }}/S00_AXI] + + # # M00_AXI connected to dummy HBM bandwidth core + # connect_bd_intf_net [get_bd_intf_pins hbm_bandwidth_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M00_AXI] + # connect_bd_net [get_bd_ports service_clk] [get_bd_pins hbm_bandwidth_0/ap_clk] + # connect_bd_net [get_bd_ports arstn] [get_bd_pins hbm_bandwidth_0/ap_rst_n] + # connect_bd_intf_net [get_bd_intf_pins hbm_bandwidth_0/m_axi_gmem0] [get_bd_intf_pins sl2noc_0/S00_AXI] + +{% endif %} + + +# === QSFP <-> NoC AXIS links (inside service_layer) === +{% if sl_axis_noc_links %} + # Enter service_layer hierarchy + set __oldCurInst [current_bd_instance .] + current_bd_instance [get_bd_cells /service_layer] + + {% for L in sl_axis_noc_links %} + # Link: {{ L.src_pin }} -> {{ L.dst_pin }} + set __src [get_bd_intf_pins {{ L.src_pin }}] + set __dst [get_bd_intf_pins {{ L.dst_pin }}] + if { $__src eq "" } { + error "AXIS source pin '{{ L.src_pin }}' not found in service_layer." + } + if { $__dst eq "" } { + error "AXIS dest pin '{{ L.dst_pin }}' not found in service_layer." + } + connect_bd_intf_net $__src $__dst + {% endfor %} + + # Restore previous instance + current_bd_instance $__oldCurInst + assign_bd_address -offset 0x020302040400 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040400 -range 0x00000100 -with_name SEG_axi_gpio_datapath_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_datapath/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040000 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040000 -range 0x00000100 -with_name SEG_axi_gpio_gt_control_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_gt_control/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040200 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040200 -range 0x00000100 -with_name SEG_axi_gpio_monitor_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_monitor/S_AXI/Reg] -force + assign_bd_address -offset 0x020302040600 -range 0x00000100 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x020303040600 -range 0x00000100 -with_name SEG_axi_gpio_reset_txrx_Reg_1 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/control_intf/axi_gpio_reset_txrx/S_AXI/Reg] -force + assign_bd_address -offset 0x020302000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_0_n_1/DCMAC_subsys/dcmac_0_core/s_axi/Reg] -force + assign_bd_address -offset 0x020303000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces S_AXILITE_INI] [get_bd_addr_segs qsfp_2_n_3/DCMAC_subsys/dcmac_1_core/s_axi/Reg] -force + +{% else %} + # No QSFP <-> NoC links required +{% endif %} + +# @TODO: change this when virtualization core is available. +# === Temporary VIRT wiring: S_VIRT_x -> sl2noc_virt_x/S00_AXI === +# current_bd_design service_layer_user +# for {set i 0} {$i < 4} {incr i} { +# set sv [get_bd_intf_pins S_VIRT_$i] +# set noc_in [get_bd_intf_pins sl2noc_virt_$i/S00_AXI] + +# if { $sv eq "" } { +# puts "Info: service_layer: S_VIRT_$i not present; skipping." +# continue +# } +# if { $noc_in eq "" } { +# puts "Info: service_layer: sl2noc_virt_$i/S00_AXI not present; skipping." +# continue +# } +# connect_bd_intf_net $sv $noc_in +# } + +assign_bd_address -offset 0xE0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces S_QDMA_SLV_BRIDGE] [get_bd_addr_segs M_QDMA_SLV_BRIDGE/Reg] -force +assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces S_VIRT_00] [get_bd_addr_segs M_VIRT_0/Reg] -force +assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces S_VIRT_01] [get_bd_addr_segs M_VIRT_1/Reg] -force +assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces S_VIRT_02] [get_bd_addr_segs M_VIRT_2/Reg] -force +assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces S_VIRT_03] [get_bd_addr_segs M_VIRT_3/Reg] -force +assign_bd_address +validate_bd_design +save_bd_design +# current_bd_design [get_bd_designs top] +# validate_bd_design +# save_bd_design + +# ===== End Service Layer ===== diff --git a/linker/slashkit/resources/templates/sim_prj.tcl b/linker/slashkit/resources/templates/sim_prj.tcl new file mode 100644 index 00000000..f7e918c1 --- /dev/null +++ b/linker/slashkit/resources/templates/sim_prj.tcl @@ -0,0 +1,227 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set sim_root "{{ sim_root }}" +set sim_prj_dir "{{ sim_prj_dir }}" +set ip_repo_path "{{ ip_repo_path }}" +set sim_mem_path "{{ sim_mem_path }}" +set bd_name "{{ bd_name }}" +set part "{{ part }}" + +create_project sim_prj "${sim_prj_dir}" -part ${part} -force + +add_files -norecurse ${sim_mem_path} +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 + +set_property ip_repo_paths "${ip_repo_path}" [current_project] +update_ip_catalog +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 + +# --- Preprocess checkpoint-backed kernels into funcsim Verilog (per instance) --- +{% if sim_checkpoint_netlists %} +set slash_ckpt_vlog_files [list] +file mkdir [file join ${sim_root} checkpoint_funcsim] +{% for ck in sim_checkpoint_netlists %} +if {![file exists "{{ ck.dcp_path }}"]} { + error "Simulation checkpoint DCP not found for instance {{ ck.inst }}: {{ ck.dcp_path }}" +} +open_checkpoint "{{ ck.dcp_path }}" +write_verilog -force -mode funcsim -rename_top {{ ck.rename_top }} -prefix {{ ck.rename_prefix }} "{{ ck.funcsim_v_path }}" +close_design +set ckpt_funcsim_file "{{ ck.funcsim_v_path }}" +lappend slash_ckpt_vlog_files ${ckpt_funcsim_file} +add_files -fileset sim_1 -norecurse ${ckpt_funcsim_file} +set ckpt_funcsim_obj [get_files -all ${ckpt_funcsim_file}] +if {[llength ${ckpt_funcsim_obj}] > 0} { + # Ensure checkpoint-derived netlists participate in simulation only. + catch { set_property USED_IN_SIMULATION true ${ckpt_funcsim_obj} } + catch { set_property USED_IN_SYNTHESIS false ${ckpt_funcsim_obj} } + catch { set_property USED_IN_IMPLEMENTATION false ${ckpt_funcsim_obj} } + catch { set_property IS_USER_DISABLED false ${ckpt_funcsim_obj} } + catch { set_property IS_ENABLED true ${ckpt_funcsim_obj} } +} +{% endfor %} +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 +{% endif %} +create_bd_design ${bd_name} +current_bd_design ${bd_name} + +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_ctrl +set_property -dict [list CONFIG.ADDR_WIDTH 64] [get_bd_intf_ports s_axi_ctrl] +set_property -dict [list CONFIG.HAS_BURST 0 CONFIG.HAS_CACHE 0 CONFIG.HAS_LOCK 0 CONFIG.HAS_PROT 0 CONFIG.HAS_QOS 0 CONFIG.HAS_REGION 0] [get_bd_intf_ports s_axi_ctrl] + +create_bd_port -dir I -type clk clk +create_bd_port -dir I -type rst rst +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 mem +set_property -dict [list CONFIG.ADDR_WIDTH 64] [get_bd_intf_ports mem] +set_property -dict [list CONFIG.READ_WRITE_MODE READ_WRITE] [get_bd_intf_ports mem] +set_property -dict [list CONFIG.DATA_WIDTH 64] [get_bd_intf_ports mem] + +create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 bram_ctrl +set_property -dict [list CONFIG.SINGLE_PORT_BRAM {0} CONFIG.DATA_WIDTH {64} CONFIG.ECC_TYPE {0} CONFIG.READ_LATENCY {50}] [get_bd_cells bram_ctrl] + +create_bd_cell -type module -reference sim_mem sim_mem_0 + +connect_bd_intf_net [get_bd_intf_pins bram_ctrl/BRAM_PORTA] [get_bd_intf_pins sim_mem_0/MEM_PORT_A] +connect_bd_intf_net [get_bd_intf_pins bram_ctrl/BRAM_PORTB] [get_bd_intf_pins sim_mem_0/MEM_PORT_B] + +create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 bram_ctrl_ddr +set_property -dict [list CONFIG.SINGLE_PORT_BRAM {0} CONFIG.DATA_WIDTH {64} CONFIG.ECC_TYPE {0} CONFIG.READ_LATENCY {50}] [get_bd_cells bram_ctrl_ddr] + +create_bd_cell -type module -reference sim_mem sim_mem_1 + +connect_bd_intf_net [get_bd_intf_pins bram_ctrl_ddr/BRAM_PORTA] [get_bd_intf_pins sim_mem_1/MEM_PORT_A] +connect_bd_intf_net [get_bd_intf_pins bram_ctrl_ddr/BRAM_PORTB] [get_bd_intf_pins sim_mem_1/MEM_PORT_B] + +# --- Kernel IPs --- +{% for k in kernels %} +# set custom kernel: {{ k.vlnv }} +set {{ k.name }} [ create_bd_cell -type ip -vlnv {{ k.vlnv }} {{ k.name }} ] +{% endfor %} + +# --- AXI-Lite SmartConnect fanout tree --- +{% for sc in axilite_scs %} +set {{ sc.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect {{ sc.name }} ] +set_property -dict [list \ + CONFIG.NUM_SI {1} \ + CONFIG.NUM_MI {{ "{" ~ sc.num_mi ~ "}" }} \ +] [get_bd_cells {{ sc.name }}] +connect_bd_net [get_bd_ports clk] [get_bd_pins {{ sc.name }}/aclk] +connect_bd_net [get_bd_ports rst] [get_bd_pins {{ sc.name }}/aresetn] +{% endfor %} + +{% for sc in axilite_scs %} +{% if sc.si_from.type == "bd_port" %} +connect_bd_intf_net [get_bd_intf_ports {{ sc.si_from.name }}] [get_bd_intf_pins {{ sc.name }}/S00_AXI] +{% else %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.si_from.prev }}/{{ sc.si_from.prev_slot_name }}] [get_bd_intf_pins {{ sc.name }}/S00_AXI] +{% endif %} +{% for mi in sc.mi %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.name }}/{{ mi.slot_name }}] [get_bd_intf_pins {{ mi.dst_pin }}] +{% endfor %} +{% endfor %} + +# --- Unified Memory SmartConnect root (mem port + kernel masters -> memories) --- +set mem_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect mem_sc ] +set_property -dict [list \ + CONFIG.NUM_SI {{ "{" ~ mem_sc_num_si ~ "}" }} \ + CONFIG.NUM_MI {2} \ +] [get_bd_cells mem_sc] +connect_bd_net [get_bd_ports clk] [get_bd_pins mem_sc/aclk] +connect_bd_net [get_bd_ports rst] [get_bd_pins mem_sc/aresetn] + +connect_bd_intf_net [get_bd_intf_pins mem_sc/M00_AXI] [get_bd_intf_pins bram_ctrl/S_AXI] +connect_bd_intf_net [get_bd_intf_pins mem_sc/S00_AXI] [get_bd_intf_ports mem] +connect_bd_intf_net [get_bd_intf_pins mem_sc/M01_AXI] [get_bd_intf_pins bram_ctrl_ddr/S_AXI] +connect_bd_net [get_bd_ports clk] [get_bd_pins bram_ctrl/s_axi_aclk] +connect_bd_net [get_bd_ports rst] [get_bd_pins bram_ctrl/s_axi_aresetn] +connect_bd_net [get_bd_ports clk] [get_bd_pins bram_ctrl_ddr/s_axi_aclk] +connect_bd_net [get_bd_ports rst] [get_bd_pins bram_ctrl_ddr/s_axi_aresetn] + +# --- AXI-Full reduction tree (fan-in) --- +{% for n in mem_reduce_nodes %} +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_SI {{ "{" ~ n.num_si ~ "}" }} \ + CONFIG.NUM_MI {1} \ +] [get_bd_cells {{ n.name }}] +connect_bd_net [get_bd_ports clk] [get_bd_pins {{ n.name }}/aclk] +connect_bd_net [get_bd_ports rst] [get_bd_pins {{ n.name }}/aresetn] +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ n.name }}/{{ si.slot_name }}] [get_bd_intf_pins {{ si.src }}] +{% endfor %} +{% endfor %} + +{% for root in mem_roots %} +connect_bd_intf_net [get_bd_intf_pins mem_sc/{{ root.slot_name }}] [get_bd_intf_pins {{ root.src_pin }}] +{% endfor %} + +# --- Clocks / resets to kernels --- +{% for p in clock_ports %} +connect_bd_net [get_bd_ports clk] [get_bd_pins {{ p }}] +{% endfor %} +{% for p in reset_ports %} +connect_bd_net [get_bd_ports rst] [get_bd_pins {{ p }}] +{% endfor %} + +# --- AXIS streams --- +{% for s in axis_streams %} +connect_bd_intf_net -intf_net {{ s.net_name }} [get_bd_intf_pins {{ s.src_pin }}] [get_bd_intf_pins {{ s.dst_pin }}] +{% endfor %} + +# --- AXI-Lite address assignment --- +{% for a in axilite_addr %} +assign_bd_address -offset {{ a.offset_hex }} -range {{ a.range_hex }} [get_bd_addr_segs {{ a.inst }}/{{ a.busif }}/{{ a.segment }}] -force +{% endfor %} + +assign_bd_address -offset 0x4000000000 -range 128M [get_bd_addr_segs /bram_ctrl/S_AXI/Mem0] -force +assign_bd_address -offset 0x60000000000 -range 128M [get_bd_addr_segs /bram_ctrl_ddr/S_AXI/Mem0] -force +save_bd_design +validate_bd_design +add_files -norecurse [make_wrapper -files [get_files "${bd_name}.bd"] -top] +set_property top top_wrapper [current_fileset] +update_compile_order -fileset sources_1 +set_property top top_wrapper [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +update_compile_order -fileset sim_1 +set_property -name {xsim.elaborate.xelab.more_options} -value {-dll} -objects [get_filesets sim_1] +set_property generate_scripts_only 1 [current_fileset -simset] +launch_simulation -scripts_only +{% if sim_checkpoint_netlists %} +# Vivado may mark checkpoint-derived netlists as AutoDisabled in the project file. +# Ensure they are present in the generated XSIM compile project. +set vlog_prj [file join ${sim_prj_dir} "sim_prj.sim" "sim_1" "behav" "xsim" "top_wrapper_vlog.prj"] +if {[file exists ${vlog_prj}]} { + set fh [open ${vlog_prj} r] + set prj_data [read ${fh}] + close ${fh} + + set missing_ckpt [list] + foreach f ${slash_ckpt_vlog_files} { + if {[string first ${f} ${prj_data}] < 0} { + lappend missing_ckpt ${f} + } + } + + if {[llength ${missing_ckpt}] > 0} { + set insert_block "\n# SLASH checkpoint-backed kernel netlists\n" + foreach f ${missing_ckpt} { + append insert_block "verilog xil_defaultlib \"${f}\"\n" + } + + set marker "# compile glbl module" + set idx [string first ${marker} ${prj_data}] + if {$idx >= 0} { + set new_data "[string range ${prj_data} 0 [expr {$idx - 1}]]${insert_block}[string range ${prj_data} ${idx} end]" + } else { + set new_data "${prj_data}${insert_block}" + } + + set fh [open ${vlog_prj} w] + puts -nonewline ${fh} ${new_data} + close ${fh} + } +} +{% endif %} +close_project +exit diff --git a/linker/slashkit/resources/templates/slash.tcl b/linker/slashkit/resources/templates/slash.tcl new file mode 100644 index 00000000..22fba3f3 --- /dev/null +++ b/linker/slashkit/resources/templates/slash.tcl @@ -0,0 +1,1335 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +delete_bd_objs [get_bd_cells ] +delete_bd_objs [get_bd_intf_nets] +delete_bd_objs [get_bd_nets] +update_compile_order -fileset sources_1 + {% raw %} + set_property APERTURES {{0x40_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_00] + set_property APERTURES {{0x40_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_01] + set_property APERTURES {{0x40_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_02] + set_property APERTURES {{0x40_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_03] + set_property APERTURES {{0x40_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_04] + set_property APERTURES {{0x40_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_05] + set_property APERTURES {{0x40_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_06] + set_property APERTURES {{0x40_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_07] + set_property APERTURES {{0x41_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_08] + set_property APERTURES {{0x41_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_09] + set_property APERTURES {{0x41_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_10] + set_property APERTURES {{0x41_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_11] + set_property APERTURES {{0x41_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_12] + set_property APERTURES {{0x41_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_13] + set_property APERTURES {{0x41_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_14] + set_property APERTURES {{0x41_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_15] + set_property APERTURES {{0x42_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_16] + set_property APERTURES {{0x42_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_17] + set_property APERTURES {{0x42_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_18] + set_property APERTURES {{0x42_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_19] + set_property APERTURES {{0x42_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_20] + set_property APERTURES {{0x42_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_21] + set_property APERTURES {{0x42_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_22] + set_property APERTURES {{0x42_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_23] + set_property APERTURES {{0x43_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_24] + set_property APERTURES {{0x43_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_25] + set_property APERTURES {{0x43_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_26] + set_property APERTURES {{0x43_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_27] + set_property APERTURES {{0x43_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_28] + set_property APERTURES {{0x43_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_29] + set_property APERTURES {{0x43_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_30] + set_property APERTURES {{0x43_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_31] + set_property APERTURES {{0x44_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_32] + set_property APERTURES {{0x44_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_33] + set_property APERTURES {{0x44_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_34] + set_property APERTURES {{0x44_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_35] + set_property APERTURES {{0x44_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_36] + set_property APERTURES {{0x44_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_37] + set_property APERTURES {{0x44_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_38] + set_property APERTURES {{0x44_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_39] + set_property APERTURES {{0x45_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_40] + set_property APERTURES {{0x45_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_41] + set_property APERTURES {{0x45_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_42] + set_property APERTURES {{0x45_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_43] + set_property APERTURES {{0x45_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_44] + set_property APERTURES {{0x45_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_45] + set_property APERTURES {{0x45_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_46] + set_property APERTURES {{0x45_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_47] + set_property APERTURES {{0x46_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_48] + set_property APERTURES {{0x46_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_49] + set_property APERTURES {{0x46_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_50] + set_property APERTURES {{0x46_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_51] + set_property APERTURES {{0x46_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_52] + set_property APERTURES {{0x46_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_53] + set_property APERTURES {{0x46_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_54] + set_property APERTURES {{0x46_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_55] + set_property APERTURES {{0x47_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_56] + set_property APERTURES {{0x47_0000_0000 1G}} [get_bd_intf_ports HBM_AXI_57] + set_property APERTURES {{0x47_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_58] + set_property APERTURES {{0x47_4000_0000 1G}} [get_bd_intf_ports HBM_AXI_59] + set_property APERTURES {{0x47_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_60] + set_property APERTURES {{0x47_8000_0000 1G}} [get_bd_intf_ports HBM_AXI_61] + set_property APERTURES {{0x47_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_62] + set_property APERTURES {{0x47_C000_0000 1G}} [get_bd_intf_ports HBM_AXI_63] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_00] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_01] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_02] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_03] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_04] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_05] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_06] + set_property APERTURES {{0x0 2G} {0x40_0000_0000 1G} {0x40_4000_0000 1G} {0x40_8000_0000 1G} {0x40_C000_0000 1G} {0x41_0000_0000 1G} {0x41_4000_0000 1G} {0x41_8000_0000 1G} {0x41_C000_0000 1G} {0x42_0000_0000 1G} {0x42_4000_0000 1G} {0x42_8000_0000 1G} {0x42_C000_0000 1G} {0x43_0000_0000 1G} {0x43_4000_0000 1G} {0x43_8000_0000 1G} {0x43_C000_0000 1G} {0x44_0000_0000 1G} {0x44_4000_0000 1G} {0x44_8000_0000 1G} {0x44_C000_0000 1G} {0x45_0000_0000 1G} {0x45_4000_0000 1G} {0x45_8000_0000 1G} {0x45_C000_0000 1G} {0x46_0000_0000 1G} {0x46_4000_0000 1G} {0x46_8000_0000 1G} {0x46_C000_0000 1G} {0x47_0000_0000 1G} {0x47_4000_0000 1G} {0x47_8000_0000 1G} {0x47_C000_0000 1G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports HBM_VNOC_INI_07] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports M00_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports M01_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports M02_INI] + set_property APERTURES {{0x0 2G} {0x500_8000_0000 2G} {0x600_0000_0000 32G}} [get_bd_intf_ports M03_INI] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports QDMA_SLAVE_BRIDGE_0] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports SL_VIRT_00] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports SL_VIRT_01] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports SL_VIRT_02] + set_property APERTURES {{0x208_0000_0000 32G}} [get_bd_intf_ports SL_VIRT_03] + set_property APERTURES {{0x202_0000_0000 128M}} [get_bd_intf_ports S_AXILITE_INI] + {% endraw %} + # Create instance: ddr_noc_0, and set properties + set ddr_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc ddr_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_0/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_0/aclk0] + + # Create instance: ddr_noc_1, and set properties + set ddr_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc ddr_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_1/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_1/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_1/aclk0] + + # Create instance: ddr_noc_2, and set properties + set ddr_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc ddr_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_2/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_2/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_2/aclk0] + + # Create instance: ddr_noc_3, and set properties + set ddr_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc ddr_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $ddr_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /ddr_noc_3/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /ddr_noc_3/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /ddr_noc_3/aclk0] + + # Create instance: hbm_vnoc_00, and set properties + set hbm_vnoc_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_00 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_00 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_00/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_00/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_00/aclk0] + + # Create instance: hbm_vnoc_01, and set properties + set hbm_vnoc_01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_01 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_01 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_01/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_01/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_01/aclk0] + + # Create instance: hbm_vnoc_02, and set properties + set hbm_vnoc_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_02 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_02 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_02/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_02/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_02/aclk0] + + # Create instance: hbm_vnoc_03, and set properties + set hbm_vnoc_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_03 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_03 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_03/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_03/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_03/aclk0] + + # Create instance: hbm_vnoc_04, and set properties + set hbm_vnoc_04 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_04 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_04 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_04/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_04/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_04/aclk0] + + # Create instance: hbm_vnoc_05, and set properties + set hbm_vnoc_05 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_05 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_05 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_05/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_05/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_05/aclk0] + + # Create instance: hbm_vnoc_06, and set properties + set hbm_vnoc_06 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_06 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_06 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_06/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_06/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_06/aclk0] + + # Create instance: hbm_vnoc_07, and set properties + set hbm_vnoc_07 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc hbm_vnoc_07 ] + set_property -dict [list \ + CONFIG.NSI_NAMES {} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $hbm_vnoc_07 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /hbm_vnoc_07/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /hbm_vnoc_07/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /hbm_vnoc_07/aclk0] + + # Create instance: dcmac_axis_noc_0, and set properties + set dcmac_axis_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_0 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS { write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_0/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_0/aclk0] + + # Create instance: dcmac_axis_noc_1, and set properties + set dcmac_axis_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_1 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_1 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_1/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_1/aclk0] + + # Create instance: dcmac_axis_noc_2, and set properties + set dcmac_axis_noc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_2 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_2 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_2/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_2/aclk0] + + # Create instance: dcmac_axis_noc_3, and set properties + set dcmac_axis_noc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_3 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_3 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_3/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_3/aclk0] + + # Create instance: dcmac_axis_noc_4, and set properties + set dcmac_axis_noc_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_4 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_4 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_4/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_4/aclk0] + + # Create instance: dcmac_axis_noc_5, and set properties + set dcmac_axis_noc_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_5 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_5 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_5/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_5/aclk0] + + # Create instance: dcmac_axis_noc_6, and set properties + set dcmac_axis_noc_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_6 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_6 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_6/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_6/aclk0] + + # Create instance: dcmac_axis_noc_7, and set properties + set dcmac_axis_noc_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_7 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $dcmac_axis_noc_7 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/M00_INIS] + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CONNECTIONS {M00_INIS {write_bw {500}}} \ + CONFIG.DEST_IDS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_7/S00_AXIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_7/aclk0] + + # Create instance: dcmac_axis_noc_s_0, and set properties + set dcmac_axis_noc_s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_0 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_0/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_0/aclk0] + + # Create instance: dcmac_axis_noc_s_1, and set properties + set dcmac_axis_noc_s_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_1 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_1 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_1/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_1/aclk0] + + # Create instance: dcmac_axis_noc_s_2, and set properties + set dcmac_axis_noc_s_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_2 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_2 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_2/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_2/aclk0] + + # Create instance: dcmac_axis_noc_s_3, and set properties + set dcmac_axis_noc_s_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_3 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_3 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_3/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_3/aclk0] + + # Create instance: dcmac_axis_noc_s_4, and set properties + set dcmac_axis_noc_s_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_4 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_4 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_4/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_4/aclk0] + + # Create instance: dcmac_axis_noc_s_5, and set properties + set dcmac_axis_noc_s_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_5 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_5 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_5/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_5/aclk0] + + # Create instance: dcmac_axis_noc_s_6, and set properties + set dcmac_axis_noc_s_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_6 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_6 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_6/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_6/aclk0] + + # Create instance: dcmac_axis_noc_s_7, and set properties + set dcmac_axis_noc_s_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_noc:1.0 dcmac_axis_noc_s_7 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $dcmac_axis_noc_s_7 + + + set_property -dict [ list \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/M00_AXIS] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXIS { write_bw {500} write_avg_burst {4}}} \ + CONFIG.DEST_IDS {} \ + ] [get_bd_intf_pins /dcmac_axis_noc_s_7/S00_INIS] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXIS} \ + ] [get_bd_pins /dcmac_axis_noc_s_7/aclk0] + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + + # Create instance: axi_noc_0, and set properties + set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_0 ] + set_property -dict [list \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_0 + +{% raw %} + set_property -dict [ list \ + CONFIG.APERTURES {{0x202_0000_0000 128M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_0/M00_AXI] + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI {read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ + ] [get_bd_intf_pins /axi_noc_0/S00_INI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + ] [get_bd_pins /axi_noc_0/aclk0] + {% endraw %} + + + # Create instance: noc_virt_00, and set properties + set noc_virt_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_00 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_00 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_00/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_00/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_00/aclk0] + + # Create instance: noc_virt_01, and set properties + set noc_virt_01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_01 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_01 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_01/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_01/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_01/aclk0] + + # Create instance: noc_virt_02, and set properties + set noc_virt_02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_02 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_02 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_02/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_02/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_02/aclk0] + + # Create instance: noc_virt_03, and set properties + set noc_virt_03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc noc_virt_03 ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + CONFIG.NUM_NSI {0} \ + ] $noc_virt_03 + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /noc_virt_03/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /noc_virt_03/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /noc_virt_03/aclk0] + + # Create instance: qdma_slave_bridge_noc, and set properties + set qdma_slave_bridge_noc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc qdma_slave_bridge_noc ] + set_property -dict [list \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {1} \ + ] $qdma_slave_bridge_noc + + + set_property -dict [ list \ + CONFIG.INI_STRATEGY {driver} \ + ] [get_bd_intf_pins /qdma_slave_bridge_noc/M00_INI] + + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {500} write_bw {500}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /qdma_slave_bridge_noc/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /qdma_slave_bridge_noc/aclk0] + + + # Create instance: c_shift_ram_0, and set properties + set c_shift_ram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 c_shift_ram_0 ] + set_property -dict [list \ + CONFIG.Depth {1} \ + CONFIG.Width {1} \ + ] $c_shift_ram_0 + + + # Create instance: ilreduced_logic_0, and set properties + set ilreduced_logic_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilreduced_logic:1.0 ilreduced_logic_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $ilreduced_logic_0 + + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ] + set_property CONFIG.C_BUF_TYPE {BUFG_FABRIC} $util_ds_buf_0 + + connect_bd_net -net util_ds_buf_0_BUFG_FABRIC_O [get_bd_pins util_ds_buf_0/BUFG_FABRIC_O] \ + [get_bd_pins ilreduced_logic_0/Op1] + + connect_bd_net -net arstn_1 [get_bd_ports arstn] \ + [get_bd_pins c_shift_ram_0/D] + + connect_bd_net -net c_shift_ram_0_Q [get_bd_pins c_shift_ram_0/Q] \ + [get_bd_pins util_ds_buf_0/BUFG_FABRIC_I] + + + # Create interface connections + connect_bd_intf_net -intf_net S00_INIS_0_1 [get_bd_intf_ports S_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_s_0/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_1_1 [get_bd_intf_ports S_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_s_1/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_2_1 [get_bd_intf_ports S_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_s_2/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_3_1 [get_bd_intf_ports S_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_s_3/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_4_1 [get_bd_intf_ports S_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_s_4/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_5_1 [get_bd_intf_ports S_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_s_5/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_6_1 [get_bd_intf_ports S_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_s_6/S00_INIS] + connect_bd_intf_net -intf_net S00_INIS_7_1 [get_bd_intf_ports S_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_s_7/S00_INIS] + connect_bd_intf_net -intf_net S_AXILITE_INI_1 [get_bd_intf_ports S_AXILITE_INI] [get_bd_intf_pins axi_noc_0/S00_INI] + connect_bd_intf_net -intf_net axi_noc_1_M00_INI [get_bd_intf_ports QDMA_SLAVE_BRIDGE_0] [get_bd_intf_pins qdma_slave_bridge_noc/M00_INI] + connect_bd_intf_net -intf_net dcmac_axis_noc_0_M00_INIS [get_bd_intf_ports M_DCMAC_INIS0] [get_bd_intf_pins dcmac_axis_noc_0/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_1_M00_INIS [get_bd_intf_ports M_DCMAC_INIS1] [get_bd_intf_pins dcmac_axis_noc_1/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_2_M00_INIS [get_bd_intf_ports M_DCMAC_INIS2] [get_bd_intf_pins dcmac_axis_noc_2/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_3_M00_INIS [get_bd_intf_ports M_DCMAC_INIS3] [get_bd_intf_pins dcmac_axis_noc_3/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_4_M00_INIS [get_bd_intf_ports M_DCMAC_INIS4] [get_bd_intf_pins dcmac_axis_noc_4/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_5_M00_INIS [get_bd_intf_ports M_DCMAC_INIS5] [get_bd_intf_pins dcmac_axis_noc_5/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_6_M00_INIS [get_bd_intf_ports M_DCMAC_INIS6] [get_bd_intf_pins dcmac_axis_noc_6/M00_INIS] + connect_bd_intf_net -intf_net dcmac_axis_noc_7_M00_INIS [get_bd_intf_ports M_DCMAC_INIS7] [get_bd_intf_pins dcmac_axis_noc_7/M00_INIS] + connect_bd_intf_net -intf_net ddr_noc_0_M00_INI [get_bd_intf_ports M00_INI] [get_bd_intf_pins ddr_noc_0/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_1_M00_INI [get_bd_intf_ports M01_INI] [get_bd_intf_pins ddr_noc_1/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_2_M00_INI [get_bd_intf_ports M02_INI] [get_bd_intf_pins ddr_noc_2/M00_INI] + connect_bd_intf_net -intf_net ddr_noc_3_M00_INI [get_bd_intf_ports M03_INI] [get_bd_intf_pins ddr_noc_3/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_00_M00_INI [get_bd_intf_ports HBM_VNOC_INI_00] [get_bd_intf_pins hbm_vnoc_00/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_01_M00_INI [get_bd_intf_ports HBM_VNOC_INI_01] [get_bd_intf_pins hbm_vnoc_01/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_02_M00_INI [get_bd_intf_ports HBM_VNOC_INI_02] [get_bd_intf_pins hbm_vnoc_02/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_03_M00_INI [get_bd_intf_ports HBM_VNOC_INI_03] [get_bd_intf_pins hbm_vnoc_03/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_04_M00_INI [get_bd_intf_ports HBM_VNOC_INI_04] [get_bd_intf_pins hbm_vnoc_04/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_05_M00_INI [get_bd_intf_ports HBM_VNOC_INI_05] [get_bd_intf_pins hbm_vnoc_05/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_06_M00_INI [get_bd_intf_ports HBM_VNOC_INI_06] [get_bd_intf_pins hbm_vnoc_06/M00_INI] + connect_bd_intf_net -intf_net hbm_vnoc_07_M00_INI [get_bd_intf_ports HBM_VNOC_INI_07] [get_bd_intf_pins hbm_vnoc_07/M00_INI] + connect_bd_intf_net -intf_net noc_virt_00_M00_INI [get_bd_intf_ports SL_VIRT_00] [get_bd_intf_pins noc_virt_00/M00_INI] + connect_bd_intf_net -intf_net noc_virt_01_M00_INI [get_bd_intf_ports SL_VIRT_01] [get_bd_intf_pins noc_virt_01/M00_INI] + connect_bd_intf_net -intf_net noc_virt_02_M00_INI [get_bd_intf_ports SL_VIRT_02] [get_bd_intf_pins noc_virt_02/M00_INI] + connect_bd_intf_net -intf_net noc_virt_03_M00_INI [get_bd_intf_ports SL_VIRT_03] [get_bd_intf_pins noc_virt_03/M00_INI] + + # Create port connections + connect_bd_net -net user_clk_net [get_bd_pins user_clk] \ + [get_bd_pins ddr_noc_0/aclk0] \ + [get_bd_pins ddr_noc_3/aclk0] \ + [get_bd_pins ddr_noc_2/aclk0] \ + [get_bd_pins ddr_noc_1/aclk0] \ + [get_bd_pins hbm_vnoc_00/aclk0] \ + [get_bd_pins hbm_vnoc_01/aclk0] \ + [get_bd_pins hbm_vnoc_02/aclk0] \ + [get_bd_pins hbm_vnoc_03/aclk0] \ + [get_bd_pins hbm_vnoc_04/aclk0] \ + [get_bd_pins hbm_vnoc_05/aclk0] \ + [get_bd_pins hbm_vnoc_06/aclk0] \ + [get_bd_pins hbm_vnoc_07/aclk0] \ + [get_bd_pins dcmac_axis_noc_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_7/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_0/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_1/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_2/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_3/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_4/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_5/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_6/aclk0] \ + [get_bd_pins dcmac_axis_noc_s_7/aclk0] \ + [get_bd_pins noc_virt_00/aclk0] \ + [get_bd_pins noc_virt_01/aclk0] \ + [get_bd_pins noc_virt_02/aclk0] \ + [get_bd_pins noc_virt_03/aclk0] \ + [get_bd_pins qdma_slave_bridge_noc/aclk0] \ + [get_bd_pins axi_noc_0/aclk0] \ + [get_bd_pins c_shift_ram_0/CLK] + + # Tie-off RX tready only for unused DCMAC RX NoC slots. + {% if dcmac_rx_tready_tie_pins|default([]) %} + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] \ + {% for p in dcmac_rx_tready_tie_pins %} + [get_bd_pins {{ p }}]{{ " \\" if not loop.last else "" }} + {% endfor %} + {% endif %} + +# === Instantiate kernel IPs === +{% for name, inst in instances.items() %} +set {{ name }} [ create_bd_cell -type ip -vlnv {{ inst.kernel.vlnv }} {{ name }} ] +{% endfor %} + +# === Per-kernel AXI-MM data width tweaks for HBM/VIRT === +{% for p in data_width_params %} +#set_property {{ p.param }} {{ "{" ~ p.value ~ "}" }} [get_bd_cells {{ p.inst }}] +{% endfor %} + + +# === Connect kernel clocks to aclk1 === +{% for c in clocks %} +connect_bd_net [get_bd_pins {{ c.src_pin }}] [get_bd_pins user_clk] +{% endfor %} + +# === Connect kernel resets to ap_rst_n === +{% for r in resets %} +connect_bd_net [get_bd_pins {{ r.src_pin }}] [get_bd_pins ilreduced_logic_0/Res] +{% endfor %} + +# === SmartConnects for AXI-Lite control === +{% for sc in smartconnects %} +# Create {{ sc.name }} +set {{ sc.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ sc.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_SI {1} \ + CONFIG.NUM_MI {{ '{' ~ sc.num_mi ~ '}' }} \ +] ${{ sc.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ sc.name }}/aclk] [get_bd_pins user_clk] +connect_bd_net [get_bd_pins {{ sc.name }}/aresetn] [get_bd_pins ilreduced_logic_0/Res] + +# SI (slave) connection +{% if sc.si_from.type == 'bd_port' %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.si_from.name }}] [get_bd_intf_pins {{ sc.name }}/S00_AXI] +{% else %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.si_from.prev }}/M{{ "%02d"|format(sc.chain_slot) }}_AXI] [get_bd_intf_pins {{ sc.name }}/S00_AXI] +{% endif %} + +# MI (master) connections to kernel AXI-Lite pins +{% for m in sc.mi %} +connect_bd_intf_net [get_bd_intf_pins {{ sc.name }}/M{{ "%02d"|format(m.slot) }}_AXI] [get_bd_intf_pins {{ m.dst_pin }}] +{% endfor %} + +{% endfor %} + +# === HBM AXI-MM connections === + +# === HBM reduction nodes (internal fan-in) === +{% for n in hbm_reduce_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ "{" ~ n.num_si ~ "}" }} \ +] ${{ n.name }} +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_pins {{ n.clk }}] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_pins {{ n.rst }}] +{% for si in n.si %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ si.src }}] \ + [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} +{% endfor %} + +# === HBM root SmartConnects (instantiate only for channels with writers) === +{% for r in hbm_root_create|default([]) %} +# {{ r.name }} drives HBM{{ "%02d"|format(r.idx) }} +set {{ r.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ r.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ +] ${{ r.name }} +# Clocks / reset +connect_bd_net [get_bd_pins {{ r.name }}/aclk] [get_bd_pins {{ r.clk0 }}] +connect_bd_net [get_bd_pins {{ r.name }}/aclk1] {{ r.clk1 }} +connect_bd_net [get_bd_pins {{ r.name }}/aresetn] [get_bd_pins {{ r.rst }}] +{% endfor %} + +# === Wire into the root (either single source or last reduction MI) === +{% for w in hbm_root_in|default([]) %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ w.src_pin }}] \ + [get_bd_intf_pins {{ w.dst_pin }}] +{% endfor %} + +# === Root MI -> real HBM port === +{% for o in hbm_root_out|default([]) %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ o.src_pin }}] \ + [get_bd_intf_ports {{ o.dst_port }}] +{% endfor %} + + +# === DDR AXI-MM connections (via Versal NoC) === + +# Direct connects: single writer to a DDRx NoC slave +{% for c in ddr_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_pins {{ c.dst_pin }}] +{% endfor %} + +# SmartConnect reduction nodes (NUM_CLKS=1, aclk→aclk1, aresetn→ap_rst_n) +{% for n in ddr_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ '{' ~ n.num_si ~ '}' }} \ +] ${{ n.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_pins user_clk] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_pins ilreduced_logic_0/Res] + +# SIs into this SmartConnect +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ si.src }}] [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} + +{% endfor %} + +# Root outputs to DDR NoC slaves +{% for r in ddr_smart_roots|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] [get_bd_intf_pins {{ r.dst_pin }}] +{% endfor %} + +# === MEM AXI-MM connections (via VNOC) === + +# Direct connects: single writer to a MEMx VNOC slave +{% for c in mem_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_pins {{ c.dst_pin }}] +{% endfor %} + +# SmartConnect reduction nodes for MEMx (NUM_CLKS=1, aclk→aclk1, aresetn→ap_rst_n) +{% for n in mem_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ '{' ~ n.num_si ~ '}' }} \ +] ${{ n.name }} + +# Clocks/Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_pins user_clk] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_pins ilreduced_logic_0/Res] + +# SIs into this SmartConnect +{% for si in n.si %} +connect_bd_intf_net [get_bd_intf_pins {{ si.src }}] [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} + +{% endfor %} + +# Root outputs to VNOC slaves +{% for r in mem_smart_roots|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] [get_bd_intf_pins {{ r.dst_pin }}] +{% endfor %} + +# === VIRT AXI-MM connections (connects to NoC) === +{% for c in virt_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_pins {{ c.dst_pin }}] +{% endfor %} + +# VIRT SmartConnect nodes (NUM_CLKS=1; aclk=aclk1, aresetn=ap_rst_n) +{% for n in virt_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ "{" ~ n.num_si ~ "}" }} \ +] ${{ n.name }} + +# Clock / Reset +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_pins user_clk] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_pins ilreduced_logic_0/Res] + +# SI fan-in +{% for si in n.si %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ si.src }}] \ + [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} +{% endfor %} + +# VIRT SmartConnect roots → NoC pin +{% for r in virt_smart_roots|default([]) %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] \ + [get_bd_intf_pins {{ r.dst_pin }}] +{% endfor %} + + +# === AXIS stream connections from config === +{% for e in axis_streams|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + +# === AXIS network: instance -> fabric TX === +{% for e in axis_to_fabric|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + +# === AXIS network: fabric RX -> instance === +{% for e in axis_from_fabric|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ e.src_pin }}] [get_bd_intf_pins {{ e.dst_pin }}] +{% endfor %} + +# === AXI Register Slice terminators for UNUSED memory endpoints === +{% for t in axi_terminators|default([]) %} +# {{ t.name }} -> {{ t.dst }} +set {{ t.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 {{ t.name }} ] + +# Clock / Reset (defaults to user_clk and arstn if not provided) +connect_bd_net [get_bd_pins {{ t.name }}/aclk] [get_bd_pins {{ t.clk|default('user_clk') }}] +connect_bd_net [get_bd_pins {{ t.name }}/aresetn] [get_bd_pins {{ t.rst|default('ilreduced_logic_0/Res') }}] + +# Leave S_AXI unconnected on purpose + +# Connect M_AXI to the free destination pin +connect_bd_intf_net [get_bd_intf_pins {{ t.name }}/M_AXI] [get_bd_intf_pins {{ t.dst }}] + +{% endfor %} + + +# === HOST aggregation: SmartConnect tree -> QDMA_SLAVE_BRIDGE === +{% for c in host_direct|default([]) %} +connect_bd_intf_net [get_bd_intf_pins {{ c.src_pin }}] [get_bd_intf_pins {{ c.dst_pin }}] +{% endfor %} + +# HOST SmartConnect nodes (if any) +{% for n in host_smart_nodes|default([]) %} +# {{ n.name }} (NUM_SI={{ n.num_si }}, NUM_MI=1) +set {{ n.name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 {{ n.name }} ] +set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {{ "{" ~ n.num_si ~ "}" }} \ +] ${{ n.name }} +connect_bd_net [get_bd_pins {{ n.name }}/aclk] [get_bd_pins user_clk] +connect_bd_net [get_bd_pins {{ n.name }}/aresetn] [get_bd_pins ilreduced_logic_0/Res] +{% for si in n.si %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ si.src }}] \ + [get_bd_intf_pins {{ n.name }}/S{{ "%02d"|format(si.slot) }}_AXI] +{% endfor %} +{% endfor %} + +# HOST SmartConnect root to NoC sink +{% for r in host_smart_roots|default([]) %} +connect_bd_intf_net \ + [get_bd_intf_pins {{ r.sc_name }}/M00_AXI] \ + [get_bd_intf_pins {{ r.dst_pin }}] +{% endfor %} + + +# === Optional AXIS ILA debug === +{% if debug_axis_ila_enabled|default(false) %} +set {{ debug_axis_ila_name }} [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_ila:1.3 {{ debug_axis_ila_name }} ] +set_property -dict [list \ + CONFIG.C_MON_TYPE {Interface_Monitor} \ + CONFIG.C_NUM_MONITOR_SLOTS {{ "{" ~ debug_axis_ila_num_slots ~ "}" }} \ +] [get_bd_cells {{ debug_axis_ila_name }}] +{% for s in debug_axis_ila_slots %} +set_property CONFIG.C_SLOT_{{ s.idx }}_INTF_TYPE {{ "{" ~ s.intf_type ~ "}" }} [get_bd_cells {{ debug_axis_ila_name }}] +{% endfor %} +connect_bd_net [get_bd_pins {{ debug_axis_ila_name }}/clk] [get_bd_pins user_clk] +connect_bd_net [get_bd_pins {{ debug_axis_ila_name }}/resetn] [get_bd_pins ilreduced_logic_0/Res] +{% for s in debug_axis_ila_slots %} +connect_bd_intf_net [get_bd_intf_pins {{ debug_axis_ila_name }}/{{ s.slot_pin }}] [get_bd_intf_pins {{ s.src_pin }}] +{% endfor %} +{% endif %} + +# === AXI-Lite address map === +{% for a in axilite_addr %} +assign_bd_address -offset {{ "0x%012X"|format(a.offset) }} -range {{ "0x%08X"|format(a.range) }} -target_address_space [get_bd_addr_spaces {{ a.addr_space }}] [get_bd_addr_segs {{ a.inst }}/{{ a.busif }}/{{ a.segment }}] -force +{% endfor %} + +# === Assign all other addresses === +assign_bd_address +validate_bd_design +save_bd_design + +# current_bd_design [get_bd_designs top] +# validate_bd_design +# save_bd_design diff --git a/linker/slashkit/resources/templates/sw_emu_tb.cpp b/linker/slashkit/resources/templates/sw_emu_tb.cpp new file mode 100644 index 00000000..36444d89 --- /dev/null +++ b/linker/slashkit/resources/templates/sw_emu_tb.cpp @@ -0,0 +1,834 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +{% for p in prototypes %} +{{ p }} +{% endfor %} + +template +void assignValue(T& var, const Json::Value& value) { + if (value.isString()) { std::istringstream iss(value.asString()); iss >> var; } + else if (value.isInt()) var = static_cast(value.asInt()); + else if (value.isUInt()) var = static_cast(value.asUInt()); + else if (value.isDouble()) var = static_cast(value.asDouble()); + else throw std::runtime_error("Unsupported JSON value type"); +} + +template +Json::Value createJsonValue(const T& var) { + uint32_t raw = 0; + const size_t n = sizeof(raw) < sizeof(T) ? sizeof(raw) : sizeof(T); + std::memcpy(&raw, &var, n); + return Json::Value(raw); +} + +template +Json::Value createJsonValueHi(const T& var) { + uint32_t raw = 0; + if (sizeof(T) > sizeof(uint32_t)) { + const size_t off = sizeof(uint32_t); + const size_t remain = sizeof(T) - off; + const size_t n = sizeof(raw) < remain ? sizeof(raw) : remain; + std::memcpy(&raw, reinterpret_cast(&var) + off, n); + } + return Json::Value(raw); +} + +Json::Value createJsonBuffer(const uint8_t* buffer, size_t size) { + Json::Value value(Json::arrayValue); + for (size_t i = 0; i < size; ++i) { + value.append(buffer[i]); + } + return value; +} + +std::string emuJsonString(const Json::Value& value) { + Json::StreamWriterBuilder writer; + writer["indentation"] = ""; + std::string s = Json::writeString(writer, value); + if (!s.empty() && s.back() == '\n') s.pop_back(); + return s; +} + +void emuExecLog(const char* scope, const std::string& msg) { + std::cerr << "EMU_EXEC: [" << scope << "] " << msg << std::endl; +} + +bool emuExecVerboseEnabled() { + static const bool enabled = []() { + const char* env = std::getenv("EMU_EXEC_VERBOSE"); + if (env == nullptr) return false; + std::string v(env); + return !(v.empty() || v == "0" || v == "false" || v == "FALSE" || v == "off" || v == "OFF"); + }(); + return enabled; +} + +void emuExecDebug(const char* scope, const std::string& msg) { + if (emuExecVerboseEnabled()) { + emuExecLog(scope, msg); + } +} + +int main() { + zmq::context_t context(1); + zmq::socket_t socket(context, ZMQ_REP); + socket.bind("tcp://*:5555"); + emuExecLog("startup", std::string("bound REP socket to tcp://*:5555") + + (emuExecVerboseEnabled() ? " (verbose=on)" : " (verbose=off)")); + + std::map buffers; + std::map bufferSizes; + +{% for v in vars %} + {{ v }}; +{% endfor %} + +{% for w in wires %} + hls::stream<{{ w.ctype }}> {{ w.name }}; +{% endfor %} + + std::map> autostartRegistry; +{% for ac in autostart_calls %} + autostartRegistry["{{ ac.inst }}"] = [&]() { + {{ ac.top }}({{ ac.call_args | join(", ") }}); + }; +{% endfor %} + std::map> activeCallFutures; + + std::map> fetchScalarRegistry; +{% for sym in fetch_scalar_var_symbols %} + fetchScalarRegistry["{{ sym }}"] = [&]() { + return createJsonValue({{ sym }}); + }; +{% endfor %} + std::map> fetchScalarHiRegistry; +{% for sym in fetch_scalar_var_symbols %} + fetchScalarHiRegistry["{{ sym }}"] = [&]() { + return createJsonValueHi({{ sym }}); + }; +{% endfor %} + std::map> kernelRegisterShadow; + std::mutex kernelRegisterShadowMutex; + + Json::Value emuManifest; + bool emuManifestLoaded = false; + { + std::ifstream manifestFile("emu_manifest.json"); + if (!manifestFile.is_open()) { + emuExecLog("manifest", "emu_manifest.json not found"); + return 1; + } + emuExecDebug("manifest", "opened emu_manifest.json"); + Json::Reader manifestReader; + emuManifestLoaded = manifestReader.parse(manifestFile, emuManifest); + emuExecDebug("manifest", std::string("parse result=") + (emuManifestLoaded ? "success" : "failure")); + if (!emuManifestLoaded) { + emuExecLog("manifest", "parse failed"); + return 1; + } + } + + bool emuManifestUsable = emuManifestLoaded && emuManifest.isObject(); + bool emuManifestHasKernelMetadata = false; + bool emuManifestHasFetchMetadata = false; + bool emuManifestHasRegisterMetadata = false; + bool emuManifestSchemaValidated = false; + bool requireFastExitOnExit = false; + size_t manifestFetchScalarRouteCount = 0; + size_t manifestCallableKernelCount = 0; + size_t manifestAutostartKernelCount = 0; + size_t manifestRegisterCount = 0; + std::map kernelManifestRegistry; + + if (emuManifestLoaded && !emuManifest.isObject()) { + emuExecLog("manifest", "emu_manifest.json parsed but root is not an object"); + return 1; + } + if (emuManifestUsable) { + const Json::Value schema = emuManifest["manifest_schema"]; + if (schema.isObject()) { + emuExecDebug("manifest", std::string("manifest_schema=") + emuJsonString(schema)); + const Json::Value required = schema["required_sections"]; + bool requiredOk = required.isArray(); + if (requiredOk) { + for (const auto& name : required) { + if (!name.isString()) { + requiredOk = false; + emuExecLog("manifest", "required_sections contains non-string entry"); + break; + } + if (!emuManifest.isMember(name.asString())) { + requiredOk = false; + emuExecLog("manifest", std::string("missing required section '") + name.asString() + + "'"); + break; + } + } + } + emuManifestSchemaValidated = schema.get("version", 0).asUInt() >= 1 && requiredOk; + } else { + emuExecLog("manifest", "emu_manifest.json has no manifest_schema"); + return 1; + } + + const Json::Value fetchMeta = emuManifest["fetch"]; + if (fetchMeta.isObject()) { + const Json::Value fetchScalar = fetchMeta["scalar"]; + if (fetchScalar.isArray()) { + emuManifestHasFetchMetadata = true; + manifestFetchScalarRouteCount = fetchScalar.size(); + emuExecDebug("manifest", "fetch.scalar routes=" + std::to_string(manifestFetchScalarRouteCount)); + } + } + } + + if (!emuManifestSchemaValidated) { + emuExecLog("manifest", "manifest schema validation failed"); + return 1; + } + + if (emuManifestUsable) { + const Json::Value kernels = emuManifest["kernels"]; + if (kernels.isArray()) { + emuManifestHasKernelMetadata = true; + for (const auto& k : kernels) { + if (!k.isObject()) continue; + std::string instance = k.get("instance", "").asString(); + if (!instance.empty()) { + kernelManifestRegistry[instance] = k; + std::map regShadow; + const Json::Value regs = k["registers"]; + if (regs.isArray()) { + for (const auto& reg : regs) { + if (!reg.isObject()) continue; + const Json::Value offsetVal = reg["offset"]; + if (!offsetVal.isUInt() && !offsetVal.isInt()) continue; + regShadow[static_cast(offsetVal.asUInt())] = 0u; + manifestRegisterCount += 1; + } + emuManifestHasRegisterMetadata = true; + } + auto ctrlIt = regShadow.find(0x00u); + if (ctrlIt != regShadow.end()) { + // HLS ap_ctrl_hs reset-like state: idle=1, ready=1, done=0, start=0. + ctrlIt->second = 0x0Cu; + } + kernelRegisterShadow[instance] = std::move(regShadow); + emuExecDebug("manifest", std::string("kernel meta loaded for '") + instance + "'"); + } + if (k.get("callable", false).asBool()) { + manifestCallableKernelCount += 1; + } + if (!k.get("autostart", false).asBool()) continue; + manifestAutostartKernelCount += 1; + auto it = autostartRegistry.find(instance); + if (it == autostartRegistry.end()) { + emuExecLog("autostart", std::string("manifest requested autostart for unknown instance '") + instance + "'"); + continue; + } + if (k.get("shutdown_policy", "").asString() == "fast_exit") { + requireFastExitOnExit = true; + } + emuExecLog("autostart", std::string("launching '") + instance + "' from manifest"); + std::thread(it->second).detach(); + } + } + } + + if (!emuManifestHasKernelMetadata) { + emuExecLog("manifest", "manifest missing kernels metadata"); + return 1; + } + if (!emuManifestHasFetchMetadata) { + emuExecLog("manifest", "manifest missing fetch.scalar metadata"); + return 1; + } + if (!emuManifestHasRegisterMetadata) { + emuExecLog("manifest", "manifest missing kernel register metadata"); + return 1; + } + + emuExecLog("manifest", + std::string("manifest loaded") + + " schema=" + (emuManifestSchemaValidated ? "ok" : "invalid") + + " kernels=" + std::to_string(kernelManifestRegistry.size()) + + " regs=" + std::to_string(manifestRegisterCount) + + " callable=" + std::to_string(manifestCallableKernelCount) + + " autostart=" + std::to_string(manifestAutostartKernelCount) + + " fetch.scalar=" + std::to_string(manifestFetchScalarRouteCount)); + + auto setKernelCtrlRunning = [&](const std::string& functionName) { + std::lock_guard lock(kernelRegisterShadowMutex); + auto kernelIt = kernelRegisterShadow.find(functionName); + if (kernelIt == kernelRegisterShadow.end()) return; + auto ctrlIt = kernelIt->second.find(0x00u); + if (ctrlIt == kernelIt->second.end()) return; + const uint32_t autoRestart = ctrlIt->second & 0x80u; + ctrlIt->second = autoRestart | 0x01u; // ap_start=1, done/idle/ready cleared while active + }; + + auto setKernelCtrlCompleted = [&](const std::string& functionName) { + std::lock_guard lock(kernelRegisterShadowMutex); + auto kernelIt = kernelRegisterShadow.find(functionName); + if (kernelIt == kernelRegisterShadow.end()) return; + auto ctrlIt = kernelIt->second.find(0x00u); + if (ctrlIt == kernelIt->second.end()) return; + const uint32_t autoRestart = ctrlIt->second & 0x80u; + ctrlIt->second = autoRestart | 0x0Eu; // ap_done=1, ap_idle=1, ap_ready=1 + }; + + auto refreshKernelRegisterShadowFromManifest = + [&](const std::string& functionName, bool includeSyntheticCtrlValid) { + std::lock_guard lock(kernelRegisterShadowMutex); + auto kernelIt = kernelRegisterShadow.find(functionName); + if (kernelIt == kernelRegisterShadow.end()) return; + const Json::Value fetchRoutes = emuManifest["fetch"]["scalar"]; + if (!fetchRoutes.isArray()) return; + const Json::Value kernelMeta = kernelManifestRegistry[functionName]; + const Json::Value callableArgs = kernelMeta["call_args"]; + + for (const auto& route : fetchRoutes) { + if (!route.isObject()) continue; + if (route.get("function", "").asString() != functionName) continue; + if (!includeSyntheticCtrlValid && callableArgs.isArray()) { + const std::string routeArg = route.get("arg", "").asString(); + bool routeArgIsCallBound = false; + for (const auto& ca : callableArgs) { + if (!ca.isObject()) continue; + if (ca.get("arg", "").asString() == routeArg) { + routeArgIsCallBound = true; + break; + } + } + if (!routeArgIsCallBound) continue; + } + const Json::Value source = route["source"]; + if (!source.isObject()) continue; + const Json::Value regOffVal = source["register_offset"]; + if (!regOffVal.isUInt() && !regOffVal.isInt()) continue; + const uint32_t regOff = static_cast(regOffVal.asUInt()); + auto regIt = kernelIt->second.find(regOff); + if (regIt == kernelIt->second.end()) continue; + + const bool isSyntheticCtrlValid = + source.isMember("synthetic") && source["synthetic"].isString() + && source["synthetic"].asString() == "ctrl_valid"; + if (isSyntheticCtrlValid && !includeSyntheticCtrlValid) { + regIt->second = 0u; + continue; + } + + Json::Value routeValue; + bool handled = false; + const std::string kind = route.get("kind", "").asString(); + if (kind == "var") { + std::string symbol = route.get("var_symbol", "").asString(); + auto it = fetchScalarRegistry.find(symbol); + if (it != fetchScalarRegistry.end()) { + routeValue = it->second(); + handled = true; + } else { + emuExecLog("reg_shadow", + "manifest var route symbol missing from fetchScalarRegistry: " + symbol); + } + } else if (kind == "var_u32_hi") { + std::string symbol = route.get("var_symbol", "").asString(); + auto it = fetchScalarHiRegistry.find(symbol); + if (it != fetchScalarHiRegistry.end()) { + routeValue = it->second(); + handled = true; + } else { + emuExecLog("reg_shadow", + "manifest var_u32_hi symbol missing from fetchScalarHiRegistry: " + symbol); + } + } else if (kind == "const_u32") { + routeValue = Json::Value(static_cast(route.get("value", 0).asUInt())); + handled = true; + } else { + emuExecLog("reg_shadow", "unsupported manifest route kind for shadow refresh: " + kind); + } + + if (!handled) continue; + if (!routeValue.isUInt() && !routeValue.isInt()) { + emuExecLog("reg_shadow", "non-scalar manifest route value for shadow refresh"); + continue; + } + regIt->second = static_cast(routeValue.asUInt()); + } + }; + + while (true) { + zmq::message_t request; + if (!socket.recv(request, zmq::recv_flags::none)) { + emuExecDebug("zmq", "recv(request) returned no message"); + continue; + } + std::string req_str(static_cast(request.data()), request.size()); + Json::Value root; + Json::Reader reader; + if (!reader.parse(req_str, root)) { + emuExecLog("request", std::string("JSON parse failed: ") + reader.getFormattedErrorMessages()); + emuExecDebug("request", std::string("raw=") + req_str); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + continue; + } + + std::string command = root["command"].asString(); + std::string argType; + emuExecDebug("request", "command=" + command + " json=" + emuJsonString(root)); + + if (command == "populate") { + std::string name = root["name"].asString(); + size_t bufferSize = root["size"].asUInt64(); + emuExecDebug("populate", "name=" + name + " size=" + std::to_string(bufferSize)); + + zmq::message_t data; + if (!socket.recv(data, zmq::recv_flags::none)) { + emuExecLog("populate", "failed to receive payload frame"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + continue; + } + void* buffer = new uint8_t[bufferSize]; + memcpy(buffer, data.data(), bufferSize); + + buffers[name] = buffer; + bufferSizes[name] = bufferSize; + emuExecDebug("populate", "stored buffer '" + name + "' bytes=" + std::to_string(bufferSize)); + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + } else if (command == "stream_in") { + std::string name = root["name"].asString(); + emuExecDebug("stream_in", "name=" + name); + zmq::message_t data; + if (!socket.recv(data, zmq::recv_flags::none)) { + emuExecLog("stream_in", "failed to receive payload frame"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + continue; + } + bool handled = false; + +{% for s in stream_routes %} +{% for alias in s.names %} + if (!handled && name == "{{ alias }}") { + handled = true; + emuExecDebug("stream_in", "alias '" + name + "' -> wire '{{ s.wire }}' ctype='{{ s.ctype }}' bytes=" + std::to_string(data.size())); + for (size_t i = 0; i < data.size() / sizeof({{ s.ctype }}); i++) { + {{ s.ctype }} value; + memcpy(&value, static_cast(data.data()) + i * sizeof({{ s.ctype }}), sizeof({{ s.ctype }})); + {{ s.wire }}.write(value); + } + } +{% endfor %} +{% endfor %} + + if (!handled) { + emuExecLog("stream_in", "no alias match for '" + name + "'"); + } + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + } else if (command == "stream_out") { + std::string name = root["name"].asString(); + size_t size = root["size"].asUInt64(); + std::vector buffer(size, 0); + bool handled = false; + emuExecDebug("stream_out", "name=" + name + " size=" + std::to_string(size)); + +{% for s in stream_routes %} +{% for alias in s.names %} + if (!handled && name == "{{ alias }}") { + handled = true; + emuExecDebug("stream_out", "alias '" + name + "' -> wire '{{ s.wire }}' ctype='{{ s.ctype }}' bytes=" + std::to_string(size)); + for (size_t i = 0; i < size / sizeof({{ s.ctype }}); i++) { + {{ s.ctype }} value = {{ s.wire }}.read(); + memcpy(buffer.data() + i * sizeof({{ s.ctype }}), &value, sizeof({{ s.ctype }})); + } + } +{% endfor %} +{% endfor %} + + if (!handled) { + emuExecLog("stream_out", "no alias match for '" + name + "'"); + } + socket.send(zmq::message_t(buffer.data(), buffer.size()), zmq::send_flags::none); + } else if (command == "call" || command == "start") { + std::string functionName = root["function"].asString(); + bool isAsyncStart = (command == "start"); + bool callRejected = false; + std::string callRejectReason; + emuExecDebug("call", "function=" + functionName + + " mode=" + (isAsyncStart ? "start_async" : "call_sync")); + + if (emuManifestHasKernelMetadata) { + auto kernelIt = kernelManifestRegistry.find(functionName); + if (kernelIt == kernelManifestRegistry.end()) { + callRejected = true; + callRejectReason = "unknown_function"; + emuExecDebug("call", "manifest validation failed: function missing from kernelManifestRegistry"); + } else { + const Json::Value& kernelMeta = kernelIt->second; + emuExecDebug("call", "manifest kernel meta=" + emuJsonString(kernelMeta)); + if (!kernelMeta.get("callable", true).asBool()) { + callRejected = true; + callRejectReason = "kernel_not_callable"; + emuExecDebug("call", "manifest validation failed: kernel marked callable=false"); + } else { + const Json::Value expectedArgs = kernelMeta["call_args"]; + const Json::Value providedArgs = root["args"]; + if (expectedArgs.isArray()) { + if (!providedArgs.isObject()) { + if (expectedArgs.size() != 0) { + callRejected = true; + callRejectReason = "missing_args_object"; + emuExecDebug("call", "manifest validation failed: missing args object, expected " + + std::to_string(expectedArgs.size()) + " args"); + } + } else { + size_t providedArgCount = 0; + for (const auto& memberName : providedArgs.getMemberNames()) { + if (memberName.rfind("arg", 0) == 0) { + providedArgCount += 1; + } + } + emuExecDebug("call", "arg count provided=" + std::to_string(providedArgCount) + + " expected=" + std::to_string(expectedArgs.size())); + if (providedArgCount != static_cast(expectedArgs.size())) { + callRejected = true; + callRejectReason = "arg_count_mismatch"; + emuExecDebug("call", "manifest validation failed: arg_count_mismatch"); + } + } + + if (!callRejected) { + for (const auto& spec : expectedArgs) { + if (!spec.isObject()) continue; + std::string argKey = spec.get("arg", "").asString(); + std::string expectedKind = spec.get("kind", "").asString(); + if (argKey.empty()) continue; + emuExecDebug("call", "validating " + argKey + " expectedKind=" + expectedKind); + if (!providedArgs.isObject() || !providedArgs.isMember(argKey) || !providedArgs[argKey].isObject()) { + callRejected = true; + callRejectReason = "missing_" + argKey; + emuExecDebug("call", "manifest validation failed: missing arg object for " + argKey); + break; + } + std::string actualKind = providedArgs[argKey].get("type", "").asString(); + emuExecDebug("call", argKey + " actualKind=" + actualKind + + " payload=" + emuJsonString(providedArgs[argKey])); + if (!expectedKind.empty() && actualKind != expectedKind) { + callRejected = true; + callRejectReason = "arg_kind_mismatch_" + argKey; + emuExecDebug("call", "manifest validation failed: arg kind mismatch for " + argKey); + break; + } + } + } + } + } + } + } + + if (callRejected) { + emuExecLog("call", "rejecting call to '" + functionName + "': " + callRejectReason); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + continue; + } + + bool handledCall = false; + std::function invokeCall; + +{% for fc in function_calls %} + if (functionName == "{{ fc.inst }}") { + handledCall = true; + emuExecDebug("call", "dispatch -> instance='{{ fc.inst }}' top='{{ fc.top }}'"); +{% for line in fc.decode_blocks %} + {{ line }} +{% endfor %} + invokeCall = [&]() { + {{ fc.top }}({{ fc.call_args | join(", ") }}); + emuExecDebug("call", "completed instance='{{ fc.inst }}'"); + }; + } +{% endfor %} + + if (handledCall) { + auto invokeCallTracked = [ + invokeCall, + functionName, + &refreshKernelRegisterShadowFromManifest, + &setKernelCtrlCompleted + ]() { + invokeCall(); + refreshKernelRegisterShadowFromManifest(functionName, true); + setKernelCtrlCompleted(functionName); + }; + + if (isAsyncStart) { + auto activeIt = activeCallFutures.find(functionName); + if (activeIt != activeCallFutures.end()) { + if (activeIt->second.valid() + && activeIt->second.wait_for(std::chrono::milliseconds(0)) != std::future_status::ready) { + emuExecLog("call", "rejecting async start for busy kernel '" + functionName + "'"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + continue; + } + if (activeIt->second.valid()) { + try { + activeIt->second.get(); + } catch (const std::exception& e) { + emuExecLog("call", std::string("prior async kernel '") + functionName + + "' completed with error before restart: " + e.what()); + } catch (...) { + emuExecLog("call", std::string("prior async kernel '") + functionName + + "' completed with unknown error before restart"); + } + } + activeCallFutures.erase(activeIt); + } + + try { + setKernelCtrlRunning(functionName); + refreshKernelRegisterShadowFromManifest(functionName, false); + activeCallFutures[functionName] = std::async(std::launch::async, invokeCallTracked); + emuExecDebug("call", "launched async instance='" + functionName + "'"); + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + } catch (const std::exception& e) { + emuExecLog("call", std::string("async launch failed for '") + functionName + "': " + e.what()); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } catch (...) { + emuExecLog("call", std::string("async launch failed for '") + functionName + "' (unknown error)"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } + } else { + try { + setKernelCtrlRunning(functionName); + refreshKernelRegisterShadowFromManifest(functionName, false); + invokeCallTracked(); + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + } catch (const std::exception& e) { + emuExecLog("call", std::string("call failed for '") + functionName + "': " + e.what()); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } catch (...) { + emuExecLog("call", std::string("call failed for '") + functionName + "' (unknown error)"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } + } + } else { + emuExecLog("call", "unknown call target '" + functionName + "'"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } + } else if (command == "wait") { + std::string functionName = root["function"].asString(); + emuExecDebug("wait", "function=" + functionName); + auto activeIt = activeCallFutures.find(functionName); + if (activeIt == activeCallFutures.end() || !activeIt->second.valid()) { + emuExecDebug("wait", "no active async call for '" + functionName + "' (no-op)"); + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + continue; + } + + try { + activeIt->second.get(); + activeCallFutures.erase(activeIt); + emuExecDebug("wait", "completed async wait for '" + functionName + "'"); + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + } catch (const std::exception& e) { + activeCallFutures.erase(activeIt); + emuExecLog("wait", std::string("async kernel '") + functionName + "' failed: " + e.what()); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } catch (...) { + activeCallFutures.erase(activeIt); + emuExecLog("wait", std::string("async kernel '") + functionName + "' failed (unknown error)"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } + } else if (command == "read_register") { + Json::Value response; + std::string functionName = root["function"].asString(); + const Json::Value offsetVal = root["offset"]; + if (!offsetVal.isUInt() && !offsetVal.isInt()) { + emuExecLog("read_register", "invalid or missing offset"); + response["error"] = "invalid_offset"; + } else { + const uint32_t offset = static_cast(offsetVal.asUInt()); + std::lock_guard lock(kernelRegisterShadowMutex); + auto kernelIt = kernelRegisterShadow.find(functionName); + if (kernelIt == kernelRegisterShadow.end()) { + emuExecLog("read_register", "unknown function '" + functionName + "'"); + response["error"] = "unknown_function"; + response["function"] = functionName; + } else { + auto regIt = kernelIt->second.find(offset); + if (regIt == kernelIt->second.end()) { + emuExecLog("read_register", "unknown register offset for '" + functionName + + "' offset=0x" + std::to_string(offset)); + response["error"] = "unknown_register"; + response["function"] = functionName; + response["offset"] = offset; + } else { + response = Json::Value(static_cast(regIt->second)); + emuExecDebug("read_register", "function=" + functionName + + " offset=0x" + std::to_string(offset) + + " value=" + emuJsonString(response)); + } + } + } + + std::string responseStr = Json::writeString(Json::StreamWriterBuilder(), response); + socket.send(zmq::message_t(responseStr.c_str(), responseStr.size()), zmq::send_flags::none); + } else if (command == "fetch") { + std::string type = root["type"].asString(); + Json::Value response; + emuExecDebug("fetch", "type=" + type); + + if (type == "scalar") { + std::string functionName = root["function"].asString(); + std::string arg = root["arg"].asString(); + bool hasOffsetHint = root.isMember("offset") && root["offset"].isUInt(); + Json::UInt offsetHint = hasOffsetHint ? root["offset"].asUInt() : 0; + bool handledScalar = false; + bool manifestRouteMatched = false; + emuExecDebug("fetch", "scalar function=" + functionName + " arg=" + arg); + + if (emuManifestHasFetchMetadata) { + const Json::Value fetchRoutes = emuManifest["fetch"]["scalar"]; + if (fetchRoutes.isArray()) { + for (const auto& route : fetchRoutes) { + if (!route.isObject()) continue; + if (route.get("function", "").asString() != functionName) continue; + if (route.get("arg", "").asString() != arg) continue; + if (hasOffsetHint) { + const Json::Value source = route["source"]; + if (!source.isObject() || !source.isMember("register_offset") + || !source["register_offset"].isUInt()) { + continue; + } + if (source["register_offset"].asUInt() != offsetHint) { + continue; + } + } + manifestRouteMatched = true; + emuExecDebug("fetch", "manifest route match " + emuJsonString(route)); + + std::string kind = route.get("kind", "").asString(); + if (kind == "var") { + std::string symbol = route.get("var_symbol", "").asString(); + auto it = fetchScalarRegistry.find(symbol); + if (it != fetchScalarRegistry.end()) { + response = it->second(); + handledScalar = true; + emuExecDebug("fetch", "manifest var route resolved symbol=" + symbol + + " value=" + emuJsonString(response)); + break; + } else { + emuExecLog("fetch", "manifest route matched but symbol missing from fetchScalarRegistry: " + symbol); + } + } else if (kind == "var_u32_hi") { + std::string symbol = route.get("var_symbol", "").asString(); + auto it = fetchScalarHiRegistry.find(symbol); + if (it != fetchScalarHiRegistry.end()) { + response = it->second(); + handledScalar = true; + emuExecDebug("fetch", "manifest var_u32_hi route resolved symbol=" + symbol + + " value=" + emuJsonString(response)); + break; + } else { + emuExecLog("fetch", "manifest route matched but symbol missing from fetchScalarHiRegistry: " + symbol); + } + } else if (kind == "const_u32") { + response = Json::Value(static_cast(route.get("value", 0).asUInt())); + handledScalar = true; + emuExecDebug("fetch", "manifest const_u32 route value=" + emuJsonString(response)); + break; + } else { + emuExecLog("fetch", "manifest route matched but kind unsupported: " + kind); + break; + } + } + if (!manifestRouteMatched) { + emuExecDebug("fetch", "no manifest route matched scalar fetch request"); + } + } + } + + if (!handledScalar) { + emuExecLog("fetch", "scalar fetch unresolved in manifest"); + response["error"] = "scalar_fetch_unresolved"; + response["function"] = functionName; + response["arg"] = arg; + if (hasOffsetHint) { + response["offset"] = offsetHint; + } + } + } else if (type == "buffer") { + std::string name = root["name"].asString(); + emuExecDebug("fetch", "buffer name=" + name); + if (buffers.find(name) != buffers.end()) { + response = createJsonBuffer(static_cast(buffers[name]), bufferSizes[name]); + emuExecDebug("fetch", "buffer fetch hit name=" + name + " bytes=" + std::to_string(bufferSizes[name])); + } else { + emuExecLog("fetch", "buffer fetch miss for name=" + name); + } + } else { + emuExecLog("fetch", "unsupported fetch type=" + type); + } + + std::string responseStr = Json::writeString(Json::StreamWriterBuilder(), response); + emuExecDebug("fetch", "reply=" + responseStr); + socket.send(zmq::message_t(responseStr.c_str(), responseStr.size()), zmq::send_flags::none); + } else if (command == "exit") { + emuExecLog("exit", std::string("received exit; fast_exit=") + (requireFastExitOnExit ? "true" : "false")); + socket.send(zmq::message_t("OK", 2), zmq::send_flags::none); + if (requireFastExitOnExit) { + // Free-running autostart kernels (e.g. ap_ctrl_none stream-only kernels) + // run in detached threads and may never return. Exiting main() would destroy + // local hls::stream objects while those threads are still active. + std::this_thread::sleep_for(std::chrono::milliseconds(1)); + emuExecLog("exit", "terminating via std::_Exit(0)"); + std::_Exit(0); + } + emuExecDebug("exit", "clean shutdown via return path"); + break; + } else { + emuExecLog("request", "unknown command '" + command + "'"); + socket.send(zmq::message_t("ERR", 3), zmq::send_flags::none); + } + } + + emuExecDebug("shutdown", "main() returning"); + return 0; +} diff --git a/linker/slashkit/resources/templates/system_map.xml b/linker/slashkit/resources/templates/system_map.xml new file mode 100644 index 00000000..4904d12d --- /dev/null +++ b/linker/slashkit/resources/templates/system_map.xml @@ -0,0 +1,36 @@ + + {{ platform }} + {{ clock_hz }} + + +{% for idx in service_layer.eth_indices %} + +{% endfor %} + + +{% for v in service_layer.virt %} + +{% endfor %} + + +{% for k in kernels %} + + {{ k.name }} + {{ k.base_addr }} + {{ k.range }} +{% for r in k.registers %} + +{% endfor %} +{% if k.functional_args %} + +{% for a in k.functional_args %} + +{% endfor %} + +{% endif %} +{% for c in k.connections %} + +{% endfor %} + +{% endfor %} + diff --git a/linker/test/__init__.py b/linker/test/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/test/fixtures/dma_in/hls/hls_data.json b/linker/test/fixtures/dma_in/hls/hls_data.json new file mode 100644 index 00000000..ba3dcc26 --- /dev/null +++ b/linker/test/fixtures/dma_in/hls/hls_data.json @@ -0,0 +1,851 @@ +{ + "Top": "dma_in", + "RtlTop": "dma_in", + "RtlPrefix": "", + "RtlSubPrefix": "dma_in_", + "SourceLanguage": "cpp", + "HostMachineBits": "64", + "FunctionProtocol": "ap_ctrl_hs", + "ResetStyle": "control", + "Target": { + "Family": "versal", + "Device": "xcv80", + "Package": "-lsva4737", + "Speed": "-2MHP-e-S", + "Triple": "fpga64-xilinx-none" + }, + "Args": { + "in": { + "index": "0", + "direction": "in", + "srcType": "ap_uint<64>*", + "srcSize": "64", + "hwRefs": [ + { + "type": "interface", + "interface": "m_axi_gmem0", + "name": "", + "usage": "data", + "direction": "in" + }, + { + "type": "register", + "interface": "s_axi_control", + "name": "in_r_1", + "usage": "address", + "direction": "in" + }, + { + "type": "register", + "interface": "s_axi_control", + "name": "in_r_2", + "usage": "address", + "direction": "in" + } + ] + }, + "axis_out": { + "index": "1", + "direction": "out", + "srcType": "stream, 0>&", + "srcSize": "64", + "hwRefs": [{ + "type": "interface", + "interface": "axis_out", + "name": "", + "usage": "data", + "direction": "out" + }] + }, + "size": { + "index": "2", + "direction": "in", + "srcType": "ap_uint<32>", + "srcSize": "32", + "hwRefs": [{ + "type": "register", + "interface": "s_axi_control", + "name": "size", + "usage": "data", + "direction": "in" + }] + } + }, + "HlsSolution": { + "FlowTarget": "vivado", + "ConfigTcl": [ + "config_export -format=ip_catalog", + "config_export -flow=none" + ], + "ProfileOption": "0", + "ProfileType": "none", + "KernelName": "dma_in" + }, + "ClockInfo": { + "ClockName": "ap_clk", + "ClockPeriod": "2", + "Uncertainty": "0.54", + "IsCombinational": "0", + "II": "0", + "Latency": "undef" + }, + "Xdc": {"OocClocks": ["create_clock -name ap_clk -period 2.000 [get_ports ap_clk]"]}, + "Ipx": { + "Vendor": "xilinx.com", + "Library": "hls", + "Name": "dma_in", + "Version": "1.0", + "DisplayName": "Dma_in", + "Revision": "2114517586", + "Description": "An IP generated by Vitis HLS", + "Taxonomy": "\/VITIS_HLS_IP", + "AutoFamilySupport": "", + "ZipFile": "xilinx_com_hls_dma_in_1_0.zip" + }, + "Files": { + "CSource": [], + "Vhdl": [], + "Verilog": [], + "SwDriver": [], + "IpMisc": [], + "DebugDir": ".debug", + "Xo": "", + "XoHlsDir": "", + "ProtoInst": [""] + }, + "SubcoreInfo": { + "HasXpmMemory": false, + "HasClockedDsp": false, + "Ip": [ + + ] + }, + "Interfaces": { + "s_axi_control": { + "type": "axi4lite", + "busTypeName": "aximm", + "mode": "slave", + "dataWidth": "32", + "addrWidth": "6", + "portPrefix": "s_axi_control_", + "paramPrefix": "C_S_AXI_CONTROL_", + "offsetMasterName": "m_axi_gmem0", + "ports": [ + "s_axi_control_ARADDR", + "s_axi_control_ARREADY", + "s_axi_control_ARVALID", + "s_axi_control_AWADDR", + "s_axi_control_AWREADY", + "s_axi_control_AWVALID", + "s_axi_control_BREADY", + "s_axi_control_BRESP", + "s_axi_control_BVALID", + "s_axi_control_RDATA", + "s_axi_control_RREADY", + "s_axi_control_RRESP", + "s_axi_control_RVALID", + "s_axi_control_WDATA", + "s_axi_control_WREADY", + "s_axi_control_WSTRB", + "s_axi_control_WVALID" + ], + "registers": [ + { + "offset": "0x00", + "name": "CTRL", + "access": "RW", + "description": "Control signals", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "AP_START", + "access": "RW", + "description": "Control signal Register for 'ap_start'." + }, + { + "offset": "1", + "width": "1", + "name": "AP_DONE", + "access": "R", + "description": "Control signal Register for 'ap_done'." + }, + { + "offset": "2", + "width": "1", + "name": "AP_IDLE", + "access": "R", + "description": "Control signal Register for 'ap_idle'." + }, + { + "offset": "3", + "width": "1", + "name": "AP_READY", + "access": "R", + "description": "Control signal Register for 'ap_ready'." + }, + { + "offset": "4", + "width": "3", + "name": "RESERVED_1", + "access": "R", + "description": "Reserved. 0s on read." + }, + { + "offset": "7", + "width": "1", + "name": "AUTO_RESTART", + "access": "RW", + "description": "Control signal Register for 'auto_restart'." + }, + { + "offset": "8", + "width": "1", + "name": "RESERVED_2", + "access": "R", + "description": "Reserved. 0s on read." + }, + { + "offset": "9", + "width": "1", + "name": "INTERRUPT", + "access": "R", + "description": "Control signal Register for 'interrupt'." + }, + { + "offset": "10", + "width": "22", + "name": "RESERVED_3", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x04", + "name": "GIER", + "access": "RW", + "description": "Global Interrupt Enable Register", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "Enable", + "access": "RW", + "description": "Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled" + }, + { + "offset": "1", + "width": "31", + "name": "RESERVED", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x08", + "name": "IP_IER", + "access": "RW", + "description": "IP Interrupt Enable Register", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "CHAN0_INT_EN", + "access": "RW", + "description": "Enable Channel 0 (ap_done) Interrupt. 0 = Disabled, 1 = Enabled." + }, + { + "offset": "1", + "width": "1", + "name": "CHAN1_INT_EN", + "access": "RW", + "description": "Enable Channel 1 (ap_ready) Interrupt. 0 = Disabled, 1 = Enabled." + }, + { + "offset": "2", + "width": "30", + "name": "RESERVED_0", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x0c", + "name": "IP_ISR", + "access": "RW", + "description": "IP Interrupt Status Register", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "CHAN0_INT_ST", + "access": "RTOW", + "description": "Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 interrupt, 1 = Channel 0 interrupt." + }, + { + "offset": "1", + "width": "1", + "name": "CHAN1_INT_ST", + "access": "RTOW", + "description": "Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 interrupt, 1 = Channel 1 interrupt." + }, + { + "offset": "2", + "width": "30", + "name": "RESERVED_0", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x10", + "name": "in_r_1", + "access": "W", + "description": "Data signal of in_r", + "range": "32", + "fields": [{ + "offset": "0", + "width": "32", + "name": "in_r", + "access": "W", + "description": "Bit 31 to 0 of in_r" + }] + }, + { + "offset": "0x14", + "name": "in_r_2", + "access": "W", + "description": "Data signal of in_r", + "range": "32", + "fields": [{ + "offset": "0", + "width": "32", + "name": "in_r", + "access": "W", + "description": "Bit 63 to 32 of in_r" + }] + }, + { + "offset": "0x1c", + "name": "size", + "access": "W", + "description": "Data signal of size", + "range": "32", + "fields": [{ + "offset": "0", + "width": "32", + "name": "size", + "access": "W", + "description": "Bit 31 to 0 of size" + }] + } + ], + "constraints": [ + { + "constraint_type": "pragma interface", + "mode": "s_axilite", + "register_option": "0", + "offset": "16", + "argName": "in" + }, + { + "constraint_type": "pragma interface", + "mode": "s_axilite", + "register_option": "0", + "offset": "28", + "argName": "size" + } + ] + }, + "ap_clk": { + "type": "clock", + "busTypeName": "clock", + "mode": "slave", + "busParams": { + "ASSOCIATED_BUSIF": "s_axi_control:axis_out:m_axi_gmem0", + "ASSOCIATED_RESET": "ap_rst_n" + }, + "portMap": {"ap_clk": "CLK"}, + "ports": ["ap_clk"] + }, + "ap_rst_n": { + "type": "reset", + "busTypeName": "reset", + "mode": "slave", + "busParams": {"POLARITY": "ACTIVE_LOW"}, + "portMap": {"ap_rst_n": "RST"}, + "ports": ["ap_rst_n"] + }, + "interrupt": { + "type": "interrupt", + "busTypeName": "interrupt", + "mode": "master", + "dataWidth": "1", + "busParams": {"SENSITIVITY": "LEVEL_HIGH"}, + "portMap": {"interrupt": "INTERRUPT"}, + "ports": ["interrupt"] + }, + "axis_out": { + "type": "axi4stream", + "busTypeName": "axis", + "mode": "master", + "direction": "out", + "dataWidth": "64", + "portPrefix": "axis_out_", + "ports": [ + "axis_out_TDATA", + "axis_out_TREADY", + "axis_out_TVALID" + ], + "constraints": [{ + "constraint_type": "pragma interface", + "mode": "axis", + "register_option": "1", + "register_mode": "both", + "argName": "axis_out" + }] + }, + "m_axi_gmem0": { + "type": "axi4full", + "busTypeName": "aximm", + "mode": "master", + "dataWidth": "64", + "addrWidth": "64", + "portPrefix": "m_axi_gmem0_", + "paramPrefix": "C_M_AXI_GMEM0_", + "offsetSlaveName": "s_axi_control", + "preferredUsageValue": "MEMORY", + "busParams": { + "NUM_READ_OUTSTANDING": "16", + "NUM_WRITE_OUTSTANDING": "16", + "MAX_READ_BURST_LENGTH": "16", + "MAX_WRITE_BURST_LENGTH": "16", + "MAX_BURST_LENGTH": "256", + "PROTOCOL": "AXI4", + "READ_WRITE_MODE": "READ_ONLY", + "HAS_BURST": "0", + "SUPPORTS_NARROW_BURST": "0" + }, + "ports": [ + "m_axi_gmem0_ARADDR", + "m_axi_gmem0_ARBURST", + "m_axi_gmem0_ARCACHE", + "m_axi_gmem0_ARID", + "m_axi_gmem0_ARLEN", + "m_axi_gmem0_ARLOCK", + "m_axi_gmem0_ARPROT", + "m_axi_gmem0_ARQOS", + "m_axi_gmem0_ARREADY", + "m_axi_gmem0_ARREGION", + "m_axi_gmem0_ARSIZE", + "m_axi_gmem0_ARUSER", + "m_axi_gmem0_ARVALID", + "m_axi_gmem0_AWADDR", + "m_axi_gmem0_AWBURST", + "m_axi_gmem0_AWCACHE", + "m_axi_gmem0_AWID", + "m_axi_gmem0_AWLEN", + "m_axi_gmem0_AWLOCK", + "m_axi_gmem0_AWPROT", + "m_axi_gmem0_AWQOS", + "m_axi_gmem0_AWREADY", + "m_axi_gmem0_AWREGION", + "m_axi_gmem0_AWSIZE", + "m_axi_gmem0_AWUSER", + "m_axi_gmem0_AWVALID", + "m_axi_gmem0_BID", + "m_axi_gmem0_BREADY", + "m_axi_gmem0_BRESP", + "m_axi_gmem0_BUSER", + "m_axi_gmem0_BVALID", + "m_axi_gmem0_RDATA", + "m_axi_gmem0_RID", + "m_axi_gmem0_RLAST", + "m_axi_gmem0_RREADY", + "m_axi_gmem0_RRESP", + "m_axi_gmem0_RUSER", + "m_axi_gmem0_RVALID", + "m_axi_gmem0_WDATA", + "m_axi_gmem0_WID", + "m_axi_gmem0_WLAST", + "m_axi_gmem0_WREADY", + "m_axi_gmem0_WSTRB", + "m_axi_gmem0_WUSER", + "m_axi_gmem0_WVALID" + ], + "constraints": [ + { + "constraint_type": "pragma interface", + "mode": "m_axi", + "register_option": "0", + "offset": "slave", + "latency": "0", + "num_read_outstanding": "16", + "num_write_outstanding": "16", + "max_read_burst_length": "16", + "max_write_burst_length": "16", + "max_widen_bitwidth": "64", + "channel_id": "0", + "argName": "in" + }, + { + "constraint_type": "bitwidth", + "orig_bitwidth": "64", + "final_bitwidth": "64", + "argName": "in" + } + ] + } + }, + "RtlPorts": { + "s_axi_control_AWVALID": { + "dir": "in", + "width": "1" + }, + "s_axi_control_AWREADY": { + "dir": "out", + "width": "1" + }, + "s_axi_control_AWADDR": { + "dir": "in", + "width": "6" + }, + "s_axi_control_WVALID": { + "dir": "in", + "width": "1" + }, + "s_axi_control_WREADY": { + "dir": "out", + "width": "1" + }, + "s_axi_control_WDATA": { + "dir": "in", + "width": "32" + }, + "s_axi_control_WSTRB": { + "dir": "in", + "width": "4" + }, + "s_axi_control_ARVALID": { + "dir": "in", + "width": "1" + }, + "s_axi_control_ARREADY": { + "dir": "out", + "width": "1" + }, + "s_axi_control_ARADDR": { + "dir": "in", + "width": "6" + }, + "s_axi_control_RVALID": { + "dir": "out", + "width": "1" + }, + "s_axi_control_RREADY": { + "dir": "in", + "width": "1" + }, + "s_axi_control_RDATA": { + "dir": "out", + "width": "32" + }, + "s_axi_control_RRESP": { + "dir": "out", + "width": "2" + }, + "s_axi_control_BVALID": { + "dir": "out", + "width": "1" + }, + "s_axi_control_BREADY": { + "dir": "in", + "width": "1" + }, + "s_axi_control_BRESP": { + "dir": "out", + "width": "2" + }, + "ap_clk": { + "dir": "in", + "width": "1" + }, + "ap_rst_n": { + "dir": "in", + "width": "1" + }, + "interrupt": { + "dir": "out", + "width": "1" + }, + "axis_out_TREADY": { + "dir": "in", + "width": "1" + }, + "axis_out_TDATA": { + "dir": "out", + "width": "64" + }, + "axis_out_TVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_AWVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_AWREADY": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_AWADDR": { + "dir": "out", + "width": "64" + }, + "m_axi_gmem0_AWID": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_AWLEN": { + "dir": "out", + "width": "8" + }, + "m_axi_gmem0_AWSIZE": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_AWBURST": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_AWLOCK": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_AWCACHE": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_AWPROT": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_AWQOS": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_AWREGION": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_AWUSER": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_WVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_WREADY": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_WDATA": { + "dir": "out", + "width": "64" + }, + "m_axi_gmem0_WSTRB": { + "dir": "out", + "width": "8" + }, + "m_axi_gmem0_WLAST": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_WID": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_WUSER": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_ARVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_ARREADY": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_ARADDR": { + "dir": "out", + "width": "64" + }, + "m_axi_gmem0_ARID": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_ARLEN": { + "dir": "out", + "width": "8" + }, + "m_axi_gmem0_ARSIZE": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_ARBURST": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_ARLOCK": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_ARCACHE": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_ARPROT": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_ARQOS": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_ARREGION": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_ARUSER": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_RVALID": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_RREADY": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_RDATA": { + "dir": "in", + "width": "64" + }, + "m_axi_gmem0_RLAST": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_RID": { + "dir": "in", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_RUSER": { + "dir": "in", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_RRESP": { + "dir": "in", + "width": "2" + }, + "m_axi_gmem0_BVALID": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_BREADY": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_BRESP": { + "dir": "in", + "width": "2" + }, + "m_axi_gmem0_BID": { + "dir": "in", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_BUSER": { + "dir": "in", + "width": "1", + "isVector": "true" + } + }, + "ModuleInfo": { + "Hierarchy": { + "ModuleName": "dma_in", + "BindInstances": "icmp_ln30_fu_133_p2 add_ln30_fu_139_p2 control_s_axi_U gmem0_m_axi_U" + }, + "Info": {"dma_in": { + "FunctionProtocol": "ap_ctrl_hs", + "isTaskLevelControl": "0", + "isPipelined": "0", + "isCombinational": "0", + "isOneStateSeq": "0" + }}, + "Metrics": {"dma_in": { + "Latency": { + "LatencyBest": "", + "LatencyAvg": "", + "LatencyWorst": "", + "PipelineII": "0", + "PipelineDepth": "", + "PipelineType": "loop auto-rewind stp (delay=0 clock cycles(s))" + }, + "Timing": { + "Target": "2.00", + "Uncertainty": "0.54", + "Estimate": "2.130" + }, + "Loops": [{ + "Name": "VITIS_LOOP_30_1", + "TripCount": "", + "Latency": "", + "PipelineII": "1", + "PipelineDepth": "14" + }], + "Area": { + "BRAM_18K": "2", + "AVAIL_BRAM": "7482", + "UTIL_BRAM": "~0", + "FF": "1582", + "AVAIL_FF": "5148416", + "UTIL_FF": "~0", + "LUT": "1088", + "AVAIL_LUT": "2574208", + "UTIL_LUT": "~0", + "URAM": "0", + "AVAIL_URAM": "1925", + "UTIL_URAM": "0", + "DSP": "0", + "AVAIL_DSP": "10848", + "UTIL_DSP": "0" + } + }} + }, + "GenerateBdFiles": "0", + "GenData": { + "DataVersion": "0.2", + "Time": "2026-03-12 09:46:22 GMT", + "ToolName": "vitis_hls", + "ToolVersion": "2025.1" + } +} diff --git a/linker/test/fixtures/dma_in/hls/impl/ip/component.xml b/linker/test/fixtures/dma_in/hls/impl/ip/component.xml new file mode 100644 index 00000000..4307f8f6 --- /dev/null +++ b/linker/test/fixtures/dma_in/hls/impl/ip/component.xml @@ -0,0 +1,2638 @@ + + + xilinx.com + hls + dma_in + 1.0 + + + s_axi_control + + + + + + + + + ARADDR + + + s_axi_control_ARADDR + + + + + ARREADY + + + s_axi_control_ARREADY + + + + + ARVALID + + + s_axi_control_ARVALID + + + + + AWADDR + + + s_axi_control_AWADDR + + + + + AWREADY + + + s_axi_control_AWREADY + + + + + AWVALID + + + s_axi_control_AWVALID + + + + + BREADY + + + s_axi_control_BREADY + + + + + BRESP + + + s_axi_control_BRESP + + + + + BVALID + + + s_axi_control_BVALID + + + + + RDATA + + + s_axi_control_RDATA + + + + + RREADY + + + s_axi_control_RREADY + + + + + RRESP + + + s_axi_control_RRESP + + + + + RVALID + + + s_axi_control_RVALID + + + + + WDATA + + + s_axi_control_WDATA + + + + + WREADY + + + s_axi_control_WREADY + + + + + WSTRB + + + s_axi_control_WSTRB + + + + + WVALID + + + s_axi_control_WVALID + + + + + + ADDR_WIDTH + 6 + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE + + + + + ap_clk + + + + + + + CLK + + + ap_clk + + + + + + ASSOCIATED_BUSIF + s_axi_control:axis_out:m_axi_gmem0 + + + ASSOCIATED_RESET + ap_rst_n + + + + + ap_rst_n + + + + + + + RST + + + ap_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + interrupt + + + + + + + INTERRUPT + + + interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + axis_out + + + + + + + TDATA + + + axis_out_TDATA + + + + + TREADY + + + axis_out_TREADY + + + + + TVALID + + + axis_out_TVALID + + + + + + TUSER_WIDTH + 0 + + + TDATA_NUM_BYTES + 8 + + + + + m_axi_gmem0 + + + + + + + + + ARADDR + + + m_axi_gmem0_ARADDR + + + + + ARBURST + + + m_axi_gmem0_ARBURST + + + + + ARCACHE + + + m_axi_gmem0_ARCACHE + + + + + ARID + + + m_axi_gmem0_ARID + + + + + ARLEN + + + m_axi_gmem0_ARLEN + + + + + ARLOCK + + + m_axi_gmem0_ARLOCK + + + + + ARPROT + + + m_axi_gmem0_ARPROT + + + + + ARQOS + + + m_axi_gmem0_ARQOS + + + + + ARREADY + + + m_axi_gmem0_ARREADY + + + + + ARREGION + + + m_axi_gmem0_ARREGION + + + + + ARSIZE + + + m_axi_gmem0_ARSIZE + + + + + ARUSER + + + m_axi_gmem0_ARUSER + + + + + ARVALID + + + m_axi_gmem0_ARVALID + + + + + AWADDR + + + m_axi_gmem0_AWADDR + + + + + AWBURST + + + m_axi_gmem0_AWBURST + + + + + AWCACHE + + + m_axi_gmem0_AWCACHE + + + + + AWID + + + m_axi_gmem0_AWID + + + + + AWLEN + + + m_axi_gmem0_AWLEN + + + + + AWLOCK + + + m_axi_gmem0_AWLOCK + + + + + AWPROT + + + m_axi_gmem0_AWPROT + + + + + AWQOS + + + m_axi_gmem0_AWQOS + + + + + AWREADY + + + m_axi_gmem0_AWREADY + + + + + AWREGION + + + m_axi_gmem0_AWREGION + + + + + AWSIZE + + + m_axi_gmem0_AWSIZE + + + + + AWUSER + + + m_axi_gmem0_AWUSER + + + + + AWVALID + + + m_axi_gmem0_AWVALID + + + + + BID + + + m_axi_gmem0_BID + + + + + BREADY + + + m_axi_gmem0_BREADY + + + + + BRESP + + + m_axi_gmem0_BRESP + + + + + BUSER + + + m_axi_gmem0_BUSER + + + + + BVALID + + + m_axi_gmem0_BVALID + + + + + RDATA + + + m_axi_gmem0_RDATA + + + + + RID + + + m_axi_gmem0_RID + + + + + RLAST + + + m_axi_gmem0_RLAST + + + + + RREADY + + + m_axi_gmem0_RREADY + + + + + RRESP + + + m_axi_gmem0_RRESP + + + + + RUSER + + + m_axi_gmem0_RUSER + + + + + RVALID + + + m_axi_gmem0_RVALID + + + + + WDATA + + + m_axi_gmem0_WDATA + + + + + WID + + + m_axi_gmem0_WID + + + + + WLAST + + + m_axi_gmem0_WLAST + + + + + WREADY + + + m_axi_gmem0_WREADY + + + + + WSTRB + + + m_axi_gmem0_WSTRB + + + + + WUSER + + + m_axi_gmem0_WUSER + + + + + WVALID + + + m_axi_gmem0_WVALID + + + + + + NUM_READ_OUTSTANDING + 16 + + + NUM_WRITE_OUTSTANDING + 16 + + + MAX_READ_BURST_LENGTH + 16 + + + MAX_WRITE_BURST_LENGTH + 16 + + + MAX_BURST_LENGTH + 256 + + + PROTOCOL + AXI4 + + + READ_WRITE_MODE + READ_ONLY + + + HAS_BURST + 0 + + + SUPPORTS_NARROW_BURST + 0 + + + ADDR_WIDTH + 64 + + + + + + + Data_m_axi_gmem0 + 16E + 64 + + + DEPENDENT_ON + s_axi_control + + + PREFERRED_USAGE + MEMORY + + + + + + + s_axi_control + + Reg + 0 + 65536 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S_AXI_CONTROL_BASEADDR + + + OFFSET_HIGH_PARAM + C_S_AXI_CONTROL_HIGHADDR + + + + CTRL + CTRL + Control signals + 0 + 32 + read-write + + 0 + + + AP_START + Control signal Register for 'ap_start'. + 0 + 1 + read-write + modify + + 0 + 0 + + false + + + AP_DONE + Control signal Register for 'ap_done'. + 1 + 1 + read-only + + 0 + 0 + + modify + false + + + AP_IDLE + Control signal Register for 'ap_idle'. + 2 + 1 + read-only + + 0 + 0 + + modify + false + + + AP_READY + Control signal Register for 'ap_ready'. + 3 + 1 + read-only + + 0 + 0 + + modify + false + + + RESERVED_1 + Reserved. 0s on read. + 4 + 3 + read-only + + 0 + 0 + + modify + false + + + AUTO_RESTART + Control signal Register for 'auto_restart'. + 7 + 1 + read-write + modify + + 0 + 0 + + false + + + RESERVED_2 + Reserved. 0s on read. + 8 + 1 + read-only + + 0 + 0 + + modify + false + + + INTERRUPT + Control signal Register for 'interrupt'. + 9 + 1 + read-only + + 0 + 0 + + modify + false + + + RESERVED_3 + Reserved. 0s on read. + 10 + 22 + read-only + + 0 + 0 + + modify + false + + + + GIER + GIER + Global Interrupt Enable Register + 4 + 32 + read-write + + 0 + + + Enable + Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled + 0 + 1 + read-write + modify + + 0 + 0 + + false + + + RESERVED + Reserved. 0s on read. + 1 + 31 + read-only + + 0 + 0 + + modify + false + + + + IP_IER + IP_IER + IP Interrupt Enable Register + 8 + 32 + read-write + + 0 + + + CHAN0_INT_EN + Enable Channel 0 (ap_done) Interrupt. 0 = Disabled, 1 = Enabled. + 0 + 1 + read-write + modify + + 0 + 0 + + false + + + CHAN1_INT_EN + Enable Channel 1 (ap_ready) Interrupt. 0 = Disabled, 1 = Enabled. + 1 + 1 + read-write + modify + + 0 + 0 + + false + + + RESERVED_0 + Reserved. 0s on read. + 2 + 30 + read-only + + 0 + 0 + + modify + false + + + + IP_ISR + IP_ISR + IP Interrupt Status Register + 12 + 32 + read-write + + 0 + + + CHAN0_INT_ST + Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 interrupt, 1 = Channel 0 interrupt. + 0 + 1 + read-only + oneToToggle + + 0 + 0 + + modify + false + + + CHAN1_INT_ST + Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 interrupt, 1 = Channel 1 interrupt. + 1 + 1 + read-only + oneToToggle + + 0 + 0 + + modify + false + + + RESERVED_0 + Reserved. 0s on read. + 2 + 30 + read-only + + 0 + 0 + + modify + false + + + + in_r_1 + in_r_1 + Data signal of in_r + 16 + 32 + write-only + + 0 + + + in_r + Bit 31 to 0 of in_r + 0 + 32 + write-only + + 0 + 0 + + false + + + + in_r_2 + in_r_2 + Data signal of in_r + 20 + 32 + write-only + + 0 + + + in_r + Bit 63 to 32 of in_r + 0 + 32 + write-only + + 0 + 0 + + false + + + + size + size + Data signal of size + 28 + 32 + write-only + + 0 + + + size + Bit 31 to 0 of size + 0 + 32 + write-only + + 0 + 0 + + false + + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + dma_in + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + b80d0b0a + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + dma_in + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 5b148322 + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + dma_in + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + a3745c1f + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + dma_in + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 114e20b0 + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + c821f584 + + + + + xilinx_documentation + Documentation + :vivado.xilinx.com:docs.all + + xilinx_documentation_view_fileset + + + + xilinx_miscfiles + Miscellaneous + :vivado.xilinx.com:misc.files + + xilinx_miscfiles_view_fileset + + + + viewChecksum + 34797a57 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 13f0ffc0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 34797a57 + + + + + + + s_axi_control_ARADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_ARREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_ARVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_AWADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_AWREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_AWVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_BREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_BVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ap_clk + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ap_rst_n + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + interrupt + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_out_TDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_out_TREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_out_TVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARADDR + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_ARLEN + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARREGION + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_gmem0_ARVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWADDR + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_AWLEN + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWREGION + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_gmem0_AWVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_BID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_BREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_BRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_BUSER + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_gmem0_BVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_RLAST + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RUSER + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_gmem0_RVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_WLAST + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WSTRB + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_gmem0_WVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + C_S_AXI_CONTROL_ADDR_WIDTH + 6 + + + C_S_AXI_CONTROL_DATA_WIDTH + 32 + + + C_M_AXI_GMEM0_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_GMEM0_ADDR_WIDTH + 64 + + + C_M_AXI_GMEM0_DATA_WIDTH + 64 + + + C_M_AXI_GMEM0_AWUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_ARUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_WUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_RUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_BUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_USER_VALUE + 0x00000000 + + + + false + + + + + + C_M_AXI_GMEM0_PROT_VALUE + "000" + + + C_M_AXI_GMEM0_CACHE_VALUE + "0011" + + + + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + + + xilinx_verilogsynthesis_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + xilinx_softwaredriver_view_fileset + + + xilinx_documentation_view_fileset + + + xilinx_miscfiles_view_fileset + + + xilinx_xpgui_view_fileset + + + xilinx_utilityxitfiles_view_fileset + + + An IP generated by Vitis HLS + + + C_M_AXI_GMEM0_ENABLE_ID_PORTS + Enable ID ports + true + + + C_M_AXI_GMEM0_ID_WIDTH + ID width + 1 + + + + true + + + + + + C_M_AXI_GMEM0_DATA_WIDTH + Data width + 64 + + + C_M_AXI_GMEM0_ENABLE_USER_PORTS + Enable USER ports + false + + + C_M_AXI_GMEM0_AWUSER_WIDTH + AWUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_WUSER_WIDTH + WUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_BUSER_WIDTH + BUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_ARUSER_WIDTH + ARUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_RUSER_WIDTH + RUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_USER_VALUE + USER value + 0x00000000 + + + + false + + + + + + C_M_AXI_GMEM0_PROT_VALUE + PROT value + "000" + + + C_M_AXI_GMEM0_CACHE_VALUE + CACHE value + "0011" + + + Component_Name + dma_in_v1_0 + + + clk_period + 2 + + + machine + 64 + + + combinational + 0 + + + latency + undef + + + II + 0 + + + + + + versal + + + /VITIS_HLS_IP + + Dma_in + HLS + 2114517586 + 2026-03-12T09:46:34Z + + true + hls + + + + 2025.1 + + + + + + + + + + diff --git a/linker/test/fixtures/dma_out/hls/hls_data.json b/linker/test/fixtures/dma_out/hls/hls_data.json new file mode 100644 index 00000000..707d2e32 --- /dev/null +++ b/linker/test/fixtures/dma_out/hls/hls_data.json @@ -0,0 +1,853 @@ +{ + "Top": "dma_out", + "RtlTop": "dma_out", + "RtlPrefix": "", + "RtlSubPrefix": "dma_out_", + "SourceLanguage": "cpp", + "HostMachineBits": "64", + "FunctionProtocol": "ap_ctrl_hs", + "ResetStyle": "control", + "Target": { + "Family": "versal", + "Device": "xcv80", + "Package": "-lsva4737", + "Speed": "-2MHP-e-S", + "Triple": "fpga64-xilinx-none" + }, + "Args": { + "size": { + "index": "0", + "direction": "in", + "srcType": "ap_uint<32>", + "srcSize": "32", + "hwRefs": [{ + "type": "register", + "interface": "s_axi_control", + "name": "size", + "usage": "data", + "direction": "in" + }] + }, + "axis_in": { + "index": "1", + "direction": "in", + "srcType": "stream, 0>&", + "srcSize": "64", + "hwRefs": [{ + "type": "interface", + "interface": "axis_in", + "name": "", + "usage": "data", + "direction": "in" + }] + }, + "out": { + "index": "2", + "direction": "out", + "srcType": "ap_uint<64>*", + "srcSize": "64", + "hwRefs": [ + { + "type": "interface", + "interface": "m_axi_gmem0", + "name": "", + "usage": "data", + "direction": "out" + }, + { + "type": "register", + "interface": "s_axi_control", + "name": "out_r_1", + "usage": "address", + "direction": "in" + }, + { + "type": "register", + "interface": "s_axi_control", + "name": "out_r_2", + "usage": "address", + "direction": "in" + } + ] + } + }, + "HlsSolution": { + "FlowTarget": "vivado", + "ConfigTcl": [ + "config_export -format=ip_catalog", + "config_export -flow=none" + ], + "ProfileOption": "0", + "ProfileType": "none", + "KernelName": "dma_out" + }, + "ClockInfo": { + "ClockName": "ap_clk", + "ClockPeriod": "2", + "Uncertainty": "0.54", + "IsCombinational": "0", + "II": "0", + "Latency": "undef" + }, + "Xdc": {"OocClocks": ["create_clock -name ap_clk -period 2.000 [get_ports ap_clk]"]}, + "Ipx": { + "Vendor": "xilinx.com", + "Library": "hls", + "Name": "dma_out", + "Version": "1.0", + "DisplayName": "Dma_out", + "Revision": "2114517586", + "Description": "An IP generated by Vitis HLS", + "Taxonomy": "\/VITIS_HLS_IP", + "AutoFamilySupport": "", + "ZipFile": "xilinx_com_hls_dma_out_1_0.zip" + }, + "Files": { + "CSource": [], + "Vhdl": [], + "Verilog": [], + "SwDriver": [], + "IpMisc": [], + "CsynthXml": "", + "DebugDir": ".debug", + "KernelXml": "", + "Xo": "", + "XoHlsDir": "", + "ProtoInst": [""] + }, + "SubcoreInfo": { + "HasXpmMemory": false, + "HasClockedDsp": false, + "Ip": [ + + ] + }, + "Interfaces": { + "s_axi_control": { + "type": "axi4lite", + "busTypeName": "aximm", + "mode": "slave", + "dataWidth": "32", + "addrWidth": "6", + "portPrefix": "s_axi_control_", + "paramPrefix": "C_S_AXI_CONTROL_", + "offsetMasterName": "m_axi_gmem0", + "ports": [ + "s_axi_control_ARADDR", + "s_axi_control_ARREADY", + "s_axi_control_ARVALID", + "s_axi_control_AWADDR", + "s_axi_control_AWREADY", + "s_axi_control_AWVALID", + "s_axi_control_BREADY", + "s_axi_control_BRESP", + "s_axi_control_BVALID", + "s_axi_control_RDATA", + "s_axi_control_RREADY", + "s_axi_control_RRESP", + "s_axi_control_RVALID", + "s_axi_control_WDATA", + "s_axi_control_WREADY", + "s_axi_control_WSTRB", + "s_axi_control_WVALID" + ], + "registers": [ + { + "offset": "0x00", + "name": "CTRL", + "access": "RW", + "description": "Control signals", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "AP_START", + "access": "RW", + "description": "Control signal Register for 'ap_start'." + }, + { + "offset": "1", + "width": "1", + "name": "AP_DONE", + "access": "R", + "description": "Control signal Register for 'ap_done'." + }, + { + "offset": "2", + "width": "1", + "name": "AP_IDLE", + "access": "R", + "description": "Control signal Register for 'ap_idle'." + }, + { + "offset": "3", + "width": "1", + "name": "AP_READY", + "access": "R", + "description": "Control signal Register for 'ap_ready'." + }, + { + "offset": "4", + "width": "3", + "name": "RESERVED_1", + "access": "R", + "description": "Reserved. 0s on read." + }, + { + "offset": "7", + "width": "1", + "name": "AUTO_RESTART", + "access": "RW", + "description": "Control signal Register for 'auto_restart'." + }, + { + "offset": "8", + "width": "1", + "name": "RESERVED_2", + "access": "R", + "description": "Reserved. 0s on read." + }, + { + "offset": "9", + "width": "1", + "name": "INTERRUPT", + "access": "R", + "description": "Control signal Register for 'interrupt'." + }, + { + "offset": "10", + "width": "22", + "name": "RESERVED_3", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x04", + "name": "GIER", + "access": "RW", + "description": "Global Interrupt Enable Register", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "Enable", + "access": "RW", + "description": "Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled" + }, + { + "offset": "1", + "width": "31", + "name": "RESERVED", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x08", + "name": "IP_IER", + "access": "RW", + "description": "IP Interrupt Enable Register", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "CHAN0_INT_EN", + "access": "RW", + "description": "Enable Channel 0 (ap_done) Interrupt. 0 = Disabled, 1 = Enabled." + }, + { + "offset": "1", + "width": "1", + "name": "CHAN1_INT_EN", + "access": "RW", + "description": "Enable Channel 1 (ap_ready) Interrupt. 0 = Disabled, 1 = Enabled." + }, + { + "offset": "2", + "width": "30", + "name": "RESERVED_0", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x0c", + "name": "IP_ISR", + "access": "RW", + "description": "IP Interrupt Status Register", + "range": "32", + "fields": [ + { + "offset": "0", + "width": "1", + "name": "CHAN0_INT_ST", + "access": "RTOW", + "description": "Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 interrupt, 1 = Channel 0 interrupt." + }, + { + "offset": "1", + "width": "1", + "name": "CHAN1_INT_ST", + "access": "RTOW", + "description": "Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 interrupt, 1 = Channel 1 interrupt." + }, + { + "offset": "2", + "width": "30", + "name": "RESERVED_0", + "access": "R", + "description": "Reserved. 0s on read." + } + ] + }, + { + "offset": "0x10", + "name": "size", + "access": "W", + "description": "Data signal of size", + "range": "32", + "fields": [{ + "offset": "0", + "width": "32", + "name": "size", + "access": "W", + "description": "Bit 31 to 0 of size" + }] + }, + { + "offset": "0x18", + "name": "out_r_1", + "access": "W", + "description": "Data signal of out_r", + "range": "32", + "fields": [{ + "offset": "0", + "width": "32", + "name": "out_r", + "access": "W", + "description": "Bit 31 to 0 of out_r" + }] + }, + { + "offset": "0x1c", + "name": "out_r_2", + "access": "W", + "description": "Data signal of out_r", + "range": "32", + "fields": [{ + "offset": "0", + "width": "32", + "name": "out_r", + "access": "W", + "description": "Bit 63 to 32 of out_r" + }] + } + ], + "constraints": [ + { + "constraint_type": "pragma interface", + "mode": "s_axilite", + "register_option": "0", + "offset": "16", + "argName": "size" + }, + { + "constraint_type": "pragma interface", + "mode": "s_axilite", + "register_option": "0", + "offset": "24", + "argName": "out" + } + ] + }, + "ap_clk": { + "type": "clock", + "busTypeName": "clock", + "mode": "slave", + "busParams": { + "ASSOCIATED_BUSIF": "s_axi_control:axis_in:m_axi_gmem0", + "ASSOCIATED_RESET": "ap_rst_n" + }, + "portMap": {"ap_clk": "CLK"}, + "ports": ["ap_clk"] + }, + "ap_rst_n": { + "type": "reset", + "busTypeName": "reset", + "mode": "slave", + "busParams": {"POLARITY": "ACTIVE_LOW"}, + "portMap": {"ap_rst_n": "RST"}, + "ports": ["ap_rst_n"] + }, + "interrupt": { + "type": "interrupt", + "busTypeName": "interrupt", + "mode": "master", + "dataWidth": "1", + "busParams": {"SENSITIVITY": "LEVEL_HIGH"}, + "portMap": {"interrupt": "INTERRUPT"}, + "ports": ["interrupt"] + }, + "axis_in": { + "type": "axi4stream", + "busTypeName": "axis", + "mode": "slave", + "direction": "in", + "dataWidth": "64", + "portPrefix": "axis_in_", + "ports": [ + "axis_in_TDATA", + "axis_in_TREADY", + "axis_in_TVALID" + ], + "constraints": [{ + "constraint_type": "pragma interface", + "mode": "axis", + "register_option": "1", + "register_mode": "both", + "argName": "axis_in" + }] + }, + "m_axi_gmem0": { + "type": "axi4full", + "busTypeName": "aximm", + "mode": "master", + "dataWidth": "64", + "addrWidth": "64", + "portPrefix": "m_axi_gmem0_", + "paramPrefix": "C_M_AXI_GMEM0_", + "offsetSlaveName": "s_axi_control", + "preferredUsageValue": "MEMORY", + "busParams": { + "NUM_READ_OUTSTANDING": "16", + "NUM_WRITE_OUTSTANDING": "16", + "MAX_READ_BURST_LENGTH": "16", + "MAX_WRITE_BURST_LENGTH": "16", + "MAX_BURST_LENGTH": "256", + "PROTOCOL": "AXI4", + "READ_WRITE_MODE": "WRITE_ONLY", + "HAS_BURST": "0", + "SUPPORTS_NARROW_BURST": "0" + }, + "ports": [ + "m_axi_gmem0_ARADDR", + "m_axi_gmem0_ARBURST", + "m_axi_gmem0_ARCACHE", + "m_axi_gmem0_ARID", + "m_axi_gmem0_ARLEN", + "m_axi_gmem0_ARLOCK", + "m_axi_gmem0_ARPROT", + "m_axi_gmem0_ARQOS", + "m_axi_gmem0_ARREADY", + "m_axi_gmem0_ARREGION", + "m_axi_gmem0_ARSIZE", + "m_axi_gmem0_ARUSER", + "m_axi_gmem0_ARVALID", + "m_axi_gmem0_AWADDR", + "m_axi_gmem0_AWBURST", + "m_axi_gmem0_AWCACHE", + "m_axi_gmem0_AWID", + "m_axi_gmem0_AWLEN", + "m_axi_gmem0_AWLOCK", + "m_axi_gmem0_AWPROT", + "m_axi_gmem0_AWQOS", + "m_axi_gmem0_AWREADY", + "m_axi_gmem0_AWREGION", + "m_axi_gmem0_AWSIZE", + "m_axi_gmem0_AWUSER", + "m_axi_gmem0_AWVALID", + "m_axi_gmem0_BID", + "m_axi_gmem0_BREADY", + "m_axi_gmem0_BRESP", + "m_axi_gmem0_BUSER", + "m_axi_gmem0_BVALID", + "m_axi_gmem0_RDATA", + "m_axi_gmem0_RID", + "m_axi_gmem0_RLAST", + "m_axi_gmem0_RREADY", + "m_axi_gmem0_RRESP", + "m_axi_gmem0_RUSER", + "m_axi_gmem0_RVALID", + "m_axi_gmem0_WDATA", + "m_axi_gmem0_WID", + "m_axi_gmem0_WLAST", + "m_axi_gmem0_WREADY", + "m_axi_gmem0_WSTRB", + "m_axi_gmem0_WUSER", + "m_axi_gmem0_WVALID" + ], + "constraints": [ + { + "constraint_type": "pragma interface", + "mode": "m_axi", + "register_option": "0", + "offset": "slave", + "latency": "0", + "num_read_outstanding": "16", + "num_write_outstanding": "16", + "max_read_burst_length": "16", + "max_write_burst_length": "16", + "max_widen_bitwidth": "64", + "channel_id": "0", + "argName": "out" + }, + { + "constraint_type": "bitwidth", + "orig_bitwidth": "64", + "final_bitwidth": "64", + "argName": "out" + } + ] + } + }, + "RtlPorts": { + "s_axi_control_AWVALID": { + "dir": "in", + "width": "1" + }, + "s_axi_control_AWREADY": { + "dir": "out", + "width": "1" + }, + "s_axi_control_AWADDR": { + "dir": "in", + "width": "6" + }, + "s_axi_control_WVALID": { + "dir": "in", + "width": "1" + }, + "s_axi_control_WREADY": { + "dir": "out", + "width": "1" + }, + "s_axi_control_WDATA": { + "dir": "in", + "width": "32" + }, + "s_axi_control_WSTRB": { + "dir": "in", + "width": "4" + }, + "s_axi_control_ARVALID": { + "dir": "in", + "width": "1" + }, + "s_axi_control_ARREADY": { + "dir": "out", + "width": "1" + }, + "s_axi_control_ARADDR": { + "dir": "in", + "width": "6" + }, + "s_axi_control_RVALID": { + "dir": "out", + "width": "1" + }, + "s_axi_control_RREADY": { + "dir": "in", + "width": "1" + }, + "s_axi_control_RDATA": { + "dir": "out", + "width": "32" + }, + "s_axi_control_RRESP": { + "dir": "out", + "width": "2" + }, + "s_axi_control_BVALID": { + "dir": "out", + "width": "1" + }, + "s_axi_control_BREADY": { + "dir": "in", + "width": "1" + }, + "s_axi_control_BRESP": { + "dir": "out", + "width": "2" + }, + "ap_clk": { + "dir": "in", + "width": "1" + }, + "ap_rst_n": { + "dir": "in", + "width": "1" + }, + "interrupt": { + "dir": "out", + "width": "1" + }, + "axis_in_TVALID": { + "dir": "in", + "width": "1" + }, + "axis_in_TDATA": { + "dir": "in", + "width": "64" + }, + "axis_in_TREADY": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_AWVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_AWREADY": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_AWADDR": { + "dir": "out", + "width": "64" + }, + "m_axi_gmem0_AWID": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_AWLEN": { + "dir": "out", + "width": "8" + }, + "m_axi_gmem0_AWSIZE": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_AWBURST": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_AWLOCK": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_AWCACHE": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_AWPROT": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_AWQOS": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_AWREGION": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_AWUSER": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_WVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_WREADY": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_WDATA": { + "dir": "out", + "width": "64" + }, + "m_axi_gmem0_WSTRB": { + "dir": "out", + "width": "8" + }, + "m_axi_gmem0_WLAST": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_WID": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_WUSER": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_ARVALID": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_ARREADY": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_ARADDR": { + "dir": "out", + "width": "64" + }, + "m_axi_gmem0_ARID": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_ARLEN": { + "dir": "out", + "width": "8" + }, + "m_axi_gmem0_ARSIZE": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_ARBURST": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_ARLOCK": { + "dir": "out", + "width": "2" + }, + "m_axi_gmem0_ARCACHE": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_ARPROT": { + "dir": "out", + "width": "3" + }, + "m_axi_gmem0_ARQOS": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_ARREGION": { + "dir": "out", + "width": "4" + }, + "m_axi_gmem0_ARUSER": { + "dir": "out", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_RVALID": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_RREADY": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_RDATA": { + "dir": "in", + "width": "64" + }, + "m_axi_gmem0_RLAST": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_RID": { + "dir": "in", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_RUSER": { + "dir": "in", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_RRESP": { + "dir": "in", + "width": "2" + }, + "m_axi_gmem0_BVALID": { + "dir": "in", + "width": "1" + }, + "m_axi_gmem0_BREADY": { + "dir": "out", + "width": "1" + }, + "m_axi_gmem0_BRESP": { + "dir": "in", + "width": "2" + }, + "m_axi_gmem0_BID": { + "dir": "in", + "width": "1", + "isVector": "true" + }, + "m_axi_gmem0_BUSER": { + "dir": "in", + "width": "1", + "isVector": "true" + } + }, + "ModuleInfo": { + "Hierarchy": { + "ModuleName": "dma_out", + "BindInstances": "icmp_ln30_fu_164_p2 add_ln30_fu_170_p2 icmp_ln30_1_fu_187_p2 control_s_axi_U gmem0_m_axi_U" + }, + "Info": {"dma_out": { + "FunctionProtocol": "ap_ctrl_hs", + "isTaskLevelControl": "0", + "isPipelined": "0", + "isCombinational": "0", + "isOneStateSeq": "0" + }}, + "Metrics": {"dma_out": { + "Latency": { + "LatencyBest": "", + "LatencyAvg": "", + "LatencyWorst": "", + "PipelineII": "0", + "PipelineDepth": "", + "PipelineType": "loop auto-rewind stp (delay=0 clock cycles(s))" + }, + "Timing": { + "Target": "2.00", + "Uncertainty": "0.54", + "Estimate": "2.130" + }, + "Loops": [{ + "Name": "VITIS_LOOP_30_1", + "TripCount": "", + "Latency": "", + "PipelineII": "1", + "PipelineDepth": "14" + }], + "Area": { + "BRAM_18K": "0", + "AVAIL_BRAM": "7482", + "UTIL_BRAM": "0", + "FF": "1927", + "AVAIL_FF": "5148416", + "UTIL_FF": "~0", + "LUT": "1408", + "AVAIL_LUT": "2574208", + "UTIL_LUT": "~0", + "URAM": "0", + "AVAIL_URAM": "1925", + "UTIL_URAM": "0", + "DSP": "0", + "AVAIL_DSP": "10848", + "UTIL_DSP": "0" + } + }} + }, + "GenerateBdFiles": "0", + "GenData": { + "DataVersion": "0.2", + "Time": "2026-03-12 09:46:23 GMT", + "ToolName": "vitis_hls", + "ToolVersion": "2025.1" + } +} diff --git a/linker/test/fixtures/dma_out/hls/impl/ip/component.xml b/linker/test/fixtures/dma_out/hls/impl/ip/component.xml new file mode 100644 index 00000000..59f76120 --- /dev/null +++ b/linker/test/fixtures/dma_out/hls/impl/ip/component.xml @@ -0,0 +1,2638 @@ + + + xilinx.com + hls + dma_out + 1.0 + + + s_axi_control + + + + + + + + + ARADDR + + + s_axi_control_ARADDR + + + + + ARREADY + + + s_axi_control_ARREADY + + + + + ARVALID + + + s_axi_control_ARVALID + + + + + AWADDR + + + s_axi_control_AWADDR + + + + + AWREADY + + + s_axi_control_AWREADY + + + + + AWVALID + + + s_axi_control_AWVALID + + + + + BREADY + + + s_axi_control_BREADY + + + + + BRESP + + + s_axi_control_BRESP + + + + + BVALID + + + s_axi_control_BVALID + + + + + RDATA + + + s_axi_control_RDATA + + + + + RREADY + + + s_axi_control_RREADY + + + + + RRESP + + + s_axi_control_RRESP + + + + + RVALID + + + s_axi_control_RVALID + + + + + WDATA + + + s_axi_control_WDATA + + + + + WREADY + + + s_axi_control_WREADY + + + + + WSTRB + + + s_axi_control_WSTRB + + + + + WVALID + + + s_axi_control_WVALID + + + + + + ADDR_WIDTH + 6 + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE + + + + + ap_clk + + + + + + + CLK + + + ap_clk + + + + + + ASSOCIATED_BUSIF + s_axi_control:axis_in:m_axi_gmem0 + + + ASSOCIATED_RESET + ap_rst_n + + + + + ap_rst_n + + + + + + + RST + + + ap_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + interrupt + + + + + + + INTERRUPT + + + interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + axis_in + + + + + + + TDATA + + + axis_in_TDATA + + + + + TREADY + + + axis_in_TREADY + + + + + TVALID + + + axis_in_TVALID + + + + + + TUSER_WIDTH + 0 + + + TDATA_NUM_BYTES + 8 + + + + + m_axi_gmem0 + + + + + + + + + ARADDR + + + m_axi_gmem0_ARADDR + + + + + ARBURST + + + m_axi_gmem0_ARBURST + + + + + ARCACHE + + + m_axi_gmem0_ARCACHE + + + + + ARID + + + m_axi_gmem0_ARID + + + + + ARLEN + + + m_axi_gmem0_ARLEN + + + + + ARLOCK + + + m_axi_gmem0_ARLOCK + + + + + ARPROT + + + m_axi_gmem0_ARPROT + + + + + ARQOS + + + m_axi_gmem0_ARQOS + + + + + ARREADY + + + m_axi_gmem0_ARREADY + + + + + ARREGION + + + m_axi_gmem0_ARREGION + + + + + ARSIZE + + + m_axi_gmem0_ARSIZE + + + + + ARUSER + + + m_axi_gmem0_ARUSER + + + + + ARVALID + + + m_axi_gmem0_ARVALID + + + + + AWADDR + + + m_axi_gmem0_AWADDR + + + + + AWBURST + + + m_axi_gmem0_AWBURST + + + + + AWCACHE + + + m_axi_gmem0_AWCACHE + + + + + AWID + + + m_axi_gmem0_AWID + + + + + AWLEN + + + m_axi_gmem0_AWLEN + + + + + AWLOCK + + + m_axi_gmem0_AWLOCK + + + + + AWPROT + + + m_axi_gmem0_AWPROT + + + + + AWQOS + + + m_axi_gmem0_AWQOS + + + + + AWREADY + + + m_axi_gmem0_AWREADY + + + + + AWREGION + + + m_axi_gmem0_AWREGION + + + + + AWSIZE + + + m_axi_gmem0_AWSIZE + + + + + AWUSER + + + m_axi_gmem0_AWUSER + + + + + AWVALID + + + m_axi_gmem0_AWVALID + + + + + BID + + + m_axi_gmem0_BID + + + + + BREADY + + + m_axi_gmem0_BREADY + + + + + BRESP + + + m_axi_gmem0_BRESP + + + + + BUSER + + + m_axi_gmem0_BUSER + + + + + BVALID + + + m_axi_gmem0_BVALID + + + + + RDATA + + + m_axi_gmem0_RDATA + + + + + RID + + + m_axi_gmem0_RID + + + + + RLAST + + + m_axi_gmem0_RLAST + + + + + RREADY + + + m_axi_gmem0_RREADY + + + + + RRESP + + + m_axi_gmem0_RRESP + + + + + RUSER + + + m_axi_gmem0_RUSER + + + + + RVALID + + + m_axi_gmem0_RVALID + + + + + WDATA + + + m_axi_gmem0_WDATA + + + + + WID + + + m_axi_gmem0_WID + + + + + WLAST + + + m_axi_gmem0_WLAST + + + + + WREADY + + + m_axi_gmem0_WREADY + + + + + WSTRB + + + m_axi_gmem0_WSTRB + + + + + WUSER + + + m_axi_gmem0_WUSER + + + + + WVALID + + + m_axi_gmem0_WVALID + + + + + + NUM_READ_OUTSTANDING + 16 + + + NUM_WRITE_OUTSTANDING + 16 + + + MAX_READ_BURST_LENGTH + 16 + + + MAX_WRITE_BURST_LENGTH + 16 + + + MAX_BURST_LENGTH + 256 + + + PROTOCOL + AXI4 + + + READ_WRITE_MODE + WRITE_ONLY + + + HAS_BURST + 0 + + + SUPPORTS_NARROW_BURST + 0 + + + ADDR_WIDTH + 64 + + + + + + + Data_m_axi_gmem0 + 16E + 64 + + + DEPENDENT_ON + s_axi_control + + + PREFERRED_USAGE + MEMORY + + + + + + + s_axi_control + + Reg + 0 + 65536 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S_AXI_CONTROL_BASEADDR + + + OFFSET_HIGH_PARAM + C_S_AXI_CONTROL_HIGHADDR + + + + CTRL + CTRL + Control signals + 0 + 32 + read-write + + 0 + + + AP_START + Control signal Register for 'ap_start'. + 0 + 1 + read-write + modify + + 0 + 0 + + false + + + AP_DONE + Control signal Register for 'ap_done'. + 1 + 1 + read-only + + 0 + 0 + + modify + false + + + AP_IDLE + Control signal Register for 'ap_idle'. + 2 + 1 + read-only + + 0 + 0 + + modify + false + + + AP_READY + Control signal Register for 'ap_ready'. + 3 + 1 + read-only + + 0 + 0 + + modify + false + + + RESERVED_1 + Reserved. 0s on read. + 4 + 3 + read-only + + 0 + 0 + + modify + false + + + AUTO_RESTART + Control signal Register for 'auto_restart'. + 7 + 1 + read-write + modify + + 0 + 0 + + false + + + RESERVED_2 + Reserved. 0s on read. + 8 + 1 + read-only + + 0 + 0 + + modify + false + + + INTERRUPT + Control signal Register for 'interrupt'. + 9 + 1 + read-only + + 0 + 0 + + modify + false + + + RESERVED_3 + Reserved. 0s on read. + 10 + 22 + read-only + + 0 + 0 + + modify + false + + + + GIER + GIER + Global Interrupt Enable Register + 4 + 32 + read-write + + 0 + + + Enable + Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled + 0 + 1 + read-write + modify + + 0 + 0 + + false + + + RESERVED + Reserved. 0s on read. + 1 + 31 + read-only + + 0 + 0 + + modify + false + + + + IP_IER + IP_IER + IP Interrupt Enable Register + 8 + 32 + read-write + + 0 + + + CHAN0_INT_EN + Enable Channel 0 (ap_done) Interrupt. 0 = Disabled, 1 = Enabled. + 0 + 1 + read-write + modify + + 0 + 0 + + false + + + CHAN1_INT_EN + Enable Channel 1 (ap_ready) Interrupt. 0 = Disabled, 1 = Enabled. + 1 + 1 + read-write + modify + + 0 + 0 + + false + + + RESERVED_0 + Reserved. 0s on read. + 2 + 30 + read-only + + 0 + 0 + + modify + false + + + + IP_ISR + IP_ISR + IP Interrupt Status Register + 12 + 32 + read-write + + 0 + + + CHAN0_INT_ST + Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 interrupt, 1 = Channel 0 interrupt. + 0 + 1 + read-only + oneToToggle + + 0 + 0 + + modify + false + + + CHAN1_INT_ST + Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 interrupt, 1 = Channel 1 interrupt. + 1 + 1 + read-only + oneToToggle + + 0 + 0 + + modify + false + + + RESERVED_0 + Reserved. 0s on read. + 2 + 30 + read-only + + 0 + 0 + + modify + false + + + + size + size + Data signal of size + 16 + 32 + write-only + + 0 + + + size + Bit 31 to 0 of size + 0 + 32 + write-only + + 0 + 0 + + false + + + + out_r_1 + out_r_1 + Data signal of out_r + 24 + 32 + write-only + + 0 + + + out_r + Bit 31 to 0 of out_r + 0 + 32 + write-only + + 0 + 0 + + false + + + + out_r_2 + out_r_2 + Data signal of out_r + 28 + 32 + write-only + + 0 + + + out_r + Bit 63 to 32 of out_r + 0 + 32 + write-only + + 0 + 0 + + false + + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + dma_out + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + fe1ae42c + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + dma_out + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + 1bc7b0e1 + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + dma_out + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + d01f6ccc + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + dma_out + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + d8aa000d + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + 53b8ee29 + + + + + xilinx_documentation + Documentation + :vivado.xilinx.com:docs.all + + xilinx_documentation_view_fileset + + + + xilinx_miscfiles + Miscellaneous + :vivado.xilinx.com:misc.files + + xilinx_miscfiles_view_fileset + + + + viewChecksum + 34797a57 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 13f0ffc0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 34797a57 + + + + + + + s_axi_control_ARADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_ARREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_ARVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_AWADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_AWREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_AWVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_BREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_BVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_RVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_control_WVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ap_clk + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ap_rst_n + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + interrupt + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_in_TDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_in_TREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_in_TVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARADDR + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_ARLEN + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARREGION + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_ARUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_gmem0_ARVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWADDR + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWBURST + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWCACHE + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_AWLEN + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWLOCK + + out + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWPROT + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWQOS + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWREGION + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWSIZE + + out + + 2 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_AWUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_gmem0_AWVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_BID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_BREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_BRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_BUSER + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_gmem0_BVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RID + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_RLAST + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RRESP + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_RUSER + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_gmem0_RVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WID + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_gmem0_WLAST + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WSTRB + + out + + 7 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_gmem0_WUSER + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_gmem0_WVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + C_S_AXI_CONTROL_ADDR_WIDTH + 6 + + + C_S_AXI_CONTROL_DATA_WIDTH + 32 + + + C_M_AXI_GMEM0_ID_WIDTH + 1 + + + + true + + + + + + C_M_AXI_GMEM0_ADDR_WIDTH + 64 + + + C_M_AXI_GMEM0_DATA_WIDTH + 64 + + + C_M_AXI_GMEM0_AWUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_ARUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_WUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_RUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_BUSER_WIDTH + 1 + + + + false + + + + + + C_M_AXI_GMEM0_USER_VALUE + 0x00000000 + + + + false + + + + + + C_M_AXI_GMEM0_PROT_VALUE + "000" + + + C_M_AXI_GMEM0_CACHE_VALUE + "0011" + + + + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + + + xilinx_verilogsynthesis_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + xilinx_softwaredriver_view_fileset + + + xilinx_documentation_view_fileset + + + xilinx_miscfiles_view_fileset + + + xilinx_xpgui_view_fileset + + + xilinx_utilityxitfiles_view_fileset + + + An IP generated by Vitis HLS + + + C_M_AXI_GMEM0_ENABLE_ID_PORTS + Enable ID ports + true + + + C_M_AXI_GMEM0_ID_WIDTH + ID width + 1 + + + + true + + + + + + C_M_AXI_GMEM0_DATA_WIDTH + Data width + 64 + + + C_M_AXI_GMEM0_ENABLE_USER_PORTS + Enable USER ports + false + + + C_M_AXI_GMEM0_AWUSER_WIDTH + AWUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_WUSER_WIDTH + WUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_BUSER_WIDTH + BUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_ARUSER_WIDTH + ARUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_RUSER_WIDTH + RUSER width + 1 + + + + false + + + + + + C_M_AXI_GMEM0_USER_VALUE + USER value + 0x00000000 + + + + false + + + + + + C_M_AXI_GMEM0_PROT_VALUE + PROT value + "000" + + + C_M_AXI_GMEM0_CACHE_VALUE + CACHE value + "0011" + + + Component_Name + dma_out_v1_0 + + + clk_period + 2 + + + machine + 64 + + + combinational + 0 + + + latency + undef + + + II + 0 + + + + + + versal + + + /VITIS_HLS_IP + + Dma_out + HLS + 2114517586 + 2026-03-12T09:46:34Z + + true + hls + + + + 2025.1 + + + + + + + + + + diff --git a/linker/test/fixtures/passthrough/hls/hls_data.json b/linker/test/fixtures/passthrough/hls/hls_data.json new file mode 100644 index 00000000..84c28321 --- /dev/null +++ b/linker/test/fixtures/passthrough/hls/hls_data.json @@ -0,0 +1,246 @@ +{ + "Top": "passthrough", + "RtlTop": "passthrough", + "RtlPrefix": "", + "RtlSubPrefix": "passthrough_", + "SourceLanguage": "cpp", + "HostMachineBits": "64", + "FunctionProtocol": "ap_ctrl_none", + "ResetStyle": "control", + "Target": { + "Family": "versal", + "Device": "xcv80", + "Package": "-lsva4737", + "Speed": "-2MHP-e-S", + "Triple": "fpga64-xilinx-none" + }, + "Args": { + "axis_in": { + "index": "0", + "direction": "in", + "srcType": "stream, 0>&", + "srcSize": "64", + "hwRefs": [{ + "type": "interface", + "interface": "axis_in", + "name": "", + "usage": "data", + "direction": "in" + }] + }, + "axis_out": { + "index": "1", + "direction": "out", + "srcType": "stream, 0>&", + "srcSize": "64", + "hwRefs": [{ + "type": "interface", + "interface": "axis_out", + "name": "", + "usage": "data", + "direction": "out" + }] + } + }, + "HlsSolution": { + "FlowTarget": "vivado", + "ConfigTcl": [ + "config_export -format=ip_catalog", + "config_export -flow=none" + ], + "ProfileOption": "0", + "ProfileType": "none", + "KernelName": "passthrough" + }, + "ClockInfo": { + "ClockName": "ap_clk", + "ClockPeriod": "2", + "Uncertainty": "0.54", + "IsCombinational": "0", + "II": "undef", + "Latency": "undef" + }, + "Xdc": {"OocClocks": ["create_clock -name ap_clk -period 2.000 [get_ports ap_clk]"]}, + "Ipx": { + "Vendor": "xilinx.com", + "Library": "hls", + "Name": "passthrough", + "Version": "1.0", + "DisplayName": "Passthrough", + "Revision": "2114517586", + "Description": "An IP generated by Vitis HLS", + "Taxonomy": "\/VITIS_HLS_IP", + "AutoFamilySupport": "", + "ZipFile": "xilinx_com_hls_passthrough_1_0.zip" + }, + "Files": { + "CSource": [], + "Vhdl": [], + "Verilog": [], + "IpMisc": [], + "CsynthXml": "", + "DebugDir": ".debug", + "KernelXml": "", + "Xo": "", + "XoHlsDir": "", + "ProtoInst": [] + }, + "SubcoreInfo": { + "HasXpmMemory": false, + "HasClockedDsp": false, + "Ip": [ + + ] + }, + "Interfaces": { + "ap_clk": { + "type": "clock", + "busTypeName": "clock", + "mode": "slave", + "busParams": { + "ASSOCIATED_BUSIF": "axis_in:axis_out", + "ASSOCIATED_RESET": "ap_rst_n" + }, + "portMap": {"ap_clk": "CLK"}, + "ports": ["ap_clk"] + }, + "ap_rst_n": { + "type": "reset", + "busTypeName": "reset", + "mode": "slave", + "busParams": {"POLARITY": "ACTIVE_LOW"}, + "portMap": {"ap_rst_n": "RST"}, + "ports": ["ap_rst_n"] + }, + "axis_in": { + "type": "axi4stream", + "busTypeName": "axis", + "mode": "slave", + "direction": "in", + "dataWidth": "64", + "portPrefix": "axis_in_", + "ports": [ + "axis_in_TDATA", + "axis_in_TREADY", + "axis_in_TVALID" + ], + "constraints": [{ + "constraint_type": "pragma interface", + "mode": "axis", + "register_option": "1", + "register_mode": "both", + "argName": "axis_in" + }] + }, + "axis_out": { + "type": "axi4stream", + "busTypeName": "axis", + "mode": "master", + "direction": "out", + "dataWidth": "64", + "portPrefix": "axis_out_", + "ports": [ + "axis_out_TDATA", + "axis_out_TREADY", + "axis_out_TVALID" + ], + "constraints": [{ + "constraint_type": "pragma interface", + "mode": "axis", + "register_option": "1", + "register_mode": "both", + "argName": "axis_out" + }] + } + }, + "RtlPorts": { + "ap_clk": { + "dir": "in", + "width": "1" + }, + "ap_rst_n": { + "dir": "in", + "width": "1" + }, + "axis_in_TDATA": { + "dir": "in", + "width": "64" + }, + "axis_in_TVALID": { + "dir": "in", + "width": "1" + }, + "axis_in_TREADY": { + "dir": "out", + "width": "1" + }, + "axis_out_TDATA": { + "dir": "out", + "width": "64" + }, + "axis_out_TVALID": { + "dir": "out", + "width": "1" + }, + "axis_out_TREADY": { + "dir": "in", + "width": "1" + } + }, + "ModuleInfo": { + "Hierarchy": {"ModuleName": "passthrough"}, + "Info": {"passthrough": { + "FunctionProtocol": "ap_ctrl_none", + "isTaskLevelControl": "0", + "isPipelined": "0", + "isCombinational": "0", + "isOneStateSeq": "0" + }}, + "Metrics": {"passthrough": { + "Latency": { + "LatencyBest": "", + "LatencyAvg": "", + "LatencyWorst": "", + "PipelineII": "", + "PipelineDepth": "", + "PipelineType": "no" + }, + "Timing": { + "Target": "2.00", + "Uncertainty": "0.54", + "Estimate": "1.442" + }, + "Loops": [{ + "Name": "VITIS_LOOP_30_1", + "TripCount": "inf", + "Latency": "", + "PipelineII": "1", + "PipelineDepth": "3" + }], + "Area": { + "FF": "71", + "AVAIL_FF": "5148416", + "UTIL_FF": "~0", + "LUT": "23", + "AVAIL_LUT": "2574208", + "UTIL_LUT": "~0", + "BRAM_18K": "0", + "AVAIL_BRAM": "7482", + "UTIL_BRAM": "0", + "DSP": "0", + "AVAIL_DSP": "10848", + "UTIL_DSP": "0", + "URAM": "0", + "AVAIL_URAM": "1925", + "UTIL_URAM": "0" + } + }} + }, + "GenerateBdFiles": "0", + "GenData": { + "DataVersion": "0.2", + "Time": "2026-03-12 09:46:20 GMT", + "ToolName": "vitis_hls", + "ToolVersion": "2025.1" + } +} diff --git a/linker/test/fixtures/passthrough/hls/impl/ip/component.xml b/linker/test/fixtures/passthrough/hls/impl/ip/component.xml new file mode 100644 index 00000000..2052e4eb --- /dev/null +++ b/linker/test/fixtures/passthrough/hls/impl/ip/component.xml @@ -0,0 +1,451 @@ + + + xilinx.com + hls + passthrough + 1.0 + + + ap_clk + + + + + + + CLK + + + ap_clk + + + + + + ASSOCIATED_BUSIF + axis_in:axis_out + + + ASSOCIATED_RESET + ap_rst_n + + + + + ap_rst_n + + + + + + + RST + + + ap_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_in + + + + + + + TDATA + + + axis_in_TDATA + + + + + TREADY + + + axis_in_TREADY + + + + + TVALID + + + axis_in_TVALID + + + + + + TUSER_WIDTH + 0 + + + TDATA_NUM_BYTES + 8 + + + + + axis_out + + + + + + + TDATA + + + axis_out_TDATA + + + + + TREADY + + + axis_out_TREADY + + + + + TVALID + + + axis_out_TVALID + + + + + + TUSER_WIDTH + 0 + + + TDATA_NUM_BYTES + 8 + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + passthrough + + xilinx_verilogsynthesis_view_fileset + + + + viewChecksum + f8b5aaf6 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + passthrough + + xilinx_verilogbehavioralsimulation_view_fileset + + + + viewChecksum + d9530e31 + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + passthrough + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 58202d1a + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + passthrough + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + edbf1d79 + + + + + xilinx_documentation + Documentation + :vivado.xilinx.com:docs.all + + xilinx_documentation_view_fileset + + + + xilinx_miscfiles + Miscellaneous + :vivado.xilinx.com:misc.files + + xilinx_miscfiles_view_fileset + + + + viewChecksum + 34797a57 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 34797a57 + + + + + + + ap_clk + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + ap_rst_n + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_in_TDATA + + in + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_in_TREADY + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_in_TVALID + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_out_TDATA + + out + + 63 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_out_TREADY + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_out_TVALID + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + xilinx_documentation_view_fileset + + + xilinx_miscfiles_view_fileset + + + xilinx_xpgui_view_fileset + + + xilinx_utilityxitfiles_view_fileset + + + An IP generated by Vitis HLS + + + Component_Name + passthrough_v1_0 + + + clk_period + 2 + + + machine + 64 + + + combinational + 0 + + + latency + undef + + + II + undef + + + + + + versal + + + /VITIS_HLS_IP + + Passthrough + HLS + 2114517586 + 2026-03-12T09:46:34Z + + true + hls + + + + 2025.1 + + + + + + + diff --git a/linker/test/parser/__init__.py b/linker/test/parser/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linker/test/parser/test_component_parser.py b/linker/test/parser/test_component_parser.py new file mode 100644 index 00000000..2278a59c --- /dev/null +++ b/linker/test/parser/test_component_parser.py @@ -0,0 +1,452 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +"""Tests for parser.component_parser — parse_component_xml and helpers.""" + +import textwrap +import xml.etree.ElementTree as ET +from pathlib import Path + +import pytest + +from slashkit.parser.component_parser import parse_component_xml, _int +from slashkit.core.port import BusType +from slashkit.emit.hls_meta import load_hls_metadata, parse_hls_args + + +# --------------------------------------------------------------------------- +# Minimal component.xml builder +# --------------------------------------------------------------------------- + +_NS_SPIRIT = "http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" +_NS_XILINX = "http://www.xilinx.com" + +_XML_HEADER = f"""\ + + + xilinx.com + hls + {{name}} + 1.0 + +{{bus_interfaces}} + + +""" + +_AXILITE_SLAVE_NO_PROTOCOL = """\ + + s_axi_ctrl + + + + """ + +_UNKNOWN_BUS_TYPE = """\ + + mystery_if + + + """ + +_AXIS_NO_TDATA = """\ + + axis_stream + + + """ + +_NAMELESS_BUSIF = """\ + + + + """ + +_AXILITE_BUSIF = """\ + + s_axilite + + + + + PROTOCOL + AXI4LITE + + + DATA_WIDTH + 32 + + + """ + +_AXIS_BUSIF = """\ + + axis_in + + + + TDATA_NUM_BYTES + 8 + + + """ + + +@pytest.fixture +def component_xml(tmp_path: Path): + """ + Factory fixture: writes a component.xml with given bus interfaces and + returns its path. + """ + def _write(name: str = "dma", bus_interfaces: str = "") -> Path: + # Place under impl/ip/ so hls_meta path inference doesn't crash + ip_dir = tmp_path / "sol1" / "impl" / "ip" + ip_dir.mkdir(parents=True, exist_ok=True) + xml_path = ip_dir / "component.xml" + content = _XML_HEADER.format(name=name, bus_interfaces=bus_interfaces) + xml_path.write_text(textwrap.dedent(content), encoding="utf-8") + return xml_path + + return _write + + +# --------------------------------------------------------------------------- +# Tests +# --------------------------------------------------------------------------- + +class TestParseComponentXml: + def test_kernel_name(self, component_xml): + path = component_xml(name="my_kernel") + k = parse_component_xml(path) + assert k.name == "my_kernel" + + def test_vlnv(self, component_xml): + path = component_xml(name="dma") + k = parse_component_xml(path) + assert k.vlnv.startswith("xilinx.com:hls:dma:") + + def test_axilite_port_parsed(self, component_xml): + path = component_xml(bus_interfaces=_AXILITE_BUSIF) + k = parse_component_xml(path) + assert "s_axilite" in k.ports + assert k.ports["s_axilite"].ptype == BusType.AXILITE + assert k.ports["s_axilite"].width == 32 + + def test_axis_port_parsed(self, component_xml): + path = component_xml(bus_interfaces=_AXIS_BUSIF) + k = parse_component_xml(path) + assert "axis_in" in k.ports + assert k.ports["axis_in"].ptype == BusType.AXIS + assert k.ports["axis_in"].width == 64 # 8 bytes * 8 + + def test_no_bus_interfaces(self, component_xml): + path = component_xml() + k = parse_component_xml(path) + assert k.ports == {} + + def test_missing_file_raises(self, tmp_path): + with pytest.raises(Exception): + parse_component_xml(tmp_path / "missing.xml") + + def test_int_invalid_string_returns_none(self): + # _int() must catch ValueError and return None when the element text + # cannot be parsed as an integer (e.g. a malformed XML value). + el = ET.fromstring("not_a_number") + assert _int(el) is None + + def test_axilite_inferred_from_slave_without_protocol_param(self, component_xml): + # An aximm slave with no PROTOCOL parameter still resolves to AXILITE + # via the is_slave fallback branch, distinct from the PROTOCOL="AXI4LITE" path. + path = component_xml(bus_interfaces=_AXILITE_SLAVE_NO_PROTOCOL) + k = parse_component_xml(path) + assert "s_axi_ctrl" in k.ports + assert k.ports["s_axi_ctrl"].ptype == BusType.AXILITE + + def test_unknown_bus_type_is_skipped(self, component_xml): + # An unrecognised vendor/library/name combination causes _to_port_type() + # to return None, and the interface is silently skipped. + path = component_xml(bus_interfaces=_UNKNOWN_BUS_TYPE) + k = parse_component_xml(path) + assert k.ports == {} + + def test_axis_width_none_when_tdata_num_bytes_absent(self, component_xml): + # _axis_width_from_params() returns None when TDATA_NUM_BYTES is not + # present in the parameter map, so the port is created with width=None. + path = component_xml(bus_interfaces=_AXIS_NO_TDATA) + k = parse_component_xml(path) + assert "axis_stream" in k.ports + assert k.ports["axis_stream"].width is None + + def test_nameless_bus_interface_is_skipped(self, component_xml): + # A bus interface with no element is skipped entirely + # rather than being added under an empty key. + path = component_xml(bus_interfaces=_NAMELESS_BUSIF) + k = parse_component_xml(path) + assert k.ports == {} + + +# --------------------------------------------------------------------------- +# Tests against real HLS-generated fixtures +# --------------------------------------------------------------------------- + +FIXTURES_DIR = Path(__file__).parents[1] / "fixtures" + + +def component_path_for_kernel(name: str) -> Path: + return FIXTURES_DIR / name / "hls" / "impl" / "ip" / "component.xml" + + +class TestPassthroughFixture: + """AXIS-only kernel: slave + master stream, clock, reset, no AXI control.""" + + @classmethod + def setup_class(cls): + cls.k = parse_component_xml(component_path_for_kernel("passthrough")) + cls.hls = load_hls_metadata(cls.k.hls_data_path) + cls.args = parse_hls_args(cls.hls) + + def test_name(self): + assert self.k.name == "passthrough" + + def test_axis_in_port(self): + assert "axis_in" in self.k.ports + assert self.k.ports["axis_in"].ptype == BusType.AXIS + assert self.k.ports["axis_in"].width == 64 + + def test_axis_out_port(self): + assert "axis_out" in self.k.ports + assert self.k.ports["axis_out"].ptype == BusType.AXIS + assert self.k.ports["axis_out"].width == 64 + + def test_clock_port(self): + assert "ap_clk" in self.k.ports + assert self.k.ports["ap_clk"].ptype == BusType.CLOCK + + def test_reset_port(self): + assert "ap_rst_n" in self.k.ports + assert self.k.ports["ap_rst_n"].ptype == BusType.RESET + + def test_no_memory_maps(self): + assert self.k.memory_maps == [] + + # hls_data.json tests + def test_hls_data_path_resolved(self): + assert self.k.hls_data_path is not None + assert self.k.hls_data_path.exists() + + def test_hls_function_protocol(self): + assert self.hls["FunctionProtocol"] == "ap_ctrl_none" + + def test_hls_clock_name(self): + assert self.hls["ClockInfo"]["ClockName"] == "ap_clk" + + def test_hls_clock_period(self): + assert self.hls["ClockInfo"]["ClockPeriod"] == "2" + + def test_hls_top_name(self): + assert self.hls["Top"] == "passthrough" + + def test_hls_args_count(self): + # passthrough has axis_in and axis_out — two args + assert len(self.args) == 2 + + def test_hls_args_sorted_by_index(self): + indices = [a["index"] for a in self.args] + assert indices == sorted(indices) + + def test_hls_arg_axis_in(self): + arg = next(a for a in self.args if a["name"] == "axis_in") + assert arg["direction"] == "in" + assert arg["src_size"] == 64 + refs = arg["hw_refs"] + assert len(refs) == 1 + assert refs[0]["type"] == "interface" + assert refs[0]["interface"] == "axis_in" + + def test_hls_arg_axis_out(self): + arg = next(a for a in self.args if a["name"] == "axis_out") + assert arg["direction"] == "out" + assert arg["src_size"] == 64 + refs = arg["hw_refs"] + assert len(refs) == 1 + assert refs[0]["type"] == "interface" + assert refs[0]["interface"] == "axis_out" + + +class TestDmaInFixture: + """AXI4Lite control + AXI4Full master + AXIS master (read-from-memory, stream-out).""" + + @classmethod + def setup_class(cls): + cls.k = parse_component_xml(component_path_for_kernel("dma_in")) + cls.hls = load_hls_metadata(cls.k.hls_data_path) + cls.args = parse_hls_args(cls.hls) + + def test_name(self): + assert self.k.name == "dma_in" + + def test_axilite_port(self): + assert "s_axi_control" in self.k.ports + assert self.k.ports["s_axi_control"].ptype == BusType.AXILITE + assert self.k.ports["s_axi_control"].width == 32 + + def test_axi4full_port_present(self): + axi_full = [p for p in self.k.ports.values() if p.ptype == + BusType.AXI4FULL] + assert len(axi_full) >= 1 + + def test_axis_port_present(self): + axis = [p for p in self.k.ports.values() if p.ptype == BusType.AXIS] + assert len(axis) >= 1 + + def test_memory_maps(self): + assert len(self.k.memory_maps) >= 1 + + # hls_data.json tests + def test_hls_data_path_resolved(self): + assert self.k.hls_data_path is not None + assert self.k.hls_data_path.exists() + + def test_hls_function_protocol(self): + assert self.hls["FunctionProtocol"] == "ap_ctrl_hs" + + def test_hls_top_name(self): + assert self.hls["Top"] == "dma_in" + + def test_hls_clock_name(self): + assert self.hls["ClockInfo"]["ClockName"] == "ap_clk" + + def test_hls_args_count(self): + # dma_in has: in (pointer), axis_out (stream), size (scalar) — three args + assert len(self.args) == 3 + + def test_hls_args_sorted_by_index(self): + indices = [a["index"] for a in self.args] + assert indices == sorted(indices) + + def test_hls_arg_in_has_axi_interface_ref(self): + arg = next(a for a in self.args if a["name"] == "in") + assert arg["direction"] == "in" + iface_refs = [r for r in arg["hw_refs"] if r["type"] == "interface"] + assert any(r["interface"] == "m_axi_gmem0" for r in iface_refs) + + def test_hls_arg_in_has_register_refs(self): + arg = next(a for a in self.args if a["name"] == "in") + reg_refs = [r for r in arg["hw_refs"] if r["type"] == "register"] + assert len(reg_refs) >= 1 + assert all(r["interface"] == "s_axi_control" for r in reg_refs) + + def test_hls_arg_axis_out(self): + arg = next(a for a in self.args if a["name"] == "axis_out") + assert arg["direction"] == "out" + assert arg["src_size"] == 64 + refs = arg["hw_refs"] + assert any(r["interface"] == "axis_out" for r in refs) + + def test_hls_arg_size_is_scalar_register(self): + arg = next(a for a in self.args if a["name"] == "size") + assert arg["direction"] == "in" + assert arg["src_size"] == 32 + assert all(r["type"] == "register" for r in arg["hw_refs"]) + + +class TestDmaOutFixture: + """AXI4Lite control + AXI4Full master + AXIS slave (stream-in, write-to-memory).""" + + @classmethod + def setup_class(cls): + cls.k = parse_component_xml(component_path_for_kernel("dma_out")) + cls.hls = load_hls_metadata(cls.k.hls_data_path) + cls.args = parse_hls_args(cls.hls) + + def test_name(self): + assert self.k.name == "dma_out" + + def test_axilite_port(self): + assert "s_axi_control" in self.k.ports + assert self.k.ports["s_axi_control"].ptype == BusType.AXILITE + assert self.k.ports["s_axi_control"].width == 32 + + def test_axi4full_port_present(self): + axi_full = [p for p in self.k.ports.values() if p.ptype == + BusType.AXI4FULL] + assert len(axi_full) >= 1 + + def test_axis_port_present(self): + axis = [p for p in self.k.ports.values() if p.ptype == BusType.AXIS] + assert len(axis) >= 1 + + def test_memory_maps(self): + assert len(self.k.memory_maps) >= 1 + + # hls_data.json tests + def test_hls_data_path_resolved(self): + assert self.k.hls_data_path is not None + assert self.k.hls_data_path.exists() + + def test_hls_function_protocol(self): + assert self.hls["FunctionProtocol"] == "ap_ctrl_hs" + + def test_hls_top_name(self): + assert self.hls["Top"] == "dma_out" + + def test_hls_clock_name(self): + assert self.hls["ClockInfo"]["ClockName"] == "ap_clk" + + def test_hls_args_count(self): + # dma_out has: size (scalar), axis_in (stream), out (pointer) — three args + assert len(self.args) == 3 + + def test_hls_args_sorted_by_index(self): + indices = [a["index"] for a in self.args] + assert indices == sorted(indices) + + def test_hls_arg_out_has_axi_interface_ref(self): + arg = next(a for a in self.args if a["name"] == "out") + assert arg["direction"] == "out" + iface_refs = [r for r in arg["hw_refs"] if r["type"] == "interface"] + assert any(r["interface"] == "m_axi_gmem0" for r in iface_refs) + + def test_hls_arg_out_has_register_refs(self): + arg = next(a for a in self.args if a["name"] == "out") + reg_refs = [r for r in arg["hw_refs"] if r["type"] == "register"] + assert len(reg_refs) >= 1 + assert all(r["interface"] == "s_axi_control" for r in reg_refs) + + def test_hls_arg_axis_in(self): + arg = next(a for a in self.args if a["name"] == "axis_in") + assert arg["direction"] == "in" + assert arg["src_size"] == 64 + refs = arg["hw_refs"] + assert any(r["interface"] == "axis_in" for r in refs) + + def test_hls_arg_size_is_scalar_register(self): + arg = next(a for a in self.args if a["name"] == "size") + assert arg["direction"] == "in" + assert arg["src_size"] == 32 + assert all(r["type"] == "register" for r in arg["hw_refs"]) diff --git a/linker/test/parser/test_config_parser.py b/linker/test/parser/test_config_parser.py new file mode 100644 index 00000000..9e43555f --- /dev/null +++ b/linker/test/parser/test_config_parser.py @@ -0,0 +1,574 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +"""Tests for parser.config_parser — helper functions and file parser.""" + +import textwrap +from pathlib import Path + +import pytest + +from slashkit.parser.config_parser import ( + _parse_target, + _parse_nk_value, + _parse_stream_connect_value, + _parse_sp_value, + _parse_debug_net_value, + _resolve_port_name_for_kernel, + parse_connectivity_file, + apply_config_to_instances, +) +from slashkit.core.kernel import Kernel +from slashkit.core.port import BusType, Port +from slashkit.core.connectivity import ( + ConnectivityConfig, + NKSpec, + ClockSpec, + SpMapping, + MemoryTarget, +) + + +# --------------------------------------------------------------------------- +# Shared helpers +# --------------------------------------------------------------------------- + +def _make_kernel(name, port_specs): + """Build a Kernel from {port_name: (BusType, width)} without any XML.""" + ports = {pname: Port(name=pname, ptype=ptype, width=width) + for pname, (ptype, width) in port_specs.items()} + return Kernel(name=name, component_xml_path=Path(), ports=ports) + + +@pytest.fixture +def cfg_file(tmp_path): + """Factory: write cfg text to a temp file and return its path.""" + def _write(content: str) -> Path: + p = tmp_path / "connectivity.cfg" + p.write_text(textwrap.dedent(content)) + return p + return _write + + +# --------------------------------------------------------------------------- +# Helper function tests +# --------------------------------------------------------------------------- + +class TestHelperFunctions: + + # --- _parse_target --- + + def test_parse_target_hbm(self): + t = _parse_target("HBM0") + assert t.domain == "HBM" + assert t.index == 0 + + def test_parse_target_ddr(self): + t = _parse_target("DDR3") + assert t.domain == "DDR" + assert t.index == 3 + + def test_parse_target_host(self): + # HOST has no numeric index; the parser stores "" for it. + t = _parse_target("HOST") + assert t.domain == "HOST" + assert t.index == "" + + def test_parse_target_mem(self): + # MEM likewise carries no index. + t = _parse_target("MEM") + assert t.domain == "MEM" + assert t.index == "" + + def test_parse_target_invalid_domain(self): + # An unrecognised domain name must be rejected. + with pytest.raises(ValueError, match="Unsupported memory domain"): + _parse_target("FLASH0") + + def test_parse_target_bad_format(self): + # The regex requires a single alphabetic word optionally followed by + # digits; extra tokens fail to match. + with pytest.raises(ValueError, match="Invalid memory target"): + _parse_target("HBM 0 extra") + + # --- _parse_nk_value --- + + def test_parse_nk_explicit_names(self): + spec = _parse_nk_value("dma:2:dma_0 dma_1") + assert spec.kernel_type == "dma" + assert spec.count == 2 + assert spec.instance_names == ["dma_0", "dma_1"] + + def test_parse_nk_auto_names(self): + # When no names are provided they are auto-generated as _0.._N-1. + spec = _parse_nk_value("foo:3") + assert spec.kernel_type == "foo" + assert spec.count == 3 + assert spec.instance_names == ["foo_0", "foo_1", "foo_2"] + + def test_parse_nk_partial_names_padded(self): + # Fewer names than count triggers auto-fill for the remainder. + spec = _parse_nk_value("foo:3:foo_0") + assert spec.count == 3 + assert spec.instance_names == ["foo_0", "foo_1", "foo_2"] + + def test_parse_nk_bad_format(self): + # A value without a colon does not match the expected pattern. + with pytest.raises(ValueError, match="Invalid nk entry"): + _parse_nk_value("dma") + + # --- _parse_stream_connect_value --- + + def test_parse_stream_connect(self): + sc = _parse_stream_connect_value("src_inst.out_port:dst_inst.in_port") + assert sc.src_inst == "src_inst" + assert sc.src_port == "out_port" + assert sc.dst_inst == "dst_inst" + assert sc.dst_port == "in_port" + + def test_parse_stream_connect_bad(self): + # Missing the colon separator between src and dst is invalid. + with pytest.raises(ValueError, match="Invalid stream_connect"): + _parse_stream_connect_value("src_inst.out_port") + + # --- _parse_sp_value --- + + def test_parse_sp_hbm(self): + sp = _parse_sp_value("dma_0.m_axi_gmem:HBM2") + assert sp.inst == "dma_0" + assert sp.port == "m_axi_gmem" + assert sp.target.domain == "HBM" + assert sp.target.index == 2 + + def test_parse_sp_bad_format(self): + # No colon → cannot split into instance.port and target. + with pytest.raises(ValueError, match="Invalid sp"): + _parse_sp_value("dma_0.m_axi_gmem") + + # --- _parse_debug_net_value --- + + def test_parse_debug_net(self): + dn = _parse_debug_net_value("my_inst.my_port") + assert dn.inst == "my_inst" + assert dn.port == "my_port" + + def test_parse_debug_net_bad(self): + # A value with no dot does not match the expected pattern. + with pytest.raises(ValueError, match="Invalid debug net"): + _parse_debug_net_value("no_dot") + + # --- _resolve_port_name_for_kernel --- + + def test_resolve_port_exact_match(self): + # When the requested name matches a port exactly it is returned unchanged. + k = Kernel(name="k", component_xml_path=Path(), + ports={"m_axi_gmem": Port(name="m_axi_gmem", ptype=BusType.AXI4FULL, width=512)}) + assert _resolve_port_name_for_kernel(k, "m_axi_gmem") == "m_axi_gmem" + + def test_resolve_port_case_insensitive(self): + # A differently-cased request resolves to the canonical port name from the kernel. + k = Kernel(name="k", component_xml_path=Path(), + ports={"M_AXI_GMEM": Port(name="M_AXI_GMEM", ptype=BusType.AXI4FULL, width=512)}) + assert _resolve_port_name_for_kernel(k, "m_axi_gmem") == "M_AXI_GMEM" + + def test_resolve_port_unknown_raises(self): + # A name that does not appear in the kernel's ports raises KeyError. + k = Kernel(name="k", component_xml_path=Path(), + ports={"axis_in": Port(name="axis_in", ptype=BusType.AXIS, width=64)}) + with pytest.raises(KeyError, match="not found"): + _resolve_port_name_for_kernel(k, "nonexistent") + + +# --------------------------------------------------------------------------- +# parse_connectivity_file tests +# --------------------------------------------------------------------------- + +class TestParseConnectivityFile: + + def test_empty_file(self, cfg_file): + cfg = parse_connectivity_file(cfg_file("")) + assert cfg.nk == [] + assert cfg.streams == [] + assert cfg.sps == [] + assert cfg.clocks == [] + assert cfg.net.enabled_eth == set() + + def test_comment_lines_ignored(self, cfg_file): + # Lines starting with # or ; are treated as comments and produce no output. + cfg = parse_connectivity_file(cfg_file("""\ + # this is a comment + ; so is this + """)) + assert cfg.nk == [] + + def test_nk_parsed(self, cfg_file): + cfg_inside = parse_connectivity_file(cfg_file("""\ + [connectivity] + nk=dma:1:dma_0 + """)) + assert len(cfg_inside.nk) == 1 + assert cfg_inside.nk[0].kernel_type == "dma" + assert cfg_inside.nk[0].instance_names == ["dma_0"] + + def test_stream_connect_parsed(self, cfg_file): + cfg_inside = parse_connectivity_file(cfg_file("""\ + [connectivity] + stream_connect=a.out:b.in + """)) + assert len(cfg_inside.streams) == 1 + sc = cfg_inside.streams[0] + assert sc.src_inst == "a" and sc.src_port == "out" + assert sc.dst_inst == "b" and sc.dst_port == "in" + + def test_sp_parsed(self, cfg_file): + cfg_inside = parse_connectivity_file(cfg_file("""\ + [connectivity] + sp=dma_0.m_axi_gmem:HBM0 + """)) + assert len(cfg_inside.sps) == 1 + sp = cfg_inside.sps[0] + assert sp.inst == "dma_0" and sp.port == "m_axi_gmem" + assert sp.target.domain == "HBM" and sp.target.index == 0 + + def test_clock_section_committed(self, cfg_file): + # A complete [clock] block followed by another section is committed. + cfg = parse_connectivity_file(cfg_file("""\ + [clock] + krnl=dma_0 + freqhz=300000000 + [connectivity] + """)) + assert len(cfg.clocks) == 1 + assert cfg.clocks[0].inst == "dma_0" + assert cfg.clocks[0].freq_hz == 300_000_000 + + def test_multiple_clock_sections(self, cfg_file): + # Each [clock] block produces an independent ClockSpec. + cfg = parse_connectivity_file(cfg_file("""\ + [clock] + krnl=dma_0 + freqhz=300000000 + [clock] + krnl=pass_0 + freqhz=500000000 + """)) + assert len(cfg.clocks) == 2 + insts = {c.inst for c in cfg.clocks} + assert insts == {"dma_0", "pass_0"} + + def test_clock_missing_equals_raises(self, cfg_file): + # A line inside [clock] that is not a key=value pair raises ValueError. + with pytest.raises(ValueError, match="Invalid line in \\[clock\\]"): + parse_connectivity_file(cfg_file("""\ + [clock] + not_an_assignment + """)) + + def test_clock_missing_freqhz_raises(self, cfg_file): + # A [clock] block with krnl but no freqhz is incomplete and must raise. + with pytest.raises(ValueError, match="Incomplete"): + parse_connectivity_file(cfg_file("""\ + [clock] + krnl=dma_0 + [connectivity] + """)) + + def test_clock_invalid_freqhz_raises(self, cfg_file): + # A non-integer freqhz value must raise ValueError. + with pytest.raises(ValueError, match="Invalid freqhz"): + parse_connectivity_file(cfg_file("""\ + [clock] + krnl=dma_0 + freqhz=not_a_number + [connectivity] + """)) + + def test_clock_committed_at_eof(self, cfg_file): + # A [clock] block that is the last section in the file (no trailing + # section header) must still be committed by the post-loop call. + cfg = parse_connectivity_file(cfg_file("""\ + [clock] + krnl=dma_0 + freqhz=250000000 + """)) + assert len(cfg.clocks) == 1 + assert cfg.clocks[0].inst == "dma_0" + + def test_network_section_eth_enabled(self, cfg_file): + cfg = parse_connectivity_file(cfg_file("""\ + [network] + eth_0=1 + """)) + assert 0 in cfg.net.enabled_eth + + def test_network_section_eth_disabled(self, cfg_file): + # A zero value means the interface is not enabled. + cfg = parse_connectivity_file(cfg_file("""\ + [network] + eth_0=0 + """)) + assert cfg.net.enabled_eth == set() + + def test_network_invalid_value_treated_as_zero(self, cfg_file): + # A non-integer eth value is silently treated as 0 (not enabled). + cfg = parse_connectivity_file(cfg_file("""\ + [network] + eth_0=bad + """)) + assert cfg.net.enabled_eth == set() + + def test_network_unknown_key_ignored(self, cfg_file): + # Unrecognised keys in [network] are silently skipped. + cfg = parse_connectivity_file(cfg_file("""\ + [network] + foo=1 + """)) + assert cfg.net.enabled_eth == set() + + def test_network_missing_equals_raises(self, cfg_file): + with pytest.raises(ValueError, match="Invalid line in \\[network\\]"): + parse_connectivity_file(cfg_file("""\ + [network] + eth_0 + """)) + + def test_user_region_pre_synth_relative_path(self, cfg_file, tmp_path): + # A relative pre_synth path is resolved relative to the cfg file's parent. + cfg = parse_connectivity_file(cfg_file("""\ + [user_region] + pre_synth=setup.tcl + """)) + expected = str((tmp_path / "setup.tcl").resolve()) + assert cfg.user_region.pre_synth_tcls == [expected] + + def test_user_region_pre_synth_absolute_path(self, cfg_file): + cfg = parse_connectivity_file(cfg_file("""\ + [user_region] + pre_synth=/absolute/path/to/setup.tcl + """)) + assert cfg.user_region.pre_synth_tcls == [ + "/absolute/path/to/setup.tcl"] + + def test_user_region_empty_pre_synth_raises(self, cfg_file): + with pytest.raises(ValueError, match="empty pre_synth"): + parse_connectivity_file(cfg_file("""\ + [user_region] + pre_synth= + """)) + + def test_user_region_unknown_key_ignored(self, cfg_file): + # Unrecognised keys in [user_region] are silently skipped. + cfg = parse_connectivity_file(cfg_file("""\ + [user_region] + unknown_key=value + """)) + assert cfg.user_region.pre_synth_tcls == [] + + def test_user_region_missing_equals_raises(self, cfg_file): + with pytest.raises(ValueError, match="Invalid line in \\[user_region\\]"): + parse_connectivity_file(cfg_file("""\ + [user_region] + not_an_assignment + """)) + + def test_debug_net_parsed(self, cfg_file): + cfg = parse_connectivity_file(cfg_file("""\ + [debug] + net=my_inst.my_port + """)) + assert len(cfg.debug.nets) == 1 + assert cfg.debug.nets[0].inst == "my_inst" + assert cfg.debug.nets[0].port == "my_port" + + def test_debug_unknown_key_raises(self, cfg_file): + with pytest.raises(ValueError, match="Invalid key"): + parse_connectivity_file(cfg_file("""\ + [debug] + foo=bar + """)) + + def test_debug_missing_equals_raises(self, cfg_file): + with pytest.raises(ValueError, match="Invalid line in \\[debug\\]"): + parse_connectivity_file(cfg_file("""\ + [debug] + no_equals_here + """)) + + def test_unknown_section_lines_silently_ignored(self, cfg_file): + # Lines under an unrecognised section header produce no error. + cfg = parse_connectivity_file(cfg_file("""\ + [totally_unknown] + some_key=some_value + """)) + assert cfg.nk == [] + + def test_missing_file_raises(self, tmp_path): + with pytest.raises(Exception): + parse_connectivity_file(tmp_path / "nonexistent.cfg") + + +# --------------------------------------------------------------------------- +# apply_config_to_instances tests +# --------------------------------------------------------------------------- + +class TestApplyConfigToInstances: + + # --- instantiation from nk --- + + def test_instantiates_kernels_from_nk(self): + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig(nk=[NKSpec("dma", 1, ["dma_0"])]) + instances = apply_config_to_instances(cfg, [k]) + assert len(instances) == 1 + assert instances[0].name == "dma_0" + assert instances[0].kernel is k + + def test_multiple_nk_entries(self): + dma = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + pt = _make_kernel("passthrough", {"axis_in": (BusType.AXIS, 64)}) + cfg = ConnectivityConfig(nk=[ + NKSpec("dma", 1, ["dma_0"]), + NKSpec("passthrough", 2, ["pt_0", "pt_1"]), + ]) + instances = apply_config_to_instances(cfg, [dma, pt]) + names = {i.name for i in instances} + assert names == {"dma_0", "pt_0", "pt_1"} + + def test_unknown_kernel_type_raises(self): + cfg = ConnectivityConfig( + nk=[NKSpec("nonexistent", 1, ["nonexistent_0"])]) + with pytest.raises(KeyError, match="nonexistent"): + apply_config_to_instances(cfg, []) + + def test_duplicate_instance_name_raises(self): + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig(nk=[ + NKSpec("dma", 1, ["dma_0"]), + NKSpec("dma", 1, ["dma_0"]), # duplicate + ]) + with pytest.raises(ValueError, match="Duplicate"): + apply_config_to_instances(cfg, [k]) + + # --- clock attachment --- + + def test_clock_attached_to_instance(self): + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + clocks=[ClockSpec(inst="dma_0", freq_hz=300_000_000)], + ) + instances = apply_config_to_instances(cfg, [k]) + inst = next(i for i in instances if i.name == "dma_0") + assert inst.params["clock_hz"] == 300_000_000 + + def test_clock_unknown_instance_raises(self): + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + clocks=[ClockSpec(inst="nonexistent", freq_hz=300_000_000)], + ) + with pytest.raises(KeyError, match="nonexistent"): + apply_config_to_instances(cfg, [k]) + + # --- sp mapping --- + + def test_sp_mapping_applied(self): + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + sps=[SpMapping("dma_0", "m_axi_gmem", MemoryTarget("HBM", 2))], + ) + instances = apply_config_to_instances(cfg, [k]) + inst = next(i for i in instances if i.name == "dma_0") + assert inst.params["mem_sp"]["m_axi_gmem"] == { + "domain": "HBM", "index": 2} + + def test_sp_unknown_instance_raises(self): + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + sps=[SpMapping("nonexistent", "m_axi_gmem", + MemoryTarget("HBM", 0))], + ) + with pytest.raises(KeyError, match="nonexistent"): + apply_config_to_instances(cfg, [k]) + + def test_sp_non_axi4full_port_raises(self): + k = _make_kernel("dma", { + "m_axi_gmem": (BusType.AXI4FULL, 512), + "s_axi_control": (BusType.AXILITE, 32), + }) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + sps=[SpMapping("dma_0", "s_axi_control", MemoryTarget("HBM", 0))], + ) + with pytest.raises(ValueError, match="not an AXI4FULL port"): + apply_config_to_instances(cfg, [k]) + + def test_sp_port_name_case_insensitive(self): + # Port defined as uppercase; sp references it in lowercase. + k = _make_kernel("dma", {"M_AXI_GMEM": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + sps=[SpMapping("dma_0", "m_axi_gmem", MemoryTarget("DDR", 0))], + ) + instances = apply_config_to_instances(cfg, [k]) + inst = next(i for i in instances if i.name == "dma_0") + # Stored under the canonical (uppercase) name. + assert "M_AXI_GMEM" in inst.params["mem_sp"] + + # --- AXI4FULL fallback --- + + def test_axi4full_fallback_mem_assigned(self): + # An AXI4FULL port with no explicit sp gets the MEM fallback. + k = _make_kernel("dma", {"m_axi_gmem": (BusType.AXI4FULL, 512)}) + cfg = ConnectivityConfig(nk=[NKSpec("dma", 1, ["dma_0"])]) + instances = apply_config_to_instances(cfg, [k]) + inst = next(i for i in instances if i.name == "dma_0") + assert inst.params["mem_sp"]["m_axi_gmem"] == { + "domain": "MEM", "index": ""} + + def test_explicit_sp_not_overwritten_by_fallback(self): + # Explicit sp for one port, fallback for the other — both coexist correctly. + k = _make_kernel("dma", { + "m_axi_gmem0": (BusType.AXI4FULL, 512), + "m_axi_gmem1": (BusType.AXI4FULL, 512), + }) + cfg = ConnectivityConfig( + nk=[NKSpec("dma", 1, ["dma_0"])], + sps=[SpMapping("dma_0", "m_axi_gmem0", MemoryTarget("HBM", 3))], + ) + instances = apply_config_to_instances(cfg, [k]) + inst = next(i for i in instances if i.name == "dma_0") + assert inst.params["mem_sp"]["m_axi_gmem0"] == { + "domain": "HBM", "index": 3} + assert inst.params["mem_sp"]["m_axi_gmem1"] == { + "domain": "MEM", "index": ""} + + def test_no_axi4full_ports_mem_sp_empty(self): + # Kernels with no AXI4FULL ports still get mem_sp={} (empty, not absent). + k = _make_kernel("passthrough", { + "axis_in": (BusType.AXIS, 64), + "axis_out": (BusType.AXIS, 64), + }) + cfg = ConnectivityConfig(nk=[NKSpec("passthrough", 1, ["pt_0"])]) + instances = apply_config_to_instances(cfg, [k]) + inst = next(i for i in instances if i.name == "pt_0") + assert inst.params["mem_sp"] == {} diff --git a/packaging/debian/changelog b/packaging/debian/changelog new file mode 100644 index 00000000..c2ed9e1e --- /dev/null +++ b/packaging/debian/changelog @@ -0,0 +1,5 @@ +slash (UNRELEASED) UNRELEASED; urgency=medium + + * Testing release. + + -- Vlad-Gabriel Serbu Tue, 03 Mar 2026 15:09:17 +0000 diff --git a/packaging/debian/control b/packaging/debian/control new file mode 100644 index 00000000..a6ad9ca6 --- /dev/null +++ b/packaging/debian/control @@ -0,0 +1,98 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +Source: slash +Section: utils +Priority: optional +Maintainer: Vlad-Gabriel Serbu +Rules-Requires-Root: no +Build-Depends: debhelper-compat (= 13), bash, build-essential, cmake, libcli11-dev, libinih-dev, libjsoncpp-dev, libsystemd-dev, libxml2-dev, libzmq3-dev, ninja-build, pkg-config, python3.10, python3-jinja2, python3-pip, python3-setuptools, python3-venv, python3-wheel, rsync, zlib1g-dev +Standards-Version: 4.6.0.1 + +Package: slash-dev +Architecture: all +Depends: slash-sim-emu-dev (= ${binary:Version}), libslash-dev (= ${binary:Version}), libvrtd-dev (= ${binary:Version}) +Description: SLASH/VRT System Full (development files) + +Package: slash +Architecture: all +Depends: slash-sim-emu (= ${binary:Version}), slash-dkms (= ${binary:Version}), libslash (= ${binary:Version}), vrtd (= ${binary:Version}), libvrtd (= ${binary:Version}) +Description: SLASH/VRT System Full + +Package: slash-sim-emu-dev +Architecture: all +Depends: slash-sim-emu (= ${binary:Version}), slashkit (= ${binary:Version}), libvrt-dev (= ${binary:Version}) +Description: SLASH/VRT System for simulation and emulation (development files) + +Package: slash-sim-emu +Architecture: all +Depends: libvrt (= ${binary:Version}) +Description: SLASH/VRT System for simulation and emulation + +Package: slash-dkms +Architecture: all +Depends: dkms, gcc, make, ${misc:Depends} +Provides: slash-kernel-module +Description: SLASH kernel module (DKMS) + +Package: libslash +Architecture: any +Depends: ${shlibs:Depends}, ${misc:Depends} +Description: Library for interacting with the SLASH kernel module + +Package: libslash-dev +Architecture: any +Depends: libslash (= ${binary:Version}), ${misc:Depends} +Description: Library for interacting with the SLASH kernel module (development files) + +Package: vrtd +Architecture: any +Depends: libslash (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: VRTd daemon for managing VRT devices + +Package: libvrtd +Architecture: any +Depends: libslash (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Library for interacting with the VRTd daemon for managing VRT devices + +Package: libvrtd-dev +Architecture: any +Depends: libvrtd (= ${binary:Version}), libslash-dev (= ${binary:Version}), ${misc:Depends} +Description: Library for interacting with the VRTd daemon for managing VRT devices (development files) + +Package: libvrt +Architecture: any +Depends: libvrtd (= ${binary:Version}), systemd-sysusers, ${shlibs:Depends}, ${misc:Depends} +Description: VRT Runtime + +Package: libvrt-dev +Architecture: any +Depends: libvrt (= ${binary:Version}), libvrtd-dev (= ${binary:Version}), libjsoncpp-dev, libxml2-dev, libzmq3-dev, zlib1g-dev, ${misc:Depends} +Description: VRT Runtime (development files) + +Package: v80-smi +Architecture: any +Depends: libvrt (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: V80 System Management Interface + +Package: slashkit +Architecture: any +Depends: python3, python3-jinja2, libzmq3-dev, ${misc:Depends} +Description: SLASH Linker diff --git a/packaging/debian/libslash-dev.install b/packaging/debian/libslash-dev.install new file mode 100644 index 00000000..fcf1596c --- /dev/null +++ b/packaging/debian/libslash-dev.install @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/include/slash/ +usr/lib/*/cmake/slash/ diff --git a/packaging/debian/libslash.install b/packaging/debian/libslash.install new file mode 100644 index 00000000..f824728f --- /dev/null +++ b/packaging/debian/libslash.install @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/lib/*/libslash.so +usr/lib/*/libslash.so.* diff --git a/packaging/debian/libvrt-dev.install b/packaging/debian/libvrt-dev.install new file mode 100644 index 00000000..f2f0f22b --- /dev/null +++ b/packaging/debian/libvrt-dev.install @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/include/vrt/ +usr/lib/*/cmake/vrt/ diff --git a/packaging/debian/libvrt.install b/packaging/debian/libvrt.install new file mode 100644 index 00000000..4beb498e --- /dev/null +++ b/packaging/debian/libvrt.install @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/lib/*/libvrt.so +usr/lib/*/libvrt.so.* diff --git a/packaging/debian/libvrtd-dev.install b/packaging/debian/libvrtd-dev.install new file mode 100644 index 00000000..17d99d06 --- /dev/null +++ b/packaging/debian/libvrtd-dev.install @@ -0,0 +1,22 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/include/vrtd/ +usr/lib/*/cmake/vrtd/ diff --git a/packaging/debian/libvrtd.install b/packaging/debian/libvrtd.install new file mode 100644 index 00000000..70089415 --- /dev/null +++ b/packaging/debian/libvrtd.install @@ -0,0 +1,24 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/lib/*/libvrtd.so +usr/lib/*/libvrtd.so.* +usr/lib/*/libvrtdpp.so +usr/lib/*/libvrtdpp.so.* diff --git a/packaging/debian/rules b/packaging/debian/rules new file mode 100755 index 00000000..2deda5ad --- /dev/null +++ b/packaging/debian/rules @@ -0,0 +1,44 @@ +#!/usr/bin/make -f + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +export DH_VERBOSE=1 +ARTIFACTS_DIR=$(CURDIR)/deb + +%: + dh $@ --with dkms + +override_dh_auto_configure: + bash scripts/pconfigure.sh lib/$(DEB_HOST_MULTIARCH) + +override_dh_auto_build: + bash scripts/pbuild.sh + +override_dh_auto_test: + true + +override_dh_auto_install: + bash scripts/pinstall.sh $(CURDIR)/debian/tmp + +override_dh_builddeb: + mkdir -p $(ARTIFACTS_DIR) + dh_builddeb $@ --destdir=$(ARTIFACTS_DIR) + diff --git a/packaging/debian/slash-dkms.dkms b/packaging/debian/slash-dkms.dkms new file mode 100644 index 00000000..4841d92b --- /dev/null +++ b/packaging/debian/slash-dkms.dkms @@ -0,0 +1,30 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +PACKAGE_NAME="slash" +PACKAGE_VERSION="@VERSION@" + +BUILT_MODULE_NAME[0]="slash" +BUILT_MODULE_LOCATION[0]="driver" +DEST_MODULE_LOCATION[0]="/updates/dkms" +AUTOINSTALL="yes" + +MAKE[0]="make -C driver KDIR=/lib/modules/${kernelver}/build SLASH_VERSION=${PACKAGE_VERSION}" +CLEAN="make -C driver KDIR=/lib/modules/${kernelver}/build clean" diff --git a/packaging/debian/slash-dkms.install b/packaging/debian/slash-dkms.install new file mode 100644 index 00000000..d0496a33 --- /dev/null +++ b/packaging/debian/slash-dkms.install @@ -0,0 +1,27 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +driver/*.c usr/src/slash-@VERSION@/driver/ +driver/*.h usr/src/slash-@VERSION@/driver/ +driver/Makefile usr/src/slash-@VERSION@/driver/ +driver/kcompat usr/src/slash-@VERSION@/driver/ +driver/libslash/include/slash/uapi usr/src/slash-@VERSION@/driver/libslash/include/slash/ + +submodules/qdma_drv/QDMA/linux-kernel/driver/libqdma/ usr/src/slash-@VERSION@/driver/ diff --git a/packaging/debian/slashkit.install b/packaging/debian/slashkit.install new file mode 100644 index 00000000..c047d8ff --- /dev/null +++ b/packaging/debian/slashkit.install @@ -0,0 +1,24 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/bin/slashkit +usr/lib/python3.10/dist-packages/slashkit/ +usr/lib/python3.10/dist-packages/slashkit-*.dist-info/ +usr/lib/*/cmake/SlashTools/ diff --git a/packaging/debian/source/format b/packaging/debian/source/format new file mode 100644 index 00000000..89ae9db8 --- /dev/null +++ b/packaging/debian/source/format @@ -0,0 +1 @@ +3.0 (native) diff --git a/packaging/debian/v80-smi.install b/packaging/debian/v80-smi.install new file mode 100644 index 00000000..6d654294 --- /dev/null +++ b/packaging/debian/v80-smi.install @@ -0,0 +1,21 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/bin/v80-smi diff --git a/packaging/debian/vrtd.dirs b/packaging/debian/vrtd.dirs new file mode 100644 index 00000000..df59628e --- /dev/null +++ b/packaging/debian/vrtd.dirs @@ -0,0 +1,21 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +etc/vrt/vrtd.conf.d diff --git a/packaging/debian/vrtd.install b/packaging/debian/vrtd.install new file mode 100644 index 00000000..7c1ef823 --- /dev/null +++ b/packaging/debian/vrtd.install @@ -0,0 +1,25 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +usr/bin/vrtd usr/lib/vrt/ +usr/bin/vrtd-* usr/lib/vrt/ + +vrt/vrtd/conf/vrtd.conf etc/vrt/ +vrt/vrtd/sysusers/vrtd.conf usr/lib/sysusers.d/ diff --git a/packaging/debian/vrtd.postinst b/packaging/debian/vrtd.postinst new file mode 100644 index 00000000..faaa9ce0 --- /dev/null +++ b/packaging/debian/vrtd.postinst @@ -0,0 +1,36 @@ +#!/bin/sh + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -e + +case "$1" in + configure) + if command -v systemd-sysusers >/dev/null 2>&1; then + systemd-sysusers /usr/lib/sysusers.d/vrtd.conf + fi + if command -v udevadm >/dev/null 2>&1; then + udevadm control --reload-rules && udevadm trigger || true + fi + ;; +esac + +exit 0 diff --git a/packaging/rpm/slash.spec b/packaging/rpm/slash.spec new file mode 100644 index 00000000..a18ccd59 --- /dev/null +++ b/packaging/rpm/slash.spec @@ -0,0 +1,333 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +%global debug_package %{nil} +%global dkms_name slash +%global dkms_version %{version} + +Name: slash +Version: %{_version} +Release: 1%{?dist} +Summary: SLASH/VRT System +License: MIT +URL: https://github.com/Xilinx/SLASH + +Source0: %{name}-%{version}.tar.gz + +BuildRequires: bash +BuildRequires: cmake +BuildRequires: make +BuildRequires: gcc +BuildRequires: gcc-c++ +BuildRequires: ninja-build +BuildRequires: pkg-config +BuildRequires: cli11-devel +BuildRequires: cppzmq-devel +BuildRequires: inih-devel +BuildRequires: jsoncpp-devel +BuildRequires: libxml2-devel +BuildRequires: systemd-devel +BuildRequires: zeromq-devel +BuildRequires: zlib-devel +BuildRequires: rsync +BuildRequires: python3 +BuildRequires: python3-devel +BuildRequires: python3-jinja2 +BuildRequires: python3-pip +BuildRequires: python3-setuptools +BuildRequires: python3-wheel +BuildRequires: systemd-rpm-macros + +# ---- Metapackages ---- + +%description +SLASH/VRT System Full + +%package -n slash-devel +Summary: SLASH/VRT System Full (development files) +Requires: slash-sim-emu-devel = %{version}-%{release} +Requires: libslash-devel = %{version}-%{release} +Requires: libvrtd-devel = %{version}-%{release} +BuildArch: noarch + +%description -n slash-devel +SLASH/VRT System Full (development files) + +%package -n slash-sim-emu +Summary: SLASH/VRT System for simulation and emulation +Requires: libvrt = %{version}-%{release} +BuildArch: noarch + +%description -n slash-sim-emu +SLASH/VRT System for simulation and emulation + +%package -n slash-sim-emu-devel +Summary: SLASH/VRT System for simulation and emulation (development files) +Requires: slash-sim-emu = %{version}-%{release} +Requires: slashkit = %{version}-%{release} +Requires: libvrt-devel = %{version}-%{release} +BuildArch: noarch + +%description -n slash-sim-emu-devel +SLASH/VRT System for simulation and emulation (development files) + +%package -n slash-dkms +Summary: SLASH kernel module (DKMS) +Requires: dkms, gcc, make +BuildArch: noarch + +%description -n slash-dkms +SLASH kernel module (DKMS) + +# ---- Libraries ---- + +%package -n libslash +Summary: Library for interacting with the SLASH kernel module + +%description -n libslash +Library for interacting with the SLASH kernel module + +%package -n libslash-devel +Summary: Library for interacting with the SLASH kernel module (development files) +Requires: libslash = %{version}-%{release} + +%description -n libslash-devel +Library for interacting with the SLASH kernel module (development files) + +%package -n vrtd +Summary: VRTd daemon for managing VRT devices +Requires: libslash = %{version}-%{release} +%{?systemd_requires} + +%description -n vrtd +VRTd daemon for managing VRT devices + +%package -n libvrtd +Summary: Library for interacting with the VRTd daemon +Requires: libslash = %{version}-%{release} + +%description -n libvrtd +Library for interacting with the VRTd daemon for managing VRT devices + +%package -n libvrtd-devel +Summary: Library for interacting with the VRTd daemon (development files) +Requires: libvrtd = %{version}-%{release} +Requires: libslash-devel = %{version}-%{release} + +%description -n libvrtd-devel +Library for interacting with the VRTd daemon for managing VRT devices (development files) + +%package -n libvrt +Summary: VRT Runtime +Requires: libvrtd = %{version}-%{release} +Requires: systemd + +%description -n libvrt +VRT Runtime + +%package -n libvrt-devel +Summary: VRT Runtime (development files) +Requires: libvrt = %{version}-%{release} +Requires: libvrtd-devel = %{version}-%{release} +Requires: jsoncpp-devel +Requires: libxml2-devel +Requires: zeromq-devel +Requires: zlib-devel + +%description -n libvrt-devel +VRT Runtime (development files) + +%package -n v80-smi +Summary: V80 System Management Interface +Requires: libvrt = %{version}-%{release} + +%description -n v80-smi +V80 System Management Interface + +%package -n slashkit +Summary: SLASH Linker +Requires: python3 +Requires: python3-jinja2 +Requires: cppzmq-devel + +%description -n slashkit +SLASH Linker + +# ---- Build ---- + +%prep +%autosetup -n %{name}-%{version} + +%build + +bash scripts/pconfigure.sh %{_lib} +bash scripts/pbuild.sh + +%install +bash scripts/pinstall.sh %{buildroot} + +# systemd units (mirrors debian/rules rsync lines) +install -D -m 0644 vrt/vrtd/systemd/vrtd.service \ + %{buildroot}%{_unitdir}/vrtd.service +install -D -m 0644 vrt/vrtd/systemd/vrtd.socket \ + %{buildroot}%{_unitdir}/vrtd.socket + +# sysusers (mirrors debian/vrtd.install + vrtd.postinst) +install -D -m 0644 vrt/vrtd/sysusers/vrtd.conf \ + %{buildroot}%{_sysusersdir}/vrtd.conf + +# vrtd config and drop-in directory +install -D -m 0644 vrt/vrtd/conf/vrtd.conf \ + %{buildroot}%{_sysconfdir}/vrt/vrtd.conf +install -d %{buildroot}%{_sysconfdir}/vrt/vrtd.conf.d + +# udev rules (mirrors debian/vrtd.udev) +install -D -m 0644 vrt/vrtd/udev/99-vrtd.rules \ + %{buildroot}%{_udevrulesdir}/99-vrtd.rules + +# DKMS source tree (mirrors debian/slash-dkms.install exactly) +install -d %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/libslash/include/slash + +install -m 0644 driver/*.c %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/ +install -m 0644 driver/*.h %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/ +install -m 0644 driver/Makefile %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/ + +cp -a driver/kcompat %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/ + +cp -a driver/libslash/include/slash/uapi \ + %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/libslash/include/slash/ + +cp -a submodules/qdma_drv/QDMA/linux-kernel/driver/libqdma \ + %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/driver/ + +# DKMS config (equivalent to debian/slash-dkms.dkms) +cat > %{buildroot}%{_usrsrc}/%{dkms_name}-%{dkms_version}/dkms.conf << 'EOF' +PACKAGE_NAME="slash" +PACKAGE_VERSION="%{dkms_version}" + +BUILT_MODULE_NAME[0]="slash" +BUILT_MODULE_LOCATION[0]="driver" +DEST_MODULE_LOCATION[0]="/updates/dkms" +AUTOINSTALL="yes" + +MAKE[0]="make -C driver KDIR=/lib/modules/${kernelver}/build SLASH_VERSION=${PACKAGE_VERSION}" +CLEAN="make -C driver KDIR=/lib/modules/${kernelver}/build clean" +EOF + +# ---- File lists ---- +# You must list every file each subpackage owns. +# Adjust these globs to match your actual installed files. + +%files +# metapackage — empty + +%files -n slash-devel +# metapackage — empty + +%files -n slash-sim-emu +# metapackage — empty + +%files -n slash-sim-emu-devel +# metapackage — empty + +%files -n slash-dkms +%{_prefix}/src/%{dkms_name}-%{dkms_version}/ + +%files -n libslash +%{_libdir}/libslash.so +%{_libdir}/libslash.so.* + +%files -n libslash-devel +%{_includedir}/slash/ +%{_libdir}/cmake/slash/ + +%pre -n vrtd +%sysusers_create_package vrtd vrt/vrtd/sysusers/vrtd.conf + +%post -n vrtd +%systemd_post vrtd.service vrtd.socket +udevadm control --reload-rules && udevadm trigger 2>/dev/null || : + +%preun -n vrtd +%systemd_preun vrtd.service vrtd.socket + +%postun -n vrtd +%systemd_postun_with_restart vrtd.service vrtd.socket +udevadm control --reload-rules && udevadm trigger 2>/dev/null || : + +%files -n vrtd +%{_bindir}/vrtd +%{_bindir}/vrtd-* +%{_unitdir}/vrtd.service +%{_unitdir}/vrtd.socket +%{_udevrulesdir}/99-vrtd.rules +%{_sysusersdir}/vrtd.conf +%config(noreplace) %{_sysconfdir}/vrt/vrtd.conf +%dir %{_sysconfdir}/vrt/vrtd.conf.d + +%files -n libvrtd +%{_libdir}/libvrtd.so +%{_libdir}/libvrtd.so.* +%{_libdir}/libvrtdpp.so +%{_libdir}/libvrtdpp.so.* + +%files -n libvrtd-devel +%{_includedir}/vrtd/ +%{_libdir}/cmake/vrtd/ + +%files -n libvrt +%{_libdir}/libvrt.so +%{_libdir}/libvrt.so.* + +%files -n libvrt-devel +%{_includedir}/vrt/ +%{_libdir}/cmake/vrt/ + +%files -n v80-smi +%{_bindir}/v80-smi + +%files -n slashkit +%{_bindir}/slashkit +%{python3_sitelib}/slashkit/ +%{python3_sitelib}/slashkit-*.dist-info/ +%{_libdir}/cmake/SlashTools/ + +# ---- Scriptlets ---- + +%post -n slash-dkms +dkms add -m %{dkms_name} -v %{dkms_version} --rpm_safe_upgrade +dkms build -m %{dkms_name} -v %{dkms_version} +dkms install -m %{dkms_name} -v %{dkms_version} + +%preun -n slash-dkms +dkms remove -m %{dkms_name} -v %{dkms_version} --all --rpm_safe_upgrade + +%post -n libslash -p /sbin/ldconfig +%postun -n libslash -p /sbin/ldconfig + +%post -n libvrtd -p /sbin/ldconfig +%postun -n libvrtd -p /sbin/ldconfig + +%post -n libvrt -p /sbin/ldconfig +%postun -n libvrt -p /sbin/ldconfig + +%changelog +* Thu Jun 12 2025 Vlad-Gabriel Serbu - %{_version}-1 +- Initial RPM packaging diff --git a/packaging/version b/packaging/version new file mode 100644 index 00000000..6e8bf73a --- /dev/null +++ b/packaging/version @@ -0,0 +1 @@ +0.1.0 diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 00000000..a73d287b --- /dev/null +++ b/requirements.txt @@ -0,0 +1,6 @@ +pyzmq +jinja2 +pytest +pytest-cov +ruff +autopep8 diff --git a/scripts/Dockerfile.package-rocky b/scripts/Dockerfile.package-rocky new file mode 100644 index 00000000..000c0266 --- /dev/null +++ b/scripts/Dockerfile.package-rocky @@ -0,0 +1,24 @@ +FROM rockylinux:9 + +ARG USER_ID=1000 + +RUN dnf install -y epel-release +RUN dnf config-manager --set-enabled crb +RUN dnf distro-sync -y +RUN dnf install -y python3 python3-devel python3-jinja2 python3-pip python3-setuptools python3-wheel \ + git langpacks-en cmake gcc gcc-c++ pkg-config ninja-build rsync systemd-rpm-macros rpm-build createrepo_c procps-ng \ + cli11-devel cppzmq-devel inih-devel jsoncpp-devel libxml2-devel systemd-devel zeromq-devel zlib-devel libyaml-devel \ + ncurses-compat-libs glib2 libXext libXrender-devel pixman lsb_release + +# Setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone +ENV LC_ALL=en_US.utf-8 + +# Adding the slash user +RUN useradd -m -U -u $USER_ID slash +USER slash + +# Again, setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +ENV LC_ALL=en_US.utf-8 diff --git a/scripts/Dockerfile.package-ubuntu b/scripts/Dockerfile.package-ubuntu new file mode 100644 index 00000000..27b21919 --- /dev/null +++ b/scripts/Dockerfile.package-ubuntu @@ -0,0 +1,26 @@ +FROM ubuntu:22.04 + +ARG USER_ID=1000 + +ENV DEBIAN_FRONTEND=noninteractive + +RUN apt-get update -qq && \ + apt-get install -y --no-install-recommends \ + build-essential ca-certificates debhelper devscripts dkms apt-utils pkg-config \ + rsync bash cmake git ninja-build \ + libcli11-dev libinih-dev libjsoncpp-dev libsystemd-dev libxml2-dev libzmq3-dev zlib1g-dev libyaml-dev \ + python3 python3-venv python3-jinja2 python3-pip python3-setuptools python3-wheel \ + locales locales-all libtinfo5 libc6-dev-i386 libglib2.0-0 libsm6 libxext6 libxrender-dev libpixman-1-0 lsb-core + +# Setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone +ENV LC_ALL=en_US.utf-8 + +# Adding the slash user +RUN useradd -m -U -u $USER_ID slash +USER slash + +# Again, setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +ENV LC_ALL=en_US.utf-8 diff --git a/scripts/Dockerfile.run-rocky b/scripts/Dockerfile.run-rocky new file mode 100644 index 00000000..fd2c0cab --- /dev/null +++ b/scripts/Dockerfile.run-rocky @@ -0,0 +1,26 @@ +FROM rockylinux:9 + +ARG USER_ID=1000 + +RUN dnf install -y epel-release +RUN dnf config-manager --set-enabled crb +RUN dnf distro-sync -y +RUN dnf install -y git langpacks-en cmake gcc gcc-c++ pkg-config ninja-build rsync \ + ncurses-compat-libs glib2 libXext libXrender-devel pixman lsb_release + +COPY rpm/*.rpm /tmp +RUN dnf install -y /tmp/*.rpm + +# Setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone +ENV LC_ALL=en_US.utf-8 + +# Adding the slash user +RUN useradd -m -U -u $USER_ID slash +USER slash + +# Again, setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +ENV LC_ALL=en_US.utf-8 + diff --git a/scripts/Dockerfile.run-ubuntu b/scripts/Dockerfile.run-ubuntu new file mode 100644 index 00000000..65ad50c8 --- /dev/null +++ b/scripts/Dockerfile.run-ubuntu @@ -0,0 +1,35 @@ +FROM ubuntu:22.04 + +ARG USER_ID=1000 + +ENV DEBIAN_FRONTEND=noninteractive + +RUN apt-get update -qq && \ + apt-get install -y --no-install-recommends \ + build-essential ca-certificates pkg-config git rsync bash cmake git ninja-build \ + locales locales-all libtinfo5 libc6-dev-i386 libglib2.0-0 libsm6 libxext6 libxrender-dev libpixman-1-0 lsb-core + +COPY deb/*.deb /tmp +RUN apt install -y /tmp/slash-dev_*.deb \ + /tmp/slash-sim-emu-dev_*.deb \ + /tmp/slash-sim-emu_*.deb \ + /tmp/slashkit_*.deb \ + /tmp/libslash-dev_*.deb \ + /tmp/libslash_*.deb \ + /tmp/libvrtd-dev_*.deb \ + /tmp/libvrtd_*.deb \ + /tmp/libvrt-dev_*.deb \ + /tmp/libvrt_*.deb + +# Setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone +ENV LC_ALL=en_US.utf-8 + +# Adding the slash user +RUN useradd -m -U -u $USER_ID slash +USER slash + +# Again, setting timezone and locale for Vivado +ENV TZ="Europe/Dublin" +ENV LC_ALL=en_US.utf-8 diff --git a/scripts/package-ami.sh b/scripts/package-ami.sh new file mode 100755 index 00000000..7ab6f1aa --- /dev/null +++ b/scripts/package-ami.sh @@ -0,0 +1,68 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euxo pipefail + +# Ensure directories created during packaging have standard permissions. +# dpkg-deb requires the control directory to be >=0755 and <=0775. +umask 0022 + +# SLASH root +cd "$(dirname "$0")/.." + +ARTIFACTS_DIR="${ARTIFACTS_DIR:-$(pwd)/ami}" +AMI_BUILD_DIR="$(pwd)/ami-build" +AVED_DIR="$(pwd)/submodules/AVED" +AMI_DIR="${AVED_DIR}/sw/AMI" +PKG_PY="${AMI_DIR}/scripts/package_data/pkg.py" +GEN_PKG_PY="${AMI_DIR}/scripts/gen_package.py" +AMI_PROGRAM_C="${AMI_DIR}/driver/ami_program.c" + +rm -rf "${AMI_BUILD_DIR}" +mkdir -p "${ARTIFACTS_DIR}" + +# Restore submodule files and clean up build directory on exit +trap 'git -C "${AVED_DIR}" checkout -- sw/AMI/scripts/package_data/pkg.py sw/AMI/scripts/gen_package.py sw/AMI/driver/ami_program.c; rm -rf "${AMI_BUILD_DIR}"' EXIT + +# Patch in Rocky Linux support (RHEL-compatible, RPM-based) +sed -i "/^DIST_ID_RHEL /a DIST_ID_ROCKY = 'rocky'" "${PKG_PY}" +sed -i "/^ DIST_ID_RHEL,$/a\\ DIST_ID_ROCKY," "${PKG_PY}" +sed -i "s/DIST_RPM = \[DIST_ID_CENTOS, DIST_ID_REDHAT, DIST_ID_REDHAT2, DIST_ID_SLES, DIST_ID_RHEL\]/DIST_RPM = [DIST_ID_CENTOS, DIST_ID_REDHAT, DIST_ID_REDHAT2, DIST_ID_SLES, DIST_ID_RHEL, DIST_ID_ROCKY]/" "${PKG_PY}" +sed -i "s/DIST_ID_CENTOS, DIST_ID_REDHAT, DIST_ID_REDHAT2, DIST_ID_RHEL\]/DIST_ID_CENTOS, DIST_ID_REDHAT, DIST_ID_REDHAT2, DIST_ID_RHEL, DIST_ID_ROCKY]/" "${GEN_PKG_PY}" + +# Extend the eventfd_signal() version gate in ami_program.c so the +# void-arg form is also picked up on RHEL 9.5+, which is when Red Hat +# backported the upstream 6.8 eventfd_signal() simplification into the +# 5.14-based kernel. +# Stopgap: revert once upstream AVED carries an equivalent fix. +sed -i 's@#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 8, 0)$@#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 8, 0) || (defined(RHEL_RELEASE_CODE) \&\& RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(9, 5))@' "${AMI_PROGRAM_C}" + +cd "${AMI_DIR}" +# --no_driver skips a pre-flight driver compilation check (build+clean) only; +# it does NOT affect which files are included in the package. +# We skip it here so the packaging can run in environments (eg. containers) +# that may not have linux-headers available to compile the driver. +python3 scripts/gen_package.py --no_driver -o "${AMI_BUILD_DIR}" + +# Copy only the package files to the artifacts directory +cp "${AMI_BUILD_DIR}"/*.rpm "${ARTIFACTS_DIR}/" 2>/dev/null || \ +cp "${AMI_BUILD_DIR}"/*.deb "${ARTIFACTS_DIR}/" 2>/dev/null || true diff --git a/scripts/package-deb.sh b/scripts/package-deb.sh new file mode 100755 index 00000000..f5089819 --- /dev/null +++ b/scripts/package-deb.sh @@ -0,0 +1,122 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euo pipefail + +NONINTERACTIVE=0 +while [[ $# -gt 0 ]]; do + case "$1" in + --noninteractive) NONINTERACTIVE=1; shift ;; + *) echo "Unknown argument: $1" >&2; exit 1 ;; + esac +done + +# SLASH root +cd "$(dirname "$0")/.." + +VERSION="$(tr -d '[:space:]' < packaging/version)" + +export ARTIFACTS_DIR="${ARTIFACTS_DIR:-"$(pwd)"/deb}" +export DPKG_ARCH="$(dpkg --print-architecture)" +export DPKG_PARSED_VERSION="$(dpkg-parsechangelog -SVersion)" + +# Warn before overwriting an existing build +if [[ -d "${ARTIFACTS_DIR}" ]] && [[ -t 0 ]] && [[ "${NONINTERACTIVE}" -eq 0 ]]; then + echo "WARNING: A previous .deb build already exists." >&2 + echo "Proceeding will remove the following directories and restart the build from scratch:" >&2 + echo " ${ARTIFACTS_DIR} (built .deb packages)" >&2 + echo " pbuild/ (CMake build tree)" >&2 + echo " debian/ (generated packaging metadata)" >&2 + echo " linker/install.prj" >&2 + echo " linker/slashkit/resources/static_shell" >&2 + echo "This includes the static shell, which can take several hours to rebuild." >&2 + read -r -p "Overwrite existing build and start from scratch? [y/N] " _answer &2; exit 1 ;; + esac +fi + +# Check build prerequisites +_prereq_ok=1 + +if ! command -v v++ > /dev/null 2>&1; then + echo "ERROR: v++ not found in PATH. Source Vitis 2025.1 before building:" >&2 + echo " source /settings64.sh" >&2 + echo "See docs/tutorials/admin/platform-setup.rst for details." >&2 + _prereq_ok=0 +fi + +if ! compgen -G 'linker/slashkit/resources/base/iprepo/smbus*/' > /dev/null 2>&1; then + echo "ERROR: SMBus IP (xilinx.com:ip:smbus:1.1) not found in linker/slashkit/resources/base/iprepo/." >&2 + echo "Download it from https://www.xilinx.com/member/v80.html and place the IP" >&2 + echo "directory into linker/slashkit/resources/base/iprepo/ before building." >&2 + echo "See docs/tutorials/admin/platform-setup.rst for details." >&2 + _prereq_ok=0 +fi + +if [[ "${_prereq_ok}" -eq 0 ]]; then + exit 1 +fi + +set -x + +# Clean build +rm -rf deb +mkdir -p deb +rm -rf pbuild +rm -rf debian + +rsync -a packaging/debian/ ./debian/ + +sed -i "1s/(UNRELEASED) UNRELEASED;/(${VERSION}) unstable;/" debian/changelog + +# Substitute the packaging version into DKMS metadata files. +sed -i "s/@VERSION@/${VERSION}/g" \ + debian/slash-dkms.dkms \ + debian/slash-dkms.install + +rsync vrt/vrtd/systemd/vrtd.service debian/vrtd.service +rsync vrt/vrtd/systemd/vrtd.socket debian/vrtd.socket +rsync vrt/vrtd/udev/99-vrtd.rules debian/vrtd.udev + +# It should be noted that while the buildinfo file and the changes file are rerouted here +# from their default location of `..`, the .dsc and .tar.xz files are rerouted by the debian/rules +# file by manual move because there apparently is no way to convince dpkg-source to write anywhere other +# than to `..`. +# +# This means that `..` has to be writable by the user building, which is inconvenient. +dpkg-buildpackage \ + --no-sign \ + --build=binary \ + --diff-ignore='.*' \ + --buildinfo-option="-u${ARTIFACTS_DIR}" \ + --buildinfo-file"=${ARTIFACTS_DIR}/slash_${DPKG_PARSED_VERSION}_${DPKG_ARCH}.buildinfo" \ + --changes-option="-u${ARTIFACTS_DIR}" \ + --changes-file="${ARTIFACTS_DIR}/slash_${DPKG_PARSED_VERSION}_${DPKG_ARCH}.changes" + +# Build AMI package into the same artifacts directory +ARTIFACTS_DIR="${ARTIFACTS_DIR}" "$(dirname "$0")/package-ami.sh" + +cd "${ARTIFACTS_DIR:-deb}" +apt-ftparchive packages . > Packages +apt-ftparchive release . > Release diff --git a/scripts/package-rpm.sh b/scripts/package-rpm.sh new file mode 100755 index 00000000..51072176 --- /dev/null +++ b/scripts/package-rpm.sh @@ -0,0 +1,111 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euo pipefail + +NONINTERACTIVE=0 +while [[ $# -gt 0 ]]; do + case "$1" in + --noninteractive) NONINTERACTIVE=1; shift ;; + *) echo "Unknown argument: $1" >&2; exit 1 ;; + esac +done + +# SLASH root +cd "$(dirname "$0")/.." + +VERSION="$(tr -d '[:space:]' < packaging/version)" +TOPDIR="$(pwd)/rpmbuild" +ARTIFACTS_DIR="${ARTIFACTS_DIR:-$(pwd)/rpm}" + +# Warn before overwriting an existing build +if [[ -d "${ARTIFACTS_DIR}" ]] && [[ -t 0 ]] && [[ "${NONINTERACTIVE}" -eq 0 ]]; then + echo "WARNING: A previous .rpm build already exists." >&2 + echo "Proceeding will remove the following directories and restart the build from scratch:" >&2 + [[ -d "${TOPDIR}" ]] && echo " ${TOPDIR} (rpmbuild tree)" >&2 + [[ -d "${ARTIFACTS_DIR}" ]] && echo " ${ARTIFACTS_DIR} (built .rpm packages)" >&2 + [[ -d pbuild ]] && echo " pbuild/ (CMake build tree)" >&2 + echo " linker/install.prj" >&2 + echo " linker/slashkit/resources/static_shell" >&2 + echo "This includes the static shell, which can take several hours to rebuild." >&2 + read -r -p "Overwrite existing build and start from scratch? [y/N] " _answer &2; exit 1 ;; + esac +fi + +# Check build prerequisites +_prereq_ok=1 + +if ! command -v v++ > /dev/null 2>&1; then + echo "ERROR: v++ not found in PATH. Source Vitis 2025.1 before building:" >&2 + echo " source /settings64.sh" >&2 + echo "See docs/tutorials/admin/platform-setup.rst for details." >&2 + _prereq_ok=0 +fi + +if ! compgen -G 'linker/slashkit/resources/base/iprepo/smbus*/' > /dev/null 2>&1; then + echo "ERROR: SMBus IP (xilinx.com:ip:smbus:1.1) not found in linker/slashkit/resources/base/iprepo/." >&2 + echo "Download it from https://www.xilinx.com/member/v80.html and place the IP" >&2 + echo "directory into linker/slashkit/resources/base/iprepo/ before building." >&2 + echo "See docs/tutorials/admin/platform-setup.rst for details." >&2 + _prereq_ok=0 +fi + +if [[ "${_prereq_ok}" -eq 0 ]]; then + exit 1 +fi + +set -x + +rm -rf "${TOPDIR}" "${ARTIFACTS_DIR}" pbuild +mkdir -p "${TOPDIR}"/{BUILD,RPMS,SOURCES,SPECS,SRPMS} +mkdir -p "${ARTIFACTS_DIR}" + +# Create source tarball (rpmbuild expects name-version/ inside) +tar czf "${TOPDIR}/SOURCES/slash-${VERSION}.tar.gz" \ + --transform="s,^\.,slash-${VERSION}," \ + --exclude='.git' \ + --exclude='rpmbuild' \ + --exclude='rpm' \ + --exclude='deb' \ + --exclude='pbuild' \ + . + +cp packaging/rpm/slash.spec "${TOPDIR}/SPECS/" + +rpmbuild \ + --define "_topdir ${TOPDIR}" \ + --define "_version ${VERSION}" \ + -bb "${TOPDIR}/SPECS/slash.spec" + +cp "${TOPDIR}"/RPMS/*/*.rpm "${ARTIFACTS_DIR}/" + +# Build AMI package into the same artifacts directory +ARTIFACTS_DIR="${ARTIFACTS_DIR}" "$(dirname "$0")/package-ami.sh" + +pushd "${ARTIFACTS_DIR}" +createrepo . +popd + +echo "RPMs available in ${ARTIFACTS_DIR}/" diff --git a/scripts/pbuild.sh b/scripts/pbuild.sh new file mode 100755 index 00000000..cadad59b --- /dev/null +++ b/scripts/pbuild.sh @@ -0,0 +1,40 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euxo pipefail + +# SLASH root +cd "$(dirname "$0")/.." + +cmake --build pbuild/smi + +if [[ -z "${SLASH_PKG_SKIP_ROOT_DESIGN_BUILD:-}" ]]; then + bash scripts/root-design-clean.sh + bash scripts/root-design-build.sh +fi + +rm -rf linker/dist linker/build linker/slashkit.egg-info +rm -rf .venv +python3 -m venv .venv +source .venv/bin/activate +pip install --upgrade pip +pip wheel --no-deps --wheel-dir ./linker/dist ./linker/ diff --git a/scripts/pconfigure.sh b/scripts/pconfigure.sh new file mode 100755 index 00000000..169787a5 --- /dev/null +++ b/scripts/pconfigure.sh @@ -0,0 +1,45 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euxo pipefail + +# SLASH root +cd "$(dirname "$0")/.." + +if [[ $# -ne 1 ]]; then + LIBDIR=lib +else + LIBDIR="$1" +fi + +COMMON_CMAKE_OPTIONS=( + "-DCMAKE_INSTALL_PREFIX=/usr" + "-DCMAKE_INSTALL_BINDIR=bin" + "-DCMAKE_INSTALL_LIBDIR=${LIBDIR}" + "-DCMAKE_INSTALL_SYSCONF=/etc" + "-DCMAKE_INSTALL_LOCALSTATEDIR=/var" + # These get stripped to separate debug symbol deb files + "-DCMAKE_BUILD_TYPE=RelWithDebInfo" +) + +cmake -B pbuild/smi -S smi -G Ninja -DSMI_INCLUDE_VRT=ON -DVRT_INCLUDE_VRTD=ON -DVRTD_INCLUDE_LIBSLASH=ON "${COMMON_CMAKE_OPTIONS[@]}" +cmake -B pbuild/cmake-tools -S cmake -G Ninja "${COMMON_CMAKE_OPTIONS[@]}" diff --git a/scripts/pinstall.sh b/scripts/pinstall.sh new file mode 100755 index 00000000..c02dcfc5 --- /dev/null +++ b/scripts/pinstall.sh @@ -0,0 +1,43 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euxo pipefail + +# SLASH root +cd "$(dirname "$0")/.." + +if [[ $# -ne 1 ]]; then + echo "Must provide one argument: DESTDIR" 1>&2 + exit 1 +fi + +# Install smi, vrt, vrtd, libvrt*, libslash +DESTDIR="$1" cmake --build pbuild/smi --target install + +# Install CMake toolchain modules (SlashTools) +DESTDIR="$1" cmake --build pbuild/cmake-tools --target install + +python3 -m pip install --no-deps --root $1 linker/dist/slashkit-*.whl +if [ -f $1/usr/local/bin/slashkit ]; then + mv $1/usr/local/bin/slashkit $1/usr/bin/ + mv $1/usr/local/lib/python3* $1/usr/lib/ +fi diff --git a/scripts/root-design-build.sh b/scripts/root-design-build.sh new file mode 100755 index 00000000..b04fc220 --- /dev/null +++ b/scripts/root-design-build.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euxo pipefail + +# SLASH root +cd "$(dirname "$0")/.." + +make -C linker/slashkit/resources/base/iprepo + +pushd linker +python3 -m slashkit install --out-dir slashkit/resources +popd diff --git a/scripts/root-design-clean.sh b/scripts/root-design-clean.sh new file mode 100755 index 00000000..530b6821 --- /dev/null +++ b/scripts/root-design-clean.sh @@ -0,0 +1,31 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euxo pipefail + +# SLASH root +cd "$(dirname "$0")/.." + +make -C linker/slashkit/resources/base/iprepo clean + +rm -rf linker/slashkit/install.prj +rm -rf linker/slashkit/resources/static_shell diff --git a/scripts/run-with-docker.sh b/scripts/run-with-docker.sh new file mode 100755 index 00000000..0b90b836 --- /dev/null +++ b/scripts/run-with-docker.sh @@ -0,0 +1,141 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -exo pipefail + +# Usage: scripts/run-with-docker.sh +# +# Builds (if necessary) and runs one of the SLASH Docker containers defined by +# scripts/Dockerfile.-. The current working +# directory and the Xilinx tools install (plus optionally a separate license +# path) are mounted into the container at the same paths they have on the +# host so that paths generated inside the container are also valid outside +# of it. +# +# Modes: +# package Run the matching distro's packaging script +# (scripts/package-deb.sh on Ubuntu, scripts/package-rpm.sh on +# Rocky) inside a clean container that only has the build +# dependencies installed. +# run Drop into an interactive bash shell inside a container that has +# the freshly built SLASH packages already installed. +# +# Required environment variables: +# SLASH_XILINX_PATH Path to the Xilinx tools install on the host +# (e.g. /opt/Xilinx). Vivado is sourced from +# $SLASH_XILINX_PATH/2025.1/Vivado/settings64.sh inside +# the container. +# +# Optional environment variables: +# SLASH_XILINX_ROOT Mount point for the Xilinx tools inside the +# container. Defaults to SLASH_XILINX_PATH so +# paths match host and container. +# SLASH_LICENSE_PATH Path to the Xilinx license file (or +# directory) on the host. When set, it is +# mounted into the container and exported as +# XILINXD_LICENSE_FILE. When unset (typical +# for installs under /opt/Xilinx or +# /tools/Xilinx where the license lives +# inside the Xilinx tree already mounted via +# SLASH_XILINX_PATH), Vivado's default +# license discovery is used. +# SLASH_PKG_SKIP_ROOT_DESIGN_BUILD If set, forwarded into the container so +# that pbuild.sh skips the (expensive) +# root-design build step. +# +# Examples: +# scripts/run-with-docker.sh package ubuntu # build .deb packages +# scripts/run-with-docker.sh package rocky # build .rpm packages +# scripts/run-with-docker.sh run ubuntu # interactive shell with +# # the .debs preinstalled + +if [ $# -ne 2 ]; then + echo "Usage: " 2>&1 + exit 1 +fi + +DOCKER_RUN_ARGS=" " +DOCKER_RUN_ARGS+="--rm " + +# Using the current working directory in the container +DOCKER_RUN_ARGS+="-v $PWD:$PWD " +DOCKER_RUN_ARGS+="-w $PWD " + +# Mounting the Xilinx toolchain in the container +if [ -z $SLASH_XILINX_PATH ]; then + echo "Please set SLASH_XILINX_PATH to the path of your Xilinx tools installation (e.g. /opt/Xilinx)" 2&1 + exit 1 +fi + +if [ -z $SLASH_XILINX_ROOT ]; then + SLASH_XILINX_ROOT=$SLASH_XILINX_PATH +fi + +DOCKER_RUN_ARGS+="-v $SLASH_XILINX_ROOT:$SLASH_XILINX_ROOT " + +# Mounting the license file for synthesis and implementation, if provided. +# When unset, the license is assumed to be reachable via SLASH_XILINX_PATH +# (already mounted above) and Vivado's default license discovery. +if [ -n "$SLASH_LICENSE_PATH" ]; then + DOCKER_RUN_ARGS+="-v $SLASH_LICENSE_PATH:$SLASH_LICENSE_PATH " + DOCKER_RUN_ARGS+="-e XILINXD_LICENSE_FILE=$SLASH_LICENSE_PATH " +fi + +# If set, add the skip-root-build flag +if [ -n $SLASH_PKG_SKIP_ROOT_DESIGN_BUILD ]; then + DOCKER_RUN_ARGS+="-e SLASH_PKG_SKIP_ROOT_DESIGN_BUILD=$SLASH_PKG_SKIP_ROOT_DESIGN_BUILD " +fi + +CONTAINER=$1 +DISTRO=$2 + +# Check the distro argument and set the relevant packaging script +if [ $DISTRO = "ubuntu" ]; then + PACKAGE_SCRIPT="./scripts/package-deb.sh" +elif [ $DISTRO = "rocky" ]; then + PACKAGE_SCRIPT="./scripts/package-rpm.sh" +else + echo "Unknown Linux distro $DISTRO" 2>&1 + exit 1 +fi + +# Build the script to run inside the container. +# This script will load Vivado, set the LD_LIBRARY_PATH for simulation, +# and then either run bash or the packaging script +# This block also cks the container argument. +DOCKER_COMMAND="source $SLASH_XILINX_PATH/2025.1/Vivado/settings64.sh " +DOCKER_COMMAND+="&& export LD_LIBRARY_PATH=\$LD_LIBRARY_PATH:$SLASH_XILINX_PATH/2025.1/Vivado/lib/lnx64.o " +if [ $CONTAINER = "package" ]; then + DOCKER_COMMAND+="&& $PACKAGE_SCRIPT " +elif [ $CONTAINER = "run" ]; then + DOCKER_COMMAND+="&& bash" + DOCKER_RUN_ARGS+="-it " +else + echo "Unknown container definition $CONTAINER" 2>&1 + exit 1 +fi + +# Build and run the container. +docker build --build-arg USER_ID=$(id -u) -t "slash-$CONTAINER-$DISTRO" -f "scripts/Dockerfile.$CONTAINER-$DISTRO" . +docker run $DOCKER_RUN_ARGS \ + "slash-$CONTAINER-$DISTRO" \ + bash -c "$DOCKER_COMMAND" diff --git a/scripts/stress-test.sh b/scripts/stress-test.sh new file mode 100755 index 00000000..a3b26cda --- /dev/null +++ b/scripts/stress-test.sh @@ -0,0 +1,342 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +REPO_ROOT="$(cd "$SCRIPT_DIR/.." && pwd)" +EXAMPLES_DIR="$REPO_ROOT/examples" + +# Examples: directory:vbin_prefix:executable +EXAMPLES=( + "00_axilite:axilite:00_axilite" + "01_aximm:aximm:01_aximm" + "02_chain:chain:02_chain" + "04_freq:freq:04_freq" +) + +NUM_EXAMPLES=${#EXAMPLES[@]} + +# Action names for reporting +ACTION_NAMES=("run_example" "reset" "program" "validate") +NUM_ACTIONS=${#ACTION_NAMES[@]} + +# Counters +declare -A ACTION_PASS +declare -A ACTION_FAIL +for name in "${ACTION_NAMES[@]}"; do + ACTION_PASS[$name]=0 + ACTION_FAIL[$name]=0 +done +ACCURACY_FAIL=0 +ITERATIONS_DONE=0 +START_TIME=$(date +%s) + +# ========================================================================= +# Usage +# ========================================================================= +usage() { + echo "Usage: $0 [--iterations N]" + echo "" + echo " Stress test a V80 board by randomly running examples, resets," + echo " programming vbins, and memory validation." + echo "" + echo " Arguments:" + echo " BDF Device BDF address (e.g. 0000:e2:00.0)" + echo " --iterations N Number of iterations (default: 100)" + echo "" + echo " Pre-built vbins and executables must exist in examples/*/build/." + exit 1 +} + +# ========================================================================= +# Summary +# ========================================================================= +print_summary() { + local end_time + end_time=$(date +%s) + local elapsed=$((end_time - START_TIME)) + + echo "" + echo "========================================================================" + echo " Stress Test Summary" + echo "========================================================================" + echo " Iterations completed: $ITERATIONS_DONE" + echo " Elapsed time: ${elapsed}s" + echo " Accuracy failures: $ACCURACY_FAIL" + echo "------------------------------------------------------------------------" + printf " %-15s %6s %6s\n" "Action" "Pass" "Fail" + echo "------------------------------------------------------------------------" + for name in "${ACTION_NAMES[@]}"; do + printf " %-15s %6d %6d\n" "$name" "${ACTION_PASS[$name]}" "${ACTION_FAIL[$name]}" + done + echo "========================================================================" +} + +# ========================================================================= +# Helpers +# ========================================================================= +timestamp() { + date "+%Y-%m-%d %H:%M:%S" +} + +log() { + echo "[$(timestamp)] $*" +} + +# Derive bdf_base from BDF by stripping the PCI function suffix (e.g. 0000:1b:00.0 -> 0000:1b:00) +bdf_to_base() { + echo "${1%.*}" +} + +check_device() { + log "v80-smi list -j" + local json + json=$(v80-smi list -j) + echo "$json" + + local bdf_base + bdf_base=$(bdf_to_base "$BDF") + + local board_status + board_status=$(echo "$json" | jq -r --arg b "$bdf_base" '.boards[] | select(.bdf_base == $b) | .status') + + if [[ -z "$board_status" ]]; then + log "ERROR: Board $bdf_base not found in v80-smi list output" + return 1 + fi + + if [[ "$board_status" != "OK" ]]; then + log "ERROR: Board $bdf_base status is '$board_status' (expected 'OK')" + return 1 + fi + + log "Board $bdf_base status: OK" +} + +random_delay() { + local delay=$((RANDOM % 11)) + if [[ $delay -gt 0 ]]; then + log "Sleeping ${delay}s..." + sleep "$delay" + fi +} + +pick_random_example() { + local idx=$((RANDOM % NUM_EXAMPLES)) + echo "${EXAMPLES[$idx]}" +} + +# ========================================================================= +# Parse arguments +# ========================================================================= +if [[ $# -lt 1 ]]; then + usage +fi + +BDF="$1" +shift + +ITERATIONS=100 +NO_RESET=0 +while [[ $# -gt 0 ]]; do + case "$1" in + --iterations) + if [[ $# -lt 2 ]]; then + echo "ERROR: --iterations requires a value" + usage + fi + ITERATIONS="$2" + shift 2 + ;; + --no-reset) + NO_RESET=1 + shift + ;; + *) + echo "ERROR: Unknown argument '$1'" + usage + ;; + esac +done + +if [[ "$NO_RESET" -eq 1 ]]; then + ACTION_NAMES=("run_example" "program" "validate") + NUM_ACTIONS=${#ACTION_NAMES[@]} +fi + +# ========================================================================= +# Pre-flight checks +# ========================================================================= +log "Starting stress test: BDF=$BDF, iterations=$ITERATIONS" +echo "" + +log "Checking device visibility..." +if ! check_device; then + echo "ERROR: Device check failed. Is the device present and vrtd running?" + exit 1 +fi +echo "" + +MISSING=0 +for entry in "${EXAMPLES[@]}"; do + IFS=':' read -r dir vbin_prefix executable <<< "$entry" + + vbin_file="$EXAMPLES_DIR/$dir/build/${vbin_prefix}_hw.vbin" + exec_file="$EXAMPLES_DIR/$dir/build/$executable" + + if [[ ! -f "$vbin_file" ]]; then + echo "ERROR: Missing vbin: $vbin_file" + MISSING=1 + fi + if [[ ! -f "$exec_file" ]]; then + echo "ERROR: Missing executable: $exec_file" + MISSING=1 + fi +done + +if [[ $MISSING -ne 0 ]]; then + echo "" + echo "Pre-built vbins and executables are required. Build them first:" + echo " ./scripts/test-examples.sh hw $BDF" + exit 1 +fi + +log "All pre-flight checks passed." +echo "" + +# ========================================================================= +# Signal handler +# ========================================================================= +trap 'log "Interrupted."; print_summary; exit 130' INT TERM + +# ========================================================================= +# Main loop +# ========================================================================= +for ((i = 1; i <= ITERATIONS; i++)); do + action_idx=$((RANDOM % NUM_ACTIONS)) + action="${ACTION_NAMES[$action_idx]}" + + echo "" + echo "========================================================================" + log "Iteration $i/$ITERATIONS — action: $action" + echo "========================================================================" + + case "$action" in + run_example) + IFS=':' read -r dir vbin_prefix executable <<< "$(pick_random_example)" + vbin_file="$EXAMPLES_DIR/$dir/build/${vbin_prefix}_hw.vbin" + exec_file="$EXAMPLES_DIR/$dir/build/$executable" + + log "Running: $exec_file $BDF $vbin_file" + rc=0 + "$exec_file" "$BDF" "$vbin_file" || rc=$? + if [[ $rc -eq 2 ]]; then + log "ACCURACY FAILURE: $action ($dir) at iteration $i (continuing)" + ACCURACY_FAIL=$((ACCURACY_FAIL + 1)) + elif [[ $rc -ne 0 ]]; then + log "FAILED: $action ($dir) at iteration $i" + ACTION_FAIL[$action]=$((ACTION_FAIL[$action] + 1)) + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ACTION_PASS[$action]=$((ACTION_PASS[$action] + 1)) + if ! check_device; then + log "FAILED: device check after $action ($dir) at iteration $i" + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ;; + + reset) + log "Running: v80-smi reset -d $BDF" + if ! v80-smi reset -d "$BDF"; then + log "FAILED: $action at iteration $i" + ACTION_FAIL[$action]=$((ACTION_FAIL[$action] + 1)) + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ACTION_PASS[$action]=$((ACTION_PASS[$action] + 1)) + if ! check_device; then + log "FAILED: device check after $action at iteration $i" + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ;; + + program) + IFS=':' read -r dir vbin_prefix executable <<< "$(pick_random_example)" + vbin_file="$EXAMPLES_DIR/$dir/build/${vbin_prefix}_hw.vbin" + + log "Running: v80-smi program -d $BDF $vbin_file" + if ! v80-smi program -d "$BDF" "$vbin_file"; then + log "FAILED: $action ($dir) at iteration $i" + ACTION_FAIL[$action]=$((ACTION_FAIL[$action] + 1)) + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ACTION_PASS[$action]=$((ACTION_PASS[$action] + 1)) + if ! check_device; then + log "FAILED: device check after $action ($dir) at iteration $i" + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + # TODO: Add "v80-smi query -d $BDF -j" here once the query bug is fixed + ;; + + validate) + threads=$((RANDOM % 64 + 1)) + NO_RESET_FLAG="" + if [[ "$NO_RESET" -eq 1 ]]; then NO_RESET_FLAG="--no-reset"; fi + log "Running: v80-smi validate -d $BDF -j $threads $NO_RESET_FLAG" + if ! v80-smi validate -d "$BDF" -j "$threads" $NO_RESET_FLAG; then + log "FAILED: $action (threads=$threads) at iteration $i" + ACTION_FAIL[$action]=$((ACTION_FAIL[$action] + 1)) + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ACTION_PASS[$action]=$((ACTION_PASS[$action] + 1)) + if ! check_device; then + log "FAILED: device check after $action (threads=$threads) at iteration $i" + ITERATIONS_DONE=$i + print_summary + exit 1 + fi + ;; + esac + + ITERATIONS_DONE=$i + random_delay +done + +# ========================================================================= +# Final summary +# ========================================================================= +log "Stress test completed successfully." +print_summary diff --git a/scripts/test-examples.sh b/scripts/test-examples.sh new file mode 100755 index 00000000..edfb2b71 --- /dev/null +++ b/scripts/test-examples.sh @@ -0,0 +1,244 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +REPO_ROOT="$(cd "$SCRIPT_DIR/.." && pwd)" +EXAMPLES_DIR="$REPO_ROOT/examples" + +SANITIZE=false + +usage() { + echo "Usage: $0 [--sanitize] [BDF]" + echo "" + echo " Build and run examples 0, 1, 2, and 4 for the specified platform." + echo "" + echo " Options:" + echo " --sanitize Build with AddressSanitizer and UBSan" + echo "" + echo " Arguments:" + echo " hw|sim|emu Target platform (hardware, simulation, or emulation)" + echo " BDF Device BDF (optional, auto-detected via v80-smi if omitted)" + echo "" + exit 1 +} + +# Parse --sanitize flag +while [[ $# -gt 0 && "$1" == --* ]]; do + case "$1" in + --sanitize) SANITIZE=true; shift ;; + *) echo "ERROR: Unknown option '$1'"; usage ;; + esac +done + +if [[ $# -lt 1 ]]; then + usage +fi + +PLATFORM="$1" + +if [[ "$PLATFORM" != "hw" && "$PLATFORM" != "sim" && "$PLATFORM" != "emu" ]]; then + echo "ERROR: Invalid platform '$PLATFORM'. Must be one of: hw, sim, emu" + usage +fi + +# Sanitizer cmake flags +CMAKE_EXTRA_ARGS=() +if [[ "$SANITIZE" == true ]]; then + echo "=== AddressSanitizer + UBSan ENABLED ===" + CMAKE_EXTRA_ARGS+=( + -DCMAKE_CXX_FLAGS="-fsanitize=address,undefined -fno-omit-frame-pointer" + -DCMAKE_C_FLAGS="-fsanitize=address,undefined -fno-omit-frame-pointer" + -DCMAKE_EXE_LINKER_FLAGS="-fsanitize=address,undefined" + -DCMAKE_SHARED_LINKER_FLAGS="-fsanitize=address,undefined" + -DENABLE_SANITIZERS=ON + ) +fi + +# Determine BDF (only required for hw) +if [[ $# -ge 2 ]]; then + BDF="$2" +else + echo "=== Auto-detecting BDF via v80-smi ===" + BDF=$(v80-smi list 2>/dev/null | grep -oP 'Board \K[0-9a-fA-F:.]+' | head -1 || true) + if [[ -z "$BDF" ]]; then + if [[ "$PLATFORM" == "hw" ]]; then + echo "ERROR: Could not auto-detect BDF. Please provide it as the second argument." + exit 1 + fi + BDF="0000:00:00.0" + echo "No device found, using default BDF: $BDF" + else + echo "Detected BDF: $BDF" + fi +fi + +# Examples to build and run: directory name, vbin prefix, executable name +EXAMPLES=( + "00_axilite:axilite:00_axilite" + "01_aximm:aximm:01_aximm" + "02_chain:chain:02_chain" + "04_freq:freq:04_freq" +) + +# ========================================================================= +# Stage 1: Configure all examples +# ========================================================================= +echo "" +echo "========================================================================" +echo " Stage 1: Configure" +echo "========================================================================" + +for entry in "${EXAMPLES[@]}"; do + IFS=':' read -r dir vbin_prefix executable <<< "$entry" + + EXAMPLE_DIR="$EXAMPLES_DIR/$dir" + BUILD_DIR="$EXAMPLE_DIR/build" + + echo "--- Configuring $dir ---" + cmake -B "$BUILD_DIR" -S "$EXAMPLE_DIR" "${CMAKE_EXTRA_ARGS[@]+"${CMAKE_EXTRA_ARGS[@]}"}" + echo "" +done + +# ========================================================================= +# Stage 2: Build HLS kernels for all examples +# ========================================================================= +echo "" +echo "========================================================================" +echo " Stage 2: Build HLS kernels" +echo "========================================================================" + +for entry in "${EXAMPLES[@]}"; do + IFS=':' read -r dir vbin_prefix executable <<< "$entry" + + BUILD_DIR="$EXAMPLES_DIR/$dir/build" + + echo "--- Building HLS kernels for $dir ---" + cmake --build "$BUILD_DIR" --target hls + echo "" +done + +# ========================================================================= +# Stage 3: Build VBIN targets for all examples +# ========================================================================= +echo "" +echo "========================================================================" +echo " Stage 3: Build VBIN targets ($PLATFORM)" +echo "========================================================================" + +for entry in "${EXAMPLES[@]}"; do + IFS=':' read -r dir vbin_prefix executable <<< "$entry" + + BUILD_DIR="$EXAMPLES_DIR/$dir/build" + VBIN_TARGET="${vbin_prefix}_${PLATFORM}" + + echo "--- Building VBIN target: $VBIN_TARGET ---" + cmake --build "$BUILD_DIR" --target "$VBIN_TARGET" + echo "" +done + +# ========================================================================= +# Stage 4: Build host applications for all examples +# ========================================================================= +echo "" +echo "========================================================================" +echo " Stage 4: Build host applications" +echo "========================================================================" + +for entry in "${EXAMPLES[@]}"; do + IFS=':' read -r dir vbin_prefix executable <<< "$entry" + + BUILD_DIR="$EXAMPLES_DIR/$dir/build" + + echo "--- Building application: $executable ---" + cmake --build "$BUILD_DIR" --target "$executable" + echo "" +done + +# ========================================================================= +# Stage 5: Run all examples +# ========================================================================= + +# ASAN runtime options +if [[ "$SANITIZE" == true ]]; then + export ASAN_OPTIONS="abort_on_error=1:detect_leaks=0" + export UBSAN_OPTIONS="print_stacktrace=1" +fi + +# For emu/sim, Vivado libraries are required at runtime +if [[ "$PLATFORM" == "emu" || "$PLATFORM" == "sim" ]]; then + if [[ -z "${XILINX_VIVADO:-}" ]]; then + echo "ERROR: XILINX_VIVADO is not set." + echo "Please source the settings64.sh (or settings64.csh) file from your Vivado installation directory." + exit 1 + fi + export LD_LIBRARY_PATH="${XILINX_VIVADO}/lib/lnx64.o${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH}" +fi + +echo "" +echo "========================================================================" +echo " Stage 5: Run examples ($PLATFORM, BDF: $BDF)" +echo "========================================================================" + +PASS_COUNT=0 +FAIL_COUNT=0 +SKIP_COUNT=0 +RESULTS=() + +for entry in "${EXAMPLES[@]}"; do + IFS=':' read -r dir vbin_prefix executable <<< "$entry" + + BUILD_DIR="$EXAMPLES_DIR/$dir/build" + VBIN_TARGET="${vbin_prefix}_${PLATFORM}" + VBIN_FILE="$BUILD_DIR/${VBIN_TARGET}.vbin" + + echo "--- Running: $executable $BDF $VBIN_FILE ---" + if "$BUILD_DIR/$executable" "$BDF" "$VBIN_FILE"; then + echo "PASS: $dir" + RESULTS+=("$dir: PASSED") + PASS_COUNT=$((PASS_COUNT + 1)) + else + echo "FAIL: $dir (exit code: $?)" + RESULTS+=("$dir: FAILED") + FAIL_COUNT=$((FAIL_COUNT + 1)) + fi + echo "" +done + +# ========================================================================= +# Summary +# ========================================================================= +echo "" +echo "========================================================================" +echo " Summary | Platform: $PLATFORM | BDF: $BDF" +echo "========================================================================" +for result in "${RESULTS[@]}"; do + echo " $result" +done +echo "------------------------------------------------------------------------" +echo " Passed: $PASS_COUNT | Failed: $FAIL_COUNT | Skipped: $SKIP_COUNT" +echo "========================================================================" + +if [[ $FAIL_COUNT -gt 0 ]]; then + exit 1 +fi diff --git a/scripts/test-fresh-install.sh b/scripts/test-fresh-install.sh new file mode 100755 index 00000000..247d6b2b --- /dev/null +++ b/scripts/test-fresh-install.sh @@ -0,0 +1,289 @@ +#!/bin/bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set -euo pipefail + +CLEAN_ONLY=false + +usage() { + echo "Usage: $0 [--clean]" + echo "" + echo " --clean Remove installed SLASH packages only (skip install and verification)" + exit 1 +} + +# Parse long options +while [[ $# -gt 0 && "$1" == --* ]]; do + case "$1" in + --clean) + CLEAN_ONLY=true + shift + ;; + *) + echo "ERROR: Unknown option '$1'" + usage + ;; + esac +done + +if [[ $# -gt 0 ]]; then + echo "ERROR: Unexpected argument '$1'" + usage +fi + +# SLASH root +cd "$(dirname "$0")/.." + +# ========================================================================= +# Detect package manager from /etc/os-release +# ========================================================================= + +if [[ ! -f /etc/os-release ]]; then + echo "ERROR: /etc/os-release not found. Cannot detect distribution." + exit 1 +fi + +source /etc/os-release + +case "${ID_LIKE:-$ID}" in + *debian*|*ubuntu*) + PKG_TYPE="deb" + ;; + *rhel*|*fedora*|*centos*|*suse*) + PKG_TYPE="rpm" + ;; + *) + # Fallback: check ID directly + case "${ID}" in + debian|ubuntu|linuxmint|pop) + PKG_TYPE="deb" + ;; + rhel|fedora|centos|rocky|alma|ol|sles|opensuse*) + PKG_TYPE="rpm" + ;; + *) + echo "ERROR: Unsupported distribution: ${ID} (ID_LIKE=${ID_LIKE:-unset})" + exit 1 + ;; + esac + ;; +esac + +echo "Detected package type: ${PKG_TYPE} (distro: ${PRETTY_NAME})" + +# ========================================================================= +# Package lists +# ========================================================================= + +DEB_PACKAGES=( + slash + slash-dev + slash-sim-emu + slash-sim-emu-dev + slash-dkms + libslash + libslash-dev + vrtd + libvrtd + libvrtd-dev + libvrt + libvrt-dev + v80-smi + slashkit + ami +) + +RPM_PACKAGES=( + slash + slash-devel + slash-sim-emu + slash-sim-emu-devel + slash-dkms + libslash + libslash-devel + vrtd + libvrtd + libvrtd-devel + libvrt + libvrt-devel + v80-smi + slashkit + ami +) + +# ========================================================================= +# DEB workflow +# ========================================================================= + +if [[ "${PKG_TYPE}" == "deb" ]]; then + echo "" + echo "========================================================================" + echo " Stage 1: Purge existing SLASH packages (DEB)" + echo "========================================================================" + + INSTALLED=() + for pkg in "${DEB_PACKAGES[@]}"; do + if dpkg -l "${pkg}" 2>/dev/null | grep -q '^ii'; then + INSTALLED+=("${pkg}") + fi + done + + if [[ ${#INSTALLED[@]} -gt 0 ]]; then + echo "Purging: ${INSTALLED[*]}" + apt-get purge -y "${INSTALLED[@]}" + apt-get autoremove --purge -y + else + echo "No SLASH packages currently installed." + fi + + if [[ "${CLEAN_ONLY}" == "true" ]]; then + echo "" + echo "========================================================================" + echo " --clean enabled: stopping after Stage 1 purge" + echo "========================================================================" + exit 0 + fi + + ARTIFACTS_DIR="${ARTIFACTS_DIR:-$(pwd)/deb}" + + if [[ ! -d "${ARTIFACTS_DIR}" ]]; then + echo "ERROR: DEB artifacts directory not found: ${ARTIFACTS_DIR}" + echo " Run scripts/package-deb.sh first." + exit 1 + fi + + echo "" + echo "========================================================================" + echo " Stage 2: Install SLASH packages from ${ARTIFACTS_DIR}" + echo "========================================================================" + + apt-get install -y "${ARTIFACTS_DIR}"/*.deb + +# ========================================================================= +# RPM workflow +# ========================================================================= + +elif [[ "${PKG_TYPE}" == "rpm" ]]; then + echo "" + echo "========================================================================" + echo " Stage 1: Remove existing SLASH packages (RPM)" + echo "========================================================================" + + INSTALLED=() + for pkg in "${RPM_PACKAGES[@]}"; do + if rpm -q "${pkg}" &>/dev/null; then + INSTALLED+=("${pkg}") + fi + done + + if [[ ${#INSTALLED[@]} -gt 0 ]]; then + echo "Removing: ${INSTALLED[*]}" + dnf remove -y "${INSTALLED[@]}" + else + echo "No SLASH packages currently installed." + fi + + if [[ "${CLEAN_ONLY}" == "true" ]]; then + echo "" + echo "========================================================================" + echo " --clean enabled: stopping after Stage 1 removal" + echo "========================================================================" + exit 0 + fi + + ARTIFACTS_DIR="${ARTIFACTS_DIR:-$(pwd)/rpm}" + + if [[ ! -d "${ARTIFACTS_DIR}" ]]; then + echo "ERROR: RPM artifacts directory not found: ${ARTIFACTS_DIR}" + echo " Run scripts/package-rpm.sh first." + exit 1 + fi + + echo "" + echo "========================================================================" + echo " Stage 2: Install SLASH packages from ${ARTIFACTS_DIR}" + echo "========================================================================" + + # Exclude source, debuginfo, and debugsource RPMs + mapfile -t RPMS < <(find "${ARTIFACTS_DIR}" -maxdepth 1 -name '*.rpm' \ + ! -name '*.src.rpm' ! -name '*-debuginfo-*' ! -name '*-debugsource-*') + dnf install -y "${RPMS[@]}" +fi + +# ========================================================================= +# Verify +# ========================================================================= + +echo "" +echo "========================================================================" +echo " Stage 3: Verify installation" +echo "========================================================================" + +PASS_COUNT=0 +FAIL_COUNT=0 +RESULTS=() + +if [[ "${PKG_TYPE}" == "deb" ]]; then + PACKAGES=("${DEB_PACKAGES[@]}") +else + PACKAGES=("${RPM_PACKAGES[@]}") +fi + +for pkg in "${PACKAGES[@]}"; do + if [[ "${PKG_TYPE}" == "deb" ]]; then + if dpkg -l "${pkg}" 2>/dev/null | grep -q '^ii'; then + RESULTS+=("${pkg}: INSTALLED") + PASS_COUNT=$((PASS_COUNT + 1)) + else + RESULTS+=("${pkg}: MISSING") + FAIL_COUNT=$((FAIL_COUNT + 1)) + fi + else + if rpm -q "${pkg}" &>/dev/null; then + RESULTS+=("${pkg}: INSTALLED") + PASS_COUNT=$((PASS_COUNT + 1)) + else + RESULTS+=("${pkg}: MISSING") + FAIL_COUNT=$((FAIL_COUNT + 1)) + fi + fi +done + +echo "" +echo "========================================================================" +echo " Summary | Type: ${PKG_TYPE} | Distro: ${PRETTY_NAME}" +echo "========================================================================" +for result in "${RESULTS[@]}"; do + echo " ${result}" +done +echo "------------------------------------------------------------------------" +echo " Installed: ${PASS_COUNT} | Missing: ${FAIL_COUNT}" +echo "========================================================================" + +if [[ ${FAIL_COUNT} -gt 0 ]]; then + echo "" + echo "WARNING: ${FAIL_COUNT} package(s) failed to install." + exit 1 +fi + +echo "" +echo "All SLASH packages installed successfully." diff --git a/scripts/vrtd-debug.sh b/scripts/vrtd-debug.sh new file mode 100755 index 00000000..cfde5174 --- /dev/null +++ b/scripts/vrtd-debug.sh @@ -0,0 +1,38 @@ +#!/usr/bin/env bash + +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + + +set -euo pipefail + +OVERRIDE_DIR="/etc/systemd/system/vrtd.service.d" + +mkdir -p "$OVERRIDE_DIR" +cat > "$OVERRIDE_DIR/debug.conf" <<'EOF' +[Service] +LogLevelMax=debug +EOF + +systemctl daemon-reload +systemctl restart vrtd +systemctl enable --now vrtd + +echo "vrtd debug logging enabled. View with: journalctl -u vrtd -f" diff --git a/smi/CMakeLists.txt b/smi/CMakeLists.txt index 5e880ec2..58cf9771 100644 --- a/smi/CMakeLists.txt +++ b/smi/CMakeLists.txt @@ -1,6 +1,6 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -20,21 +20,52 @@ cmake_minimum_required(VERSION 3.10) -project(v80-smi) +# Read version from packaging/version +file(READ "${CMAKE_CURRENT_SOURCE_DIR}/../packaging/version" SMI_VERSION) +string(STRIP "${SMI_VERSION}" SMI_VERSION) -set(CMAKE_CXX_STANDARD 20) -set(CMAKE_CXX_STANDARD_REQUIRED True) +# Parse into components +string(REPLACE "." ";" VERSION_LIST "${SMI_VERSION}") +list(GET VERSION_LIST 0 SMI_VERSION_MAJOR) +list(GET VERSION_LIST 1 SMI_VERSION_MINOR) +list(GET VERSION_LIST 2 SMI_VERSION_PATCH) -include_directories(include /usr/include/ami/ /usr/include/libxml2 /usr/include/jsoncpp) +message(STATUS "SMI version: ${SMI_VERSION} (${SMI_VERSION_MAJOR}.${SMI_VERSION_MINOR}.${SMI_VERSION_PATCH})") -file(GLOB APP_SOURCES v80-smi.cpp src/*.cpp src/commands/*.cpp src/utils/*.cpp) - -set(SOURCES - ${APP_SOURCES} +project( + v80-smi + + VERSION ${SMI_VERSION} + LANGUAGES C CXX ) -add_executable(v80-smi ${SOURCES}) +option(SMI_INCLUDE_VRT "Include vrtd as subdirectory instead of building from system" OFF) + +include(GNUInstallDirs) + +if (SMI_INCLUDE_VRT) + add_subdirectory(../vrt vrt) +else() + find_package(vrt REQUIRED CONFIG) +endif() + +if(NOT TARGET vrt::vrt) + message(FATAL_ERROR + "vrt package is missing target vrt::vrt. " + "Build and install vrt first (cmake --install), then configure smi again.") +endif() -target_link_libraries(v80-smi ami jsoncpp xml2) +find_package(CLI11 CONFIG REQUIRED) -install(TARGETS v80-smi DESTINATION /usr/local/bin) \ No newline at end of file +configure_file( + "${CMAKE_CURRENT_SOURCE_DIR}/cmake/version.hpp.in" + "${CMAKE_CURRENT_BINARY_DIR}/generated/version.hpp" + @ONLY +) + +add_subdirectory(src) + +install( + TARGETS v80-smi + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" +) diff --git a/smi/README.md b/smi/README.md new file mode 100644 index 00000000..d528ed92 --- /dev/null +++ b/smi/README.md @@ -0,0 +1,388 @@ +# v80-smi + +Command-line tool for managing AMD Alveo V80 devices. v80-smi can +enumerate boards, inspect vrtbin metadata, program devices, reset +hardware, and validate memory integrity and bandwidth. + +| Command | Purpose | +|------------|---------------------------------------------------| +| `version` | Print build version | +| `list` | Enumerate V80 boards and check readiness | +| `inspect` | Display metadata from a vbin file on disk | +| `query` | Display metadata of the vbin loaded on a device | +| `program` | Load a vbin file onto a V80 device | +| `reset` | Hardware-reset a V80 board | +| `validate` | Reset board and test memory integrity + bandwidth | +| `debug` | Low-level BAR, memory, and clock debug utilities | + +## Building + +```sh +cmake -B build -S . -G Ninja +cmake --build build +``` + +CMake options: + +| Option | Default | Description | +|-------------------|---------|----------------------------------------------| +| `SMI_INCLUDE_VRT` | `OFF` | Build the bundled VRT library instead of using the system package | + +Requires a C++20 compiler. + +## Installing + +```sh +sudo cmake --install build --prefix /usr/local +``` + +This installs the `v80-smi` binary to `/bin/`. + +## Commands + +### version + +Print build version and exit. + +``` +v80-smi version [-p] +``` + +| Flag | Description | +|----------------|----------------------------------------------------------| +| `-p,--plain` | Print only the version number (useful in scripts) | + +```console +$ v80-smi version +SMI v1.2.3 + +$ v80-smi version --plain +1.2.3 +``` + +### list + +Enumerate V80 boards by scanning sysfs for matching PCI vendor/device +IDs. Each board's readiness is checked across all three PCI functions +and the VRTD daemon. + +``` +v80-smi list [-l] [-s] [-j | -J] +``` + +| Flag | Description | +|--------------------|---------------------------------------------------------| +| `-l,--long` | Print detailed per-PF info (vendor/device ID, driver, NUMA node, IRQ) | +| `-s,--sensors` | Include sensor readings from VRTD (temperature, current, voltage, power) | +| `-j,--json` | Compact JSON output | +| `-J,--pretty-json` | Indented JSON output | + +Readiness checks per board: + +- **PF0** (device 0x50B4) — expected driver: `ami` +- **PF1** (device 0x50B5) — expected driver: `slash_qdma` +- **PF2** (device 0x50B6) — expected driver: `slash_ctl` +- **VRTD** — daemon reachable and device registered + +```console +$ v80-smi list +Board 0000:03:00 OK (PF0: OK) (PF1: OK) (PF2: OK) (VRTD: OK) +Board 0000:83:00 NOT READY (PF0: OK) (PF1: NOT READY: wrong driver) (PF2: OK) (VRTD: NOT READY) +``` + +### inspect + +Display metadata from a vbin file without hardware. Shows the target +platform, clock frequency, resource utilization, and kernel argument +maps. + +``` +v80-smi inspect [-j | -J] +``` + +| Flag | Description | +|--------------------|-------------------------------| +| `-j,--json` | Compact JSON output | +| `-J,--pretty-json` | Indented JSON output | + +```console +$ v80-smi inspect design.vbin +Vbin design.vbin: + Platform: HARDWARE + Clock frequency: 300000000 + Utilization: + Slash: LUTs: 45032 (5.2%), FFs: 62001 (3.6%), LUTRAM: 3200 (0.7%), SRL: 1100 (0.3%), RAMB36: 48, RAMB18: 12, URAM: 0, DSP: 12 + Kernel: + Name: increment_0 + Physical address: 0x20100000000 + Argument: + Index: 0 + Name: size + Type: int + Offset: 0x10 + Range: 0x20 + Direction: Read +``` + +No hardware or VRTD required. + +### query + +Same output as `inspect`, but reads metadata from the vbin last +programmed by the user on a device. + +``` +v80-smi query -d [-j | -J] +``` + +| Flag | Description | +|--------------------|-----------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | +| `-j,--json` | Compact JSON output | +| `-J,--pretty-json` | Indented JSON output | + +Requires the device to have been programmed at least once. + +### program + +Load a vbin file onto a V80 device. + +``` +v80-smi program -d +``` + +| Flag | Description | +|-------------------|------------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | + +```console +$ v80-smi program design.vbin -d 03:00 +``` + +### reset + +Hardware-reset a V80 board. Performs the full hotplug sequence +(remove → SBR → settle → rescan → hotplug) via the +VRTD daemon. + +``` +v80-smi reset -d +``` + +| Flag | Description | +|-------------------|------------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | + +Requires root access and a running VRTD daemon. The device must be +programmed with the static SLASH design. + +### validate + +Reset a board, then test HBM and DDR memory for data integrity and +bandwidth. + +``` +v80-smi validate -d [-j ] +``` + +| Flag | Description | +|-------------------|------------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | +| `-j,--threads` | Parallel buffers/threads, 1-64 (default 8) | + +Each buffer is 64 MB. The integrity test writes a pattern, syncs to +device, clears host memory, syncs back, and verifies. The bandwidth +test runs parallel H2C writes and C2H reads. + +```console +$ v80-smi validate -d 03:00 +Resetting device 0000:03:00... +Testing HBM data integrity (8 regions)... + HBM0: OK + HBM1: OK + ... +Testing HBM bandwidth (8 threads)... + Write: 9832.10 MB/s + Read: 9547.22 MB/s +Testing DDR data integrity (8 buffers)... + DDR0: OK + DDR1: OK + ... +Testing DDR bandwidth (8 threads)... + Write: 5120.45 MB/s + Read: 4980.33 MB/s +``` + +Requires root access and a running VRTD daemon. + +### debug bar-poke + +Perform low-level BAR reads or writes for troubleshooting. + +``` +v80-smi debug bar-poke -d -b (-r | -w) [-x] [-W ] [-c ]
[value] +``` + +| Flag | Description | +|-------------------|------------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | +| `-b,--bar` | BAR number (required), range `0-5` | +| `-r,--read` | Read operation (required unless `--write`) | +| `-w,--write` | Write operation (required unless `--read`) | +| `-x,--hex` | Print read output in hex | +| `-W,--word-size` | Word size in bytes: `1`, `2`, `4`, or `8` (default `4`) | +| `-c,--count` | Number of words to read (default `1`; must be `1` for write) | + +Rules: + +- Exactly one of `--read` or `--write` must be provided. +- `
` is a BAR-relative byte offset. +- `` is required for `--write` and forbidden for `--read`. +- Input numbers are auto-detected: `0x...` is parsed as hex; otherwise values are parsed as base-10. +- `--hex` affects output formatting only. + +Examples: + +```console +$ v80-smi debug bar-poke -d 03:00 -b 4 --read 65536 +0 + +$ v80-smi debug bar-poke -d 03:00 -b 4 --read --hex -W 4 -c 4 0x10000 +0x0 +0x1 +0x2 +0x3 + +$ v80-smi debug bar-poke -d 03:00 -b 4 --write --hex -W 4 0x10000 0x1 +``` + +### debug mem-poke + +Perform low-level raw memory reads or writes at device physical addresses. +This bypasses the allocator and requires raw-mem-access permission in vrtd. + +``` +v80-smi debug mem-poke -d (-r | -w) [-x] [-W ] [-c ]
[value] [-f ] +``` + +| Flag | Description | +|-------------------|------------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | +| `-r,--read` | Read operation (required unless `--write`) | +| `-w,--write` | Write operation (required unless `--read`) | +| `-x,--hex` | Hex output in read mode; hex text/hexdump file mode with `-f` | +| `-W,--word-size` | Word size in bytes: `1`, `2`, `4`, or `8` (default `4`) | +| `-c,--count` | Number of words (default `1`) | +| `-f,--file` | File path for file-mode read/write | + +Rules: + +- Exactly one of `--read` or `--write` must be provided. +- `
` is a device physical address. +- In scalar mode (no `--file`): + - `--write` requires `` and `--count` must be `1`. + - `--read` forbids ``. + - Address must be aligned to word size. +- In file mode (`--file`): + - `` is forbidden. + - Byte count is exactly `word-size * count`. + - With `--hex`: file is parsed/emitted as hex text (hexdump-compatible). + - Without `--hex`: file is raw binary. + +Examples: + +```console +$ v80-smi debug mem-poke -d 03:00 --read --hex -W 4 -c 4 0x40000000 +0x3f800000 +0x40000000 +0x40400000 +0x40800000 + +$ v80-smi debug mem-poke -d 03:00 --write --hex -W 4 0x40000000 0x3f800000 + +$ v80-smi debug mem-poke -d 03:00 --write -W 4 -c 256 -f input.bin 0x40000000 +``` + +### debug clockwiz + +Read or set clock rates through the vrtd clock-op API. + +``` +v80-smi debug clockwiz -d (--get | --set ) [--region ] [-x] +``` + +| Flag | Description | +|-------------------|------------------------------------------------------| +| `-d,--device` | Board address (required), e.g. `03:00` or `0000:03:00` | +| `--get` | Read current clock rate for selected region | +| `--set` | Set requested clock rate in Hz for selected region | +| `--region` | Clock region: `user` or `service` (default `user`) | +| `-x,--hex` | Print `--get` output in hex | + +Rules: + +- Exactly one of `--get` or `--set` must be provided. +- `--set` value is in Hz and must be greater than zero. +- `--hex` is valid only with `--get`. +- `--set` prints both requested and achieved frequencies. + +Examples: + +```console +$ v80-smi debug clockwiz -d 03:00 --get +300000000 + +$ v80-smi debug clockwiz -d 03:00 --get --region service --hex +0x11e1a300 + +$ v80-smi debug clockwiz -d 03:00 --set 300000000 --region user +requested_hz=300000000 +achieved_hz=300000000 +``` + +Requires a running VRTD daemon and clock permission in the user's role. + +## Device addressing + +All commands that accept a `-d,--device` option support four BDF +(Bus:Device.Function) formats: + +| Format | Example | Notes | +|-----------------|-----------------|-----------------------------| +| `DDDD:BB:DD` | `0000:03:00` | Board-level, no function | +| `BB:DD` | `03:00` | Short form | +| `DDDD:BB:DD.F` | `0000:03:00.0` | Full with PCI function (not recommended) | +| `BB:DD.F` | `03:00.0` | Domain defaults to `0000` (not recommended) | + +All forms are normalised to board-level `DDDD:BB:DD`. If a PCI +function digit is supplied it is accepted but ignored with a warning, +since v80-smi always operates at board granularity. + +## Dependencies + +| Dependency | Purpose | +|------------|--------------------------------------------------| +| libvrt | VRT runtime library (device, kernel, vrtbin APIs) | +| vrtd | Runtime daemon (sensors, reset, validate, query) | + +## Project layout + +``` +smi/ + src/ + smi.cpp Entry point and subcommand dispatch + list.cpp/hpp Board enumeration via sysfs + inspect.cpp/hpp Vbin metadata inspection and device query + program.cpp/hpp Device programming + reset.cpp/hpp Hardware reset via VRTD + validate.cpp/hpp Memory integrity and bandwidth testing + debug/bar_poke.cpp/hpp BAR read/write debug command + debug/mem_poke.cpp/hpp Raw device memory read/write command + debug/clockwiz.cpp/hpp Clock read/set debug command + bdf.hpp BDF address parser + utils.hpp Formatting and output utilities +``` + +## License + +MIT — see [LICENSE](../LICENSE). diff --git a/smi/cmake/version.hpp.in b/smi/cmake/version.hpp.in new file mode 100644 index 00000000..aefe7092 --- /dev/null +++ b/smi/cmake/version.hpp.in @@ -0,0 +1,43 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file version.hpp.in +/// @brief Compile-time version constants for the smi CLI tool. +/// +/// This is a CMake configure_file() template. At build time, the +/// @-delimited placeholders are replaced with values from the CMake +/// project definition to produce version.hpp. + +#ifndef SMI_VERSION_HPP +#define SMI_VERSION_HPP + +/// Full semantic-version string (e.g., "1.2.3"). +constexpr char VERSION[] = "@SMI_VERSION@"; + +/// Major version component. +constexpr unsigned int VERSION_MAJOR = @SMI_VERSION_MAJOR@; + +/// Minor version component. +constexpr unsigned int VERSION_MINOR = @SMI_VERSION_MINOR@; + +/// Patch version component. +constexpr unsigned int VERSION_PATCH = @SMI_VERSION_PATCH@; + +#endif // SMI_VERSION_HPP diff --git a/smi/include/arg_parser.hpp b/smi/include/arg_parser.hpp deleted file mode 100644 index acd0397e..00000000 --- a/smi/include/arg_parser.hpp +++ /dev/null @@ -1,129 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef ARG_PARSER_HPP -#define ARG_PARSER_HPP - -#include -#include -#include -#include - -/** - * @brief Class for parsing command-line arguments. - * - * The ArgParser class handles the parsing of command-line arguments for the application. - */ -class ArgParser { - public: - /** - * @brief Constructor for ArgParser. - * - * Initializes the ArgParser and registers the available commands. - */ - ArgParser(); - - /** - * @brief Parses the command-line arguments. - * - * @param argc The number of arguments. - * @param argv The array of argument strings. - */ - void parse(int argc, char* argv[]); - - /** - * @brief Gets the device BDF (Bus:Device.Function) identifier. - * - * @return The device BDF as a string. - */ - std::string getDevice() const; - - /** - * @brief Gets the path to the image file. - * - * @return The image file path as a string. - */ - std::string getImagePath() const; - - /** - * @brief Gets the partition number. - * - * @return The partition number. - */ - uint8_t getPartition() const; - - /** - * @brief Checks if a specific command was specified. - * - * @param command The command to check for. - * @return True if the specified command was given, false otherwise. - */ - bool isCommand(const std::string& command) const; - - /** - * @brief Prints the help message. - * - * Displays usage information, available commands, and options. - */ - void printHelp() const; - - /** - * @brief Checks if a string ends with a specific suffix. - * - * @param str The string to check. - * @param suffix The suffix to look for. - * @return True if the string ends with the suffix, false otherwise. - */ - static bool endsWith(const std::string& str, const std::string& suffix); - - private: - std::unordered_map> - commands; ///< Map of command names to handler functions. - std::string device; ///< The device BDF identifier. - std::string image; ///< The path to the image file. - uint8_t partition = -1; ///< The partition number. - std::string currentCommand; ///< The currently active command. - - /** - * @brief Registers a command with its handler function. - * - * @param command The command name. - * @param handler The function to execute when the command is invoked. - */ - void addCommand(const std::string& command, const std::function& handler); - - /** - * @brief Converts a BDF string to a standardized format. - * - * @param bdf The BDF string to convert. - * @return The standardized BDF string. - */ - std::string convertBdf(const std::string& bdf) const; - - /** - * @brief Strips whitespace from a string. - * - * @param bdf The string to strip. - * @return The stripped string. - */ - std::string strip(const std::string& bdf) const; -}; - -#endif // ARG_PARSER_HPP \ No newline at end of file diff --git a/smi/include/commands/inspect_command.hpp b/smi/include/commands/inspect_command.hpp deleted file mode 100644 index 1dd329fa..00000000 --- a/smi/include/commands/inspect_command.hpp +++ /dev/null @@ -1,67 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef INSPECT_COMMAND_HPP -#define INSPECT_COMMAND_HPP - -#include -#include - -#include - -#include "utils/vrtbin.hpp" - -#define INSPECT_SYSTEM_MAP_PATH ((FilesystemCache::getCachePath() / "system_map.xml").c_str()) ///< Path to the system map XML file -#define INSPECT_VERSION_PATH ((FilesystemCache::getCachePath() / "version.json").c_str()) ///< Path to the version JSON file - -/** - * @brief Class for inspecting VRTBIN files. - * - * The InspectCommand class provides functionality to inspect and analyze VRTBIN - * files, extracting metadata. - */ -class InspectCommand { - public: - /** - * @brief Constructor for InspectCommand. - * - * @param image_path Path to the VRTBIN file to inspect. - */ - InspectCommand(const std::string &image_path); - - /** - * @brief Executes the inspection command. - * - * This method processes the VRTBIN file and displays relevant information. - */ - void execute(); - - private: - std::string imagePath; ///< Path to the VRTBIN file being inspected. - - /** - * @brief Queries metadata from the VRTBIN file. - * - * Extracts and processes metadata information from the VRTBIN file. - */ - void queryMetadata(); -}; - -#endif // INSPECT_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/partial_program_command.hpp b/smi/include/commands/partial_program_command.hpp deleted file mode 100644 index e6350436..00000000 --- a/smi/include/commands/partial_program_command.hpp +++ /dev/null @@ -1,78 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef PARTIAL_PROGRAM_COMMAND_HPP -#define PARTIAL_PROGRAM_COMMAND_HPP - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "arg_parser.hpp" -#include "pcie_hotplug.hpp" -#include "utils/vrtbin.hpp" - -/** - * @brief Delay in microseconds for partial boot process. - * - * This constant defines the delay time in microseconds that the system - * will wait during the partial boot process. - */ -#define DELAY_PARTIAL_BOOT (4 * 1000 * 1000) - -/** - * @brief Class for handling partial program commands. - * - * The PartialProgramCommand class provides functionality to program a device - * with a segmented PDI image file. - */ -class PartialProgramCommand { - public: - /** - * @brief Constructor for PartialProgramCommand. - * - * @param device The BDF of the device to program. - * @param image_path Path to the segmented PDI image file. - */ - PartialProgramCommand(const std::string& device, const std::string& image_path); - - /** - * @brief Executes the partial program command. - * - * This method programs the specified device with the segmented PDI image. - */ - void execute(); - - private: - std::string device; ///< The BDF of the device to program. - std::string imagePath; ///< Path to the segmented PDI image file. - ami_device* dev; ///< Pointer to the AMI device object. -}; - -#endif // PARTIAL_PROGRAM_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/program_command.hpp b/smi/include/commands/program_command.hpp deleted file mode 100644 index 84d3d809..00000000 --- a/smi/include/commands/program_command.hpp +++ /dev/null @@ -1,89 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef PROGRAM_COMMAND_HPP -#define PROGRAM_COMMAND_HPP - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "arg_parser.hpp" -#include "pcie_hotplug.hpp" -#include "utils/vrtbin.hpp" - -/** - * @brief Enumeration for image types. - * - * This enum represents the different types of images that can be programmed. - */ -enum class ImageType { - PDI, ///< PDI (Platform Device Image) type - VRTBIN, ///< VRTBIN (VRT Binary) type -}; - -/** - * @brief Class for handling program commands. - * - * The ProgramCommand class provides functionality to program a device - * with a specified image file. - */ -class ProgramCommand { - public: - /** - * @brief Constructor for ProgramCommand. - * - * @param device The BDF of the device to program. - * @param image_path Path to the image file. - * @param partition The partition number to program. - */ - ProgramCommand(const std::string& device, const std::string& image_path, uint8_t partition); - - /** - * @brief Executes the program command. - * - * This method programs the specified device with the image file. - */ - void execute(); - - /** - * @brief Boots the device. - * - * This method initiates the boot process for the device after programming. - */ - void bootDevice(); - - private: - std::string device; ///< The BDF of the device to program. - std::string imagePath; ///< Path to the image file. - uint8_t partition; ///< The partition number to program. - ami_device* dev; ///< Pointer to the AMI device object. -}; - -#endif // PROGRAM_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/query_command.hpp b/smi/include/commands/query_command.hpp deleted file mode 100644 index ef1a79f3..00000000 --- a/smi/include/commands/query_command.hpp +++ /dev/null @@ -1,168 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef QUERY_COMMAND_HPP -#define QUERY_COMMAND_HPP - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "utils/vrtbin.hpp" - -/** - * @brief Path format for system map XML file. - * - * This macro defines the format string for the path to the system map XML file. - */ -#define SYSTEM_MAP_PATH "%s/%s:00.0/system_map.xml" - -/** - * @brief Path format for version JSON file. - * - * This macro defines the format string for the path to the version JSON file. - */ -#define VERSION_PATH "%s/%s:00.0/version.json" - -/** - * @brief Path format for QDMA queue device file. - * - * This macro defines the format string for the path to the QDMA queue device file. - */ -#define QDMA_QUEUE_PATH "/dev/qdma%s001-MM-0" // /dev/qdma-MM- - -/** - * @brief Path format for QDMA queue maximum value file. - * - * This macro defines the format string for the path to the QDMA queue maximum value file. - */ -#define QDMA_QMAX_PATH "/sys/bus/pci/devices/0000:%s:00.1/qdma/qmax" - -/** - * @brief Buffer size for reading files. - * - * This macro defines the size of the buffer used for reading files. - */ -#define BUFFER_SIZE 1024 - -/** - * @brief Maximum length for metadata strings. - * - * This macro defines the maximum length for metadata strings. - */ -#define META_MAX_STR_LEN 256 - -/** - * @brief Base for manufacturing timestamp conversion. - * - * This macro defines the base value for converting manufacturing timestamps. - */ -#define MFG_TIMESTAMP_BASE 16 - -/** - * @brief Base year offset for manufacturing date. - * - * This macro defines the base year offset (1970) for manufacturing date calculations. - */ -#define MFG_DATE_TM_YEAR 70 - -/** - * @brief Class for querying device information. - * - * The QueryCommand class provides functionality to query and display - * information about a specified device, including its hardware details, - * kernels, and QDMA queues. - */ -class QueryCommand { - public: - /** - * @brief Constructor for QueryCommand. - * - * @param device The BDF of the device to query. - */ - QueryCommand(const std::string& device); - - /** - * @brief Executes the query command. - * - * This method queries the specified device and displays its information. - */ - void execute(); - - private: - std::string device; ///< The BDF of the device to query. - - /** - * @brief Queries basic device information. - * - * This method retrieves and displays basic information about the device. - */ - void queryDevice(); - - /** - * @brief Queries kernel information. - * - * @param bdf The BDF of the device to query. - * - * This method retrieves and displays information about the kernels on the device. - */ - void queryKernels(const std::string& bdf); - - /** - * @brief Queries QDMA queue information. - * - * @param bdf The BDF of the device to query. - * - * This method retrieves and displays information about the QDMA queues on the device. - */ - void queryQueues(const std::string& bdf); - - /** - * @brief Prints AMI-specific device details. - * - * This method retrieves and displays AMI-specific information about the device. - */ - void printAmiDetails(); - - /** - * @brief Formats the manufacturing date. - * - * @param timestamp The manufacturing timestamp to format. - * - * This method formats and displays the manufacturing date based on the provided timestamp. - */ - void formatManufacturingDate(long timestamp); -}; - -#endif // QUERY_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/reload_command.hpp b/smi/include/commands/reload_command.hpp deleted file mode 100644 index d32ee44d..00000000 --- a/smi/include/commands/reload_command.hpp +++ /dev/null @@ -1,59 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef RELOAD_COMMAND_HPP -#define RELOAD_COMMAND_HPP - -#include -#include - -#include "pcie_hotplug.hpp" - -/** - * @brief Class for handling device reload commands. - * - * The ReloadCommand class provides functionality to reload a specified FPGA device - * by managing the PCIe connection through a hot-plug cycle without performing a complete - * hardware reset. This is useful for refreshing the device state or recovering from - * certain error conditions. - */ -class ReloadCommand { - public: - /** - * @brief Constructor for ReloadCommand. - * - * @param device The BDF (Bus:Device.Function) identifier of the device to reload. - */ - ReloadCommand(const std::string& device); - - /** - * @brief Executes the reload command. - * - * This method performs the device reload sequence, which typically involves - * removing the device from the PCIe bus and then rescanning to rediscover it, - * effectively reestablishing the connection without a full hardware reset. - */ - void execute(); - - private: - std::string device; ///< The BDF identifier of the device to reload. -}; - -#endif // RELOAD_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/reset_command.hpp b/smi/include/commands/reset_command.hpp deleted file mode 100644 index cb4a09e7..00000000 --- a/smi/include/commands/reset_command.hpp +++ /dev/null @@ -1,63 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef RESET_COMMAND_HPP -#define RESET_COMMAND_HPP - -#include -#include -#include - -#include -#include -#include - -#include "pcie_hotplug.hpp" - -/** - * @brief Class for handling device reset commands. - * - * The ResetCommand class provides functionality to reset a specified FPGA device - * by managing the device's PCIe connection and hardware reset sequence. - */ -class ResetCommand { - public: - /** - * @brief Constructor for ResetCommand. - * - * @param device The BDF (Bus:Device.Function) identifier of the device to reset. - */ - ResetCommand(const std::string& device); - - /** - * @brief Executes the reset command. - * - * This method performs the device reset sequence, which includes - * properly shutting down the PCIe connection, performing the hardware - * reset, and re-establishing the connection if necessary. - */ - void execute(); - - private: - std::string device; ///< The BDF identifier of the device to reset. - ami_device* dev; ///< Pointer to the AMI device object. -}; - -#endif // RESET_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/resource_command.hpp b/smi/include/commands/resource_command.hpp deleted file mode 100644 index 64cb075a..00000000 --- a/smi/include/commands/resource_command.hpp +++ /dev/null @@ -1,155 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef RESOURCE_COMMAND_HPP -#define RESOURCE_COMMAND_HPP - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/** - * @brief Format string for resource utilization file path. - * - * This macro defines the format string for the path to the resource utilization XML file. - */ -#define RESOURCE_UTILIZATION_FILE "%s/%s:00.0/report_utilization.xml" - -/** - * @brief Structure representing an instance in the resource hierarchy. - * - * This structure holds resource utilization data for a specific instance, including - * its name, module type, resource counts, and child instances. - */ -struct Instance { - std::string name; ///< Name of the instance. - std::string module; ///< Module type of the instance. - std::pair totalLUTs; ///< Total number of LUTs used and percentage of total. - std::pair logicLUTs; ///< Number of logic LUTs used and percentage of total. - std::pair lutRAMs; ///< Number of LUT RAMs used and percentage of total. - std::pair srls; ///< Number of SRLs used and percentage of total. - std::pair ffs; ///< Number of flip-flops used and percentage of total. - std::pair ramb36; ///< Number of RAMB36 blocks used and percentage of total. - std::pair ramb18; ///< Number of RAMB18 blocks used and percentage of total. - std::pair uram; ///< Number of URAMs used and percentage of total. - std::pair dspBlocks; ///< Number of DSP blocks used and percentage of total. - std::vector children; ///< Child instances. -}; - -/** - * @brief Class for displaying resource utilization information. - * - * The ResourceCommand class provides functionality to display resource utilization - * information for a specified device, showing detailed breakdowns of hardware resources - * used by different components. - */ -class ResourceCommand { - public: - /** - * @brief Constructor for ResourceCommand. - * - * @param device The BDF of the device to query for resource utilization. - */ - ResourceCommand(const std::string& device); - - /** - * @brief Executes the resource command. - * - * This method retrieves and displays resource utilization information for the specified device. - */ - void execute() const; - - private: - std::string device; ///< The BDF of the device to query. - Instance rootInstance; ///< Root instance of the resource hierarchy. - - /** - * @brief Parses the resource utilization XML file. - * - * @param filename Path to the XML file containing resource utilization data. - * - * This method parses the XML file and builds the resource hierarchy. - */ - void parseXML(const std::string& filename); - - /** - * @brief Parses a single instance node from the XML. - * - * @param a_node The XML node to parse. - * @param instance The Instance structure to populate. - * - * This method parses a single XML node representing an instance and populates - * the corresponding Instance structure. - */ - void parseInstance(xmlNode* a_node, Instance& instance); - - /** - * @brief Prints resource utilization information. - * - * This method displays formatted resource utilization information. - */ - void printResources(); - - /** - * @brief Prints detailed information for a specific instance. - * - * @param instance The instance to print information for. - * @param level The hierarchical level of the instance. - * @param headerPrinted Reference to a flag indicating if the header has been printed. - * - * This method prints detailed resource utilization information for a specific instance. - */ - void printInstance(const Instance& instance, int level, bool& headerPrinted) const; - - /** - * @brief Prints information for an instance with a specific name. - * - * @param instance The root instance to search in. - * @param targetName The name of the instance to print information for. - * @param headerPrinted Flag indicating if the header has been printed. - * - * This method searches for and prints information for an instance with a specific name. - */ - void printSpecificInstance(const Instance& instance, const std::string& targetName, - bool headerPrinted) const; - - /** - * @brief Prints information for children of the base logic instance. - * - * @param instance The root instance to search in. - * @param excludeList List of instance names to exclude from the output. - * @param headerPrinted Reference to a flag indicating if the header has been printed. - * - * This method prints resource utilization information for children of the base logic - * instance, excluding instances in the provided exclude list. - */ - void printChildrenOfBaseLogic(const Instance& instance, - const std::vector& excludeList, - bool& headerPrinted) const; -}; - -#endif // RESOURCE_COMMAND_HPP \ No newline at end of file diff --git a/smi/include/commands/validate_command.hpp b/smi/include/commands/validate_command.hpp deleted file mode 100644 index a502e67b..00000000 --- a/smi/include/commands/validate_command.hpp +++ /dev/null @@ -1,376 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef VALIDATE_CMD_HPP -#define VALIDATE_CMD_HPP - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/** - * @brief Starting address for DDR memory. - * - * This macro defines the starting address for DDR memory testing. - */ -#define ADDR_START_DDR 0x50080000000 - -/** - * @brief Starting address for DIMM DDR memory. - * - * This macro defines the starting address for DIMM DDR memory testing. - */ -#define ADDR_START_DIMM_DDR 0x60000000000 - -/** - * @brief Starting address for HBM memory. - * - * This macro defines the starting address for HBM memory testing. - */ -#define ADDR_START_HBM 0x4000000000 - -/** - * @brief Size per HBM channel. - * - * This macro defines the size of each HBM channel. - */ -#define SIZE_PER_HBM_CHANNEL 0x40000000 - -/** - * @brief Default test size in bytes. - * - * This macro defines the default size used for memory tests. - */ -#define DEFAULT_TEST_SIZE 255000000 - -/** - * @brief Default number of test iterations. - * - * This macro defines the default number of times each test is run. - */ -#define DEFAULT_COUNT_TIMES 50 - -/** - * @brief Maximum size for read/write operations. - * - * This macro defines the maximum allowed size for a single read/write operation. - */ -#define RW_MAX_SIZE 0x7ffff000 - -/** - * @brief Divisor for gigabyte conversion. - * - * This macro defines the divisor used to convert bytes to gigabytes. - */ -#define GB_DIV 1000000000 - -/** - * @brief Divisor for megabyte conversion. - * - * This macro defines the divisor used to convert bytes to megabytes. - */ -#define MB_DIV 1000000 - -/** - * @brief Divisor for kilobyte conversion. - * - * This macro defines the divisor used to convert bytes to kilobytes. - */ -#define KB_DIV 1000 - -/** - * @brief Divisor for nanosecond conversion. - * - * This macro defines the divisor used to convert nanoseconds to seconds. - */ -#define NSEC_DIV 1000000000 - -/** - * @brief Enumeration for test types. - */ -typedef enum { - TEST_TYPE_READ = 0, /**< Read test type. */ - TEST_TYPE_WRITE /**< Write test type. */ -} test_type; - -/** - * @brief Structure to hold thread data. - */ -typedef struct { - std::string devname; /**< Device name. */ - uint64_t addr; /**< Address to test. */ - uint64_t size; /**< Size of the memory region. */ - uint64_t offset; /**< Offset within the memory region. */ - uint64_t count; /**< Number of iterations. */ - int verbose; /**< Verbose flag. */ -} thread_data_t; - -/** - * @brief Class for validating device memory and bandwidth. - * - * The ValidateCommand class provides functionality to validate the memory and - * bandwidth of a device by running various DMA read and write tests. - */ -class ValidateCommand { - public: - /** - * @brief Constructor for ValidateCommand. - * - * @param device The BDF of the device to validate. - */ - ValidateCommand(const std::string& device); - - /** - * @brief Executes the validate command. - * - * This method runs a series of memory and bandwidth tests on the specified device. - */ - void execute(); - - private: - std::string device; ///< The BDF of the device to validate. - - /** - * @brief Performs a DMA test. - * - * @param devname The device name. - * @param addr The memory address to test. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * - * This method performs a DMA test with the specified parameters. - */ - void test_dma(const std::string& devname, uint64_t addr, uint64_t size, uint64_t offset, - uint64_t count, int verbose); - - /** - * @brief Writes data from a buffer to a device. - * - * @param fname The device file name. - * @param fd The file descriptor. - * @param buffer The buffer containing data to write. - * @param size The size of data to write. - * @param base The base address to write to. - * @return The number of bytes written. - * - * This method writes data from a buffer to a device at the specified address. - */ - std::size_t write_from_buffer(const std::string& fname, int fd, char* buffer, uint64_t size, - uint64_t base); - - /** - * @brief Reads data from a device to a buffer. - * - * @param fname The device file name. - * @param fd The file descriptor. - * @param buffer The buffer to read data into. - * @param size The size of data to read. - * @param base The base address to read from. - * @return The number of bytes read. - * - * This method reads data from a device at the specified address into a buffer. - */ - std::size_t read_to_buffer(const std::string& fname, int fd, char* buffer, uint64_t size, - uint64_t base); - - /** - * @brief Tests DMA write operations. - * - * @param devname The device name. - * @param addr The memory address to test. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * @return The number of bytes written. - * - * This method tests DMA write operations with the specified parameters. - */ - std::size_t test_dma_write(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose); - - /** - * @brief Tests DMA read operations. - * - * @param devname The device name. - * @param addr The memory address to test. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * @return The number of bytes read. - * - * This method tests DMA read operations with the specified parameters. - */ - std::size_t test_dma_read(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose); - - /** - * @brief Prints test results. - * - * @param devname The device name. - * @param addr The memory address tested. - * @param total_time The total time taken for the test. - * @param avg_time The average time per iteration. - * @param size The size of the memory region tested. - * @param result The test result. - * @param type The type of test (read or write). - * @param verbose Flag for verbose output. - * - * This method prints the results of a DMA test. - */ - void print_results(const std::string& devname, uint64_t addr, double total_time, - double avg_time, double size, double result, test_type type, int verbose); - - /** - * @brief Prints PCIe bandwidth results. - * - * @param pci_bw_result The PCIe bandwidth measurement result. - * - * This method prints the results of a PCIe bandwidth test. - */ - void print_pci_bandwidth(double pci_bw_result); - - /** - * @brief Thread function for DMA read tests. - * - * @param data Pointer to thread data structure. - * - * This method is executed in a thread to perform DMA read tests. - */ - void dma_read_thread(thread_data_t* data); - - /** - * @brief Thread function for DMA write tests. - * - * @param data Pointer to thread data structure. - * - * This method is executed in a thread to perform DMA write tests. - */ - void dma_write_thread(thread_data_t* data); - - /** - * @brief Runs sequential read/write tests in threads. - * - * @param devname The device name. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * @return The result code. - * - * This method runs sequential read/write tests in separate threads. - */ - int run_sim_seq_rw_threads(const std::string& devname, uint64_t size, uint64_t offset, - uint64_t count, int verbose); - - /** - * @brief Runs read/write tests for a specific memory type. - * - * @param devname The device name. - * @param addr The memory address to test. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * @param mem_type The type of memory being tested. - * @return The result code. - * - * This method runs read/write tests for a specific memory type. - */ - int run_sim_rw_per_memory(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose, - const std::string& mem_type); - - /** - * @brief Runs PCIe bandwidth tests. - * - * @param devname The device name. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * @return The result code. - * - * This method runs PCIe bandwidth tests. - */ - int run_pcie_bw_test(const std::string& devname, uint64_t size, uint64_t offset, uint64_t count, - int verbose); - - /** - * @brief Tests DMA write operations for PCIe bandwidth measurement. - * - * @param devname The device name. - * @param addr The memory address to test. - * @param size The size of the memory region to test. - * @param offset The offset within the memory region. - * @param count The number of test iterations. - * @param verbose Flag for verbose output. - * @return The bandwidth measurement result. - * - * This method tests DMA write operations for PCIe bandwidth measurement. - */ - double test_dma_write_pcie(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose); - - /** - * @brief Thread function for PCIe DMA write tests. - * - * @param data Pointer to thread data structure. - * - * This method is executed in a thread to perform PCIe DMA write tests. - */ - void dma_write_thread_pcie(thread_data_t* data); - - /** - * @brief Subtracts one timespec structure from another. - * - * @param t1 Pointer to the first timespec structure. - * @param t2 Pointer to the second timespec structure. - * - * This method subtracts t2 from t1, storing the result in t1. - */ - void timespec_sub(struct timespec* t1, struct timespec* t2); - - /** - * @brief Checks if a timespec structure is valid. - * - * @param t Pointer to the timespec structure to check. - * @return 1 if valid, 0 otherwise. - * - * This method checks if a timespec structure is valid. - */ - int timespec_check(struct timespec* t); -}; - -#endif // VALIDATE_CMD_HPP \ No newline at end of file diff --git a/smi/include/pcie_hotplug.hpp b/smi/include/pcie_hotplug.hpp deleted file mode 100644 index 208c9d48..00000000 --- a/smi/include/pcie_hotplug.hpp +++ /dev/null @@ -1,73 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef PCIE_HOTPLUG_HPP -#define PCIE_HOTPLUG_HPP - -#include -#include - -#include -#include -#include - -class PcieDriverHandler { - public: - /** - * @brief Enum for PCIe driver commands. - */ - enum class Command { - REMOVE, ///< Remove command - TOGGLE_SBR, ///< Toggle Secondary Bus Reset command - RESCAN, ///< Rescan command - HOTPLUG ///< Hotplug command - }; - - /** - * @brief Constructor for PcieDriverHandler. - * @param bdf The BDF of the PCIe device. - */ - PcieDriverHandler(const std::string& bdf); - - /** - * @brief Sends a command to the PCIe driver. - * @param cmd The command to send. - */ - void sendCommand(Command cmd); - - /** - * @brief Executes a PCIe driver command. - * @param cmd The command to execute. - */ - void execute(Command cmd); - - private: - /** - * @brief Helper method to convert enum to string. - * @param cmd The command to convert. - * @return The string representation of the command. - */ - std::string commandToString(Command cmd); - std::string bdf; ///< The BDF of the PCIe device. - std::string driverPath; ///< The path to the PCIe driver. - std::string pcieHotplugRootPath = "/dev/pcie_hotplug"; ///< The root path for PCIe hotplug. -}; - -#endif // PCIE_HOTPLUG_HPP \ No newline at end of file diff --git a/smi/include/utils/filesystem_cache.hpp b/smi/include/utils/filesystem_cache.hpp deleted file mode 100644 index 372de0fb..00000000 --- a/smi/include/utils/filesystem_cache.hpp +++ /dev/null @@ -1,77 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef FILESYSTEM_CACHE_HPP -#define FILESYSTEM_CACHE_HPP - -#include - -/** - * @brief Static class for managing the filesystem cache - i.e. where trivial temporary files can be stored. - * - * There are two directories with different pourposes: - * 1. Runtime directory, generally stored as tmpfs on Linux (in RAM). Locks or really small files go here. - * 2. Cache directory, generally stored on disk. - * - * For more information see: https://specifications.freedesktop.org/basedir-spec/0.8/ - * - * SLASH uses subdirectories within each of the main directories, and smi uses a subdirectory within the SLASH - * directory. - * - * See each function for a description of paths used and what enviornment variables to set to override these choices. - * However, the default behaviour (where the user sets nothing extra) should be reasonable for most Linux installations. - */ -class FilesystemCache { - static void ensureDirExists(const std::filesystem::path& path); - public: - /** - * @brief Disable construction of static class. - */ - FilesystemCache() = delete; - - /** - * @brief Get path to the cache directory. - * - * This function creates the cache directory if it does not exist. - * - * The following paths are used: - * - * 1. $SLASH_CACHE_PATH/smi, if $SLASH_CACHE_PATH is set in the environment. - * 2. $XDG_CACHE_HOME/SLASH/smi, if $XDG_CACHE_HOME is set. - * 3. $HOME/.cache/SLASH/smi, if $HOME is set. - * 4. /tmp/SLASH-cache-/smi, as a final fallback. - */ - static std::filesystem::path getCachePath(); - - /** - * @brief Get path to the runtime directory. - * - * This function creates the runtime directory if it does not exist. - * - * The following paths are used: - * - * 1. $SLASH_RUNTIME_PATH/smi, if $SLASH_RUNTIME_PATH is set in the environment. - * 2. $XDG_RUNTIME_DIR/SLASH/smi, if $XDG_RUNTIME_DIR is set. - * 3. /tmp/SLASH-run-/smi, as a final fallback. - */ - static std::filesystem::path getRuntimePath(); -}; - -#endif // FILESYSTEM_CACHE_HPP diff --git a/smi/include/utils/vrtbin.hpp b/smi/include/utils/vrtbin.hpp deleted file mode 100644 index 9f79f80d..00000000 --- a/smi/include/utils/vrtbin.hpp +++ /dev/null @@ -1,101 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef VRTBIN_HPP -#define VRTBIN_HPP - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/** - * @brief Class for managing VRTBIN files. - * - * The Vrtbin class provides utilities for handling VRTBIN files, including - * extraction, copying, and information retrieval. - */ -class Vrtbin { - public: - /** - * @brief Extracts the contents of a VRTBIN file. - * - * @param source Path to the source VRTBIN file. - * @param destination Path where the contents will be extracted. - */ - static void extract(std::string source, std::string destination); - - /** - * @brief Copies a VRTBIN file. - * - * @param source Path to the source VRTBIN file. - * @param destination Path where the file will be copied. - */ - static void copy(const std::string& source, const std::string& destination); - - /** - * @brief Handler for progress events during VRTBIN operations. - * - * @param status The current status of the operation. - * @param ctr Counter value indicating progress. - * @param data Additional data for the handler. - */ - static void progressHandler(enum ami_event_status status, uint64_t ctr, void* data); - - /** - * @brief Generates a progress bar string. - * - * @param cur Current progress value. - * @param max Maximum progress value. - * @param width Width of the progress bar in characters. - * @param left Character for the left end of the progress bar. - * @param right Character for the right end of the progress bar. - * @param fill Character for filled portions of the progress bar. - * @param empty Character for empty portions of the progress bar. - * @param state Character indicating the current state. - * @return A character representing the current state of the progress bar. - */ - static char print_progress_bar(uint32_t cur, uint32_t max, uint32_t width, char left, - char right, char fill, char empty, char state); - - /** - * @brief Extracts the UUID from a VRTBIN file. - * - * @return The UUID as a string. - */ - static std::string extractUUID(); - - /** - * @brief Extracts and prints information about a VRTBIN file. - * - * @param path Path to the VRTBIN file. - */ - static void extractAndPrintInfo(const std::string& path); -}; - -#endif // VRTBIN_HPP \ No newline at end of file diff --git a/smi/src/CMakeLists.txt b/smi/src/CMakeLists.txt new file mode 100644 index 00000000..30e509aa --- /dev/null +++ b/smi/src/CMakeLists.txt @@ -0,0 +1,53 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_executable( + v80-smi + + debug/bar_poke.cpp + debug/clockwiz.cpp + debug/mem_poke.cpp + inspect.cpp + list.cpp + program.cpp + reset.cpp + validate.cpp + smi.cpp +) + +target_compile_features(v80-smi PRIVATE cxx_std_20) + +target_include_directories( + v80-smi + + PRIVATE + + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_BINARY_DIR}/../generated # For version.hpp +) + +target_link_libraries( + v80-smi + + PRIVATE + + vrt::vrt + CLI11::CLI11 +) diff --git a/smi/src/arg_parser.cpp b/smi/src/arg_parser.cpp deleted file mode 100644 index 4b74b644..00000000 --- a/smi/src/arg_parser.cpp +++ /dev/null @@ -1,219 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "arg_parser.hpp" - -#include - -#include -#include - -ArgParser::ArgParser() { - addCommand("query", [this]() { currentCommand = "query"; }); - addCommand("validate", [this]() { currentCommand = "validate"; }); - addCommand("report_utilization", [this]() { currentCommand = "report_utilization"; }); - addCommand("list", [this]() { currentCommand = "list"; }); - addCommand("program", [this]() { currentCommand = "program"; }); - addCommand("partial_program", [this]() { currentCommand = "partial_program"; }); - addCommand("inspect", [this]() { currentCommand = "inspect"; }); - addCommand("reload", [this]() { currentCommand = "reload"; }); - addCommand("reset", [this]() { currentCommand = "reset"; }); -} - -void ArgParser::parse(int argc, char* argv[]) { - static struct option long_options[] = {{"device", required_argument, 0, 'd'}, - {"image", required_argument, 0, 'i'}, - {"partition", required_argument, 0, 'p'}, - {"help", no_argument, 0, 'h'}, - {0, 0, 0, 0}}; - - int opt; - int option_index = 0; - bool isProgram = false; - bool isPartialProgram = false; - bool isInspect = false; - for (int i = 1; i < argc; i++) { - if (std::string(argv[i]) == "program") { - isProgram = true; - break; - } - } - for (int i = 1; i < argc; i++) { - if (std::string(argv[i]) == "partial_program") { - isPartialProgram = true; - break; - } - } - - for (int i = 1; i < argc; i++) { - if (std::string(argv[i]) == "inspect") { - isInspect = true; - break; - } - } - while ((opt = getopt_long(argc, argv, "d:i:p:h", long_options, &option_index)) != -1) { - switch (opt) { - case 'd': - device = convertBdf(optarg); - break; - case 'i': - image = optarg; - break; - case 'p': - partition = std::stoi(optarg); - break; - case 'h': - printHelp(); - exit(EXIT_SUCCESS); - case '?': - printHelp(); - exit(EXIT_FAILURE); - default: - break; - } - } - - if (optind < argc) { - std::string command = argv[optind]; - auto it = commands.find(command); - if (it != commands.end()) { - it->second(); - } else { - std::cerr << "Error: Unknown command " << command << std::endl; - printHelp(); - exit(EXIT_FAILURE); - } - } else { - std::cerr << "Error: No command specified" << std::endl; - printHelp(); - exit(EXIT_FAILURE); - } - if (isProgram) { - if (device.empty() || image.empty() || partition == -1) { - std::cerr << "Error: Missing required options for 'program' command." << std::endl; - printHelp(); - exit(EXIT_FAILURE); - } - if (partition > 1) { - std::cerr << "Partition must be 0 or 1" << std::endl; - exit(EXIT_FAILURE); - } - if (!(endsWith(image, ".vrtbin"))) { - std::cerr << "Image must be a .vrtbin file" << std::endl; - exit(EXIT_FAILURE); - } - if (!std::filesystem::exists(image)) { - std::cerr << "Image file does not exist" << std::endl; - exit(EXIT_FAILURE); - } - } - if (isPartialProgram) { - if (device.empty() || image.empty() || partition == -1) { - std::cerr << "Error: Missing required options for 'partial_program' command." - << std::endl; - printHelp(); - exit(EXIT_FAILURE); - } - - if (!((endsWith(image, ".vrtbin")) || (endsWith(image, ".pdi")))) { - std::cerr << "Image must be a .vrtbin or pdi file" << std::endl; - exit(EXIT_FAILURE); - } - - if (!std::filesystem::exists(image)) { - std::cerr << "Image file does not exist" << std::endl; - exit(EXIT_FAILURE); - } - } - - if (isInspect) { - if (image.empty()) { - std::cerr << "Error: Missing required options for 'inspect' command." << std::endl; - printHelp(); - exit(EXIT_FAILURE); - } - - if (!(endsWith(image, ".vrtbin"))) { - std::cerr << "Image must be a .vrtbin file" << std::endl; - exit(EXIT_FAILURE); - } - - if (!std::filesystem::exists(image)) { - std::cerr << "Image file does not exist" << std::endl; - exit(EXIT_FAILURE); - } - } -} - -std::string ArgParser::getDevice() const { return device; } - -bool ArgParser::isCommand(const std::string& command) const { return currentCommand == command; } - -void ArgParser::printHelp() const { - std::cout - << "Usage: v80-smi [options]\n" - << "Commands:\n" - << " query Query the device\n" - << " validate Validate the device\n" - << " report_utilization Report device utilization for the current programmed shell\n" - << " list List V80s installed\n" - << " program Program the device's flash memory\n" - << " partial_program Program the device with a segmented PDI image\n" - << " inspect Inspect a vrtbin before programming\n" - << " reload Reloads the PCIe handler for device\n" - << " reset Resets the device to a clean state\n" - << "Options:\n" - << " -d, --device Specify the device (e.g., 21:00.0)\n" - << " -i, --image Specify the image file to program. Only relevant for " - "program/partial_program commands\n" - << " -p, --partition Specify the partition to program. Only relevant for program " - "command\n" - << " -h, --help Show this help message\n"; -} - -void ArgParser::addCommand(const std::string& command, const std::function& handler) { - commands[command] = handler; -} - -std::string ArgParser::convertBdf(const std::string& bdf) const { - std::regex pattern("^0000:(.*)"); - std::smatch match; - if (std::regex_match(bdf, match, pattern)) { - return match[1].str(); - } - return strip(bdf); -} - -std::string ArgParser::strip(const std::string& bdf) const { - size_t colonPos = bdf.find(':'); - if (colonPos != std::string::npos) { - return bdf.substr(0, colonPos); - } - return bdf; -} - -std::string ArgParser::getImagePath() const { return image; } - -uint8_t ArgParser::getPartition() const { return partition; } - -bool ArgParser::endsWith(const std::string& str, const std::string& suffix) { - return str.size() >= suffix.size() && - str.compare(str.size() - suffix.size(), suffix.size(), suffix) == 0; -} diff --git a/smi/src/bdf.hpp b/smi/src/bdf.hpp new file mode 100644 index 00000000..34f23a9f --- /dev/null +++ b/smi/src/bdf.hpp @@ -0,0 +1,106 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file bdf.hpp +/// @brief BDF (Bus:Device.Function) parsing and normalization for SMI user input. +/// +/// Accepts four formats: DDDD:BB:DD.F, BB:DD.F, DDDD:BB:DD, BB:DD. +/// Normalizes to board-level DDDD:BB:DD for internal use. If a function +/// digit is supplied, prints a warning and strips it. + +#ifndef SMI_BDF_HPP +#define SMI_BDF_HPP + +#include +#include +#include +#include +#include + +/// Result of parsing a BDF string from user input. +struct ParsedBdf { + std::string domain; ///< 4-hex-digit domain, e.g. "0000". + std::string bus; ///< 2-hex-digit bus, e.g. "03". + std::string device; ///< 2-hex-digit device/slot, e.g. "00". + std::optional function; ///< Function digit 0-7, or nullopt. + + /// Returns the board-level base: "DDDD:BB:DD" (no function). + std::string base() const { + return domain + ":" + bus + ":" + device; + } +}; + +/// Parse a user-supplied BDF string. +/// +/// Accepts: "DDDD:BB:DD.F", "BB:DD.F", "DDDD:BB:DD", "BB:DD". +/// Prepends domain "0000" if not present. +/// +/// @param input Raw BDF string from user. +/// @return ParsedBdf on success. +/// @throws std::invalid_argument if the format is unrecognized. +inline ParsedBdf parseBdf(const std::string& input) { + static const std::regex bdfRegex( + R"(^(?:([0-9a-fA-F]{4}):)?([0-9a-fA-F]{2}):([0-9a-fA-F]{2})(?:\.([0-7]))?$)" + ); + + std::smatch match; + if (!std::regex_match(input, match, bdfRegex)) { + throw std::invalid_argument( + "Invalid BDF format: '" + input + "'. " + "Expected DDDD:BB:DD, BB:DD, DDDD:BB:DD.F, or BB:DD.F " + "(e.g. 0000:03:00 or 03:00)"); + } + + ParsedBdf result; + result.domain = match[1].matched ? match[1].str() : "0000"; + result.bus = match[2].str(); + result.device = match[3].str(); + if (match[4].matched) { + result.function = static_cast(match[4].str()[0] - '0'); + } + + return result; +} + +/// Resolve a user-supplied BDF to a board-level "DDDD:BB:DD" string. +/// +/// If a function digit (.F) is present, a warning is printed to stderr +/// and the function is stripped. The result is always "DDDD:BB:DD". +/// +/// @param input Raw BDF string from user. +/// @param cmdName Command name for the warning message (e.g. "reset"). +/// @return Board-level BDF in "DDDD:BB:DD" format. +/// @throws std::invalid_argument if the BDF format is invalid. +inline std::string resolveBoardBdf(const std::string& input, + const std::string& cmdName) { + auto parsed = parseBdf(input); + + if (parsed.function.has_value()) { + std::cerr << "Warning: " << cmdName + << " operates on a board, not a specific PF. " + << "Ignoring function ." << *parsed.function + << " from '" << input << "'; using board address " + << parsed.base() << std::endl; + } + + return parsed.base(); +} + +#endif // SMI_BDF_HPP diff --git a/smi/src/commands/inspect_command.cpp b/smi/src/commands/inspect_command.cpp deleted file mode 100644 index 242e4094..00000000 --- a/smi/src/commands/inspect_command.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/inspect_command.hpp" -#include "utils/filesystem_cache.hpp" - -InspectCommand::InspectCommand(const std::string& image_path) : imagePath(image_path) {} - -void InspectCommand::execute() { - Vrtbin::extract(this->imagePath, FilesystemCache::getCachePath()); - queryMetadata(); -} - -void InspectCommand::queryMetadata() { - xmlDocPtr document = xmlReadFile(INSPECT_SYSTEM_MAP_PATH, NULL, 0); - if (document == NULL) { - std::cerr << "Error: could not read system map file" << std::endl; - return; - } - xmlNode* rootNode = xmlDocGetRootElement(document); - if (rootNode == NULL) { - std::cerr << "Error: could not get root element" << std::endl; - return; - } - - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "VRTBIN Information\n"; - std::cout << "--------------------------------------------------------------------\n"; - std::string platform, type, clockFrequency; - - for (xmlNode* kernelNode = rootNode->children; kernelNode; kernelNode = kernelNode->next) { - if (kernelNode->type == XML_ELEMENT_NODE && - xmlStrcmp(kernelNode->name, BAD_CAST "Platform") == 0) { - platform = (const char*)xmlNodeGetContent(kernelNode); - std::cout << "Platform | " << platform << "\n"; - } else if (kernelNode->type == XML_ELEMENT_NODE && - xmlStrcmp(kernelNode->name, BAD_CAST "Type") == 0) { - type = (const char*)xmlNodeGetContent(kernelNode); - std::cout << "Type | " << type << "\n"; - } else if (kernelNode->type == XML_ELEMENT_NODE && - xmlStrcmp(kernelNode->name, BAD_CAST "ClockFrequency") == 0) { - clockFrequency = (const char*)xmlNodeGetContent(kernelNode); - std::cout << "Max clock Frequency | " << clockFrequency << " Hz\n"; - } - } - std::cout << "\n"; - Vrtbin::extractAndPrintInfo(INSPECT_VERSION_PATH); - - for (xmlNode* kernelNode = rootNode->children; kernelNode; kernelNode = kernelNode->next) { - if (kernelNode->type == XML_ELEMENT_NODE && - xmlStrcmp(kernelNode->name, BAD_CAST "Kernel") == 0) { - std::string name, baseAddr, range; - for (xmlNode* childNode = kernelNode->children; childNode; - childNode = childNode->next) { - if (childNode->type == XML_ELEMENT_NODE) { - if (xmlStrcmp(childNode->name, BAD_CAST "Name") == 0) { - name = (char*)xmlNodeGetContent(childNode); - } else if (xmlStrcmp(childNode->name, BAD_CAST "BaseAddress") == 0) { - baseAddr = (char*)xmlNodeGetContent(childNode); - } else if (xmlStrcmp(childNode->name, BAD_CAST "Range") == 0) { - range = (char*)xmlNodeGetContent(childNode); - } - } - } - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Kernel Information\n"; - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Kernel Name | " << name << "\n"; - std::cout << "Base Address | " << baseAddr << "\n"; - std::cout << "Range | " << range << "\n\n"; - } - } -} diff --git a/smi/src/commands/list_command.cpp b/smi/src/commands/list_command.cpp deleted file mode 100644 index 520da277..00000000 --- a/smi/src/commands/list_command.cpp +++ /dev/null @@ -1,60 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/list_command.hpp" - -#include -#include -#include -#include - -ListCommand::ListCommand(uint16_t vendorId, uint16_t deviceId) - : vendorId(vendorId), deviceId(deviceId) {} - -void ListCommand::execute() const { listDevices(); } - -void ListCommand::listDevices() const { - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Listing V80 devices " - << "\n"; - std::cout << "--------------------------------------------------------------------\n"; - - for (const auto& entry : std::filesystem::directory_iterator("/sys/bus/pci/devices")) { - std::string path = entry.path(); - std::ifstream vendorFile(path + "/vendor"); - std::ifstream deviceFile(path + "/device"); - - if (vendorFile.is_open() && deviceFile.is_open()) { - std::string vendorIdStr, deviceIdStr; - std::getline(vendorFile, vendorIdStr); - std::getline(deviceFile, deviceIdStr); - - uint16_t vendorId = std::stoi(vendorIdStr, nullptr, 16); - uint16_t deviceId = std::stoi(deviceIdStr, nullptr, 16); - - if (vendorId == this->vendorId && deviceId == this->deviceId) { - std::cout << "V80 device found with BDF: " << entry.path().filename().string() - << "\n"; - std::cout - << "--------------------------------------------------------------------\n"; - } - } - } -} \ No newline at end of file diff --git a/smi/src/commands/partial_program_command.cpp b/smi/src/commands/partial_program_command.cpp deleted file mode 100644 index d12c78f4..00000000 --- a/smi/src/commands/partial_program_command.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/partial_program_command.hpp" - -#include "utils/filesystem_cache.hpp" - -PartialProgramCommand::PartialProgramCommand(const std::string& device, - const std::string& image_path) { - this->device = device; - this->imagePath = image_path; - this->dev = nullptr; - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } - - if (ami_dev_request_access(dev) != AMI_STATUS_OK) { - throw std::runtime_error("Failed to request elevated access to device"); - } -} - -void PartialProgramCommand::execute() { - PcieDriverHandler pcieDriverHandler(device + ":00.0"); - int found_current_uuid = AMI_STATUS_ERROR; - int found_new_uuid = AMI_STATUS_ERROR; - std::string new_uuid; - char current_uuid[AMI_LOGIC_UUID_SIZE] = {0}; - uint16_t dev_bdf; - ami_dev_get_pci_bdf(dev, &dev_bdf); - - if (ArgParser::endsWith(this->imagePath, ".vrtbin")) { - Vrtbin::extract(this->imagePath, FilesystemCache::getCachePath()); - std::string ami_path = std::string(std::getenv("AMI_HOME")); - std::string create_path = "mkdir -p " + ami_path + "/" + device + ":00.0/"; - std::string basePath = ami_path + "/" + device + ":00.0/"; - system(create_path.c_str()); - Vrtbin::copy(FilesystemCache::getCachePath() / "system_map.xml", basePath + "system_map.xml"); - Vrtbin::copy(FilesystemCache::getCachePath() / "version.json", basePath + "version.json"); - Vrtbin::copy(FilesystemCache::getCachePath() / "report_utilization.xml", basePath + "report_utilization.xml"); - imagePath = FilesystemCache::getCachePath() / "design.pdi"; - } - - int ret = ami_prog_device_boot(&dev, 1); // segmented PDI is on partition 1 - - if (ret != AMI_STATUS_OK && geteuid() == 0) { - throw std::runtime_error("Error booting device to partition 1"); - } - - ami_mem_bar_write(dev, 0, 0x1040000, - 1); // PMC GPIO. this is needed for reset PDI into partition 1 - ami_dev_delete(&dev); - pcieDriverHandler.execute(PcieDriverHandler::Command::REMOVE); - pcieDriverHandler.execute(PcieDriverHandler::Command::TOGGLE_SBR); - usleep(5000000); - pcieDriverHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieDriverHandler.execute(PcieDriverHandler::Command::HOTPLUG); - - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } - - found_current_uuid = ami_dev_read_uuid(dev, current_uuid); - found_new_uuid = Vrtbin::extractUUID().empty() ? AMI_STATUS_ERROR : AMI_STATUS_OK; - new_uuid = Vrtbin::extractUUID().substr(0, 32); - printf( - "----------------------------------------------\r\n" - "Device | %02x:%02x.%01x\r\n" - "----------------------------------------------\r\n" - "Current Configuration\r\n" - "----------------------------------------------\r\n" - "UUID | %s\r\n" - "----------------------------------------------\r\n" - "Incoming Configuration\r\n" - "----------------------------------------------\r\n" - "UUID | %s\r\n" - "Path | %s\r\n" - "----------------------------------------------\r\n", - AMI_PCI_BUS(dev_bdf), AMI_PCI_DEV(dev_bdf), AMI_PCI_FUNC(dev_bdf), - ((found_current_uuid != AMI_STATUS_OK) ? ("N/A") : (current_uuid)), - ((found_new_uuid != AMI_STATUS_OK) ? ("N/A") : (new_uuid.c_str())), imagePath.c_str()); - - if (new_uuid == current_uuid) { - std::cout << "Device configured with the same image.\n"; - ami_dev_delete(&dev); - return; - } - - if (ami_dev_request_access(dev) != AMI_STATUS_OK) { - std::cerr << "Error requesting access to ami device: " << device << std::endl; - throw std::runtime_error("Error requesting access to device"); - } - - if (ami_prog_download_pdi(dev, imagePath.c_str(), 0, 0, Vrtbin::progressHandler, true) != - AMI_STATUS_OK) { - std::cerr << "Error downloading image to ami device: " << device << std::endl; - throw std::runtime_error("Error downloading image to device"); - } - ami_dev_delete(&dev); - pcieDriverHandler.execute(PcieDriverHandler::Command::REMOVE); - usleep(DELAY_PARTIAL_BOOT); - pcieDriverHandler.execute(PcieDriverHandler::Command::RESCAN); - - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } - - found_current_uuid = ami_dev_read_uuid(dev, current_uuid); - - if (std::string(current_uuid) == new_uuid) { - std::cout << "\nPartial Program Command executed successfully\n"; - } else { - std::cerr << "Error: Partial Program Command failed\n"; - std::cerr << "Possible NoC configuration missmatch. Check V80 PLM logs\n"; - } -} \ No newline at end of file diff --git a/smi/src/commands/program_command.cpp b/smi/src/commands/program_command.cpp deleted file mode 100644 index 71cc23ee..00000000 --- a/smi/src/commands/program_command.cpp +++ /dev/null @@ -1,115 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/program_command.hpp" -#include "utils/filesystem_cache.hpp" - -ProgramCommand::ProgramCommand(const std::string& device, const std::string& image_path, - uint8_t partition) { - this->device = device; - this->imagePath = image_path; - this->partition = partition; - this->dev = nullptr; - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } -} - -void ProgramCommand::execute() { - int found_current_uuid = AMI_STATUS_ERROR; - int found_new_uuid = AMI_STATUS_ERROR; - std::string new_uuid; - char current_uuid[AMI_LOGIC_UUID_SIZE] = {0}; - - ImageType extension = - ArgParser::endsWith(this->imagePath, ".pdi") ? ImageType::PDI : ImageType::VRTBIN; - - if (extension == ImageType::VRTBIN) { - Vrtbin::extract(this->imagePath, FilesystemCache::getCachePath()); - std::string ami_path = std::string(std::getenv("AMI_HOME")); - std::string create_path = "mkdir -p " + ami_path + "/" + device + ":00.0/"; - std::string basePath = ami_path + "/" + device + ":00.0/"; - system(create_path.c_str()); - Vrtbin::copy(FilesystemCache::getCachePath() / "system_map.xml", basePath + "system_map.xml"); - Vrtbin::copy(FilesystemCache::getCachePath() / "version.json", basePath + "version.json"); - Vrtbin::copy(FilesystemCache::getCachePath() / "report_utilization.xml", basePath + "report_utilization.xml"); - imagePath = FilesystemCache::getCachePath() / "design.pdi"; - } - - uint16_t dev_bdf; - ami_dev_get_pci_bdf(dev, &dev_bdf); - - found_current_uuid = ami_dev_read_uuid(dev, current_uuid); - found_new_uuid = Vrtbin::extractUUID().empty() ? AMI_STATUS_ERROR : AMI_STATUS_OK; - new_uuid = Vrtbin::extractUUID().substr(0, 32); - printf( - "----------------------------------------------\r\n" - "Device | %02x:%02x.%01x\r\n" - "----------------------------------------------\r\n" - "Current Configuration\r\n" - "----------------------------------------------\r\n" - "UUID | %s\r\n" - "----------------------------------------------\r\n" - "Incoming Configuration\r\n" - "----------------------------------------------\r\n" - "UUID | %s\r\n" - "Path | %s\r\n" - "Partition | %d\r\n" - "----------------------------------------------\r\n", - AMI_PCI_BUS(dev_bdf), AMI_PCI_DEV(dev_bdf), AMI_PCI_FUNC(dev_bdf), - ((found_current_uuid != AMI_STATUS_OK) ? ("N/A") : (current_uuid)), - ((found_new_uuid != AMI_STATUS_OK) ? ("N/A") : (new_uuid.c_str())), imagePath.c_str(), - partition); - - if (ami_dev_request_access(dev) != AMI_STATUS_OK) { - std::cerr << "Error requesting access to ami device: " << device << std::endl; - throw std::runtime_error("Error requesting access to device"); - } - - if (ami_prog_download_pdi(dev, imagePath.c_str(), 0, partition, Vrtbin::progressHandler, - false) != AMI_STATUS_OK) { - std::cerr << "Error downloading image to ami device: " << device << std::endl; - throw std::runtime_error("Error downloading image to device"); - } - - bootDevice(); -} - -void ProgramCommand::bootDevice() { - int ret = ami_prog_device_boot(&dev, 1); - if (ret != AMI_STATUS_OK && geteuid() == 0) { // for root users this should not matter - throw std::runtime_error("Failed to boot device"); - } - PcieDriverHandler pcieHandler(device + ":00.0"); - ami_mem_bar_write(dev, 0, 0x1040000, 1); - ami_dev_delete(&dev); - pcieHandler.execute(PcieDriverHandler::Command::REMOVE); - pcieHandler.execute(PcieDriverHandler::Command::TOGGLE_SBR); - usleep(5000000); - pcieHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieHandler.execute(PcieDriverHandler::Command::HOTPLUG); - std::cout << device.c_str() << "\n"; - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } - std::cout << "Image programmed successfully" << std::endl; -} diff --git a/smi/src/commands/query_command.cpp b/smi/src/commands/query_command.cpp deleted file mode 100644 index 548eb4aa..00000000 --- a/smi/src/commands/query_command.cpp +++ /dev/null @@ -1,347 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/query_command.hpp" - -#define SYSTEM_MAP_PATH "%s/%s:00.0/system_map.xml" -#define VERSION_PATH "%s/%s:00.0/version.json" -#define QDMA_QUEUE_PATH "/dev/qdma%s001-MM-0" // /dev/qdma:.-MM- -#define QDMA_QMAX_PATH "/sys/bus/pci/devices/0000:%s:00.1/qdma/qmax" -#define BUFFER_SIZE 1024 - -QueryCommand::QueryCommand(const std::string& device) : device(device) {} - -void QueryCommand::execute() { queryDevice(); } - -void QueryCommand::queryDevice() { - std::string bdf = device; - if (bdf.empty()) { - std::cerr << "Error: BDF is required for query" << std::endl; - return; - } - - printAmiDetails(); - queryKernels(bdf); - queryQueues(bdf); -} - -void QueryCommand::queryKernels(const std::string& bdf) { - std::string bus = bdf; - char path[256], versionPath[256]; - char* amiHome = getenv("AMI_HOME"); - if (amiHome == nullptr) { - std::cerr << "Error: AMI_HOME environment variable is not set" << std::endl; - return; - } - sprintf(path, SYSTEM_MAP_PATH, amiHome, bus.c_str()); - sprintf(versionPath, VERSION_PATH, amiHome, bus.c_str()); - - xmlDocPtr document = xmlReadFile(path, NULL, 0); - if (document == NULL) { - std::cerr << "Error: could not parse file " << path << std::endl; - return; - } - xmlNode* rootNode = xmlDocGetRootElement(document); - if (rootNode == NULL) { - std::cerr << "Error: could not get root element" << std::endl; - return; - } - Vrtbin::extractAndPrintInfo(versionPath); - for (xmlNode* kernelNode = rootNode->children; kernelNode; kernelNode = kernelNode->next) { - if (kernelNode->type == XML_ELEMENT_NODE && - xmlStrcmp(kernelNode->name, BAD_CAST "Kernel") == 0) { - std::string name, baseAddr, range; - for (xmlNode* childNode = kernelNode->children; childNode; - childNode = childNode->next) { - if (childNode->type == XML_ELEMENT_NODE) { - if (xmlStrcmp(childNode->name, BAD_CAST "Name") == 0) { - name = (char*)xmlNodeGetContent(childNode); - } else if (xmlStrcmp(childNode->name, BAD_CAST "BaseAddress") == 0) { - baseAddr = (char*)xmlNodeGetContent(childNode); - } else if (xmlStrcmp(childNode->name, BAD_CAST "Range") == 0) { - range = (char*)xmlNodeGetContent(childNode); - } - } - } - std::cout << "\t------------------------------------------------------------\n"; - std::cout << "\tKernel Information\n"; - std::cout << "\t------------------------------------------------------------\n"; - std::cout << "\tKernel Name | " << name << "\n"; - std::cout << "\tBase Address | " << baseAddr << "\n"; - std::cout << "\tRange | " << range << "\n\n"; - } - } - xmlFreeDoc(document); -} - -void QueryCommand::queryQueues(const std::string& bdf) { - std::string bus = bdf; - char queuePath[256], qmaxPath[256]; - char buffer[BUFFER_SIZE]; - int fd; - ssize_t bytesRead; - - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "QDMA Queue Status\n"; - std::cout << "--------------------------------------------------------------------\n"; - sprintf(queuePath, QDMA_QUEUE_PATH, bus.c_str()); - sprintf(qmaxPath, QDMA_QMAX_PATH, bus.c_str()); - - fd = open(queuePath, O_RDONLY); - if (fd < 0) { - std::cerr << "QDMA MM Queue not present. Expected queue " << queuePath << std::endl; - return; - } else { - std::cout << "QDMA MM Queue present at " << queuePath << ", mode bi" << std::endl; - close(fd); - } - - fd = open(qmaxPath, O_RDONLY); - if (fd < 0) { - std::cerr << "Could not open QMAX file " << qmaxPath << std::endl; - return; - } else { - bytesRead = read(fd, buffer, sizeof(buffer) - 1); - if (bytesRead < 0) { - std::cerr << "Error reading from QMAX file " << qmaxPath << std::endl; - close(fd); - return; - } else { - buffer[bytesRead] = '\0'; - std::cout << "Max allocable queues: " << buffer << std::endl; - } - close(fd); - } -} - -void QueryCommand::printAmiDetails() { - ami_device* dev = nullptr; - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error: AMI Device " << device << " not found" << std::endl; - return; - } - std::cout << "Query device: " << device << ":00.0" << std::endl; - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "AMI Device Information\n"; - std::cout << "--------------------------------------------------------------------\n"; - - char devName[AMI_DEV_NAME_SIZE]; - - if (ami_dev_get_name(dev, devName) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get device name" << std::endl; - return; - } - - char devState[AMI_DEV_STATE_SIZE]; - - if (ami_dev_get_state(dev, devState) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get device state" << std::endl; - return; - } - - char uuid[AMI_LOGIC_UUID_SIZE]; - if (ami_dev_read_uuid(dev, uuid) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to read UUID" << std::endl; - return; - } - - struct ami_version ami_version; - - if (ami_get_driver_version(&ami_version) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get driver version" << std::endl; - return; - } - - struct ami_version api_version; - - if (ami_get_api_version(&api_version) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get API version" << std::endl; - return; - } - - struct amc_version amc_version; - - if (ami_dev_get_amc_version(dev, &amc_version) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get AMC version" << std::endl; - return; - } - - std::cout << "Device Name | " << devName << "\n"; - std::cout << "Device State | " << devState << "\n"; - std::cout << "Logic UUID | " << std::string(uuid).substr(0, 32) << "\n"; - std::cout << "Driver Version | " << std::to_string(ami_version.major) << "." - << std::to_string(ami_version.minor) << "." << std::to_string(ami_version.patch) - << "\n"; - std::cout << "API Version | " << std::to_string(api_version.major) << "." - << std::to_string(api_version.minor) << "." << std::to_string(api_version.patch) - << "\n"; - std::cout << "FW Version | " << std::to_string(amc_version.major) << "." - << std::to_string(amc_version.minor) << "." << std::to_string(amc_version.patch) - << "\n"; - std::cout << "\n"; - - uint16_t pciVendor; - if (ami_dev_get_pci_vendor(dev, &pciVendor) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get PCI vendor" << std::endl; - return; - } - - uint16_t pciDevice; - if (ami_dev_get_pci_device(dev, &pciDevice) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get PCI device" << std::endl; - return; - } - - uint8_t currentLinkSpeed, maxLinkSpeed; - if (ami_dev_get_pci_link_speed(dev, ¤tLinkSpeed, &maxLinkSpeed) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get PCI link speed" << std::endl; - return; - } - - uint8_t currentLinkWidth, maxLinkWidth; - if (ami_dev_get_pci_link_width(dev, ¤tLinkWidth, &maxLinkWidth) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get PCI link width" << std::endl; - return; - } - - uint8_t numaNode; - - if (ami_dev_get_pci_numa_node(dev, &numaNode) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get PCI NUMA mode" << std::endl; - return; - } - - char cpuList[AMI_PCI_CPULIST_SIZE]; - if (ami_dev_get_pci_cpulist(dev, cpuList) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get CPU affinity" << std::endl; - return; - } - - char productName[AMI_MFG_INFO_MAX_STR], boardRev[AMI_MFG_INFO_MAX_STR], - eepromVersion[AMI_MFG_INFO_MAX_STR], boardSerial[AMI_MFG_INFO_MAX_STR], - partNum[AMI_MFG_INFO_MAX_STR], mPartNum[AMI_MFG_INFO_MAX_STR], - macAddr[AMI_MFG_INFO_MAX_STR], macAddrN[AMI_MFG_INFO_MAX_STR], mDate[AMI_MFG_INFO_MAX_STR], - uuid_system[AMI_MFG_INFO_MAX_STR]; - - if (ami_mfg_get_info(dev, AMI_MFG_PRODUCT_NAME, productName) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get product name" << std::endl; - return; - } - - if (ami_mfg_get_info(dev, AMI_MFG_BOARD_REV, boardRev) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get board revision" << std::endl; - return; - } - - if (ami_mfg_get_info(dev, AMI_MFG_EEPROM_VERSION, eepromVersion) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get eeprom version" << std::endl; - return; - } - if (ami_mfg_get_info(dev, AMI_MFG_BOARD_SERIAL, boardSerial) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get board serial" << std::endl; - return; - } - if (ami_mfg_get_info(dev, AMI_MFG_PART_NUM, partNum) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get part number" << std::endl; - return; - } - if (ami_mfg_get_info(dev, AMI_MFG_M_PART_NUM, mPartNum) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get m part number" << std::endl; - return; - } - - if (ami_mfg_get_info(dev, AMI_MFG_MAC_ADDR, macAddr) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get mac addr" << std::endl; - return; - } - - if (ami_mfg_get_info(dev, AMI_MFG_MAC_ADDR_N, macAddrN) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get mac addr n" << std::endl; - return; - } - - if (ami_mfg_get_info(dev, AMI_MFG_M_DATE, mDate) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get m date" << std::endl; - return; - } - - if (ami_mfg_get_info(dev, AMI_MFG_UUID, uuid_system) != AMI_STATUS_OK) { - std::cerr << "Error: Failed to get uuid" << std::endl; - return; - } - - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Manufacturing Information\n"; - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Product Name | " << productName << "\n"; - std::cout << "Board Revision | " << boardRev << "\n"; - std::cout << "EEPROM Version | " << eepromVersion << "\n"; - std::cout << "Board Serial Number | " << boardSerial << "\n"; - std::cout << "Part Number | " << partNum << "\n"; - std::cout << "M Part Number | " << mPartNum << "\n"; - std::cout << "MAC Address | " << macAddr << "\n"; - std::cout << "MAC Address N | " << macAddrN << "\n"; - formatManufacturingDate(std::strtoul(mDate, nullptr, 10)); - std::cout << "UUID | " << uuid_system << "\n\n"; - - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "PCI Information\n"; - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "PCI Vendor | " << std::hex << std::showbase << pciVendor - << std::dec << "\n"; - std::cout << "PCI Device | " << std::hex << std::showbase << pciDevice - << std::dec << "\n"; - std::cout << "Current Link Speed | Gen" << (int)currentLinkSpeed << " (max Gen" - << (int)maxLinkSpeed << ")\n"; - std::cout << "Current Link Width | x" << (int)currentLinkWidth << " (max x" - << (int)maxLinkWidth << ")\n"; - std::cout << "NUMA Mode | " << (int)numaNode << "\n"; - std::cout << "CPU Affinity | " << cpuList << "\n\n"; -} - -void QueryCommand::formatManufacturingDate(long manufacturing_date_mins) { - char manufacturing_date_str[META_MAX_STR_LEN] = {0}; - struct tm info = {0}; - - if (manufacturing_date_mins) { - info.tm_year = 96; // Base year 1970 - info.tm_mon = 1; - info.tm_mday = 1; - info.tm_hour = 0; - info.tm_min = manufacturing_date_mins; - info.tm_sec = 0; - info.tm_isdst = -1; - - if (mktime(&info) == -1) { - std::cerr << "Error: mktime failed" << std::endl; - return; - } - - if (!strftime(manufacturing_date_str, sizeof(manufacturing_date_str), "%c", &info)) { - std::cerr << "Error: strftime failed" << std::endl; - return; - } - } else { - std::cerr << "Error: Invalid manufacturing date minutes" << std::endl; - return; - } - - std::cout << "MFG Date | " << manufacturing_date_str << std::endl; -} diff --git a/smi/src/commands/reset_command.cpp b/smi/src/commands/reset_command.cpp deleted file mode 100644 index fa0cc529..00000000 --- a/smi/src/commands/reset_command.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/reset_command.hpp" - -ResetCommand::ResetCommand(const std::string& device) : device(device) { - this->dev = nullptr; - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } - - if (ami_dev_request_access(dev) != AMI_STATUS_OK) { - throw std::runtime_error("Failed to request elevated access to device"); - } -} - -void ResetCommand::execute() { - PcieDriverHandler pcieDriverHandler(device + ":00.0"); - - int ret = ami_prog_device_boot(&dev, 1); // segmented PDI is on partition 1 - - if (ret != AMI_STATUS_OK && geteuid() == 0) { - throw std::runtime_error("Error booting device to partition 1"); - } - - ami_mem_bar_write(dev, 0, 0x1040000, 1); - ami_dev_delete(&dev); - pcieDriverHandler.execute(PcieDriverHandler::Command::REMOVE); - pcieDriverHandler.execute(PcieDriverHandler::Command::TOGGLE_SBR); - usleep(5000000); - pcieDriverHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieDriverHandler.execute(PcieDriverHandler::Command::HOTPLUG); - - if (ami_dev_find(device.c_str(), &dev) != AMI_STATUS_OK) { - std::cerr << "Error finding ami device: " << device << std::endl; - throw std::runtime_error("Error finding device"); - } - - std::cout << "Device resetted successfully" << std::endl; - ami_dev_delete(&dev); -} \ No newline at end of file diff --git a/smi/src/commands/resource_command.cpp b/smi/src/commands/resource_command.cpp deleted file mode 100644 index e70de2f8..00000000 --- a/smi/src/commands/resource_command.cpp +++ /dev/null @@ -1,228 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/resource_command.hpp" - -ResourceCommand::ResourceCommand(const std::string& device) : device(device) { - std::string amiHome = std::string(getenv("AMI_HOME")); - if (amiHome.empty()) { - std::cerr << "AMI_HOME environment variable is not set." << std::endl; - exit(1); - } - char filePath[1024]; - sprintf(filePath, RESOURCE_UTILIZATION_FILE, amiHome.c_str(), device.c_str()); - parseXML(std::string(filePath)); - printResources(); -} - -void ResourceCommand::parseXML(const std::string& filename) { - xmlDoc* doc = xmlReadFile(filename.c_str(), NULL, 0); - if (doc == NULL) { - std::cerr << "Failed to parse XML file: " << filename << std::endl; - exit(1); - } - - xmlNode* rootElement = xmlDocGetRootElement(doc); - if (rootElement) { - parseInstance(rootElement, rootInstance); - } - - xmlFreeDoc(doc); - xmlCleanupParser(); -} - -void ResourceCommand::parseInstance(xmlNode* node, Instance& instance) { - std::regex re("(\\d+)\\((\\d+\\.\\d+)%\\)"); - std::smatch match; - for (xmlNode* curNode = node; curNode; curNode = curNode->next) { - if (curNode->type == XML_ELEMENT_NODE) { - if (xmlStrcmp(curNode->name, BAD_CAST "UtilizationReport") == 0) { - parseInstance(curNode->children, instance); - continue; - } - if (xmlStrcmp(curNode->name, BAD_CAST "Instance") == 0) { - Instance childInstance; - for (xmlNode* child = curNode->children; child; child = child->next) { - if (child->type == XML_ELEMENT_NODE) { - std::string content = (const char*)xmlNodeGetContent(child); - if (xmlStrcmp(child->name, BAD_CAST "Name") == 0) { - childInstance.name = content; - } else if (xmlStrcmp(child->name, BAD_CAST "Module") == 0) { - childInstance.module = content; - } else if (xmlStrcmp(child->name, BAD_CAST "TotalLUTs") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.totalLUTs.first = std::stoi(match.str(1)); - childInstance.totalLUTs.second = std::stof(match.str(2)); - } else { - childInstance.totalLUTs.first = 0; - childInstance.totalLUTs.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "LogicLUTs") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.logicLUTs.first = std::stoi(match.str(1)); - childInstance.logicLUTs.second = std::stof(match.str(2)); - } else { - childInstance.logicLUTs.first = 0; - childInstance.logicLUTs.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "LUTRAMs") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.lutRAMs.first = std::stoi(match.str(1)); - childInstance.lutRAMs.second = std::stof(match.str(2)); - } else { - childInstance.lutRAMs.first = 0; - childInstance.lutRAMs.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "SRLs") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.srls.first = std::stoi(match.str(1)); - childInstance.srls.second = std::stof(match.str(2)); - } else { - childInstance.srls.first = 0; - childInstance.srls.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "FFs") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.ffs.first = std::stoi(match.str(1)); - childInstance.ffs.second = std::stof(match.str(2)); - } else { - childInstance.ffs.first = 0; - childInstance.ffs.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "RAMB36") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.ramb36.first = std::stoi(match.str(1)); - childInstance.ramb36.second = std::stof(match.str(2)); - } else { - childInstance.ramb36.first = 0; - childInstance.ramb36.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "RAMB18") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.ramb18.first = std::stoi(match.str(1)); - childInstance.ramb18.second = std::stof(match.str(2)); - } else { - childInstance.ramb18.first = 0; - childInstance.ramb18.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "URAM") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.uram.first = std::stoi(match.str(1)); - childInstance.uram.second = std::stof(match.str(2)); - } else { - childInstance.uram.first = 0; - childInstance.uram.second = 0.0; - } - } else if (xmlStrcmp(child->name, BAD_CAST "DSPBlocks") == 0) { - if (std::regex_search(content, match, re) && match.size() == 3) { - childInstance.dspBlocks.first = std::stoi(match.str(1)); - childInstance.dspBlocks.second = std::stof(match.str(2)); - } else { - childInstance.dspBlocks.first = 0; - childInstance.dspBlocks.second = 0.0; - } - } - } - } - parseInstance(curNode->children, childInstance); - instance.children.push_back(childInstance); - } - } - } -} - -void ResourceCommand::printResources() { - bool headerPrinted = false; - std::cout << "Total usage" << std::endl; - printSpecificInstance(rootInstance, "top_wrapper", headerPrinted); - std::cout << "Base logic usage. AVED + VRT + User kernels" << std::endl; - printSpecificInstance(rootInstance, "base_logic", headerPrinted); - const std::vector excludeList = {"axi_smbus_rpu", "gcq_m2r", "hw_discovery", - "pcie_slr0_mgmt_sc", "rpu_sc", "uuid_rom", - "clk_wiz", "sys_rst", "noc_xbar"}; - std::cout << "User kernels usage" << std::endl; - printChildrenOfBaseLogic(rootInstance, excludeList, headerPrinted); -} - -void ResourceCommand::printInstance(const Instance& instance, int level, - bool& headerPrinted) const { - if (!headerPrinted) { - // Print the table header - printf( - "+--------------------+--------------------+--------------------+--------------------+-" - "-------------------+--------------------+--------------------+\n"); - printf( - "| Name | TotalLUTs | LogicLUTs | FFs | " - "BlockRAM Tiles | URAM | DSPBlocks |\n"); - printf( - "+--------------------+--------------------+--------------------+--------------------+-" - "-------------------+--------------------+--------------------+\n"); - headerPrinted = true; - } - - // Helper function to format the value and percentage - auto formatValue = [](int value, float percentage) { - std::ostringstream oss; - oss << value << "(" << std::fixed << std::setprecision(2) << percentage << "%)"; - return oss.str(); - }; - - // Print the instance details - printf("| %-18s | %-18s | %-18s | %-18s | %-18s | %-18s | %-18s |\n", instance.name.c_str(), - formatValue(instance.totalLUTs.first, instance.totalLUTs.second).c_str(), - formatValue(instance.logicLUTs.first, instance.logicLUTs.second).c_str(), - formatValue(instance.ffs.first, instance.ffs.second).c_str(), - formatValue(instance.ramb36.first + instance.ramb18.first / 2, - instance.ramb36.second + instance.ramb18.second / 2) - .c_str(), - formatValue(instance.uram.first, instance.uram.second).c_str(), - formatValue(instance.dspBlocks.first, instance.dspBlocks.second).c_str()); - - printf( - "+--------------------+--------------------+--------------------+--------------------+-----" - "---------------+--------------------+--------------------+\n"); -} -void ResourceCommand::printSpecificInstance(const Instance& instance, const std::string& targetName, - bool headerPrinted) const { - if (instance.name == targetName) { - printInstance(instance, 0, headerPrinted); - return; - } - for (const auto& child : instance.children) { - printSpecificInstance(child, targetName, headerPrinted); - } -} - -void ResourceCommand::printChildrenOfBaseLogic(const Instance& instance, - const std::vector& excludeList, - bool& headerPrinted) const { - if (instance.name == "base_logic") { - for (const auto& child : instance.children) { - if (std::find(excludeList.begin(), excludeList.end(), child.name) == - excludeList.end()) { - printInstance(child, 1, headerPrinted); - } - } - return; - } - for (const auto& child : instance.children) { - printChildrenOfBaseLogic(child, excludeList, headerPrinted); - } -} \ No newline at end of file diff --git a/smi/src/commands/validate_command.cpp b/smi/src/commands/validate_command.cpp deleted file mode 100644 index 9da00a3b..00000000 --- a/smi/src/commands/validate_command.cpp +++ /dev/null @@ -1,555 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "commands/validate_command.hpp" - -#include -#include - -#include -#include -#include -#include -#include -#include - -static std::atomic pci_bw_result(0); - -ValidateCommand::ValidateCommand(const std::string& device) : device(device) {} - -void ValidateCommand::execute() { - if (device.empty()) { - std::cerr << "Error: Device is required for validation" << std::endl; - return; - } - - std::cout << "Running validation for device: " << device << std::endl; - - uint64_t address = 0; - uint64_t size = DEFAULT_TEST_SIZE; - uint64_t offset = 0; - uint64_t count = DEFAULT_COUNT_TIMES; - int verbose = 0; - int read = 0; - int write = 0; - int port = 0; - char cmd[256]; - sprintf(cmd, "/dev/qdma%s001-MM-0", device.c_str()); - if (access(cmd, F_OK) != 0) { - std::cerr << "Error: Device " << cmd << " does not exist" << std::endl; - std::cerr << "Please run as root: /usr/local/vrt/setup_queues.sh " << cmd << " --mm 0 bi\n"; - return; - } - test_dma(std::string(cmd), address, size, offset, count, verbose); - - std::cout << "All tests passed" << std::endl; -} - -void ValidateCommand::test_dma(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose) { - int ret = -1; - addr = ADDR_START_HBM; - std::cout << "Performing seq RW test for HBM\n"; - ret = test_dma_write(devname, addr, size, offset, count, verbose); - if (ret < 0) { - std::cerr << "Error: Write test failed" << std::endl; - return; - } - ret = test_dma_read(devname, addr, size, offset, count, verbose); - if (ret < 0) { - std::cerr << "Error: Read test failed" << std::endl; - return; - } - addr = ADDR_START_DDR; - std::cout << "Performing seq RW test for DDR\n"; - ret = test_dma_write(devname, addr, size, offset, count, verbose); - if (ret < 0) { - std::cerr << "Error: Write test failed" << std::endl; - return; - } - ret = test_dma_read(devname, addr, size, offset, count, verbose); - if (ret < 0) { - std::cerr << "Error: Read test failed" << std::endl; - return; - } - ret = run_sim_seq_rw_threads(devname, size, offset, count, verbose); - if (ret < 0) { - std::cerr << "Error: Simultaneous RW test failed" << std::endl; - return; - } - ret = run_sim_rw_per_memory(devname, addr, size, offset, count, verbose, "hbm"); - if (ret < 0) { - std::cerr << "Error: Simultaneous RW test per memory failed" << std::endl; - return; - } - ret = run_sim_rw_per_memory(devname, addr, size, offset, count, verbose, "ddr"); - if (ret < 0) { - std::cerr << "Error: Simultaneous RW test per memory failed" << std::endl; - return; - } - ret = run_pcie_bw_test(devname, size, offset, count, verbose); - if (ret < 0) { - std::cerr << "Error: PCIe bandwidth test failed" << std::endl; - return; - } -} - -std::size_t ValidateCommand::test_dma_write(const std::string& devname, uint64_t addr, - uint64_t size, uint64_t offset, uint64_t count, - int verbose) { - uint64_t i; - char* buffer = NULL; - char* allocated = NULL; - struct timespec ts_start, ts_end; - int fpga_fd = open(devname.c_str(), O_RDWR); - double total_time = 0; - double result; - double avg_time = 0; - int ret = EXIT_FAILURE; - if (fpga_fd < 0) { - fprintf(stderr, "unable to open device %s, %d.\n", devname.c_str(), fpga_fd); - return EXIT_FAILURE; - } - posix_memalign((void**)&allocated, 4096 /*alignment */, size + 4096); - if (!allocated) { - fprintf(stderr, "OOM %lu.\n", size + 4096); - close(fpga_fd); - free(allocated); - return EXIT_FAILURE; - } - buffer = allocated + offset; - if (verbose) { - fprintf(stdout, "host buffer 0x%lx = %p\n", size + 4096, buffer); - } - for (i = 0; i < count; i++) { - clock_gettime(CLOCK_MONOTONIC, &ts_start); - ret = write_from_buffer(devname, fpga_fd, buffer, size, addr); - if (ret < 0) { - fprintf(stderr, "Could not write to device buffer.\n"); - close(fpga_fd); - free(allocated); - return EXIT_FAILURE; - } - clock_gettime(CLOCK_MONOTONIC, &ts_end); - timespec_sub(&ts_end, &ts_start); - total_time += (ts_end.tv_sec + ((double)ts_end.tv_nsec / NSEC_DIV)); - if (verbose) { - fprintf(stdout, "CLOCK_MONOTONIC %ld.%09ld sec. write %lu bytes\n", ts_end.tv_sec, - ts_end.tv_nsec, size); - } - } - avg_time = (double)total_time / (double)count; - result = ((double)size) / avg_time; - // pthread_mutex_lock(&print_mutex); - print_results(devname, addr, total_time, avg_time, size, result, TEST_TYPE_WRITE, verbose); - // pthread_mutex_unlock(&print_mutex); - close(fpga_fd); - free(allocated); - return 0; -} - -std::size_t ValidateCommand::test_dma_read(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose) { - uint64_t i; - char* buffer = NULL; - char* allocated = NULL; - struct timespec ts_start, ts_end; - int fpga_fd = open(devname.c_str(), O_RDWR | O_NONBLOCK); - double total_time = 0; - double result; - double avg_time = 0; - int ret = EXIT_FAILURE; - if (fpga_fd < 0) { - fprintf(stderr, "unable to open device %s, %d.\n", devname.c_str(), fpga_fd); - return 1; - } - posix_memalign((void**)&allocated, 4096 /*alignment */, size + 4096); - if (!allocated) { - fprintf(stderr, "OOM %lu.\n", size + 4096); - close(fpga_fd); - free(allocated); - return EXIT_FAILURE; - } - buffer = allocated + offset; - if (verbose) fprintf(stdout, "host buffer 0x%lx = %p\n", size + 4096, buffer); - - for (i = 0; i < count; i++) { - clock_gettime(CLOCK_MONOTONIC, &ts_start); - /* lseek & read data from AXI MM into buffer using SGDMA */ - ret = read_to_buffer(devname, fpga_fd, buffer, size, addr); - if (ret < 0) { - fprintf(stderr, "Could not read to device buffer.\n"); - close(fpga_fd); - free(allocated); - return 1; - } - clock_gettime(CLOCK_MONOTONIC, &ts_end); - - /* subtract the start time from the end time */ - timespec_sub(&ts_end, &ts_start); - total_time += (ts_end.tv_sec + ((double)ts_end.tv_nsec / NSEC_DIV)); - /* a bit less accurate but side-effects are accounted for */ - if (verbose) { - fprintf(stdout, "#%lu: CLOCK_MONOTONIC %ld.%09ld sec. read %lu bytes\n", i, - ts_end.tv_sec, ts_end.tv_nsec, size); - } - } - avg_time = (double)total_time / (double)count; - result = ((double)size) / avg_time; - // pthread_mutex_lock(&print_mutex); - this->print_results(devname, addr, total_time, avg_time, size, result, TEST_TYPE_READ, verbose); - // pthread_mutex_unlock(&print_mutex); - close(fpga_fd); - free(allocated); - return 0; -} - -std::size_t ValidateCommand::write_from_buffer(const std::string& fname, int fd, char* buffer, - uint64_t size, uint64_t base) { - ssize_t rc; - uint64_t count = 0; - char* buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > RW_MAX_SIZE) bytes = RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - fprintf(stderr, "%s, seek off 0x%lx failed %zd.\n", fname.c_str(), offset, rc); - perror("seek file"); - return -EIO; - } - if (rc != offset) { - fprintf(stderr, "%s, seek off 0x%lx != 0x%lx.\n", fname.c_str(), rc, offset); - return -EIO; - } - } - - /* write data to file from memory buffer */ - rc = write(fd, buf, bytes); - if (rc < 0) { - fprintf(stderr, "%s, W off 0x%lx, 0x%lx failed %zd.\n", fname.c_str(), offset, bytes, - rc); - perror("write file"); - return -EIO; - } - if (rc != bytes) { - fprintf(stderr, "%s, W off 0x%lx, 0x%lx != 0x%lx.\n", fname.c_str(), offset, rc, bytes); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - } while (count < size); - - if (count != size) { - fprintf(stderr, "%s, R failed 0x%lx != 0x%lx.\n", fname.c_str(), count, size); - return -EIO; - } - return count; -} - -std::size_t ValidateCommand::read_to_buffer(const std::string& fname, int fd, char* buffer, - uint64_t size, uint64_t base) { - ssize_t rc; - uint64_t count = 0; - char* buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > RW_MAX_SIZE) bytes = RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - fprintf(stderr, "%s, seek off 0x%lx failed %zd.\n", fname.c_str(), offset, rc); - perror("seek file"); - return -EIO; - } - if (rc != offset) { - fprintf(stderr, "%s, seek off 0x%lx != 0x%lx.\n", fname.c_str(), rc, offset); - return -EIO; - } - } - - /* read data from file into memory buffer */ - rc = read(fd, buf, bytes); - if (rc < 0) { - fprintf(stderr, "%s, read off 0x%lx + 0x%lx failed %zd.\n", fname.c_str(), offset, - bytes, rc); - perror("read file"); - return -EIO; - } - if (rc != bytes) { - fprintf(stderr, "%s, R off 0x%lx, 0x%lx != 0x%lx.\n", fname.c_str(), count, rc, bytes); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - } while (count < size); - - if (count != size) { - fprintf(stderr, "%s, R failed 0x%lx != 0x%lx.\n", fname.c_str(), count, size); - return -EIO; - } - return count; -} - -void ValidateCommand::print_results(const std::string& devname, uint64_t addr, double total_time, - double avg_time, double size, double result, test_type type, - int verbose) { - std::string test_type_str = (type == TEST_TYPE_READ) ? "Read" : "Write"; - std::string memory_type = (addr >= ADDR_START_HBM && addr < ADDR_START_DDR) ? "HBM" : "DDR"; - - if (verbose) { - printf( - "+----------------+----------------+----------------+----------------+----------------+" - "----------------+-----------------+\n"); - printf( - "| Test Type | Device | Memory Type | Total Time (ns)| Avg Time (ns) " - "| Size (GB) | Bandwidth (GB/s)|\n"); - printf( - "+----------------+----------------+----------------+----------------+----------------+" - "----------------+-----------------+\n"); - printf("| %-14s | %-14s | %-14s | %-14.2f | %-14.2f | %-14.2f | %-14.2f |\n", - test_type_str.c_str(), devname.c_str(), memory_type.c_str(), total_time, avg_time, - size / GB_DIV, result / GB_DIV); - printf( - "+----------------+----------------+----------------+----------------+----------------+" - "----------------+-----------------\n"); - } else { - printf("+----------------+----------------+-----------------+\n"); - printf("| Test Type | Memory Type | Bandwidth (GB/s)|\n"); - printf("+----------------+----------------+-----------------+\n"); - printf("| %-14s | %-14s | %-14.2f |\n", test_type_str.c_str(), memory_type.c_str(), - result / GB_DIV); - printf("+----------------+----------------+-----------------+\n"); - } -} - -void ValidateCommand::print_pci_bandwidth(double pci_bw_result) { - printf("+---------------------------------------------------+\n"); - printf("| Total PCIe Bandwidth (GB/s): %-19.2f |\n", pci_bw_result); - printf("+---------------------------------------------------+\n"); -} - -void ValidateCommand::dma_read_thread(thread_data_t* data) { - test_dma_read(data->devname, data->addr, data->size, data->offset, data->count, data->verbose); -} - -void ValidateCommand::dma_write_thread(thread_data_t* data) { - test_dma_write(data->devname, data->addr, data->size, data->offset, data->count, data->verbose); -} - -int ValidateCommand::run_sim_seq_rw_threads(const std::string& devname, uint64_t size, - uint64_t offset, uint64_t count, int verbose) { - std::cout << "Performing simultaneous RW test for HBM\n"; - thread_data_t args_hbm, args_ddr; - args_hbm.devname = devname; - args_hbm.addr = ADDR_START_HBM; - args_hbm.size = size; - args_hbm.offset = offset; - args_hbm.count = count; - args_hbm.verbose = verbose; - args_ddr.devname = devname; - args_ddr.addr = ADDR_START_DDR; - args_ddr.size = size; - args_ddr.offset = offset; - args_ddr.count = count; - args_ddr.verbose = verbose; - - std::thread thread_read_hbm(&ValidateCommand::dma_read_thread, this, &args_hbm); - std::thread thread_write_hbm(&ValidateCommand::dma_write_thread, this, &args_hbm); - thread_read_hbm.join(); - thread_write_hbm.join(); - - std::cout << "Performing simultaneous RW test for DDR\n"; - std::thread thread_read_ddr(&ValidateCommand::dma_read_thread, this, &args_ddr); - std::thread thread_write_ddr(&ValidateCommand::dma_write_thread, this, &args_ddr); - thread_read_ddr.join(); - thread_write_ddr.join(); - - return EXIT_SUCCESS; -} - -int ValidateCommand::run_sim_rw_per_memory(const std::string& devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, int verbose, - const std::string& mem_type) { - std::cout << "Running bandwidth test for HBM memory\n"; - std::cout << "Running simultaneous write test on multiple HBM channels\n"; - - thread_data_t args_chan0, args_chan1; - args_chan0.devname = devname; - args_chan0.addr = addr; - args_chan0.size = size; - args_chan0.offset = offset; - args_chan0.count = count; - args_chan0.verbose = verbose; - - std::thread write_chan_0(&ValidateCommand::dma_write_thread, this, &args_chan0); - - args_chan1.devname = devname; - if (mem_type == "hbm") { - args_chan1.addr = addr + (uint64_t)2 * SIZE_PER_HBM_CHANNEL; - } else { - args_chan1.addr = ADDR_START_DIMM_DDR; - } - args_chan1.size = size; - args_chan1.offset = offset; - args_chan1.count = count; - args_chan1.verbose = verbose; - - std::thread write_chan_1(&ValidateCommand::dma_write_thread, this, &args_chan1); - - write_chan_0.join(); - write_chan_1.join(); - - std::thread read_chan_0(&ValidateCommand::dma_read_thread, this, &args_chan0); - std::thread read_chan_1(&ValidateCommand::dma_read_thread, this, &args_chan1); - - read_chan_0.join(); - read_chan_1.join(); - - return EXIT_SUCCESS; -} - -int ValidateCommand::run_pcie_bw_test(const std::string& devname, uint64_t size, uint64_t offset, - uint64_t count, int verbose) { - int ret = EXIT_SUCCESS; - int num_of_threads = 8; - std::vector write_threads; - std::vector args_chan(num_of_threads); - - for (int i = 0; i < num_of_threads; i++) { - args_chan[i].devname = devname; - args_chan[i].addr = ADDR_START_DDR + i * 0x80000000; // ADDR_START_HBM - args_chan[i].size = size; - args_chan[i].offset = offset; - args_chan[i].count = count; - args_chan[i].verbose = verbose; - } - - for (int i = 0; i < num_of_threads; i++) { - write_threads.emplace_back(&ValidateCommand::dma_write_thread_pcie, this, &args_chan[i]); - } - - for (auto& thread : write_threads) { - if (thread.joinable()) { - thread.join(); - } else { - std::cerr << "Error joining write thread" << std::endl; - ret = EXIT_FAILURE; - } - } - - print_pci_bandwidth(pci_bw_result); - return ret; -} - -double ValidateCommand::test_dma_write_pcie(const std::string& devname, uint64_t addr, - uint64_t size, uint64_t offset, uint64_t count, - int verbose) { - uint64_t i; - char* buffer = NULL; - char* allocated = NULL; - struct timespec ts_start, ts_end; - int fpga_fd = open(devname.c_str(), O_RDWR); - double total_time = 0; - double result; - double avg_time = 0; - int ret = EXIT_FAILURE; - if (fpga_fd < 0) { - fprintf(stderr, "unable to open device %s, %d.\n", devname.c_str(), fpga_fd); - return EXIT_FAILURE; - } - posix_memalign((void**)&allocated, 4096 /*alignment */, size + 4096); - if (!allocated) { - fprintf(stderr, "OOM %lu.\n", size + 4096); - close(fpga_fd); - free(allocated); - return EXIT_FAILURE; - } - buffer = allocated + offset; - if (verbose) { - fprintf(stdout, "host buffer 0x%lx = %p\n", size + 4096, buffer); - } - for (i = 0; i < count; i++) { - clock_gettime(CLOCK_MONOTONIC, &ts_start); - ret = write(fpga_fd, buffer, size); - if (ret < 0) { - fprintf(stderr, "Could not write to device buffer.\n"); - close(fpga_fd); - free(allocated); - return EXIT_FAILURE; - } - clock_gettime(CLOCK_MONOTONIC, &ts_end); - timespec_sub(&ts_end, &ts_start); - total_time += (ts_end.tv_sec + ((double)ts_end.tv_nsec / 1000000000.0)); - if (verbose) { - fprintf(stdout, "CLOCK_MONOTONIC %ld.%09ld sec. write %lu bytes\n", ts_end.tv_sec, - ts_end.tv_nsec, size); - } - } - avg_time = (double)total_time / (double)count; - result = ((double)size) / avg_time; - close(fpga_fd); - free(allocated); - return result; -} - -void ValidateCommand::dma_write_thread_pcie(thread_data_t* data) { - double result = test_dma_write_pcie(data->devname, data->addr, data->size, data->offset, - data->count, data->verbose); - pci_bw_result.fetch_add(result / GB_DIV, std::memory_order_relaxed); -} - -void ValidateCommand::timespec_sub(struct timespec* t1, struct timespec* t2) { - if (timespec_check(t1) < 0) { - fprintf(stderr, "invalid time #1: %lld.%.9ld.\n", (long long)t1->tv_sec, t1->tv_nsec); - return; - } - if (timespec_check(t2) < 0) { - fprintf(stderr, "invalid time #2: %lld.%.9ld.\n", (long long)t2->tv_sec, t2->tv_nsec); - return; - } - t1->tv_sec -= t2->tv_sec; - t1->tv_nsec -= t2->tv_nsec; - if (t1->tv_nsec >= 1000000000) { - t1->tv_sec++; - t1->tv_nsec -= 1000000000; - } else if (t1->tv_nsec < 0) { - t1->tv_sec--; - t1->tv_nsec += 1000000000; - } -} - -int ValidateCommand::timespec_check(struct timespec* t) { - if ((t->tv_nsec < 0) || (t->tv_nsec >= 1000000000)) return -1; - return 0; -} \ No newline at end of file diff --git a/smi/src/debug/bar_poke.cpp b/smi/src/debug/bar_poke.cpp new file mode 100644 index 00000000..a52414fc --- /dev/null +++ b/smi/src/debug/bar_poke.cpp @@ -0,0 +1,236 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file debug/bar_poke.cpp +/// @brief Implementation of the debug BAR read/write command. + +#include "bar_poke.hpp" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../bdf.hpp" + +namespace { + +bool hasHexPrefix(const std::string_view text) { + return text.size() >= 2 && text[0] == '0' && (text[1] == 'x' || text[1] == 'X'); +} + +uint64_t parseUnsigned(const std::string_view text, + const char* fieldName) { + if (text.empty()) { + throw std::invalid_argument(std::string(fieldName) + " is required"); + } + + std::string_view digits = text; + int base = 10; + + if (hasHexPrefix(text)) { + digits = text.substr(2); + base = 16; + + if (digits.empty()) { + throw std::invalid_argument(std::string(fieldName) + " has no digits after 0x prefix"); + } + } + + uint64_t value{}; + const auto* begin = digits.data(); + const auto* end = begin + digits.size(); + std::from_chars_result result = std::from_chars(begin, end, value, base); + if (result.ec != std::errc() || result.ptr != end) { + throw std::invalid_argument(std::string("Invalid ") + fieldName + ": '" + std::string(text) + "'"); + } + + return value; +} + +void validateOptions(const BarPoke::Options& options) { + if (options.readMode == options.writeMode) { + throw std::invalid_argument("Exactly one of --read or --write must be specified"); + } + + if (options.wordSize != 1 && options.wordSize != 2 && + options.wordSize != 4 && options.wordSize != 8) { + throw std::invalid_argument("word-size must be one of: 1, 2, 4, 8"); + } + + if (options.count == 0) { + throw std::invalid_argument("count must be greater than zero"); + } + + if (options.writeMode && options.count != 1) { + throw std::invalid_argument("--count must be 1 for --write"); + } + + if (options.writeMode && !options.valueText.has_value()) { + throw std::invalid_argument("value is required for --write"); + } + + if (options.readMode && options.valueText.has_value()) { + throw std::invalid_argument("value is not allowed for --read"); + } +} + +void validateRangeAndAlignment(uint64_t address, + uint64_t count, + unsigned wordSize, + uint64_t barLength) { + if (address % wordSize != 0) { + throw std::invalid_argument("address must be aligned to word-size"); + } + + if (address > barLength) { + throw std::invalid_argument("address is outside BAR range"); + } + + if (count > (std::numeric_limits::max() / wordSize)) { + throw std::invalid_argument("requested count is too large"); + } + + const uint64_t totalBytes = count * wordSize; + if (totalBytes > barLength - address) { + throw std::invalid_argument("BAR access range is out of bounds"); + } +} + +template +void printValue(T value, bool hexMode) { + if (hexMode) { + const std::ios_base::fmtflags flags = std::cout.flags(); + const char fill = std::cout.fill(); + std::cout << "0x" + << std::hex << std::nouppercase + << std::setw(static_cast(sizeof(T) * 2)) + << std::setfill('0') + << static_cast(value) + << '\n'; + std::cout.flags(flags); + std::cout.fill(fill); + } else { + std::cout << static_cast(value) << '\n'; + } +} + +template +void runRead(vrtd::BarFile& barFile, + uint64_t address, + uint64_t count, + bool hexMode) { + auto ptr = barFile.getPtr(vrtd::BarFile::Direction::Read, + static_cast(address)); + for (uint64_t i = 0; i < count; ++i) { + printValue(ptr[i], hexMode); + } +} + +template +void runWrite(vrtd::BarFile& barFile, + uint64_t address, + uint64_t value) { + auto ptr = barFile.getPtr(vrtd::BarFile::Direction::Write, + static_cast(address)); + *ptr = static_cast(value); +} + +void executeByWordSize(const BarPoke::Options& options, + vrtd::BarFile& barFile, + uint64_t address, + uint64_t count, + uint64_t value) { + switch (options.wordSize) { + case 1: + if (value > std::numeric_limits::max()) { + throw std::invalid_argument("value does not fit in 1-byte word"); + } + if (options.readMode) { + runRead(barFile, address, count, options.hexMode); + } else { + runWrite(barFile, address, value); + } + break; + case 2: + if (value > std::numeric_limits::max()) { + throw std::invalid_argument("value does not fit in 2-byte word"); + } + if (options.readMode) { + runRead(barFile, address, count, options.hexMode); + } else { + runWrite(barFile, address, value); + } + break; + case 4: + if (value > std::numeric_limits::max()) { + throw std::invalid_argument("value does not fit in 4-byte word"); + } + if (options.readMode) { + runRead(barFile, address, count, options.hexMode); + } else { + runWrite(barFile, address, value); + } + break; + case 8: + if (options.readMode) { + runRead(barFile, address, count, options.hexMode); + } else { + runWrite(barFile, address, value); + } + break; + default: + throw std::runtime_error("Internal error: unsupported word-size"); + } +} + +} // namespace + +int BarPoke::run(const Options& options) { + validateOptions(options); + + const uint64_t address = parseUnsigned(options.addressText, "address"); + const uint64_t value = options.valueText.has_value() + ? parseUnsigned(*options.valueText, "value") + : 0; + + const std::string bdf = resolveBoardBdf(options.bdf, "debug bar-poke"); + + vrtd::Session session; + auto device = session.getDeviceByBdf(bdf); + auto bar = device.getBar(static_cast(options.bar)); + + if (!bar.isUsable()) { + throw std::runtime_error("Requested BAR is not usable"); + } + + vrtd::BarFile barFile = bar.openBarFile(); + const uint64_t barLength = static_cast(barFile.getLen()); + + validateRangeAndAlignment(address, options.count, options.wordSize, barLength); + executeByWordSize(options, barFile, address, options.count, value); + + return 0; +} diff --git a/smi/src/debug/bar_poke.hpp b/smi/src/debug/bar_poke.hpp new file mode 100644 index 00000000..19271617 --- /dev/null +++ b/smi/src/debug/bar_poke.hpp @@ -0,0 +1,57 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file debug/bar_poke.hpp +/// @brief Declaration of the BarPoke debug command. + +#ifndef SMI_DEBUG_BAR_POKE_HPP +#define SMI_DEBUG_BAR_POKE_HPP + +#include +#include +#include + +/// @brief Static entry-point for the debug bar-poke command. +/// +/// This class is not instantiable; it groups the command options and +/// its run() entry-point. +class BarPoke { + BarPoke() = delete; +public: + /// @brief Options parsed from the CLI for the bar-poke command. + struct Options { + std::string bdf; ///< Target board address. + unsigned bar{}; ///< BAR number (0-5). + bool readMode{}; ///< True for read operations. + bool writeMode{}; ///< True for write operations. + bool hexMode{}; ///< True for hex-formatted read output. + unsigned wordSize = 4; ///< Access width in bytes: 1, 2, 4, or 8. + uint64_t count = 1; ///< Number of words to read (must be 1 for write). + std::string addressText; ///< Raw address argument from CLI. + std::optional valueText; ///< Optional raw value argument from CLI. + }; + + /// @brief Executes the bar-poke command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +#endif // SMI_DEBUG_BAR_POKE_HPP diff --git a/smi/src/debug/clockwiz.cpp b/smi/src/debug/clockwiz.cpp new file mode 100644 index 00000000..93cf600d --- /dev/null +++ b/smi/src/debug/clockwiz.cpp @@ -0,0 +1,169 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file debug/clockwiz.cpp +/// @brief Implementation of the debug clock read/set command. + +#include "clockwiz.hpp" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../bdf.hpp" + +namespace { + +bool hasHexPrefix(const std::string_view text) { + return text.size() >= 2 && text[0] == '0' && (text[1] == 'x' || text[1] == 'X'); +} + +uint64_t parseUnsigned(const std::string_view text, + const char* fieldName) { + if (text.empty()) { + throw std::invalid_argument(std::string(fieldName) + " is required"); + } + + std::string_view digits = text; + int base = 10; + + if (hasHexPrefix(text)) { + digits = text.substr(2); + base = 16; + + if (digits.empty()) { + throw std::invalid_argument(std::string(fieldName) + " has no digits after 0x prefix"); + } + } + + uint64_t value{}; + const auto* begin = digits.data(); + const auto* end = begin + digits.size(); + std::from_chars_result result = std::from_chars(begin, end, value, base); + if (result.ec != std::errc() || result.ptr != end) { + throw std::invalid_argument(std::string("Invalid ") + fieldName + ": '" + std::string(text) + "'"); + } + + return value; +} + +std::string toLower(std::string_view text) { + std::string out(text); + std::transform(out.begin(), out.end(), out.begin(), [](unsigned char c) { + return static_cast(std::tolower(c)); + }); + return out; +} + +vrtd::ClockRegion parseClockRegion(const std::string_view text) { + const std::string normalized = toLower(text); + if (normalized == "user") { + return vrtd::ClockRegion::User; + } + if (normalized == "service") { + return vrtd::ClockRegion::Service; + } + + throw std::invalid_argument("region must be one of: user, service"); +} + +uint32_t parseSetRate(const Clockwiz::Options& options) { + if (!options.setRateText.has_value()) { + throw std::invalid_argument("--set requires a rate in Hz"); + } + + const uint64_t rate = parseUnsigned(*options.setRateText, "set rate"); + if (rate == 0) { + throw std::invalid_argument("set rate must be greater than zero"); + } + if (rate > std::numeric_limits::max()) { + throw std::invalid_argument("set rate does not fit in 32-bit Hz value"); + } + + return static_cast(rate); +} + +void validateOptions(const Clockwiz::Options& options) { + const bool hasSet = options.setRateText.has_value(); + if (options.getMode == hasSet) { + throw std::invalid_argument("Exactly one of --get or --set must be specified"); + } + + if (options.hexMode && hasSet) { + throw std::invalid_argument("--hex is only valid with --get"); + } + + (void)parseClockRegion(options.regionText); + if (hasSet) { + (void)parseSetRate(options); + } +} + +template +void printValue(T value, bool hexMode) { + if (hexMode) { + const std::ios_base::fmtflags flags = std::cout.flags(); + const char fill = std::cout.fill(); + std::cout << "0x" + << std::hex << std::nouppercase + << std::setw(static_cast(sizeof(T) * 2)) + << std::setfill('0') + << static_cast(value) + << '\n'; + std::cout.flags(flags); + std::cout.fill(fill); + } else { + std::cout << static_cast(value) << '\n'; + } +} + +} // namespace + +int Clockwiz::run(const Options& options) { + validateOptions(options); + + const std::string bdf = resolveBoardBdf(options.bdf, "debug clockwiz"); + const vrtd::ClockRegion region = parseClockRegion(options.regionText); + + vrtd::Session session; + auto device = session.getDeviceByBdf(bdf); + + if (options.getMode) { + const uint32_t currentRate = device.getClockRate(region); + printValue(currentRate, options.hexMode); + return 0; + } + + const uint32_t requestedRate = parseSetRate(options); + const uint32_t achievedRate = device.setClockRate(region, requestedRate); + + std::cout << "requested_hz=" << requestedRate << '\n'; + std::cout << "achieved_hz=" << achievedRate << '\n'; + + return 0; +} diff --git a/smi/src/debug/clockwiz.hpp b/smi/src/debug/clockwiz.hpp new file mode 100644 index 00000000..b7372970 --- /dev/null +++ b/smi/src/debug/clockwiz.hpp @@ -0,0 +1,52 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file debug/clockwiz.hpp +/// @brief Declaration of the Clockwiz debug command. + +#ifndef SMI_DEBUG_CLOCKWIZ_HPP +#define SMI_DEBUG_CLOCKWIZ_HPP + +#include +#include + +/// @brief Static entry-point for the debug clockwiz command. +/// +/// This class is not instantiable; it groups the command options and +/// its run() entry-point. +class Clockwiz { + Clockwiz() = delete; +public: + /// @brief Options parsed from the CLI for the clockwiz command. + struct Options { + std::string bdf; ///< Target board address. + bool getMode{}; ///< True to read a clock rate. + std::optional setRateText; ///< Optional set-rate argument (Hz). + std::string regionText = "user"; ///< Clock region selector: user or service. + bool hexMode{}; ///< True for hex-formatted --get output. + }; + + /// @brief Executes the clockwiz command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +#endif // SMI_DEBUG_CLOCKWIZ_HPP diff --git a/smi/src/debug/mem_poke.cpp b/smi/src/debug/mem_poke.cpp new file mode 100644 index 00000000..fa860db4 --- /dev/null +++ b/smi/src/debug/mem_poke.cpp @@ -0,0 +1,489 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file debug/mem_poke.cpp +/// @brief Implementation of the debug device-memory read/write command. + +#include "mem_poke.hpp" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../bdf.hpp" + +namespace { + +// ---- Region constants (mirror vrt/vrtd/src/allocator.h, which is private) -- + +constexpr uint64_t HBM_BASE = 0x4000000000ULL; +constexpr uint64_t DDR_BASE = 0x60000000000ULL; +constexpr uint64_t MEM_REGION_SIZE = 512ULL * 1024 * 1024; +constexpr uint32_t HBM_REGION_COUNT = 64; +constexpr uint32_t DDR_REGION_COUNT = 64; + +// ---- Region helpers --------------------------------------------------------- + +std::string toUpper(std::string_view text) { + std::string out(text); + std::transform(out.begin(), out.end(), out.begin(), + [](unsigned char c) { return static_cast(std::toupper(c)); }); + return out; +} + +MemRegion parseRegion(std::string_view text) { + const std::string upper = toUpper(text); + + if (upper == "RAW") { + return MemRegion{MemRegionKind::Raw, 0, false}; + } + if (upper == "DDR") { + return MemRegion{MemRegionKind::Ddr, 0, false}; + } + if (upper == "HBM") { + return MemRegion{MemRegionKind::Hbm, 0, true}; + } + if (upper.size() > 3 && upper.substr(0, 3) == "HBM") { + const std::string_view indexStr = std::string_view(upper).substr(3); + uint32_t index{}; + const auto* begin = indexStr.data(); + const auto* end = begin + indexStr.size(); + const auto result = std::from_chars(begin, end, index); + if (result.ec == std::errc() && result.ptr == end && index < HBM_REGION_COUNT) { + return MemRegion{MemRegionKind::Hbm, index, false}; + } + } + + throw std::invalid_argument( + std::string("Invalid region '") + std::string(text) + + "': must be DDR, HBM, HBM0..HBM63, or RAW"); +} + +uint64_t regionBase(const MemRegion& region) { + switch (region.kind) { + case MemRegionKind::Raw: return 0; + case MemRegionKind::Ddr: return DDR_BASE; + case MemRegionKind::Hbm: return HBM_BASE + region.hbmIndex * MEM_REGION_SIZE; + } + return 0; // unreachable +} + +uint64_t regionSize(const MemRegion& region) { + switch (region.kind) { + case MemRegionKind::Raw: return std::numeric_limits::max(); + case MemRegionKind::Ddr: return DDR_REGION_COUNT * MEM_REGION_SIZE; + case MemRegionKind::Hbm: + return region.hbmWholeSpace ? HBM_REGION_COUNT * MEM_REGION_SIZE : MEM_REGION_SIZE; + } + return 0; // unreachable +} + +// ---- General helpers -------------------------------------------------------- + +bool hasHexPrefix(const std::string_view text) { + return text.size() >= 2 && text[0] == '0' && (text[1] == 'x' || text[1] == 'X'); +} + +uint64_t parseUnsigned(const std::string_view text, + const char* fieldName) { + if (text.empty()) { + throw std::invalid_argument(std::string(fieldName) + " is required"); + } + + std::string_view digits = text; + int base = 10; + + if (hasHexPrefix(text)) { + digits = text.substr(2); + base = 16; + + if (digits.empty()) { + throw std::invalid_argument(std::string(fieldName) + " has no digits after 0x prefix"); + } + } + + uint64_t value{}; + const auto* begin = digits.data(); + const auto* end = begin + digits.size(); + std::from_chars_result result = std::from_chars(begin, end, value, base); + if (result.ec != std::errc() || result.ptr != end) { + throw std::invalid_argument(std::string("Invalid ") + fieldName + ": '" + std::string(text) + "'"); + } + + return value; +} + +void validateOptions(const MemPoke::Options& options) { + // --print-base-address / --print-size are mutually exclusive with I/O flags + if (options.printBaseAddress || options.printSize) { + if (options.readMode || options.writeMode) { + throw std::invalid_argument( + "--print-base-address/--print-size cannot be combined with --read or --write"); + } + if (options.relativeAddress) { + throw std::invalid_argument( + "--print-base-address/--print-size cannot be combined with --relative"); + } + if (!options.addressText.empty()) { + throw std::invalid_argument( + "--print-base-address/--print-size cannot be combined with an address argument"); + } + if (options.valueText.has_value()) { + throw std::invalid_argument( + "--print-base-address/--print-size cannot be combined with a value argument"); + } + if (options.filePath.has_value()) { + throw std::invalid_argument( + "--print-base-address/--print-size cannot be combined with --file"); + } + return; + } + + if (options.readMode == options.writeMode) { + throw std::invalid_argument("Exactly one of --read or --write must be specified"); + } + + if (options.wordSize != 1 && options.wordSize != 2 && + options.wordSize != 4 && options.wordSize != 8) { + throw std::invalid_argument("word-size must be one of: 1, 2, 4, 8"); + } + + if (options.count == 0) { + throw std::invalid_argument("count must be greater than zero"); + } + + if (options.filePath.has_value()) { + if (options.valueText.has_value()) { + throw std::invalid_argument("value argument is not allowed with --file"); + } + } else { + // Scalar (non-file) mode rules + if (options.writeMode && options.count != 1) { + throw std::invalid_argument("--count must be 1 for --write (use --file for multi-word writes)"); + } + + if (options.writeMode && !options.valueText.has_value()) { + throw std::invalid_argument("value is required for --write (or use --file)"); + } + + if (options.readMode && options.valueText.has_value()) { + throw std::invalid_argument("value is not allowed for --read"); + } + } +} + +void validateRangeAndAlignment(uint64_t address, uint64_t count, unsigned wordSize) { + if (address % wordSize != 0) { + throw std::invalid_argument("address must be aligned to word-size"); + } + + if (count > (std::numeric_limits::max() / wordSize)) { + throw std::invalid_argument("requested count is too large"); + } +} + +// ---- Scalar word-oriented mode ------------------------------------------ + +template +void printValue(T value, bool hexMode) { + if (hexMode) { + const std::ios_base::fmtflags flags = std::cout.flags(); + const char fill = std::cout.fill(); + std::cout << "0x" + << std::hex << std::nouppercase + << std::setw(static_cast(sizeof(T) * 2)) + << std::setfill('0') + << static_cast(value) + << '\n'; + std::cout.flags(flags); + std::cout.fill(fill); + } else { + std::cout << static_cast(value) << '\n'; + } +} + +template +void runRead(vrtd::Buffer& buf, uint64_t count, bool hexMode) { + buf.syncFromDevice(0, count * sizeof(T)); + const T* ptr = static_cast(buf.data()); + for (uint64_t i = 0; i < count; ++i) { + printValue(ptr[i], hexMode); + } +} + +template +void runWrite(vrtd::Buffer& buf, uint64_t value) { + T typed = static_cast(value); + std::memcpy(buf.data(), &typed, sizeof(T)); + buf.syncToDevice(0, sizeof(T)); +} + +void executeByWordSize(const MemPoke::Options& options, + vrtd::Buffer& buf, + uint64_t count, + uint64_t value) { + switch (options.wordSize) { + case 1: + if (value > std::numeric_limits::max()) { + throw std::invalid_argument("value does not fit in 1-byte word"); + } + if (options.readMode) { + runRead(buf, count, options.hexMode); + } else { + runWrite(buf, value); + } + break; + case 2: + if (value > std::numeric_limits::max()) { + throw std::invalid_argument("value does not fit in 2-byte word"); + } + if (options.readMode) { + runRead(buf, count, options.hexMode); + } else { + runWrite(buf, value); + } + break; + case 4: + if (value > std::numeric_limits::max()) { + throw std::invalid_argument("value does not fit in 4-byte word"); + } + if (options.readMode) { + runRead(buf, count, options.hexMode); + } else { + runWrite(buf, value); + } + break; + case 8: + if (options.readMode) { + runRead(buf, count, options.hexMode); + } else { + runWrite(buf, value); + } + break; + default: + throw std::runtime_error("Internal error: unsupported word-size"); + } +} + +// ---- File mode ----------------------------------------------------------- + +/// Write a hexdump of @p data to @p out. +/// +/// Format: "XXXXXXXX: HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH HH\n" +/// 16 bytes per line, address prefix, no 0x prefix on bytes, groups of 8. +void writeHexdump(std::ostream& out, const uint8_t* data, uint64_t size, uint64_t baseAddr) { + const std::ios_base::fmtflags flags = out.flags(); + const char fill = out.fill(); + + out << std::hex << std::nouppercase << std::setfill('0'); + + for (uint64_t offset = 0; offset < size; offset += 16) { + out << std::setw(8) << (baseAddr + offset) << ':'; + + const uint64_t lineBytes = std::min(16, size - offset); + for (uint64_t i = 0; i < lineBytes; ++i) { + if (i == 8) { + out << ' '; // extra space between the two groups of 8 + } + out << ' ' << std::setw(2) << static_cast(data[offset + i]); + } + out << '\n'; + } + + out.flags(flags); + out.fill(fill); +} + +/// Parse a hexdump or plain hex stream into bytes. +/// +/// Accepts any mix of whitespace, colons, and newlines between hex digit pairs. +/// Stops at EOF. Throws if an odd digit is left over or a non-hex character +/// is encountered (other than whitespace/colons). +std::vector parseHexStream(std::istream& in) { + std::vector result; + + int hi = -1; // pending high nibble (-1 = none) + int ch; + while ((ch = in.get()) != std::char_traits::eof()) { + if (std::isxdigit(ch)) { + int nibble = (ch >= '0' && ch <= '9') ? ch - '0' + : (ch >= 'a' && ch <= 'f') ? ch - 'a' + 10 + : ch - 'A' + 10; + if (hi < 0) { + hi = nibble; + } else { + result.push_back(static_cast((hi << 4) | nibble)); + hi = -1; + } + } else if (std::isspace(ch) || ch == ':') { + // Separators are fine; a lone nibble before a separator is an error. + if (hi >= 0) { + throw std::invalid_argument("Odd hex digit in input (unpaired nibble)"); + } + } else { + throw std::invalid_argument( + std::string("Unexpected character in hex input: '") + static_cast(ch) + "'"); + } + } + + if (hi >= 0) { + throw std::invalid_argument("Odd hex digit at end of input (unpaired nibble)"); + } + + return result; +} + +void runFileRead(vrtd::Buffer& buf, uint64_t totalBytes, uint64_t address, + const std::string& filePath, bool hexMode) { + buf.syncFromDevice(0, totalBytes); + const uint8_t* data = static_cast(buf.data()); + + std::ofstream out(filePath, std::ios::binary | std::ios::trunc); + if (!out) { + throw std::runtime_error("Cannot open output file: " + filePath); + } + + if (hexMode) { + writeHexdump(out, data, totalBytes, address); + } else { + out.write(reinterpret_cast(data), static_cast(totalBytes)); + if (!out) { + throw std::runtime_error("Failed to write binary data to file: " + filePath); + } + } +} + +void runFileWrite(vrtd::Buffer& buf, uint64_t totalBytes, + const std::string& filePath, bool hexMode) { + std::ifstream in(filePath, std::ios::binary); + if (!in) { + throw std::runtime_error("Cannot open input file: " + filePath); + } + + std::vector fileData; + + if (hexMode) { + fileData = parseHexStream(in); + } else { + fileData.assign(std::istreambuf_iterator(in), + std::istreambuf_iterator()); + } + + if (fileData.size() != totalBytes) { + throw std::invalid_argument( + "File size (" + std::to_string(fileData.size()) + + " bytes) does not match requested transfer size (" + + std::to_string(totalBytes) + " bytes)"); + } + + std::memcpy(buf.data(), fileData.data(), totalBytes); + buf.syncToDevice(0, totalBytes); +} + +} // namespace + +int MemPoke::run(const Options& options) { + validateOptions(options); + + const MemRegion region = parseRegion(options.regionText); + + // --print-base-address / --print-size: no device access needed. + if (options.printBaseAddress || options.printSize) { + const std::ios_base::fmtflags flags = std::cout.flags(); + std::cout << std::hex << std::nouppercase; + if (options.printBaseAddress) { + std::cout << "0x" << regionBase(region) << '\n'; + } + if (options.printSize) { + std::cout << "0x" << regionSize(region) << '\n'; + } + std::cout.flags(flags); + return 0; + } + + const uint64_t rawAddress = parseUnsigned(options.addressText, "address"); + + // Resolve relative addresses before bounds checking. + uint64_t address = rawAddress; + if (options.relativeAddress) { + if (region.kind == MemRegionKind::Raw) { + throw std::invalid_argument("--relative has no effect with --region RAW"); + } + address = regionBase(region) + rawAddress; + } + + if (options.count > std::numeric_limits::max() / options.wordSize) { + throw std::invalid_argument("requested count is too large"); + } + const uint64_t totalBytes = options.count * static_cast(options.wordSize); + + if (!options.filePath.has_value()) { + validateRangeAndAlignment(address, options.count, options.wordSize); + } + + // Region bounds check (skipped for RAW). + if (region.kind != MemRegionKind::Raw) { + const uint64_t base = regionBase(region); + const uint64_t size = regionSize(region); + // Check: address must be within [base, base+size) and address+totalBytes <= base+size. + // Written to avoid unsigned underflow: totalBytes <= size && address - base <= size - totalBytes. + if (address < base || totalBytes > size || (address - base) > size - totalBytes) { + throw std::invalid_argument( + "address+size is out of bounds for region " + options.regionText); + } + } + + const std::string bdf = resolveBoardBdf(options.bdf, "debug mem-poke"); + + vrtd::Session session; + auto device = session.getDeviceByBdf(bdf); + + auto buf = device.openRawBuffer( + address, + totalBytes, + options.readMode ? vrtd::BufferAllocDir::DeviceToHost + : vrtd::BufferAllocDir::HostToDevice + ); + + if (options.filePath.has_value()) { + if (options.readMode) { + runFileRead(buf, totalBytes, address, *options.filePath, options.hexMode); + } else { + runFileWrite(buf, totalBytes, *options.filePath, options.hexMode); + } + } else { + const uint64_t value = options.valueText.has_value() + ? parseUnsigned(*options.valueText, "value") + : 0; + executeByWordSize(options, buf, options.count, value); + } + + return 0; +} diff --git a/smi/src/debug/mem_poke.hpp b/smi/src/debug/mem_poke.hpp new file mode 100644 index 00000000..bc8813bf --- /dev/null +++ b/smi/src/debug/mem_poke.hpp @@ -0,0 +1,78 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file debug/mem_poke.hpp +/// @brief Declaration of the MemPoke debug command. + +#ifndef SMI_DEBUG_MEM_POKE_HPP +#define SMI_DEBUG_MEM_POKE_HPP + +#include +#include +#include + +/// @brief Identifies which broad memory space a mem-poke region belongs to. +enum class MemRegionKind { Raw, Ddr, Hbm }; + +/// @brief A parsed memory region specifier. +/// +/// For HBM, @p hbmIndex selects a specific 512 MiB channel (0–63). +/// When the user passes bare "HBM" (no index), @p hbmWholeSpace is true +/// and bounds checking covers the entire HBM address space. +struct MemRegion { + MemRegionKind kind = MemRegionKind::Raw; + uint32_t hbmIndex = 0; + bool hbmWholeSpace = false; ///< True when region is "HBM" (all channels). +}; + +/// @brief Static entry-point for the debug mem-poke command. +/// +/// Reads or writes device memory at a raw physical address, bypassing the +/// allocator entirely. Requires the raw-mem-access permission in vrtd. +/// +/// This class is not instantiable; it groups the command options and +/// its run() entry-point. +class MemPoke { + MemPoke() = delete; +public: + /// @brief Options parsed from the CLI for the mem-poke command. + struct Options { + std::string bdf; ///< Target board address. + bool readMode{}; ///< True for read operations. + bool writeMode{}; ///< True for write operations. + bool hexMode{}; ///< True for hex-formatted read output. + unsigned wordSize = 4; ///< Access width in bytes: 1, 2, 4, or 8. + uint64_t count = 1; ///< Number of words to read (must be 1 for write). + std::string addressText; ///< Raw device physical address argument from CLI. + std::optional valueText; ///< Optional raw value argument from CLI (scalar write). + std::optional filePath; ///< Optional file path for file-mode read/write. + std::string regionText; ///< Memory region: DDR, HBM, HBM0..HBM63, or RAW. + bool relativeAddress{}; ///< Interpret address as relative to region base. + bool printBaseAddress{}; ///< Print region base address (hex) and exit. + bool printSize{}; ///< Print region size in bytes (hex) and exit. + }; + + /// @brief Executes the mem-poke command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +#endif // SMI_DEBUG_MEM_POKE_HPP diff --git a/smi/src/inspect.cpp b/smi/src/inspect.cpp new file mode 100644 index 00000000..131a0107 --- /dev/null +++ b/smi/src/inspect.cpp @@ -0,0 +1,444 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file inspect.cpp +/// @brief Implementation of the Inspect (and Query) command. +/// +/// Reads vbin metadata - either from a vbin file on disk or from the +/// system-map of whatever was last loaded on a device - and prints +/// kernel information (name, physical address, arguments) in text or JSON. + +#include "inspect.hpp" + +#include +#include +#include +#include +#include + +#include +#include + +#include "bdf.hpp" + +#include "utils.hpp" + +//. BDF string corresponding to the all-ones sentinel value (0xFFFF). +/// +/// Passed to vrt::Vrtbin when we're inspecting a file and have no real device. +/// This will only determine the name of the path where the vbin is extracted. +/// This BDF should never occur in reality. +constexpr char BDF_SENTINEL[] = "FF:1F.7"; + + +// --------------------------------------------------------------------------- +// Direction helpers +// --------------------------------------------------------------------------- + +/// Converts readable/writable flags into a human-readable direction string. +/// @return "Read", "Write", "ReadWrite", or "" if neither flag is set. +std::string directionToString(bool readable, bool writable) { + std::stringstream ss; + + ss << (readable ? "Read" : "") << (writable ? "Write" : ""); + + return ss.str(); +} + +/// Convenience overload that extracts the flags from a FunctionalArg. +std::string directionToString(const vrt::FunctionalArg& arg) { + return directionToString(arg.readable, arg.writable); +} + +// --------------------------------------------------------------------------- +// FunctionalArg formatting (text & JSON) +// --------------------------------------------------------------------------- + +/// Human-readable output for a single kernel argument. +std::ostream& operator<<(std::ostream& out, const vrt::FunctionalArg& arg) { + return out + << INDENT2 << "Argument:\n" + << INDENT3 << "Index: " << arg.idx << "\n" + << INDENT3 << "Name: " << arg.name << "\n" + << INDENT3 << "Type: " << arg.type << "\n" + << INDENT3 << "Offset: " << arg.offset << "\n" + << INDENT3 << "Range: " << arg.range << "\n" + << INDENT3 << "Direction: " << directionToString(arg) << "\n"; +} + +/// JSON representation of a single kernel argument. +Json::Value toJson(const vrt::FunctionalArg& arg) { + Json::Value j; + + j["index"] = toHexString(arg.idx); + j["name"] = arg.name; + j["type"] = arg.type; + j["offset"] = toHexString(arg.offset); // Prevent JSON number issues + j["range"] = toHexString(arg.range); // Prevent JSON number issues + j["direction"] = directionToString(arg); + + return j; +} + +// --------------------------------------------------------------------------- +// KernelData — lightweight snapshot of a vrt::Kernel +// --------------------------------------------------------------------------- + +/// @brief Holds the subset of vrt::Kernel data needed for display. +struct KernelData { + std::string name; ///< Kernel name from the system map. + uint64_t physAddress{}; ///< Physical (mapped) address of the kernel. + std::vector args; ///< HLS functional arguments. + + /// Extracts display-relevant data from a live vrt::Kernel object. + static KernelData fromKernel(const vrt::Kernel& kernel) { + return KernelData { + .name{kernel.getName()}, + .physAddress{kernel.getPhysAddr()}, + .args{kernel.getFunctionalArgs()}, + }; + } +}; + +/// Human-readable output for a kernel and its arguments. +std::ostream& operator<<(std::ostream& out, const KernelData& kernel) { + out + << INDENT1 << "Kernel:\n" + << INDENT2 << "Name: " << kernel.name << "\n" + << INDENT2 << "Physical address: " << toHexString(kernel.physAddress) << "\n"; + + for (const auto& arg : kernel.args) { + out << arg; + } + + return out; +} + +/// JSON representation of a kernel and its arguments. +Json::Value toJson(const KernelData& kernel) { + Json::Value j; + + j["name"] = kernel.name; + j["address"] = toHexString(kernel.physAddress); + + if (!kernel.args.empty()) { + j["args"] = Json::Value(Json::arrayValue); + + for (const auto& arg : kernel.args) { + j["args"].append(toJson(arg)); + } + } + + return j; +} + +// --------------------------------------------------------------------------- +// Utilization formatting (text & JSON) +// --------------------------------------------------------------------------- + +/// Helper to append " (X.XX%)" to a stream if a percentage is present. +void streamPct(std::ostream& out, const std::optional& pct) { + if (pct) { + out << " (" << *pct << "%)"; + } +} + +/// Human-readable output for resource metrics. +std::ostream& operator<<(std::ostream& out, const vrt::ResourceMetrics& m) { + out << "LUTs: " << m.totalLuts; + streamPct(out, m.totalLutsPct); + out << ", FFs: " << m.ff; + streamPct(out, m.ffPct); + out << ", LUTRAM: " << m.lutram; + streamPct(out, m.lutramPct); + out << ", SRL: " << m.srl; + streamPct(out, m.srlPct); + out << ", RAMB36: " << m.ramb36; + streamPct(out, m.ramb36Pct); + out << ", RAMB18: " << m.ramb18; + streamPct(out, m.ramb18Pct); + out << ", URAM: " << m.uram; + streamPct(out, m.uramPct); + out << ", DSP: " << m.dsp; + streamPct(out, m.dspPct); + return out; +} + +/// JSON representation of resource metrics. +Json::Value toJson(const vrt::ResourceMetrics& m) { + Json::Value j; + j["total_luts"] = m.totalLuts; + if (m.totalLutsPct) j["total_luts_pct"] = *m.totalLutsPct; + j["lutram"] = m.lutram; + if (m.lutramPct) j["lutram_pct"] = *m.lutramPct; + j["srl"] = m.srl; + if (m.srlPct) j["srl_pct"] = *m.srlPct; + j["ff"] = m.ff; + if (m.ffPct) j["ff_pct"] = *m.ffPct; + j["ramb36"] = m.ramb36; + if (m.ramb36Pct) j["ramb36_pct"] = *m.ramb36Pct; + j["ramb18"] = m.ramb18; + if (m.ramb18Pct) j["ramb18_pct"] = *m.ramb18Pct; + j["ramb"] = m.ramb; + j["uram"] = m.uram; + if (m.uramPct) j["uram_pct"] = *m.uramPct; + j["dsp"] = m.dsp; + if (m.dspPct) j["dsp_pct"] = *m.dspPct; + return j; +} + +/// JSON representation of a utilization cell. +Json::Value toJson(const vrt::UtilizationCell& cell) { + Json::Value j; + j["instance"] = cell.instance; + j["module"] = cell.module; + j["metrics"] = toJson(cell.metrics); + return j; +} + +/// JSON representation of a utilization block. +Json::Value toJson(const vrt::UtilizationBlock& block) { + Json::Value j; + j["totals"] = toJson(block.totals); + if (block.subhierarchy) { + const auto& sub = *block.subhierarchy; + if (!sub.cells.empty()) { + j["cells"] = Json::Value(Json::arrayValue); + for (const auto& cell : sub.cells) { + j["cells"].append(toJson(cell)); + } + } + if (!sub.slashLogic.empty()) { + j["slash_logic"] = Json::Value(Json::arrayValue); + for (const auto& cell : sub.slashLogic) { + j["slash_logic"].append(toJson(cell)); + } + } + j["subhierarchy_sum"] = toJson(sub.subhierarchySum); + j["slash_logic_sum"] = toJson(sub.slashLogicSum); + } + return j; +} + +/// JSON representation of the full utilization report. +Json::Value toJson(const vrt::UtilizationReport& report) { + Json::Value j; + j["slash"] = toJson(report.slash); + if (report.serviceLayer) { + j["service_layer"] = toJson(*report.serviceLayer); + } + return j; +} + +/// Human-readable output for a utilization block. +void printBlock(std::ostream& out, const vrt::UtilizationBlock& block, const char* indent) { + out << indent << block.name << ": " << block.totals << "\n"; + if (block.subhierarchy) { + const auto& sub = *block.subhierarchy; + if (!sub.cells.empty()) { + out << indent << INDENT1 << "Cells:\n"; + for (const auto& cell : sub.cells) { + out << indent << INDENT2 << cell.instance + << " (" << cell.module << "): " << cell.metrics << "\n"; + } + } + if (!sub.slashLogic.empty()) { + out << indent << INDENT1 << "Slash logic:\n"; + for (const auto& cell : sub.slashLogic) { + out << indent << INDENT2 << cell.instance + << " (" << cell.module << "): " << cell.metrics << "\n"; + } + } + } +} + +/// Human-readable output for the full utilization report. +std::ostream& operator<<(std::ostream& out, const vrt::UtilizationReport& report) { + printBlock(out, report.slash, INDENT2); + if (report.serviceLayer) { + printBlock(out, *report.serviceLayer, INDENT2); + } + return out; +} + +// --------------------------------------------------------------------------- +// VbinData — lightweight snapshot of a whole vbin / system-map +// --------------------------------------------------------------------------- + +/// @brief Holds the metadata extracted from a vbin or a device's system map. +struct VbinData { + std::string name{}; ///< Display label (file path or "on "). + vrt::Platform platform{vrt::Platform::UNKNOWN}; ///< Target platform (HW / emulation / sim). + uint64_t clockFrequency{}; ///< Design clock frequency in Hz. + std::map kernels; ///< Kernels keyed by name. + std::optional utilization; ///< Utilization report (if present). + + /// Builds a VbinData from an already-parsed system-map XMLParser. + static VbinData fromParser(vrt::XMLParser& parser, const std::string& name) { + std::map kernels; + + for (const auto& [kernelName, kernel] : parser.getKernels()) { + kernels.emplace(kernelName, KernelData::fromKernel(kernel)); + } + + return VbinData { + .name{name}, + .platform{parser.getPlatform()}, + .clockFrequency{parser.getClockFrequency()}, + .kernels{std::move(kernels)}, + }; + } + + /// Builds a VbinData from a vrt::Vrtbin that has already been opened. + static VbinData fromVbin(vrt::Vrtbin& vbin, const std::string& name) { + vrt::XMLParser parser{vbin.getSystemMapPath()}; + parser.parseXML(); + + auto data = fromParser(parser, name); + + const auto utilPath = vbin.getUtilizationReportPath(); + if (!utilPath.empty() && std::filesystem::exists(utilPath)) { + vrt::UtilizationParser utilParser{utilPath}; + utilParser.parse(); + data.utilization = utilParser.getReport(); + } + + return data; + } + + /// Builds a VbinData by querying the system map currently loaded on + /// the device at the given BDF address. + static VbinData fromBdf(const std::string& bdf) { + const std::string mapPath = vrt::Vrtbin::getSystemMapPathFromBdf(bdf); + + if (!std::filesystem::exists(mapPath)) { + throw std::runtime_error( + "No vbin has been programmed on device " + bdf + + " (system map not found: " + mapPath + ")"); + } + + if ((std::filesystem::status(mapPath).permissions() & std::filesystem::perms::owner_read) == + std::filesystem::perms::none) { + throw std::runtime_error( + "Cannot read system map for device " + bdf + + " (permission denied: " + mapPath + ")"); + } + + vrt::XMLParser parser{mapPath}; + parser.parseXML(); + + auto data = fromParser(parser, "on " + bdf); + + const std::string utilPath = vrt::Vrtbin::getUtilizationReportPathFromBdf(bdf); + if (std::filesystem::exists(utilPath)) { + vrt::UtilizationParser utilParser{utilPath}; + utilParser.parse(); + data.utilization = utilParser.getReport(); + } + + return data; + } + + /// Builds a VbinData by extracting and parsing a vbin file on disk. + static VbinData fromPath(const std::string& path) { + // BDF_SENTINEL is used because Vrtbin requires a BDF string even + // when we only need to inspect the file contents, not target a device. + vrt::Vrtbin vbin{path, BDF_SENTINEL}; + vbin.extract(); + + return fromVbin(vbin, path); + } +}; + +/// Converts a vrt::Platform enum to its string name. +const char* toString(vrt::Platform platform) { + switch (platform) { + case vrt::Platform::HARDWARE: + return "HARDWARE"; + case vrt::Platform::EMULATION: + return "EMULATION"; + case vrt::Platform::SIMULATION: + return "SIMULATION"; + default: + return "UNKNOWN"; + } +} + +/// Human-readable output for an entire vbin's metadata. +std::ostream& operator<<(std::ostream& out, const VbinData& vbin) { + out + << "Vbin " << vbin.name << ":\n" + << INDENT1 << "Platform: " << toString(vbin.platform) << "\n" + << INDENT1 << "Clock frequency: " << vbin.clockFrequency << "\n"; + + if (vbin.utilization) { + out << INDENT1 << "Utilization:\n" << *vbin.utilization; + } + + for (const auto& [_, kernel] : vbin.kernels) { + out << kernel; + } + + return out; +} + +/// JSON representation of an entire vbin's metadata. +Json::Value toJson(const VbinData& vbin) { + Json::Value j; + + j["clock_frequency"] = toHexString(vbin.clockFrequency); + + if (vbin.utilization) { + j["utilization"] = toJson(*vbin.utilization); + } + + if (!vbin.kernels.empty()) { + j["kernels"] = Json::Value{}; + + for (const auto& [name, kernel] : vbin.kernels) { + j["kernels"][name] = toJson(kernel); + } + } + + return j; +} + +// --------------------------------------------------------------------------- +// Command entry-point +// --------------------------------------------------------------------------- + +/// Loads and reads the data source (BDF query or file path) based on the options. +VbinData getVbinData(const Inspect::Options& options) { + if (options.isBdfQuery) { + std::string bdf = resolveBoardBdf(options.bdf, "query"); + return VbinData::fromBdf(bdf); + } else { + return VbinData::fromPath(options.vbinPath); + } +} + +/// Runs the inspect/query command: loads vbin metadata and prints it. +int Inspect::run(const Options& options) { + const auto vbinData{getVbinData(options)}; + + print(vbinData, options.jsonOutput, options.prettyJsonOutput); + + return 0; +} diff --git a/smi/src/inspect.hpp b/smi/src/inspect.hpp new file mode 100644 index 00000000..07eff77c --- /dev/null +++ b/smi/src/inspect.hpp @@ -0,0 +1,60 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file inspect.hpp +/// @brief Declaration of the Inspect (and Query) command. +/// +/// The Inspect command displays the contents of a vbin file: its target +/// platform, clock frequency, and the kernels it contains along with their +/// arguments. When used as Query (the type alias below), it retrieves the +/// same information from whatever was last loaded on a device, identified +/// by its BDF (Bus:Device.Function) address. + +#ifndef SMI_INSPECT_HPP +#define SMI_INSPECT_HPP + +#include + +/// @brief Static entry-point for the inspect / query command. +/// +/// This class is not instantiable; it simply groups the command's option +/// struct and its `run()` entry-point. +class Inspect { + Inspect() = delete; +public: + /// @brief Options parsed from the CLI for inspect / query. + struct Options { + std::string vbinPath; ///< Path to the vbin file to inspect. + std::string bdf; ///< BDF address of the device to query. + bool isBdfQuery{}; ///< True when querying a device rather than a file. + bool jsonOutput{}; ///< Emit compact JSON instead of human-readable text. + bool prettyJsonOutput{}; ///< Emit indented JSON instead of human-readable text. + }; + + /// @brief Executes the inspect/query command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +/// Query is simply Inspect with Options::isBdfQuery set to true. +using Query = Inspect; + +#endif // SMI_INSPECT_HPP diff --git a/smi/src/list.cpp b/smi/src/list.cpp new file mode 100644 index 00000000..153d1a64 --- /dev/null +++ b/smi/src/list.cpp @@ -0,0 +1,730 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file list.cpp +/// @brief Implementation of the List command. +/// +/// Discovers V80 devices by scanning /sys/bus/pci/devices for entries +/// whose vendor and device IDs match the Slash platform, then prints +/// them in short, long, or JSON format. + +#include "list.hpp" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "utils.hpp" + +/// Root sysfs directory that contains one symlink per PCI device. +static const std::filesystem::path PCI_DEVICES_PATH{"/sys/bus/pci/devices"}; + +/// PCI vendor ID assigned to Slash/V80 devices (Xilinx). +constexpr unsigned int SLASH_VENDOR_ID{0x10EE}; + +/// PCI device ID for the V80 accelerator. +constexpr unsigned int SLASH_DEVICE_ID{0x50B4}; + +/// Physical Function number used by Slash on the V80. +/// Only PF0 is relevant; other functions belong to other subsystems. +constexpr unsigned int SLASH_PF_NUMBER{0}; + +/// PCI device ID for the V80 QDMA function (PF1). +constexpr unsigned int SLASH_PF1_DEVICE_ID{0x50B5}; + +/// PCI device ID for the V80 control function (PF2). +constexpr unsigned int SLASH_PF2_DEVICE_ID{0x50B6}; + +/// Expected driver for PF0 (AMI management function). +constexpr char PF0_EXPECTED_DRIVER[] = "ami"; + +/// Expected driver for PF1 (QDMA function). +constexpr char PF1_EXPECTED_DRIVER[] = "slash_qdma"; + +/// Expected driver for PF2 (control function). +constexpr char PF2_EXPECTED_DRIVER[] = "slash_ctl"; + + +// --------------------------------------------------------------------------- +// sysfs helpers +// --------------------------------------------------------------------------- + +/// Reads a single numeric value from a sysfs file. +/// +/// Most sysfs attribute files contain one value optionally prefixed with +/// "0x" and followed by a newline. Returns sentinel() if the file +/// cannot be opened or parsed. +/// +/// @tparam Int Integral type to read into. +/// @tparam Hex If true (default), parse as hexadecimal; otherwise decimal. +/// @param path Absolute path to the sysfs attribute file. +template +static Int readNumFile(const std::filesystem::path& path) { + std::ifstream f{path}; + Int val{sentinel()}; + if (f.is_open()) { + if constexpr (Hex) { + f >> std::hex >> val; + } else { + f >> val; + } + } + return val; +} + +/// Reads a sysfs file as a single trimmed line. +/// +/// Trailing whitespace and carriage returns are stripped. Returns an +/// empty string if the file cannot be opened. +/// +/// @param path Absolute path to the sysfs attribute file. +static std::string readStringFile(const std::filesystem::path& path) { + std::ifstream f(path); + std::string val; + if (f.is_open()) { + std::getline(f, val); + while (!val.empty() && (val.back() == '\n' || val.back() == '\r' || val.back() == ' ')) { + val.pop_back(); + } + } + return val; +} + +// --------------------------------------------------------------------------- +// PfStatus — per-physical-function readiness check +// --------------------------------------------------------------------------- + +/// @brief Result of checking one physical function's readiness. +struct PfStatus { + int pfNumber{}; ///< Physical function number (0, 1, or 2). + std::string bdf; ///< Full BDF address of this PF. + bool ok{}; ///< True if the PF passes all checks. + std::string reason; ///< Empty when ok; describes the failure otherwise. +}; + +/// Checks whether a given PCI physical function exists, has the expected +/// device ID, and has the expected driver bound. +/// +/// @param bdf Full BDF string, e.g. "0000:03:00.1". +/// @param pfNumber PF index (0, 1, or 2). +/// @param expectedDeviceId PCI device ID this PF should report. +/// @param expectedDriver Kernel driver name that should be bound. +/// @return PfStatus with ok=true if all checks pass, or ok=false with reason. +static PfStatus checkPf(const std::string& bdf, int pfNumber, + unsigned int expectedDeviceId, + const char* expectedDriver) { + std::filesystem::path devPath = PCI_DEVICES_PATH / bdf; + + if (!std::filesystem::exists(devPath)) { + return {.pfNumber = pfNumber, .bdf = bdf, .ok = false, .reason = "not found"}; + } + + auto deviceId = readNumFile(devPath / "device"); + if (deviceId != expectedDeviceId) { + return {.pfNumber = pfNumber, .bdf = bdf, .ok = false, .reason = "bad device ID"}; + } + + std::string driver; + { + std::filesystem::path driverLink = devPath / "driver"; + if (std::filesystem::is_symlink(driverLink)) { + driver = std::filesystem::read_symlink(driverLink).filename().string(); + } + } + + if (driver != expectedDriver) { + std::string actual = driver.empty() ? "(none)" : driver; + return { + .pfNumber = pfNumber, + .bdf = bdf, + .ok = false, + .reason = "wanted driver: '" + std::string(expectedDriver) + + "', currently loaded driver: '" + actual + "'", + }; + } + + return {.pfNumber = pfNumber, .bdf = bdf, .ok = true}; +} + +// --------------------------------------------------------------------------- +// VrtdStatus — VRTD daemon readiness check +// --------------------------------------------------------------------------- + +/// @brief Result of checking whether a board is registered with the VRTD daemon. +struct VrtdStatus { + bool ok{}; ///< True if the board was found in VRTD. + std::string reason; ///< Empty when ok; describes the failure otherwise. +}; + +/// Checks whether a board with the given BDF base is registered with VRTD. +/// +/// Attempts to connect to the VRTD daemon and look up the device by BDF. +/// Catches all vrtd::Error exceptions so that a missing or unreachable +/// daemon does not prevent the list command from working. +/// +/// @param bdfBase Board-level BDF, e.g. "0000:03:00". +/// @return VrtdStatus with ok=true if found, or ok=false with reason. +static VrtdStatus checkVrtd(const std::string& bdfBase) { + try { + vrtd::Session session; + session.getDeviceByBdf(bdfBase); + return {.ok = true}; + } catch (const std::exception& e) { + return {.ok = false, .reason = e.what()}; + } +} + +// --------------------------------------------------------------------------- +// PciDevice — snapshot of one PCI device's sysfs attributes +// --------------------------------------------------------------------------- + +/// @brief Holds the sysfs attributes of a single PCI device. +/// +/// All fields are populated once by fromDevPath() and are then read-only. +/// The @c longPrinting flag controls how much detail is shown in text and +/// JSON output — short mode prints only the BDF. +struct PciDevice { + std::string bdf; ///< BDF address, e.g. "0000:03:00.0". + std::filesystem::path sysfsPath; ///< Full path under /sys/bus/pci/devices/. + unsigned int vendorId{}; ///< PCI vendor ID. + unsigned int deviceId{}; ///< PCI device ID. + unsigned int classCode{}; ///< 24-bit PCI class code. + unsigned int subsysVendor{}; ///< Subsystem vendor ID. + unsigned int subsysDevice{}; ///< Subsystem device ID. + int numaNode{}; ///< NUMA node affinity (-1 if not applicable). + std::string driver; ///< Currently bound kernel driver (empty if unbound). + std::string irq; ///< IRQ number as reported by sysfs. + bool enabled{}; ///< Whether the device is enabled (sysfs "enable" == "1"). + std::string resource; ///< First line of the resource file (BAR0 mapping). + std::string localCpulist; ///< CPU list local to this device's NUMA node. + bool longPrinting{}; ///< If true, output detailed info; otherwise BDF only. + + + /// Constructs a PciDevice by reading all relevant sysfs attributes from + /// @p devPath (e.g. /sys/bus/pci/devices/0000:03:00.0). + static PciDevice fromDevPath(const std::filesystem::path& devPath, bool longPrinting) { + std::string driver; + { + std::filesystem::path driverLink = devPath / "driver"; + if (std::filesystem::is_symlink(driverLink)) { + driver = std::filesystem::read_symlink(driverLink).filename().string(); + } + } + + return PciDevice{ + .bdf{devPath.filename().string()}, + .sysfsPath{devPath}, + .vendorId{readNumFile(devPath / "vendor")}, + .deviceId{readNumFile(devPath / "device")}, + .classCode{readNumFile(devPath / "class")}, + .subsysVendor{readNumFile(devPath / "subsystem_vendor")}, + .subsysDevice{readNumFile(devPath / "subsystem_device")}, + .numaNode{readNumFile(devPath / "numa_node")}, + .driver{std::move(driver)}, + .irq{readStringFile(devPath / "irq")}, + .enabled{readStringFile(devPath / "enable") == "1"}, + .resource{readStringFile(devPath / "resource")}, + .localCpulist{readStringFile(devPath / "local_cpulist")}, + .longPrinting{longPrinting}, + }; + } +}; + + + +// --------------------------------------------------------------------------- +// PciDevice text output +// --------------------------------------------------------------------------- + +/// Human-readable output for a single PCI device. +/// In short mode, prints only the BDF; in long mode, prints all attributes. +std::ostream& operator<<(std::ostream& out, const PciDevice& dev) { + if (!dev.longPrinting) { + return out << dev.bdf << "\n"; + } else { + out + << "Device " << dev.bdf << ":\n" + << INDENT1 << "Vendor ID: " << toHexString(dev.vendorId) << "\n" + << INDENT1 << "Device ID: " << toHexString(dev.deviceId) << "\n" + << INDENT1 << "Class: " << toHexString(dev.classCode) << "\n" + << INDENT1 << "Subsystem vendor: " << toHexString(dev.subsysVendor) << "\n" + << INDENT1 << "Subsystem device: " << toHexString(dev.subsysDevice) << "\n" + << INDENT1 << "NUMA node: " << dev.numaNode << "\n" + << INDENT1 << "Driver: " << (dev.driver.empty() ? "(none)" : dev.driver) << "\n" + << INDENT1 << "IRQ: " << dev.irq << "\n" + << INDENT1 << "Enabled: " << (dev.enabled ? "yes" : "no") << "\n" + << INDENT1 << "Local CPUs: " << dev.localCpulist << "\n"; + } + + return out; +} + +/// Outputs a vector of PCI devices sequentially. +std::ostream& operator<<(std::ostream& out, const std::vector& devices) { + for (const auto& dev : devices) { + out << dev; + } + + return out; +} + +// --------------------------------------------------------------------------- +// PciDevice JSON output +// --------------------------------------------------------------------------- + +/// JSON representation of a single PCI device. +/// In short mode only the BDF is included; long mode adds all attributes. +Json::Value toJson(const PciDevice& dev) { + Json::Value j; + + j["bdf"] = dev.bdf; + + if (dev.longPrinting) { + j["vendor_id"] = toHexString(dev.vendorId); + j["device_id"] = toHexString(dev.deviceId); + j["class"] = toHexString(dev.classCode); + j["subsystem_vendor"] = toHexString(dev.subsysVendor); + j["subsystem_device"] = toHexString(dev.subsysDevice); + j["numa_node"] = toHexString(static_cast(dev.numaNode)); + j["driver"] = dev.driver; + j["irq"] = dev.irq; + j["enabled"] = dev.enabled; + j["local_cpulist"] = dev.localCpulist; + } + + return j; +} + +/// JSON representation of a list of PCI devices, wrapped in a +/// `{ "devices": [ ... ] }` object. +Json::Value toJson(const std::vector& devices) { + Json::Value j; + + j["devices"] = Json::Value(Json::arrayValue); + + for (const auto &dev : devices) { + j["devices"].append(toJson(dev)); + } + + return j; +} + +// --------------------------------------------------------------------------- +// PCI device discovery +// --------------------------------------------------------------------------- + +/// Scans sysfs for PCI devices matching a vendor/device ID, optionally +/// filtered to a specific Physical Function number. +/// +/// The PF number corresponds to the function digit in the BDF string +/// ("DDDD:BB:DD.**F**"). Pass sentinel() to skip PF filtering. +/// +/// @param vendorId PCI vendor ID to match. +/// @param deviceId PCI device ID to match. +/// @param pfNumber Physical Function number to require (0–7), or +/// sentinel to accept any function. +/// @param longPrinting Forwarded to PciDevice; controls output verbosity. +/// @return Vector of matching PciDevice snapshots. +/// @throws std::out_of_range if pfNumber is outside 0–7 (and not sentinel). +std::vector findPciDevices(unsigned int vendorId, unsigned int deviceId, int pfNumber, bool longPrinting) { + std::vector results; + + // Build the BDF suffix filter, e.g. ".0" for PF0. + std::string suffix; + if (!isSentinel(pfNumber)) { + if (pfNumber < 0 || pfNumber > 7) { + throw std::out_of_range("PF Number out of range"); + } + + suffix = "." + std::to_string(pfNumber); + } + + for (const auto& entry : std::filesystem::directory_iterator(PCI_DEVICES_PATH)) { + std::string bdf{entry.path().filename().string()}; + + // BDF must end with the required PF suffix. + if (!bdf.ends_with(suffix)) { + continue; + } + + auto vendor{readNumFile(entry.path() / "vendor")}; + auto device{readNumFile(entry.path() / "device")}; + + if (vendor == vendorId && device == deviceId) { + results.push_back(PciDevice::fromDevPath(entry.path(), longPrinting)); + } + } + + return results; +} + +// --------------------------------------------------------------------------- +// V80Board — aggregated board-level readiness +// --------------------------------------------------------------------------- + +/// @brief Aggregated readiness status of one V80 board (PF0 + PF1 + PF2). +struct V80Board { + std::string bdfBase; ///< BDF prefix without function digit, e.g. "0000:03:00". + PfStatus pf0; ///< Status of PF0 (AMI management). + PfStatus pf1; ///< Status of PF1 (QDMA). + PfStatus pf2; ///< Status of PF2 (control). + VrtdStatus vrtd; ///< Status of VRTD daemon registration. + bool longPrinting{}; ///< If true, include detailed sysfs info per PF. + + /// Detailed sysfs snapshot for each PF (populated only when longPrinting). + std::optional pf0Device; + std::optional pf1Device; + std::optional pf2Device; + + /// Sensor readings (populated only when -s/--sensors is given and VRTD is reachable). + std::vector sensors; + + /// True when all three PFs and VRTD are ready. + bool ok() const { return pf0.ok && pf1.ok && pf2.ok && vrtd.ok; } +}; + +/// Tries to read a PciDevice from sysfs for the given BDF. +/// Returns std::nullopt if the sysfs path does not exist. +static std::optional tryReadDevice(const std::string& bdf, bool longPrinting) { + std::filesystem::path devPath = PCI_DEVICES_PATH / bdf; + if (!std::filesystem::exists(devPath)) { + return std::nullopt; + } + return PciDevice::fromDevPath(devPath, longPrinting); +} + +/// Discovers V80 boards by scanning for PF0 devices, then checking PF1 and PF2. +/// +/// @param longPrinting If true, also reads detailed sysfs attributes for each PF. +/// @param sensors If true, query sensor data from VRTD for each reachable board. +static std::vector discoverBoards(bool longPrinting, bool sensors) { + auto pf0Devices = findPciDevices(SLASH_VENDOR_ID, SLASH_DEVICE_ID, + SLASH_PF_NUMBER, /*longPrinting=*/false); + + std::vector boards; + boards.reserve(pf0Devices.size()); + + for (const auto& pf0Dev : pf0Devices) { + std::string base = pf0Dev.bdf.substr(0, pf0Dev.bdf.rfind('.')); + std::string pf1Bdf = base + ".1"; + std::string pf2Bdf = base + ".2"; + + V80Board board{ + .bdfBase = base, + .pf0 = checkPf(pf0Dev.bdf, 0, SLASH_DEVICE_ID, PF0_EXPECTED_DRIVER), + .pf1 = checkPf(pf1Bdf, 1, SLASH_PF1_DEVICE_ID, PF1_EXPECTED_DRIVER), + .pf2 = checkPf(pf2Bdf, 2, SLASH_PF2_DEVICE_ID, PF2_EXPECTED_DRIVER), + .vrtd = checkVrtd(base), + .longPrinting = longPrinting, + }; + + if (longPrinting) { + board.pf0Device = tryReadDevice(pf0Dev.bdf, true); + board.pf1Device = tryReadDevice(pf1Bdf, true); + board.pf2Device = tryReadDevice(pf2Bdf, true); + } + + if (sensors && board.vrtd.ok) { + try { + vrtd::Session session; + auto device = session.getDeviceByBdf(base); + board.sensors = device.getSensorInfo(); + } catch (...) { + // Sensor query failed — leave sensors empty, don't fail the command. + } + } + + boards.push_back(std::move(board)); + } + + return boards; +} + +// --------------------------------------------------------------------------- +// V80Board text output +// --------------------------------------------------------------------------- + +/// Writes a single PF's status in parenthesized form. +static void printPfStatus(std::ostream& out, const PfStatus& pf) { + out << "(PF" << pf.pfNumber << ": "; + if (pf.ok) { + out << "OK"; + } else { + out << "NOT READY: " << pf.reason; + } + out << ")"; +} + +/// Prints the long-form device details for a PF, indented under the board. +static void printPfDetail(std::ostream& out, const PfStatus& pf, + const std::optional& device) { + out << INDENT1 << "PF" << pf.pfNumber << " " << pf.bdf << ": "; + if (pf.ok) { + out << "OK"; + } else { + out << "NOT READY: " << pf.reason; + } + out << "\n"; + + if (device) { + const auto& dev = *device; + out << INDENT2 << "Vendor ID: " << toHexString(dev.vendorId) << "\n" + << INDENT2 << "Device ID: " << toHexString(dev.deviceId) << "\n" + << INDENT2 << "Class: " << toHexString(dev.classCode) << "\n" + << INDENT2 << "Subsystem vendor: " << toHexString(dev.subsysVendor) << "\n" + << INDENT2 << "Subsystem device: " << toHexString(dev.subsysDevice) << "\n" + << INDENT2 << "NUMA node: " << dev.numaNode << "\n" + << INDENT2 << "Driver: " << (dev.driver.empty() ? "(none)" : dev.driver) << "\n" + << INDENT2 << "IRQ: " << dev.irq << "\n" + << INDENT2 << "Enabled: " << (dev.enabled ? "yes" : "no") << "\n" + << INDENT2 << "Local CPUs: " << dev.localCpulist << "\n"; + } +} + +/// Writes VRTD status in parenthesized form matching the PF style. +static void printVrtdStatus(std::ostream& out, const VrtdStatus& vrtd) { + out << "(VRTD: "; + if (vrtd.ok) { + out << "OK"; + } else { + out << "NOT READY: " << vrtd.reason; + } + out << ")"; +} + +/// Returns a human-readable name for a sensor type bitmask. +static const char *sensorTypeName(uint8_t type) { + switch (type) { + case 1: return "temp"; + case 2: return "current"; + case 4: return "voltage"; + case 8: return "power"; + default: return "unknown"; + } +} + +/// Returns a human-readable name for a sensor status code. +static const char *sensorStatusName(uint8_t status) { + switch (status) { + case 0x01: return "OK"; + case 0x00: return "not present"; + case 0x02: return "no data"; + case 0x03: return "cached"; + case 0x7F: return "N/A"; + default: return "unknown"; + } +} + +/// Returns the base unit string for a sensor type. +static const char *sensorUnitName(uint8_t type) { + switch (type) { + case 1: return "C"; + case 2: return "A"; + case 4: return "V"; + case 8: return "W"; + default: return "?"; + } +} + +/// Converts a raw sensor value with a unit modifier exponent into a +/// human-friendly floating-point value and picks the best SI prefix. +/// For example, value=850 with unitMod=-3 gives 0.85 V (not "850 x10^-3 V"). +struct FormattedSensor { + double value; ///< Scaled value ready for display. + const char* prefix; ///< SI prefix string (e.g. "m", "k", or ""). +}; + +static FormattedSensor formatSensorValue(int32_t raw, int8_t unitMod) { + // Convert to base unit (e.g. V, A, W, C). + double base = raw * std::pow(10.0, static_cast(unitMod)); + double absBase = std::fabs(base); + + struct { double threshold; double divisor; const char* prefix; } constexpr scales[] = { + {1e6, 1e6, "M"}, + {1e3, 1e3, "k"}, + {1.0, 1.0, "" }, + {1e-3, 1e-3, "m"}, + {1e-6, 1e-6, "u"}, + }; + + for (const auto& sc : scales) { + if (absBase >= sc.threshold) { + return {base / sc.divisor, sc.prefix}; + } + } + // Extremely small or zero — just show base units. + return {base, ""}; +} + +/// Prints sensor readings indented under a board. +static void printSensors(std::ostream& out, + const std::vector& sensors) { + out << INDENT1 << "Sensors:\n"; + for (const auto& s : sensors) { + auto [val, prefix] = formatSensorValue(s.value, s.unitMod); + + // Build the unit string, e.g. "mV", "W", "kA". + std::string unit = std::string(prefix) + sensorUnitName(s.type); + + out << INDENT2 + << std::left << std::setw(24) << s.name + << std::setw(10) << sensorTypeName(s.type) + << std::right << std::fixed << std::setprecision(2) + << std::setw(10) << val << " " << std::left << std::setw(4) << unit + << " " << sensorStatusName(s.status) << "\n"; + } +} + +/// Human-readable output for one V80 board. +/// In short mode, prints a single summary line. In long mode, also +/// prints detailed sysfs attributes for each PF. +std::ostream& operator<<(std::ostream& out, const V80Board& board) { + out << "Board " << board.bdfBase << " " + << (board.ok() ? "OK" : "NOT READY") << " "; + printPfStatus(out, board.pf0); + out << " "; + printPfStatus(out, board.pf1); + out << " "; + printPfStatus(out, board.pf2); + out << " "; + printVrtdStatus(out, board.vrtd); + out << "\n"; + + if (board.longPrinting) { + printPfDetail(out, board.pf0, board.pf0Device); + printPfDetail(out, board.pf1, board.pf1Device); + printPfDetail(out, board.pf2, board.pf2Device); + out << INDENT1 << "VRTD: "; + if (board.vrtd.ok) { + out << "OK"; + } else { + out << "NOT READY: " << board.vrtd.reason; + } + out << "\n"; + } + + if (!board.sensors.empty()) { + printSensors(out, board.sensors); + } + + return out; +} + +/// Human-readable output for a list of V80 boards. +std::ostream& operator<<(std::ostream& out, const std::vector& boards) { + for (const auto& board : boards) { + out << board; + } + return out; +} + +// --------------------------------------------------------------------------- +// V80Board JSON output +// --------------------------------------------------------------------------- + +/// JSON representation of a single PF status. +/// If @p device is provided, its sysfs attributes are merged in. +static Json::Value pfToJson(const PfStatus& pf, + const std::optional& device) { + Json::Value j; + j["bdf"] = pf.bdf; + j["status"] = pf.ok ? "OK" : "NOT READY"; + if (!pf.ok) { + j["reason"] = pf.reason; + } + if (device) { + const auto& dev = *device; + j["vendor_id"] = toHexString(dev.vendorId); + j["device_id"] = toHexString(dev.deviceId); + j["class"] = toHexString(dev.classCode); + j["subsystem_vendor"] = toHexString(dev.subsysVendor); + j["subsystem_device"] = toHexString(dev.subsysDevice); + j["numa_node"] = toHexString(static_cast(dev.numaNode)); + j["driver"] = dev.driver; + j["irq"] = dev.irq; + j["enabled"] = dev.enabled; + j["local_cpulist"] = dev.localCpulist; + } + return j; +} + +/// JSON representation of a V80 board. +Json::Value toJson(const V80Board& board) { + Json::Value j; + j["bdf_base"] = board.bdfBase; + j["status"] = board.ok() ? "OK" : "NOT READY"; + j["pf0"] = pfToJson(board.pf0, board.pf0Device); + j["pf1"] = pfToJson(board.pf1, board.pf1Device); + j["pf2"] = pfToJson(board.pf2, board.pf2Device); + + Json::Value vrtdJson; + vrtdJson["status"] = board.vrtd.ok ? "OK" : "NOT READY"; + if (!board.vrtd.ok) { + vrtdJson["reason"] = board.vrtd.reason; + } + j["vrtd"] = vrtdJson; + + if (!board.sensors.empty()) { + Json::Value sensorsJson(Json::arrayValue); + for (const auto& s : board.sensors) { + Json::Value sj; + sj["name"] = s.name; + sj["type"] = sensorTypeName(s.type); + sj["value"] = s.value; + sj["unit_mod"] = static_cast(s.unitMod); + sj["status"] = sensorStatusName(s.status); + sensorsJson.append(sj); + } + j["sensors"] = sensorsJson; + } + + return j; +} + +/// JSON representation of a list of V80 boards. +Json::Value toJson(const std::vector& boards) { + Json::Value j; + j["boards"] = Json::Value(Json::arrayValue); + for (const auto& board : boards) { + j["boards"].append(toJson(board)); + } + return j; +} + +// --------------------------------------------------------------------------- +// Command entry-point +// --------------------------------------------------------------------------- + +/// Discovers all V80 boards and prints their readiness status. +/// +/// In default mode, prints a one-line summary per board. In long mode +/// (`-l`), also prints detailed sysfs attributes for each PF. +int List::run(const Options& options) { + auto boards = discoverBoards(options.longOutput, options.sensorsOutput); + print(boards, options.jsonOutput, options.prettyJsonOutput); + + return 0; +} diff --git a/smi/src/list.hpp b/smi/src/list.hpp new file mode 100644 index 00000000..021a65db --- /dev/null +++ b/smi/src/list.hpp @@ -0,0 +1,51 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file list.hpp +/// @brief Declaration of the List command. +/// +/// The List command enumerates V80 devices visible on the PCI bus by +/// scanning sysfs for devices matching the Slash vendor/device ID. + +#ifndef SMI_LIST_HPP +#define SMI_LIST_HPP + +/// @brief Static entry-point for the list command. +/// +/// This class is not instantiable; it groups the command's option +/// struct and its run() entry-point. +class List { + List() = delete; +public: + /// @brief Options parsed from the CLI for the list command. + struct Options { + bool longOutput{}; ///< Show detailed per-device info (vendor, driver, NUMA, etc.). + bool jsonOutput{}; ///< Emit compact JSON instead of human-readable text. + bool prettyJsonOutput{}; ///< Emit indented JSON instead of human-readable text. + bool sensorsOutput{}; ///< Include sensor readings per device (requires VRTD). + }; + + /// @brief Executes the list command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +#endif // SMI_LIST_HPP diff --git a/smi/src/pcie_hotplug.cpp b/smi/src/pcie_hotplug.cpp deleted file mode 100644 index bf919fb6..00000000 --- a/smi/src/pcie_hotplug.cpp +++ /dev/null @@ -1,58 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "pcie_hotplug.hpp" - -PcieDriverHandler::PcieDriverHandler(const std::string& bdf) { - this->bdf = bdf; - driverPath = pcieHotplugRootPath + "_0000:" + bdf; - if (!std::filesystem::exists(driverPath)) { - throw std::invalid_argument("PCIe Hotplug driver does not exist: " + driverPath); - } -} - -void PcieDriverHandler::execute(Command cmd) { - std::string cmdStr = commandToString(cmd); - int fd = open(driverPath.c_str(), O_WRONLY); - if (fd < 0) { - throw std::runtime_error("Could not open device"); - } - - if (write(fd, cmdStr.c_str(), cmdStr.size()) < 0) { - close(fd); - throw std::runtime_error("Could not write to device " + driverPath); - } - close(fd); -} - -std::string PcieDriverHandler::commandToString(Command cmd) { - switch (cmd) { - case Command::REMOVE: - return "remove"; - case Command::TOGGLE_SBR: - return "toggle_sbr"; - case Command::RESCAN: - return "rescan"; - case Command::HOTPLUG: - return "hotplug"; - default: - throw std::invalid_argument("Invalid command"); - } -} \ No newline at end of file diff --git a/smi/src/program.cpp b/smi/src/program.cpp new file mode 100644 index 00000000..8be8c7ad --- /dev/null +++ b/smi/src/program.cpp @@ -0,0 +1,38 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file program.cpp +/// @brief Implementation of the Program command. + +#include "program.hpp" + +#include + +#include "bdf.hpp" + +int Program::run(const Options& options) { + std::string bdf = resolveBoardBdf(options.bdf, "program"); + + // vrt::Device's constructor handles programming when the third argument + // (program) is true, so simply constructing the object is sufficient. + vrt::Device device(bdf, options.vbinPath, true); + + return 0; +} diff --git a/submodules/v80-vitis-flow/src/sw_emu/arg.cpp b/smi/src/program.hpp similarity index 52% rename from submodules/v80-vitis-flow/src/sw_emu/arg.cpp rename to smi/src/program.hpp index ff2f4ba1..78b3f15d 100644 --- a/submodules/v80-vitis-flow/src/sw_emu/arg.cpp +++ b/smi/src/program.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,25 +18,34 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "arg.hpp" +/// @file program.hpp +/// @brief Declaration of the Program command. +/// +/// The Program command loads a vbin file onto a V80 device identified +/// by its BDF address. -#include +#ifndef SMI_PROGRAM_HPP +#define SMI_PROGRAM_HPP -Arg::Arg(std::string name, uint32_t index, std::string argType) - : name(name), index(index), argType(argType) { - // Check and convert argType - std::regex stream_regex(R"(stream<([^,]+), 0>)"); - std::regex stream_ref_regex(R"(stream<([^,]+), 0>&)"); +#include - if (std::regex_match(argType, stream_regex)) { - this->argType = std::regex_replace(argType, stream_regex, "hls::stream<$1>"); - } else if (std::regex_match(argType, stream_ref_regex)) { - this->argType = std::regex_replace(argType, stream_ref_regex, "hls::stream<$1>&"); - } -} +/// @brief Static entry-point for the program command. +/// +/// This class is not instantiable; it groups the command's option +/// struct and its run() entry-point. +class Program { + Program() = delete; +public: + /// @brief Options parsed from the CLI for the program command. + struct Options { + std::string vbinPath; ///< Path to the vbin file to load onto the device. + std::string bdf; ///< BDF (Bus:Device.Function) address of the target device. + }; -std::string Arg::getName() { return name; } + /// @brief Executes the program command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; -uint32_t Arg::getIndex() { return index; } - -std::string Arg::getArgType() { return argType; } \ No newline at end of file +#endif // SMI_PROGRAM_HPP diff --git a/smi/src/reset.cpp b/smi/src/reset.cpp new file mode 100644 index 00000000..2e53cd8b --- /dev/null +++ b/smi/src/reset.cpp @@ -0,0 +1,39 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file reset.cpp +/// @brief Implementation of the Reset command. + +#include "reset.hpp" + +#include + +#include "bdf.hpp" + +int Reset::run(const Options& options) { + std::string bdf = resolveBoardBdf(options.bdf, "reset"); + + // We use vrtd manually here, since vrt does not implement reset operations. + vrtd::Session session; + auto device = session.getDeviceByBdf(bdf); + device.hotplugOp(vrtd::HotplugOp::ResetSequence); + + return 0; +} diff --git a/submodules/v80-vitis-flow/src/sw_emu/func.cpp b/smi/src/reset.hpp similarity index 55% rename from submodules/v80-vitis-flow/src/sw_emu/func.cpp rename to smi/src/reset.hpp index 3ea6154e..94f3dd3f 100644 --- a/submodules/v80-vitis-flow/src/sw_emu/func.cpp +++ b/smi/src/reset.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,29 +18,33 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "func.hpp" - -Func::Func(const std::string& fn_name, std::vector args) : name(fn_name), args(args) {} - -std::vector Func::getArgs() { return args; } - -std::string Func::getFunctionPrototype() { - std::stringstream ss; - - ss << "extern void " << name << "("; - for (std::size_t i = 0; i < args.size() - 1; i++) { - ss << args.at(i).getArgType() << " " << args.at(i).getName() << ", "; - } - ss << args.at(args.size() - 1).getArgType() << " " << args.at(args.size() - 1).getName() - << ");\n"; - - return ss.str(); -} - -std::string Func::getName() { return name; } - -FunctionCall::FunctionCall(Func fn, std::string fn_name) : function(fn), functionName(fn_name) {} - -std::string FunctionCall::getFunctionName() { return functionName; } - -Func FunctionCall::getFunction() { return function; } \ No newline at end of file +#ifndef SMI_RESET_HPP +#define SMI_RESET_HPP + +/// @file program.hpp +/// @brief Declaration of the Reset command. +/// +/// The Reset hardware resets a V80 board. The board must be programmed +/// with the static SLASH design. + +#include + +/// @brief Static entry-point for the reset command. +/// +/// This class is not instantiable; it groups the command's option +/// struct and its run() entry-point. +class Reset { + Reset() = delete; +public: + /// @brief Options parsed from the CLI for the reset command. + struct Options { + std::string bdf; ///< BDF (Bus:Device.Function) address of the target device. + }; + + /// @brief Executes the reset command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +#endif // SMI_RESET_HPP diff --git a/smi/src/smi.cpp b/smi/src/smi.cpp new file mode 100644 index 00000000..063fdb8e --- /dev/null +++ b/smi/src/smi.cpp @@ -0,0 +1,215 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file smi.cpp +/// +/// Entry point for the SMI (System Management Interface) CLI tool. +/// +/// Parses command-line arguments using CLI11 and dispatches to the +/// appropriate command handler (version, inspect, query, list, program, +/// reset, validate, debug). + +#include +#include + +#include + +#include "debug/bar_poke.hpp" +#include "debug/clockwiz.hpp" +#include "debug/mem_poke.hpp" +#include "inspect.hpp" +#include "list.hpp" +#include "program.hpp" +#include "reset.hpp" +#include "validate.hpp" +#include "version.hpp" + +// Forward declarations +static int smiMain(int argc, char **argv); +static int version(bool plain); + +/// Top-level entry point. Wraps smiMain() in a catch-all so that +/// unhandled exceptions produce a readable error instead of a crash. +int main(int argc, char** argv) { + try { + return smiMain(argc, argv); + } catch (std::exception& e) { + std::cerr << "SMI execution failed: " << e.what() << std::endl; + return 1; + } catch (...) { + std::cerr << "SMI execution failed with unknown error" << std::endl; + return 1; + } +} + +/// The real main function — sets up CLI11 subcommands, parses argv, +/// and routes to the matching command handler. +static int smiMain(int argc, char **argv) { + CLI::App app{std::string("SMI v") + VERSION}; + // Require [0, 1] subcommands. + // Without this positional arguments can get interpreted as commands. + app.require_subcommand(0, 1); + + // -- version -- + auto* versionCommand = app.add_subcommand("version", "Print version information and exit"); + bool versionPlain{}; + versionCommand->add_flag("-p,--plain", versionPlain, "Print only the version in x.y.z format and nothing else (useful in scripting)"); + + // -- inspect (file on disk) -- + auto* inspectCommand = app.add_subcommand("inspect", "Inspect vbin file"); + Inspect::Options inspectOptions; + inspectCommand->add_option("vbin", inspectOptions.vbinPath, "Path to vbin file")->required(); + inspectCommand->add_flag("-j,--json", inspectOptions.jsonOutput, "Print information as compact json (default is human-readable)"); + inspectCommand->add_flag("-J,--pretty-json", inspectOptions.prettyJsonOutput, "Print information as json with indentation (default is human-readable)"); + + // -- query (inspect what's loaded on a device) -- + auto* queryCommand = app.add_subcommand("query", "Query vbin file last loaded on device"); + Query::Options queryOptions{.isBdfQuery=true}; + queryCommand->add_option("-d,--device", queryOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + queryCommand->add_flag("-j,--json", queryOptions.jsonOutput, "Print information as compact json (default is human-readable)"); + queryCommand->add_flag("-J,--pretty-json", queryOptions.prettyJsonOutput, "Print information as json with indentation (default is human-readable)"); + + // -- list (enumerate devices) -- + auto* listCommand = app.add_subcommand("list", "List V80 devices"); + List::Options listOptions; + listCommand->add_flag("-j,--json", listOptions.jsonOutput, "Print information as compact json (default is human-readable)"); + listCommand->add_flag("-J,--pretty-json", listOptions.prettyJsonOutput, "Print information as json with indentation (default is human-readable)"); + listCommand->add_flag("-l,--long", listOptions.longOutput, "Print additional information"); + listCommand->add_flag("-s,--sensors", listOptions.sensorsOutput, "Include sensor readings (requires VRTD)"); + + // -- program (load vbin onto device) -- + auto* programCommand = app.add_subcommand("program", "Program a hardware device"); + Program::Options programOptions; + programCommand->add_option("vbin", programOptions.vbinPath, "Path to vbin file")->required(); + programCommand->add_option("-d,--device", programOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + + // -- reset (hardware reset of board) -- + auto* resetCommand = app.add_subcommand("reset", "Hardware reset a V80 board"); + Reset::Options resetOptions; + resetCommand->add_option("-d,--device", resetOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + + // -- validate (memory integrity + bandwidth) -- + auto* validateCommand = app.add_subcommand("validate", "Validate board memory (integrity + bandwidth)"); + Validate::Options validateOptions; + validateCommand->add_option("-d,--device", validateOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + validateCommand->add_option("-j,--threads", validateOptions.threads, + "Number of parallel buffers/threads (1-64)")->default_val(8)->check(CLI::Range(1u, 64u)); + validateCommand->add_flag("-R,--no-reset", validateOptions.noReset, + "Skip the device reset step before running memory tests"); + + // -- debug (low-level debug utilities) -- + auto* debugCommand = app.add_subcommand("debug", "Low-level debug utilities"); + debugCommand->require_subcommand(1, 1); + + auto* barPokeCommand = debugCommand->add_subcommand("bar-poke", "Read or write BAR words"); + BarPoke::Options barPokeOptions; + barPokeCommand->add_option("-d,--device", barPokeOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + barPokeCommand->add_option("-b,--bar", barPokeOptions.bar, "BAR number (0-5)")->required()->check(CLI::Range(0u, 5u)); + barPokeCommand->add_flag("-r,--read", barPokeOptions.readMode, "Read words from BAR"); + barPokeCommand->add_flag("-w,--write", barPokeOptions.writeMode, "Write one word to BAR"); + barPokeCommand->add_flag("-x,--hex", barPokeOptions.hexMode, "Print read output in hexadecimal"); + barPokeCommand->add_option("-W,--word-size", barPokeOptions.wordSize, "Word size in bytes (1, 2, 4, 8)") + ->default_val(4)->check(CLI::IsMember({1u, 2u, 4u, 8u})); + barPokeCommand->add_option("-c,--count", barPokeOptions.count, "Number of words to read (must be 1 for write)") + ->default_val(1); + barPokeCommand->add_option("address", barPokeOptions.addressText, + "BAR-relative address (0x... for hex, decimal otherwise)")->required(); + barPokeCommand->add_option("value", barPokeOptions.valueText, + "Value for --write (0x... for hex, decimal otherwise)"); + + auto* clockwizCommand = debugCommand->add_subcommand("clockwiz", "Read or set clock rates via vrtd clock-op"); + Clockwiz::Options clockwizOptions; + clockwizCommand->add_option("-d,--device", clockwizOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + clockwizCommand->add_flag("--get", clockwizOptions.getMode, "Read clock rate for selected region"); + clockwizCommand->add_option("--set", clockwizOptions.setRateText, "Set requested clock rate in Hz for selected region"); + clockwizCommand->add_option("--region", clockwizOptions.regionText, "Clock region: user or service") + ->default_val("user"); + clockwizCommand->add_flag("-x,--hex", clockwizOptions.hexMode, "Print --get output in hexadecimal"); + + auto* memPokeCommand = debugCommand->add_subcommand("mem-poke", + "Read or write device memory at a raw physical address (bypasses allocator; requires raw-mem-access permission). " + "Use --region to declare the target memory space and validate address bounds."); + MemPoke::Options memPokeOptions; + memPokeCommand->add_option("-d,--device", memPokeOptions.bdf, "Board address (e.g. 03:00 or 0000:03:00)")->required(); + memPokeCommand->add_option("--region,-r", memPokeOptions.regionText, + "Memory region: DDR, HBM, HBM0..HBM63, or RAW (no bounds check)")->required(); + memPokeCommand->add_flag("--read", memPokeOptions.readMode, "Read words from device memory"); + memPokeCommand->add_flag("--write,-w", memPokeOptions.writeMode, "Write one word to device memory"); + memPokeCommand->add_flag("-x,--hex", memPokeOptions.hexMode, "Print read output in hexadecimal"); + memPokeCommand->add_flag("--relative", memPokeOptions.relativeAddress, + "Interpret address as relative to the region base address"); + memPokeCommand->add_flag("--print-base-address", memPokeOptions.printBaseAddress, + "Print the region base address in hex and exit (mutually exclusive with I/O flags)"); + memPokeCommand->add_flag("--print-size", memPokeOptions.printSize, + "Print the region size in bytes in hex and exit (mutually exclusive with I/O flags)"); + memPokeCommand->add_option("-W,--word-size", memPokeOptions.wordSize, "Word size in bytes (1, 2, 4, 8)") + ->default_val(4)->check(CLI::IsMember({1u, 2u, 4u, 8u})); + memPokeCommand->add_option("-c,--count", memPokeOptions.count, "Number of words to read (must be 1 for write)") + ->default_val(1); + memPokeCommand->add_option("address", memPokeOptions.addressText, + "Device physical address (0x... for hex, decimal otherwise); relative to region base if --relative"); + memPokeCommand->add_option("value", memPokeOptions.valueText, + "Value for --write (0x... for hex, decimal otherwise)"); + memPokeCommand->add_option("-f,--file", memPokeOptions.filePath, + "File path: source for --write, destination for --read. " + "With -x: hexdump format (no 0x prefix); without -x: raw binary. " + "In file mode -W and -c determine the byte count (-W * -c), not word alignment."); + + CLI11_PARSE(app, argc, argv); + + // Route commands + if (versionCommand->parsed()) { + return version(versionPlain); + } else if (inspectCommand->parsed()) { + return Inspect::run(inspectOptions); + } else if (queryCommand->parsed()) { + return Query::run(queryOptions); + } else if (listCommand->parsed()) { + return List::run(listOptions); + } else if (programCommand->parsed()) { + return Program::run(programOptions); + } else if (resetCommand->parsed()) { + return Reset::run(resetOptions); + } else if (validateCommand->parsed()) { + return Validate::run(validateOptions); + } else if (barPokeCommand->parsed()) { + return BarPoke::run(barPokeOptions); + } else if (clockwizCommand->parsed()) { + return Clockwiz::run(clockwizOptions); + } else if (memPokeCommand->parsed()) { + return MemPoke::run(memPokeOptions); + } else { + // No subcommand given - print help and exit with error. + std::cerr << app.help() << std::endl; + return 1; + } +} + +/// Print version information and exit. +static int version(bool plain) { + if (!plain) { + std::cout << "SMI v"; + } + + std::cout << VERSION << std::endl; + + return 0; +} + diff --git a/smi/src/utils.hpp b/smi/src/utils.hpp new file mode 100644 index 00000000..c8654061 --- /dev/null +++ b/smi/src/utils.hpp @@ -0,0 +1,116 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file utils.hpp +/// @brief Common utilities for formatting, sentinel values, and output in smi. + +#ifndef SMI_UTILS_HPP +#define SMI_UTILS_HPP + +#include +#include +#include +#include +#include + +#include + +/// Indentation constant for hierarchical text output (one level). +constexpr char INDENT1[] = " "; + +/// Indentation constant for hierarchical text output (two levels). +constexpr char INDENT2[] = " "; + +/// Indentation constant for hierarchical text output (three levels). +constexpr char INDENT3[] = " "; + +/// Converts an integer value to a "0x"-prefixed hexadecimal string. +/// +/// @tparam Int Integral type of the value. +/// @param value The integer to convert. +/// @return Hex string (e.g., "0x1a3f"). +/// @throws std::runtime_error if the internal conversion fails (should not +/// happen under normal circumstances). +template +std::string toHexString(Int value) { + constexpr size_t buf_size{32}; + char buf[buf_size]{'0', 'x'}; + std::to_chars_result result = std::to_chars(buf + 2, buf + buf_size, value, 16); + + if (result.ec != std::errc()) { + throw std::runtime_error("Internal error in toHexString. This is a bug in smi. Please report."); + } + + return {buf}; +} + +/// Returns a generic sentinel value for the given integer type. +/// +/// @tparam Int Integral type. +/// @return -1 for signed types; max representable value for unsigned types. +template +consteval Int sentinel() { + if constexpr (std::numeric_limits::is_signed) { + return static_cast(-1); + } else { + return std::numeric_limits::max(); + } +} + + +/// Tests whether @p i holds the sentinel value for its type. +/// +/// @tparam Int Integral type. +/// @param i Value to test. +/// @return true if @p i equals sentinel(). +template +constexpr bool isSentinel(Int i) { + return i == sentinel(); +} + +/// Prints an object to stdout, either as human-readable text or as JSON. +/// +/// In text mode the object is streamed via its `operator<<` overload. +/// In JSON mode the object is first converted via an ADL-found `toJson()` +/// overload and then serialized through jsoncpp. +/// +/// In order to use this, commands must define `operator<<` and `toJson()` +/// functions for the objects they want to print. +/// +/// @tparam T Type that supports `operator<<` and a free `toJson()`. +/// @param object The object to print. +/// @param json If true, output compact JSON. +/// @param prettyJson If true, output indented (pretty-printed) JSON. +template +void print(const T& object, bool json = false, bool prettyJson = false) { + if (json || prettyJson) { + const auto data = toJson(object); + + Json::StreamWriterBuilder builder; + builder["indentation"] = (prettyJson ? INDENT1 : ""); + std::unique_ptr writer(builder.newStreamWriter()); + writer->write(data, &std::cout); + std::cout << std::endl; // writer doesn't add trailing newline + } else { + std::cout << object << std::flush; + } +} + +#endif // SMI_PROGRAM_HPP diff --git a/smi/src/utils/filesystem_cache.cpp b/smi/src/utils/filesystem_cache.cpp deleted file mode 100644 index 31b59a23..00000000 --- a/smi/src/utils/filesystem_cache.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "utils/filesystem_cache.hpp" - -#include -#include -#include - -std::filesystem::path FilesystemCache::getCachePath() { - std::filesystem::path path; - - // 1. Try $SLASH_CACHE_PATH - if (const char* slashCache = std::getenv("SLASH_CACHE_PATH")) { - path = slashCache; - } - - // 2. Try $XDG_CACHE_HOME/SLASH - else if (const char* xdgCache = std::getenv("XDG_CACHE_HOME")) { - path = std::filesystem::path(xdgCache) / "SLASH" / "smi"; - } - - // 3. Try $HOME/.cache/SLASH - else if (const char* home = std::getenv("HOME")) { - path = std::filesystem::path(home) / ".cache" / "SLASH" / "smi"; - } - - // 4. Fallback: /tmp/SLASH-cache- - else { - path = "/tmp/SLASH-cache-" + std::to_string(getuid()) + "/smi"; - } - - ensureDirExists(path); - - return path; -} - -std::filesystem::path FilesystemCache::getRuntimePath() { - std::filesystem::path path; - - // 1. Try $SLASH_RUNTIME_PATH - if (const char* slashCache = std::getenv("SLASH_RUNTIME_PATH")) { - path = slashCache; - } - - // 2. Try XDG_RUNTIME_DIR/SLASH - else if (const char* xdgCache = std::getenv("XDG_RUNTIME_DIR")) { - path = std::filesystem::path(xdgCache) / "SLASH" / "smi"; - } - - // 3. Fallback: /tmp/SLASH-run- - else { - path = "/tmp/SLASH-run-" + std::to_string(getuid()) + "/smi"; - } - - ensureDirExists(path); - - return path; -} - -void FilesystemCache::ensureDirExists(const std::filesystem::path& path) { - std::error_code ec; - std::filesystem::create_directories(path, ec); - if (ec) { - throw std::system_error(ec); - } -} diff --git a/smi/src/utils/vrtbin.cpp b/smi/src/utils/vrtbin.cpp deleted file mode 100644 index b5e3e45f..00000000 --- a/smi/src/utils/vrtbin.cpp +++ /dev/null @@ -1,182 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "utils/vrtbin.hpp" -#include "utils/filesystem_cache.hpp" - -void Vrtbin::extract(std::string source, std::string destination) { - std::string command = "tar -xvf " + source + " -C " + destination + " 2>&1"; - std::array buffer; - std::string result; - - std::unique_ptr pipe(popen(command.c_str(), "r"), pclose); - if (!pipe) { - throw std::runtime_error("popen() failed!"); - } - - while (fgets(buffer.data(), buffer.size(), pipe.get()) != nullptr) { - result += buffer.data(); - } -} - -void Vrtbin::copy(const std::string& source, const std::string& destination) { - std::ifstream src(source, std::ios::binary); - if (!src) { - std::cerr << "Error opening source file: " << source << std::endl; - throw std::runtime_error("Error opening source file"); - } - - std::ofstream dest(destination, std::ios::binary); - if (!dest) { - std::cerr << "Error opening destination file: " << destination << std::endl; - throw std::runtime_error("Error opening destination file"); - } - - dest << src.rdbuf(); - - if (!src) { - std::cerr << "Error reading from source file: " << source << std::endl; - throw std::runtime_error("Error reading from source file"); - } - - if (!dest) { - std::cerr << "Error writing to destination file: " << destination << std::endl; - throw std::runtime_error("Error writing to destination file"); - } -} - -std::string Vrtbin::extractUUID() { - std::string uuid; - std::ifstream jsonFile(FilesystemCache::getCachePath() / "version.json"); - if (!jsonFile.is_open()) { - uuid = ""; - } - std::string line; - while (std::getline(jsonFile, line)) { - std::size_t pos = line.find("\"logic_uuid\":"); - if (pos != std::string::npos) { - std::size_t start = line.find("\"", pos + 13) + 1; - std::size_t end = line.find("\"", start); - uuid = line.substr(start, end - start); - break; - } - } - jsonFile.close(); - return uuid; -} - -void Vrtbin::progressHandler(enum ami_event_status status, uint64_t ctr, void* data) { - struct ami_pdi_progress* prog = NULL; - - if (!data) return; - - prog = (struct ami_pdi_progress*)data; - - if (status == AMI_EVENT_STATUS_OK) prog->bytes_written += ctr; - - prog->reserved = print_progress_bar(prog->bytes_written, prog->bytes_to_write, - 100, // progress bar width - '[', ']', '#', '.', prog->reserved); -} - -char Vrtbin::print_progress_bar(uint32_t cur, uint32_t max, uint32_t width, char left, char right, - char fill, char empty, char state) { - int i = 0; - char new_state = 0; - uint32_t progress = 0; - - if (max == 0) max = 1; - - progress = ((unsigned long long)cur * width) / max; - - /* Move to beginning of the line */ - putchar('\r'); - - /* Print left margin */ - putchar(left); - - if (width < progress) progress = width; - - for (i = 0; i < progress; i++) putchar(fill); - - for (i = 0; i < (width - progress); i++) putchar(empty); - - putchar(right); - printf(" %.0f%% ", ((double)cur / (double)max) * 100); - - switch (state) { - case '|': - putchar('|'); - new_state = '-'; - break; - - case '-': - putchar('-'); - new_state = '|'; - break; - - default: - putchar('|'); - new_state = '-'; - break; - } - - /* Print space so cursor doesn't obstruct last character. */ - putchar(' '); - - fflush(stdout); - return new_state; -} - -void Vrtbin::extractAndPrintInfo(const std::string& path) { - std::ifstream jsonFile(path); - if (!jsonFile.is_open()) { - std::cerr << "Error: could not open file " << path << std::endl; - return; - } - - std::string line; - char name[256] = {0}; - char release[256] = {0}; - char logicUuid[256] = {0}; - char application[256] = {0}; - - while (std::getline(jsonFile, line)) { - if (line.find("\"name\":") != std::string::npos) { - sscanf(line.c_str(), " \"name\": \"%[^\"]\"", name); - } else if (line.find("\"release\":") != std::string::npos) { - sscanf(line.c_str(), " \"release\": \"%[^\"]\"", release); - } else if (line.find("\"logic_uuid\":") != std::string::npos) { - sscanf(line.c_str(), " \"logic_uuid\": \"%[^\"]\"", logicUuid); - } else if (line.find("\"application\":") != std::string::npos) { - sscanf(line.c_str(), " \"application\": \"%[^\"]\"", application); - } - } - - jsonFile.close(); - - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Design Information\n"; - std::cout << "--------------------------------------------------------------------\n"; - std::cout << "Design Name | " << name << "\n"; - std::cout << "Release | " << release << "\n"; - std::cout << "Logic UUID | " << logicUuid << "\n"; - std::cout << "Application | " << application << "\n\n"; -} diff --git a/smi/src/validate.cpp b/smi/src/validate.cpp new file mode 100644 index 00000000..605e9abc --- /dev/null +++ b/smi/src/validate.cpp @@ -0,0 +1,213 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/// @file validate.cpp +/// @brief Implementation of the Validate command. +/// +/// Resets a V80 board, then exercises HBM and DDR memory over PCIe: +/// 1. Data integrity checks (write pattern, read back, verify). +/// 2. Parallel bandwidth measurements (N threads, one per buffer). +/// +/// We use libvrtdpp (vrtd::Session / vrtd::Device / vrtd::Buffer) directly +/// rather than the higher-level vrt::Device because vrt::Device requires a +/// vrtbin path for system-map parsing, which is unnecessary for raw memory +/// validation. +/// +/// TODO: Decide whether vrt::Device should gain a vrtbin-less constructor so +/// that commands like validate can go through the standard vrt:: layer. + +#include "validate.hpp" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bdf.hpp" + +/// Buffer size for each allocation (64 MB — one allocator subregion). +static constexpr uint64_t BUFFER_SIZE = 64ULL * 1024 * 1024; + +/// Fill @p buf with a deterministic pattern seeded by @p seed. +static void fillPattern(void* buf, uint64_t size, uint32_t seed) { + auto* p = static_cast(buf); + uint64_t count = size / sizeof(uint32_t); + for (uint64_t i = 0; i < count; ++i) { + p[i] = static_cast(i) ^ seed; + } +} + +/// Verify @p buf matches the pattern produced by fillPattern(). +/// Returns true on match, false on first mismatch. +static bool verifyPattern(const void* buf, uint64_t size, uint32_t seed) { + auto* p = static_cast(buf); + uint64_t count = size / sizeof(uint32_t); + for (uint64_t i = 0; i < count; ++i) { + if (p[i] != (static_cast(i) ^ seed)) { + return false; + } + } + return true; +} + +/// Run data integrity on every buffer: write pattern → sync to device → +/// clear host → sync from device → verify. +/// @return true if all buffers pass. +static bool testDataIntegrity(std::vector& buffers, + const std::string& label) { + bool allPassed = true; + + for (size_t i = 0; i < buffers.size(); ++i) { + auto& buf = buffers[i]; + uint32_t seed = static_cast(i); + uint64_t size = buf.getSize(); + + fillPattern(buf.data(), size, seed); + buf.syncToDevice(0, size); + + std::memset(buf.data(), 0, size); + buf.syncFromDevice(0, size); + + bool ok = verifyPattern(buf.data(), size, seed); + std::cout << " " << label << i << ": " + << (ok ? "OK" : "FAIL") << std::endl; + + if (!ok) { + allPassed = false; + } + } + + return allPassed; +} + +/// Measure aggregate write and read bandwidth across all buffers in parallel +/// (one std::thread per buffer). +static void testBandwidth(std::vector& buffers) { + uint64_t totalBytes = 0; + for (auto& buf : buffers) { + std::memset(buf.data(), 0xAB, buf.getSize()); + totalBytes += buf.getSize(); + } + + // -- Write (H2C) bandwidth -- + auto writeStart = std::chrono::steady_clock::now(); + { + std::vector threads; + threads.reserve(buffers.size()); + for (auto& buf : buffers) { + threads.emplace_back([&buf] { + buf.syncToDevice(0, buf.getSize()); + }); + } + for (auto& t : threads) { + t.join(); + } + } + auto writeEnd = std::chrono::steady_clock::now(); + + // -- Read (C2H) bandwidth -- + auto readStart = std::chrono::steady_clock::now(); + { + std::vector threads; + threads.reserve(buffers.size()); + for (auto& buf : buffers) { + threads.emplace_back([&buf] { + buf.syncFromDevice(0, buf.getSize()); + }); + } + for (auto& t : threads) { + t.join(); + } + } + auto readEnd = std::chrono::steady_clock::now(); + + double writeSec = std::chrono::duration(writeEnd - writeStart).count(); + double readSec = std::chrono::duration(readEnd - readStart).count(); + double totalMB = static_cast(totalBytes) / (1024.0 * 1024.0); + + std::cout << " Write: " << std::fixed << std::setprecision(2) + << (totalMB / writeSec) << " MB/s" << std::endl; + std::cout << " Read: " << std::fixed << std::setprecision(2) + << (totalMB / readSec) << " MB/s" << std::endl; +} + +int Validate::run(const Options& options) { + std::string bdf = resolveBoardBdf(options.bdf, "validate"); + unsigned N = options.threads; + + // -- Step 1: (Optional) Reset the device via vrtd -- + if (!options.noReset) { + std::cout << "Resetting device " << bdf << "..." << std::endl; + { + vrtd::Session session; + auto device = session.getDeviceByBdf(bdf); + device.hotplugOp(vrtd::HotplugOp::ResetSequence); + } + // Session is torn down; the daemon has re-discovered the device. + } + + vrtd::Session session; + auto device = session.getDeviceByBdf(bdf); + + // -- Step 2: HBM — integrity then bandwidth -- + std::cout << "Testing HBM data integrity (" << N << " regions)..." << std::endl; + { + std::vector hbmBuffers; + hbmBuffers.reserve(N); + for (unsigned i = 0; i < N; ++i) { + hbmBuffers.push_back(device.openHbmBuffer(i, BUFFER_SIZE)); + } + + if (!testDataIntegrity(hbmBuffers, "HBM")) { + std::cerr << "HBM data integrity check failed" << std::endl; + return 1; + } + + std::cout << "Testing HBM bandwidth (" << N << " threads)..." << std::endl; + testBandwidth(hbmBuffers); + } + // HBM buffers released. + + // -- Step 3: DDR — integrity then bandwidth -- + std::cout << "Testing DDR data integrity (" << N << " buffers)..." << std::endl; + { + std::vector ddrBuffers; + ddrBuffers.reserve(N); + for (unsigned i = 0; i < N; ++i) { + ddrBuffers.push_back(device.openDdrBuffer(BUFFER_SIZE)); + } + + if (!testDataIntegrity(ddrBuffers, "DDR")) { + std::cerr << "DDR data integrity check failed" << std::endl; + return 1; + } + + std::cout << "Testing DDR bandwidth (" << N << " threads)..." << std::endl; + testBandwidth(ddrBuffers); + } + // DDR buffers released. + + return 0; +} diff --git a/smi/src/validate.hpp b/smi/src/validate.hpp new file mode 100644 index 00000000..2e5d1f8e --- /dev/null +++ b/smi/src/validate.hpp @@ -0,0 +1,53 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMI_VALIDATE_HPP +#define SMI_VALIDATE_HPP + +/// @file validate.hpp +/// @brief Declaration of the Validate command. +/// +/// The Validate command resets a V80 board and then exercises DDR and HBM +/// memory via PCIe by running data integrity checks followed by parallel +/// bandwidth measurements. + +#include + +/// @brief Static entry-point for the validate command. +/// +/// This class is not instantiable; it groups the command's option +/// struct and its run() entry-point. +class Validate { + Validate() = delete; +public: + /// @brief Options parsed from the CLI for the validate command. + struct Options { + std::string bdf; ///< BDF (Bus:Device.Function) address of the target device. + unsigned threads = 8; ///< Number of parallel buffers/threads (1-64). + bool noReset = false; ///< Skip the device reset step before running memory tests. + }; + + /// @brief Executes the validate command. + /// @param options Populated options struct. + /// @return Exit code (0 on success). + static int run(const Options& options); +}; + +#endif // SMI_VALIDATE_HPP diff --git a/smi/v80-smi.cpp b/smi/v80-smi.cpp deleted file mode 100644 index 33ed2d0b..00000000 --- a/smi/v80-smi.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "arg_parser.hpp" -#include "commands/inspect_command.hpp" -#include "commands/list_command.hpp" -#include "commands/partial_program_command.hpp" -#include "commands/program_command.hpp" -#include "commands/query_command.hpp" -#include "commands/reload_command.hpp" -#include "commands/reset_command.hpp" -#include "commands/resource_command.hpp" -#include "commands/validate_command.hpp" - -int main(int argc, char* argv[]) { - ArgParser parser; - parser.parse(argc, argv); - - if (parser.isCommand("query")) { - std::string device = parser.getDevice(); - if (!device.empty()) { - QueryCommand queryCommand(device); - queryCommand.execute(); - } else { - std::cerr << "Error: Device not specified" << std::endl; - parser.printHelp(); - return EXIT_FAILURE; - } - } else if (parser.isCommand("validate")) { - std::cout << "Validating device..." << std::endl; - ValidateCommand validateCommand(parser.getDevice()); - validateCommand.execute(); - } else if (parser.isCommand("report_utilization")) { - ResourceCommand resourceCommand(parser.getDevice()); - } else if (parser.isCommand("list")) { - ListCommand listCommand(0x10ee, 0x50b4); - listCommand.execute(); - } else if (parser.isCommand("program")) { - ProgramCommand programCommand(parser.getDevice(), parser.getImagePath(), - parser.getPartition()); - programCommand.execute(); - } else if (parser.isCommand("partial_program")) { - PartialProgramCommand partialProgramCommand(parser.getDevice(), parser.getImagePath()); - partialProgramCommand.execute(); - } else if (parser.isCommand("inspect")) { - InspectCommand inspectCommand(parser.getImagePath()); - inspectCommand.execute(); - } else if (parser.isCommand("reload")) { - ReloadCommand reloadCommand(parser.getDevice()); - reloadCommand.execute(); - } else if (parser.isCommand("reset")) { - ResetCommand resetCommand(parser.getDevice()); - resetCommand.execute(); - } else { - parser.printHelp(); - } - - return EXIT_SUCCESS; -} \ No newline at end of file diff --git a/submodules/AVED b/submodules/AVED new file mode 160000 index 00000000..ed544986 --- /dev/null +++ b/submodules/AVED @@ -0,0 +1 @@ +Subproject commit ed5449865a597e3909ed0426a81140c31aa30cec diff --git a/submodules/pcie-hotplug-drv/LICENSE b/submodules/pcie-hotplug-drv/LICENSE deleted file mode 100644 index b46cac89..00000000 --- a/submodules/pcie-hotplug-drv/LICENSE +++ /dev/null @@ -1,82 +0,0 @@ -GNU GENERAL PUBLIC LICENSE -Version 2, June 1991 - -Copyright (C) 1989, 1991 Free Software Foundation, Inc. - -Everyone is permitted to copy and distribute verbatim copies -of this license document, but changing it is not allowed. -Preamble -The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. - -When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. - -To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. - -For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. - -We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. - -Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. - -Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. - -The precise terms and conditions for copying, distribution and modification follow. - -TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION -0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". - -Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. - -1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. - -You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. - -2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: - -a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. -b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. -c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) -These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. - -Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. - -In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. - -3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: - -a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, -b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, -c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) -The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. - -If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. - -4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. - -5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. - -6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. - -7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. - -If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. - -It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. - -This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. - -8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. - -9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. - -Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. - -10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. - -NO WARRANTY - -11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - -12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - -END OF TERMS AND CONDITIONS \ No newline at end of file diff --git a/submodules/pcie-hotplug-drv/Makefile b/submodules/pcie-hotplug-drv/Makefile deleted file mode 100644 index 0c12e538..00000000 --- a/submodules/pcie-hotplug-drv/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# ################################################################################################## -# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. -# This program is free software; you can redistribute it and/or modify it under the terms of the -# GNU General Public License as published by the Free Software Foundation; version 2. -# -# This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without -# even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. -# -# You should have received a copy of the GNU General Public License along with this program; if -# not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -# 02110-1301, USA. -# ################################################################################################## - -KMOD := pcie_hotplug - -KDIR := /lib/modules/$(shell uname -r)/build -PWD := $(shell pwd) -CC := g++ - -all: $(KMOD).ko - -$(KMOD).ko: driver/$(KMOD).c - $(MAKE) -C $(KDIR) M=$(PWD)/driver modules - -clean: - $(MAKE) -C $(KDIR) M=$(PWD)/driver clean - - -install: $(KMOD).ko - cp driver/$(KMOD).ko /lib/modules/$(shell uname -r)/kernel/drivers/misc/ - depmod - modprobe $(KMOD) - chmod 666 /dev/$(KMOD)_* || echo "Warning: Failed to set permissions for dev" - -uninstall: - modprobe -r $(KMOD) - rm -f /lib/modules/$(shell uname -r)/kernel/drivers/misc/$(KMOD).ko - depmod - -.PHONY: all clean install uninstall diff --git a/submodules/pcie-hotplug-drv/README.md b/submodules/pcie-hotplug-drv/README.md deleted file mode 100644 index 8049d2e4..00000000 --- a/submodules/pcie-hotplug-drv/README.md +++ /dev/null @@ -1,63 +0,0 @@ -# PCIe Hotplug Driver - -This project contains a kernel module for PCIe hotplug functionality. The kernel module is located in the `driver` directory. - -## Building - -To build the kernel module, run: - -``` -make -``` - -## Cleaning - -To clean up the build artifacts, run: - -``` -make clean -``` - -## Installing the Kernel Module - -To install the kernel module, run: - -``` -sudo make install -``` -Hotplug driver insertion automatically searches for devices with VENDOR_ID and DEVICE_ID defined in driver/pcie_hotplug_ids.h. To add another device, add your VENDOR_ID and DEVICE_ID above the last line: - -```C - { PCI_DEVICE(0x10ee, 0x50b4) }, /**< Xilinx V80 PCIe device */ - { PCI_DEVICE(0xXXXX, 0xXXXX) }, /**< Add new devices here */ - { 0, } /**< End of list */ -``` - -Then re-run make and sudo make install to reinstall the driver. -## Uninstalling the Kernel Module - -To uninstall the kernel module, run: - -``` -sudo make uninstall -``` - -## Makefile Targets - -- `all`: Builds both the kernel module and the user-space application. -- `clean`: Cleans up the build artifacts. -- `install`: Installs the kernel module to the appropriate directory and updates the module dependencies. -- `uninstall`: Removes the kernel module and cleans up the installation. - -## Example Usage -After installing the driver, a device file should be present: `/dev/pcie_hotplug`. You can interact with it as follows: -- `echo 'remove' > /dev/pcie_hotplug_0000:bb:dd.f`. This removes the device from the root tree. -- `echo 'toggle_sbr' > /dev/pcie_hotplug_0000:bb:dd.f`. This triggers PCIe Secondary Bus Reset. -- `echo 'rescan' > /dev/pcie_hotplug_0000:bb:dd.f`. This rescans the PCIe bus. -- `echo 'hotplug' > /dev/pcie_hotplug_0000:bb:dd.f`. This performs a PCIe device hotplug, which reinitializes bound drivers of the device. - - -## Notes - -- Ensure you have the necessary permissions to install and uninstall kernel modules. -- The adding of the hotplug driver should be done after each reboot. diff --git a/submodules/pcie-hotplug-drv/driver/Makefile b/submodules/pcie-hotplug-drv/driver/Makefile deleted file mode 100644 index 32ce55d5..00000000 --- a/submodules/pcie-hotplug-drv/driver/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# ################################################################################################## -# Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. -# This program is free software; you can redistribute it and/or modify it under the terms of the -# GNU General Public License as published by the Free Software Foundation; version 2. -# -# This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without -# even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. -# -# You should have received a copy of the GNU General Public License along with this program; if -# not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -# 02110-1301, USA. -# ################################################################################################## -obj-m := pcie_hotplug.o - -KDIR := /lib/modules/$(shell uname -r)/build -PWD := $(shell pwd) - -all: - $(MAKE) -C $(KDIR) M=$(PWD) modules - -clean: - $(MAKE) -C $(KDIR) M=$(PWD) clean \ No newline at end of file diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c b/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c deleted file mode 100644 index a60e1fa9..00000000 --- a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.c +++ /dev/null @@ -1,518 +0,0 @@ -/** - * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. - * This program is free software; you can redistribute it and/or modify it under the terms of the - * GNU General Public License as published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without - * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with this program; if - * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#include "pcie_hotplug.h" -#include - -#if (defined(LINUX_VERSION_CODE) && defined(KERNEL_VERSION) && \ - (LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,0))) || \ - (defined(RHEL_RELEASE_CODE) && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(9,0))) - /* New API: class_create(const char *name) */ -# define CLASS_CREATE(name) class_create(name) -#else - /* Old API: class_create(struct module *, const char *name) */ -# define CLASS_CREATE(name) class_create(THIS_MODULE, name) -#endif - -// # define CLASS_CREATE(name) class_create(THIS_MODULE, name) - - -#define DEVICE_NAME "pcie_hotplug" -#define CLASS_NAME "pcie" -#define BUF_SIZE 16 - - -static struct pci_dev *get_pci_dev_by_bdf(const char* bdf) { - int domain, bus, slot, func; - struct pci_dev* pdev; - - if (sscanf(bdf, "%x:%x:%x.%x", &domain, &bus, &slot, &func) != 4) { - printk(KERN_ERR "Invalid BDF format\n"); - return NULL; - } - - pdev = pci_get_domain_bus_and_slot(domain, bus, PCI_DEVFN(slot, func)); - if (!pdev) { - printk(KERN_ERR "Cannot find PCI device\n"); - return NULL; - } - - return pdev; -} - -static struct pci_dev *get_next_function_pci_dev(const char* bdf) { - int domain, bus, slot, func; - char new_bdf[16]; - struct pci_dev* pdev; - - if (sscanf(bdf, "%x:%x:%x.%x", &domain, &bus, &slot, &func) != 4) { - printk(KERN_ERR "Invalid BDF format\n"); - return NULL; - } - - // Increment the function number - func += 1; - - // Construct the new BDF string - snprintf(new_bdf, sizeof(new_bdf), "%04x:%02x:%02x.%x", domain, bus, slot, func); - - // Get the PCI device with the new BDF - pdev = get_pci_dev_by_bdf(new_bdf); - if (!pdev) { - printk(KERN_ERR "Cannot find PCI device with BDF %s\n", new_bdf); - return NULL; - } - - return pdev; -} - -static void toggle_sbr(struct pcie_hotplug_device *dev) -{ - struct pci_dev *ep = NULL, *bridge = NULL; - struct pci_bus *root; - int domain, bus, slot, func; - u16 ctrl; - unsigned long t0 = jiffies; - - /* configurable delays to match userspace; provide sane defaults */ -#ifndef HOT_RESET_GPIO_SET_DELAY_MS -# define HOT_RESET_GPIO_SET_DELAY_MS 20 -#endif -#ifndef HOT_RESET_SBR_SET_DELAY_MS -# define HOT_RESET_SBR_SET_DELAY_MS 2 -#endif -#ifndef HOT_RESET_RESCAN_DELAY_MS -# define HOT_RESET_RESCAN_DELAY_MS 300 -#endif - - printk(KERN_INFO "toggle_sbr: ENTER dev=%p bdf=%s (t0=%lu)\n", - dev, dev ? dev->bdf : "(null)", t0); - - if (!dev || !dev->bdf) { - printk(KERN_ERR "toggle_sbr: invalid device or BDF (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - return; - } - - if (sscanf(dev->bdf, "%x:%x:%x.%x", &domain, &bus, &slot, &func) != 4) { - printk(KERN_ERR "toggle_sbr: invalid BDF format: %s (dt=%ums)\n", - dev->bdf, jiffies_to_msecs(jiffies - t0)); - return; - } - printk(KERN_INFO "toggle_sbr: parsed BDF dom=%04x bus=%02x slot=%02x func=%x (dt=%ums)\n", - domain, bus, slot, func, jiffies_to_msecs(jiffies - t0)); - - /* Resolve EP if present (may already be gone) */ - printk(KERN_INFO "toggle_sbr: resolving EP @ %s (dt=%ums)\n", - dev->bdf, jiffies_to_msecs(jiffies - t0)); - ep = pci_get_domain_bus_and_slot(domain, bus, PCI_DEVFN(slot, func)); - - /* Resolve the *immediate upstream bridge* (same as the sysfs "port") */ - if (ep) { - printk(KERN_INFO "toggle_sbr: EP PRESENT %04x:%02x:%02x.%x ven=%04x dev=%04x class=0x%06x (dt=%ums)\n", - pci_domain_nr(ep->bus), ep->bus->number, - PCI_SLOT(ep->devfn), PCI_FUNC(ep->devfn), - ep->vendor, ep->device, ep->class, - jiffies_to_msecs(jiffies - t0)); - { - struct pci_dev *up = pci_upstream_bridge(ep); - if (up) { - bridge = pci_dev_get(up); - printk(KERN_INFO "toggle_sbr: upstream bridge via pci_upstream_bridge(): %04x:%02x:%02x.%x (dt=%ums)\n", - pci_domain_nr(bridge->bus), bridge->bus->number, - PCI_SLOT(bridge->devfn), PCI_FUNC(bridge->devfn), - jiffies_to_msecs(jiffies - t0)); - } else { - printk(KERN_INFO "toggle_sbr: pci_upstream_bridge() returned NULL (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - } - } - } else { - printk(KERN_INFO "toggle_sbr: EP ABSENT at %s (dt=%ums)\n", - dev->bdf, jiffies_to_msecs(jiffies - t0)); - } - - /* Fallback without walking global device list: use bus->self */ - if (!bridge) { - struct pci_bus *ep_bus; - - printk(KERN_INFO "toggle_sbr: fallback via pci_find_bus(dom=%04x,bus=%02x) (dt=%ums)\n", - domain, bus, jiffies_to_msecs(jiffies - t0)); - - ep_bus = pci_find_bus(domain, bus); - if (!ep_bus) { - printk(KERN_ERR "toggle_sbr: pci_find_bus() returned NULL for %04x:%02x (dt=%ums)\n", - domain, bus, jiffies_to_msecs(jiffies - t0)); - } else if (!ep_bus->self) { - printk(KERN_ERR "toggle_sbr: bus %02x has no upstream bridge (root bus?) (dt=%ums)\n", - bus, jiffies_to_msecs(jiffies - t0)); - } else { - bridge = pci_dev_get(ep_bus->self); - printk(KERN_INFO "toggle_sbr: found bridge via bus->self: %04x:%02x:%02x.%x (sec=%02x) (dt=%ums)\n", - pci_domain_nr(bridge->bus), bridge->bus->number, - PCI_SLOT(bridge->devfn), PCI_FUNC(bridge->devfn), - bridge->subordinate ? bridge->subordinate->number : 0xff, - jiffies_to_msecs(jiffies - t0)); - } - } - - if (!bridge) { - if (ep) pci_dev_put(ep); - printk(KERN_ERR "toggle_sbr: NO upstream bridge for %s — abort (dt=%ums)\n", - dev->bdf, jiffies_to_msecs(jiffies - t0)); - return; - } - - printk(KERN_INFO "toggle_sbr: using bridge %04x:%02x:%02x.%x (secondary=%02x) (dt=%ums)\n", - pci_domain_nr(bridge->bus), bridge->bus->number, - PCI_SLOT(bridge->devfn), PCI_FUNC(bridge->devfn), - bridge->subordinate ? bridge->subordinate->number : 0xff, - jiffies_to_msecs(jiffies - t0)); - - /* 1) REMOVE the endpoint under the PCI remove/rescan lock — like sysfs */ - if (ep) { - printk(KERN_INFO "toggle_sbr: acquiring rescan/remove lock to delete EP (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_lock_rescan_remove(); - - printk(KERN_INFO "toggle_sbr: clearing bus master on EP (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_clear_master(ep); - - printk(KERN_INFO "toggle_sbr: calling pci_stop_and_remove_bus_device_locked(ep) (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_stop_and_remove_bus_device_locked(ep); - - printk(KERN_INFO "toggle_sbr: releasing rescan/remove lock after EP removal (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_unlock_rescan_remove(); - - printk(KERN_INFO "toggle_sbr: EP removed; dropping EP ref (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_dev_put(ep); - ep = NULL; - } else { - printk(KERN_INFO "toggle_sbr: EP already absent — skipping removal (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - } - - /* (userspace did a small guard delay after GPIO poke) */ - printk(KERN_INFO "toggle_sbr: sleeping %d ms before SBR (dt=%ums)\n", - HOT_RESET_GPIO_SET_DELAY_MS, jiffies_to_msecs(jiffies - t0)); - msleep(HOT_RESET_GPIO_SET_DELAY_MS); - printk(KERN_INFO "toggle_sbr: woke from pre-SBR sleep (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - - /* 2) PULSE SBR on the bridge — *NO PCI LOCK HELD* (matches sysfs fd write) */ -#if IS_ENABLED(CONFIG_PCI) - printk(KERN_INFO "toggle_sbr: attempting pci_bridge_secondary_bus_reset() (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - if (!pci_bridge_secondary_bus_reset(bridge)) { - printk(KERN_INFO "toggle_sbr: pci_bridge_secondary_bus_reset() OK; settle sleep %d ms (dt=%ums)\n", - HOT_RESET_SBR_SET_DELAY_MS + HOT_RESET_RESCAN_DELAY_MS, - jiffies_to_msecs(jiffies - t0)); - msleep(HOT_RESET_SBR_SET_DELAY_MS + HOT_RESET_RESCAN_DELAY_MS); - } else -#endif - { - u16 ctrl_before = 0, ctrl_after = 0; - printk(KERN_INFO "toggle_sbr: manual SBR path (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &ctrl_before); - printk(KERN_INFO "toggle_sbr: BRIDGE_CONTROL before=0x%04x (dt=%ums)\n", - ctrl_before, jiffies_to_msecs(jiffies - t0)); - - ctrl = ctrl_before | PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, ctrl); - printk(KERN_INFO "toggle_sbr: set BUS_RESET; sleep %d ms (dt=%ums)\n", - HOT_RESET_SBR_SET_DELAY_MS, jiffies_to_msecs(jiffies - t0)); - msleep(HOT_RESET_SBR_SET_DELAY_MS); - - ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, ctrl); - pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &ctrl_after); - printk(KERN_INFO "toggle_sbr: cleared BUS_RESET; BRIDGE_CONTROL after=0x%04x; settle %d ms (dt=%ums)\n", - ctrl_after, HOT_RESET_RESCAN_DELAY_MS, - jiffies_to_msecs(jiffies - t0)); - msleep(HOT_RESET_RESCAN_DELAY_MS); - } - - printk(KERN_INFO "toggle_sbr: extra settle sleep 5000 ms (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - msleep(5000); - - /* 3) GLOBAL RESCAN under the PCI lock — exactly like /sys/bus/pci/rescan */ - printk(KERN_INFO "toggle_sbr: BEGIN global rescan (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - pci_lock_rescan_remove(); - list_for_each_entry(root, &pci_root_buses, node) { - printk(KERN_INFO "toggle_sbr: pci_rescan_bus(root=%02x) (dt=%ums)\n", - root->number, jiffies_to_msecs(jiffies - t0)); - pci_rescan_bus(root); - } - pci_unlock_rescan_remove(); - printk(KERN_INFO "toggle_sbr: END global rescan (dt=%ums)\n", - jiffies_to_msecs(jiffies - t0)); - - pci_dev_put(bridge); - printk(KERN_INFO "toggle_sbr: EXIT (total=%ums)\n", - jiffies_to_msecs(jiffies - t0)); -} - - - -static void handle_rescan(void) { - struct pci_bus* bus; - printk(KERN_INFO "Rescanning PCIe bus\n"); - list_for_each_entry(bus, &pci_root_buses, node) { - pci_rescan_bus(bus); - } -} - -static void handle_pcie_remove(struct pcie_hotplug_device *dev) { - struct pci_dev* device_dev = NULL; - if(dev->bdf) { - device_dev = get_pci_dev_by_bdf(dev->bdf); - if (!device_dev) { - return; - } - } - - if(device_dev) { - printk(KERN_INFO "Removing PCIe device: %s\n", dev->bdf); - pci_stop_and_remove_bus_device(device_dev); - } -} - -static void handle_pcie_hotplug(struct pcie_hotplug_device *dev) { - struct pci_dev* rootport_dev = NULL; - struct pci_dev* device_dev = NULL; - struct pci_bus* bus; - if(dev->bdf) { - device_dev = get_next_function_pci_dev(dev->bdf); - if(!device_dev) { - return; - } - } - - if(device_dev) { - printk(KERN_INFO "Removing PCIe device: %s\n", dev->bdf); - pci_stop_and_remove_bus_device(device_dev); - } - - rootport_dev = pcie_find_root_port(device_dev); - - if(!rootport_dev) { - return; - } else { - printk(KERN_INFO "Root port: %04x:%02x:%02x.%x\n", - pci_domain_nr(rootport_dev->bus), - rootport_dev->bus->number, - PCI_SLOT(rootport_dev->devfn), - PCI_FUNC(rootport_dev->devfn)); - } - bus = rootport_dev->subordinate; - - if(bus) { - printk(KERN_INFO "Rescanning PCIe bus\n"); - pci_rescan_bus(bus); - } - -} - -static int get_bdfs(const char *device_bdf, char *rootport_bdf) { - struct pci_dev* device_dev = NULL; - struct pci_dev* rootport_dev = NULL; - - if(device_bdf) { - device_dev = get_pci_dev_by_bdf(device_bdf); - if (!device_dev) { - return -EINVAL; - } - } - - rootport_dev = pcie_find_root_port(device_dev); - snprintf(rootport_bdf, 32, "%04x:%02x:%02x.%x", - pci_domain_nr(rootport_dev->bus), - rootport_dev->bus->number, - PCI_SLOT(rootport_dev->devfn), - PCI_FUNC(rootport_dev->devfn)); - - return 0; -} - -static int pcie_hotplug_open(struct inode *inode, struct file *file) { - struct pcie_hotplug_device *dev; - - dev = container_of(inode->i_cdev, struct pcie_hotplug_device, cdev); - file->private_data = dev; - - return 0; -} - -static int pcie_hotplug_release(struct inode *inode, struct file *file) { - return 0; -} - -static ssize_t pcie_hotplug_write(struct file* file, const char __user* buffer, size_t len, loff_t* offset) { - char cmd[16]; - struct pcie_hotplug_device *dev = file->private_data; - - if(len > 15) { - return -EINVAL; - } - - if(copy_from_user(cmd, buffer, len)) { - return -EFAULT; - } - - cmd[len] = '\0'; - printk(KERN_INFO "Received command: %s\n", cmd); - - if(strncmp(cmd, "rescan", 6) == 0) { - handle_rescan(); - } else if(strncmp(cmd, "remove", 6) == 0) { - handle_pcie_remove(dev); - } else if(strncmp(cmd, "toggle_sbr", 10) == 0) { - toggle_sbr(dev); - } else if(strncmp(cmd, "hotplug", 7) == 0) { - handle_pcie_hotplug(dev); - } else { - printk(KERN_WARNING "Invalid command\n"); - } - - return len; -} - -static struct file_operations fops = { - .owner = THIS_MODULE, - .open = pcie_hotplug_open, - .release = pcie_hotplug_release, - .write = pcie_hotplug_write, -}; - -static void discover_and_add_devices(void) { - struct pci_dev *pdev = NULL; - char bdf[16]; - const struct pci_device_id *id; - - for_each_pci_dev(pdev) { - for (id = pcie_hotplug_ids; id->vendor != 0; id++) { - if (pdev->vendor == id->vendor && pdev->device == id->device && PCI_FUNC(pdev->devfn) == 0) { - snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", - pci_domain_nr(pdev->bus), - pdev->bus->number, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn)); - add_device(bdf); - } - } - } -} - -static void add_device(const char *bdf) { - struct pcie_hotplug_device *dev; - int ret; - - dev = kzalloc(sizeof(*dev), GFP_KERNEL); - if (!dev) { - return; - } - - dev->bdf = kstrdup(bdf, GFP_KERNEL); - if (!dev->bdf) { - kfree(dev); - return; - } - - // Find root port for the device - ret = get_bdfs(dev->bdf, dev->rootport_bdf); - if (ret < 0) { - kfree(dev->bdf); - kfree(dev); - return; - } - - ret = alloc_chrdev_region(&dev->devt, 0, 1, DEVICE_NAME); - if (ret < 0) { - kfree(dev->bdf); - kfree(dev); - return; - } - - cdev_init(&dev->cdev, &fops); - dev->cdev.owner = THIS_MODULE; - ret = cdev_add(&dev->cdev, dev->devt, 1); - if (ret < 0) { - unregister_chrdev_region(dev->devt, 1); - kfree(dev->bdf); - kfree(dev); - return; - } - - device_create(pcie_hotplug_class, NULL, dev->devt, NULL, "pcie_hotplug_%s", dev->bdf); - - list_add(&dev->list, &device_list); - device_count++; - - printk(KERN_INFO "Added PCIe hotplug device: %s, root port: %s\n", dev->bdf, dev->rootport_bdf); -} - -static int __init pcie_hotplug_init(void) { - - // Register character device - major_number = register_chrdev(0, DEVICE_NAME, &fops); - if (major_number < 0) { - printk(KERN_ERR "Failed to register chrdev\n"); - return major_number; - } - - // Initialize class - pcie_hotplug_class = CLASS_CREATE(CLASS_NAME); - if (IS_ERR(pcie_hotplug_class)) { - unregister_chrdev(major_number, DEVICE_NAME); - printk(KERN_ERR "Failed to create class\n"); - return PTR_ERR(pcie_hotplug_class); - } - - // Discover and add devices with the specified vendor ID - discover_and_add_devices(); - - printk(KERN_INFO "PCIe hotplug initialized\n"); - return 0; -} - -static void __exit pcie_hotplug_exit(void) { - struct pcie_hotplug_device *dev, *tmp; - - list_for_each_entry_safe(dev, tmp, &device_list, list) { - device_destroy(pcie_hotplug_class, dev->devt); - cdev_del(&dev->cdev); - unregister_chrdev_region(dev->devt, 1); - kfree(dev->bdf); - kfree(dev); - } - - class_unregister(pcie_hotplug_class); - class_destroy(pcie_hotplug_class); - unregister_chrdev(major_number, DEVICE_NAME); - printk(KERN_INFO "pcie_hotplug module unloaded\n"); -} - -module_init(pcie_hotplug_init); -module_exit(pcie_hotplug_exit); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("AMD Inc."); -MODULE_DESCRIPTION("PCIe hotplug module"); -MODULE_VERSION("1.0"); \ No newline at end of file diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h b/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h deleted file mode 100644 index 11285a71..00000000 --- a/submodules/pcie-hotplug-drv/driver/pcie_hotplug.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. - * This program is free software; you can redistribute it and/or modify it under the terms of the - * GNU General Public License as published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without - * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with this program; if - * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#ifndef PCIE_HOTPLUG_H -#define PCIE_HOTPLUG_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pcie_hotplug_ids.h" - - -static int major_number; -static struct class* pcie_hotplug_class = NULL; - -struct pcie_hotplug_device { - char *bdf; - char rootport_bdf[32]; - dev_t devt; - struct cdev cdev; - struct list_head list; -}; - - -static LIST_HEAD(device_list); -static int device_count = 0; - - /** - * Helper Functions - */ - - /** - * get_pci_dev_by_bdf - Get PCI device by BDF - * @bdf: BDF string - * - * Returns the PCI device corresponding to the given BDF. - */ - static struct pci_dev *get_pci_dev_by_bdf(const char* bdf); - - /** - * get_bdfs - Get BDFs for the device and root port - * - * Returns 0 on success, negative error code on failure. - */ - static int get_bdfs(const char *device_bdf, char *rootport_bdf); - - /** - * get_next_function_pci_dev - Get next function PCIe device - * Returns the PCIe device corresponding to the given BDF. - */ - static struct pci_dev *get_next_function_pci_dev(const char* bdf); - - /** - * toggle_sbr - Toggle Secondary Bus Reset (SBR) - * - * Toggles the SBR for the given device. - */ - static void toggle_sbr(struct pcie_hotplug_device *dev); - - /** - * handle_rescan - Handle PCIe bus rescan - * - * Rescans the PCIe bus. - */ - static void handle_rescan(void); - - /** - * handle_pcie_remove - Handle PCIe device removal - * - * Removes the given PCIe device. - */ - static void handle_pcie_remove(struct pcie_hotplug_device *dev); - - /** - * handle_pcie_hotplug - Handle PCIe hotplug - * - * Handles the hotplug operation for the given device. - */ - static void handle_pcie_hotplug(struct pcie_hotplug_device *dev); - - /** - * Kernel Specific Functions - */ - - /** - * pcie_hotplug_write - Write handler for the character device - * @file: File structure - * @buffer: User buffer - * @len: Length of the buffer - * @offset: Offset in the file - * - * Handles write operations to the character device. - * - * Returns the number of bytes written on success, negative error code on failure. - */ - static ssize_t pcie_hotplug_write(struct file* file, const char __user* buffer, size_t len, loff_t* offset); - - // /** - // * @brief Store function for adding a new PCIe hotplug device. - // * - // * This function is called when a new device BDF is written to the sysfs entry. - // * It allocates and initializes a new `pcie_hotplug_device` structure, finds the - // * root port for the device, allocates a character device region, and creates - // * the character device. - // * - // * @param kobj Pointer to the kobject. - // * @param attr Pointer to the kobj_attribute. - // * @param buf Buffer containing the BDF string. - // * @param count Number of bytes in the buffer. - // * @return Number of bytes processed on success, negative error code on failure. - // */ - // static ssize_t add_device_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count); - - static void add_device(const char *bdf); - - /** - * pcie_hotplug_init - Module initialization function - * - * Initializes the PCIe hotplug module. - * - * Returns 0 on success, negative error code on failure. - */ - static int __init pcie_hotplug_init(void); - - /** - * pcie_hotplug_exit - Module exit function - * - * Cleans up the PCIe hotplug module. - */ - static void __exit pcie_hotplug_exit(void); - -#endif // PCIE_HOTPLUG_H \ No newline at end of file diff --git a/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h b/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h deleted file mode 100644 index 952d3b43..00000000 --- a/submodules/pcie-hotplug-drv/driver/pcie_hotplug_ids.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. - * This program is free software; you can redistribute it and/or modify it under the terms of the - * GNU General Public License as published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without - * even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with this program; if - * not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#ifndef PCIE_HOTPLUG_IDS -#define PCIE_HOTPLUG_IDS - -#include - -/** - * @file pcie_hotplug_ids.h - * @brief Defines a list of PCI device IDs for the PCIe hotplug driver. - * - * This header file contains a list of PCI device IDs that the PCIe hotplug driver - * will recognize and handle. The list is defined using the `pci_device_id` structure - * and the `PCI_DEVICE` macro. - */ - -/** - * @brief List of PCI device IDs supported by the PCIe hotplug driver. - * - * This list contains the vendor ID and device ID pairs for the PCI devices that - * the PCIe hotplug driver will recognize and handle. The list is terminated by - * an entry with all fields set to 0. - */ -static const struct pci_device_id pcie_hotplug_ids[] = { - {PCI_DEVICE(0x10ee, 0x50b4)}, /**< Xilinx V80 PCIe device */ - { - 0, - } /**< End of list */ -}; - -#endif // PCIE_HOTPLUG_IDS \ No newline at end of file diff --git a/submodules/v80-vitis-flow/.gitignore b/submodules/v80-vitis-flow/.gitignore deleted file mode 100644 index e9f89332..00000000 --- a/submodules/v80-vitis-flow/.gitignore +++ /dev/null @@ -1,55 +0,0 @@ -# Ignore build directories -**/build/ -/cmake-build-debug/ -/cmake-build-release/ -**/build_* -# Ignore CMake generated files -CMakeFiles/ -CMakeCache.txt -cmake_install.cmake -#Makefile - -# Ignore compiled dynamic libraries -*.dll -*.so -*.dylib - -# Ignore compiled static libraries -*.lib -*.a - -# Ignore object files -*.o -*.obj - -# Ignore executable files -*.exe -*.out -*.app - -# Ignore logs and databases -*.jou -*.log -*.sql -*.sqlite - -# Ignore system files -.DS_Store -Thumbs.db - -# Ignore IDE specific files -.vscode/ -.idea/ -*.iml - -# Ignore test binaries -/tests/*.exe -/tests/*.out -/tests/*.o -/tests/*.obj - -# Ignore user-specific files -*.swp -*~ -*.Xil -!build_all.sh \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp b/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp deleted file mode 100644 index cc8d07a0..00000000 --- a/submodules/v80-vitis-flow/include/arg_parser/arg_parser.hpp +++ /dev/null @@ -1,188 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef ARG_PARSER_HPP -#define ARG_PARSER_HPP - -#include -#include -#include -#include -#include -#include - -#include "kernel.hpp" -#include "logger.hpp" -#include "xml_parser.hpp" - -/** - * @brief Structure representing the Tcl scripts to inject into the Vivado build scripts. - */ -struct TclInjections { - std::vector scriptsPreSynth; ///< The name of the scripts to inject before the synthesis phase - std::vector scriptsPostBuild; ///< The name of the scripts to inject after the build phase -}; - -/** - * @brief Structure representing a connection element within a hardware design. - */ -struct ConnectionElement { - std::string kernelName; ///< The name of the kernel - std::string interfaceName; ///< The name of the interface on the kernel -}; - -/** - * @brief Structure representing a connection between two elements in a hardware design. - */ -struct Connection { - ConnectionElement src; ///< The source connection element - ConnectionElement dst; ///< The destination connection element -}; - -/** - * @brief Enum class representing the direction of a streaming interface. - */ -enum class StreamDirection { - HOST_TO_DEVICE, ///< Stream from host to device - DEVICE_TO_HOST ///< Stream from device to host -}; - -/** - * @brief Structure representing a streaming connection in a hardware design. - * - * Streaming connections are used for high-throughput data transfer between - * the host and device or between kernels. - */ -struct StreamingConnection { - std::string kernelName; ///< The name of the kernel - uint32_t qid; ///< Queue ID for the streaming connection - std::string interfaceName; ///< The name of the interface on the kernel - StreamDirection direction; ///< Direction of the stream -}; - -/** - * @brief Enum class representing the platform type for execution. - */ -enum class Platform { - EMULATOR, ///< Software emulation platform - SIMULATOR, ///< Hardware simulation platform - HARDWARE ///< Actual hardware execution platform -}; - -/** - * @brief Class for parsing command line arguments and configuration files. - * - * This class parses command line arguments and configuration files to extract - * information about kernels, connections, and platform settings for hardware - * acceleration designs. - */ -class ArgParser { - public: - /** - * @brief Path to the XML configuration file. - */ - static const std::string XML_PATH; - - /** - * @brief Constructor for the ArgParser. - * @param argc Number of command line arguments. - * @param argv Array of command line arguments. - */ - ArgParser(int argc, char** argv); - - /** - * @brief Gets the list of kernels defined in the configuration. - * @return Vector of kernel objects. - */ - std::vector getKernels(); - - /** - * @brief Gets the path to the configuration file. - * @return String containing the path to the configuration file. - */ - std::string getConfigFile() const; - - /** - * @brief Gets the mapping between kernel names and their corresponding entity names. - * @return Map from kernel names to entity names. - */ - std::map getKernelEntities() const; - - /** - * @brief Gets the list of connections defined in the configuration. - * @return Vector of connection objects. - */ - std::vector getConnections() const; - - /** - * @brief Gets the clock frequency in Hertz. - * @return Clock frequency in Hertz. - */ - uint64_t getFreqHz() const; - - /** - * @brief Checks if the design is segmented. - * @return True if the design is segmented, false otherwise. - */ - bool isSegmented() const; - - /** - * @brief Gets the target platform. - * @return The target platform (Emulator, Simulator, or Hardware). - */ - Platform getPlatform(); - - /** - * @brief Gets the list of kernel file paths. - * @return Vector of paths to kernel files. - */ - std::vector getKernelPaths(); - - /** - * @brief Gets the set of Tcl files to inject. - * @return Structure representing the set of Tcl files to inject. - */ - const TclInjections &getTclInjections() const; - - private: - std::vector kernelPaths; ///< Paths to kernel files - std::string configFile; ///< Path to the configuration file - std::vector kernels; ///< List of kernels - std::map - kernelEntities; ///< Mapping from kernel names to entity names - std::vector connections; ///< List of connections - uint64_t freqHz; ///< Clock frequency in Hz - bool segmented; ///< Flag indicating if the design is segmented - Platform platform; ///< Target platform - TclInjections tclInjections; ///< Tcl files to inject - - /** - * @brief Parses kernel information from configuration files. - * @return Vector of parsed kernel objects. - */ - std::vector parseKernels(); - - /** - * @brief Parses the configuration file. - */ - void parseConfig(); -}; - -#endif // ARG_PARSER_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp b/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp deleted file mode 100644 index 616bcda7..00000000 --- a/submodules/v80-vitis-flow/include/bd_builder/bd_builder.hpp +++ /dev/null @@ -1,358 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#pragma once - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arg_parser.hpp" -#include "kernel.hpp" -#include "logger.hpp" -#include "system_map.hpp" - -/** - * @brief Class for building Vivado Block Design TCL scripts. - * - * This class generates TCL scripts that create and configure Vivado block designs - * with hardware kernels and their interconnections. It supports both hardware and - * simulation platforms, with appropriate settings for each. - */ -class BdBuilder { - static bool hasAximmIntf; ///< Flag indicating if any kernel has AXI-MM interface - std::string KERNEL_NAME = "xilinx.com:hls:"; ///< Base kernel name prefix for IP cores - std::string ALL_REGEX_CHAR = ":*"; ///< Regex characters for wildcard matching - std::string BASE_BD_TCL_PATH = "../resources/"; ///< Path to base TCL scripts - std::string INPUT_FILE_HW = - "../resources/base_bd.tcl"; ///< Base TCL file for hardware platform - std::string INPUT_FILE_SIM = - "../resources/sim_prj.tcl"; ///< Base TCL file for simulation platform - std::string PRE_OUTPUT_FILE = "run_pre.tcl"; ///< Output pre TCL file name - std::string POST_OUTPUT_FILE = "run_post.tcl"; ///< Output post TCL file name - std::string NOC_SOLUTION = "../resources/noc_sol_compute.ncr"; ///< NoC solution file path - std::string NOC0_ADDR_STR = - " -target_address_space [get_bd_addr_spaces cips/CPM_PCIE_NOC_0] [get_bd_addr_segs " - "base_logic/"; ///< NoC 0 address space TCL string - std::string NOC1_ADDR_STR = - " -target_address_space [get_bd_addr_spaces cips/CPM_PCIE_NOC_1] [get_bd_addr_segs " - "base_logic/"; ///< NoC 1 address space TCL string - static constexpr uint64_t BASE_ADDRESS = - 0x20100000000; ///< Base address for kernel memory mapping - static constexpr uint64_t KERNEL_MEMORY_MAP_SIZE = - 0x00001000; ///< Size of each kernel's memory map - static constexpr uint16_t MAX_ALLOCABLE_BW_HBM_PER_CHANNEL = - 400; ///< Maximum allocable bandwidth for HBM per channel in MBps - std::vector kernels; ///< List of kernels to include in the design - std::vector streamConnections; ///< List of streaming connections between kernels - uint64_t targetClockFreq; ///< Target clock frequency in Hz - SystemMap systemMap; ///< System memory map for the design - bool segmented; ///< Flag indicating if design is segmented - Platform platform; ///< Target platform (hardware, simulation, emulation) - TclInjections tclInjections; ///< Set of Tcl files to inject - - /** - * @brief Generate source instruction. - * @param path The path to source. - * @return The source instruction. - */ - std::string generateSourceInstruction(const std::string& path) const; - - public: - /** - * @brief Constructor for BdBuilder. - * @param kernels Vector of kernel objects to include in the design. - * @param connections Vector of connection objects defining inter-kernel connections. - */ - BdBuilder(std::vector kernels, std::vector connections); - - /** - * @brief Extended constructor for BdBuilder with additional parameters. - * @param kernels Vector of kernel objects to include in the design. - * @param connections Vector of connection objects defining inter-kernel connections. - * @param targetClockFreq Target clock frequency in Hz. - * @param segmented Flag indicating if design is segmented. - * @param platform Target platform (hardware, simulation, emulation). - * @param tclInjections Set of Tcl files to inject. - */ - BdBuilder(std::vector kernels, std::vector connections, - double targetClockFreq, bool segmented, Platform platform, - TclInjections tclInjections); - - /** - * @brief Builds the block design by generating TCL commands. - * - * This is the main function that orchestrates the creation of the entire block design. - * It calls various helper functions to configure different aspects of the design. - */ - void buildBlockDesign(); - - /** - * @brief Generates TCL commands to connect a kernel interface. - * @param krnl_name Name of the kernel. - * @param intf Interface to connect. - * @param idx Index of the kernel. - * @return String containing TCL commands for interface connection. - */ - std::string connectInterface(std::string krnl_name, Interface intf, int idx); - - /** - * @brief Generates TCL commands to configure the number of AXI-Lite slaves. - * @return String containing TCL commands for AXI-Lite slave configuration. - */ - std::string configNumberOfAXILiteSlaves(); - - /** - * @brief Generates TCL commands to create an IP for a kernel. - * @param idx Index of the kernel. - * @return String containing TCL commands for IP creation. - */ - std::string createIp(int idx); - - /** - * @brief Generates TCL commands for Quality of Service (QoS) settings. - * @param slave_offset Offset for slave addressing. - * @param bw Bandwidth allocation. - * @return String containing TCL commands for QoS configuration. - */ - std::string genQoS(int slave_offset, int bw); - - /** - * @brief Generates TCL commands to assign an address to a slave interface. - * @param krnl_name Name of the kernel. - * @param idx Index of the kernel. - * @param intf Interface to assign address to. - * @param base_addr Base address for the interface. - * @return String containing TCL commands for address assignment. - */ - std::string assignSlaveAddress(std::string krnl_name, int idx, Interface intf, - uint64_t base_addr); - - /** - * @brief Generates TCL commands to configure the number of AXI-Full slaves. - * @return String containing TCL commands for AXI-Full slave configuration. - */ - std::string configNumberOfAXIFullSlaves(); - - /** - * @brief Generates TCL commands to connect AXI-Stream interfaces. - * @param krnl_name Name of the kernel. - * @return String containing TCL commands for AXI-Stream connections. - */ - std::string connectAxis(std::string krnl_name); - - /** - * @brief Calculates the required bandwidth for the design. - * @return Required bandwidth in MBps. - */ - uint16_t calculateBw(); - - /** - * @brief Gets the number of AXI-MM interfaces in the design. - * @return Number of AXI-MM interfaces. - */ - uint8_t getNumberOfAxiMmInterfaces(); - - /** - * @brief Gets the number of AXI-Lite interfaces in the design. - * @return Number of AXI-Lite interfaces. - */ - uint8_t getNumberOfAxiLiteInterfaces(); - - /** - * @brief Generates TCL commands to configure the user clock. - * @return String containing TCL commands for user clock configuration. - */ - std::string configureUserClock(); - - /** - * @brief Generates TCL commands to connect the clock wizard. - * @return String containing TCL commands for clock wizard connections. - */ - std::string connectClkWiz(); - - /** - * @brief Exports the system memory map to a file. - */ - void exportSystemMap(); - - /** - * @brief Generates TCL commands to set up the clock wizard. - * @return String containing TCL commands for clock wizard setup. - */ - std::string setupClkWiz(); - - /** - * @brief Generates TCL commands to set up the system reset. - * @return String containing TCL commands for system reset setup. - */ - std::string setupSysRst(); - - /** - * @brief Generates TCL commands for the footer section of the script. - * @return String containing TCL commands for the footer. - */ - std::string printFooter(); - - /** - * @brief Generates TCL commands to configure HBM (High-Bandwidth Memory). - * @return String containing TCL commands for HBM configuration. - */ - std::string setHBMConfig(); - - /** - * @brief Generates TCL commands to assign address to the clock wizard. - * @return String containing TCL commands for clock wizard address assignment. - */ - std::string assignClkWizAddr(); - - /** - * @brief Generates TCL commands for segmented design configuration. - * @return String containing TCL commands for segmented design setup. - */ - std::string setSegmented(); - - /** - * @brief Generates TCL commands to add an AXI crossbar. - * @param numSlaves Number of slave interfaces. - * @return String containing TCL commands for crossbar creation. - */ - std::string addXbar(uint8_t numSlaves); - - /** - * @brief Generates TCL commands to connect the crossbar to NoC. - * @return String containing TCL commands for crossbar-NoC connections. - */ - std::string connectXbarToNoC(); - - /** - * @brief Generates TCL commands for QDMA streaming setup. - * @return String containing TCL commands for QDMA streaming. - */ - std::string setupQdmaStreaming(); - - /** - * @brief Generates TCL commands to add Host-to-Card AXI-Stream router. - * @return String containing TCL commands for H2C router. - */ - std::string addH2CAxisRouter(); - - /** - * @brief Generates TCL commands to add Card-to-Host AXI-Stream router. - * @return String containing TCL commands for C2H router. - */ - std::string addC2HAxisRouter(); - - /** - * @brief Generates TCL commands to connect QDMA H2C to router. - * @return String containing TCL commands for QDMA H2C connections. - */ - std::string connectQdmaH2CToRouter(); - - /** - * @brief Generates TCL commands to connect QDMA C2H to router. - * @return String containing TCL commands for QDMA C2H connections. - */ - std::string connectQdmaC2HToRouter(); - - /** - * @brief Generates TCL commands to add QDMA logic. - * @return String containing TCL commands for QDMA logic addition. - */ - std::string addQdmaLogic(); - - /** - * @brief Generates TCL commands to connect QDMA logic. - * @return String containing TCL commands for QDMA logic connections. - */ - std::string connectQdmaLogic(); - - /** - * @brief Generates TCL commands to assign GPIO address for QDMA logic. - * @return String containing TCL commands for QDMA logic GPIO address. - */ - std::string assignQdmaLogicGpioAddr(); - - /** - * @brief Generates TCL commands to add Host-to-Card FIFO. - * @return String containing TCL commands for H2C FIFO creation. - */ - std::string addH2CFifo(); - - /** - * @brief Generates TCL commands to configure AXI-Lite slaves for simulation platform. - * @return String containing TCL commands for simulation AXI-Lite slaves. - */ - std::string configNumberOfAXILiteSlavesSim(); - - /** - * @brief Generates TCL commands to configure AXI-Full slaves for simulation platform. - * @return String containing TCL commands for simulation AXI-Full slaves. - */ - std::string configNumberOfAXIFullSlavesSim(); - - /** - * @brief Generates TCL commands to connect interfaces in simulation platform. - * @param krnl_name Name of the kernel. - * @param intf Interface to connect. - * @param idx Index of the kernel. - * @return String containing TCL commands for simulation interface connections. - */ - std::string connectInterfaceSim(std::string krnl_name, Interface intf, int idx); - - /** - * @brief Generates TCL commands to create IPs for simulation platform. - * @param idx Index of the kernel. - * @return String containing TCL commands for simulation IP creation. - */ - std::string createIpSim(int idx); - - /** - * @brief Generates TCL commands to assign slave addresses for simulation platform. - * @param krnl_name Name of the kernel. - * @param idx Index of the kernel. - * @param intf Interface to assign address to. - * @param base_addr Base address for the interface. - * @return String containing TCL commands for simulation address assignment. - */ - std::string assignSlaveAddressSim(std::string krnl_name, int idx, Interface intf, - uint64_t base_addr); - - /** - * @brief Generates TCL commands to connect AXI-Stream in simulation platform. - * @param krnl_name Name of the kernel. - * @return String containing TCL commands for simulation AXI-Stream connections. - */ - std::string connectAxisSim(std::string krnl_name); - - /** - * @brief Generates TCL commands for the header of the run_pre.tcl script. - * @return String containing TCL commands for script header. - */ - std::string addRunPreHeader(); -}; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/bd_builder/map_entry.hpp b/submodules/v80-vitis-flow/include/bd_builder/map_entry.hpp deleted file mode 100644 index a2d10b8a..00000000 --- a/submodules/v80-vitis-flow/include/bd_builder/map_entry.hpp +++ /dev/null @@ -1,89 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef MAP_ENTRY_HPP -#define MAP_ENTRY_HPP - -#include -#include -#include -#include - -#include "register.hpp" - -/** - * @brief Class representing a memory map entry for a hardware component. - * - * This class stores information about a memory-mapped component in a hardware design, - * including its base address, address range, and register definitions. It is used - * to document the memory map of kernels and other components in the system. - */ -class MapEntry { - std::string name; ///< Name of the memory-mapped component - uint64_t baseAddress; ///< Base address of the component in the memory map - uint64_t range; ///< Size of the address range in bytes - std::vector registers; ///< List of registers within this component - - public: - /** - * @brief Default constructor for MapEntry. - */ - MapEntry() = default; - - /** - * @brief Constructor for MapEntry with initialization parameters. - * @param name Name of the memory-mapped component. - * @param base_addr Base address of the component in the system memory map. - * @param range Size of the address range in bytes. - */ - MapEntry(std::string name, uint64_t base_addr, uint64_t range); - - /** - * @brief Gets the name of the memory-mapped component. - * @return String containing the component name. - */ - std::string getName(); - - /** - * @brief Gets the base address of the component. - * @return Base address as a 64-bit unsigned integer. - */ - uint64_t getBaseAddr(); - - /** - * @brief Gets the size of the address range. - * @return Range size in bytes as a 64-bit unsigned integer. - */ - uint64_t getRange(); - - /** - * @brief Gets the list of registers within this component. - * @return Vector of Register objects defining the component's registers. - */ - std::vector getRegisters(); - - /** - * @brief Sets the list of registers for this component. - * @param registers Vector of Register objects to associate with this component. - */ - void setRegisters(std::vector registers); -}; - -#endif // MAP_ENTRY_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/bd_builder/register.hpp b/submodules/v80-vitis-flow/include/bd_builder/register.hpp deleted file mode 100644 index 5b7171d0..00000000 --- a/submodules/v80-vitis-flow/include/bd_builder/register.hpp +++ /dev/null @@ -1,130 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef REGISTER_HPP -#define REGISTER_HPP - -#include -#include -#include - -#include "logger.hpp" - -/** - * @brief Class representing a hardware register definition. - * - * This class stores information about a register within a memory-mapped component, - * including its name, offset within the component, bit width, access permissions, - * and a description of its functionality. - */ -class Register { - std::string registerName; ///< Name of the register - uint32_t offset; ///< Offset from the base address in bytes - uint32_t width; ///< Width of the register in bits - std::string rw; ///< Read/write permissions (e.g., "RW", "RO", "WO") - std::string description; ///< Description of the register's functionality - - public: - /** - * @brief Constructor for Register with initialization parameters. - * @param registerName Name of the register. - * @param offset Offset from the component's base address in bytes. - * @param width Width of the register in bits. - * @param rw Read/write permissions (e.g., "RW", "RO", "WO"). - * @param description Description of the register's functionality. - */ - Register(std::string registerName, uint32_t offset, uint32_t width, std::string rw, - std::string description); - - /** - * @brief Default constructor for Register. - */ - Register() = default; - - /** - * @brief Gets the name of the register. - * @return String containing the register name. - */ - std::string getRegisterName(); - - /** - * @brief Gets the offset of the register. - * @return Offset from the component's base address in bytes. - */ - uint32_t getOffset(); - - /** - * @brief Gets the width of the register. - * @return Width of the register in bits. - */ - uint32_t getWidth(); - - /** - * @brief Gets the read/write permissions of the register. - * @return String containing the access permissions (e.g., "RW", "RO", "WO"). - */ - std::string getRW(); - - /** - * @brief Gets the description of the register. - * @return String containing the register's functional description. - */ - std::string getDescription(); - - /** - * @brief Sets the name of the register. - * @param registerName Name of the register to set. - */ - void setRegisterName(std::string registerName); - - /** - * @brief Sets the offset of the register. - * @param offset Offset from the component's base address in bytes. - */ - void setOffset(uint32_t offset); - - /** - * @brief Sets the width of the register. - * @param width Width of the register in bits. - */ - void setWidth(uint32_t width); - - /** - * @brief Sets the read/write permissions of the register. - * @param rw Read/write permissions (e.g., "RW", "RO", "WO"). - */ - void setRW(std::string rw); - - /** - * @brief Sets the description of the register. - * @param description Description of the register's functionality. - */ - void setDescription(std::string description); - - /** - * @brief Prints the register information to the console. - * - * This method outputs the register's details including name, offset, - * width, permissions and description for debugging or documentation purposes. - */ - void print(); -}; - -#endif // REGISTER_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/bd_builder/system_map.hpp b/submodules/v80-vitis-flow/include/bd_builder/system_map.hpp deleted file mode 100644 index a07244fd..00000000 --- a/submodules/v80-vitis-flow/include/bd_builder/system_map.hpp +++ /dev/null @@ -1,123 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef SYSTEM_MAP_HPP -#define SYSTEM_MAP_HPP - -#include -#include - -#include -#include -#include -#include -#include - -#include "arg_parser.hpp" -#include "map_entry.hpp" - -/** - * @brief Class representing the complete system memory map for a hardware design. - * - * This class manages memory map entries for all components in the system and provides - * functionality to export the system map to files for documentation and runtime use. - * It also tracks streaming connections and clock frequency settings. - */ -class SystemMap { - std::vector entries; ///< List of memory map entries for all components - std::vector qdmaStreamConnections; ///< List of QDMA streaming connections - uint64_t targetClockFreq; ///< Target clock frequency in Hz - std::string SYSTEM_MAP_OUTPUT = "system.map"; ///< Output file name for the system map - bool segmented; ///< Flag indicating if the design is segmented - Platform platform; ///< Target platform (hardware, simulation, emulation) - - public: - /** - * @brief Constructor for SystemMap. - * @param segmented Flag indicating if the design is segmented. - * @param platform Target platform (hardware, simulation, emulation). - */ - SystemMap(bool segmented, Platform platform); - - /** - * @brief Adds a memory map entry to the system map. - * @param entry MapEntry object to add to the system map. - */ - void addEntry(MapEntry entry); - - /** - * @brief Writes the system map to output files. - * - * This method exports the complete system memory map to the output file specified - * in SYSTEM_MAP_OUTPUT for use by runtime software and documentation. - */ - void printToFile(); - - /** - * @brief Converts an integer value to a hexadecimal string representation. - * @param value Integer value to convert. - * @return String containing the hexadecimal representation. - */ - static std::string intToHex(uint64_t value); - - /** - * @brief Sets the target clock frequency for the system. - * @param freq Clock frequency in Hz. - */ - void setClockFreq(uint64_t freq); - - /** - * @brief Adds a streaming connection to the system map. - * @param connection StreamingConnection object to add to the system. - */ - void addStreamConnection(StreamingConnection connection); - - /** - * @brief Gets the list of memory map entries in the system. - * @return Vector of MapEntry objects in the system map. - */ - std::vector getEntries(); - - /** - * @brief Gets the list of QDMA streaming connections. - * @return Vector of StreamingConnection objects in the system. - */ - std::vector getStreamConnections(); - - /** - * @brief Gets the target clock frequency. - * @return Target clock frequency in Hz. - */ - uint64_t getClockFreq(); - - /** - * @brief Checks if the design is segmented. - * @return True if the design is segmented, false otherwise. - */ - bool isSegmented(); - - /** - * @brief Gets the target platform. - * @return Target platform (hardware, simulation, emulation). - */ - Platform getPlatform(); -}; - -#endif // SYSTEM_MAP_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/defines.hpp b/submodules/v80-vitis-flow/include/defines.hpp deleted file mode 100644 index 10b758ad..00000000 --- a/submodules/v80-vitis-flow/include/defines.hpp +++ /dev/null @@ -1,136 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#pragma once - -/** - * @file defines.hpp - * @brief Constants for XML parsing in the Vitis Flow. - * - * This header file defines constants used for parsing XML files - * that contain hardware kernel definitions. These constants specify - * XML node names, attribute names, and other parsing parameters - * used throughout the application. - */ - -/** - * @brief XML node name for version information. - */ -#define XML_NODE_VERSION "Version" - -/** - * @brief XML node name for time unit specification. - */ -#define XML_NODE_UNIT "unit" - -/** - * @brief XML node name for FPGA product family. - */ -#define XML_NODE_PRODUCT_FAMILY "ProductFamily" - -/** - * @brief XML node name for FPGA part number. - */ -#define XML_NODE_PART "Part" - -/** - * @brief XML node name for top-level model name. - */ -#define XML_NODE_TOP_MODEL_NAME "TopModelName" - -/** - * @brief XML node name for target clock period. - */ -#define XML_NODE_TARGET_CLK "TargetClockPeriod" - -/** - * @brief XML node name for clock uncertainty. - */ -#define XML_NODE_CLK_UNCERTAINTY "ClockUncertainty" - -/** - * @brief XML node name for estimated clock period. - */ -#define XML_NODE_ESTIMATED_CLK "EstimatedClockPeriod" - -/** - * @brief XML node name for 18K BRAM resource. - */ -#define XML_NODE_BRAM_18K "BRAM_18K" - -/** - * @brief XML node name for flip-flop (FF) resource. - */ -#define XML_NODE_FF "FF" - -/** - * @brief XML node name for look-up table (LUT) resource. - */ -#define XML_NODE_LUT "LUT" - -/** - * @brief XML node name for ultra RAM (URAM) resource. - */ -#define XML_NODE_URAM "URAM" - -/** - * @brief XML node name for DSP resource. - */ -#define XML_NODE_DSP "DSP" - -/** - * @brief XML node name for interface definitions. - */ -#define XML_NODE_INTERFACE "Interface" - -/** - * @brief XML node name for register definitions. - */ -#define XML_NODE_REGISTER "register" - -/** - * @brief XML attribute name for interface name. - */ -#define XML_ATTR_INTF_NAME "InterfaceName" - -/** - * @brief XML attribute name for type specification. - */ -#define XML_ATTR_TYPE "type" - -/** - * @brief XML attribute name for bus type. - */ -#define XML_ATTR_BUS_TYPE "busTypeName" - -/** - * @brief XML attribute name for interface mode. - */ -#define XML_ATTR_MODE "mode" - -/** - * @brief XML attribute name for data width. - */ -#define XML_ATTR_DATA_WIDTH "dataWidth" - -/** - * @brief XML attribute name for address width. - */ -#define XML_ATTR_ADDR_WIDTH "addrWidth" \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/sw_emu/arg.hpp b/submodules/v80-vitis-flow/include/sw_emu/arg.hpp deleted file mode 100644 index f574ed47..00000000 --- a/submodules/v80-vitis-flow/include/sw_emu/arg.hpp +++ /dev/null @@ -1,67 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef ARG_HPP -#define ARG_HPP - -#include -#include - -/** - * @brief Class representing a function argument. - * - * This class stores information about an argument passed to a function, - * including its name, position index, and argument type. - */ -class Arg { - private: - std::string name; ///< Name of the argument - uint32_t index; ///< Index position of the argument in the kernel signature - std::string argType; ///< Type of the argument (e.g., "scalar", "buffer") - - public: - /** - * @brief Constructor for Arg with initialization parameters. - * @param name Name of the kernel argument. - * @param index Index position of the argument in the kernel signature. - * @param argType Type of the argument (e.g., "scalar", "buffer"). - */ - Arg(std::string name, uint32_t index, std::string argType); - - /** - * @brief Gets the name of the argument. - * @return String containing the argument name. - */ - std::string getName(); - - /** - * @brief Gets the index position of the argument. - * @return Index position as a 32-bit unsigned integer. - */ - uint32_t getIndex(); - - /** - * @brief Gets the type of the argument. - * @return String describing the argument type (e.g., "scalar", "buffer"). - */ - std::string getArgType(); -}; - -#endif // ARG_HPP diff --git a/submodules/v80-vitis-flow/include/sw_emu/emulator.hpp b/submodules/v80-vitis-flow/include/sw_emu/emulator.hpp deleted file mode 100644 index b584d237..00000000 --- a/submodules/v80-vitis-flow/include/sw_emu/emulator.hpp +++ /dev/null @@ -1,73 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef EMULATOR_HPP -#define EMULATOR_HPP - -#include - -#include -#include -#include - -#include "arg_parser.hpp" -#include "func.hpp" -#include "json_parser.hpp" -#include "kernel.hpp" -#include "logger.hpp" -#include "zmq_client.hpp" - -#define JSON_PATH "/sol1_data.json" - -/** - * @brief Class providing a software emulation environment for hardware kernels. - * - * This class manages software emulation of hardware accelerator kernels, - * allowing functionality testing without actual hardware. It parses kernel - * function definitions, handles function call sequences, and maintains the - * connections between various kernels in the design. - */ -class Emulator { - private: - std::vector functions; ///< List of emulated functions - std::vector functionCalls; ///< Sequence of function calls to emulate - std::vector kernels; ///< Hardware kernels to emulate - std::vector connections; ///< Connections between kernels - - public: - /** - * @brief Constructor for Emulator. - * @param paths Vector of paths to source files containing function definitions. - * @param krnls Vector of kernel objects to emulate. - * @param conns Vector of connection objects defining inter-kernel connections. - */ - Emulator(std::vector paths, std::vector krnls, - std::vector conns); - - /** - * @brief Prints information about the emulation setup. - * - * This method outputs details about the loaded functions, kernels, - * and connections for debugging or documentation purposes. - */ - void print(); -}; - -#endif // EMULATOR_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/sw_emu/func.hpp b/submodules/v80-vitis-flow/include/sw_emu/func.hpp deleted file mode 100644 index 5750d266..00000000 --- a/submodules/v80-vitis-flow/include/sw_emu/func.hpp +++ /dev/null @@ -1,105 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef FUNC_HPP -#define FUNC_HPP - -#include -#include -#include - -#include "arg.hpp" - -/** - * @brief Class representing a function for emulation. - * - * This class stores information about a function including its name and arguments. - * It is used in the software emulation environment to represent hardware kernel functions. - */ -class Func { - private: - std::vector args; ///< List of arguments for the function - std::string name; ///< Name of the function - - public: - /** - * @brief Default constructor for Func. - */ - Func() = default; - - /** - * @brief Constructor for Func with initialization parameters. - * @param fn_name Name of the function. - * @param args Vector of Arg objects representing function arguments. - */ - Func(const std::string& fn_name, std::vector args); - - /** - * @brief Gets the list of arguments for this function. - * @return Vector of Arg objects representing function arguments. - */ - std::vector getArgs(); - - /** - * @brief Generates a function prototype for this function. - * @return String containing the function prototype. - */ - std::string getFunctionPrototype(); - - /** - * @brief Gets the name of the function. - * @return String containing the function name. - */ - std::string getName(); -}; - -/** - * @brief Class representing a function call in an emulation sequence. - * - * This class represents a specific invocation of a function during emulation, - * storing the function object and its name for execution tracking. - */ -class FunctionCall { - private: - Func function; ///< The function being called - std::string functionName; ///< Name of the function being called - - public: - /** - * @brief Constructor for FunctionCall with initialization parameters. - * @param fn Function object representing the function to call. - * @param fn_name Name of the function being called. - */ - FunctionCall(Func fn, std::string fn_name); - - /** - * @brief Gets the name of the function being called. - * @return String containing the function name. - */ - std::string getFunctionName(); - - /** - * @brief Gets the function object for this call. - * @return Func object representing the function being called. - */ - Func getFunction(); -}; - -#endif // FUNC_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/sw_emu/json_parser.hpp b/submodules/v80-vitis-flow/include/sw_emu/json_parser.hpp deleted file mode 100644 index 5b50e1ef..00000000 --- a/submodules/v80-vitis-flow/include/sw_emu/json_parser.hpp +++ /dev/null @@ -1,73 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef JSON_PARSER_HPP -#define JSON_PARSER_HPP - -#include - -#include -#include -#include - -#include "arg.hpp" -#include "func.hpp" -#include "logger.hpp" - -/** - * @brief Structure to store JSON format information. - * - * This structure holds information about JSON elements including their index, - * key name, and value for processing structured data. - */ -struct JsonFormat { - int idx; ///< Index of the JSON element - Json::Value value; ///< Value of the JSON element - std::string key; ///< Key name of the JSON element -}; - -/** - * @brief Class for parsing JSON configuration files for kernel functions. - * - * This class parses JSON files that contain function definitions for hardware - * kernels, extracting information about function names and argument lists. - */ -class JsonParser { - private: - Func func; ///< Function object extracted from the JSON file - - public: - /** - * @brief Constructor for JsonParser. - * @param file Path to the JSON file to parse. - * - * This constructor loads and parses the specified JSON file, - * extracting function information and storing it in the func member. - */ - JsonParser(const std::string& file); - - /** - * @brief Gets the parsed function. - * @return Func object containing the parsed function information. - */ - Func getFunction() const; -}; - -#endif // JSON_PARSER_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/sw_emu/zmq_client.hpp b/submodules/v80-vitis-flow/include/sw_emu/zmq_client.hpp deleted file mode 100644 index 785d7ae8..00000000 --- a/submodules/v80-vitis-flow/include/sw_emu/zmq_client.hpp +++ /dev/null @@ -1,81 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef ZMQ_CLIENT_HPP -#define ZMQ_CLIENT_HPP - -#include -#include - -/** - * @brief Client class for ZeroMQ messaging. - * - * This class provides a client implementation for ZeroMQ-based communication, - * allowing software components to communicate with hardware emulators or simulators. - * It handles connection setup, message reception, and acknowledgments. - */ -class ZmqClient { - private: - zmq::context_t context; ///< ZeroMQ context for socket management - zmq::socket_t socket; ///< ZeroMQ socket for communication - - public: - /** - * @brief Default constructor for ZmqClient. - * - * Initializes the ZeroMQ context and creates a REQ-type socket - * for request-reply communication pattern. - */ - ZmqClient(); - - /** - * @brief Destructor for ZmqClient. - * - * Closes the socket and terminates the ZeroMQ context. - */ - ~ZmqClient(); - - /** - * @brief Connects to a ZeroMQ server. - * @param address String containing the server address (e.g., "tcp://localhost:5555"). - * - * This method establishes a connection to a ZeroMQ server at the specified address. - */ - void connect(const std::string& address); - - /** - * @brief Receives a message from the server. - * @return String containing the received message. - * - * This method blocks until a message is received from the connected server. - */ - std::string recv(); - - /** - * @brief Sends an acknowledgment message to the server. - * @param ackMessage String containing the acknowledgment message. - * - * This method sends an acknowledgment message back to the server - * to complete the request-reply communication pattern. - */ - void ack(const std::string& ackMessage); -}; - -#endif // ZMQ_CLIENT_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/utils/logger.hpp b/submodules/v80-vitis-flow/include/utils/logger.hpp deleted file mode 100644 index ed7a54ae..00000000 --- a/submodules/v80-vitis-flow/include/utils/logger.hpp +++ /dev/null @@ -1,197 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef LOGGER_HPP -#define LOGGER_HPP - -#include -#include -#include -#include -#include -#include -#include -#include - -namespace utils { - -/** - * @brief Enumeration of available log levels. - * - * These log levels control the verbosity of logging output. - */ -enum class LogLevel { - INFO, ///< Informational messages for general reporting - ERROR, ///< Error messages indicating failures or issues - DEBUG ///< Detailed debug information for troubleshooting -}; - -/** - * @brief Static class providing logging facilities. - * - * This class implements a flexible logging system with support for - * different log levels, formatted output, and redirection to files. - * It supports colored output and custom formatting options. - */ -class Logger { - public: - /** - * @brief Sets the current log level. - * @param level The log level to set. - * - * Only messages at or above the specified level will be logged. - */ - static void setLogLevel(LogLevel level); - - /** - * @brief Sets the output destination for log messages. - * @param filename Path to the file where logs should be written. - * - * If this method is called, logs will be written to the specified file - * instead of the default standard output. - */ - static void setOutput(const std::string& filename); - - /** - * @brief Logs a formatted message. - * @param level The log level for this message. - * @param function The function name from where this log is called. - * @param format Format string with placeholders for variables. - * @param args Variable arguments to include in the formatted string. - * - * The format string uses {} for regular value insertion, - * {x} for hexadecimal, {b} for binary, and {o} for octal formatting. - * - * @tparam Args Variadic template parameter for formatting arguments. - */ - template - static void log(LogLevel level, const char* function, const char* format, Args... args) { - if (level > currentLogLevel_) { - return; - } - std::string color = getColor(level); - std::string resetColor = (useColours_) ? "\033[0m" : ""; - std::string levelStr = getLevelString(level); - std::string currentTime = getCurrentTime(); - std::string message = formatString(format, std::forward(args)...); - (*output_) << color << "[" << currentTime << "] [" << std::setw(5) << std::left << levelStr - << "] " << std::setw(80) << std::left << function << resetColor << ": " - << message << std::endl; - } - - private: - static std::unique_ptr fileStream_; ///< File stream for log output - static std::ostream* output_; ///< Current output stream - static bool useColours_; ///< Flag to enable/disable colored output - static LogLevel currentLogLevel_; ///< Current log level threshold - - /** - * @brief Gets the ANSI color code for a log level. - * @param level The log level. - * @return String containing the ANSI color code. - */ - static std::string getColor(LogLevel level); - - /** - * @brief Gets the string representation of a log level. - * @param level The log level. - * @return String containing the log level name. - */ - static std::string getLevelString(LogLevel level); - - /** - * @brief Gets the current time as a formatted string. - * @return String containing the current time. - */ - static std::string getCurrentTime(); - - /** - * @brief Helper function for string formatting (base case). - * @param oss Output string stream for the formatted result. - * @param format Format string remainder. - */ - static inline void formatStringHelper(std::ostringstream& oss, const char* format) { - while (*format) { - if (*format == '{' && *(format + 1) == '}') { - throw std::runtime_error("Too few arguments provided for format string"); - } - oss << *format++; - } - } - - /** - * @brief Helper function for string formatting (recursive case). - * @param oss Output string stream for the formatted result. - * @param format Format string remainder. - * @param value Current value to insert. - * @param args Remaining arguments to format. - * - * @tparam T Type of the current value. - * @tparam Args Types of the remaining arguments. - */ - template - static void formatStringHelper(std::ostringstream& oss, const char* format, T value, - Args&&... args) { - while (*format) { - if (*format == '{' && *(format + 1) == '}') { - oss << value; - format += 2; - formatStringHelper(oss, format, std::forward(args)...); - return; - } else if (*format == '{' && *(format + 1) == 'x' && *(format + 2) == '}') { - oss << std::hex << std::showbase << value; - format += 3; - formatStringHelper(oss, format, std::forward(args)...); - return; - } else if (*format == '{' && *(format + 1) == 'b' && *(format + 2) == '}') { - oss << "0b" << std::bitset(value); - format += 3; - formatStringHelper(oss, format, std::forward(args)...); - return; - } else if (*format == '{' && *(format + 1) == 'o' && *(format + 2) == '}') { - oss << "0o" << std::oct << std::showbase << value; - format += 3; - formatStringHelper(oss, format, std::forward(args)...); - return; - } - oss << *format++; - } - throw std::runtime_error("Too many arguments provided for format string"); - } - - /** - * @brief Formats a string with the given arguments. - * @param format Format string with placeholders. - * @param args Values to insert into the placeholders. - * @return Formatted string result. - * - * @tparam Args Types of the arguments for formatting. - */ - template - static std::string formatString(const char* format, Args&&... args) { - std::ostringstream oss; - formatStringHelper(oss, format, std::forward(args)...); - return oss.str(); - } -}; - -} // namespace utils - -#endif // LOGGER_HPP \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/xml_parser/area_estimates.hpp b/submodules/v80-vitis-flow/include/xml_parser/area_estimates.hpp deleted file mode 100644 index 3b2345ba..00000000 --- a/submodules/v80-vitis-flow/include/xml_parser/area_estimates.hpp +++ /dev/null @@ -1,77 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - - -#pragma once -#include -#include - -#include "logger.hpp" -#include "resource.hpp" - -/** - * @brief Class representing FPGA resource utilization and availability estimates. - * - * This class stores information about FPGA resource usage including both the - * resources consumed by a design and the total available resources on the target - * device. It supports tracking multiple resource types such as LUTs, FFs, BRAMs, etc. - */ -class AreaEstimates { - std::vector usedResources; ///< Resources used by the design - std::vector availableResources; ///< Total resources available on the target device - - public: - /** - * @brief Default constructor for AreaEstimates. - */ - AreaEstimates() = default; - - /** - * @brief Adds a used resource to the estimates. - * @param resource Resource object representing a used FPGA resource. - */ - void addResource(Resource resource); - - /** - * @brief Adds an available resource to the estimates. - * @param resource Resource object representing an available FPGA resource. - */ - void addAvailableResource(Resource resource); - - /** - * @brief Gets the list of used resources. - * @return Vector of Resource objects representing used FPGA resources. - */ - std::vector getUsedResources(); - - /** - * @brief Gets the list of available resources. - * @return Vector of Resource objects representing available FPGA resources. - */ - std::vector getAvailableResources(); - - /** - * @brief Prints the resource utilization information. - * - * This method outputs both used and available resources along with - * utilization percentages for each resource type. - */ - void print(); -}; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/xml_parser/interface.hpp b/submodules/v80-vitis-flow/include/xml_parser/interface.hpp deleted file mode 100644 index 846e3c9a..00000000 --- a/submodules/v80-vitis-flow/include/xml_parser/interface.hpp +++ /dev/null @@ -1,129 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#pragma once - -#include -#include -#include - -#include "logger.hpp" - -/** - * @brief Class representing a hardware interface in a kernel. - * - * This class stores information about hardware interfaces such as AXI4, AXI-Lite, - * or AXI-Stream interfaces that connect kernels to each other or to the system. - * It includes properties like interface type, bus type, mode, and width settings. - */ -class Interface { - std::string interfaceName; ///< Name of the interface - std::string interfaceType; ///< Type of interface (e.g., "s_axilite", "m_axi") - std::string busType; ///< Type of bus (e.g., "axi4", "axi4lite") - std::string mode; ///< Mode of the interface (e.g., "master", "slave") - uint8_t dataWidth; ///< Width of the data bus in bits - uint8_t addrWidth; ///< Width of the address bus in bits - - public: - /** - * @brief Default constructor for Interface. - */ - Interface() = default; - - /** - * @brief Gets the name of the interface. - * @return String containing the interface name. - */ - std::string getInterfaceName(); - - /** - * @brief Sets the name of the interface. - * @param name String containing the interface name. - */ - void setInterfaceName(const std::string& name); - - /** - * @brief Gets the type of the interface. - * @return String containing the interface type. - */ - std::string getInterfaceType(); - - /** - * @brief Sets the type of the interface. - * @param type String containing the interface type. - */ - void setInterfaceType(const std::string& type); - - /** - * @brief Gets the bus type of the interface. - * @return String containing the bus type. - */ - std::string getBusType(); - - /** - * @brief Sets the bus type of the interface. - * @param type String containing the bus type. - */ - void setBusType(const std::string& type); - - /** - * @brief Gets the mode of the interface. - * @return String containing the interface mode. - */ - std::string getMode(); - - /** - * @brief Sets the mode of the interface. - * @param mode String containing the interface mode. - */ - void setMode(const std::string& mode); - - /** - * @brief Gets the data width of the interface. - * @return Data width in bits. - */ - uint8_t getDataWidth(); - - /** - * @brief Sets the data width of the interface. - * @param width Data width in bits. - */ - void setDataWidth(uint8_t width); - - /** - * @brief Gets the address width of the interface. - * @return Address width in bits. - */ - uint8_t getAddrWidth(); - - /** - * @brief Sets the address width of the interface. - * @param width Address width in bits. - */ - void setAddrWidth(uint8_t width); - - /** - * @brief Prints interface information. - * - * This method outputs the interface details including name, type, - * bus type, mode, and width settings for debugging or documentation. - */ - void print(); -}; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp b/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp deleted file mode 100644 index 3572c6ef..00000000 --- a/submodules/v80-vitis-flow/include/xml_parser/kernel.hpp +++ /dev/null @@ -1,220 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#pragma once -#include -#include -#include -#include - -#include "area_estimates.hpp" -#include "interface.hpp" -#include "logger.hpp" -#include "register.hpp" - -/** - * @brief Enumeration for specifying resource type categories. - */ -enum ResourceType { - RESOURCE_TYPE_USED = 0, ///< Resources used by the kernel - RESOURCE_TYPE_AVAILABLE ///< Resources available on the target device -}; - -/** - * @brief Class representing a hardware kernel in an FPGA design. - * - * This class stores information about a hardware kernel including its build properties, - * clock settings, resource utilization, interfaces, and registers. It provides methods - * to access and modify these properties for design analysis and implementation. - */ -class Kernel { - std::string buildVersion; ///< Version of the build tools - std::string unit; ///< Unit of measurement for timing (typically ns) - std::string productFamily; ///< FPGA product family (e.g., "Virtex", "Versal") - std::string part; ///< Specific FPGA part number - std::string topModelName; ///< Name of the top-level module - std::string name; ///< Kernel name for identification - float targetClk; ///< Target clock frequency in MHz - float clkUncertainty; ///< Clock uncertainty in ns - float estimatedClk; ///< Estimated achievable clock frequency in MHz - AreaEstimates estimates; ///< Resource utilization estimates - std::vector interfaces; ///< List of kernel interfaces - std::vector registers; ///< List of registers in the kernel - - public: - /** - * @brief Default constructor for Kernel. - */ - Kernel() = default; - - /** - * @brief Gets the build version of the tools used. - * @return String containing the build version. - */ - std::string getBuildVersion(); - - /** - * @brief Sets the build version of the tools. - * @param buildVersion String containing the build version. - */ - void setBuildVersion(const std::string& buildVersion); - - /** - * @brief Gets the time unit used for timing measurements. - * @return String containing the time unit (typically "ns"). - */ - std::string getUnit(); - - /** - * @brief Sets the time unit for timing measurements. - * @param unit String containing the time unit. - */ - void setUnit(const std::string& unit); - - /** - * @brief Gets the FPGA product family. - * @return String containing the product family name. - */ - std::string getProductFamily(); - - /** - * @brief Sets the FPGA product family. - * @param family String containing the product family name. - */ - void setProductFamily(const std::string& family); - - /** - * @brief Gets the FPGA part number. - * @return String containing the FPGA part number. - */ - std::string getPart(); - - /** - * @brief Sets the FPGA part number. - * @param part String containing the FPGA part number. - */ - void setPart(const std::string& part); - - /** - * @brief Gets the top module name of the kernel. - * @return String containing the top module name. - */ - std::string getTopModelName(); - - /** - * @brief Sets the top module name of the kernel. - * @param modelName String containing the top module name. - */ - void setTopModelName(const std::string& modelName); - - /** - * @brief Gets the target clock frequency. - * @return Target clock frequency in MHz. - */ - float getTargetClk(); - - /** - * @brief Sets the target clock frequency. - * @param clk Target clock frequency in MHz. - */ - void setTargetClk(float clk); - - /** - * @brief Gets the clock uncertainty. - * @return Clock uncertainty in ns. - */ - float getClkUncertainty(); - - /** - * @brief Sets the clock uncertainty. - * @param uncertainty Clock uncertainty in ns. - */ - void setClkUncertainty(float uncertainty); - - /** - * @brief Gets the estimated achievable clock frequency. - * @return Estimated achievable clock frequency in MHz. - */ - float getEstimatedClk(); - - /** - * @brief Sets the estimated achievable clock frequency. - * @param clk Estimated achievable clock frequency in MHz. - */ - void setEstimatedClk(float clk); - - /** - * @brief Gets the resource utilization estimates. - * @return AreaEstimates object containing resource utilization. - */ - AreaEstimates getAreaEstimates(); - - /** - * @brief Adds a resource estimate to the kernel. - * @param type Type of resource (used or available). - * @param resource Resource object to add. - */ - void addEstimate(ResourceType type, Resource resource); - - /** - * @brief Gets the list of interfaces for this kernel. - * @return Vector of Interface objects for this kernel. - */ - std::vector getInterfaces(); - - /** - * @brief Adds an interface to the kernel. - * @param interface Interface object to add. - */ - void addInterface(Interface interface); - - /** - * @brief Gets the list of registers for this kernel. - * @return Vector of Register objects for this kernel. - */ - std::vector getRegisters(); - - /** - * @brief Adds a register to the kernel. - * @param reg Register object to add. - */ - void addRegister(Register reg); - - /** - * @brief Sets the name of the kernel. - * @param name String containing the kernel name. - */ - void setName(const std::string& name); - - /** - * @brief Gets the name of the kernel. - * @return String containing the kernel name. - */ - std::string getName(); - - /** - * @brief Prints detailed information about the kernel. - * - * This method outputs comprehensive information about the kernel including - * its build properties, clock settings, resource utilization, interfaces, - * and registers for debugging or documentation. - */ - void print(); -}; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/xml_parser/resource.hpp b/submodules/v80-vitis-flow/include/xml_parser/resource.hpp deleted file mode 100644 index 0c3f6f72..00000000 --- a/submodules/v80-vitis-flow/include/xml_parser/resource.hpp +++ /dev/null @@ -1,83 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#pragma once -#include -#include -#include - -#include "logger.hpp" - -/** - * @brief Class representing a hardware resource in an FPGA design. - * - * This class stores information about a hardware resource such as LUTs, - * FFs, BRAMs, or DSPs, including its name and numeric value (quantity). - * It is used for tracking resource utilization in FPGA designs. - */ -class Resource { - std::string name; ///< Name of the resource type (e.g., "LUT", "FF", "BRAM", "DSP") - uint32_t value; ///< Quantity of the resource (count) - - public: - /** - * @brief Default constructor for Resource. - */ - Resource() = default; - - /** - * @brief Constructor for Resource with initialization parameters. - * @param name String containing the resource type name. - * @param value Quantity of the resource. - */ - Resource(const std::string& name, uint32_t value) : name(name), value(value) {} - - /** - * @brief Gets the name of the resource. - * @return String containing the resource type name. - */ - std::string getName(); - - /** - * @brief Sets the name of the resource. - * @param name String containing the resource type name. - */ - void setName(const std::string& name); - - /** - * @brief Gets the quantity of the resource. - * @return Unsigned integer representing the resource quantity. - */ - uint32_t getValue(); - - /** - * @brief Sets the quantity of the resource. - * @param value Unsigned integer representing the resource quantity. - */ - void setValue(uint32_t value); - - /** - * @brief Prints the resource information. - * - * This method outputs the resource type and quantity for - * debugging or documentation purposes. - */ - void print(); -}; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/include/xml_parser/xml_parser.hpp b/submodules/v80-vitis-flow/include/xml_parser/xml_parser.hpp deleted file mode 100644 index bd9d60a2..00000000 --- a/submodules/v80-vitis-flow/include/xml_parser/xml_parser.hpp +++ /dev/null @@ -1,92 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#pragma once -#include -#include - -#include - -#include "kernel.hpp" -#include "register.hpp" - -/** - * @brief Class for parsing XML files containing kernel definitions. - * - * This class parses XML files generated by Vitis HLS tools - * to extract kernel information, including interfaces, resource usage, - * and register definitions. It uses the libxml2 library for XML parsing. - */ -class XmlParser { - std::string fileName; ///< Name of the XML file to parse - xmlDocPtr document; ///< XML document pointer - xmlNode* rootNode; ///< Root node of the XML document - xmlNode* workingNode; ///< Current working node during parsing - Kernel kernel; ///< Kernel object being populated from XML - - public: - /** - * @brief Constructor for XmlParser. - * @param filename Path to the XML file to parse. - * - * Initializes the parser and loads the XML document. - */ - XmlParser(const std::string& filename); - - /** - * @brief Parses the XML file and populates the kernel object. - * - * This method traverses the XML document structure to extract - * all relevant information about the kernel. - */ - void parseXml(); - - /** - * @brief Gets the parsed kernel object. - * @return Kernel object populated with data from the XML file. - */ - Kernel getKernel(); - - /** - * @brief Converts xmlChar pointer to standard C++ string. - * @param xmlCharPtr XML character pointer to convert. - * @return Standard C++ string containing the converted value. - * - * Helper method to convert between libxml2 character types and C++ strings. - */ - static std::string convertFromXmlCharPtr(const xmlChar* xmlCharPtr); - - /** - * @brief Parses a register node from the XML document. - * @param node XML node containing register information. - * - * This method extracts register information from an XML node - * and adds it to the kernel object. - */ - void parseRegisterNode(xmlNodePtr node); - - /** - * @brief Parses a register field node from the XML document. - * @param node XML node containing register field information. - * - * This method extracts register field details from an XML node. - */ - void parseFieldNode(xmlNodePtr node); -}; \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/create_clk.py b/submodules/v80-vitis-flow/resources/create_clk.py deleted file mode 100644 index 8c5a004b..00000000 --- a/submodules/v80-vitis-flow/resources/create_clk.py +++ /dev/null @@ -1,71 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -import re -import xml.etree.ElementTree as ET -import argparse - -def extract_clkout1_primitive(filename): - with open(filename, 'r') as file: - for line in file: - if 'clkout1_primitive' in line: - match = re.search(r'clkout1_primitive\s+([\d.]+)', line) - if match: - return float(match.group(1)) - return None - -def update_clock_frequency(xml_filename, clkout1_primitive_value): - tree = ET.parse(xml_filename) - root = tree.getroot() - - clock_frequency_element = root.find('ClockFrequency') - if clock_frequency_element is not None: - current_frequency_hz = int(clock_frequency_element.text) - - current_period_ns = 1e9 / current_frequency_hz - - new_period_ns = current_period_ns - clkout1_primitive_value - - new_frequency_hz = int(1e9 / new_period_ns) - - clock_frequency_element.text = str(new_frequency_hz) - - tree.write(xml_filename) - return new_frequency_hz - return None - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Update ClockFrequency in system map XML based on timing report.') - parser.add_argument('--system_map', required=True, help='Path to the system map XML file') - parser.add_argument('--timing', required=True, help='Path to the timing report file') - - args = parser.parse_args() - - clkout1_primitive_value = extract_clkout1_primitive(args.timing) - if clkout1_primitive_value is not None: - print(f'clkout1_primitive value: {clkout1_primitive_value}') - - new_frequency_hz = update_clock_frequency(args.system_map, clkout1_primitive_value) - if new_frequency_hz is not None: - print(f'Updated ClockFrequency value: {new_frequency_hz} Hz') - else: - print('ClockFrequency element not found in the XML file') - else: - print('clkout1_primitive value not found in the timing report') \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/gen_version.py b/submodules/v80-vitis-flow/resources/gen_version.py deleted file mode 100644 index e1d29288..00000000 --- a/submodules/v80-vitis-flow/resources/gen_version.py +++ /dev/null @@ -1,59 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -import json -import re -import argparse -from datetime import datetime - -def extract_logic_uuid(log_file): - with open(log_file, 'r') as file: - for line in file: - match = re.search(r'Logic-UUID is ([a-f0-9]+)', line) - if match: - return match.group(1) - raise ValueError("Logic-UUID not found in log file") - -def create_json(log_file, name): - logic_uuid = extract_logic_uuid(log_file) - release = datetime.now().strftime("%Y%m%d") - application = name - - data = { - "design": { - "name": name, - "release": release, - "logic_uuid": logic_uuid, - "application": application - } - } - - with open('version.json', 'w') as json_file: - json.dump(data, json_file, indent=4) - - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Create JSON from vivado.log and input parameters.') - parser.add_argument('--log_file', type=str, required=True, help='Path to the vivado.log file') - parser.add_argument('--name', type=str, required=True, help='Design name') - - args = parser.parse_args() - - create_json(args.log_file, args.name) \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/noc_sol.ncr b/submodules/v80-vitis-flow/resources/noc_sol.ncr deleted file mode 100644 index d5d00d37..00000000 --- a/submodules/v80-vitis-flow/resources/noc_sol.ncr +++ /dev/null @@ -1,59058 +0,0 @@ -{ - "SolutionType": "OPTIMAL", - "LockAllDestIds": false, - "Paths": [ - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X10Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB1_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X10Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB1_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X10Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X10Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB3_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port2_out", - "NOC_NPS5555_X19Y0", - "port0_in", - "NOC_NPS5555_X19Y0", - "port2_out", - "NOC_NPS5555_X21Y0", - "port0_in", - "NOC_NPS5555_X21Y0", - "port2_out", - "NOC_NPS5555_X23Y0", - "port0_in", - "NOC_NPS5555_X23Y0", - "port3_out", - "NOC_NPS5555_X23Y1", - "port1_in", - "NOC_NPS5555_X23Y1", - "port2_out", - "NOC_NPS_VNOC_X3Y0", - "port0_in", - "NOC_NPS_VNOC_X3Y0", - "port2_out", - "NOC_NPS_VNOC_X3Y2", - "port0_in", - "NOC_NPS_VNOC_X3Y2", - "port2_out", - "NOC_NPS_VNOC_X3Y4", - "port0_in", - "NOC_NPS_VNOC_X3Y4", - "port2_out", - "NOC_NPS_VNOC_X3Y6", - "port0_in", - "NOC_NPS_VNOC_X3Y6", - "port2_out", - "NOC_NPS_VNOC_X3Y8", - "port0_in", - "NOC_NPS_VNOC_X3Y8", - "port2_out", - "NOC_NPS_VNOC_X3Y10", - "port0_in", - "NOC_NPS_VNOC_X3Y10", - "port2_out", - "NOC_NPS_VNOC_X3Y12", - "port0_in", - "NOC_NPS_VNOC_X3Y12", - "port2_out", - "NOC_NPS7575_X7Y0", - "port1_in", - "NOC_NPS7575_X7Y0", - "port3_out", - "NOC_NIDB_X3Y1", - "port0_in", - "NOC_NIDB_X3Y1", - "port1_out", - "NOC_NIDB_X3Y3", - "port1_in", - "NOC_NIDB_X3Y3", - "port0_out", - "NOC_NPS7575_X7Y2", - "port3_in", - "NOC_NPS7575_X7Y2", - "port1_out", - "NOC_NPS_VNOC_X3Y14", - "port0_in", - "NOC_NPS_VNOC_X3Y14", - "port2_out", - "NOC_NPS_VNOC_X3Y16", - "port0_in", - "NOC_NPS_VNOC_X3Y16", - "port2_out", - "NOC_NPS_VNOC_X3Y18", - "port0_in", - "NOC_NPS_VNOC_X3Y18", - "port2_out", - "NOC_NPS_VNOC_X3Y20", - "port0_in", - "NOC_NPS_VNOC_X3Y20", - "port2_out", - "NOC_NPS_VNOC_X3Y22", - "port0_in", - "NOC_NPS_VNOC_X3Y22", - "port2_out", - "NOC_NPS_VNOC_X3Y24", - "port0_in", - "NOC_NPS_VNOC_X3Y24", - "port2_out", - "NOC_NPS7575_X7Y4", - "port1_in", - "NOC_NPS7575_X7Y4", - "port3_out", - "NOC_NIDB_X3Y5", - "port0_in", - "NOC_NIDB_X3Y5", - "port1_out", - "NOC_NIDB_X3Y7", - "port1_in", - "NOC_NIDB_X3Y7", - "port0_out", - "NOC_NPS7575_X7Y6", - "port3_in", - "NOC_NPS7575_X7Y6", - "port1_out", - "NOC_NPS_VNOC_X3Y26", - "port0_in", - "NOC_NPS_VNOC_X3Y26", - "port2_out", - "NOC_NPS_VNOC_X3Y28", - "port0_in", - "NOC_NPS_VNOC_X3Y28", - "port2_out", - "NOC_NPS_VNOC_X3Y30", - "port0_in", - "NOC_NPS_VNOC_X3Y30", - "port2_out", - "NOC_NPS_VNOC_X3Y32", - "port0_in", - "NOC_NPS_VNOC_X3Y32", - "port2_out", - "NOC_NPS_VNOC_X3Y34", - "port0_in", - "NOC_NPS_VNOC_X3Y34", - "port2_out", - "NOC_NPS_VNOC_X3Y36", - "port0_in", - "NOC_NPS_VNOC_X3Y36", - "port2_out", - "NOC_NCRB_X3Y1", - "port1_in", - "NOC_NCRB_X3Y1", - "port1_out", - "NOC_NPS5555_X8Y6", - "port3_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB3_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB2_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB2_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X6Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB0_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X6Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB0_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", - "portSideA2_out", - "NOC_NPS6_X6Y2", - "port5_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA2_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB1_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB1_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X6Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB1_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X6Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB1_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB1_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB1_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB0_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB0_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB0_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB0_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA1_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", - "portSideA1_out", - "NOC_NPS6_X4Y1", - "port5_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X14Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB2_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB2_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X3Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB3_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB3_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB1_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB1_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB3_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB3_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB3_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB3_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB3_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB3_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA2_out", - "NOC_NPS6_X6Y2", - "port5_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port1_out", - "NOC_NPS5555_X17Y0", - "port3_in", - "NOC_NPS5555_X17Y0", - "port0_out", - "NOC_NPS5555_X15Y0", - "port2_in", - "NOC_NPS5555_X15Y0", - "port0_out", - "NOC_NPS5555_X13Y0", - "port2_in", - "NOC_NPS5555_X13Y0", - "port0_out", - "NOC_NPS5555_X11Y0", - "port2_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port2_out", - "NOC_NPS5555_X13Y0", - "port0_in", - "NOC_NPS5555_X13Y0", - "port2_out", - "NOC_NPS5555_X15Y0", - "port0_in", - "NOC_NPS5555_X15Y0", - "port2_out", - "NOC_NPS5555_X17Y0", - "port0_in", - "NOC_NPS5555_X17Y0", - "port3_out", - "NOC_NPS5555_X17Y1", - "port1_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA2_in", - "NOC_NPS4_X6Y0", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB2_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB2_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB2_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port2_out", - "NOC_NPS5555_X9Y0", - "port0_in", - "NOC_NPS5555_X9Y0", - "port2_out", - "NOC_NPS5555_X11Y0", - "port0_in", - "NOC_NPS5555_X11Y0", - "port3_out", - "NOC_NPS5555_X11Y1", - "port1_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB2_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port1_out", - "NOC_NPS5555_X11Y0", - "port3_in", - "NOC_NPS5555_X11Y0", - "port0_out", - "NOC_NPS5555_X9Y0", - "port2_in", - "NOC_NPS5555_X9Y0", - "port0_out", - "NOC_NPS5555_X7Y0", - "port2_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA2_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port5_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/M00_AXI_nsu", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 5, - "WriteBW": 5, - "ReadAchievedBW": 5, - "WriteAchievedBW": 5, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port2_out", - "NOC_NPS5555_X3Y0", - "port0_in", - "NOC_NPS5555_X3Y0", - "port2_out", - "NOC_NPS5555_X5Y0", - "port0_in", - "NOC_NPS5555_X5Y0", - "port2_out", - "NOC_NPS5555_X7Y0", - "port0_in", - "NOC_NPS5555_X7Y0", - "port3_out", - "NOC_NPS5555_X7Y1", - "port1_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port1_out", - "NOC_NPS5555_X7Y0", - "port3_in", - "NOC_NPS5555_X7Y0", - "port0_out", - "NOC_NPS5555_X5Y0", - "port2_in", - "NOC_NPS5555_X5Y0", - "port0_out", - "NOC_NPS5555_X3Y0", - "port2_in", - "NOC_NPS5555_X3Y0", - "port0_out", - "NOC_NPS5555_X1Y0", - "port2_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 22 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 24 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 24 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 24 - }, - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 24 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S00_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y0", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y0", - "req_out", - "NOC_NPS5555_X1Y0", - "port3_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y0", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port3_out", - "NOC_NMU128_X0Y0", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X10Y0", - "pc1_port1_out", - "NOC_NPS4_X5Y1", - "portSideB1_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port2_out", - "NOC_NPS5555_X13Y2", - "port0_in", - "NOC_NPS5555_X13Y2", - "port2_out", - "NOC_NPS5555_X15Y2", - "port0_in", - "NOC_NPS5555_X15Y2", - "port2_out", - "NOC_NPS5555_X17Y2", - "port0_in", - "NOC_NPS5555_X17Y2", - "port1_out", - "NOC_NPS5555_X17Y1", - "port3_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA2_in", - "NOC_NPS4_X5Y1", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X10Y0", - "pc1_port1_out", - "NOC_NPS4_X5Y1", - "portSideB1_in", - "NOC_NPS4_X5Y1", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port4_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port3_out", - "NOC_NPS5555_X17Y2", - "port1_in", - "NOC_NPS5555_X17Y2", - "port0_out", - "NOC_NPS5555_X15Y2", - "port2_in", - "NOC_NPS5555_X15Y2", - "port0_out", - "NOC_NPS5555_X13Y2", - "port2_in", - "NOC_NPS5555_X13Y2", - "port0_out", - "NOC_NPS5555_X11Y2", - "port2_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X10Y0", - "pc0_port1_out", - "NOC_NPS4_X5Y1", - "portSideB0_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port2_out", - "NOC_NPS5555_X13Y2", - "port0_in", - "NOC_NPS5555_X13Y2", - "port2_out", - "NOC_NPS5555_X15Y2", - "port0_in", - "NOC_NPS5555_X15Y2", - "port2_out", - "NOC_NPS5555_X17Y2", - "port0_in", - "NOC_NPS5555_X17Y2", - "port1_out", - "NOC_NPS5555_X17Y1", - "port3_in", - "NOC_NPS5555_X17Y1", - "port2_out", - "NOC_NPS_VNOC_X2Y0", - "port0_in", - "NOC_NPS_VNOC_X2Y0", - "port2_out", - "NOC_NPS_VNOC_X2Y2", - "port0_in", - "NOC_NPS_VNOC_X2Y2", - "port2_out", - "NOC_NPS_VNOC_X2Y4", - "port0_in", - "NOC_NPS_VNOC_X2Y4", - "port2_out", - "NOC_NPS_VNOC_X2Y6", - "port0_in", - "NOC_NPS_VNOC_X2Y6", - "port2_out", - "NOC_NPS_VNOC_X2Y8", - "port0_in", - "NOC_NPS_VNOC_X2Y8", - "port2_out", - "NOC_NPS_VNOC_X2Y10", - "port0_in", - "NOC_NPS_VNOC_X2Y10", - "port2_out", - "NOC_NPS_VNOC_X2Y12", - "port0_in", - "NOC_NPS_VNOC_X2Y12", - "port2_out", - "NOC_NPS7575_X6Y0", - "port1_in", - "NOC_NPS7575_X6Y0", - "port3_out", - "NOC_NIDB_X2Y1", - "port0_in", - "NOC_NIDB_X2Y1", - "port1_out", - "NOC_NIDB_X2Y3", - "port1_in", - "NOC_NIDB_X2Y3", - "port0_out", - "NOC_NPS7575_X6Y2", - "port3_in", - "NOC_NPS7575_X6Y2", - "port1_out", - "NOC_NPS_VNOC_X2Y14", - "port0_in", - "NOC_NPS_VNOC_X2Y14", - "port2_out", - "NOC_NPS_VNOC_X2Y16", - "port0_in", - "NOC_NPS_VNOC_X2Y16", - "port2_out", - "NOC_NPS_VNOC_X2Y18", - "port0_in", - "NOC_NPS_VNOC_X2Y18", - "port2_out", - "NOC_NPS_VNOC_X2Y20", - "port0_in", - "NOC_NPS_VNOC_X2Y20", - "port2_out", - "NOC_NPS_VNOC_X2Y22", - "port0_in", - "NOC_NPS_VNOC_X2Y22", - "port2_out", - "NOC_NPS_VNOC_X2Y24", - "port0_in", - "NOC_NPS_VNOC_X2Y24", - "port2_out", - "NOC_NPS7575_X6Y4", - "port1_in", - "NOC_NPS7575_X6Y4", - "port3_out", - "NOC_NIDB_X2Y5", - "port0_in", - "NOC_NIDB_X2Y5", - "port1_out", - "NOC_NIDB_X2Y7", - "port1_in", - "NOC_NIDB_X2Y7", - "port0_out", - "NOC_NPS7575_X6Y6", - "port3_in", - "NOC_NPS7575_X6Y6", - "port1_out", - "NOC_NPS_VNOC_X2Y26", - "port0_in", - "NOC_NPS_VNOC_X2Y26", - "port2_out", - "NOC_NPS_VNOC_X2Y28", - "port0_in", - "NOC_NPS_VNOC_X2Y28", - "port2_out", - "NOC_NPS_VNOC_X2Y30", - "port0_in", - "NOC_NPS_VNOC_X2Y30", - "port2_out", - "NOC_NPS_VNOC_X2Y32", - "port0_in", - "NOC_NPS_VNOC_X2Y32", - "port2_out", - "NOC_NPS_VNOC_X2Y34", - "port0_in", - "NOC_NPS_VNOC_X2Y34", - "port2_out", - "NOC_NPS_VNOC_X2Y36", - "port0_in", - "NOC_NPS_VNOC_X2Y36", - "port2_out", - "NOC_NCRB_X2Y1", - "port1_in", - "NOC_NCRB_X2Y1", - "port1_out", - "NOC_NPS5555_X7Y6", - "port3_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA2_in", - "NOC_NPS4_X5Y1", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X10Y0", - "pc0_port1_out", - "NOC_NPS4_X5Y1", - "portSideB0_in", - "NOC_NPS4_X5Y1", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port4_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port3_out", - "NOC_NCRB_X2Y0", - "port1_in", - "NOC_NCRB_X2Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y36", - "port2_in", - "NOC_NPS_VNOC_X2Y36", - "port0_out", - "NOC_NPS_VNOC_X2Y34", - "port2_in", - "NOC_NPS_VNOC_X2Y34", - "port0_out", - "NOC_NPS_VNOC_X2Y32", - "port2_in", - "NOC_NPS_VNOC_X2Y32", - "port0_out", - "NOC_NPS_VNOC_X2Y30", - "port2_in", - "NOC_NPS_VNOC_X2Y30", - "port0_out", - "NOC_NPS_VNOC_X2Y28", - "port2_in", - "NOC_NPS_VNOC_X2Y28", - "port0_out", - "NOC_NPS_VNOC_X2Y26", - "port2_in", - "NOC_NPS_VNOC_X2Y26", - "port0_out", - "NOC_NPS7575_X6Y6", - "port1_in", - "NOC_NPS7575_X6Y6", - "port3_out", - "NOC_NIDB_X2Y7", - "port0_in", - "NOC_NIDB_X2Y7", - "port1_out", - "NOC_NIDB_X2Y5", - "port1_in", - "NOC_NIDB_X2Y5", - "port0_out", - "NOC_NPS7575_X6Y4", - "port3_in", - "NOC_NPS7575_X6Y4", - "port1_out", - "NOC_NPS_VNOC_X2Y24", - "port2_in", - "NOC_NPS_VNOC_X2Y24", - "port0_out", - "NOC_NPS_VNOC_X2Y22", - "port2_in", - "NOC_NPS_VNOC_X2Y22", - "port0_out", - "NOC_NPS_VNOC_X2Y20", - "port2_in", - "NOC_NPS_VNOC_X2Y20", - "port0_out", - "NOC_NPS_VNOC_X2Y18", - "port2_in", - "NOC_NPS_VNOC_X2Y18", - "port0_out", - "NOC_NPS_VNOC_X2Y16", - "port2_in", - "NOC_NPS_VNOC_X2Y16", - "port0_out", - "NOC_NPS_VNOC_X2Y14", - "port2_in", - "NOC_NPS_VNOC_X2Y14", - "port0_out", - "NOC_NPS7575_X6Y2", - "port1_in", - "NOC_NPS7575_X6Y2", - "port3_out", - "NOC_NIDB_X2Y3", - "port0_in", - "NOC_NIDB_X2Y3", - "port1_out", - "NOC_NIDB_X2Y1", - "port1_in", - "NOC_NIDB_X2Y1", - "port0_out", - "NOC_NPS7575_X6Y0", - "port3_in", - "NOC_NPS7575_X6Y0", - "port1_out", - "NOC_NPS_VNOC_X2Y12", - "port2_in", - "NOC_NPS_VNOC_X2Y12", - "port0_out", - "NOC_NPS_VNOC_X2Y10", - "port2_in", - "NOC_NPS_VNOC_X2Y10", - "port0_out", - "NOC_NPS_VNOC_X2Y8", - "port2_in", - "NOC_NPS_VNOC_X2Y8", - "port0_out", - "NOC_NPS_VNOC_X2Y6", - "port2_in", - "NOC_NPS_VNOC_X2Y6", - "port0_out", - "NOC_NPS_VNOC_X2Y4", - "port2_in", - "NOC_NPS_VNOC_X2Y4", - "port0_out", - "NOC_NPS_VNOC_X2Y2", - "port2_in", - "NOC_NPS_VNOC_X2Y2", - "port0_out", - "NOC_NPS_VNOC_X2Y0", - "port2_in", - "NOC_NPS_VNOC_X2Y0", - "port0_out", - "NOC_NPS5555_X17Y1", - "port2_in", - "NOC_NPS5555_X17Y1", - "port3_out", - "NOC_NPS5555_X17Y2", - "port1_in", - "NOC_NPS5555_X17Y2", - "port0_out", - "NOC_NPS5555_X15Y2", - "port2_in", - "NOC_NPS5555_X15Y2", - "port0_out", - "NOC_NPS5555_X13Y2", - "port2_in", - "NOC_NPS5555_X13Y2", - "port0_out", - "NOC_NPS5555_X11Y2", - "port2_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port1_out", - "NOC_NPS4_X2Y1", - "portSideB2_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port1_out", - "NOC_NPS4_X2Y1", - "portSideB2_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc1_port1_out", - "NOC_NPS4_X7Y1", - "portSideB3_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc1_port1_out", - "NOC_NPS4_X7Y1", - "portSideB3_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port1_out", - "NOC_NPS4_X0Y1", - "portSideB1_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port1_out", - "NOC_NPS4_X0Y1", - "portSideB1_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port1_out", - "NOC_NPS4_X7Y1", - "portSideB2_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port1_out", - "NOC_NPS4_X7Y1", - "portSideB2_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc0_port1_out", - "NOC_NPS4_X0Y1", - "portSideB2_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc0_port1_out", - "NOC_NPS4_X0Y1", - "portSideB2_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port1_out", - "NOC_NPS4_X2Y1", - "portSideB3_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port1_out", - "NOC_NPS4_X2Y1", - "portSideB3_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port1_out", - "NOC_NPS4_X0Y1", - "portSideB3_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port1_out", - "NOC_NPS4_X0Y1", - "portSideB3_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X6Y0", - "pc0_port1_out", - "NOC_NPS4_X3Y1", - "portSideB0_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA1_in", - "NOC_NPS4_X3Y1", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 129 - }, - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X6Y0", - "pc0_port1_out", - "NOC_NPS4_X3Y1", - "portSideB0_in", - "NOC_NPS4_X3Y1", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port4_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 129 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port1_out", - "NOC_NPS4_X7Y1", - "portSideB1_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port1_out", - "NOC_NPS4_X7Y1", - "portSideB1_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port1_out", - "NOC_NPS4_X0Y1", - "portSideB0_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port4_out", - "NOC_NPS4_X0Y1", - "portSideA2_in", - "NOC_NPS4_X0Y1", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port1_out", - "NOC_NPS4_X0Y1", - "portSideB0_in", - "NOC_NPS4_X0Y1", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port4_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port1_out", - "NOC_NPS4_X4Y1", - "portSideB1_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port1_out", - "NOC_NPS4_X4Y1", - "portSideB1_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port1_out", - "NOC_NPS4_X6Y1", - "portSideB0_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port1_out", - "NOC_NPS4_X6Y1", - "portSideB0_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X6Y0", - "pc1_port1_out", - "NOC_NPS4_X3Y1", - "portSideB1_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA1_in", - "NOC_NPS4_X3Y1", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 129 - }, - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X6Y0", - "pc1_port1_out", - "NOC_NPS4_X3Y1", - "portSideB1_in", - "NOC_NPS4_X3Y1", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port4_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 129 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port1_out", - "NOC_NPS4_X6Y1", - "portSideB1_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port1_out", - "NOC_NPS4_X6Y1", - "portSideB1_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port1_out", - "NOC_NPS4_X4Y1", - "portSideB0_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port1_out", - "NOC_NPS4_X4Y1", - "portSideB0_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X14Y0", - "pc0_port1_out", - "NOC_NPS4_X7Y1", - "portSideB0_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port4_out", - "NOC_NPS4_X7Y1", - "portSideA1_in", - "NOC_NPS4_X7Y1", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 141 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc0_port1_out", - "NOC_NPS4_X7Y1", - "portSideB0_in", - "NOC_NPS4_X7Y1", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port4_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 141 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port1_out", - "NOC_NPS4_X1Y1", - "portSideB2_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port1_out", - "NOC_NPS4_X1Y1", - "portSideB2_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X3Y0", - "pc1_port1_out", - "NOC_NPS4_X1Y1", - "portSideB3_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc1_port1_out", - "NOC_NPS4_X1Y1", - "portSideB3_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port1_out", - "NOC_NPS4_X2Y1", - "portSideB0_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port1_out", - "NOC_NPS4_X2Y1", - "portSideB0_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port1_out", - "NOC_NPS4_X4Y1", - "portSideB2_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port1_out", - "NOC_NPS4_X4Y1", - "portSideB2_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port1_out", - "NOC_NPS4_X2Y1", - "portSideB1_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port4_out", - "NOC_NPS4_X2Y1", - "portSideA2_in", - "NOC_NPS4_X2Y1", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 127 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port1_out", - "NOC_NPS4_X2Y1", - "portSideB1_in", - "NOC_NPS4_X2Y1", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port4_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 127 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port1_out", - "NOC_NPS4_X4Y1", - "portSideB3_in", - "NOC_NPS4_X4Y1", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port4_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA2_in", - "NOC_NPS4_X4Y1", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 133 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port4_out", - "NOC_NPS4_X4Y1", - "portSideA1_in", - "NOC_NPS4_X4Y1", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port1_out", - "NOC_NPS4_X4Y1", - "portSideB3_in", - "NOC_NPS4_X4Y1", - "portSideA1_out", - "NOC_NPS6_X4Y1", - "port4_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port1_out", - "NOC_NPS4_X5Y1", - "portSideB3_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port1_out", - "NOC_NPS4_X5Y1", - "portSideB3_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port1_out", - "NOC_NPS4_X5Y1", - "portSideB2_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port4_out", - "NOC_NPS4_X5Y1", - "portSideA1_in", - "NOC_NPS4_X5Y1", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 135 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port1_out", - "NOC_NPS4_X5Y1", - "portSideB2_in", - "NOC_NPS4_X5Y1", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port4_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 135 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port1_out", - "NOC_NPS4_X3Y1", - "portSideB3_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port1_out", - "NOC_NPS4_X3Y1", - "portSideB3_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port1_out", - "NOC_NPS4_X6Y1", - "portSideB2_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port1_out", - "NOC_NPS4_X6Y1", - "portSideB2_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port1_out", - "NOC_NPS4_X3Y1", - "portSideB2_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port4_out", - "NOC_NPS4_X3Y1", - "portSideA2_in", - "NOC_NPS4_X3Y1", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 131 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port1_out", - "NOC_NPS4_X3Y1", - "portSideB2_in", - "NOC_NPS4_X3Y1", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port4_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 131 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port1_out", - "NOC_NPS4_X1Y1", - "portSideB1_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port1_out", - "NOC_NPS4_X1Y1", - "portSideB1_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port1_out", - "NOC_NPS4_X1Y1", - "portSideB0_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port2_out", - "NOC_NPS7575_X4Y4", - "port1_in", - "NOC_NPS7575_X4Y4", - "port3_out", - "NOC_NIDB_X0Y5", - "port0_in", - "NOC_NIDB_X0Y5", - "port1_out", - "NOC_NIDB_X0Y7", - "port1_in", - "NOC_NIDB_X0Y7", - "port0_out", - "NOC_NPS7575_X4Y6", - "port3_in", - "NOC_NPS7575_X4Y6", - "port1_out", - "NOC_NPS_VNOC_X0Y26", - "port0_in", - "NOC_NPS_VNOC_X0Y26", - "port2_out", - "NOC_NPS_VNOC_X0Y28", - "port0_in", - "NOC_NPS_VNOC_X0Y28", - "port2_out", - "NOC_NPS_VNOC_X0Y30", - "port0_in", - "NOC_NPS_VNOC_X0Y30", - "port2_out", - "NOC_NPS_VNOC_X0Y32", - "port0_in", - "NOC_NPS_VNOC_X0Y32", - "port2_out", - "NOC_NPS_VNOC_X0Y34", - "port0_in", - "NOC_NPS_VNOC_X0Y34", - "port2_out", - "NOC_NPS_VNOC_X0Y36", - "port0_in", - "NOC_NPS_VNOC_X0Y36", - "port2_out", - "NOC_NCRB_X0Y1", - "port1_in", - "NOC_NCRB_X0Y1", - "port1_out", - "NOC_NPS5555_X5Y6", - "port3_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port4_out", - "NOC_NPS4_X1Y1", - "portSideA2_in", - "NOC_NPS4_X1Y1", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 125 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port1_out", - "NOC_NPS4_X1Y1", - "portSideB0_in", - "NOC_NPS4_X1Y1", - "portSideA2_out", - "NOC_NPS6_X1Y2", - "port4_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port3_out", - "NOC_NCRB_X0Y0", - "port1_in", - "NOC_NCRB_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y36", - "port2_in", - "NOC_NPS_VNOC_X0Y36", - "port0_out", - "NOC_NPS_VNOC_X0Y34", - "port2_in", - "NOC_NPS_VNOC_X0Y34", - "port0_out", - "NOC_NPS_VNOC_X0Y32", - "port2_in", - "NOC_NPS_VNOC_X0Y32", - "port0_out", - "NOC_NPS_VNOC_X0Y30", - "port2_in", - "NOC_NPS_VNOC_X0Y30", - "port0_out", - "NOC_NPS_VNOC_X0Y28", - "port2_in", - "NOC_NPS_VNOC_X0Y28", - "port0_out", - "NOC_NPS_VNOC_X0Y26", - "port2_in", - "NOC_NPS_VNOC_X0Y26", - "port0_out", - "NOC_NPS7575_X4Y6", - "port1_in", - "NOC_NPS7575_X4Y6", - "port3_out", - "NOC_NIDB_X0Y7", - "port0_in", - "NOC_NIDB_X0Y7", - "port1_out", - "NOC_NIDB_X0Y5", - "port1_in", - "NOC_NIDB_X0Y5", - "port0_out", - "NOC_NPS7575_X4Y4", - "port3_in", - "NOC_NPS7575_X4Y4", - "port1_out", - "NOC_NPS_VNOC_X0Y24", - "port2_in", - "NOC_NPS_VNOC_X0Y24", - "port0_out", - "NOC_NPS_VNOC_X0Y22", - "port2_in", - "NOC_NPS_VNOC_X0Y22", - "port0_out", - "NOC_NPS_VNOC_X0Y20", - "port2_in", - "NOC_NPS_VNOC_X0Y20", - "port0_out", - "NOC_NPS_VNOC_X0Y18", - "port2_in", - "NOC_NPS_VNOC_X0Y18", - "port0_out", - "NOC_NPS_VNOC_X0Y16", - "port2_in", - "NOC_NPS_VNOC_X0Y16", - "port0_out", - "NOC_NPS_VNOC_X0Y14", - "port2_in", - "NOC_NPS_VNOC_X0Y14", - "port0_out", - "NOC_NPS7575_X4Y2", - "port1_in", - "NOC_NPS7575_X4Y2", - "port3_out", - "NOC_NIDB_X0Y3", - "port0_in", - "NOC_NIDB_X0Y3", - "port1_out", - "NOC_NIDB_X0Y1", - "port1_in", - "NOC_NIDB_X0Y1", - "port0_out", - "NOC_NPS7575_X0Y0", - "port3_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 125 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/M00_AXI_nsu", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 5, - "WriteBW": 5, - "ReadAchievedBW": 5, - "WriteAchievedBW": 5, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port1_out", - "NOC_NPS5555_X7Y1", - "port3_in", - "NOC_NPS5555_X7Y1", - "port2_out", - "NOC_NPS_VNOC_X0Y0", - "port0_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port0_out", - "NOC_NPS5555_X7Y1", - "port2_in", - "NOC_NPS5555_X7Y1", - "port3_out", - "NOC_NPS5555_X7Y2", - "port1_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 22 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT3", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port1_out", - "NOC_NPS4_X6Y1", - "portSideB3_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port1_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port2_out", - "NOC_NPS5555_X3Y1", - "port0_in", - "NOC_NPS5555_X3Y1", - "port2_out", - "NOC_NPS5555_X5Y1", - "port0_in", - "NOC_NPS5555_X5Y1", - "port2_out", - "NOC_NPS5555_X7Y2", - "port0_in", - "NOC_NPS5555_X7Y2", - "port2_out", - "NOC_NPS5555_X9Y2", - "port0_in", - "NOC_NPS5555_X9Y2", - "port2_out", - "NOC_NPS5555_X11Y2", - "port0_in", - "NOC_NPS5555_X11Y2", - "port1_out", - "NOC_NPS5555_X11Y1", - "port3_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port4_out", - "NOC_NPS4_X6Y1", - "portSideA1_in", - "NOC_NPS4_X6Y1", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port1_in" - ], - "RequiredBW": 165, - "AchievedBW": 165, - "RequiredLatency": 300, - "AchievedLatency": 137 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port1_out", - "NOC_NPS4_X6Y1", - "portSideB3_in", - "NOC_NPS4_X6Y1", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port4_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port3_out", - "NOC_NPS5555_X11Y2", - "port1_in", - "NOC_NPS5555_X11Y2", - "port0_out", - "NOC_NPS5555_X9Y2", - "port2_in", - "NOC_NPS5555_X9Y2", - "port0_out", - "NOC_NPS5555_X7Y2", - "port2_in", - "NOC_NPS5555_X7Y2", - "port0_out", - "NOC_NPS5555_X5Y1", - "port2_in", - "NOC_NPS5555_X5Y1", - "port0_out", - "NOC_NPS5555_X3Y1", - "port2_in", - "NOC_NPS5555_X3Y1", - "port0_out", - "NOC_NPS5555_X1Y1", - "port2_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 33, - "AchievedBW": 33, - "RequiredLatency": 300, - "AchievedLatency": 137 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X0Y0", - "Port1_resp", - "NOC_NPS5555_X2Y1", - "port3_in", - "NOC_NPS5555_X2Y1", - "port0_out", - "NOC_NPS5555_X0Y1", - "port2_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 16 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port2_out", - "NOC_NPS5555_X2Y1", - "port0_in", - "NOC_NPS5555_X2Y1", - "port3_out", - "DDRMC_X0Y0", - "Port1_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 16 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port2_out", - "NOC_NPS5555_X2Y1", - "port0_in", - "NOC_NPS5555_X2Y1", - "port3_out", - "DDRMC_X0Y0", - "Port1_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 16 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port1_resp", - "NOC_NPS5555_X2Y1", - "port3_in", - "NOC_NPS5555_X2Y1", - "port0_out", - "NOC_NPS5555_X0Y1", - "port2_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 16 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S01_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT1", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X1Y0", - "Port1_resp", - "NOC_NPS5555_X8Y2", - "port3_in", - "NOC_NPS5555_X8Y2", - "port0_out", - "NOC_NPS5555_X6Y2", - "port2_in", - "NOC_NPS5555_X6Y2", - "port0_out", - "NOC_NPS5555_X4Y1", - "port2_in", - "NOC_NPS5555_X4Y1", - "port0_out", - "NOC_NPS5555_X2Y1", - "port2_in", - "NOC_NPS5555_X2Y1", - "port0_out", - "NOC_NPS5555_X0Y1", - "port2_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port2_out", - "NOC_NPS5555_X2Y1", - "port0_in", - "NOC_NPS5555_X2Y1", - "port2_out", - "NOC_NPS5555_X4Y1", - "port0_in", - "NOC_NPS5555_X4Y1", - "port2_out", - "NOC_NPS5555_X6Y2", - "port0_in", - "NOC_NPS5555_X6Y2", - "port2_out", - "NOC_NPS5555_X8Y2", - "port0_in", - "NOC_NPS5555_X8Y2", - "port3_out", - "DDRMC_X1Y0", - "Port1_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y1", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 1, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y1", - "req_out", - "NOC_NPS5555_X1Y1", - "port1_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port2_out", - "NOC_NPS5555_X2Y1", - "port0_in", - "NOC_NPS5555_X2Y1", - "port2_out", - "NOC_NPS5555_X4Y1", - "port0_in", - "NOC_NPS5555_X4Y1", - "port2_out", - "NOC_NPS5555_X6Y2", - "port0_in", - "NOC_NPS5555_X6Y2", - "port2_out", - "NOC_NPS5555_X8Y2", - "port0_in", - "NOC_NPS5555_X8Y2", - "port3_out", - "DDRMC_X1Y0", - "Port1_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 22 - }, - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y1", - "VC": 3, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X1Y0", - "Port1_resp", - "NOC_NPS5555_X8Y2", - "port3_in", - "NOC_NPS5555_X8Y2", - "port0_out", - "NOC_NPS5555_X6Y2", - "port2_in", - "NOC_NPS5555_X6Y2", - "port0_out", - "NOC_NPS5555_X4Y1", - "port2_in", - "NOC_NPS5555_X4Y1", - "port0_out", - "NOC_NPS5555_X2Y1", - "port2_in", - "NOC_NPS5555_X2Y1", - "port0_out", - "NOC_NPS5555_X0Y1", - "port2_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port1_out", - "NOC_NMU128_X0Y1", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 22 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S02_AXI_nmu", - "FromLocked": true, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y2", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port0_out", - "NOC_NMU128_X0Y2", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 24 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y2", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y2", - "req_out", - "NOC_NPS5555_X1Y1", - "port0_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 24 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y2", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y2", - "req_out", - "NOC_NPS5555_X1Y1", - "port0_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 24 - }, - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y2", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port0_out", - "NOC_NMU128_X0Y2", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 24 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S02_AXI_nmu", - "FromLocked": true, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y2", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port0_out", - "NOC_NMU128_X0Y2", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y2", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y2", - "req_out", - "NOC_NPS5555_X1Y1", - "port0_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y2", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y2", - "req_out", - "NOC_NPS5555_X1Y1", - "port0_in", - "NOC_NPS5555_X1Y1", - "port3_out", - "NOC_NPS5555_X0Y1", - "port3_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y2", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port3_out", - "NOC_NPS5555_X1Y1", - "port3_in", - "NOC_NPS5555_X1Y1", - "port0_out", - "NOC_NMU128_X0Y2", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S03_AXI_rpu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y3", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port1_out", - "NOC_NMU128_X0Y3", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y3", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU128_X0Y3", - "req_out", - "NOC_NPS5555_X1Y0", - "port1_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "NOC_NMU128_X0Y3", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU128_X0Y3", - "req_out", - "NOC_NPS5555_X1Y0", - "port1_in", - "NOC_NPS5555_X1Y0", - "port0_out", - "NOC_NPS5555_X0Y1", - "port0_in", - "NOC_NPS5555_X0Y1", - "port1_out", - "NOC_NPS5555_X0Y0", - "port3_in", - "NOC_NPS5555_X0Y0", - "port2_out", - "NOC_NPS5555_X2Y0", - "port0_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 18 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU128_X0Y3", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port0_out", - "NOC_NPS5555_X0Y0", - "port2_in", - "NOC_NPS5555_X0Y0", - "port3_out", - "NOC_NPS5555_X0Y1", - "port1_in", - "NOC_NPS5555_X0Y1", - "port0_out", - "NOC_NPS5555_X1Y0", - "port0_in", - "NOC_NPS5555_X1Y0", - "port1_out", - "NOC_NMU128_X0Y3", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 18 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X10Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB1_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB1_out", - "HBM_MC_X10Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X10Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB1_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", - "port2_out", - "NOC_NPS5555_X8Y4", - "port0_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", - "port3_out", - "NOC_NPS5555_X7Y3", - "port0_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", - "port0_in", - "NOC_NPS6_X5Y0", - "port3_out", - "NOC_NPS6_X6Y0", - "port0_in", - "NOC_NPS6_X6Y0", - "port3_out", - "NOC_NPS5555_X8Y3", - "port0_in", - "NOC_NPS5555_X8Y3", - "port1_out", - "NOC_NPS6_X7Y0", - "port0_in", - "NOC_NPS6_X7Y0", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB2_out", - "HBM_MC_X15Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB2_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X10Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", - "portSideA2_out", - "NOC_NPS6_X5Y2", - "port5_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA2_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X10Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", - "port3_out", - "NOC_NPS5555_X7Y3", - "port0_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", - "port0_in", - "NOC_NPS6_X5Y0", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA0_in", - "NOC_NPS4_X5Y0", - "portSideB0_out", - "HBM_MC_X10Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X10Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X10Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB0_in", - "NOC_NPS4_X5Y0", - "portSideA0_out", - "NOC_NPS6_X5Y0", - "port5_in", - "NOC_NPS6_X5Y0", - "port0_out", - "NOC_NPS5555_X7Y3", - "port1_in", - "NOC_NPS5555_X7Y3", - "port0_out", - "NOC_NPS6_X4Y0", - "port3_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA0_in", - "NOC_NPS4_X2Y0", - "portSideB2_out", - "HBM_MC_X5Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB2_in", - "NOC_NPS4_X2Y0", - "portSideA0_out", - "NOC_NPS6_X2Y0", - "port5_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X15Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB3_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", - "port2_out", - "NOC_NPS5555_X8Y4", - "port0_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port0_out", - "NOC_NPS5555_X8Y3", - "port2_in", - "NOC_NPS5555_X8Y3", - "port1_out", - "NOC_NPS6_X7Y0", - "port0_in", - "NOC_NPS6_X7Y0", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X15Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB3_out", - "HBM_MC_X15Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 35 - }, - { - "PhyInstanceStart": "HBM_MC_X15Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X15Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB3_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 35 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", - "portSideA0_out", - "NOC_NPS6_X2Y0", - "port5_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA0_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X5Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA1_in", - "NOC_NPS4_X2Y0", - "portSideB3_out", - "HBM_MC_X5Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X5Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X5Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB3_in", - "NOC_NPS4_X2Y0", - "portSideA1_out", - "NOC_NPS6_X2Y1", - "port5_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB2_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB2_out", - "HBM_MC_X1Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB2_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA0_out", - "NOC_NPS6_X0Y0", - "port5_in", - "NOC_NPS6_X0Y0", - "port3_out", - "NOC_NPS5555_X5Y3", - "port0_in", - "NOC_NPS5555_X5Y3", - "port1_out", - "NOC_NPS6_X1Y0", - "port0_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port0_out", - "NOC_NPS5555_X5Y3", - "port1_in", - "NOC_NPS5555_X5Y3", - "port0_out", - "NOC_NPS6_X0Y0", - "port3_in", - "NOC_NPS6_X0Y0", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA0_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port0_out", - "NOC_NPS5555_X5Y4", - "port2_in", - "NOC_NPS5555_X5Y4", - "port1_out", - "NOC_NPS6_X0Y1", - "port3_in", - "NOC_NPS6_X0Y1", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA1_in", - "NOC_NPS4_X0Y0", - "portSideB3_out", - "HBM_MC_X1Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "HBM_MC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X1Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB3_in", - "NOC_NPS4_X0Y0", - "portSideA1_out", - "NOC_NPS6_X0Y1", - "port5_in", - "NOC_NPS6_X0Y1", - "port3_out", - "NOC_NPS5555_X5Y4", - "port1_in", - "NOC_NPS5555_X5Y4", - "port2_out", - "NOC_NPS6_X1Y1", - "port0_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X6Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB0_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB0_out", - "HBM_MC_X6Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X6Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB0_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA2_in", - "NOC_NPS4_X6Y0", - "portSideB0_out", - "HBM_MC_X12Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 33 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB0_in", - "NOC_NPS4_X6Y0", - "portSideA2_out", - "NOC_NPS6_X6Y2", - "port5_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 33 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB1_in", - "NOC_NPS4_X0Y0", - "portSideA1_out", - "NOC_NPS6_X0Y1", - "port5_in", - "NOC_NPS6_X0Y1", - "port3_out", - "NOC_NPS5555_X5Y4", - "port1_in", - "NOC_NPS5555_X5Y4", - "port2_out", - "NOC_NPS6_X1Y1", - "port0_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port0_out", - "NOC_NPS5555_X5Y4", - "port2_in", - "NOC_NPS5555_X5Y4", - "port1_out", - "NOC_NPS6_X0Y1", - "port3_in", - "NOC_NPS6_X0Y1", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA1_in", - "NOC_NPS4_X0Y0", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port0_out", - "NOC_NPS5555_X5Y3", - "port1_in", - "NOC_NPS5555_X5Y3", - "port0_out", - "NOC_NPS6_X0Y0", - "port3_in", - "NOC_NPS6_X0Y0", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA0_in", - "NOC_NPS4_X0Y0", - "portSideB1_out", - "HBM_MC_X0Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc1_port0_out", - "NOC_NPS4_X0Y0", - "portSideB1_in", - "NOC_NPS4_X0Y0", - "portSideA0_out", - "NOC_NPS6_X0Y0", - "port5_in", - "NOC_NPS6_X0Y0", - "port3_out", - "NOC_NPS5555_X5Y3", - "port0_in", - "NOC_NPS5555_X5Y3", - "port1_out", - "NOC_NPS6_X1Y0", - "port0_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X6Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB1_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X6Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA0_in", - "NOC_NPS4_X3Y0", - "portSideB1_out", - "HBM_MC_X6Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X6Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X6Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB1_in", - "NOC_NPS4_X3Y0", - "portSideA0_out", - "NOC_NPS6_X3Y0", - "port5_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB1_in", - "NOC_NPS4_X7Y0", - "portSideA1_out", - "NOC_NPS6_X7Y1", - "port5_in", - "NOC_NPS6_X7Y1", - "port0_out", - "NOC_NPS5555_X8Y4", - "port2_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 35 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port2_out", - "NOC_NPS6_X7Y1", - "port0_in", - "NOC_NPS6_X7Y1", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA1_in", - "NOC_NPS4_X7Y0", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 35 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port3_out", - "NOC_NPS5555_X8Y4", - "port1_in", - "NOC_NPS5555_X8Y4", - "port0_out", - "NOC_NPS5555_X8Y3", - "port2_in", - "NOC_NPS5555_X8Y3", - "port1_out", - "NOC_NPS6_X7Y0", - "port0_in", - "NOC_NPS6_X7Y0", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB1_out", - "HBM_MC_X14Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc1_port0_out", - "NOC_NPS4_X7Y0", - "portSideB1_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", - "port2_out", - "NOC_NPS5555_X8Y4", - "port0_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X12Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB1_out", - "HBM_MC_X12Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X12Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X12Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB1_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB0_in", - "NOC_NPS4_X0Y0", - "portSideA0_out", - "NOC_NPS6_X0Y0", - "port5_in", - "NOC_NPS6_X0Y0", - "port3_out", - "NOC_NPS5555_X5Y3", - "port0_in", - "NOC_NPS5555_X5Y3", - "port1_out", - "NOC_NPS6_X1Y0", - "port0_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port0_out", - "NOC_NPS5555_X5Y3", - "port1_in", - "NOC_NPS5555_X5Y3", - "port0_out", - "NOC_NPS6_X0Y0", - "port3_in", - "NOC_NPS6_X0Y0", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA0_in", - "NOC_NPS4_X0Y0", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port0_out", - "NOC_NPS6_X1Y2", - "port3_in", - "NOC_NPS6_X1Y2", - "port0_out", - "NOC_NPS5555_X5Y6", - "port2_in", - "NOC_NPS5555_X5Y6", - "port1_out", - "NOC_NPS6_X0Y2", - "port3_in", - "NOC_NPS6_X0Y2", - "port5_out", - "NOC_NPS4_X0Y0", - "portSideA2_in", - "NOC_NPS4_X0Y0", - "portSideB0_out", - "HBM_MC_X0Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X0Y0", - "pc0_port0_out", - "NOC_NPS4_X0Y0", - "portSideB0_in", - "NOC_NPS4_X0Y0", - "portSideA2_out", - "NOC_NPS6_X0Y2", - "port5_in", - "NOC_NPS6_X0Y2", - "port3_out", - "NOC_NPS5555_X5Y6", - "port1_in", - "NOC_NPS5555_X5Y6", - "port2_out", - "NOC_NPS6_X1Y2", - "port0_in", - "NOC_NPS6_X1Y2", - "port3_out", - "NOC_NPS6_X2Y2", - "port0_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB0_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA0_in", - "NOC_NPS4_X4Y0", - "portSideB0_out", - "HBM_MC_X8Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB0_in", - "NOC_NPS4_X4Y0", - "portSideA0_out", - "NOC_NPS6_X4Y0", - "port5_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X8Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA1_in", - "NOC_NPS4_X4Y0", - "portSideB1_out", - "HBM_MC_X8Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X8Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X8Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB1_in", - "NOC_NPS4_X4Y0", - "portSideA1_out", - "NOC_NPS6_X4Y1", - "port5_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X14Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", - "portSideA2_out", - "NOC_NPS6_X7Y2", - "port5_in", - "NOC_NPS6_X7Y2", - "port0_out", - "NOC_NPS5555_X8Y6", - "port2_in", - "NOC_NPS5555_X8Y6", - "port1_out", - "NOC_NPS6_X6Y2", - "port3_in", - "NOC_NPS6_X6Y2", - "port0_out", - "NOC_NPS6_X5Y2", - "port3_in", - "NOC_NPS6_X5Y2", - "port0_out", - "NOC_NPS5555_X7Y6", - "port2_in", - "NOC_NPS5555_X7Y6", - "port1_out", - "NOC_NPS6_X4Y2", - "port3_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port3_out", - "NOC_NPS5555_X7Y6", - "port1_in", - "NOC_NPS5555_X7Y6", - "port2_out", - "NOC_NPS6_X5Y2", - "port0_in", - "NOC_NPS6_X5Y2", - "port3_out", - "NOC_NPS6_X6Y2", - "port0_in", - "NOC_NPS6_X6Y2", - "port3_out", - "NOC_NPS5555_X8Y6", - "port1_in", - "NOC_NPS5555_X8Y6", - "port2_out", - "NOC_NPS6_X7Y2", - "port0_in", - "NOC_NPS6_X7Y2", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA2_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X14Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port0_out", - "NOC_NPS5555_X7Y3", - "port2_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", - "port0_in", - "NOC_NPS6_X5Y0", - "port3_out", - "NOC_NPS6_X6Y0", - "port0_in", - "NOC_NPS6_X6Y0", - "port3_out", - "NOC_NPS5555_X8Y3", - "port0_in", - "NOC_NPS5555_X8Y3", - "port1_out", - "NOC_NPS6_X7Y0", - "port0_in", - "NOC_NPS6_X7Y0", - "port5_out", - "NOC_NPS4_X7Y0", - "portSideA0_in", - "NOC_NPS4_X7Y0", - "portSideB0_out", - "HBM_MC_X14Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 37 - }, - { - "PhyInstanceStart": "HBM_MC_X14Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X14Y0", - "pc0_port0_out", - "NOC_NPS4_X7Y0", - "portSideB0_in", - "NOC_NPS4_X7Y0", - "portSideA0_out", - "NOC_NPS6_X7Y0", - "port5_in", - "NOC_NPS6_X7Y0", - "port0_out", - "NOC_NPS5555_X8Y3", - "port1_in", - "NOC_NPS5555_X8Y3", - "port2_out", - "NOC_NPS5555_X8Y4", - "port0_in", - "NOC_NPS5555_X8Y4", - "port1_out", - "NOC_NPS6_X6Y1", - "port3_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 37 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB2_in", - "NOC_NPS4_X1Y0", - "portSideA0_out", - "NOC_NPS6_X1Y0", - "port5_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA0_in", - "NOC_NPS4_X1Y0", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB2_out", - "HBM_MC_X3Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB2_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X3Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB3_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X3Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB3_out", - "HBM_MC_X3Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X3Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X3Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB3_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB1_in", - "NOC_NPS4_X2Y0", - "portSideA1_out", - "NOC_NPS6_X2Y1", - "port5_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA1_in", - "NOC_NPS4_X2Y0", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA1_in", - "NOC_NPS4_X2Y0", - "portSideB1_out", - "HBM_MC_X4Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc1_port0_out", - "NOC_NPS4_X2Y0", - "portSideB1_in", - "NOC_NPS4_X2Y0", - "portSideA1_out", - "NOC_NPS6_X2Y1", - "port5_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", - "portSideA2_out", - "NOC_NPS6_X2Y2", - "port5_in", - "NOC_NPS6_X2Y2", - "port3_out", - "NOC_NPS5555_X6Y6", - "port1_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port1_out", - "NOC_NPS6_X2Y2", - "port3_in", - "NOC_NPS6_X2Y2", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA2_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X4Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port5_out", - "NOC_NPS4_X2Y0", - "portSideA0_in", - "NOC_NPS4_X2Y0", - "portSideB0_out", - "HBM_MC_X4Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X4Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X4Y0", - "pc0_port0_out", - "NOC_NPS4_X2Y0", - "portSideB0_in", - "NOC_NPS4_X2Y0", - "portSideA0_out", - "NOC_NPS6_X2Y0", - "port5_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA1_in", - "NOC_NPS4_X4Y0", - "portSideB2_out", - "HBM_MC_X9Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc0_port0_out", - "NOC_NPS4_X4Y0", - "portSideB2_in", - "NOC_NPS4_X4Y0", - "portSideA1_out", - "NOC_NPS6_X4Y1", - "port5_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port0_out", - "NOC_NPS6_X2Y0", - "port3_in", - "NOC_NPS6_X2Y0", - "port0_out", - "NOC_NPS6_X1Y0", - "port3_in", - "NOC_NPS6_X1Y0", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA0_in", - "NOC_NPS4_X1Y0", - "portSideB0_out", - "HBM_MC_X2Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc0_port0_out", - "NOC_NPS4_X1Y0", - "portSideB0_in", - "NOC_NPS4_X1Y0", - "portSideA0_out", - "NOC_NPS6_X1Y0", - "port5_in", - "NOC_NPS6_X1Y0", - "port3_out", - "NOC_NPS6_X2Y0", - "port0_in", - "NOC_NPS6_X2Y0", - "port3_out", - "NOC_NPS5555_X6Y3", - "port0_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", - "port3_out", - "NOC_NPS5555_X7Y3", - "port0_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", - "port0_in", - "NOC_NPS6_X5Y0", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA0_in", - "NOC_NPS4_X5Y0", - "portSideB2_out", - "HBM_MC_X11Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc0_port0_out", - "NOC_NPS4_X5Y0", - "portSideB2_in", - "NOC_NPS4_X5Y0", - "portSideA0_out", - "NOC_NPS6_X5Y0", - "port5_in", - "NOC_NPS6_X5Y0", - "port0_out", - "NOC_NPS5555_X7Y3", - "port1_in", - "NOC_NPS5555_X7Y3", - "port0_out", - "NOC_NPS6_X4Y0", - "port3_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB3_in", - "NOC_NPS4_X4Y0", - "portSideA2_out", - "NOC_NPS6_X4Y2", - "port5_in", - "NOC_NPS6_X4Y2", - "port0_out", - "NOC_NPS6_X3Y2", - "port3_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port3_out", - "NOC_NPS6_X4Y2", - "port0_in", - "NOC_NPS6_X4Y2", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA2_in", - "NOC_NPS4_X4Y0", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X9Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", - "port5_out", - "NOC_NPS4_X4Y0", - "portSideA0_in", - "NOC_NPS4_X4Y0", - "portSideB3_out", - "HBM_MC_X9Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 27 - }, - { - "PhyInstanceStart": "HBM_MC_X9Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X9Y0", - "pc1_port0_out", - "NOC_NPS4_X4Y0", - "portSideB3_in", - "NOC_NPS4_X4Y0", - "portSideA0_out", - "NOC_NPS6_X4Y0", - "port5_in", - "NOC_NPS6_X4Y0", - "port0_out", - "NOC_NPS6_X3Y0", - "port3_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 27 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB3_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X11Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port5_out", - "NOC_NPS4_X5Y0", - "portSideA1_in", - "NOC_NPS4_X5Y0", - "portSideB3_out", - "HBM_MC_X11Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 29 - }, - { - "PhyInstanceStart": "HBM_MC_X11Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X11Y0", - "pc1_port0_out", - "NOC_NPS4_X5Y0", - "portSideB3_in", - "NOC_NPS4_X5Y0", - "portSideA1_out", - "NOC_NPS6_X5Y1", - "port5_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 29 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB3_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA1_in", - "NOC_NPS4_X3Y0", - "portSideB3_out", - "HBM_MC_X7Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 23 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc1_port0_out", - "NOC_NPS4_X3Y0", - "portSideB3_in", - "NOC_NPS4_X3Y0", - "portSideA1_out", - "NOC_NPS6_X3Y1", - "port5_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 23 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA0_out", - "NOC_NPS6_X6Y0", - "port5_in", - "NOC_NPS6_X6Y0", - "port0_out", - "NOC_NPS6_X5Y0", - "port3_in", - "NOC_NPS6_X5Y0", - "port0_out", - "NOC_NPS5555_X7Y3", - "port1_in", - "NOC_NPS5555_X7Y3", - "port2_out", - "NOC_NPS5555_X7Y4", - "port0_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 33 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port3_out", - "NOC_NPS6_X4Y0", - "port0_in", - "NOC_NPS6_X4Y0", - "port3_out", - "NOC_NPS5555_X7Y3", - "port0_in", - "NOC_NPS5555_X7Y3", - "port1_out", - "NOC_NPS6_X5Y0", - "port0_in", - "NOC_NPS6_X5Y0", - "port3_out", - "NOC_NPS6_X6Y0", - "port0_in", - "NOC_NPS6_X6Y0", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA0_in", - "NOC_NPS4_X6Y0", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 33 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB3_out", - "HBM_MC_X13Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc1_port0_out", - "NOC_NPS4_X6Y0", - "portSideB3_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB2_in", - "NOC_NPS4_X3Y0", - "portSideA2_out", - "NOC_NPS6_X3Y2", - "port5_in", - "NOC_NPS6_X3Y2", - "port0_out", - "NOC_NPS5555_X6Y6", - "port2_in", - "NOC_NPS5555_X6Y6", - "port3_out", - "NOC_NCRB_X1Y0", - "port1_in", - "NOC_NCRB_X1Y0", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port2_in", - "NOC_NPS_VNOC_X1Y36", - "port1_out", - "NOC_NPS_VNOC_X1Y37", - "port1_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port1_out", - "NOC_NPS_VNOC_X1Y36", - "port1_in", - "NOC_NPS_VNOC_X1Y36", - "port2_out", - "NOC_NCRB_X1Y1", - "port1_in", - "NOC_NCRB_X1Y1", - "port1_out", - "NOC_NPS5555_X6Y6", - "port3_in", - "NOC_NPS5555_X6Y6", - "port2_out", - "NOC_NPS6_X3Y2", - "port0_in", - "NOC_NPS6_X3Y2", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA2_in", - "NOC_NPS4_X3Y0", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X7Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port0_out", - "NOC_NPS5555_X6Y3", - "port2_in", - "NOC_NPS5555_X6Y3", - "port1_out", - "NOC_NPS6_X3Y0", - "port0_in", - "NOC_NPS6_X3Y0", - "port5_out", - "NOC_NPS4_X3Y0", - "portSideA0_in", - "NOC_NPS4_X3Y0", - "portSideB2_out", - "HBM_MC_X7Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X7Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X7Y0", - "pc0_port0_out", - "NOC_NPS4_X3Y0", - "portSideB2_in", - "NOC_NPS4_X3Y0", - "portSideA0_out", - "NOC_NPS6_X3Y0", - "port5_in", - "NOC_NPS6_X3Y0", - "port0_out", - "NOC_NPS5555_X6Y3", - "port1_in", - "NOC_NPS5555_X6Y3", - "port2_out", - "NOC_NPS5555_X6Y4", - "port0_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB2_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X13Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port2_out", - "NOC_NPS6_X3Y1", - "port0_in", - "NOC_NPS6_X3Y1", - "port3_out", - "NOC_NPS6_X4Y1", - "port0_in", - "NOC_NPS6_X4Y1", - "port3_out", - "NOC_NPS5555_X7Y4", - "port1_in", - "NOC_NPS5555_X7Y4", - "port2_out", - "NOC_NPS6_X5Y1", - "port0_in", - "NOC_NPS6_X5Y1", - "port3_out", - "NOC_NPS6_X6Y1", - "port0_in", - "NOC_NPS6_X6Y1", - "port5_out", - "NOC_NPS4_X6Y0", - "portSideA1_in", - "NOC_NPS4_X6Y0", - "portSideB2_out", - "HBM_MC_X13Y0", - "pc0_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 31 - }, - { - "PhyInstanceStart": "HBM_MC_X13Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X13Y0", - "pc0_port0_out", - "NOC_NPS4_X6Y0", - "portSideB2_in", - "NOC_NPS4_X6Y0", - "portSideA1_out", - "NOC_NPS6_X6Y1", - "port5_in", - "NOC_NPS6_X6Y1", - "port0_out", - "NOC_NPS6_X5Y1", - "port3_in", - "NOC_NPS6_X5Y1", - "port0_out", - "NOC_NPS5555_X7Y4", - "port2_in", - "NOC_NPS5555_X7Y4", - "port1_out", - "NOC_NPS6_X4Y1", - "port3_in", - "NOC_NPS6_X4Y1", - "port0_out", - "NOC_NPS6_X3Y1", - "port3_in", - "NOC_NPS6_X3Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port2_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 31 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "ToLocked": false, - "Port": "PORT2", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 132, - "WriteBW": 132, - "ReadAchievedBW": 132, - "WriteAchievedBW": 132, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "HBM_MC_X2Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port0_out", - "NOC_NCRB_X1Y1", - "port0_in", - "NOC_NCRB_X1Y1", - "port0_out", - "NOC_NPS5555_X6Y4", - "port3_in", - "NOC_NPS5555_X6Y4", - "port1_out", - "NOC_NPS6_X2Y1", - "port3_in", - "NOC_NPS6_X2Y1", - "port0_out", - "NOC_NPS6_X1Y1", - "port3_in", - "NOC_NPS6_X1Y1", - "port5_out", - "NOC_NPS4_X1Y0", - "portSideA1_in", - "NOC_NPS4_X1Y0", - "portSideB1_out", - "HBM_MC_X2Y0", - "pc1_port0_in" - ], - "RequiredBW": 264, - "AchievedBW": 264, - "RequiredLatency": 300, - "AchievedLatency": 25 - }, - { - "PhyInstanceStart": "HBM_MC_X2Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "HBM_MC_X2Y0", - "pc1_port0_out", - "NOC_NPS4_X1Y0", - "portSideB1_in", - "NOC_NPS4_X1Y0", - "portSideA1_out", - "NOC_NPS6_X1Y1", - "port5_in", - "NOC_NPS6_X1Y1", - "port3_out", - "NOC_NPS6_X2Y1", - "port0_in", - "NOC_NPS6_X2Y1", - "port3_out", - "NOC_NPS5555_X6Y4", - "port1_in", - "NOC_NPS5555_X6Y4", - "port3_out", - "NOC_NCRB_X1Y0", - "port0_in", - "NOC_NCRB_X1Y0", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port0_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 132, - "AchievedBW": 132, - "RequiredLatency": 300, - "AchievedLatency": 25 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_cips/inst/M00_AXI_nsu", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 5, - "WriteBW": 5, - "ReadAchievedBW": 5, - "WriteAchievedBW": 5, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port3_out", - "NOC_NIDB_X0Y1", - "port0_in", - "NOC_NIDB_X0Y1", - "port1_out", - "NOC_NIDB_X0Y3", - "port1_in", - "NOC_NIDB_X0Y3", - "port0_out", - "NOC_NPS7575_X4Y2", - "port3_in", - "NOC_NPS7575_X4Y2", - "port1_out", - "NOC_NPS_VNOC_X0Y14", - "port0_in", - "NOC_NPS_VNOC_X0Y14", - "port2_out", - "NOC_NPS_VNOC_X0Y16", - "port0_in", - "NOC_NPS_VNOC_X0Y16", - "port2_out", - "NOC_NPS_VNOC_X0Y18", - "port0_in", - "NOC_NPS_VNOC_X0Y18", - "port2_out", - "NOC_NPS_VNOC_X0Y20", - "port0_in", - "NOC_NPS_VNOC_X0Y20", - "port2_out", - "NOC_NPS_VNOC_X0Y22", - "port0_in", - "NOC_NPS_VNOC_X0Y22", - "port2_out", - "NOC_NPS_VNOC_X0Y24", - "port0_in", - "NOC_NPS_VNOC_X0Y24", - "port1_out", - "NOC_NPS_VNOC_X0Y25", - "port1_in", - "NOC_NPS_VNOC_X0Y25", - "port0_out", - "NOC_NPS7575_X4Y5", - "port3_in", - "NOC_NPS7575_X4Y5", - "port1_out", - "NOC_NIDB_X0Y4", - "port0_in", - "NOC_NIDB_X0Y4", - "port1_out", - "NOC_NIDB_X0Y6", - "port1_in", - "NOC_NIDB_X0Y6", - "port0_out", - "NOC_NPS7575_X4Y7", - "port1_in", - "NOC_NPS7575_X4Y7", - "port2_out", - "NOC_NPP_RPTR_X0Y15", - "port0_in", - "NOC_NPP_RPTR_X0Y15", - "port0_out", - "NOC_NCRB_SSIT_X1Y6", - "port1_in", - "NOC_NCRB_SSIT_X1Y6", - "port1_out", - "NOC_NPP_RPTR_X1Y13", - "port0_in", - "NOC_NPP_RPTR_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y7", - "port0_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 117 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port1_out", - "NOC_NPS_VNOC_X1Y14", - "port1_in", - "NOC_NPS_VNOC_X1Y14", - "port0_out", - "NOC_NPS7575_X5Y2", - "port1_in", - "NOC_NPS7575_X5Y2", - "port3_out", - "NOC_NIDB_X1Y3", - "port0_in", - "NOC_NIDB_X1Y3", - "port1_out", - "NOC_NIDB_X1Y1", - "port1_in", - "NOC_NIDB_X1Y1", - "port0_out", - "NOC_NPS7575_X5Y0", - "port3_in", - "NOC_NPS7575_X5Y0", - "port0_out", - "NOC_NPP_RPTR_X1Y0", - "port1_in", - "NOC_NPP_RPTR_X1Y0", - "port1_out", - "NOC_NCRB_SSIT_X1Y0", - "port0_in", - "NOC_NCRB_SSIT_X1Y0", - "port0_out", - "NOC_NPP_RPTR_X0Y2", - "port1_in", - "NOC_NPP_RPTR_X0Y2", - "port1_out", - "NOC_NPS7575_X0Y0", - "port2_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 117 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "NOC_NSU512_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port1_out", - "NOC_NPS_VNOC_X1Y14", - "port1_in", - "NOC_NPS_VNOC_X1Y14", - "port0_out", - "NOC_NPS7575_X5Y2", - "port1_in", - "NOC_NPS7575_X5Y2", - "port3_out", - "NOC_NIDB_X1Y3", - "port0_in", - "NOC_NIDB_X1Y3", - "port1_out", - "NOC_NIDB_X1Y1", - "port1_in", - "NOC_NIDB_X1Y1", - "port0_out", - "NOC_NPS7575_X5Y0", - "port3_in", - "NOC_NPS7575_X5Y0", - "port0_out", - "NOC_NPP_RPTR_X1Y0", - "port1_in", - "NOC_NPP_RPTR_X1Y0", - "port1_out", - "NOC_NCRB_SSIT_X1Y0", - "port0_in", - "NOC_NCRB_SSIT_X1Y0", - "port0_out", - "NOC_NPP_RPTR_X0Y2", - "port1_in", - "NOC_NPP_RPTR_X0Y2", - "port1_out", - "NOC_NPS7575_X0Y0", - "port2_in", - "NOC_NPS7575_X0Y0", - "port1_out", - "NOC_NPS_VNOC_X0Y12", - "port2_in", - "NOC_NPS_VNOC_X0Y12", - "port0_out", - "NOC_NPS_VNOC_X0Y10", - "port2_in", - "NOC_NPS_VNOC_X0Y10", - "port0_out", - "NOC_NPS_VNOC_X0Y8", - "port2_in", - "NOC_NPS_VNOC_X0Y8", - "port0_out", - "NOC_NPS_VNOC_X0Y6", - "port2_in", - "NOC_NPS_VNOC_X0Y6", - "port0_out", - "NOC_NPS_VNOC_X0Y4", - "port2_in", - "NOC_NPS_VNOC_X0Y4", - "port0_out", - "NOC_NPS_VNOC_X0Y2", - "port2_in", - "NOC_NPS_VNOC_X0Y2", - "port0_out", - "NOC_NPS_VNOC_X0Y0", - "port2_in", - "NOC_NPS_VNOC_X0Y0", - "port3_out", - "NOC_NSU512_X0Y0", - "req" - ], - "RequiredBW": 5, - "AchievedBW": 5, - "RequiredLatency": 300, - "AchievedLatency": 117 - }, - { - "PhyInstanceStart": "NOC_NSU512_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "NOC_NSU512_X0Y0", - "resp", - "NOC_NPS_VNOC_X0Y0", - "port3_in", - "NOC_NPS_VNOC_X0Y0", - "port2_out", - "NOC_NPS_VNOC_X0Y2", - "port0_in", - "NOC_NPS_VNOC_X0Y2", - "port2_out", - "NOC_NPS_VNOC_X0Y4", - "port0_in", - "NOC_NPS_VNOC_X0Y4", - "port2_out", - "NOC_NPS_VNOC_X0Y6", - "port0_in", - "NOC_NPS_VNOC_X0Y6", - "port2_out", - "NOC_NPS_VNOC_X0Y8", - "port0_in", - "NOC_NPS_VNOC_X0Y8", - "port2_out", - "NOC_NPS_VNOC_X0Y10", - "port0_in", - "NOC_NPS_VNOC_X0Y10", - "port2_out", - "NOC_NPS_VNOC_X0Y12", - "port0_in", - "NOC_NPS_VNOC_X0Y12", - "port2_out", - "NOC_NPS7575_X0Y0", - "port1_in", - "NOC_NPS7575_X0Y0", - "port2_out", - "NOC_NPP_RPTR_X0Y2", - "port0_in", - "NOC_NPP_RPTR_X0Y2", - "port0_out", - "NOC_NCRB_SSIT_X1Y1", - "port0_in", - "NOC_NCRB_SSIT_X1Y1", - "port0_out", - "NOC_NPP_RPTR_X1Y0", - "port0_in", - "NOC_NPP_RPTR_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y0", - "port0_in", - "NOC_NPS7575_X5Y0", - "port3_out", - "NOC_NIDB_X1Y1", - "port0_in", - "NOC_NIDB_X1Y1", - "port1_out", - "NOC_NIDB_X1Y3", - "port1_in", - "NOC_NIDB_X1Y3", - "port0_out", - "NOC_NPS7575_X5Y2", - "port3_in", - "NOC_NPS7575_X5Y2", - "port1_out", - "NOC_NPS_VNOC_X1Y14", - "port0_in", - "NOC_NPS_VNOC_X1Y14", - "port2_out", - "NOC_NPS_VNOC_X1Y16", - "port0_in", - "NOC_NPS_VNOC_X1Y16", - "port2_out", - "NOC_NPS_VNOC_X1Y18", - "port0_in", - "NOC_NPS_VNOC_X1Y18", - "port2_out", - "NOC_NPS_VNOC_X1Y20", - "port0_in", - "NOC_NPS_VNOC_X1Y20", - "port2_out", - "NOC_NPS_VNOC_X1Y22", - "port0_in", - "NOC_NPS_VNOC_X1Y22", - "port2_out", - "NOC_NPS_VNOC_X1Y24", - "port0_in", - "NOC_NPS_VNOC_X1Y24", - "port2_out", - "NOC_NPS7575_X5Y4", - "port1_in", - "NOC_NPS7575_X5Y4", - "port3_out", - "NOC_NIDB_X1Y5", - "port0_in", - "NOC_NIDB_X1Y5", - "port1_out", - "NOC_NIDB_X1Y7", - "port1_in", - "NOC_NIDB_X1Y7", - "port0_out", - "NOC_NPS7575_X5Y6", - "port3_in", - "NOC_NPS7575_X5Y6", - "port1_out", - "NOC_NPS_VNOC_X1Y26", - "port0_in", - "NOC_NPS_VNOC_X1Y26", - "port2_out", - "NOC_NPS_VNOC_X1Y28", - "port0_in", - "NOC_NPS_VNOC_X1Y28", - "port2_out", - "NOC_NPS_VNOC_X1Y30", - "port0_in", - "NOC_NPS_VNOC_X1Y30", - "port2_out", - "NOC_NPS_VNOC_X1Y32", - "port0_in", - "NOC_NPS_VNOC_X1Y32", - "port2_out", - "NOC_NPS_VNOC_X1Y34", - "port0_in", - "NOC_NPS_VNOC_X1Y34", - "port1_out", - "NOC_NPS_VNOC_X1Y35", - "port1_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 1, - "AchievedBW": 1, - "RequiredLatency": 300, - "AchievedLatency": 117 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port2_out", - "NOC_NPS5555_X10Y0", - "port0_in", - "NOC_NPS5555_X10Y0", - "port3_out", - "NOC_NPS5555_X10Y1", - "port1_in", - "NOC_NPS5555_X10Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port0_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 112 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port0_out", - "NOC_NPS5555_X10Y1", - "port2_in", - "NOC_NPS5555_X10Y1", - "port1_out", - "NOC_NPS5555_X10Y0", - "port3_in", - "NOC_NPS5555_X10Y0", - "port0_out", - "NOC_NPS5555_X8Y0", - "port2_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 112 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X1Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port0_out", - "NOC_NPS5555_X10Y1", - "port2_in", - "NOC_NPS5555_X10Y1", - "port1_out", - "NOC_NPS5555_X10Y0", - "port3_in", - "NOC_NPS5555_X10Y0", - "port0_out", - "NOC_NPS5555_X8Y0", - "port2_in", - "NOC_NPS5555_X8Y0", - "port1_out", - "DDRMC_X1Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 112 - }, - { - "PhyInstanceStart": "DDRMC_X1Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X1Y0", - "Port0_resp", - "NOC_NPS5555_X8Y0", - "port1_in", - "NOC_NPS5555_X8Y0", - "port2_out", - "NOC_NPS5555_X10Y0", - "port0_in", - "NOC_NPS5555_X10Y0", - "port3_out", - "NOC_NPS5555_X10Y1", - "port1_in", - "NOC_NPS5555_X10Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port0_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 112 - } - ] - }, - { - "Phase": 0, - "From": "axi_noc_cips/inst/S04_AXI_nmu", - "FromLocked": false, - "To": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "ToLocked": false, - "Port": "PORT0", - "ReadTC": "BE", - "WriteTC": "BE", - "ReadBW": 800, - "WriteBW": 800, - "ReadAchievedBW": 800, - "WriteAchievedBW": 800, - "ReadLatency": 300, - "WriteLatency": 300, - "ReadBestPossibleLatency": 300, - "WriteBestPossibleLatency": 300, - "PathLocked": true, - "Nets": [ - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 6, - "CommType": "READ", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port2_out", - "NOC_NPS5555_X10Y0", - "port0_in", - "NOC_NPS5555_X10Y0", - "port3_out", - "NOC_NPS5555_X10Y1", - "port1_in", - "NOC_NPS5555_X10Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port0_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 800, - "AchievedBW": 800, - "RequiredLatency": 300, - "AchievedLatency": 118 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 4, - "CommType": "READ_REQ", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port0_out", - "NOC_NPS5555_X10Y1", - "port2_in", - "NOC_NPS5555_X10Y1", - "port1_out", - "NOC_NPS5555_X10Y0", - "port3_in", - "NOC_NPS5555_X10Y0", - "port0_out", - "NOC_NPS5555_X8Y0", - "port2_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 118 - }, - { - "PhyInstanceStart": "NOC_NMU512_X1Y18", - "PhyInstanceEnd": "DDRMC_X0Y0", - "VC": 5, - "CommType": "WRITE", - "Connections": [ - "NOC_NMU512_X1Y18", - "req_out", - "NOC_NPS_VNOC_X1Y37", - "port3_in", - "NOC_NPS_VNOC_X1Y37", - "port2_out", - "NOC_NPS_VNOC_X1Y35", - "port0_in", - "NOC_NPS_VNOC_X1Y35", - "port2_out", - "NOC_NPS_VNOC_X1Y33", - "port0_in", - "NOC_NPS_VNOC_X1Y33", - "port2_out", - "NOC_NPS_VNOC_X1Y31", - "port0_in", - "NOC_NPS_VNOC_X1Y31", - "port2_out", - "NOC_NPS_VNOC_X1Y29", - "port0_in", - "NOC_NPS_VNOC_X1Y29", - "port2_out", - "NOC_NPS_VNOC_X1Y27", - "port0_in", - "NOC_NPS_VNOC_X1Y27", - "port2_out", - "NOC_NPS7575_X5Y7", - "port3_in", - "NOC_NPS7575_X5Y7", - "port1_out", - "NOC_NIDB_X1Y6", - "port0_in", - "NOC_NIDB_X1Y6", - "port1_out", - "NOC_NIDB_X1Y4", - "port1_in", - "NOC_NIDB_X1Y4", - "port0_out", - "NOC_NPS7575_X5Y5", - "port1_in", - "NOC_NPS7575_X5Y5", - "port3_out", - "NOC_NPS_VNOC_X1Y25", - "port0_in", - "NOC_NPS_VNOC_X1Y25", - "port2_out", - "NOC_NPS_VNOC_X1Y23", - "port0_in", - "NOC_NPS_VNOC_X1Y23", - "port2_out", - "NOC_NPS_VNOC_X1Y21", - "port0_in", - "NOC_NPS_VNOC_X1Y21", - "port2_out", - "NOC_NPS_VNOC_X1Y19", - "port0_in", - "NOC_NPS_VNOC_X1Y19", - "port2_out", - "NOC_NPS_VNOC_X1Y17", - "port0_in", - "NOC_NPS_VNOC_X1Y17", - "port2_out", - "NOC_NPS_VNOC_X1Y15", - "port0_in", - "NOC_NPS_VNOC_X1Y15", - "port2_out", - "NOC_NPS7575_X5Y3", - "port3_in", - "NOC_NPS7575_X5Y3", - "port1_out", - "NOC_NIDB_X1Y2", - "port0_in", - "NOC_NIDB_X1Y2", - "port1_out", - "NOC_NIDB_X1Y0", - "port1_in", - "NOC_NIDB_X1Y0", - "port0_out", - "NOC_NPS7575_X5Y1", - "port1_in", - "NOC_NPS7575_X5Y1", - "port3_out", - "NOC_NPS_VNOC_X1Y13", - "port0_in", - "NOC_NPS_VNOC_X1Y13", - "port2_out", - "NOC_NPS_VNOC_X1Y11", - "port0_in", - "NOC_NPS_VNOC_X1Y11", - "port2_out", - "NOC_NPS_VNOC_X1Y9", - "port0_in", - "NOC_NPS_VNOC_X1Y9", - "port2_out", - "NOC_NPS_VNOC_X1Y7", - "port0_in", - "NOC_NPS_VNOC_X1Y7", - "port2_out", - "NOC_NPS_VNOC_X1Y5", - "port0_in", - "NOC_NPS_VNOC_X1Y5", - "port2_out", - "NOC_NPS_VNOC_X1Y3", - "port0_in", - "NOC_NPS_VNOC_X1Y3", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port0_in", - "NOC_NPS_VNOC_X1Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port2_in", - "NOC_NPS5555_X11Y1", - "port0_out", - "NOC_NPS5555_X10Y1", - "port2_in", - "NOC_NPS5555_X10Y1", - "port1_out", - "NOC_NPS5555_X10Y0", - "port3_in", - "NOC_NPS5555_X10Y0", - "port0_out", - "NOC_NPS5555_X8Y0", - "port2_in", - "NOC_NPS5555_X8Y0", - "port0_out", - "NOC_NPS5555_X6Y0", - "port2_in", - "NOC_NPS5555_X6Y0", - "port0_out", - "NOC_NPS5555_X4Y0", - "port2_in", - "NOC_NPS5555_X4Y0", - "port0_out", - "NOC_NPS5555_X2Y0", - "port2_in", - "NOC_NPS5555_X2Y0", - "port3_out", - "DDRMC_X0Y0", - "Port0_req" - ], - "RequiredBW": 850, - "AchievedBW": 850, - "RequiredLatency": 300, - "AchievedLatency": 118 - }, - { - "PhyInstanceStart": "DDRMC_X0Y0", - "PhyInstanceEnd": "NOC_NMU512_X1Y18", - "VC": 7, - "CommType": "WRITE_RESP", - "Connections": [ - "DDRMC_X0Y0", - "Port0_resp", - "NOC_NPS5555_X2Y0", - "port3_in", - "NOC_NPS5555_X2Y0", - "port2_out", - "NOC_NPS5555_X4Y0", - "port0_in", - "NOC_NPS5555_X4Y0", - "port2_out", - "NOC_NPS5555_X6Y0", - "port0_in", - "NOC_NPS5555_X6Y0", - "port2_out", - "NOC_NPS5555_X8Y0", - "port0_in", - "NOC_NPS5555_X8Y0", - "port2_out", - "NOC_NPS5555_X10Y0", - "port0_in", - "NOC_NPS5555_X10Y0", - "port3_out", - "NOC_NPS5555_X10Y1", - "port1_in", - "NOC_NPS5555_X10Y1", - "port2_out", - "NOC_NPS5555_X11Y1", - "port0_in", - "NOC_NPS5555_X11Y1", - "port2_out", - "NOC_NPS_VNOC_X1Y1", - "port2_in", - "NOC_NPS_VNOC_X1Y1", - "port0_out", - "NOC_NPS_VNOC_X1Y3", - "port2_in", - "NOC_NPS_VNOC_X1Y3", - "port0_out", - "NOC_NPS_VNOC_X1Y5", - "port2_in", - "NOC_NPS_VNOC_X1Y5", - "port0_out", - "NOC_NPS_VNOC_X1Y7", - "port2_in", - "NOC_NPS_VNOC_X1Y7", - "port0_out", - "NOC_NPS_VNOC_X1Y9", - "port2_in", - "NOC_NPS_VNOC_X1Y9", - "port0_out", - "NOC_NPS_VNOC_X1Y11", - "port2_in", - "NOC_NPS_VNOC_X1Y11", - "port0_out", - "NOC_NPS_VNOC_X1Y13", - "port2_in", - "NOC_NPS_VNOC_X1Y13", - "port0_out", - "NOC_NPS7575_X5Y1", - "port3_in", - "NOC_NPS7575_X5Y1", - "port1_out", - "NOC_NIDB_X1Y0", - "port0_in", - "NOC_NIDB_X1Y0", - "port1_out", - "NOC_NIDB_X1Y2", - "port1_in", - "NOC_NIDB_X1Y2", - "port0_out", - "NOC_NPS7575_X5Y3", - "port1_in", - "NOC_NPS7575_X5Y3", - "port3_out", - "NOC_NPS_VNOC_X1Y15", - "port2_in", - "NOC_NPS_VNOC_X1Y15", - "port0_out", - "NOC_NPS_VNOC_X1Y17", - "port2_in", - "NOC_NPS_VNOC_X1Y17", - "port0_out", - "NOC_NPS_VNOC_X1Y19", - "port2_in", - "NOC_NPS_VNOC_X1Y19", - "port0_out", - "NOC_NPS_VNOC_X1Y21", - "port2_in", - "NOC_NPS_VNOC_X1Y21", - "port0_out", - "NOC_NPS_VNOC_X1Y23", - "port2_in", - "NOC_NPS_VNOC_X1Y23", - "port0_out", - "NOC_NPS_VNOC_X1Y25", - "port2_in", - "NOC_NPS_VNOC_X1Y25", - "port0_out", - "NOC_NPS7575_X5Y5", - "port3_in", - "NOC_NPS7575_X5Y5", - "port1_out", - "NOC_NIDB_X1Y4", - "port0_in", - "NOC_NIDB_X1Y4", - "port1_out", - "NOC_NIDB_X1Y6", - "port1_in", - "NOC_NIDB_X1Y6", - "port0_out", - "NOC_NPS7575_X5Y7", - "port1_in", - "NOC_NPS7575_X5Y7", - "port3_out", - "NOC_NPS_VNOC_X1Y27", - "port2_in", - "NOC_NPS_VNOC_X1Y27", - "port0_out", - "NOC_NPS_VNOC_X1Y29", - "port2_in", - "NOC_NPS_VNOC_X1Y29", - "port0_out", - "NOC_NPS_VNOC_X1Y31", - "port2_in", - "NOC_NPS_VNOC_X1Y31", - "port0_out", - "NOC_NPS_VNOC_X1Y33", - "port2_in", - "NOC_NPS_VNOC_X1Y33", - "port0_out", - "NOC_NPS_VNOC_X1Y35", - "port2_in", - "NOC_NPS_VNOC_X1Y35", - "port0_out", - "NOC_NPS_VNOC_X1Y37", - "port2_in", - "NOC_NPS_VNOC_X1Y37", - "port3_out", - "NOC_NMU512_X1Y18", - "resp_in" - ], - "RequiredBW": 50, - "AchievedBW": 50, - "RequiredLatency": 300, - "AchievedLatency": 118 - } - ] - } - ], - "Components": [ - { - "Name": "NOC_NMU512_X0Y18", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y18", - "TrafficLInst": "axi_noc_cips/inst/S04_AXI_nmu", - "DestId": 64 - }, - { - "Name": "NOC_NMU512_X2Y18", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y18", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y18", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y18", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y18", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y18", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y17", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y17", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y17", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y17", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y17", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y17", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y17", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y17", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y16", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y16", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y16", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y16", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y16", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y16", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y16", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y16", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y15", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y15", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y15", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y15", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y15", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y15", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y15", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y15", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y14", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y14", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y14", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y14", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y14", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y14", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y14", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y14", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y13", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y13", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y13", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y13", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y13", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y13", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y13", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y13", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y12", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y12", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y12", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y12", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y12", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y12", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y12", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y12", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y11", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y11", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y11", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y11", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y11", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y11", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y11", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y11", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y10", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y10", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y10", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y10", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y10", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y10", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y10", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y10", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y9", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y9", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y9", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y9", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y9", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y9", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y9", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y9", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y8", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y8", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y8", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y8", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y8", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y8", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y8", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y8", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y5", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y5", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y5", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y5", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y5", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y5", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y4", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y4", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y4", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y4", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y4", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y4", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU512_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/M00_AXI_nsu", - "DestId": 128 - }, - { - "Name": "NOC_NSU512_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NSU512_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X4Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X5Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X6Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X7Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X8Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X9Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X10Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X11Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X12Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X13Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X14Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X15Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X16Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X17Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X18Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X19Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X20Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X21Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X22Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X23Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X24Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X25Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X26Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X27Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X28Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X29Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X30Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X31Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X32Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X33Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X34Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X35Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X36Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X37Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X38Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X39Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X40Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X41Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X42Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X43Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X44Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X45Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X46Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X47Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X48Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X49Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X50Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X51Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X52Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X53Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X54Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X55Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X56Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X57Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X58Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X59Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X60Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X61Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X62Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU_HBM2E_X63Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X0Y1", - "DestId": 960 - }, - { - "Name": "NOC_NPS4_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X1Y1", - "DestId": 1536 - }, - { - "Name": "NOC_NPS4_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X2Y1", - "DestId": 1792 - }, - { - "Name": "NOC_NPS4_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X3Y1", - "DestId": 2368 - }, - { - "Name": "NOC_NPS4_X4Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X4Y1", - "DestId": 2880 - }, - { - "Name": "NOC_NPS4_X5Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X5Y1", - "DestId": 3392 - }, - { - "Name": "NOC_NPS4_X6Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X6Y1", - "DestId": 3904 - }, - { - "Name": "NOC_NPS4_X7Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS4_X7Y1", - "DestId": 1408 - }, - { - "Name": "NOC_NPS6_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X5Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X5Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X5Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X5Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X4Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X4Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X4Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X4Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X7Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X7Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X7Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X7Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X5Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X5Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X5Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X5Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X6Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X6Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X6Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X6Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X7Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X7Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X7Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS6_X7Y3", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y37", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y37", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y37", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y37", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y36", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y36", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y36", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y36", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y35", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y35", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y35", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y35", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y34", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y34", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y34", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y34", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y33", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y33", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y33", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y33", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y32", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y32", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y32", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y32", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y31", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y31", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y31", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y31", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y30", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y30", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y30", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y30", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y29", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y29", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y29", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y29", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y28", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y28", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y28", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y28", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y27", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y27", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y27", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y27", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y26", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y26", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y26", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y26", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X4Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X4Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y15", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y15", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y15", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y7", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y15", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X4Y6", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X4Y7", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X4Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X4Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y11", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X2Y4", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X2Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y11", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X4Y4", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X4Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y11", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X6Y4", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X6Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y5", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y11", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y25", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y25", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y25", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y25", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y24", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y24", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y24", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y24", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y23", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y23", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y23", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y23", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y22", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y22", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y22", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y22", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y21", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y21", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y21", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y21", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y20", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y20", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y20", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y20", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y19", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y19", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y19", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y19", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y18", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y18", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y18", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y18", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y17", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y17", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y17", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y17", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y16", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y16", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y16", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y16", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y15", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y15", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y15", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y15", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y14", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X4Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X4Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X5Y2", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X5Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y3", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X7Y2", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X7Y3", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X5Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X6Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NCRB_SSIT_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS7575_X7Y1", - "DestId": 0 - }, - { - "Name": "NOC_NIDB_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPP_RPTR_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y13", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y12", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y11", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y11", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y11", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y11", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y10", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y9", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y8", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y7", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y6", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y5", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y4", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y3", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X1Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS_VNOC_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X0Y1", - "DestId": 192 - }, - { - "Name": "NOC_NPS5555_X1Y0", - "DestId": 192 - }, - { - "Name": "NOC_NPS5555_X1Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X2Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X2Y1", - "DestId": 192 - }, - { - "Name": "NOC_NPS5555_X3Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X3Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X4Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X4Y1", - "DestId": 192 - }, - { - "Name": "NOC_NPS5555_X5Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X5Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X6Y2", - "DestId": 192 - }, - { - "Name": "NOC_NPS5555_X7Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X7Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X7Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X8Y2", - "DestId": 192 - }, - { - "Name": "NOC_NPS5555_X9Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X9Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X9Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X10Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X10Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X10Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X11Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X11Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X11Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X12Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X12Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X12Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X13Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X13Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X13Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X14Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X14Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X14Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X15Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X15Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X15Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X16Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X16Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X16Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X17Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X17Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X17Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X18Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X18Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X18Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X19Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X19Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X19Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X20Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X20Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X20Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X21Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X21Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X21Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X22Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X22Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X22Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X23Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X23Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X23Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X24Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X24Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X24Y2", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X25Y0", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X25Y1", - "DestId": 0 - }, - { - "Name": "NOC_NPS5555_X25Y2", - "DestId": 0 - }, - { - "Name": "NOC_NSU128_X0Y0", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/S00_AXI_nmu", - "DestId": 192 - }, - { - "Name": "NOC_NMU128_X0Y1", - "TrafficLInst": "axi_noc_cips/inst/S01_AXI_nmu", - "DestId": 256 - }, - { - "Name": "NOC_NSU128_X0Y1", - "DestId": 1 - }, - { - "Name": "NOC_NMU128_X0Y2", - "TrafficLInst": "axi_noc_cips/inst/S02_AXI_nmu", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y3", - "TrafficLInst": "axi_noc_cips/inst/S03_AXI_rpu", - "DestId": 320 - }, - { - "Name": "NOC_NMU128_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NSU128_X0Y2", - "DestId": 0 - }, - { - "Name": "NOC_NSU128_X0Y3", - "DestId": 0 - }, - { - "Name": "NOC_NSU128_X0Y4", - "DestId": 0 - }, - { - "Name": "NOC_NSU128_X0Y5", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y6", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y7", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y8", - "DestId": 0 - }, - { - "Name": "NOC_NMU128_X0Y9", - "DestId": 0 - }, - { - "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "DestId": 384, - "PortIndex": 0 - }, - { - "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "DestId": 192, - "PortIndex": 1 - }, - { - "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "DestId": 0, - "PortIndex": 2 - }, - { - "Name": "DDRMC_X0Y0", - "TrafficLInst": "axi_noc_mc_ddr4_0/inst/MC0_ddrc", - "DestId": 0, - "PortIndex": 3 - }, - { - "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "DestId": 512, - "PortIndex": 0 - }, - { - "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "DestId": 193, - "PortIndex": 1 - }, - { - "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "DestId": 0, - "PortIndex": 2 - }, - { - "Name": "DDRMC_X1Y0", - "TrafficLInst": "axi_noc_mc_ddr4_1/inst/MC0_ddrc", - "DestId": 0, - "PortIndex": 3 - }, - { - "Name": "DDRMC_X2Y0", - "DestId": 0, - "PortIndex": 0 - }, - { - "Name": "DDRMC_X2Y0", - "DestId": 0, - "PortIndex": 1 - }, - { - "Name": "DDRMC_X2Y0", - "DestId": 0, - "PortIndex": 2 - }, - { - "Name": "DDRMC_X2Y0", - "DestId": 0, - "PortIndex": 3 - }, - { - "Name": "DDRMC_X3Y0", - "DestId": 0, - "PortIndex": 0 - }, - { - "Name": "DDRMC_X3Y0", - "DestId": 0, - "PortIndex": 1 - }, - { - "Name": "DDRMC_X3Y0", - "DestId": 0, - "PortIndex": 2 - }, - { - "Name": "DDRMC_X3Y0", - "DestId": 0, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 640, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 961, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 768, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X0Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl0", - "DestId": 962, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 896, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 960, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 1088, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X1Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl1", - "DestId": 1152, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1216, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1537, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1344, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X2Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl2", - "DestId": 1538, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1472, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1536, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1600, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X3Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl3", - "DestId": 1664, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X4Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "DestId": 1728, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X4Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "DestId": 1792, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X4Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "DestId": 1856, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X4Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl4", - "DestId": 1793, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X5Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "DestId": 1984, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X5Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "DestId": 2112, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X5Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "DestId": 2176, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X5Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl5", - "DestId": 2240, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X6Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "DestId": 2304, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X6Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "DestId": 2368, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X6Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "DestId": 2432, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X6Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl6", - "DestId": 2369, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X7Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "DestId": 2560, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X7Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "DestId": 2624, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X7Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "DestId": 2688, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X7Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st0/I_hbm_chnl7", - "DestId": 2752, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X8Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "DestId": 2816, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X8Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "DestId": 2880, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X8Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "DestId": 2944, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X8Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl0", - "DestId": 2881, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X9Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "DestId": 3072, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X9Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "DestId": 3136, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X9Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "DestId": 3200, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X9Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl1", - "DestId": 3264, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X10Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "DestId": 3328, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X10Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "DestId": 3392, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X10Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "DestId": 3456, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X10Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl2", - "DestId": 3393, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X11Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "DestId": 3584, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X11Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "DestId": 3648, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X11Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "DestId": 3712, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X11Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl3", - "DestId": 3776, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X12Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "DestId": 3840, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X12Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "DestId": 3904, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X12Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "DestId": 3968, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X12Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl4", - "DestId": 3905, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X13Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "DestId": 448, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X13Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "DestId": 576, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X13Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "DestId": 704, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X13Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl5", - "DestId": 832, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X14Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "DestId": 1280, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X14Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "DestId": 1408, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X14Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "DestId": 1920, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X14Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl6", - "DestId": 1409, - "PortIndex": 3 - }, - { - "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 2496, - "PortIndex": 0 - }, - { - "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 3008, - "PortIndex": 1 - }, - { - "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 3520, - "PortIndex": 2 - }, - { - "Name": "HBM_MC_X15Y0", - "TrafficLInst": "axi_noc_cips/inst/MC_hbmc/inst/hbm_st1/I_hbm_chnl7", - "DestId": 4032, - "PortIndex": 3 - } - ] -} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/report_utilization.py b/submodules/v80-vitis-flow/resources/report_utilization.py deleted file mode 100644 index cd40fb93..00000000 --- a/submodules/v80-vitis-flow/resources/report_utilization.py +++ /dev/null @@ -1,114 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -import xml.etree.ElementTree as ET -from xml.dom import minidom -import argparse - -def read_input_file(file_path): - with open(file_path, 'r') as file: - return file.read() - -def add_instance(parent, instance, module, total_luts, logic_luts, lutrams, srls, ffs, ramb36, ramb18, uram, dsp_blocks): - instance_element = ET.SubElement(parent, "Instance") - ET.SubElement(instance_element, "Name").text = instance.strip() - ET.SubElement(instance_element, "Module").text = module.strip() - ET.SubElement(instance_element, "TotalLUTs").text = total_luts.strip() - ET.SubElement(instance_element, "LogicLUTs").text = logic_luts.strip() - ET.SubElement(instance_element, "LUTRAMs").text = lutrams.strip() - ET.SubElement(instance_element, "SRLs").text = srls.strip() - ET.SubElement(instance_element, "FFs").text = ffs.strip() - ET.SubElement(instance_element, "RAMB36").text = ramb36.strip() - ET.SubElement(instance_element, "RAMB18").text = ramb18.strip() - ET.SubElement(instance_element, "URAM").text = uram.strip() - ET.SubElement(instance_element, "DSPBlocks").text = dsp_blocks.strip() - return instance_element - -def main(resource_file): - root = ET.Element("UtilizationReport") - - input_text = read_input_file(resource_file) - - table_start = input_text.find("+---------------------------+") - table_end = input_text.rfind("+---------------------------+") - table_text = input_text[table_start:table_end + len("+---------------------------+")] - - lines = table_text.splitlines() - - current_parents = {0: root} - - for line in lines[1:]: - parts = line.split('|') - print(parts) - - if len(parts) < 13: - continue - - leading_whitespace = parts[1][:len(parts[1]) - len(parts[1].lstrip())] - fields = [part.strip() for part in parts[1:]] - - if len(fields) < 12: - continue - - instance = fields[0] - module = fields[1] - total_luts = fields[2] - logic_luts = fields[3] - lutrams = fields[4] - srls = fields[5] - ffs = fields[6] - ramb36 = fields[7] - ramb18 = fields[8] - uram = fields[9] - dsp_blocks = fields[10] - - level = len(leading_whitespace) - print(f"Instance: {instance}, Level: {level}, Leading whitespace: '{leading_whitespace}'") - - if level not in current_parents: - valid_levels = sorted(current_parents.keys()) - for valid_level in reversed(valid_levels): - if valid_level < level: - level = valid_level + 1 - break - else: - level = 0 - - parent_level = max(level - 1, 0) - current_parents[level] = add_instance(current_parents[parent_level], instance, module, total_luts, logic_luts, lutrams, srls, ffs, ramb36, ramb18, uram, dsp_blocks) - current_parents[level + 1] = current_parents[level] - - tree = ET.ElementTree(root) - - xml_str = ET.tostring(root, encoding='utf-8') - - parsed_xml = minidom.parseString(xml_str) - pretty_xml_str = parsed_xml.toprettyxml(indent=" ") - - with open("build/utilization_report.xml", "w", encoding="utf-8") as f: - f.write(pretty_xml_str) - - print("XML file created successfully.") - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Generate XML utilization report.') - parser.add_argument('--resource_file', type=str, required=True, help='Path to the resource file') - args = parser.parse_args() - main(args.resource_file) \ No newline at end of file diff --git a/submodules/v80-vitis-flow/resources/sim_prj.tcl b/submodules/v80-vitis-flow/resources/sim_prj.tcl deleted file mode 100644 index 66a89364..00000000 --- a/submodules/v80-vitis-flow/resources/sim_prj.tcl +++ /dev/null @@ -1,69 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -set src_dir "[pwd]/sim" -set bd_name "top" -create_project sim_prj "[pwd]/sim/sim_prj/" -part xcv80-lsva4737-2MHP-e-S -force - -add_files -norecurse ../resources/sim_mem.v -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 - -set_property ip_repo_paths "${src_dir}/iprepo" [current_project] -update_ip_catalog -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 -create_bd_design ${bd_name} -current_bd_design ${bd_name} - -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_ctrl -set_property -dict [list CONFIG.ADDR_WIDTH 64] [get_bd_intf_ports s_axi_ctrl] -set_property -dict [list CONFIG.HAS_BURST 0 CONFIG.HAS_CACHE 0 CONFIG.HAS_LOCK 0 CONFIG.HAS_PROT 0 CONFIG.HAS_QOS 0 CONFIG.HAS_REGION 0] [get_bd_intf_ports s_axi_ctrl] - -create_bd_port -dir I -type clk clk -create_bd_port -dir I -type rst rst -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 mem -set_property -dict [list CONFIG.ADDR_WIDTH 64] [get_bd_intf_ports mem] -set_property -dict [list CONFIG.READ_WRITE_MODE READ_WRITE] [get_bd_intf_ports mem] -set_property -dict [list CONFIG.DATA_WIDTH 64] [get_bd_intf_ports mem] - -create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 bram_ctrl -set_property -dict [list CONFIG.SINGLE_PORT_BRAM {0} CONFIG.DATA_WIDTH {64} CONFIG.ECC_TYPE {0} CONFIG.READ_LATENCY {50}] [get_bd_cells bram_ctrl] - -create_bd_cell -type module -reference sim_mem sim_mem_0 - -connect_bd_intf_net [get_bd_intf_pins bram_ctrl/BRAM_PORTA] [get_bd_intf_pins sim_mem_0/MEM_PORT_A] -connect_bd_intf_net [get_bd_intf_pins bram_ctrl/BRAM_PORTB] [get_bd_intf_pins sim_mem_0/MEM_PORT_B] - -set axi_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect axi_sc ] -set_property CONFIG.NUM_SI {1} [get_bd_cells axi_sc] -set mem_sc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect mem_sc ] - -connect_bd_intf_net [get_bd_intf_ports s_axi_ctrl] [get_bd_intf_pins axi_sc/S00_AXI] -connect_bd_net [get_bd_ports clk] [get_bd_pins axi_sc/aclk] -connect_bd_net [get_bd_ports rst] [get_bd_pins axi_sc/aresetn] - -connect_bd_intf_net [get_bd_intf_pins mem_sc/M00_AXI] [get_bd_intf_pins bram_ctrl/S_AXI] -connect_bd_intf_net [get_bd_intf_pins mem_sc/S00_AXI] [get_bd_intf_ports mem] -connect_bd_net [get_bd_ports clk] [get_bd_pins bram_ctrl/s_axi_aclk] -connect_bd_net [get_bd_ports rst] [get_bd_pins bram_ctrl/s_axi_aresetn] - -connect_bd_net [get_bd_ports clk] [get_bd_pins mem_sc/aclk] -connect_bd_net [get_bd_ports rst] [get_bd_pins mem_sc/aresetn] \ No newline at end of file diff --git a/submodules/v80-vitis-flow/scripts/v80++ b/submodules/v80-vitis-flow/scripts/v80++ deleted file mode 100755 index 3453b825..00000000 --- a/submodules/v80-vitis-flow/scripts/v80++ +++ /dev/null @@ -1,207 +0,0 @@ -#!/bin/bash - -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -CONFIG_FILE="" -KERNEL_PATHS=() -DESIGN_NAME="" -SEGMENTED="" -PLATFORM="hw" -TCL_INJECT_ARGS=() - -usage() { - echo "Usage: $0 --cfg --design-name --platform --kernels ..." - echo "--segmented (optional): Use this flag to create a segmented design" - echo "--platform : Specify the platform type" - exit 1 -} - -# Parse arguments -while [[ "$#" -gt 0 ]]; do - case $1 in - --cfg) - CONFIG_FILE="$2" - shift 2 - ;; - --kernels) - shift - while [[ "$#" -gt 0 && "$1" != --* ]]; do - KERNEL_PATHS+=("$1") - shift - done - ;; - --design-name) - DESIGN_NAME="$2" - shift 2 - ;; - --segmented) - SEGMENTED="--segmented" - shift - ;; - --platform) - PLATFORM="$2" - shift 2 - ;; - --source-pre-synth) - shift - TCL_INJECT_ARGS+=("--source-pre-synth") - TCL_INJECT_ARGS+=("$(realpath "$1")") - shift - ;; - --source-post-build) - shift - TCL_INJECT_ARGS+=("--source-post-build") - TCL_INJECT_ARGS+=("$(realpath "$1")") - shift - ;; - *) - echo "Unknown parameter passed: $1" - usage - ;; - esac -done - -if [[ -z "$CONFIG_FILE" || ${#KERNEL_PATHS[@]} -eq 0 || -z "$DESIGN_NAME" ]]; then - usage -fi - -CONFIG_FILE=$(realpath "$CONFIG_FILE") - -for i in "${!KERNEL_PATHS[@]}"; do - KERNEL_PATHS[$i]=$(realpath "${KERNEL_PATHS[$i]}") -done - -echo "Config file: $CONFIG_FILE" -echo "Kernel paths: ${KERNEL_PATHS[@]}" -echo "Design name: $DESIGN_NAME" - - -HOME_DIR=$(realpath .) -echo "HOME_DIR" $HOME_DIR -IPREPO_DIR=$(realpath ./iprepo) - - -mkdir -p build -cd build - -if [ "$PLATFORM" = "hw" ]; then - cp -r $HOME_DIR/submodules/aved aved-fork -fi -BUILD_DIR=$(realpath $HOME_DIR/build) -AVED_DIR=$(realpath $HOME_DIR/build/aved-fork) -AVED_HW=$(realpath $AVED_DIR/hw/amd_v80_gen5x8_24.1) -AVED_IPREPO=$(realpath $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/iprepo) - -if [ "$PLATFORM" = "sim" ]; then - mkdir -p $BUILD_DIR/sim - mkdir -p $BUILD_DIR/sim/iprepo -fi - -if [ "$PLATFORM" = "hw" ]; then - echo "Copying kernels to AVED iprepo" - cp -r $HOME_DIR/iprepo/* $AVED_IPREPO - rm -rf $AVED_IPREPO/kernel_* - for kernel_path in "${KERNEL_PATHS[@]}"; do - target_dir=$(mktemp -d "$AVED_IPREPO/kernel_XXXXXX") - cp -r "$kernel_path" "$target_dir" - done -fi - -if [ "$PLATFORM" = "sim" ]; then - echo "Copying kernels to SIM iprepo" - rm -rf $BUILD_DIR/sim/iprepo/kernel_* - for kernel_path in "${KERNEL_PATHS[@]}"; do - target_dir=$(mktemp -d "$BUILD_DIR/sim/iprepo/kernel_XXXXXX") - cp -r "$kernel_path" "$target_dir" - done -fi - -echo "Linker step" -echo "Segmented design" $SEGMENTED -vitis_include_path=$(dirname $(dirname $(which vitis)))/include -pushd ${BUILD_DIR} - cmake .. - make -j9 - ./v80++-linker --cfg "$CONFIG_FILE" --platform "$PLATFORM" $SEGMENTED "${TCL_INJECT_ARGS[@]}" --kernels "${KERNEL_PATHS[@]}" - if [ "$PLATFORM" = "hw" ]; then - cp run_pre.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/run_pre.tcl - cp run_post.tcl $AVED_DIR/hw/amd_v80_gen5x8_24.1/src/run_post.tcl - fi - if [ "$PLATFORM" = "emu" ]; then - cpp_files="tb.cpp " - for kernel_path in "${KERNEL_PATHS[@]}"; do - cpp_files+="$kernel_path/../*.cpp " - done - g++ $cpp_files -o vpp_emu -I $vitis_include_path -lzmq -I /usr/include/jsoncpp/ -ljsoncpp - fi - if [ "$PLATFORM" = "sim" ]; then - vivado -source run_pre.tcl -mode tcl - cd sim/sim_prj/sim_prj.sim/sim_1/behav/xsim - ./compile.sh - ./elaborate.sh - mkdir -p $HOME_DIR/sim/build - cp -r xsim.dir $BUILD_DIR/../../. - cd $HOME_DIR/sim/build && cmake ../ && make -j9 - cp $HOME_DIR/sim/build/vpp_sim $BUILD_DIR - cp -r $HOME_DIR/sim/build/xsim.dir $BUILD_DIR - fi -popd - -# hw build -if [ "$PLATFORM" = "hw" ]; then - echo "Hardware build" - pushd ${AVED_HW} - ./build_all.sh - python3 $HOME_DIR/resources/gen_version.py --log_file ./build/vivado.log --name $DESIGN_NAME - python3 $HOME_DIR/resources/create_clk.py --system_map $BUILD_DIR/system_map.xml --timing build/report_timing.txt - python3 $HOME_DIR/resources/report_utilization.py --resource_file build/report_utilization.txt - popd -else - echo "Skipping hardware build as the platform is not set to hardware." -fi - -# vrtbin creation -echo "Creating vrtbin" -if [ "$PLATFORM" = "hw" ]; then - - pushd ${BUILD_DIR} - if [[ "$SEGMENTED" == "--segmented" ]]; then - cp $AVED_DIR/hw/amd_v80_gen5x8_24.1/build/prj.runs/impl_1/top_wrapper_pld.pdi design.pdi - else - cp $AVED_DIR/hw/amd_v80_gen5x8_24.1/build/amd_v80_gen5x8_24.1_nofpt.pdi design.pdi - fi - cp $AVED_DIR/hw/amd_v80_gen5x8_24.1/version.json version.json - cp $AVED_DIR/hw/amd_v80_gen5x8_24.1/build/utilization_report.xml report_utilization.xml - tar -cvf ${DESIGN_NAME}_hw.vrtbin system_map.xml design.pdi version.json report_utilization.xml - popd -fi - -if [ "$PLATFORM" = "emu" ]; then - pushd ${BUILD_DIR} - tar -cvf ${DESIGN_NAME}_emu.vrtbin system_map.xml vpp_emu - popd -fi - -if [ "$PLATFORM" = "sim" ]; then - pushd ${BUILD_DIR} - tar -cvf ${DESIGN_NAME}_sim.vrtbin system_map.xml vpp_sim - popd -fi \ No newline at end of file diff --git a/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp b/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp deleted file mode 100644 index 1135bfc8..00000000 --- a/submodules/v80-vitis-flow/src/arg_parser/arg_parser.cpp +++ /dev/null @@ -1,190 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "arg_parser.hpp" -#include -#include - -const std::string ArgParser::XML_PATH = "/syn/report/csynth.xml"; - -ArgParser::ArgParser(int argc, char** argv) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Parsing arguments"); - freqHz = 200000000; - segmented = false; - bool parsingKernels = false; - for (int i = 1; i < argc; i++) { - std::string arg(argv[i]); - if (arg == "--cfg" && i + 1 < argc) { - configFile = argv[++i]; - } else if (arg == "--segmented") { - segmented = true; - } else if (arg == "--kernels") { - parsingKernels = true; - } else if (arg == "--source-pre-synth") { - if (i + 1 < argc) { - tclInjections.scriptsPreSynth.emplace_back(argv[++i]); - } else { - throw std::runtime_error("Missing argument to --source-pre-synth"); - } - } else if (arg == "--source-post-build") { - if (i + 1 < argc) { - tclInjections.scriptsPostBuild.emplace_back(argv[++i]); - } else { - throw std::runtime_error("Missing argument to --source-pre-synth"); - } - } else if (arg == "--platform") { - std::string plat = argv[++i]; - if (plat == "hw") { - platform = Platform::HARDWARE; - } else if (plat == "emu") { - platform = Platform::EMULATOR; - } else if (plat == "sim") { - platform = Platform::SIMULATOR; - } else { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Unknown platform: {}", plat); - throw std::runtime_error("Unknown platform"); - } - } else if (parsingKernels) { - if (!arg.empty() && arg.back() == '/') { - arg.pop_back(); - } - kernelPaths.emplace_back(arg); - } else { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, "Unknown argument: {}", - arg); - throw std::runtime_error("Unknown argument"); - } - } - parseConfig(); - kernels = parseKernels(); -} - -void ArgParser::parseConfig() { - std::ifstream configFileStream(configFile); - if (!configFileStream.is_open()) { - throw std::runtime_error("Config file not provided"); - } - std::string line; - while (std::getline(configFileStream, line)) { - if (line.find("nk=") == 0) { - std::istringstream iss(line.substr(3)); - std::string kernelType, count, kernelName; - if (std::getline(iss, kernelType, ':') && std::getline(iss, count, ':')) { - for (size_t i = 0; i < std::stoi(count) - 1; i++) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Kernel type: {}, count: {}", kernelType, count); - std::getline(iss, kernelName, '.'); - kernelEntities[kernelName] = kernelType; - } - std::getline(iss, kernelName); - kernelEntities[kernelName] = kernelType; - } - } else if (line.find("stream_connect=") == 0) { - std::istringstream iss(line.substr(15)); - std::string srcKernel, srcIntf; - std::string dstKernel, dstIntf; - if (std::getline(iss, srcKernel, '.') && std::getline(iss, srcIntf, ':') && - std::getline(iss, dstKernel, '.') && std::getline(iss, dstIntf)) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Parsing connection: {}.{} -> {}.{}", srcKernel, srcIntf, - dstKernel, dstIntf); - ConnectionElement src{srcKernel, srcIntf}; - ConnectionElement dst{dstKernel, dstIntf}; - Connection conn{src, dst}; - connections.emplace_back(conn); - } - } else if (line.find("freqhz=") == 0) { - std::istringstream iss(line.substr(7)); - std::string freq; - if (std::getline(iss, freq)) { - freqHz = std::stoll(freq); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Setting clock at {} Hz", freqHz); - } - } else if (line.find("pre_synth=") == 0) { - std::istringstream iss(line.substr(10)); - std::string relfile; - if (std::getline(iss, relfile)) { - std::filesystem::path base = std::filesystem::absolute(std::filesystem::path(configFile)).parent_path(); - std::filesystem::path candidate = std::filesystem::path(relfile); - - if (candidate.is_relative()) { - candidate = base / candidate; - } - - std::string path = std::filesystem::weakly_canonical(candidate).string(); - - tclInjections.scriptsPreSynth.push_back(std::move(path)); - } - } else if (line.find("post_build=") == 0) { - std::istringstream iss(line.substr(11)); - std::string relfile; - if (std::getline(iss, relfile)) { - std::filesystem::path base = std::filesystem::absolute(std::filesystem::path(configFile)).parent_path(); - std::filesystem::path candidate = std::filesystem::path(relfile); - - if (candidate.is_relative()) { - candidate = base / candidate; - } - - std::string path = std::filesystem::weakly_canonical(candidate).string(); - - tclInjections.scriptsPostBuild.push_back(std::move(path)); - } - } - } -} - -std::vector ArgParser::parseKernels() { - std::vector kernels_; - for (const auto& path : kernelPaths) { - XmlParser parser(path + ArgParser::XML_PATH); - parser.parseXml(); - std::for_each(kernelEntities.begin(), kernelEntities.end(), [&](const auto& entity) { - Kernel krnl = parser.getKernel(); - if (krnl.getTopModelName() == entity.second) { - krnl.setName(entity.first); - kernels_.emplace_back(krnl); - krnl.print(); - } - }); - // kernels_.emplace_back(parser.getKernel()); - } - return kernels_; -} - -std::string ArgParser::getConfigFile() const { return configFile; } - -std::vector ArgParser::getKernels() { return kernels; } - -std::map ArgParser::getKernelEntities() const { return kernelEntities; } - -std::vector ArgParser::getConnections() const { return connections; } - -uint64_t ArgParser::getFreqHz() const { return freqHz; } - -bool ArgParser::isSegmented() const { return segmented; } - -Platform ArgParser::getPlatform() { return platform; } - -std::vector ArgParser::getKernelPaths() { return kernelPaths; } - -const TclInjections &ArgParser::getTclInjections() const { return tclInjections; } diff --git a/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp b/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp deleted file mode 100644 index 2a230b91..00000000 --- a/submodules/v80-vitis-flow/src/bd_builder/bd_builder.cpp +++ /dev/null @@ -1,1306 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "bd_builder.hpp" - -#include "arg_parser.hpp" -#include "system_map.hpp" -#include - -bool BdBuilder::hasAximmIntf = false; - -BdBuilder::BdBuilder(std::vector kernels, std::vector connections) - : systemMap(false, Platform::HARDWARE) { - this->kernels = kernels; - this->streamConnections = connections; -} - -BdBuilder::BdBuilder(std::vector kernels, std::vector connections, - double targetClockFreq, bool segmented, Platform platform, - TclInjections tclInjections) - : systemMap(segmented, platform) { - this->kernels = kernels; - this->streamConnections = connections; - this->targetClockFreq = targetClockFreq; - this->segmented = segmented; - this->platform = platform; - this->tclInjections = std::move(tclInjections); - - systemMap.setClockFreq(targetClockFreq); - StreamingConnection qdmaStreamConnection; - for (auto sc = streamConnections.begin(); sc != streamConnections.end(); sc++) { - if (sc->src.kernelName == "cips") { - qdmaStreamConnection.interfaceName = sc->dst.interfaceName; - std::regex re("qdma_(\\d)"); - std::smatch match; - if (std::regex_search(sc->src.interfaceName, match, re) && match.size() > 1) { - qdmaStreamConnection.qid = std::stoi(match.str(1)); - } else { - throw std::runtime_error("Invalid QDMA interface name: " + sc->src.interfaceName); - } - qdmaStreamConnection.kernelName = sc->dst.kernelName; - qdmaStreamConnection.direction = StreamDirection::HOST_TO_DEVICE; - // streamConnections.erase(sc--); - systemMap.addStreamConnection(qdmaStreamConnection); - - } else if (sc->dst.kernelName == "cips") { - qdmaStreamConnection.interfaceName = sc->src.interfaceName; - std::regex re("qdma_(\\d)"); - std::smatch match; - if (std::regex_search(sc->dst.interfaceName, match, re) && match.size() > 1) { - qdmaStreamConnection.qid = std::stoi(match.str(1)); - } else { - throw std::runtime_error("Invalid QDMA interface name: " + sc->src.interfaceName); - } - qdmaStreamConnection.kernelName = sc->src.kernelName; - qdmaStreamConnection.direction = StreamDirection::DEVICE_TO_HOST; - // streamConnections.erase(sc--); - systemMap.addStreamConnection(qdmaStreamConnection); - } - } -} - -void BdBuilder::buildBlockDesign() { - std::ifstream inputBlockDesignFile; - if (platform == Platform::SIMULATOR) { - inputBlockDesignFile.open(INPUT_FILE_SIM); - } - std::ofstream blockDesignFile; - std::ofstream postBuildScriptFile; - if (platform == Platform::EMULATOR) { - blockDesignFile.open("/dev/null"); - postBuildScriptFile.open("/dev/null"); - } else { - blockDesignFile.open(PRE_OUTPUT_FILE); - postBuildScriptFile.open(POST_OUTPUT_FILE); - } - - if (platform == Platform::HARDWARE) { - std::string line; - blockDesignFile << addRunPreHeader(); - blockDesignFile << setupQdmaStreaming(); - blockDesignFile << addQdmaLogic(); - blockDesignFile << setupClkWiz(); - blockDesignFile << setupSysRst(); - blockDesignFile << configNumberOfAXILiteSlaves(); // done - - blockDesignFile << configureUserClock(); - - blockDesignFile << connectClkWiz(); - blockDesignFile << connectQdmaLogic(); - // blockDesignFile << connectQdmaToRouter(); - - // do this for each kernel to be added - int axilite_idx = 0, axifull_idx = 0; - for (int i = 0; i < kernels.size(); i++) { - auto kernel = kernels.at(i); - blockDesignFile << createIp(i); - } - for (int i = 0; i < kernels.size(); i++) { - auto kernel = kernels.at(i); - for (auto& el : kernel.getInterfaces()) { - if (el.getInterfaceType() == "axi4lite") { - blockDesignFile << connectInterface(kernel.getName(), el, axilite_idx++); - } else if (el.getInterfaceType() == "clock" || el.getInterfaceType() == "reset") { - blockDesignFile << connectInterface(kernel.getName(), el, axilite_idx - 1); - } else if (el.getInterfaceType() == "axi4stream") { - blockDesignFile << connectAxis(kernel.getName()); - } - } - } - - blockDesignFile << configNumberOfAXIFullSlaves(); - - // Do QoS for AXI NoC - uint16_t bw = calculateBw(); - blockDesignFile << setHBMConfig(); - blockDesignFile << genQoS(0, bw); - blockDesignFile << genQoS(1, bw); - blockDesignFile << genQoS(2, bw); - blockDesignFile << genQoS(3, bw); - if (segmented) { - blockDesignFile << genQoS(4, bw); - } else { - int axiMmIntfIdx = 0; - for (auto& kernel : kernels) { - for (auto& intf : kernel.getInterfaces()) { - if (intf.getInterfaceType() == "axi4full") { - blockDesignFile << genQoS(axiMmIntfIdx + 4, bw); - axiMmIntfIdx++; - } - } - } - } - // utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Segmented config: {}", - // segmented); - if (segmented) { - int countAxi4FullInterfaces = 0; - for (auto& kernel : kernels) { - for (auto& intf : kernel.getInterfaces()) { - if (intf.getInterfaceType() == "axi4full") { - countAxi4FullInterfaces++; - } - } - } - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Adding xbar for axi4full interfaces: {}", countAxi4FullInterfaces); - blockDesignFile << addXbar(countAxi4FullInterfaces); - blockDesignFile << connectXbarToNoC(); - } - for (int i = 0; i < kernels.size(); i++) { - Interface axi_intf; // TODO: make this work for any number of interfaces.... - for (auto& el : kernels[i].getInterfaces()) { - if (el.getInterfaceType() == "axi4full") { - blockDesignFile << connectInterface(kernels.at(i).getName(), el, axifull_idx++); - } - } - for (auto& el : kernels[i].getInterfaces()) { - if (el.getInterfaceType() == "axi4lite") { - uint64_t offset = std::pow(2, el.getAddrWidth()); - MapEntry entry(kernels.at(i).getName(), BASE_ADDRESS + i * offset, offset); - entry.setRegisters(kernels.at(i).getRegisters()); - systemMap.addEntry(entry); - blockDesignFile << assignSlaveAddress(kernels.at(i).getName(), i, el, - BASE_ADDRESS + i * offset); - } - } - blockDesignFile << "\n"; - } - blockDesignFile << assignClkWizAddr() << std::endl; - // blockDesignFile << assignQdmaLogicGpioAddr() << std::endl; - blockDesignFile << "assign_bd_address" << std::endl; - - if (segmented) { - blockDesignFile << "set_property segmented_configuration true [current_project]\n"; - try { - blockDesignFile << setSegmented() << std::endl; - } catch (...){ - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Segmented not set"); - } - } - - - - for (const auto &script : tclInjections.scriptsPreSynth) { - blockDesignFile << generateSourceInstruction(script); - } - - blockDesignFile << printFooter(); - blockDesignFile.close(); - - // Inline and dirty. - postBuildScriptFile << "proc run_post {} {\n" - << "\topen_run impl_1\n" - << "\treport_utilization -hierarchical -hierarchical_depth 3 -hierarchical_percentages -file build/report_utilization.txt\n" - << "\treport_timing_summary -delay_type min_max -check_timing_verbose -max_paths 1 -input_pins -routable_nets -name timing_1 -file build/report_timing.txt\n\n"; - - - for (const auto &script : tclInjections.scriptsPostBuild) { - postBuildScriptFile << generateSourceInstruction(script); - } - - postBuildScriptFile << "}\n" - << "run_post\n"; - - - systemMap.printToFile(); - } else if (platform == Platform::SIMULATOR) { - std::string line; - while (std::getline(inputBlockDesignFile, line)) { - blockDesignFile << line << std::endl; - } - for (int i = 0; i < kernels.size(); i++) { - auto kernel = kernels.at(i); - blockDesignFile << createIpSim(i); - } - blockDesignFile << configNumberOfAXIFullSlavesSim(); - blockDesignFile << configNumberOfAXILiteSlavesSim(); - int axifull_idx = 0; - int axilite_idx = 0; - for (int i = 0; i < kernels.size(); i++) { - Interface axi_intf; - - for (auto& el : kernels[i].getInterfaces()) { - if (el.getInterfaceType() == "axi4full") { - blockDesignFile - << connectInterfaceSim(kernels.at(i).getName(), el, axifull_idx++); - } else if (el.getInterfaceType() == "axi4lite") { - blockDesignFile - << connectInterfaceSim(kernels.at(i).getName(), el, axilite_idx++); - } else if (el.getInterfaceType() == "axi4stream") { - blockDesignFile << connectAxisSim(kernels.at(i).getName()); - } else { - blockDesignFile << connectInterfaceSim(kernels.at(i).getName(), el, 0); - } - } - for (auto& el : kernels[i].getInterfaces()) { - if (el.getInterfaceType() == "axi4lite") { - uint64_t offset = std::pow(2, el.getAddrWidth()); - MapEntry entry(kernels.at(i).getName(), BASE_ADDRESS + i * offset, offset); - entry.setRegisters(kernels.at(i).getRegisters()); - systemMap.addEntry(entry); - blockDesignFile << assignSlaveAddressSim(kernels.at(i).getName(), i, el, - BASE_ADDRESS + i * offset); - } - } - blockDesignFile << "\n"; - } - // blockDesignFile << "connect_bd_intf_net [get_bd_intf_ports mem] [get_bd_intf_pins - // mem_sc/M00_AXI]\n"; - blockDesignFile << "assign_bd_address -offset 0x4000000000 -range 128M [get_bd_addr_segs " - "/bram_ctrl/S_AXI/Mem0] -force\n"; - blockDesignFile << "save_bd_design\n"; - blockDesignFile << "validate_bd_design\n"; - blockDesignFile - << "add_files -norecurse [make_wrapper -files [get_files \"${bd_name}.bd\"] -top]\n"; - blockDesignFile << "update_compile_order -fileset sources_1\n"; - blockDesignFile << "update_compile_order -fileset sim_1\n"; - blockDesignFile << "set_property -name {xsim.elaborate.xelab.more_options} -value {-dll} " - "-objects [get_filesets sim_1]\n"; - blockDesignFile << "set_property generate_scripts_only 1 [current_fileset -simset]\n"; - blockDesignFile << "launch_simulation -scripts_only\n"; - blockDesignFile << "close_project\n"; - blockDesignFile << "exit\n"; - - blockDesignFile.close(); - systemMap.printToFile(); - } else if (platform == Platform::EMULATOR) { - for (int i = 0; i < kernels.size(); i++) { - for (auto& el : kernels[i].getInterfaces()) { - if (el.getInterfaceType() == "axi4lite") { - uint64_t offset = std::pow(2, el.getAddrWidth()); - MapEntry entry(kernels.at(i).getName(), BASE_ADDRESS + i * offset, offset); - entry.setRegisters(kernels.at(i).getRegisters()); - systemMap.addEntry(entry); - // blockDesignFile << assignSlaveAddressSim(kernels.at(i).getName(), i, el, - // BASE_ADDRESS + i * offset); - } - } - } - - systemMap.printToFile(); - } -} - -// TODO Change it to accept input from config file. Add axi4full support. Add axistream support -std::string BdBuilder::connectInterface(std::string krnl_name, Interface intf, int idx) { - if (intf.getInterfaceType() == "axi4lite") { - if ((idx + 5) < 10) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4lite interface: {} to axi xbar M0{} for kernel {}", - intf.getInterfaceName(), std::to_string(idx + 5), krnl_name); - return "connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M0" + std::to_string(idx + 5) + - "_AXI " + "[get_bd_intf_pins base_logic/pcie_slr0_mgmt_sc/M0" + - std::to_string(idx + 5) + "_AXI] [get_bd_intf_pins base_logic/" + krnl_name + - "/" + intf.getInterfaceName() + "]\n"; - } else { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4lite interface: {} to axi xbar M{} for kernel {}", - intf.getInterfaceName(), std::to_string(idx + 5), krnl_name); - return "connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M" + std::to_string(idx + 5) + - "_AXI " + "[get_bd_intf_pins base_logic/pcie_slr0_mgmt_sc/M" + - std::to_string(idx + 5) + "_AXI] [get_bd_intf_pins base_logic/" + krnl_name + - "/" + intf.getInterfaceName() + "]\n"; - } - } else if (intf.getInterfaceType() == "clock") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting clock interface: {} to clk_wiz for kernel {}", - intf.getInterfaceName(), krnl_name); - return "connect_bd_net -net clk_out1 [get_bd_pins base_logic/clk_wiz/clk_out1] " - "[get_bd_pins base_logic/" + - krnl_name + "/" + intf.getInterfaceName() + "]\n"; - } else if (intf.getInterfaceType() == "reset") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting reset interface: {} to sys_rst for kernel {}", - intf.getInterfaceName(), krnl_name); - return "connect_bd_net -net sys_rst_peripheral_aresetn [get_bd_pins " - "base_logic/sys_rst/peripheral_aresetn] [get_bd_pins base_logic/" + - krnl_name + "/" + intf.getInterfaceName() + "]\n"; - } else if (intf.getInterfaceType() == "axi4full") { - if (segmented) { - if ((idx) < 10) { - return "connect_bd_intf_net [get_bd_intf_pins base_logic/" + krnl_name + "/" + - intf.getInterfaceName() + "] [get_bd_intf_pins base_logic/noc_xbar/S0" + - std::to_string(idx) + "_AXI]\n"; - } else { - return "connect_bd_intf_net [get_bd_intf_pins base_logic/" + krnl_name + "/" + - intf.getInterfaceName() + "] [get_bd_intf_pins base_logic/noc_xbar/S" + - std::to_string(idx) + "_AXI]\n"; - } - } else { - if ((idx + 4) < 10) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4full interface: {} to NoC S0{} for kernel {}", - intf.getInterfaceName(), std::to_string(idx + 4), krnl_name); - return "connect_bd_intf_net [get_bd_intf_pins base_logic/" + krnl_name + "/" + - intf.getInterfaceName() + "] [get_bd_intf_pins axi_noc_cips/S0" + - std::to_string(idx + 4) + "_AXI]\n"; - } else { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4full interface: {} to NoC S{} for kernel {}", - intf.getInterfaceName(), std::to_string(idx + 4), krnl_name); - return "connect_bd_intf_net [get_bd_intf_pins base_logic/" + krnl_name + "/" + - intf.getInterfaceName() + "] [get_bd_intf_pins axi_noc_cips/S" + - std::to_string(idx + 4) + "_AXI]\n"; - } - } - } - return std::string(); -} - -std::string BdBuilder::configNumberOfAXILiteSlaves() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Configuring number of axi lite interfaces to: {}", - getNumberOfAxiLiteInterfaces() + 5); - uint8_t no = getNumberOfAxiLiteInterfaces(); - return "set_property CONFIG.NUM_MI {" + std::to_string(no + 5) + - "} [get_bd_cells base_logic/pcie_slr0_mgmt_sc] \n\ -set_property CONFIG.NUM_CLKS {2} [get_bd_cells base_logic/pcie_slr0_mgmt_sc]\n"; // one for clk_wiz -} - -std::string BdBuilder::configNumberOfAXIFullSlaves() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Configuring number of axi full interfaces to: {}", - getNumberOfAxiMmInterfaces() + 4); - uint8_t no = getNumberOfAxiMmInterfaces(); - if (segmented) { // only one noc intf which connects to a xbar - return "set_property CONFIG.NUM_SI {" + std::to_string(5) + - "} [get_bd_cells axi_noc_cips]\n\ -set_property CONFIG.NUM_CLKS {6} [get_bd_cells axi_noc_cips]\n\ -connect_bd_net [get_bd_pins axi_noc_cips/aclk5] [get_bd_pins base_logic/clk_wiz/clk_out1]\n"; - } else { - return "set_property CONFIG.NUM_SI {" + std::to_string(no + 4) + - "} [get_bd_cells axi_noc_cips]\n\ -set_property CONFIG.NUM_CLKS {6} [get_bd_cells axi_noc_cips]\n\ -connect_bd_net [get_bd_pins axi_noc_cips/aclk5] [get_bd_pins base_logic/clk_wiz/clk_out1]\n"; - } -} - -std::string BdBuilder::createIp(int idx) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Creating IP instance: {}", - kernels.at(idx).getTopModelName()); - return "# set custom kernel: " + KERNEL_NAME + kernels.at(idx).getTopModelName() + "\n" + - "set " + kernels.at(idx).getName() + " [ create_bd_cell -type ip -vlnv" + " " + - KERNEL_NAME + kernels.at(idx).getTopModelName() + " base_logic/" + - kernels.at(idx).getName() + " ]\n"; -} - -std::string BdBuilder::assignSlaveAddress(std::string krnl_name, int idx, Interface intf, - uint64_t base_addr) { - std::stringstream ss; - uint64_t offset; - offset = std::pow(2, intf.getAddrWidth()); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Assigning address {x} to axi4lite interface: {} for kernel: {}", base_addr, - intf.getInterfaceName(), krnl_name); - ss << std::hex << std::showbase << "assign_bd_address -offset " << base_addr << " -range " - << std::hex << std::showbase << offset << NOC0_ADDR_STR << krnl_name << "/" - << intf.getInterfaceName() << "/Reg] -force" << std::endl; - - ss << std::hex << std::showbase << "assign_bd_address -offset " << base_addr << " -range " - << std::hex << std::showbase << offset << NOC1_ADDR_STR << krnl_name << "/" - << intf.getInterfaceName() << "/Reg] -force" << std::endl; - - return ss.str(); -} - -std::string BdBuilder::genQoS(int slave_offset, int bw) { - std::stringstream ss; - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Generating QoS with bandwidth: {}", bw); - - if (slave_offset == 0) { - ss << "set_property -dict [list CONFIG.CONNECTIONS {" - << "HBM10_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "M02_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {false}} " - << "HBM15_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM10_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM5_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM15_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM5_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM1_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM1_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM6_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM12_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM0_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM6_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM14_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM12_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM0_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM8_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM8_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM14_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM3_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM3_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM4_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM4_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM9_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM2_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM11_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {false}} " - << "HBM9_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM11_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM7_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM13_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM7_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM13_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM2_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {false}}}] [get_bd_intf_pins /axi_noc_cips/"; - } else if (slave_offset == 1) { - ss << "set_property -dict [list CONFIG.CONNECTIONS {" - << "HBM10_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM10_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM5_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM15_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM0_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM15_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM1_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM5_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM1_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM6_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM14_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM0_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM8_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "M01_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {false}} " - << "HBM12_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM6_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM12_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM8_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM14_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM3_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM3_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM4_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM9_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM4_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM9_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM11_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM11_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM7_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM13_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM7_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "HBM2_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "M03_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {false}} " - << "HBM2_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}} " - << "M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {false}} " - << "HBM13_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4} initial_boot {false}}}] [get_bd_intf_pins " - "/axi_noc_cips/"; - } else if (slave_offset == 2) { - ss << "set_property -dict [list CONFIG.CONNECTIONS {M02_INI {read_bw {800} write_bw {800} " - "read_avg_burst {64} write_avg_burst {64} initial_boot {true}}" - << "M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64} " - "initial_boot {true}}}] [get_bd_intf_pins /axi_noc_cips/"; - - } else if (slave_offset == 3) { - ss << "set_property -dict [list CONFIG.CONNECTIONS {M00_INI {read_bw {800} write_bw {800} " - "read_avg_burst {64} write_avg_burst {64} initial_boot {true}}}] [get_bd_intf_pins " - "/axi_noc_cips/"; - } else if (slave_offset % 2 == 0) { - ss << "set_property -dict [list CONFIG.CONNECTIONS {" - << "HBM10_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "M02_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} " - << "HBM15_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM10_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM5_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM15_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM5_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM1_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM1_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM6_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM12_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM0_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM6_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM14_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM12_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM0_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM8_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM8_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM14_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM3_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM3_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM4_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM4_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM9_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM2_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM11_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "M00_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} " - << "HBM9_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM11_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM7_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM13_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM7_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM13_PORT0 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM2_PORT2 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}}}] " - "[get_bd_intf_pins /axi_noc_cips/"; - } else { - ss << "set_property -dict [list CONFIG.CONNECTIONS {" - << "HBM10_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "M03_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} " - << "HBM10_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM5_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM15_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM0_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM15_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM1_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM5_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM1_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM6_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM14_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM0_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM8_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM12_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM6_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM12_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM8_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM14_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM3_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM3_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM4_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM9_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM4_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM9_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "M01_INI {read_bw {800} write_bw {800} read_avg_burst {64} write_avg_burst {64}} " - << "HBM11_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM11_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM7_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM13_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM7_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM2_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "HBM2_PORT1 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}} " - << "M00_AXI {read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}} " - << "HBM13_PORT3 {read_bw {" << bw << "} write_bw {" << bw - << "} read_avg_burst {4} write_avg_burst {4}}}] [get_bd_intf_pins /axi_noc_cips/"; - } - - if (slave_offset < 10) { - ss << "S0" << slave_offset << "_AXI]" << std::endl; - } else { - ss << "S" << slave_offset << "_AXI]" << std::endl; - } - - return ss.str(); -} - -uint16_t BdBuilder::calculateBw() { - int numberOfAxiMMChannels = 2; // 2 aximm accesses to HBM/DDR via NoC for QDMA - if (segmented) { - numberOfAxiMMChannels = 3; - } else { - for (auto& kernel : kernels) { - for (auto& intf : kernel.getInterfaces()) { - if (intf.getInterfaceType() == "axi4full") { - numberOfAxiMMChannels++; - } - } - } - } - return MAX_ALLOCABLE_BW_HBM_PER_CHANNEL / numberOfAxiMMChannels - 1; // avoid rounding errors -} - -uint8_t BdBuilder::getNumberOfAxiMmInterfaces() { - uint8_t numberOfInterfaces = 0; - for (auto& kernel : kernels) { - for (auto& intf : kernel.getInterfaces()) { - if (intf.getInterfaceType() == "axi4full") { - numberOfInterfaces++; - } - } - } - return numberOfInterfaces; -} - -uint8_t BdBuilder::getNumberOfAxiLiteInterfaces() { - uint8_t numberOfInterfaces = 0; - for (auto& kernel : kernels) { - for (auto& intf : kernel.getInterfaces()) { - if (intf.getInterfaceType() == "axi4lite") { - numberOfInterfaces++; - } - } - } - return numberOfInterfaces; -} - -std::string BdBuilder::connectAxis(std::string krnl_name) { - // connect_bd_intf_net -intf_net accumulate_0_axis_in [get_bd_intf_pins - // base_logic/accumulate_0/axis_in] [get_bd_intf_pins base_logic/increment_0/axis_out] - - /* - return " connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M0" + std::to_string(idx + 4) - + "_AXI " + "[get_bd_intf_pins pcie_slr0_mgmt_sc/M0" + std::to_string(idx + 4) + "_AXI] - [get_bd_intf_pins " + krnl_name + "/" + intf.getInterfaceName() + "]\n"; - */ - uint32_t c2hIdx = 0; - for (auto el = streamConnections.begin(); el != streamConnections.end(); el++) { - if ((el->src.kernelName == krnl_name || el->dst.kernelName == krnl_name) && - el->src.kernelName != "cips" && el->dst.kernelName != "cips") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4stream {}.{} to {}.{}", el->src.kernelName, - el->src.interfaceName, el->dst.kernelName, el->dst.interfaceName); - std::string result = "connect_bd_intf_net -intf_net " + el->src.kernelName + "_" + - el->src.interfaceName + " [get_bd_intf_pins base_logic/" + - el->src.kernelName + "/" + el->src.interfaceName + - "] [get_bd_intf_pins base_logic/" + el->dst.kernelName + "/" + - el->dst.interfaceName + "]\n"; - streamConnections.erase(el); - return result; - } else if (el->src.kernelName == "cips") { - uint32_t qid; - std::string srcInterface = el->src.interfaceName; - std::regex re("qdma_(\\d)"); - std::smatch match; - if (std::regex_search(srcInterface, match, re) && match.size() > 1) { - qid = std::stoi(match.str(1)); - } else { - throw std::runtime_error("Invalid QDMA interface name: " + el->src.interfaceName); - } - - if (qid > 15) { - throw std::runtime_error("Max qid is 15. Actual qid: " + std::to_string(qid)); - } - - std::string result; - if (qid < 10) { - result = "connect_bd_intf_net [get_bd_intf_pins qdma/axis_switch_0/M0" + - std::to_string(qid - 1) + "_AXIS] [get_bd_intf_pins base_logic/" + - el->dst.kernelName + "/" + el->dst.interfaceName + "]\n"; - } else { - result = "connect_bd_intf_net [get_bd_intf_pins qdma/axis_switch_0/M" + - std::to_string(qid - 1) + "_AXIS] [get_bd_intf_pins base_logic/" + - el->dst.kernelName + "/" + el->dst.interfaceName + "]\n"; - } - streamConnections.erase(el); - return result; - } else if (el->dst.kernelName == "cips") { - throw std::runtime_error("QDMA Stream C2H connections not supported yet"); - // std::string result; - // if(c2hIdx > 15) { - // throw std::runtime_error("Max c2hIdx is 15. Actual c2hIdx: " + - // std::to_string(c2hIdx)); - // } - // if(c2hIdx < 10) { - // result = "connect_bd_intf_net [get_bd_intf_pins qdma/axis_switch_1/S0" + - // std::to_string(c2hIdx++) - // + "_AXIS] [get_bd_intf_pins base_logic/" + el->src.kernelName + "/" + - // el->src.interfaceName + "]\n"; - // } else { - // result = "connect_bd_intf_net [get_bd_intf_pins qdma/axis_switch_1/S" + - // std::to_string(c2hIdx++) - // + "_AXIS] [get_bd_intf_pins base_logic/" + el->src.kernelName + "/" + - // el->src.interfaceName + "]\n"; - // } - // return result; - } - } - return "\n"; // if no stream interfaces exist -} - -std::string BdBuilder::configureUserClock() { - double freqMHz = targetClockFreq / 1e6; - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Configuring user clock with frequency: {} MHz", freqMHz); - std::stringstream ss; - ss << "set_property -dict [list \\\n" - << " CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \\\n" - << " CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \\\n" - << " CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto} \\\n" - << " CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false} \\\n" - << " CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} " - "\\\n" - << " CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000} " - "\\\n" - << " CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {" << freqMHz - << ",100.000,100.000,100.000,100.000,100.000,100.000} \\\n" - << " CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \\\n" - << " CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \\\n" - << " CONFIG.USE_DYN_RECONFIG {true} \\\n" - << "] [get_bd_cells base_logic/clk_wiz]\n\n\n"; - return ss.str(); -} -// connect_bd_intf_net [get_bd_intf_pins base_logic/clk_wizard_0/s_axi_lite] [get_bd_intf_pins -// base_logic/pcie_slr0_mgmt_sc/M04_AXI] - -std::string BdBuilder::connectClkWiz() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting clock wizard axi4lite interface to axi4lite"); - return "connect_bd_intf_net -intf_net pcie_slr0_mgmt_sc_M04_AXI [get_bd_intf_pins base_logic/pcie_slr0_mgmt_sc/M04_AXI] [get_bd_intf_pins base_logic/clk_wiz/s_axi_lite]\n\ -connect_bd_net -net clk_pl_1 [get_bd_pins base_logic/clk_pl] [get_bd_pins base_logic/clk_wiz/s_axi_aclk] [get_bd_pins base_logic/clk_wiz/clk_in1]\n\ -connect_bd_net -net clk_out1 [get_bd_pins base_logic/clk_wiz/clk_out1] [get_bd_pins base_logic/pcie_slr0_mgmt_sc/aclk1] [get_bd_pins base_logic/sys_rst/slowest_sync_clk]\n\ -connect_bd_net -net clk_wiz_locked [get_bd_pins base_logic/clk_wiz/locked] [get_bd_pins base_logic/sys_rst/dcm_locked]\n\ -connect_bd_net -net resetn_pl_ic_1 [get_bd_pins resetn_pl_ic] [get_bd_pins base_logic/clk_wiz/s_axi_aresetn] [get_bd_pins base_logic/sys_rst/ext_reset_in]\n"; -} - -std::string BdBuilder::setupClkWiz() { - std::stringstream ss; - ss << "# Add clocking wizard\n" - << "set clk_wiz [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 " - "base_logic/clk_wiz]\n"; - return ss.str(); -} -std::string BdBuilder::setupSysRst() { - std::stringstream ss; - ss << "# Add system reset\n" - << "set sys_rst [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 " - "base_logic/sys_rst]\n"; - return ss.str(); -} - -std::string BdBuilder::printFooter() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Print TCL footer"); - std::stringstream ss; - ss << "}\n"; - return ss.str(); -} - -std::string BdBuilder::setHBMConfig() { - std::stringstream ss; - ss << "set_property CONFIG.HBM_CHNL0_CONFIG {HBM_REORDER_EN FALSE HBM_MAINTAIN_COHERENCY TRUE " - "HBM_Q_AGE_LIMIT 0x7F " - << "HBM_CLOSE_PAGE_REORDER FALSE HBM_LOOKAHEAD_PCH TRUE HBM_COMMAND_PARITY FALSE " - "HBM_DQ_WR_PARITY FALSE " - << "HBM_DQ_RD_PARITY FALSE HBM_RD_DBI TRUE HBM_WR_DBI TRUE HBM_REFRESH_MODE " - "SINGLE_BANK_REFRESH " - << "HBM_PC0_PRE_DEFINED_ADDRESS_MAP USER_DEFINED_ADDRESS_MAP " - "HBM_PC1_PRE_DEFINED_ADDRESS_MAP USER_DEFINED_ADDRESS_MAP " - << "HBM_PC0_USER_DEFINED_ADDRESS_MAP 1BG-15RA-1SID-2BA-5CA-1BG " - "HBM_PC1_USER_DEFINED_ADDRESS_MAP 1BG-15RA-1SID-2BA-5CA-1BG " - << "HBM_PC0_ADDRESS_MAP " - "BA3,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,SID,BA1,BA0,CA5," - "CA4,CA3,CA2,CA1,BA2,NC,NA,NA,NA,NA " - << "HBM_PC1_ADDRESS_MAP " - "BA3,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0,SID,BA1,BA0,CA5," - "CA4,CA3,CA2,CA1,BA2,NC,NA,NA,NA,NA " - << "HBM_PWR_DWN_IDLE_TIMEOUT_ENTRY FALSE HBM_SELF_REF_IDLE_TIMEOUT_ENTRY FALSE " - "HBM_IDLE_TIME_TO_ENTER_PWR_DWN_MODE 0x0001000 " - << "HBM_IDLE_TIME_TO_ENTER_SELF_REF_MODE 1X HBM_ECC_CORRECTION_EN FALSE " - "HBM_WRITE_BACK_CORRECTED_DATA TRUE " - << "HBM_ECC_SCRUBBING FALSE HBM_ECC_INITIALIZE_EN FALSE HBM_ECC_SCRUB_SIZE 1092 " - "HBM_WRITE_DATA_MASK TRUE " - << "HBM_REF_PERIOD_TEMP_COMP FALSE HBM_PARITY_LATENCY 3 HBM_PC0_PAGE_HIT 100.000 " - "HBM_PC1_PAGE_HIT 100.000 " - << "HBM_PC0_READ_RATE 25.000 HBM_PC1_READ_RATE 25.000 HBM_PC0_WRITE_RATE 25.000 " - "HBM_PC1_WRITE_RATE 25.000 " - << "HBM_PC0_PHY_ACTIVE ENABLED HBM_PC1_PHY_ACTIVE ENABLED HBM_PC0_SCRUB_START_ADDRESS " - "0x0000000 " - << "HBM_PC0_SCRUB_END_ADDRESS 0x3FFFBFF HBM_PC0_SCRUB_INTERVAL 24.000 " - "HBM_PC1_SCRUB_START_ADDRESS 0x0000000 " - << "HBM_PC1_SCRUB_END_ADDRESS 0x3FFFBFF HBM_PC1_SCRUB_INTERVAL 24.000} [get_bd_cells " - "axi_noc_cips]\n"; - return ss.str(); -} - -std::string BdBuilder::assignClkWizAddr() { - std::stringstream ss; - ss << "assign_bd_address -offset 0x20100010000 -range 0x10000 -target_address_space " - "[get_bd_addr_spaces cips/CPM_PCIE_NOC_0] [get_bd_addr_segs " - "base_logic/clk_wiz/s_axi_lite/Reg] -force\n" - << "assign_bd_address -offset 0x20100010000 -range 0x10000 -target_address_space " - "[get_bd_addr_spaces cips/CPM_PCIE_NOC_1] [get_bd_addr_segs " - "base_logic/clk_wiz/s_axi_lite/Reg] -force\n"; - return ss.str(); -} - -std::string BdBuilder::setSegmented() { - char resolvedPath[PATH_MAX]; - if (realpath(NOC_SOLUTION.c_str(), resolvedPath) == nullptr) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Failed to resolve path to {}", NOC_SOLUTION); - throw std::runtime_error("Failed to resolve path to " + std::string(NOC_SOLUTION)); - } - std::stringstream ss; - ss << "set_property NOC_SOLUTION_FILE " << std::string(resolvedPath) << " [get_runs impl_1]\n"; - return ss.str(); -} - -std::string BdBuilder::addXbar(uint8_t numSlaves) { - std::stringstream ss; - ss << "create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 base_logic/noc_xbar\n" - << "set_property CONFIG.NUM_SI {" << (int)numSlaves - << "} [get_bd_cells base_logic/noc_xbar]\n" - << "connect_bd_net [get_bd_pins base_logic/noc_xbar/aclk] [get_bd_pins " - "base_logic/clk_wiz/clk_out1]\n" - << "connect_bd_net [get_bd_pins base_logic/noc_xbar/aresetn] [get_bd_pins " - "base_logic/sys_rst/peripheral_aresetn]\n"; - - return ss.str(); -} - -std::string BdBuilder::connectXbarToNoC() { - return "connect_bd_intf_net [get_bd_intf_pins base_logic/noc_xbar/M00_AXI] [get_bd_intf_pins " - "axi_noc_cips/S04_AXI]\n"; -} - -std::string BdBuilder::setupQdmaStreaming() { - std::stringstream ss; - ss << "set_property -dict [list \\\n" - << " CONFIG.CPM_CONFIG { \\\n" - << " CPM_PCIE1_DMA_INTF {AXI_MM_and_AXI_Stream} \\\n" - << " } \\\n" - << "] [get_bd_cells cips]\n\n\n"; - return ss.str(); -} - -std::string BdBuilder::addH2CAxisRouter() { - std::stringstream ss; - ss << "set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 " - "qdma/axis_switch_0 ]\n" - << "set_property -dict [list \\\n" - << " CONFIG.M00_AXIS_BASETDEST {0x00000001} \\\n" - << " CONFIG.M00_AXIS_HIGHTDEST {0x00000001} \\\n" - << " CONFIG.M01_AXIS_BASETDEST {0x00000002} \\\n" - << " CONFIG.M01_AXIS_HIGHTDEST {0x00000002} \\\n" - << " CONFIG.M02_AXIS_BASETDEST {0x00000003} \\\n" - << " CONFIG.M02_AXIS_HIGHTDEST {0x00000003} \\\n" - << " CONFIG.M03_AXIS_BASETDEST {0x00000004} \\\n" - << " CONFIG.M03_AXIS_HIGHTDEST {0x00000004} \\\n" - << " CONFIG.M04_AXIS_BASETDEST {0x00000005} \\\n" - << " CONFIG.M04_AXIS_HIGHTDEST {0x00000005} \\\n" - << " CONFIG.M05_AXIS_BASETDEST {0x00000006} \\\n" - << " CONFIG.M05_AXIS_HIGHTDEST {0x00000006} \\\n" - << " CONFIG.M06_AXIS_BASETDEST {0x00000007} \\\n" - << " CONFIG.M06_AXIS_HIGHTDEST {0x00000007} \\\n" - << " CONFIG.M07_AXIS_BASETDEST {0x00000008} \\\n" - << " CONFIG.M07_AXIS_HIGHTDEST {0x00000008} \\\n" - << " CONFIG.M08_AXIS_BASETDEST {0x00000009} \\\n" - << " CONFIG.M08_AXIS_HIGHTDEST {0x00000009} \\\n" - << " CONFIG.M09_AXIS_BASETDEST {0x0000000a} \\\n" - << " CONFIG.M09_AXIS_HIGHTDEST {0x0000000a} \\\n" - << " CONFIG.M10_AXIS_BASETDEST {0x0000000b} \\\n" - << " CONFIG.M10_AXIS_HIGHTDEST {0x0000000b} \\\n" - << " CONFIG.M11_AXIS_BASETDEST {0x0000000c} \\\n" - << " CONFIG.M11_AXIS_HIGHTDEST {0x0000000c} \\\n" - << " CONFIG.M12_AXIS_BASETDEST {0x0000000d} \\\n" - << " CONFIG.M12_AXIS_HIGHTDEST {0x0000000d} \\\n" - << " CONFIG.M13_AXIS_BASETDEST {0x0000000e} \\\n" - << " CONFIG.M13_AXIS_HIGHTDEST {0x0000000e} \\\n" - << " CONFIG.M14_AXIS_BASETDEST {0x0000000f} \\\n" - << " CONFIG.M14_AXIS_HIGHTDEST {0x0000000f} \\\n" - << " CONFIG.M15_AXIS_BASETDEST {0x00000010} \\\n" - << " CONFIG.M15_AXIS_HIGHTDEST {0x00000010} \\\n" - << " CONFIG.NUM_MI {16} \\\n" - << " CONFIG.NUM_SI {1} \\\n" - << " CONFIG.TDATA_NUM_BYTES {64} \\\n" - << "] $axis_switch_0\n\n\n"; - return ss.str(); -} - -std::string BdBuilder::addC2HAxisRouter() { - std::stringstream ss; - ss << "set axis_switch_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 " - "qdma/axis_switch_1 ]\n"; - ss << "set_property -dict [list \\\n" - << " CONFIG.NUM_SI {16} \\\n" - << " CONFIG.NUM_MI {1} \\\n" - << " CONFIG.TDATA_NUM_BYTES {64} \\\n" - << "] $axis_switch_1\n\n\n"; - - return ss.str(); -} - -std::string BdBuilder::connectQdmaH2CToRouter() { - std::stringstream ss; - ss << "connect_bd_net [get_bd_pins qdma/h2c_fifo/s_axis_tvalid] [get_bd_pins " - "cips/dma1_m_axis_h2c_tvalid]\n" - << "connect_bd_net [get_bd_pins qdma/h2c_fifo/s_axis_tready] [get_bd_pins " - "cips/dma1_m_axis_h2c_tready]\n" - << "connect_bd_net [get_bd_pins qdma/h2c_fifo/s_axis_tdata] [get_bd_pins " - "cips/dma1_m_axis_h2c_tdata]\n" - << "connect_bd_net [get_bd_pins cips/dma1_m_axis_h2c_qid] [get_bd_pins " - "qdma/h2c_fifo/s_axis_tdest]\n" - << "connect_bd_intf_net [get_bd_intf_pins qdma/h2c_fifo/M_AXIS] [get_bd_intf_pins " - "qdma/axis_switch_0/S00_AXIS]\n" - << "connect_bd_net [get_bd_pins base_logic/sys_rst/peripheral_aresetn] [get_bd_pins " - "qdma/axis_switch_0/aresetn]\n" - << "connect_bd_net [get_bd_pins base_logic/sys_rst/peripheral_aresetn] [get_bd_pins " - "qdma/h2c_fifo/s_axis_aresetn]\n" - << "connect_bd_net [get_bd_pins base_logic/clk_wiz/clk_out1] [get_bd_pins " - "qdma/axis_switch_0/aclk]\n" - << "connect_bd_net [get_bd_pins base_logic/clk_wiz/clk_out1] [get_bd_pins " - "qdma/h2c_fifo/m_axis_aclk]\n" - << "connect_bd_net [get_bd_pins cips/pl2_ref_clk] [get_bd_pins qdma/h2c_fifo/s_axis_aclk]\n"; - return ss.str(); -} - -std::string BdBuilder::connectQdmaC2HToRouter() { - std::stringstream ss; - ss << "connect_bd_net [get_bd_pins qdma/axis_switch_1/m_axis_tvalid] [get_bd_pins " - "cips/dma1_s_axis_c2h_tvalid]\n" - << "connect_bd_net [get_bd_pins qdma/axis_switch_1/m_axis_tready] [get_bd_pins " - "cips/dma1_s_axis_c2h_tready]\n" - << "connect_bd_net [get_bd_pins qdma/axis_switch_1/m_axis_tdata] [get_bd_pins " - "cips/dma1_s_axis_c2h_tdata]\n" - << "connect_bd_net [get_bd_pins base_logic/sys_rst/peripheral_aresetn] [get_bd_pins " - "qdma/axis_switch_1/aresetn]\n" - << "connect_bd_net [get_bd_pins base_logic/clk_wiz/clk_out1] [get_bd_pins " - "qdma/axis_switch_1/aclk]\n"; - ss << "\n\n\n"; - return ss.str(); -} - -std::string BdBuilder::addQdmaLogic() { - std::stringstream ss; - ss << "create_bd_cell -type hier qdma\n"; - ss << addH2CAxisRouter(); - ss << addH2CFifo(); - // ss << addC2HAxisRouter(); - // ss << "set qdma_logic_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 - // qdma/qdma_logic_gpio]\n"; ss << "set_property CONFIG.C_ALL_OUTPUTS {1} [get_bd_cells - // qdma/qdma_logic_gpio]\n"; ss << "set qid_slice [create_bd_cell -type ip -vlnv - // xilinx.com:ip:xlslice:1.0 qdma/qid_slice]\n\n"; ss << "set_property CONFIG.DIN_FROM {11} - // [get_bd_cells qdma/qid_slice]\n"; ss << "set qlen_slice [create_bd_cell -type ip -vlnv - // xilinx.com:ip:xlslice:1.0 qdma/qlen_slice]\n\n"; ss << "set_property -dict [list \\\n" - // << " CONFIG.DIN_FROM {27} \\\n" - // << " CONFIG.DIN_TO {12} \\\n" - // << "] [get_bd_cells qdma/qlen_slice]\n\n"; - // ss << "\n\n\n"; - return ss.str(); -} - -std::string BdBuilder::connectQdmaLogic() { - std::stringstream ss; - ss << connectQdmaH2CToRouter(); - // ss << connectQdmaC2HToRouter(); - // ss << "connect_bd_net [get_bd_pins qdma/qdma_logic_gpio/gpio_io_o] [get_bd_pins - // qdma/qid_slice/Din]\n"; ss << "connect_bd_net [get_bd_pins qdma/qdma_logic_gpio/gpio_io_o] - // [get_bd_pins qdma/qlen_slice/Din]\n"; ss << "connect_bd_net [get_bd_pins qdma/qid_slice/Dout] - // [get_bd_pins cips/dma1_s_axis_c2h_ctrl_qid]\n"; ss << "connect_bd_net [get_bd_pins - // qdma/qlen_slice/Dout] [get_bd_pins cips/dma1_s_axis_c2h_ctrl_len]\n"; ss << "connect_bd_net - // [get_bd_pins base_logic/clk_wiz/clk_out1] [get_bd_pins qdma/qdma_logic_gpio/s_axi_aclk]\n"; - // ss << "connect_bd_net [get_bd_pins base_logic/sys_rst/peripheral_aresetn] [get_bd_pins - // qdma/qdma_logic_gpio/s_axi_aresetn]\n"; ss << "connect_bd_intf_net [get_bd_intf_pins - // base_logic/pcie_slr0_mgmt_sc/M05_AXI] [get_bd_intf_pins qdma/qdma_logic_gpio/S_AXI]\n"; - ss << "\n\n\n"; - return ss.str(); -} - -std::string BdBuilder::assignQdmaLogicGpioAddr() { - std::stringstream ss; - ss << "assign_bd_address -offset 0x20100020000 -range 0x00001000 -target_address_space " - "[get_bd_addr_spaces cips/CPM_PCIE_NOC_0] [get_bd_addr_segs " - "qdma/qdma_logic_gpio/S_AXI/Reg] -force\n" - << "assign_bd_address -offset 0x20100020000 -range 0x00001000 -target_address_space " - "[get_bd_addr_spaces cips/CPM_PCIE_NOC_1] [get_bd_addr_segs " - "qdma/qdma_logic_gpio/S_AXI/Reg] -force\n"; - ss << "\n\n\n"; - return ss.str(); -} - -std::string BdBuilder::addH2CFifo() { - std::stringstream ss; - ss << "set h2c_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 " - "qdma/h2c_fifo ]\n"; - ss << "set_property -dict [list \\\n" - << " CONFIG.FIFO_DEPTH {2048} \\\n" - << " CONFIG.IS_ACLK_ASYNC {1} \\\n" - << " CONFIG.TDATA_NUM_BYTES {64} \\\n" - << " CONFIG.TDEST_WIDTH {4} \\\n" - << "] [get_bd_cells qdma/h2c_fifo]\n"; - ss << "\n\n\n"; - - return ss.str(); -} - -std::string BdBuilder::configNumberOfAXILiteSlavesSim() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Configuring number of axi lite interfaces to: {}", - getNumberOfAxiLiteInterfaces()); - uint8_t no = getNumberOfAxiLiteInterfaces(); - return "set_property CONFIG.NUM_MI {" + std::to_string(no) + "} [get_bd_cells axi_sc] \n"; -} - -std::string BdBuilder::configNumberOfAXIFullSlavesSim() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Configuring number of axi full interfaces to: {}", - getNumberOfAxiMmInterfaces()); - uint8_t no = getNumberOfAxiMmInterfaces(); - - return "set_property CONFIG.NUM_SI {" + std::to_string(no + 1) + "} [get_bd_cells mem_sc] \n"; -} - -std::string BdBuilder::connectInterfaceSim(std::string krnl_name, Interface intf, int idx) { - if (intf.getInterfaceType() == "axi4lite") { - if ((idx) < 10) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4lite interface: {} to axi xbar M0{} for kernel {}", - intf.getInterfaceName(), std::to_string(idx), krnl_name); - return "connect_bd_intf_net [get_bd_intf_pins axi_sc/M0" + std::to_string(idx) + - "_AXI] [get_bd_intf_pins " + krnl_name + "/" + intf.getInterfaceName() + "]\n"; - } else { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4lite interface: {} to axi xbar M{} for kernel {}", - intf.getInterfaceName(), std::to_string(idx), krnl_name); - return "connect_bd_intf_net [get_bd_intf_pins axi_sc/M" + std::to_string(idx) + - "_AXI] [get_bd_intf_pins " + krnl_name + "/" + intf.getInterfaceName() + "]\n"; - } - } else if (intf.getInterfaceType() == "clock") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting clock interface: {} to clk_wiz for kernel {}", - intf.getInterfaceName(), krnl_name); - return "connect_bd_net [get_bd_pins clk] [get_bd_pins " + krnl_name + "/" + - intf.getInterfaceName() + "]\n"; - } else if (intf.getInterfaceType() == "reset") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting reset interface: {} to sys_rst for kernel {}", - intf.getInterfaceName(), krnl_name); - return "connect_bd_net [get_bd_pins rst] [get_bd_pins " + krnl_name + "/" + - intf.getInterfaceName() + "]\n"; - } else if (intf.getInterfaceType() == "axi4full") { - if ((idx + 1) < 10) { - return "connect_bd_intf_net [get_bd_intf_pins " + krnl_name + "/" + - intf.getInterfaceName() + "] [get_bd_intf_pins mem_sc/S0" + - std::to_string(idx + 1) + "_AXI]\n"; - } else { - return "connect_bd_intf_net [get_bd_intf_pins " + krnl_name + "/" + - intf.getInterfaceName() + "] [get_bd_intf_pins mem_sc/S" + - std::to_string(idx + 1) + "_AXI]\n"; - } - } - return std::string(); -} - -std::string BdBuilder::createIpSim(int idx) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Creating IP instance: {}", - kernels.at(idx).getTopModelName()); - return "# set custom kernel: " + KERNEL_NAME + kernels.at(idx).getTopModelName() + "\n" + - "set " + kernels.at(idx).getName() + " [ create_bd_cell -type ip -vlnv" + " " + - KERNEL_NAME + kernels.at(idx).getTopModelName() + " " + kernels.at(idx).getName() + - " ]\n"; -} - -std::string BdBuilder::assignSlaveAddressSim(std::string krnl_name, int idx, Interface intf, - uint64_t base_addr) { - std::stringstream ss; - uint64_t offset; - offset = std::pow(2, intf.getAddrWidth()); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Assigning address {x} to axi4lite interface: {} for kernel: {}", base_addr, - intf.getInterfaceName(), krnl_name); - ss << std::hex << std::showbase << "assign_bd_address -offset " << base_addr << " -range " - << std::hex << std::showbase << offset << " [get_bd_addr_segs " << krnl_name << "/" - << intf.getInterfaceName() << "/Reg] -force" << std::endl; - - return ss.str(); -} - -std::string BdBuilder::connectAxisSim(std::string krnl_name) { - uint32_t c2hIdx = 0; - for (auto el = streamConnections.begin(); el != streamConnections.end(); el++) { - if ((el->src.kernelName == krnl_name || el->dst.kernelName == krnl_name) && - el->src.kernelName != "cips" && el->dst.kernelName != "cips") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Connecting axi4stream {}.{} to {}.{}", el->src.kernelName, - el->src.interfaceName, el->dst.kernelName, el->dst.interfaceName); - std::string result = "connect_bd_intf_net -intf_net " + el->src.kernelName + "_" + - el->src.interfaceName + " [get_bd_intf_pins " + - el->src.kernelName + "/" + el->src.interfaceName + - "] [get_bd_intf_pins " + el->dst.kernelName + "/" + - el->dst.interfaceName + "]\n"; - streamConnections.erase(el); - return result; - } else if (el->src.kernelName == "cips") { - throw std::runtime_error("QDMA Stream H2C connections not supported yet in simulator"); - } else if (el->dst.kernelName == "cips") { - throw std::runtime_error("QDMA Stream C2H connections not supported yet in simulator"); - } - } - return "\n"; // if no stream interfaces exist -} - -std::string BdBuilder::addRunPreHeader() { - std::stringstream ss; - ss << "proc run_pre { parentCell } {\n" - << "\n" - << " variable script_folder\n" - << "\n" - << " if { $parentCell eq \"\" } {\n" - << " set parentCell [get_bd_cells /]\n" - << " }\n" - << "\n" - << " # Get object for parentCell\n" - << " set parentObj [get_bd_cells $parentCell]\n" - << " if { $parentObj == \"\" } {\n" - << " catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity \"ERROR\" " - "\"Unable to find parent cell <$parentCell>!\"}\n" - << " return\n" - << " }\n" - << "\n" - << " # Make sure parentObj is hier blk\n" - << " set parentType [get_property TYPE $parentObj]\n" - << " if { $parentType ne \"hier\" } {\n" - << " catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity \"ERROR\" " - "\"Parent <$parentObj> has TYPE = <$parentType>. Expected to be .\"}\n" - << " return\n" - << " }\n" - << "\n" - << " # Save current instance; Restore later\n" - << " set oldCurInst [current_bd_instance .]\n" - << "\n" - << " # Set parent object as current\n" - << " current_bd_instance $parentObj\n" - << "\n"; - - return ss.str(); -} - -std::string BdBuilder::generateSourceInstruction(const std::string& path) const { - std::stringstream ss; - - if (path.find("{") != std::string::npos - || path.find("}") != std::string::npos) { - throw std::runtime_error("Path to script to source cannot contian '{' or '}'"); - } - - ss << "\tsource {" << path << "}\n"; - - return ss.str(); -} diff --git a/submodules/v80-vitis-flow/src/bd_builder/register.cpp b/submodules/v80-vitis-flow/src/bd_builder/register.cpp deleted file mode 100644 index f7ca0642..00000000 --- a/submodules/v80-vitis-flow/src/bd_builder/register.cpp +++ /dev/null @@ -1,54 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "register.hpp" - -Register::Register(std::string registerName, uint32_t offset, uint32_t width, std::string rw, - std::string description) - : registerName(registerName), offset(offset), width(width), rw(rw), description(description) {} - -std::string Register::getRegisterName() { return registerName; } - -uint32_t Register::getOffset() { return offset; } - -uint32_t Register::getWidth() { return width; } - -std::string Register::getRW() { return rw; } - -std::string Register::getDescription() { return description; } - -void Register::setRegisterName(std::string registerName) { this->registerName = registerName; } - -void Register::setOffset(uint32_t offset) { this->offset = offset; } - -void Register::setWidth(uint32_t width) { this->width = width; } - -void Register::setRW(std::string rw) { this->rw = rw; } - -void Register::setDescription(std::string description) { this->description = description; } - -void Register::print() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Register Name: {}", - registerName); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Offset: {}", offset); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Width: {}", width); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "RW: {}", rw); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Description: {}", description); -} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/src/bd_builder/system_map.cpp b/submodules/v80-vitis-flow/src/bd_builder/system_map.cpp deleted file mode 100644 index 68e9bcde..00000000 --- a/submodules/v80-vitis-flow/src/bd_builder/system_map.cpp +++ /dev/null @@ -1,96 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "system_map.hpp" - -SystemMap::SystemMap(bool segmented, Platform platform) { - this->segmented = segmented; - this->platform = platform; -} - -void SystemMap::addEntry(MapEntry entry) { this->entries.emplace_back(entry); } - -std::string SystemMap::intToHex(uint64_t value) { - std::stringstream ss; - ss << std::hex << std::showbase << value; - return ss.str(); -} - -// TODO: Prints to xml file -void SystemMap::printToFile() { - xmlDocPtr doc = xmlNewDoc(BAD_CAST "1.0"); - xmlNodePtr rootNode = xmlNewNode(NULL, BAD_CAST "SystemMap"); - xmlDocSetRootElement(doc, rootNode); - xmlNewChild(rootNode, NULL, BAD_CAST "Platform", - BAD_CAST(platform == Platform::HARDWARE - ? "Hardware" - : (platform == Platform::EMULATOR ? "Emulation" : "Simulation"))); - xmlNewChild(rootNode, NULL, BAD_CAST "Type", BAD_CAST(segmented ? "Segmented" : "Full")); - xmlNewChild(rootNode, NULL, BAD_CAST "ClockFrequency", - BAD_CAST std::to_string(targetClockFreq).c_str()); - for (auto& entry : entries) { - xmlNodePtr newNode = xmlNewChild(rootNode, NULL, BAD_CAST "Kernel", NULL); - xmlNewChild(newNode, NULL, BAD_CAST "Name", BAD_CAST entry.getName().c_str()); - xmlNewChild(newNode, NULL, BAD_CAST "BaseAddress", - BAD_CAST intToHex(entry.getBaseAddr()).c_str()); - xmlNewChild(newNode, NULL, BAD_CAST "Range", BAD_CAST intToHex(entry.getRange()).c_str()); - for (auto& reg : entry.getRegisters()) { - xmlNodePtr register_node = xmlNewChild(newNode, NULL, BAD_CAST "register", NULL); - xmlNewProp(register_node, BAD_CAST "offset", - BAD_CAST intToHex(reg.getOffset()).c_str()); - xmlNewProp(register_node, BAD_CAST "name", BAD_CAST reg.getRegisterName().c_str()); - xmlNewProp(register_node, BAD_CAST "access", BAD_CAST reg.getRW().c_str()); - xmlNewProp(register_node, BAD_CAST "description", - BAD_CAST reg.getDescription().c_str()); - xmlNewProp(register_node, BAD_CAST "range", - BAD_CAST std::to_string(reg.getWidth()).c_str()); - } - } - - for (auto& sc : qdmaStreamConnections) { - xmlNodePtr newNode = xmlNewChild(rootNode, NULL, BAD_CAST "Qdma", NULL); - xmlNewChild(newNode, NULL, BAD_CAST "kernel", BAD_CAST sc.kernelName.c_str()); - xmlNewChild(newNode, NULL, BAD_CAST "interface", BAD_CAST sc.interfaceName.c_str()); - xmlNewChild(newNode, NULL, BAD_CAST "qid", BAD_CAST std::to_string(sc.qid).c_str()); - xmlNewChild(newNode, NULL, BAD_CAST "direction", - BAD_CAST(sc.direction == StreamDirection::DEVICE_TO_HOST ? "DeviceToHost" - : "HostToDevice")); - } - - xmlSaveFormatFileEnc("system_map.xml", doc, "UTF-8", 1); - xmlFreeDoc(doc); - xmlCleanupParser(); - - // std::ofstream systemMapOutputFile(SYSTEM_MAP_OUTPUT); - // systemMapOutputFile << "# System Map\n"; - // systemMapOutputFile << "# Name\tBase Address\tRange\n"; - // for (auto& entry : entries) { - // systemMapOutputFile << " "<< entry.getName() << '\t' << std::hex << std::showbase << - // entry.getBaseAddr() << "\t" << entry.getRange() << std::endl; - // } - // systemMapOutputFile <<"# System Map end\n"; - // systemMapOutputFile.close(); -} - -void SystemMap::setClockFreq(uint64_t freq) { this->targetClockFreq = freq; } - -void SystemMap::addStreamConnection(StreamingConnection connection) { - this->qdmaStreamConnections.emplace_back(connection); -} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/src/sw_emu/emulator.cpp b/submodules/v80-vitis-flow/src/sw_emu/emulator.cpp deleted file mode 100644 index d2eb2e5f..00000000 --- a/submodules/v80-vitis-flow/src/sw_emu/emulator.cpp +++ /dev/null @@ -1,391 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "emulator.hpp" - -#include -#include -#include -#include - -Emulator::Emulator(std::vector paths, std::vector krnls, - std::vector conns) - : kernels(krnls), connections(conns) { - for (auto path : paths) { - JsonParser parser(path + JSON_PATH); - functions.emplace_back(parser.getFunction()); - } - - for (auto krnl : kernels) { - for (auto fn : functions) { - if (fn.getName() == krnl.getTopModelName()) { - functionCalls.emplace_back(FunctionCall(fn, krnl.getName())); - } - } - } - for (auto fnc : functionCalls) { - std::cout << fnc.getFunctionName() << std::endl; - } -} - -void Emulator::print() { - std::ofstream out("tb.cpp"); - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "#include \n"; - out << "\n\n"; - - for (auto fn : functions) { - out << fn.getFunctionPrototype() << '\n'; - } - - out << "\n\n"; - - out << "template \n"; - out << "void assignValue(T& var, const Json::Value& value) {\n"; - out << "\tif (value.isString()) {\n"; - out << "\t\tstd::istringstream iss(value.asString());\n"; - out << "\t\tiss >> var;\n"; - out << "\t} else if (value.isInt()) {\n"; - out << "\t\tvar = static_cast(value.asInt());\n"; - out << "\t} else if (value.isUInt()) {\n"; - out << "\t\tvar = static_cast(value.asUInt());\n"; - out << "\t} else if (value.isDouble()) {\n"; - out << "\t\tvar = static_cast(value.asDouble());\n"; - out << "\t} else {\n"; - out << "\t\tthrow std::runtime_error(\"Unsupported JSON value type\");\n"; - out << "\t}\n"; - out << "}\n\n"; - - out << "template \n"; - out << "Json::Value createJsonValue(const T& var) {\n"; - out << "\tJson::Value value;\n"; - out << "\tvalue = *reinterpret_cast(&var);\n"; - out << "\treturn value;\n"; - out << "}\n\n"; - - out << "Json::Value createJsonBuffer(const uint8_t* buffer, size_t size) {\n"; - out << "\tJson::Value value(Json::arrayValue);\n"; - out << "\tfor (size_t i = 0; i < size; ++i) {\n"; - out << "\t\tvalue.append(buffer[i]);\n"; - out << "\t}\n"; - out << "\treturn value;\n"; - out << "}\n\n"; - - out << "int main() {\n"; - out << "\t// Initialize zmq context and socket\n"; - out << "\tzmq::context_t context(1);\n"; - out << "\tzmq::socket_t socket(context, ZMQ_REP);\n"; - out << "\tsocket.bind(\"tcp://*:5555\");\n\n"; - - out << "\tstd::map buffers;\n"; - out << "\tstd::map bufferSizes;\n"; - out << "\tstd::map streamingBuffers;\n"; - - std::map streamingBuffers; - std::map streamTypes; - std::vector refVariables; - - // Declare variables for each function parameter - for (auto fnc : functionCalls) { - std::string fncName = fnc.getFunctionName(); - for (auto param : fnc.getFunction().getArgs()) { - std::string argType = param.getArgType(); - std::string argName = fncName + "_" + param.getName(); - - // Remove reference symbol '&' if present - bool isRef = false; - if (argType.back() == '&') { - argType.pop_back(); - isRef = true; - } - - if (argType.find("hls::stream") != std::string::npos) { - // Extract the data type from the stream type - std::string streamDataType = argType.substr( - argType.find('<') + 1, argType.rfind('>') - argType.find('<') - 1); - streamTypes[argName] = streamDataType; - continue; - } else if (argType.find('*') != std::string::npos) { - out << "\t" << argType.substr(0, argType.find('*')) << "* " << argName << ";\n"; - } else { - out << "\t" << argType << " " << argName << ";\n"; - if (isRef) { - refVariables.push_back(argName); - } - } - } - } - - out << "\n"; - - // Declare hls::stream variables for each unique stream type - std::map declaredStreams; - int streamCounter = 0, streamingBufferCounter = 0; - for (const auto& connection : connections) { - std::string srcStream = connection.src.kernelName + "_" + connection.src.interfaceName; - std::string dstStream = connection.dst.kernelName + "_" + connection.dst.interfaceName; - std::string streamDataType = streamTypes[srcStream]; - if (streamDataType == "") { - streamDataType = streamTypes[dstStream]; - } - if (streamDataType == "") { // both connections made to cips which is 512bit by default - streamDataType = "ap_uint<512>"; - } - - if (declaredStreams.find(srcStream) == declaredStreams.end()) { - std::string streamName; // = "stream_" + std::to_string(streamCounter++); - if (connection.src.kernelName == "cips") { - std::regex re("qdma_(\\d)"); - std::smatch match; - if (std::regex_search(connection.src.interfaceName, match, re) && - match.size() > 1) { - std::string number = match.str(1); - streamName = "streamingBuffer_" + number; - } else { - std::cerr << "Pattern not found in string: " << connection.src.interfaceName - << std::endl; - continue; - } - // streamName = "streamingBuffer_" + std::to_string(streamingBufferCounter++); - out << "\thls::stream> " << streamName << ";\n"; - declaredStreams[srcStream] = streamName; - declaredStreams[dstStream] = streamName; - streamTypes[streamName] = "ap_uint<512>"; // Populate streamTypes map - streamingBuffers[streamName] = nullptr; // change this - } else if (connection.dst.kernelName == "cips") { - std::regex re("qdma_(\\d)"); - std::smatch match; - if (std::regex_search(connection.dst.interfaceName, match, re) && - match.size() > 1) { - std::string number = match.str(1); - streamName = "outputStreamingBuffer_" + number; - } else { - // Handle the case where the pattern is not found - std::cerr << "Pattern not found in string: " << connection.dst.interfaceName - << std::endl; - continue; // or break, depending on how you want to handle this case - } - // streamName = "streamingBuffer_" + std::to_string(streamingBufferCounter++); - out << "\thls::stream> " << streamName << ";\n"; - declaredStreams[srcStream] = streamName; - declaredStreams[dstStream] = streamName; - streamTypes[streamName] = "ap_uint<512>"; // Populate streamTypes map - streamingBuffers[streamName] = nullptr; // change this - } else { - streamName = "stream_" + std::to_string(streamCounter++); - out << "\thls::stream<" << streamDataType << "> " << streamName << ";\n"; - declaredStreams[srcStream] = streamName; - declaredStreams[dstStream] = streamName; - streamTypes[streamName] = streamDataType; // Populate streamTypes map - - streamingBuffers[streamName] = nullptr; // change this - } - } else { - declaredStreams[dstStream] = declaredStreams[srcStream]; - } - } - // Create a map to store streaming buffers - for (const auto& connection : connections) { - if (connection.src.kernelName == "cips") { - std::string srcStream = connection.src.kernelName + "_" + connection.src.interfaceName; - out << "\tstreamingBuffers[\"" << declaredStreams[srcStream] - << "\"] = reinterpret_cast(&" << declaredStreams[srcStream] << ");\n"; - } else if (connection.dst.kernelName == "cips") { - std::string dstStream = connection.dst.kernelName + "_" + connection.dst.interfaceName; - out << "\tstreamingBuffers[\"" << declaredStreams[dstStream] - << "\"] = reinterpret_cast(&" << declaredStreams[dstStream] << ");\n"; - } - } - - out << "\n\twhile (true) {\n"; // Changed to infinite loop - out << "\t\tzmq::message_t request;\n"; - out << "\t\tsocket.recv(request);\n"; - out << "\t\tstd::string req_str(static_cast(request.data()), request.size());\n"; - out << "\t\tJson::Value root;\n"; - out << "\t\tJson::Reader reader;\n"; - out << "\t\treader.parse(req_str, root);\n"; - out << "\t\tstd::string command = root[\"command\"].asString();\n"; - out << "\t\tstd::string argType;\n"; - out << "\t\tif (command == \"populate\") {\n"; - out << "\t\t\tstd::string name = root[\"name\"].asString();\n"; - out << "\t\t\tsize_t bufferSize = root[\"size\"].asUInt64();\n"; - - out << "\t\t\tzmq::message_t data;\n"; - out << "\t\t\tsocket.recv(data);\n"; - out << "\t\t\tvoid* buffer = new uint8_t[bufferSize];\n"; - out << "\t\t\tmemcpy(buffer, data.data(), bufferSize);\n"; - - out << "\t\t\tbuffers[name] = buffer;\n"; - out << "\t\t\tbufferSizes[name] = bufferSize;\n"; - out << "\t\t\tsocket.send(zmq::message_t(\"OK\", 2), zmq::send_flags::none);\n"; // Send OK - // after - // populate - out << "\t\t} else if (command == \"stream_in\") {\n"; - out << "\t\t\tstd::string name = root[\"name\"].asString();\n"; - out << "\t\t\tzmq::message_t data;\n"; - out << "\t\t\tsocket.recv(data);\n"; - out << "\t\t\thls::stream>* stream = " - "reinterpret_cast>*>(streamingBuffers[name]);\n"; - out << "\t\t\tfor (size_t i = 0; i < data.size() / sizeof(ap_uint<512>); i++) {\n"; - out << "\t\t\t\tap_uint<512> value;\n"; - out << "\t\t\t\tmemcpy(&value, static_cast(data.data()) + i * sizeof(ap_uint<512>), " - "sizeof(ap_uint<512>));\n"; - out << "\t\t\t\tstream->write(value);\n"; - out << "\t\t\t}\n"; - out << "\t\t\tsocket.send(zmq::message_t(\"OK\", 2), zmq::send_flags::none);\n"; - out << "\t\t} else if (command == \"stream_out\") {\n"; - out << "\t\t\tstd::string name = root[\"name\"].asString();\n"; - out << "\t\t\tsize_t size = root[\"size\"].asUInt64();\n"; - out << "\t\t\thls::stream>* stream = " - "reinterpret_cast>*>(streamingBuffers[name]);\n"; - out << "\t\t\tstd::vector buffer(size);\n"; - out << "\t\t\tfor (size_t i = 0; i < size / sizeof(ap_uint<512>); i++) {\n"; - out << "\t\t\t\tap_uint<512> value = stream->read();\n"; - out << "\t\t\t\tmemcpy(buffer.data() + i * sizeof(ap_uint<512>), &value, " - "sizeof(ap_uint<512>));\n"; - out << "\t\t\t}\n"; - out << "\t\t\tsocket.send(zmq::message_t(buffer.data(), buffer.size()), " - "zmq::send_flags::none);\n"; - out << "\t\t} else if (command == \"call\") {\n"; - out << "\t\t\tstd::string functionName = root[\"function\"].asString();\n"; - - for (auto fnc : functionCalls) { - std::string fncName = fnc.getFunctionName(); - out << "\t\t\tif (functionName == \"" << fncName << "\") {\n"; - int idx = 0; - for (int i = 0; i < fnc.getFunction().getArgs().size(); ++i) { - std::string argIndex = "arg" + std::to_string(idx); - std::string argName = fncName + "_" + fnc.getFunction().getArgs()[i].getName(); - - if (fnc.getFunction().getArgs()[i].getArgType().find("hls::stream") != - std::string::npos) { - if (streamingBuffers.find(declaredStreams[argName]) != streamingBuffers.end()) { - // idx++; - // out << "\t\t\t\targType = root[\"args\"][\"" << argIndex << - // "\"][\"type\"].asString();\n"; - } - - continue; - } - - out << "\t\t\t\targType = root[\"args\"][\"" << argIndex - << "\"][\"type\"].asString();\n"; - - if (fnc.getFunction().getArgs()[i].getArgType().find('*') != std::string::npos) { - out << "\t\t\t\tif (argType == \"buffer\") {\n"; - out << "\t\t\t\t\tstd::string bufferName = root[\"args\"][\"" << argIndex - << "\"][\"name\"].asString();\n"; - out << "\t\t\t\t\tif (buffers.find(bufferName) != buffers.end()) {\n"; - out << "\t\t\t\t\t\t" << argName << " = static_cast<" - << fnc.getFunction().getArgs()[i].getArgType().substr( - 0, fnc.getFunction().getArgs()[i].getArgType().find('*')) - << "*>(buffers[bufferName]);\n"; - out << "\t\t\t\t\t}\n"; - out << "\t\t\t\t}\n"; - } else { - out << "\t\t\t\tif (argType == \"scalar\") {\n"; - out << "\t\t\t\t\tassignValue(" << argName << ", root[\"args\"][\"" << argIndex - << "\"][\"value\"]);\n"; - out << "\t\t\t\t}\n"; - } - idx++; - } - - out << "\t\t\t\t" << fnc.getFunction().getName() << "("; - - bool firstArg = true; - for (int i = 0; i < fnc.getFunction().getArgs().size(); ++i) { - std::string argName = fncName + "_" + fnc.getFunction().getArgs()[i].getName(); - - if (!firstArg) { - out << ", "; - } - firstArg = false; - - if (fnc.getFunction().getArgs()[i].getArgType().find("hls::stream") != - std::string::npos) { - out << declaredStreams[argName]; - } else { - out << argName; - } - } - - out << ");\n\t\t\t}\n"; - } - - out << "\t\t\tsocket.send(zmq::message_t(\"OK\", 2), zmq::send_flags::none);\n"; // Send OK - // after call - out << "\t\t} else if (command == \"fetch\") {\n"; - out << "\t\t\tstd::string type = root[\"type\"].asString();\n"; - out << "\t\t\tJson::Value response;\n"; - out << "\t\t\tif (type == \"scalar\") {\n"; - out << "\t\t\t\tstd::string functionName = root[\"function\"].asString();\n"; - out << "\t\t\t\tstd::string arg = root[\"arg\"].asString();\n"; - - for (auto fnc : functionCalls) { - std::string fncName = fnc.getFunctionName(); - for (int i = 0; i < fnc.getFunction().getArgs().size(); ++i) { - std::string argIndex = "arg" + std::to_string(i); - std::string argName = fncName + "_" + fnc.getFunction().getArgs()[i].getName(); - if (fnc.getFunction().getArgs()[i].getArgType().find("hls::stream") == - std::string::npos) { - out << "\t\t\t\tif (functionName == \"" << fncName << "\" && arg == \"" << argIndex - << "\") {\n"; - out << "\t\t\t\t\tresponse = createJsonValue(" << argName << ");\n"; - out << "\t\t\t\t}\n"; - } - } - } - - out << "\t\t\t} else if (type == \"buffer\") {\n"; - out << "\t\t\t\tstd::string name = root[\"name\"].asString();\n"; - out << "\t\t\t\tif (buffers.find(name) != buffers.end()) {\n"; - out << "\t\t\t\t\tresponse = createJsonBuffer(static_cast(buffers[name]), " - "bufferSizes[name]);\n"; - out << "\t\t\t\t}\n"; - out << "\t\t\t}\n"; - - out << "\t\t\tstd::string responseStr = Json::writeString(Json::StreamWriterBuilder(), " - "response);\n"; - out << "\t\t\tsocket.send(zmq::message_t(responseStr.c_str(), responseStr.size()), " - "zmq::send_flags::none);\n"; - out << "\t\t} else if (command == \"exit\") {\n"; - out << "\t\t\tsocket.send(zmq::message_t(\"OK\", 2), zmq::send_flags::none);\n"; - out << "\t\t\tbreak;\n"; - out << "\t\t}\n"; - out << "\t}\n"; - - // Print reference variables at the end - for (const auto& var : refVariables) { - out << "\tstd::cout << \"" << var << ": \" << " << var << " << std::endl;\n"; - } - - out << "\treturn 0;\n"; - out << "}\n"; -} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/src/sw_emu/json_parser.cpp b/submodules/v80-vitis-flow/src/sw_emu/json_parser.cpp deleted file mode 100644 index f7bae55a..00000000 --- a/submodules/v80-vitis-flow/src/sw_emu/json_parser.cpp +++ /dev/null @@ -1,69 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "json_parser.hpp" - -JsonParser::JsonParser(const std::string& file) { - std::ifstream jsonFile(file); - if (!jsonFile.is_open()) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, "Unable to open file {}", - file); - throw std::runtime_error("Unable to open json file"); - } - - Json::Value root; - jsonFile >> root; - - const Json::Value top = root["Top"]; - - if (top.isNull()) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Top field not found in json file"); - throw std::runtime_error("Top field not found in json file"); - } - std::string functionName = top.asString(); - - const Json::Value args = root["Args"]; - if (args.isNull()) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Args field not found in json file"); - throw std::runtime_error("Args field not found in json file"); - } - std::vector sortedArgs; - for (const auto& key : args.getMemberNames()) { - const Json::Value arg = args[key]; - int index = std::stoi(arg["index"].asString()); - sortedArgs.emplace_back(JsonFormat{index, arg, key}); - } - std::sort(sortedArgs.begin(), sortedArgs.end(), [](auto a, auto b) { return a.idx < b.idx; }); - - std::vector funcArgs; - for (const auto& pair : sortedArgs) { - const Json::Value& arg = pair.value; - Arg argObj(pair.key, std::stoul(arg["index"].asString()), arg["srcType"].asString()); - funcArgs.push_back(argObj); - std::string index = arg["index"].asString(); - std::string srcType = arg["srcType"].asString(); - } - - this->func = Func(functionName, funcArgs); -} - -Func JsonParser::getFunction() const { return this->func; } \ No newline at end of file diff --git a/submodules/v80-vitis-flow/src/utils/logger.cpp b/submodules/v80-vitis-flow/src/utils/logger.cpp deleted file mode 100644 index e8d55f60..00000000 --- a/submodules/v80-vitis-flow/src/utils/logger.cpp +++ /dev/null @@ -1,86 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "utils/logger.hpp" - -#include - -namespace utils { - -std::unique_ptr Logger::fileStream_ = nullptr; -std::ostream* Logger::output_ = &std::cout; -bool Logger::useColours_ = true; -LogLevel Logger::currentLogLevel_ = LogLevel::INFO; - -void Logger::setOutput(const std::string& filename) { - fileStream_ = std::make_unique(filename); - if (fileStream_->is_open()) { - output_ = fileStream_.get(); - useColours_ = false; - } else { - output_ = &std::cout; - useColours_ = true; - } -} - -std::string Logger::getColor(LogLevel level) { - if (useColours_ == false) { - return ""; - } - switch (level) { - case LogLevel::INFO: - return "\033[32m"; // Green - case LogLevel::ERROR: - return "\033[31m"; // Red - case LogLevel::DEBUG: - return "\033[34m"; // Blue - default: - return "\033[0m"; // Reset - } -} - -std::string Logger::getLevelString(LogLevel level) { - switch (level) { - case LogLevel::INFO: - return "INFO"; - case LogLevel::ERROR: - return "ERROR"; - case LogLevel::DEBUG: - return "DEBUG"; - default: - return "UNKNOWN"; - } -} - -std::string Logger::getCurrentTime() { - auto now = std::chrono::system_clock::now(); - auto now_time_t = std::chrono::system_clock::to_time_t(now); - auto now_ms = - std::chrono::duration_cast(now.time_since_epoch()) % 1000; - - std::ostringstream oss; - oss << std::put_time(std::localtime(&now_time_t), "%Y-%m-%d %H:%M:%S") << '.' - << std::setfill('0') << std::setw(3) << now_ms.count(); - return oss.str(); -} - -void Logger::setLogLevel(LogLevel level) { currentLogLevel_ = level; } - -} // namespace utils diff --git a/submodules/v80-vitis-flow/src/xml_parser/interface.cpp b/submodules/v80-vitis-flow/src/xml_parser/interface.cpp deleted file mode 100644 index 540fd6fa..00000000 --- a/submodules/v80-vitis-flow/src/xml_parser/interface.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "interface.hpp" - -std::string Interface::getInterfaceName() { return this->interfaceName; } -void Interface::setInterfaceName(const std::string& intf_name) { this->interfaceName = intf_name; } - -std::string Interface::getInterfaceType() { return this->interfaceType; } - -void Interface::setInterfaceType(const std::string& intf_type) { this->interfaceType = intf_type; } - -std::string Interface::getBusType() { return this->busType; } - -void Interface::setBusType(const std::string& bus_type) { this->busType = bus_type; } - -std::string Interface::getMode() { return this->mode; } - -void Interface::setMode(const std::string& mode) { this->mode = mode; } - -uint8_t Interface::getDataWidth() { return this->dataWidth; } - -void Interface::setDataWidth(uint8_t dw) { this->dataWidth = dw; } - -uint8_t Interface::getAddrWidth() { return this->addrWidth; } - -void Interface::setAddrWidth(uint8_t aw) { this->addrWidth = aw; } - -void Interface::print() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Interface name: {}", - interfaceName); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Interface type: {}", - interfaceType); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Bus type: {}", busType); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Mode: {}", mode); - if (busType == "aximm") { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Data width: {}", - static_cast(dataWidth)); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Addr width: {}", - static_cast(addrWidth)); - } -} \ No newline at end of file diff --git a/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp b/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp deleted file mode 100644 index 1e08bbf2..00000000 --- a/submodules/v80-vitis-flow/src/xml_parser/kernel.cpp +++ /dev/null @@ -1,95 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include "kernel.hpp" - -std::string Kernel::getBuildVersion() { return this->buildVersion; } -void Kernel::setBuildVersion(const std::string& bv) { this->buildVersion = bv; } - -std::string Kernel::getUnit() { return this->unit; } -void Kernel::setUnit(const std::string& unit) { this->unit = unit; } - -std::string Kernel::getProductFamily() { return this->productFamily; } -void Kernel::setProductFamily(const std::string& pf) { this->productFamily = pf; } - -std::string Kernel::getPart() { return this->part; } -void Kernel::setPart(const std::string& p) { this->part = p; } - -std::string Kernel::getTopModelName() { return this->topModelName; } -void Kernel::setTopModelName(const std::string& tm) { this->topModelName = tm; } - -float Kernel::getTargetClk() { return this->targetClk; } -void Kernel::setTargetClk(float tclk) { this->targetClk = tclk; } - -float Kernel::getClkUncertainty() { return this->clkUncertainty; } -void Kernel::setClkUncertainty(float clkUncertainty) { this->clkUncertainty = clkUncertainty; } - -float Kernel::getEstimatedClk() { return this->estimatedClk; } -void Kernel::setEstimatedClk(float estimatedClk) { this->estimatedClk = estimatedClk; } - -AreaEstimates Kernel::getAreaEstimates() { return this->estimates; } -void Kernel::addEstimate(ResourceType type, Resource resource) { - if (type == RESOURCE_TYPE_USED) { - this->estimates.addResource(resource); - } else { - this->estimates.addAvailableResource(resource); - } -} - -std::vector Kernel::getInterfaces() { return this->interfaces; } -void Kernel::addInterface(Interface intf) { this->interfaces.emplace_back(intf); } - -void Kernel::addRegister(Register r) { this->registers.emplace_back(r); } - -std::vector Kernel::getRegisters() { return this->registers; } - -void Kernel::setName(const std::string& instName) { this->name = instName; } -std::string Kernel::getName() { return name; } - -void Kernel::print() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Kernel instantiation name: {}", - name); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Build Version: {}", - buildVersion); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Time unit: {}", unit); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Product family: {}", - productFamily); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Product part: {}", part); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Top function name: {}", - topModelName); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Target clock period: {} {}", - targetClk, unit); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Target clock freq: {} MHz", - (1 / targetClk) * 1000); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Clock uncertainty: {}", - clkUncertainty); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Estimated clock: {} {}", - estimatedClk, unit); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Estimated clock freq: {} MHz", - (1 / estimatedClk) * 1000); - estimates.print(); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Interfaces:"); - for (auto el : interfaces) { - el.print(); - } - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Registers:"); - for (auto& el : registers) { - el.print(); - } -} diff --git a/submodules/v80-vitis-flow/src/xml_parser/xml_parser.cpp b/submodules/v80-vitis-flow/src/xml_parser/xml_parser.cpp deleted file mode 100644 index 7947927a..00000000 --- a/submodules/v80-vitis-flow/src/xml_parser/xml_parser.cpp +++ /dev/null @@ -1,172 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "xml_parser.hpp" - -#include - -#include "defines.hpp" - -std::string XmlParser::convertFromXmlCharPtr(const xmlChar* str) { - if (str == nullptr) { - return std::string(); - } else { - return std::string(reinterpret_cast(str)); - } -} - -XmlParser::XmlParser(const std::string& fileName) { - this->fileName = fileName; - this->document = xmlReadFile(fileName.c_str(), nullptr, 0); - if (this->document == nullptr) { - throw std::runtime_error("Error: Unable to parse the XML file"); - } - rootNode = xmlDocGetRootElement(document); - workingNode = rootNode->children; -} - -void XmlParser::parseXml() { - for (auto current_node = workingNode; current_node; current_node = current_node->next) { - if (current_node->type == XML_ELEMENT_NODE) { - xmlChar* content = xmlNodeGetContent(current_node); - std::string contentStr = convertFromXmlCharPtr(content); - std::string nodeNameStr = convertFromXmlCharPtr(current_node->name); - // std::cout << "Node Name: " << nodeNameStr << ", Content: " << contentStr << - // std::endl; - if (nodeNameStr == XML_NODE_REGISTER) { - xmlChar* offset = xmlGetProp(current_node, BAD_CAST "offset"); - xmlChar* name = xmlGetProp(current_node, BAD_CAST "name"); - xmlChar* access = xmlGetProp(current_node, BAD_CAST "access"); - xmlChar* description = xmlGetProp(current_node, BAD_CAST "description"); - xmlChar* range = xmlGetProp(current_node, BAD_CAST "range"); - - std::string offsetStr = convertFromXmlCharPtr(offset); - std::string nameStr = convertFromXmlCharPtr(name); - std::string accessStr = convertFromXmlCharPtr(access); - std::string descriptionStr = convertFromXmlCharPtr(description); - std::string rangeStr = convertFromXmlCharPtr(range); - Register r; - r.setRegisterName(nameStr); - r.setOffset(std::stoi(offsetStr, nullptr, 16)); - r.setWidth(std::stoi(rangeStr)); - r.setRW(accessStr); - r.setDescription(descriptionStr); - kernel.addRegister(r); - // std::cout << "Register - Offset: " << offsetStr - // << ", Name: " << nameStr - // << ", Access: " << accessStr - // << ", Description: " << descriptionStr - // << ", Range: " << rangeStr << std::endl; - } else if (nodeNameStr == XML_NODE_VERSION) { - kernel.setBuildVersion(contentStr); - } else if (nodeNameStr == XML_NODE_UNIT) { - kernel.setUnit(contentStr); - } else if (nodeNameStr == XML_NODE_PRODUCT_FAMILY) { - kernel.setProductFamily(contentStr); - } else if (nodeNameStr == XML_NODE_PART) { - kernel.setPart(contentStr); - } else if (nodeNameStr == XML_NODE_TOP_MODEL_NAME) { - kernel.setTopModelName(contentStr); - } else if (nodeNameStr == XML_NODE_TARGET_CLK) { - kernel.setTargetClk(std::stof(contentStr)); - } else if (nodeNameStr == XML_NODE_CLK_UNCERTAINTY) { - kernel.setClkUncertainty(std::stof(contentStr)); - } else if (nodeNameStr == XML_NODE_ESTIMATED_CLK) { - kernel.setEstimatedClk(std::stof(contentStr)); - } else if (nodeNameStr == XML_NODE_BRAM_18K) { - Resource resource; - resource.setName(nodeNameStr); - resource.setValue(std::stoi(contentStr)); - if (kernel.getAreaEstimates().getUsedResources().empty()) { - kernel.addEstimate(RESOURCE_TYPE_USED, resource); - } else if (kernel.getAreaEstimates().getAvailableResources().empty()) { - kernel.addEstimate(RESOURCE_TYPE_AVAILABLE, resource); - } - } else if (nodeNameStr == XML_NODE_FF) { - Resource resource; - resource.setName(nodeNameStr); - resource.setValue(std::stoi(contentStr)); - if (kernel.getAreaEstimates().getUsedResources().size() == 1) { - kernel.addEstimate(RESOURCE_TYPE_USED, resource); - } else if (kernel.getAreaEstimates().getAvailableResources().size() == 1) { - kernel.addEstimate(RESOURCE_TYPE_AVAILABLE, resource); - } - } else if (nodeNameStr == XML_NODE_LUT) { - Resource resource; - resource.setName(nodeNameStr); - resource.setValue(std::stoi(contentStr)); - if (kernel.getAreaEstimates().getUsedResources().size() == 2) { - kernel.addEstimate(RESOURCE_TYPE_USED, resource); - } else if (kernel.getAreaEstimates().getAvailableResources().size() == 2) { - kernel.addEstimate(RESOURCE_TYPE_AVAILABLE, resource); - } - } else if (nodeNameStr == XML_NODE_URAM) { - Resource resource; - resource.setName(nodeNameStr); - resource.setValue(std::stoi(contentStr)); - if (kernel.getAreaEstimates().getUsedResources().size() == 3) { - kernel.addEstimate(RESOURCE_TYPE_USED, resource); - } else if (kernel.getAreaEstimates().getAvailableResources().size() == 3) { - kernel.addEstimate(RESOURCE_TYPE_AVAILABLE, resource); - } - } else if (nodeNameStr == XML_NODE_DSP) { - Resource resource; - resource.setName(nodeNameStr); - resource.setValue(std::stoi(contentStr)); - if (kernel.getAreaEstimates().getUsedResources().size() == 4) { - kernel.addEstimate(RESOURCE_TYPE_USED, resource); - } else if (kernel.getAreaEstimates().getAvailableResources().size() == 4) { - kernel.addEstimate(RESOURCE_TYPE_AVAILABLE, resource); - } - } else if (nodeNameStr == XML_NODE_INTERFACE) { - Interface intf; - for (xmlAttr* attr = current_node->properties; attr; attr = attr->next) { - xmlChar* value = xmlGetProp(current_node, attr->name); - std::string attrNameStr = convertFromXmlCharPtr(attr->name); - std::string valueStr = convertFromXmlCharPtr(value); - if (attrNameStr == XML_ATTR_INTF_NAME) { - intf.setInterfaceName(valueStr); - } else if (attrNameStr == XML_ATTR_TYPE) { - intf.setInterfaceType(valueStr); - } else if (attrNameStr == XML_ATTR_MODE) { - intf.setMode(valueStr); - } else if (attrNameStr == XML_ATTR_BUS_TYPE) { - intf.setBusType(valueStr); - } else if (attrNameStr == XML_ATTR_DATA_WIDTH) { - intf.setDataWidth(std::stoi(valueStr)); - } else if (attrNameStr == XML_ATTR_ADDR_WIDTH) { - if (std::stoi(valueStr) >= 7) { // min 2^7 offset - intf.setAddrWidth(std::stoi(valueStr)); - } else { - intf.setAddrWidth(7); - } - } - xmlFree(value); - } - kernel.addInterface(intf); - } - xmlFree(content); - } - workingNode = current_node->children; - parseXml(); - } -} - -Kernel XmlParser::getKernel() { return kernel; } \ No newline at end of file diff --git a/submodules/v80-vitis-flow/submodules/aved b/submodules/v80-vitis-flow/submodules/aved deleted file mode 160000 index 7497599d..00000000 --- a/submodules/v80-vitis-flow/submodules/aved +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7497599d2b452846515d7f2f22ad6bea2ebef522 diff --git a/vrt/.gitignore b/vrt/.gitignore new file mode 100644 index 00000000..325ab0db --- /dev/null +++ b/vrt/.gitignore @@ -0,0 +1 @@ +doc \ No newline at end of file diff --git a/vrt/CMakeLists.txt b/vrt/CMakeLists.txt index eec2e01c..bdd8c2b8 100644 --- a/vrt/CMakeLists.txt +++ b/vrt/CMakeLists.txt @@ -1,6 +1,6 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -19,27 +19,190 @@ # ################################################################################################## cmake_minimum_required(VERSION 3.10) -project(vrt-api) + +# Read version from packaging/version +file(READ "${CMAKE_CURRENT_SOURCE_DIR}/../packaging/version" VRT_VERSION) +string(STRIP "${VRT_VERSION}" VRT_VERSION) + +# Parse into components +string(REPLACE "." ";" VERSION_LIST "${VRT_VERSION}") +list(GET VERSION_LIST 0 VRT_VERSION_MAJOR) +list(GET VERSION_LIST 1 VRT_VERSION_MINOR) +list(GET VERSION_LIST 2 VRT_VERSION_PATCH) + +message(STATUS "VRT version: ${VRT_VERSION} (${VRT_VERSION_MAJOR}.${VRT_VERSION_MINOR}.${VRT_VERSION_PATCH})") + +project( + vrt + + VERSION ${VRT_VERSION} + LANGUAGES C CXX +) set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) + +option(VRT_INCLUDE_VRTD "Include vrtd subdirectory instead of building from system" OFF) +option(VRT_BUILD_TESTS "Build unit tests" OFF) + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) + add_compile_options("-Wunused-result") -include_directories(${CMAKE_SOURCE_DIR}/include/ ${CMAKE_SOURCE_DIR}/src/ /usr/include/ami/ /usr/include/libxml2 /usr/include/jsoncpp) +option(ENABLE_SANITIZERS "Build with AddressSanitizer and UBSan" OFF) +if(ENABLE_SANITIZERS) + add_compile_options(-fsanitize=address,undefined -fno-omit-frame-pointer) + add_link_options(-fsanitize=address,undefined) +endif() -file(GLOB LIB_SOURCES ${CMAKE_SOURCE_DIR}/src/allocator/*.cpp ${CMAKE_SOURCE_DIR}/include/buffer/*.hpp -${CMAKE_SOURCE_DIR}/src/qdma/*.cpp ${CMAKE_SOURCE_DIR}/src/api/*.cpp -${CMAKE_SOURCE_DIR}/src/parser/*.cpp ${CMAKE_SOURCE_DIR}/src/register/*.cpp ${CMAKE_SOURCE_DIR}/src/driver/*.cpp -${CMAKE_SOURCE_DIR}/src/utils/*.cpp) +option(ENABLE_COVERAGE "Build with gcov coverage instrumentation" OFF) +if(ENABLE_COVERAGE) + if(ENABLE_SANITIZERS) + message(FATAL_ERROR "ENABLE_COVERAGE and ENABLE_SANITIZERS cannot be used together") + endif() + add_compile_options(--coverage -fno-inline) + add_link_options(--coverage) +endif() + +# Generate the header +configure_file( + "${CMAKE_CURRENT_SOURCE_DIR}/cmake/vrt_version.hpp.in" + "${CMAKE_CURRENT_BINARY_DIR}/generated/vrt/vrt_version.hpp" + @ONLY +) + +file( + GLOB + LIB_SOURCES + + ${CMAKE_CURRENT_SOURCE_DIR}/src/allocator/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/include/buffer/*.hpp + ${CMAKE_CURRENT_SOURCE_DIR}/src/qdma/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/src/parser/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/src/register/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/src/driver/*.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/src/utils/*.cpp +) add_library(vrt SHARED ${LIB_SOURCES}) +add_library(vrt::vrt ALIAS vrt) + +target_include_directories( + vrt + + PUBLIC + $ + $ + $ + + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/src/ +) + +set_target_properties(vrt PROPERTIES + + VERSION ${PROJECT_VERSION} + SOVERSION ${PROJECT_VERSION_MAJOR} +) + + +if(VRT_INCLUDE_VRTD) + add_subdirectory(vrtd vrtd) +else() + find_package(vrtd REQUIRED CONFIG) +endif() + +if(NOT TARGET vrtd::libvrtdpp) + message(FATAL_ERROR + "vrtd package is missing target vrtd::libvrtdpp. " + "Build and install vrtd first (cmake --install), then configure vrt again.") +endif() + +find_package(ZLIB REQUIRED) +find_package(LibXml2 REQUIRED) +find_package(jsoncpp CONFIG REQUIRED) + +if(NOT TARGET JsonCpp::JsonCpp AND TARGET jsoncpp_lib) + add_library(JsonCpp::JsonCpp ALIAS jsoncpp_lib) +endif() + +find_package(PkgConfig REQUIRED) +pkg_check_modules(PC_ZMQ REQUIRED IMPORTED_TARGET libzmq) + +target_link_libraries(vrt + PUBLIC + vrtd::libvrtdpp + ZLIB::ZLIB + LibXml2::LibXml2 + JsonCpp::JsonCpp + PkgConfig::PC_ZMQ +) + +# Testing +if(VRT_BUILD_TESTS) + add_subdirectory(tests) +endif() + +# Installation + set_target_properties(vrt PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) -install(TARGETS vrt - LIBRARY DESTINATION lib - ARCHIVE DESTINATION lib) +install( + DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/include/ + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/generated/ + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + TARGETS vrt + EXPORT vrtTargets + ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}" + LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}" + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" + INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +# -------- CMake package configuration -------- +# Generate the version file +write_basic_package_version_file( + "${CMAKE_CURRENT_BINARY_DIR}/vrtConfigVersion.cmake" + VERSION ${PROJECT_VERSION} + COMPATIBILITY SameMinorVersion +) + +# Configure the main package config from template +configure_package_config_file( + "${PROJECT_SOURCE_DIR}/cmake/vrtConfig.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/vrtConfig.cmake" + INSTALL_DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrt" +) + +# Export targets for *install* tree +install( + EXPORT vrtTargets + NAMESPACE vrt:: + FILE vrtTargets.cmake + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrt" +) + +# Install the config + version files +install( + FILES + "${CMAKE_CURRENT_BINARY_DIR}/vrtConfig.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/vrtConfigVersion.cmake" + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrt" +) -install(DIRECTORY ${CMAKE_SOURCE_DIR}/include/ DESTINATION vrt/include) -install(DIRECTORY ${CMAKE_SOURCE_DIR}/scripts/ DESTINATION vrt - FILE_PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE) \ No newline at end of file +# Export targets for *build* tree so a project can use this directory directly +export( + EXPORT vrtTargets + NAMESPACE vrt:: + FILE "${CMAKE_CURRENT_BINARY_DIR}/vrtTargets.cmake" +) diff --git a/vrt/README.md b/vrt/README.md new file mode 100644 index 00000000..74f629b0 --- /dev/null +++ b/vrt/README.md @@ -0,0 +1,218 @@ +# VRT (V80 RunTime) + +C++17 runtime library for executing FPGA kernels on the AMD Alveo V80. +VRT provides a unified API for hardware, emulation, and simulation +platforms, handling device management, memory allocation, kernel +dispatch, and streaming DMA. + +| Class | Header | Purpose | +|--------------------|---------------------------|------------------------------------------| +| `Device` | `vrt/device.hpp` | Open a V80 board and load a vrtbin | +| `Kernel` | `vrt/kernel.hpp` | Set arguments, launch, and wait | +| `Buffer` | `vrt/buffer.hpp` | Typed device memory with host sync | +| `StreamingBuffer` | `vrt/streaming_buffer.hpp` | QDMA streaming I/O for kernel ports | +| `Vrtbin` | `vrt/vrtbin.hpp` | Archive extraction and metadata lookup | + +## Building + +```sh +cmake -B build -S . -G Ninja +cmake --build build +``` + +CMake options: + +| Option | Default | Description | +|----------------------|---------|--------------------------------------------------| +| `VRT_INCLUDE_VRTD` | `OFF` | Build the bundled vrtd daemon instead of using the system package | +| `ENABLE_SANITIZERS` | `OFF` | Build with AddressSanitizer and UBSan | + +## Installing + +```sh +sudo cmake --install build --prefix /usr/local +``` + +This installs: + +- Headers to `/include/vrt/` +- Library to `/lib/libvrt.so` +- CMake package config to `/lib/cmake/vrt/` + +Downstream projects can then use: + +```cmake +find_package(vrt REQUIRED CONFIG) +target_link_libraries(myapp PRIVATE vrt::vrt) +``` + +## Dependencies + +| Library | Package (apt) | Purpose | +|------------|----------------------|--------------------------------------| +| libxml2 | `libxml2-dev` | system_map.xml parsing | +| ZeroMQ | `libzmq3-dev` | Emulation and simulation IPC | +| JsonCpp | `libjsoncpp-dev` | Emulation manifest and JSON commands | +| ZLIB | `zlib1g-dev` | vrtbin archive decompression | +| vrtd | (bundled or system) | Low-level device access daemon | + +```sh +sudo apt install libxml2-dev libzmq3-dev libjsoncpp-dev zlib1g-dev +``` + +## API overview + +### Open a device and run kernels + +```cpp +#include +#include +#include + +vrt::Device device(bdf, vrtbinPath); + +vrt::Kernel kernel(device, "my_kernel_0"); + +/* Allocate a buffer on the memory bank the kernel argument is connected to */ +vrt::Buffer buf(device, 1024, kernel.argMemoryConfig("in")); + +/* Fill host side, then sync to device */ +for (uint32_t i = 0; i < 1024; i++) + buf[i] = static_cast(i); +buf.sync(vrt::SyncType::HOST_TO_DEVICE); + +/* Launch the kernel and wait for completion */ +kernel.setArg(0, 1024); /* scalar argument */ +kernel.setArg(1, buf); /* buffer argument (auto-resolves to physical address) */ +kernel.start(); +kernel.wait(); + +/* Read a result register */ +uint32_t result = kernel.read(0x18); + +device.cleanup(); +``` + +### Buffer memory types + +```cpp +/* DDR */ +vrt::Buffer ddr(device, size, vrt::MemoryRangeType::DDR); + +/* HBM via virtual network-on-chip (auto-placed) */ +vrt::Buffer hbm(device, size, vrt::MemoryRangeType::HBM_VNOC); + +/* HBM on a specific port (kernel metadata) */ +vrt::Buffer hbm(device, size, kernel.argMemoryConfig("in")); +``` + +### Streaming buffers (QDMA) + +```cpp +#include + +vrt::StreamingBuffer sbuf(device, kernel, "s_axis_data", size); +for (uint32_t i = 0; i < size; i++) + sbuf[i] = i; +sbuf.sync(); /* direction is inferred from port configuration */ +``` + +### Kernel launch styles + +#### Argument style + +Arguments can be passed inline or staged with `setArg` before the launch call: + +```cpp +/* Inline: pass arguments directly */ +kernel.call(size, buf); +kernel.start(size, buf); + +/* Staged: set arguments by index or name, then launch */ +kernel.setArg(0, size); +kernel.setArg("buf", buf); +kernel.call(); /* or kernel.start() */ +``` + +#### Call vs. start (blocking vs. non-blocking) + +`call` launches and waits; `start` launches and returns immediately so other work can proceed while the kernel runs: + +```cpp +/* Blocking */ +kernel.call(size, buf); + +/* Non-blocking */ +kernel.start(size, buf); +/* ... do other work ... */ +kernel.wait(); +``` + +## Platform support + +VRT transparently supports three execution platforms, selected by the +vrtbin contents: + +| Platform | Enum | Description | +|--------------|---------------------------|------------------------------------------| +| Hardware | `vrt::Platform::HARDWARE` | Real FPGA via PCIe BAR and QDMA | +| Emulation | `vrt::Platform::EMULATION` | C-model software emulation via ZeroMQ | +| Simulation | `vrt::Platform::SIMULATION` | Verilog simulation via register map | + +Kernel and buffer code paths adapt automatically. Check the current +platform with `device.getPlatform()`. + +## API documentation + +Doxygen HTML and PDF documentation can be generated from the +[doc/](doc/) directory. See [doc/README.md](doc/README.md) for +instructions. + +## Project layout + +``` +vrt/ + include/vrt/ + device.hpp Public API - device management + kernel.hpp Public API - kernel execution + buffer.hpp Public API - typed device memory + streaming_buffer.hpp Public API - QDMA streaming buffers + vrtbin.hpp Public API - archive handling + allocator/ + allocator.hpp Memory allocator (buddy system) + driver/ + qdma_logic.hpp QDMA driver logic + parser/ + xml_parser.hpp system_map.xml parser + utilization_parser.hpp Resource utilization parser + utilization_data.hpp Utilization report data structures + qdma/ + pcie_driver_handler.hpp PCIe driver handler + qdma_connection.hpp QDMA streaming connection metadata + qdma_intf.hpp QDMA interface abstraction + register/ + register.hpp Hardware register abstraction + utils/ + filesystem_cache.hpp Filesystem cache utility + logger.hpp Logging facility + platform.hpp Platform enum + zmq_server.hpp ZeroMQ IPC server + src/ + device.cpp Device implementation + kernel.cpp Kernel implementation + vrtbin.cpp Vrtbin archive extraction + allocator/ Memory allocator implementation + driver/ Driver interface implementation + parser/ XML/utilization parser implementation + qdma/ QDMA subsystem implementation + register/ Register access implementation + utils/ Utility implementations + doc/ + Doxyfile Doxygen configuration + Makefile Documentation build + vrtd/ V80 runtime daemon (see vrtd/README.md) +``` + +## License + +MIT — see [LICENSE](../LICENSE). diff --git a/vrt/cmake/vrtConfig.cmake.in b/vrt/cmake/vrtConfig.cmake.in new file mode 100644 index 00000000..6473579f --- /dev/null +++ b/vrt/cmake/vrtConfig.cmake.in @@ -0,0 +1,39 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +@PACKAGE_INIT@ + +include(CMakeFindDependencyMacro) + +# Library dependencies +find_dependency(slash) +find_dependency(vrtd) + +# Transitive dependencies (vrt links these PUBLIC) +find_dependency(ZLIB) +find_dependency(LibXml2) +find_dependency(jsoncpp CONFIG) +if(NOT TARGET JsonCpp::JsonCpp AND TARGET jsoncpp_lib) + add_library(JsonCpp::JsonCpp ALIAS jsoncpp_lib) +endif() +find_dependency(PkgConfig) +pkg_check_modules(PC_ZMQ REQUIRED IMPORTED_TARGET libzmq) + +include("${CMAKE_CURRENT_LIST_DIR}/vrtTargets.cmake") diff --git a/vrt/include/api/vrt_version.hpp b/vrt/cmake/vrt_version.hpp.in similarity index 74% rename from vrt/include/api/vrt_version.hpp rename to vrt/cmake/vrt_version.hpp.in index 4c05545a..0634357e 100644 --- a/vrt/include/api/vrt_version.hpp +++ b/vrt/cmake/vrt_version.hpp.in @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,25 +18,25 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef VRT_VERSION_HPP -#define VRT_VERSION_HPP - -#define GIT_TAG "v1.0.0" -#define VRT_VERSION_MAJOR 1 -#define VRT_VERSION_MINOR 0 -#define VRT_VERSION_PATCH 0 +#ifndef VRT_VRT_VERSION_HPP +#define VRT_VRT_VERSION_HPP namespace vrt { +constexpr char VERSION[] = "@VRT_VERSION@"; +constexpr unsigned int VERSION_MAJOR = @VRT_VERSION_MAJOR@; +constexpr unsigned int VERSION_MINOR = @VRT_VERSION_MINOR@; +constexpr unsigned int VERSION_PATCH = @VRT_VERSION_PATCH@; + /** * @brief Returns the version of the VRT library as a string. * * @return A string representing the version of the VRT library. */ -inline const char* getVersion() { - return GIT_TAG; // Returns the version string defined by GIT_TAG +constexpr const char* getVersion() { + return VERSION; } } // namespace vrt -#endif // VRT_VERSION_HPP +#endif // VRT_VRT_VERSION_HPP diff --git a/vrt/include/allocator/allocator.hpp b/vrt/include/allocator/allocator.hpp deleted file mode 100644 index 1355b49f..00000000 --- a/vrt/include/allocator/allocator.hpp +++ /dev/null @@ -1,162 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef ALLOCATOR_HPP -#define ALLOCATOR_HPP - -#include -#include -#include -#include -#include -namespace vrt { - -/** - * @brief Enum class representing the type of memory range. - */ -enum class MemoryRangeType { - HBM, ///< High Bandwidth Memory - DDR ///< Double Data Rate Memory -}; - -/// Starting address of HBM -constexpr uint64_t HBM_START = 0x4000000000; -/// Size of HBM (32 GB) -constexpr uint64_t HBM_SIZE = 32L * 1024 * 1024 * 1024; // 32G -/// Size of HBM Port (1 GB) -constexpr uint64_t HBM_PORT_SIZE = 1L * 1024 * 1024 * 1024; // 1G - -/// Starting address of DDR DIMM -constexpr uint64_t DDR_START = 0x60000000000; -/// Size of DDR (32 GB) -constexpr uint64_t DDR_SIZE = 32L * 1024 * 1024 * 1024; // 32G - -/** - * @brief Class representing a superblock of memory. - */ -class Superblock { - public: - /** - * @brief Constructor for Superblock. - * @param startAddress The starting address of the superblock. - * @param size The size of the superblock. - */ - Superblock(uint64_t startAddress, uint64_t size); - - /** - * @brief Allocates a block of memory from the superblock. - * @param size The size of the memory block to allocate. - * @return The starting address of the allocated memory block. - */ - uint64_t allocate(uint64_t size); - - /** - * @brief Deallocates a block of memory. - * @param addr The starting address of the memory block to deallocate. - */ - void deallocate(uint64_t addr); - - uint64_t startAddress; ///< The starting address of the superblock. - private: - uint64_t size; ///< The size of the superblock. - uint64_t offset; ///< The current offset for allocation. - std::vector freeList; ///< List of free memory blocks. -}; - -/** - * @brief Struct representing a range of memory. - */ -struct MemoryRange { - uint64_t startAddress; ///< The starting address of the memory range. - uint64_t size; ///< The size of the memory range. - uint64_t offset; ///< The current offset for allocation. - std::vector superblocks; ///< List of superblocks in the memory range. - std::vector freeList; ///< List of free memory blocks. - std::vector> usedMemoryBlocks; ///< List of used memory blocks. - /** - * @brief Constructor for MemoryRange. - * @param startAddress The starting address of the memory range. - * @param size The size of the memory range. - */ - MemoryRange(uint64_t startAddress, uint64_t size); -}; - -/** - * @brief Class representing a memory allocator. - */ -class Allocator { - public: - /** - * @brief Constructor for Allocator. - * @param superblockSize The size of the superblocks to use. - */ - Allocator(uint64_t superblockSize = 4096); - - Allocator() : Allocator(4096) {} - - /** - * @brief Adds a memory range to the allocator. - * @param type The type of memory range (HBM or DDR). - * @param startAddress The starting address of the memory range. - * @param size The size of the memory range. - */ - void addMemoryRange(MemoryRangeType type, uint64_t startAddress, uint64_t size); - - /** - * @brief Allocates a block of memory. - * @param size The size of the memory block to allocate. - * @param type The type of memory range to allocate from (HBM or DDR). - * @return The starting address of the allocated memory block. - */ - uint64_t allocate(uint64_t size, MemoryRangeType type); - - /** - * @brief Deallocates a block of memory. - * @param addr The starting address of the memory block to deallocate. - */ - void deallocate(uint64_t addr); - - /** - * @brief Allocates a block of memory from the specified port. - * @param size The size of the memory block to allocate. - * @param type The type of memory range to allocate from (HBM or DDR). - * @param port The port to allocate from. - * @return The starting address of the allocated memory block. - */ - uint64_t allocate(uint64_t size, MemoryRangeType type, uint8_t port); - - /** - * @brief Gets the size of the specified memory range type. - * @param type The type of memory range (HBM or DDR). - * @return The size of the specified memory range type. - */ - uint64_t getSize(MemoryRangeType type) const; - - private: - uint64_t superblockSize; ///< The size of the superblocks. - std::unordered_map - memoryRanges; ///< Map of memory ranges by type. - std::unordered_map - addrToSuperblock; ///< Map of addresses to superblocks. -}; - -} // namespace vrt - -#endif // ALLOCATOR_HPP \ No newline at end of file diff --git a/vrt/include/api/buffer.hpp b/vrt/include/api/buffer.hpp deleted file mode 100644 index 7650724f..00000000 --- a/vrt/include/api/buffer.hpp +++ /dev/null @@ -1,323 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef BUFFER_HPP -#define BUFFER_HPP - -#include "allocator/allocator.hpp" -#include "api/device.hpp" -#include "qdma/qdma_intf.hpp" -#include "utils/platform.hpp" -#include "utils/zmq_server.hpp" - -namespace vrt { - -/** - * @brief Enum class representing the type of synchronization. - */ -enum class SyncType { - HOST_TO_DEVICE, ///< Synchronize from host to device - DEVICE_TO_HOST, ///< Synchronize from device to host -}; - -/** - * @brief Class representing a buffer. - * - * This class provides an interface for managing a buffer in a device. - * It supports memory mapped QDMA connections. - * - * @tparam T The type of the elements in the buffer. - */ -template -class Buffer { - public: - /** - * @brief Constructor for Buffer. - * @param device VRT Device of the buffer. - * @param size The size of the buffer. - * @param type The type of memory range. - */ - Buffer(Device device, size_t size, MemoryRangeType type); - - /** - * @brief Constructor for Buffer. - * @param device VRT Device of the buffer. - * @param size The size of the buffer. - * @param type The type of memory range. - * @param port The HBM port number. This would not have any effect if the type is DDR. - */ - Buffer(Device device, size_t size, MemoryRangeType type, uint8_t port); - - /** - * @brief Destructor for Buffer. - */ - ~Buffer(); - - /** - * @brief Gets a pointer to the buffer. - * @return A pointer to the buffer. - */ - T* get() const; - - /** - * @brief Overloads the subscript operator to access buffer elements. - * @param index The index of the element to access. - * @return A reference to the element at the specified index. - */ - T& operator[](size_t index); - - /** - * @brief Overloads the subscript operator to access buffer elements (const version). - * @param index The index of the element to access. - * @return A const reference to the element at the specified index. - */ - const T& operator[](size_t index) const; - - /** - * @brief Gets the physical address of the buffer. - * @return The physical address of the buffer. - */ - uint64_t getPhysAddr() const; - - /** - * @brief Gets the lower 32 bits of the physical address of the buffer. - * @return The lower 32 bits of the physical address of the buffer. - */ - uint32_t getPhysAddrLow() const; - - /** - * @brief Gets the upper 32 bits of the physical address of the buffer. - * @return The upper 32 bits of the physical address of the buffer. - */ - uint32_t getPhysAddrHigh() const; - - /** - * @brief Synchronizes the buffer. - * @param syncType The type of synchronization. - */ - void sync(SyncType syncType); - - std::string getName(); - - Buffer(const Buffer&) = delete; - Buffer& operator=(const Buffer&) = delete; - Buffer(Buffer&& other) noexcept; - Buffer& operator=(Buffer&& other) noexcept; - - private: - uint64_t startAddress; ///< The starting address of the buffer - T* localBuffer; ///< Pointer to the local buffer - size_t size; ///< The size of the buffer - MemoryRangeType type; ///< The type of memory range - Device device; ///< The device associated with the buffer - std::size_t index; // Member variable to store the index of the buffer - static std::size_t bufferIndex; // Static variable to track the buffer index -}; - -template -size_t Buffer::bufferIndex = 0; - -template -Buffer::Buffer(Device device, size_t size, MemoryRangeType type) - : device(device), size(size), type(type), index(bufferIndex++) { - startAddress = device.getAllocator()->allocate(size * sizeof(T), type); - if (startAddress == 0) { - throw std::bad_alloc(); - } - - localBuffer = new T[size]; - Platform platform = device.getPlatform(); - if (platform == Platform::EMULATION) { - // send initial buffer so it is populated in the emulation environment - std::shared_ptr server = device.getZmqServer(); - std::vector sendData; - std::size_t dataSize = size * sizeof(T); - sendData.resize(dataSize); - std::memcpy(sendData.data(), localBuffer, dataSize); - server->sendBuffer(std::to_string(getPhysAddr()), sendData); - } -} - -template -Buffer::Buffer(Device device, size_t size, MemoryRangeType type, uint8_t port) - : device(device), size(size), type(type), index(bufferIndex++) { - this->device = device; - - startAddress = device.getAllocator()->allocate(size * sizeof(T), type, port); - if (startAddress == 0) { - throw std::bad_alloc(); - } - - localBuffer = new T[size]; -} - -template -Buffer::~Buffer() { - if (startAddress != 0) { - device.getAllocator()->deallocate(startAddress); - } - if (localBuffer != nullptr) { - delete[] localBuffer; - } -} - -template -T* Buffer::get() const { - return localBuffer; -} - -template -T& Buffer::operator[](size_t index) { - if (index >= size) { - throw std::out_of_range("Index out of range"); - } - return localBuffer[index]; -} - -template -const T& Buffer::operator[](size_t index) const { - if (index >= size) { - throw std::out_of_range("Index out of range"); - } - return localBuffer[index]; -} - -template -uint64_t Buffer::getPhysAddr() const { - return startAddress; -} - -template -uint32_t Buffer::getPhysAddrLow() const { - return startAddress & 0xFFFFFFFF; -} - -template -uint32_t Buffer::getPhysAddrHigh() const { - return (startAddress >> 32) & 0xFFFFFFFF; -} - -template -std::string Buffer::getName() { - return "buffer_" + std::to_string(index); -} - -template -void Buffer::sync(SyncType syncType) { - Platform platform = device.getPlatform(); - if (platform == Platform::HARDWARE) { - size_t maxChunkSize = 1 << 24; // 22 - size_t totalSize = size * sizeof(T); - size_t chunkSize = maxChunkSize * sizeof(T); - size_t offset = 0; - - while (totalSize > 0) { - size_t currentChunkSize = std::min(chunkSize, totalSize); - if (syncType == SyncType::HOST_TO_DEVICE) { - this->device.qdmaIntf.write_buff(reinterpret_cast(localBuffer) + offset, - startAddress + offset, currentChunkSize); - } else if (syncType == SyncType::DEVICE_TO_HOST) { - this->device.qdmaIntf.read_buff(reinterpret_cast(localBuffer) + offset, - startAddress + offset, currentChunkSize); - } else { - throw std::invalid_argument("Invalid sync type"); - } - offset += currentChunkSize; - totalSize -= currentChunkSize; - } - } else if (platform == Platform::EMULATION) { - std::shared_ptr server = device.getZmqServer(); - if (syncType == SyncType::HOST_TO_DEVICE) { - std::vector sendData; - std::size_t dataSize = size * sizeof(T); - sendData.resize(dataSize); - std::memcpy(sendData.data(), localBuffer, dataSize); - server->sendBuffer(std::to_string(getPhysAddr()), sendData); - } else if (syncType == SyncType::DEVICE_TO_HOST) { - std::vector recvData = server->fetchBuffer(std::to_string(getPhysAddr())); - size = recvData.size() / sizeof(T); - localBuffer = reinterpret_cast(realloc(localBuffer, recvData.size())); - std::memcpy(localBuffer, recvData.data(), recvData.size()); - - } else { - throw std::invalid_argument("Invalid sync type"); - } - - } else if (platform == Platform::SIMULATION) { - std::shared_ptr server = device.getZmqServer(); - if (syncType == SyncType::HOST_TO_DEVICE) { - std::vector sendData; - std::size_t dataSize = size * sizeof(T); - sendData.resize(dataSize); - std::memcpy(sendData.data(), localBuffer, dataSize); - server->sendBufferSim(getPhysAddr(), sendData); - } else if (syncType == SyncType::DEVICE_TO_HOST) { - std::vector recvData; - server->fetchBufferSim(getPhysAddr(), size * sizeof(T), recvData); - - size = recvData.size() * sizeof(T); - localBuffer = reinterpret_cast(realloc(localBuffer, recvData.size())); - std::memcpy(localBuffer, recvData.data(), recvData.size()); - } else { - throw std::invalid_argument("Invalid sync type"); - } - } -} -template -Buffer::Buffer(Buffer&& other) noexcept - : device(other.device), - size(other.size), - type(other.type), - index(other.index), - startAddress(other.startAddress), - localBuffer(other.localBuffer) { - other.startAddress = 0; - other.localBuffer = nullptr; - other.size = 0; -} - -template -Buffer& Buffer::operator=(Buffer&& other) noexcept { - if (this != &other) { - if (localBuffer) { - delete[] localBuffer; - } - - if (startAddress != 0) { - device.getAllocator()->deallocate(startAddress); - } - - device = other.device; - size = other.size; - type = other.type; - index = other.index; - startAddress = other.startAddress; - localBuffer = other.localBuffer; - - other.startAddress = 0; - other.localBuffer = nullptr; - other.size = 0; - } - return *this; -} - -} // namespace vrt - -#endif // BUFFER_HPP \ No newline at end of file diff --git a/vrt/include/api/device.hpp b/vrt/include/api/device.hpp deleted file mode 100644 index ab829117..00000000 --- a/vrt/include/api/device.hpp +++ /dev/null @@ -1,257 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef DEVICE_HPP -#define DEVICE_HPP - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "allocator/allocator.hpp" -#include "api/kernel.hpp" -#include "api/vrt_version.hpp" -#include "api/vrtbin.hpp" -#include "driver/clk_wiz.hpp" -#include "driver/qdma_logic.hpp" -#include "parser/xml_parser.hpp" -#include "qdma/pcie_driver_handler.hpp" -#include "qdma/qdma_connection.hpp" -#include "qdma/qdma_intf.hpp" -#include "utils/logger.hpp" -#include "utils/platform.hpp" -#include "utils/zmq_server.hpp" - -namespace vrt { - -/** - * @brief Enumeration for device programming types. - * - * This enum represents the different methods that can be used to program a device. - */ -enum class ProgramType { - FLASH, ///< Program the device using flash memory - JTAG ///< Program the device using JTAG interface -}; - -/** - * @brief Path to the JTAG programming script. - * - * This macro defines the path to the shell script used for programming devices via JTAG. - */ -#define JTAG_PROGRAM_PATH "/usr/local/vrt/jtag_program.sh " - -/** - * @brief Path to the QDMA queue setup script. - * - * This macro defines the path to the shell script used for setting up QDMA queues. - */ -#define QDMA_SETUP_QUEUES "/usr/local/vrt/setup_queues.sh " - -/** - * @brief Delay in microseconds for partial boot process. - * - * This constant defines the delay time in microseconds that the system - * will wait during the partial boot process (4 seconds). - */ -#define DELAY_PARTIAL_BOOT (4 * 1000 * 1000) -/** - * @brief Class representing a device. - */ -class Device { - static constexpr uint64_t CLK_WIZ_BASE = 0x20100010000; ///< Base address for the clock wizard - static constexpr uint32_t CLK_WIZ_OFFSET = 0x10000; - static constexpr uint64_t QDMA_LOGIC_BASE = 0x20100020000; ///< Base address for QDMA logic - static constexpr uint32_t QDMA_LOGIC_OFFSET = 0x1000; /// Offset for QDMA logic - ami_device* dev = nullptr; ///< Pointer to the AMI device - uint8_t bar = 0; ///< Base Address Register (BAR) - uint64_t offset = 0; ///< Offset for memory operations - uint16_t pci_bdf = 0; ///< PCI Bus:Device.Function identifier - std::string systemMap; ///< Path to the system map file - std::string bdf; ///< Bus:Device.Function identifier - std::string pdiPath; ///< Path to the PDI file - Vrtbin vrtbin; ///< Vrtbin object for handling VRTBIN operations - ClkWiz clkWiz; ///< Clock Wizard object for handling clock wizard operations - uint64_t clockFreq; ///< Clock frequency - ProgramType programType; ///< Type of programming - std::map kernels; ///< Map of kernel names to Kernel objects - PcieDriverHandler pcieHandler; ///< PCIe driver handler object - Allocator* allocator; ///< Allocator object - VrtbinType vrtbinType; ///< Type of VRTBIN - Platform platform; ///< Platform information - std::shared_ptr zmqServer; ///< ZeroMQ server object - std::vector qdmaConnections; ///< Vector of QDMA connections - std::vector qdmaIntfs; ///< Vector of QDMA interfaces for streaming - public: - QdmaIntf qdmaIntf; ///< QDMA interface object - - /** - * @brief Constructor for Device. - * @param bdf The Bus:Device.Function identifier. - * @param vrtbinPath The path to the VRTBIN file. - * @param program Flag indicating whether to program the device. - */ - Device(const std::string& bdf, const std::string& vrtbinPath, bool program = true, - ProgramType programType = ProgramType::FLASH); - - Device() = default; - /** - * @brief Gets a kernel by name. - * @param name The name of the kernel. - * @return The Kernel object. - */ - vrt::Kernel getKernel(const std::string& name); - - /** - * @brief Gets the Bus:Device.Function identifier. - * @return The Bus:Device.Function identifier. - */ - std::string getBdf(); - - /** - * @brief Programs the device. - */ - void programDevice(); - - /** - * @brief Sends a command to the PCIe driver. - * @param cmd The command to send. - */ - void sendPcieDriverCmd(std::string cmd); - - /** - * @brief Boots the device. - */ - void bootDevice(); - - /** - * @brief Gets a new handle for the device. - */ - void getNewHandle(); - - /** - * @brief Creates the AMI device. - */ - void createAmiDev(); - - /** - * @brief Destroys the AMI device. - */ - void destroyAmiDev(); - - /** - * @brief Destructor for Device. - */ - ~Device(); - - /** - * @brief Parses the system map file. - */ - void parseSystemMap(); - - /** - * @brief Cleans up the device. - */ - void cleanup(); - /** - * @brief Sets clk_wiz frequency. - */ - void setFrequency(uint64_t freq); - - /** - * @brief Gets the clock frequency. - */ - uint64_t getFrequency(); - - /** - * @brief Gets the maximum frequency. - */ - uint64_t getMaxFrequency(); - - /** - * @brief Gets ami device. - */ - ami_device* getAmiDev(); - - /** - * @brief Finds the VRTBIN type from system map. - */ - void findVrtbinType(); - - /** - * @brief Finds the platform from system map. - */ - void findPlatform(); - - /** - * @brief Gets the platform. - */ - Platform getPlatform(); - - /** - * @brief Gets the ZMQ server. - */ - std::shared_ptr getZmqServer(); - - /** - * @brief Gets the Allocator instance. - */ - Allocator* getAllocator(); - - /** - * @brief Gets the QDMA connections. - */ - std::vector getQdmaConnections(); - - // /** - // * @brief Gets the QDMA logic instance. - // */ - // QdmaLogic* getQdmaLogic(); - - /** - * @brief Gets the QDMA streaming interfaces. - */ - std::vector getQdmaInterfaces(); - - /** - * @brief Locks pcie device, for exclusive access. - */ - void lockPcieDevice(const std::string& bdf); - - /** - * @brief Unlocks pcie device, for exclusive access. - */ - void unlockPcieDevice(const std::string& bdf); -}; - -} // namespace vrt - -#endif // DEVICE_HPP \ No newline at end of file diff --git a/vrt/include/api/kernel.hpp b/vrt/include/api/kernel.hpp deleted file mode 100644 index 2e7772d0..00000000 --- a/vrt/include/api/kernel.hpp +++ /dev/null @@ -1,320 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef KERNEL_HPP -#define KERNEL_HPP - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "register/register.hpp" -#include "utils/logger.hpp" -#include "utils/platform.hpp" -#include "utils/zmq_server.hpp" - -namespace vrt { -class Device; -template -class Buffer; - -/** - * @brief Class representing a kernel. - */ -class Kernel { - static constexpr uint64_t BASE_BAR_ADDR = 0x20100000000; ///< Base BAR address - uint8_t bar = 0; ///< Base Address Register (BAR) - ami_device* dev = nullptr; ///< Pointer to the AMI device - std::string name; ///< Name of the kernel - uint64_t baseAddr; ///< Base address of the kernel - uint64_t range; ///< Address range of the kernel - std::vector registers; ///< List of registers in the kernel - size_t currentRegisterIndex = 4; ///< Index of the current register being processed - std::string deviceBdf; ///< BDF of the device - Platform platform; ///< Platform of the device - std::shared_ptr server; ///< Pointer to ZeroMQ server for communication - std::map registerMap; ///< Map of register offsets to values - public: - /** - * @brief Constructor for Kernel. - * @param device Pointer to the AMI device. - * @param name The name of the kernel. - * @param baseAddr The base address of the kernel. - * @param range The address range of the kernel. - * @param registers The list of registers in the kernel. - */ - Kernel(ami_device* device, const std::string& name, uint64_t baseAddr, uint64_t range, - const std::vector& registers); - - /** - * @brief Default constructor for Kernel. - */ - Kernel() = default; - - /** - * @brief Constructor for Kernel using a Device object. - * @param device The Device object. - * @param kernelName The name of the kernel. - */ - Kernel(vrt::Device& device, const std::string& kernelName); - - /** - * @brief Sets the device for the kernel. - * @param device Pointer to the AMI device. - */ - void setDevice(ami_device* device); - - /** - * @brief Writes a value to a register. - * @param offset The offset of the register. - * @param value The value to write. - */ - void write(uint32_t offset, uint32_t value); - - /** - * @brief Reads a value from a register. - * @param offset The offset of the register. - * @return The value read from the register. - */ - uint32_t read(uint32_t offset); - - /** - * @brief Waits for the kernel to complete. - */ - void wait(); - - /** - * @brief Starts the kernel. - * @param autorestart Flag indicating whether to enable autorestart. - */ - void startKernel(bool autorestart = false); - - /** - * @brief Sets the platform for the kernel. - * @param platform The platform to set. - */ - void setPlatform(Platform platform); - - /** - * @brief Writes batch register to PCIe BAR. - */ - void writeBatch(); - - /** - * @brief Calls the kernel and waits for it to complete. - * @param args The arguments to pass to the kernel. - */ - template - void call(Args... args) { - currentRegisterIndex = 4; - if (platform == Platform::HARDWARE) { - (processArg(args), ...); - this->writeBatch(); - this->startKernel(); - this->wait(); - } else if (platform == Platform::EMULATION) { - Json::Value command; - command["command"] = "call"; - command["function"] = name; - int argIdx = 0; - (processEmuArg(args, command, argIdx), ...); - server->sendCommand(command); - } else if (platform == Platform::SIMULATION) { - (processSimArg(args), ...); - this->startKernel(); - this->wait(); - } - } - - /** - * @brief Starts the kernel. - * @param args The arguments to pass to the kernel. - */ - template - void start(Args... args) { - currentRegisterIndex = 4; - if (platform == Platform::HARDWARE) { - (processArg(args), ...); - this->writeBatch(); - this->startKernel(); - - } else if (platform == Platform::EMULATION) { - Json::Value command; - command["command"] = "call"; - command["function"] = name; - int argIdx = 0; - (processEmuArg(args, command, argIdx), ...); - server->sendCommand(command); - } else if (platform == Platform::SIMULATION) { - (processSimArg(args), ...); - this->startKernel(); - } - } - /** - * @brief Helper method which processes an argument. - * @tparam T The type of the argument. - * @param arg The argument to process. - */ - template - void processArg(T arg) { - if (currentRegisterIndex < registers.size()) { - std::regex re(".*_\\d+$"); // Regular expression to match strings ending with _nr - if (std::regex_match(registers.at(currentRegisterIndex).getRegisterName(), re)) { - this->registerMap[registers.at(currentRegisterIndex).getOffset()] = - arg & 0xFFFFFFFF; - this->registerMap[registers.at(currentRegisterIndex + 1).getOffset()] = - static_cast((static_cast(arg) >> 32) & 0xFFFFFFFF); - currentRegisterIndex += 2; - } else { - this->registerMap[registers.at(currentRegisterIndex).getOffset()] = arg; - currentRegisterIndex++; - } - - } else { - throw std::runtime_error("Not enough registers to process all arguments."); - } - } - - /** - * @brief Helper method which processes an argument for simulation. - * @tparam T The type of the argument. - * @param arg The argument to process. - */ - template - void processSimArg(T arg) { - if (currentRegisterIndex < registers.size()) { - std::regex re(".*_\\d+$"); // Regular expression to match strings ending with _nr - if (std::regex_match(registers.at(currentRegisterIndex).getRegisterName(), re)) { - this->write(registers.at(currentRegisterIndex).getOffset(), arg & 0xFFFFFFFF); - this->write(registers.at(currentRegisterIndex + 1).getOffset(), - static_cast((static_cast(arg) >> 32) & 0xFFFFFFFF)); - currentRegisterIndex += 2; - } else { - this->write(registers.at(currentRegisterIndex).getOffset(), arg); - currentRegisterIndex++; - } - } - } - - /** - * @brief Helper method which processes an argument for emulation. - * @tparam T The type of the argument. - * @param arg The argument to process. - * @param command The JSON command to update. - * @param argIndex The index of the argument. - */ - template - void processEmuArg(T arg, Json::Value& command, int& argIndex) { - if (currentRegisterIndex < registers.size()) { - std::regex re(".*_\\d+$"); // Regular expression to match strings ending with _nr - if (std::regex_match(registers.at(currentRegisterIndex).getRegisterName(), re)) { - command["args"]["arg" + std::to_string(argIndex)]["type"] = "buffer"; - command["args"]["arg" + std::to_string(argIndex)]["name"] = std::to_string(arg); - currentRegisterIndex += 2; - } else { - command["args"]["arg" + std::to_string(argIndex)]["type"] = "scalar"; - command["args"]["arg" + std::to_string(argIndex)]["value"] = arg; - currentRegisterIndex++; - } - argIndex++; - } else { - throw std::runtime_error("Not enough registers to process all arguments."); - } - } - - /** - * @brief Getter for the kernel name. - * @return The name of the kernel. - */ - std::string getName() const; - - /** - * @brief Destructor for Kernel. - */ - ~Kernel(); - - /** - * @brief Copy constructor. - * - * @param other The kernel to copy from. - */ - Kernel(const Kernel& other) = default; - - /** - * @brief Move constructor. - * - * @param other The kernel to move from. - */ - Kernel(Kernel&& other) noexcept - : bar(other.bar), - dev(other.dev), - name(std::move(other.name)), - baseAddr(other.baseAddr), - range(other.range), - registers(std::move(other.registers)), - currentRegisterIndex(other.currentRegisterIndex), - deviceBdf(std::move(other.deviceBdf)), - platform(other.platform), - server(std::move(other.server)), - registerMap(std::move(other.registerMap)) {} - - /** - * @brief Copy assignment operator. - * - * @param other The kernel to copy from. - * @return Reference to this kernel. - */ - Kernel& operator=(const Kernel& other) = default; - - /** - * @brief Move assignment operator. - * - * @param other The kernel to move from. - * @return Reference to this kernel. - */ - Kernel& operator=(Kernel&& other) noexcept { - if (this != &other) { - bar = other.bar; - dev = other.dev; - name = std::move(other.name); - baseAddr = other.baseAddr; - range = other.range; - registers = std::move(other.registers); - currentRegisterIndex = other.currentRegisterIndex; - deviceBdf = std::move(other.deviceBdf); - platform = other.platform; - server = std::move(other.server); - registerMap = std::move(other.registerMap); - } - return *this; - } -}; - -} // namespace vrt - -#endif // KERNEL_HPP \ No newline at end of file diff --git a/vrt/include/driver/clk_wiz.hpp b/vrt/include/driver/clk_wiz.hpp deleted file mode 100644 index c8078806..00000000 --- a/vrt/include/driver/clk_wiz.hpp +++ /dev/null @@ -1,360 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef CLK_WIZ_HPP -#define CLK_WIZ_HPP - -#include - -#include -#include - -#include "api/kernel.hpp" -#include "utils/logger.hpp" - -namespace vrt { -#define XCLK_WIZ_HANDLER_CLK_OUTOF_RANGE 1 -#define XCLK_WIZ_HANDLER_CLK_GLITCH 2 -#define XCLK_WIZ_HANDLER_CLK_STOP 3 -#define XCLK_WIZ_HANDLER_CLK_OTHER_ERROR 4 - -#define XCLK_M_MIN 4 -#define XCLK_M_MAX 432 -#define XCLK_D_MIN 1 -#define XCLK_D_MAX 123 -#define XCLK_VCO_MIN 2160 -#define XCLK_VCO_MAX 4320 -#define XCLK_O_MIN 2 -#define XCLK_O_MAX 511 - -#define XCLK_US_VCO_MAX 1600 -#define XCLK_US_VCO_MIN 800 -#define XCLK_US_M_MIN 2 -#define XCLK_US_M_MAX 128 -#define XCLK_US_D_MAX 106 -#define XCLK_US_D_MIN 1 -#define XCLK_US_O_MAX 128 -#define XCLK_US_O_MIN 1 - -#define XCLK_MHZ 1000000 -typedef struct { -#ifndef SDT - uint32_t DeviceId; /**< Device Id */ -#else - char *Name; -#endif - uint64_t BaseAddr; /**< Base address of CLK_WIZ Controller */ - uint32_t EnableClkMon; /**< It enables the Clock Monitor*/ - uint32_t EnableUserClkWiz0; /**< Enable user clk 0 */ - uint32_t EnableUserClkWiz1; /**< Enable user clk 1 */ - uint32_t EnableUserClkWiz2; /**< Enable user clk 2 */ - uint32_t EnableUserClkWiz3; /**< Enable user clk 3 */ - double RefClkFreq; /**< Frequency of Reference Clock */ - double UserClkFreq0; /**< Hold the user clock frequency0 */ - double UserClkFreq1; /**< Hold the user clock frequency1 */ - double UserClkFreq2; /**< Hold the user clock frequency2 */ - double UserClkFreq3; /**< Hold the user clock frequency3 */ - double Precision; /**< Holds the value of precision */ - uint8_t EnablePll0; /**< specify if this user clock is - going as input to the PLL/MMCM */ - uint8_t EnablePll1; /**< specify if this user clock is - going as input to the PLL/MMCM */ - - uint64_t PrimInClkFreq; /**< Input Clock */ - uint32_t NumClocks; /**< Number of clocks */ -#ifdef SDT - u32 IntId; /**< Interrupt ID on GIC **/ - UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] - * Parent base address */ -#endif -} XClk_Wiz_Config; - -typedef void (*XClk_Wiz_CallBack)(void *CallBackRef, uint32_t Mask); - -typedef struct { - XClk_Wiz_Config Config; /**< GUI Configuration */ - uint32_t ClkWizIntrStatus; /**< Clock Stop, Clock Overrun, - * Clock Underrun, Clock Glitch - * Interrupt Status */ - uint32_t ClkIntrEnable; /**< Interrupt enable for - * Clock Stop, Clock Overrun, - * Clock Underrun, Clock Glitch */ - XClk_Wiz_CallBack ClkOutOfRangeCallBack; /**< Callback for Clock out - * of range Under flow - * .or over flow */ - void *ClkOutOfRangeRef; /**< To be passed to the clock - * out of range call back */ - XClk_Wiz_CallBack ClkGlitchCallBack; /**< Callback for - * Clock Glitch */ - void *ClkGlitchRef; /**< To be passed to the - * clock glitch call back */ - XClk_Wiz_CallBack ClkStopCallBack; /**< Callback for Clock stop */ - void *ClkStopRef; /**< To be passed to the clock - * stop call back */ - XClk_Wiz_CallBack ErrorCallBack; /**< Call back function - * for rest all errors */ - void *ErrRef; /**< To be passed to the Error Call back */ - uint32_t IsReady; /**< Driver is ready */ - uint32_t MVal; /* Multiplier valuer */ - uint32_t DVal; /* Divisor value */ - uint32_t OVal; /* Output Value */ - uint64_t MinErr; /* Min Error that is acceptable */ -} XClk_Wiz; - -#define XCLK_WIZ_STATUS_OFFSET 0x00000004 /**< Status Register */ -#define XCLK_WIZ_ISR_OFFSET 0x0000000C /**< Interrupt Status Register */ -#define XCLK_WIZ_IER_OFFSET 0x00000010 /**< Interrupt Enable Register */ -#define XCLK_WIZ_RECONFIG_OFFSET 0x00000014 /**< Reconfig Register */ -#define XCLK_WIZ_REG1_OFFSET 0x00000330 -#define XCLK_WIZ_REG2_OFFSET 0x00000334 -#define XCLK_WIZ_REG3_OFFSET 0x00000338 -#define XCLK_WIZ_REG4_OFFSET 0x0000033C -#define XCLK_WIZ_REG12_OFFSET 0x00000380 -#define XCLK_WIZ_REG13_OFFSET 0x00000384 -#define XCLK_WIZ_REG11_OFFSET 0x00000378 -#define XCLK_WIZ_REG14_OFFSET 0x00000398 -#define XCLK_WIZ_REG15_OFFSET 0x0000039C -#define XCLK_WIZ_REG16_OFFSET 0x000003A0 -#define XCLK_WIZ_REG17_OFFSET 0x000003A8 -#define XCLK_WIZ_REG19_OFFSET 0x000003CC -#define XCLK_WIZ_REG25_OFFSET 0x000003F0 -#define XCLK_WIZ_REG26_OFFSET 0x000003FC - -#define XCLK_WIZ_ZYNQMP_REG0_OFFSET 0x00000200 -#define XCLK_WIZ_ZYNQMP_REG2_OFFSET 0x00000208 - -#define XCLK_WIZ_REG0_FBMULT_SHIFT 8 -#define XCLK_WIZ_REG0_FBMULT_WIDTH 8 -#define XCLK_WIZ_REG0_FBMULT_MASK 0xFF00 -#define XCLK_WIZ_REG0_DIV_MASK 0xFF -#define XCLK_WIZ_REG0_DIV_WIDTH 8 -#define XCLK_WIZ_REG2_DIV_MASK 0xFF - -#define XCLK_WIZ_REG1_EDGE_SHIFT 8 -#define XCLK_WIZ_REG1_EDGE_MASK 0x100 -#define XCLK_WIZ_CLKFBOUT_L_MASK 0xFF -#define XCLK_WIZ_CLKFBOUT_H_MASK 0xFF00 -#define XCLK_WIZ_CLKFBOUT_H_SHIFT 8 - -#define XCLK_WIZ_EDGE_MASK (1 << 10) /** Edge */ -#define XCLK_WIZ_P5EN_MASK (1 << 8) /** p5en */ -#define XCLK_WIZ_LOCK 1 /** Lock */ -#define XCLK_WIZ_REG3_PREDIV2 (1 << 11) /**< Prediv2 3*/ -#define XCLK_WIZ_REG3_USED (1 << 12) /**< Prediv2 3*/ -#define XCLK_WIZ_REG3_MX (1 << 9) /**< MX*/ -#define XCLK_WIZ_REG1_PREDIV2 (1 << 12) /**< Prediv2 3*/ -#define XCLK_WIZ_REG1_EN (1 << 9) /**< FBout enable*/ -#define XCLK_WIZ_REG1_MX (1 << 10) /**< MX 3*/ -#define XCLK_WIZ_RECONFIG_LOAD 1 -#define XCLK_WIZ_RECONFIG_SADDR 2 - -#define XCLK_WIZ_CLKOUT0_PREDIV2_SHIFT 11 /**< Shift bits for Prediv2 */ -#define XCLK_WIZ_CLKOUT0_MX_SHIFT 9 /**< Shift bits for MUX */ -#define XCLK_WIZ_CLKOUT0_P5EN_SHIFT 13 /**< Shift bits for P5EN */ -#define XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT 15 /**< Shift bits for P5EDGE */ -#define XCLK_WIZ_CLKOUT0_P5FEDGE_MASK (1 << 15) /**< Mask for P5EDGE */ -#define XCLK_WIZ_REG12_EDGE_SHIFT 10 /**< Shift bits for Edge */ -#define XCLK_WIZ_REG1_EDGE_SHIFT 8 /**< Shift bits for Edge */ - /*@}*/ -/*@}*/ - -/** @name Bitmasks and offsets of XCLK_WIZ_ISR_OFFSET register - * This register is used to display interrupt status register - * @{ - */ - -#define XCLK_WIZ_ISR_CLK3_STOP_MASK 0x00008000 /**< User clock 3 stopped */ -#define XCLK_WIZ_ISR_CLK2_STOP_MASK 0x00004000 /**< User clock 2 stopped */ -#define XCLK_WIZ_ISR_CLK1_STOP_MASK 0x00002000 /**< User clock 1 stopped */ -#define XCLK_WIZ_ISR_CLK0_STOP_MASK 0x00001000 /**< User clock 0 stopped */ -#define XCLK_WIZ_ISR_CLK3_GLITCH_MASK 0x00000800 /**< User clock 3 has glitch */ -#define XCLK_WIZ_ISR_CLK2_GLITCH_MASK 0x00000400 /**< User clock 2 has glitch */ -#define XCLK_WIZ_ISR_CLK1_GLITCH_MASK 0x00000200 /**< User clock 1 has glitch */ -#define XCLK_WIZ_ISR_CLK0_GLITCH_MASK 0x00000100 /**< User clock 0 has glitch */ -#define XCLK_WIZ_ISR_CLK3_MINFREQ_MASK 0x00000080 /**< User clock 3 is less than specification */ -#define XCLK_WIZ_ISR_CLK2_MINFREQ_MASK 0x00000040 /**< User clock 2 is less than specification */ -#define XCLK_WIZ_ISR_CLK1_MINFREQ_MASK 0x00000020 /**< User clock 1 is less than specification */ -#define XCLK_WIZ_ISR_CLK0_MINFREQ_MASK 0x00000010 /**< User clock 0 is less than specification */ -#define XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK 0x00000008 /**< User clock 3 is max than specification */ -#define XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK 0x00000004 /**< User clock 2 is max than specification */ -#define XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK 0x00000002 /**< User clock 1 is max than specification */ -#define XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK 0x00000001 /**< User clock 0 is max than specification */ - -#define XCLK_WIZ_ISR_CLKALL_STOP_MASK 0x0000F000 /**< User clock[0-3] has stopped*/ -#define XCLK_WIZ_ISR_CLKALL_GLITCH_MASK 0x00000F00 /**< User clock[0-3] has glitch */ -#define XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK \ - 0x000000F0 /**< User clock[0-3] is min than specification */ -#define XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK \ - 0x0000000F /**< User clock[0-3] is max than specification */ - -#define XCLK_WIZ_ISR_CLK3_STOP_SHIFT 15 /**< Shift bits for User clock 3 stop*/ -#define XCLK_WIZ_ISR_CLK2_STOP_SHIFT 14 /**< Shift bits for User clock 2 stop*/ -#define XCLK_WIZ_ISR_CLK1_STOP_SHIFT 13 /**< Shift bits for User clock 1 stop*/ -#define XCLK_WIZ_ISR_CLK0_STOP_SHIFT 12 /**< Shift bits for User clock 0 stop*/ -#define XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT 11 /**< Shift bits for User clock 3 glitch */ -#define XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT 10 /**< Shift bits for User clock 2 glitch */ -#define XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT 9 /**< Shift bits for User clock 1 glitch */ -#define XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT 8 /**< Shift bits for User clock 0 glitch */ -#define XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT 7 /**< Shift bits for User clock 3 less */ -#define XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT 6 /**< Shift bits for User clock 2 less */ -#define XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT 5 /**< Shift bits for User clock 1 less */ -#define XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT 4 /**< Shift bits for User clock 0 less */ -#define XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT 3 /**< Shift bits for User clock 3 max */ -#define XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT 2 /**< Shift bits for User clock 2 max */ -#define XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT 1 /**< Shift bits for User clock 1 max */ -#define XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT 0 /**< Shift bits for User clock 0 max */ -/*@}*/ - -/** @name Bitmasks and offsets of XCLK_WIZ_IER_OFFSET register - * This register is used to display interrupt status register - * @{ - */ - -#define XCLK_WIZ_IER_CLK3_STOP_MASK 0x00008000 /**< User clock 3 stopped */ -#define XCLK_WIZ_IER_CLK2_STOP_MASK 0x00004000 /**< User clock 2 stopped */ -#define XCLK_WIZ_IER_CLK1_STOP_MASK 0x00002000 /**< User clock 1 stopped */ -#define XCLK_WIZ_IER_CLK0_STOP_MASK 0x00001000 /**< User clock 0 stopped */ -#define XCLK_WIZ_IER_CLK3_GLITCH_MASK 0x00000800 /**< User clock 3 has glitch */ -#define XCLK_WIZ_IER_CLK2_GLITCH_MASK 0x00000400 /**< User clock 2 has glitch */ -#define XCLK_WIZ_IER_CLK1_GLITCH_MASK 0x00000200 /**< User clock 1 has glitch */ -#define XCLK_WIZ_IER_CLK0_GLITCH_MASK 0x00000100 /**< User clock 0 has glitch */ -#define XCLK_WIZ_IER_CLK3_MINFREQ_MASK 0x00000080 /**< User clock 3 is less than specification */ -#define XCLK_WIZ_IER_CLK2_MINFREQ_MASK 0x00000040 /**< User clock 2 is less than specification */ -#define XCLK_WIZ_IER_CLK1_MINFREQ_MASK 0x00000020 /**< User clock 1 is less than specification */ -#define XCLK_WIZ_IER_CLK0_MINFREQ_MASK 0x00000010 /**< User clock 0 is less than specification */ -#define XCLK_WIZ_IER_CLK3_MAXFREQ_MASK 0x00000008 /**< User clock 3 is max than specification */ -#define XCLK_WIZ_IER_CLK2_MAXFREQ_MASK 0x00000004 /**< User clock 2 is max than specification */ -#define XCLK_WIZ_IER_CLK1_MAXFREQ_MASK 0x00000002 /**< User clock 1 is max than specification */ -#define XCLK_WIZ_IER_CLK0_MAXFREQ_MASK 0x00000001 /**< User clock 0 is max than specification */ - -#define XCLK_WIZ_IER_CLK3_STOP_SHIFT 15 /**< Shift bits for User clock 3 stop*/ -#define XCLK_WIZ_IER_CLK2_STOP_SHIFT 14 /**< Shift bits for User clock 2 stop*/ -#define XCLK_WIZ_IER_CLK1_STOP_SHIFT 13 /**< Shift bits for User clock 1 stop*/ -#define XCLK_WIZ_IER_CLK0_STOP_SHIFT 12 /**< Shift bits for User clock 0 stop*/ -#define XCLK_WIZ_IER_CLK3_GLITCH_SHIFT 11 /**< Shift bits for User clock 3 glitch */ -#define XCLK_WIZ_IER_CLK2_GLITCH_SHIFT 10 /**< Shift bits for User clock 2 glitch */ -#define XCLK_WIZ_IER_CLK1_GLITCH_SHIFT 9 /**< Shift bits for User clock 1 glitch */ -#define XCLK_WIZ_IER_CLK0_GLITCH_SHIFT 8 /**< Shift bits for User clock 0 glitch */ -#define XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT 7 /**< Shift bits for User clock 3 less */ -#define XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT 6 /**< Shift bits for User clock 2 less */ -#define XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT 5 /**< Shift bits for User clock 1 less */ -#define XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT 4 /**< Shift bits for User clock 0 less */ -#define XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT 3 /**< Shift bits for User clock 3 max */ -#define XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT 2 /**< Shift bits for User clock 2 max */ -#define XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT 1 /**< Shift bits for User clock 1 max */ -#define XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT 0 /**< Shift bits for User clock 0 max */ -/*@}*/ - -#define XCLK_WIZ_IER_ALLINTR_MASK 0x0000FFFF /**< All interrupts enable mask */ -#define XCLK_WIZ_IER_ALLINTR_SHIFT 0 /**< All interrupts enable shift bits */ - -#define XCLK_WIZ_ISR_ALLINTR_MASK 0x0000FFFF /**< All interrupt status register mask */ -#define XCLK_WIZ_ISR_ALLINTR_SHIFT 0 /**< All interrupts status register shift */ -#define XCLK_WIZ_MAX_OUTPUT 7 - -/** - * @class ClkWiz - * @brief A class to manage and configure the clock wizard. - * - * The ClkWiz class provides methods to configure and manage the clock settings - * for a given device. It inherits from the Kernel class and provides additional - * functionality specific to clock management. - */ -class ClkWiz : public Kernel { - private: - XClk_Wiz *instancePtr; /**< Pointer to the clock wizard instance. */ - uint64_t clockFrequency; /**< The current clock frequency. */ - - /** - * @brief Get the VCO (Voltage-Controlled Oscillator) frequency. - * - * @return The VCO frequency in Hz. - */ - uint64_t getVco(); - - /** - * @brief Set the clock rate internally. - * - * @param rate The desired clock rate in Hz. - */ - void setRateHzInternal(uint64_t rate); - - /** - * @brief Calculate the divisors for the given clock rate. - * - * @param SetRate The desired clock rate in Hz. - */ - void calculateDivisorsHz(uint64_t SetRate); - - /** - * @brief Update the O (Output) divisor. - */ - void updateO(); - - /** - * @brief Update the D (Divider) divisor. - */ - void updateD(); - - /** - * @brief Update the M (Multiplier) divisor. - */ - void updateM(); - - /** - * @brief Wait for the clock to lock. - * - * @return The status of the lock operation. - */ - uint32_t waitForLock(); - - public: - /** - * @brief Constructor for the ClkWiz class. - * - * @param device Pointer to the ami_device. - * @param name The name of the clock wizard instance. - * @param baseAddr The base address of the clock wizard. - * @param range The address range of the clock wizard. - * @param clockFreq The initial clock frequency in Hz. - */ - ClkWiz(ami_device *device, const std::string &name, uint64_t baseAddr, uint64_t range, - uint64_t clockFreq); - - /** - * @brief Set the clock rate. - * - * @param rate The desired clock rate in Hz. - * @param verbose If true, print verbose output. - */ - - void setRateHz(uint64_t rate, bool verbose = true); - - /** - * @brief Get the current clock rate. - * - * @return The current clock rate in Hz. - */ - uint64_t getClockRate(); -}; - -} // namespace vrt - -#endif // CLK_WIZ_HPP \ No newline at end of file diff --git a/vrt/include/vrt/allocator/allocator.hpp b/vrt/include/vrt/allocator/allocator.hpp new file mode 100644 index 00000000..57938712 --- /dev/null +++ b/vrt/include/vrt/allocator/allocator.hpp @@ -0,0 +1,387 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file allocator.hpp + * @brief Memory allocator with buddy-system block management. + */ + +#ifndef VRT_ALLOCATOR_HPP +#define VRT_ALLOCATOR_HPP + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +namespace vrtd { +class Device; +} + +namespace vrt { + +typedef vrtd::BufferAllocType BufferAllocType; +typedef vrtd::BufferAllocDir BufferAllocDir; + +enum class MemoryRangeType { + HBM, + DDR, + HBM_VNOC, +}; + +enum class HBMRegion : uint64_t { + HBM0 = 0, + HBM1 = 1, + HBM2 = 2, + HBM3 = 3, + HBM4 = 4, + HBM5 = 5, + HBM6 = 6, + HBM7 = 7, + HBM8 = 8, + HBM9 = 9, + HBM10 = 10, + HBM11 = 11, + HBM12 = 12, + HBM13 = 13, + HBM14 = 14, + HBM15 = 15, + HBM16 = 16, + HBM17 = 17, + HBM18 = 18, + HBM19 = 19, + HBM20 = 20, + HBM21 = 21, + HBM22 = 22, + HBM23 = 23, + HBM24 = 24, + HBM25 = 25, + HBM26 = 26, + HBM27 = 27, + HBM28 = 28, + HBM29 = 29, + HBM30 = 30, + HBM31 = 31, + HBM32 = 32, + HBM33 = 33, + HBM34 = 34, + HBM35 = 35, + HBM36 = 36, + HBM37 = 37, + HBM38 = 38, + HBM39 = 39, + HBM40 = 40, + HBM41 = 41, + HBM42 = 42, + HBM43 = 43, + HBM44 = 44, + HBM45 = 45, + HBM46 = 46, + HBM47 = 47, + HBM48 = 48, + HBM49 = 49, + HBM50 = 50, + HBM51 = 51, + HBM52 = 52, + HBM53 = 53, + HBM54 = 54, + HBM55 = 55, + HBM56 = 56, + HBM57 = 57, + HBM58 = 58, + HBM59 = 59, + HBM60 = 60, + HBM61 = 61, + HBM62 = 62, + HBM63 = 63, + + NON_HBM = std::numeric_limits::max(), +}; + +/** + * @brief Describes the memory type and optional HBM port for a Buffer. + * + * Obtained from Kernel::portMemoryConfig() or Kernel::argMemoryConfig() and + * passed directly to the Buffer constructor so callers do not need to specify + * type and port separately. + */ +struct MemoryConfig { + MemoryRangeType type; ///< DDR, HBM, or HBM_VNOC + std::optional hbmPort; ///< Set only when type == HBM +}; + +/** + * @brief RAII wrapper around a vrtd::Buffer allocation. + */ +class UntypedBuffer { + vrtd::Buffer* backingBuffer; + + uint64_t size; + uint64_t offset; +public: + UntypedBuffer(std::nullptr_t) noexcept; + UntypedBuffer(vrtd::Buffer* backingBuffer, uint64_t size = std::numeric_limits::max(), uint64_t offset = 0); + UntypedBuffer(const UntypedBuffer& parent, uint64_t size, uint64_t offset); + virtual ~UntypedBuffer(); + + BufferAllocType getAllocType() const noexcept; + BufferAllocDir getAllocDir() const noexcept; + HBMRegion getHBMRegion() const noexcept; + uint64_t getSize() const noexcept; + uint64_t getPhysAddr() const noexcept; + void* data() const noexcept; + + void syncToDevice(uint64_t offset = 0, uint64_t size = std::numeric_limits::max()); + void syncToHost(uint64_t offset = 0, uint64_t size = std::numeric_limits::max()); + + bool operator==(std::nullptr_t) const noexcept; + bool operator!=(std::nullptr_t) const noexcept; + friend bool operator==(std::nullptr_t, const UntypedBuffer& buffer) noexcept; + friend bool operator!=(std::nullptr_t, const UntypedBuffer& buffer) noexcept; +}; + +/** + * @brief Abstract base for allocated memory blocks. + */ +class Block { +public: + Block(); + virtual ~Block(); + + virtual UntypedBuffer *getUntypedBuffer() const noexcept = 0; +}; + +/** + * @brief Direct allocation for buffers larger than 64 MB. + */ +class LargeBlock : public Block { + std::unique_ptr backingBuffer; + std::unique_ptr untypedBuffer; +public: + LargeBlock(vrtd::Device& device, BufferAllocType type, BufferAllocDir dir, uint64_t size, HBMRegion region = HBMRegion::NON_HBM); + ~LargeBlock() override; + + UntypedBuffer *getUntypedBuffer() const noexcept override; +}; + +/** + * @brief Template base for buddy-system superblock allocators. + * + * Manages power-of-two blocks from 2^MIN_K to 2^MAX_K bytes, splitting + * larger blocks on allocation and coalescing buddies on deallocation. + * + * @tparam MIN_K Log2 of the minimum block size. + * @tparam MAX_K Log2 of the maximum block size (superblock size). + */ +template +class BuddySuperblockBase { +protected: + static_assert(MIN_K <= MAX_K, "MIN_K must be <= MAX_K"); + static constexpr size_t kMin = MIN_K; + static constexpr size_t kMax = MAX_K; + static constexpr size_t kNumBuckets = MAX_K - MIN_K + 1; + static constexpr size_t kToIndex(size_t k) { return k - MIN_K; } + static size_t sizeToIndex(size_t size, const char* tooSmallError) { + size_t k = 64 - __builtin_clzll((unsigned long long)(size - 1)); + if (k < MIN_K) { + throw std::runtime_error(tooSmallError); + } + return kToIndex(k); + } + + std::array, kNumBuckets> freeList; + + void seed(const UntypedBuffer& whole, const char* tooSmallError, const char* tooLargeError) { + // Seed the free list with the full superblock as a single buddy. + size_t index = sizeToIndex(whole.getSize(), tooSmallError); + if (index >= kNumBuckets) { + throw std::runtime_error(tooLargeError); + } + freeList[index].push_back(whole); + } + + UntypedBuffer allocate(uint64_t size, const char* tooSmallError) { + // Round size to a bucket index (power-of-two) and search for a free buddy. + size_t index = sizeToIndex(size, tooSmallError); + if (index >= kNumBuckets) { + throw std::bad_alloc(); + } + + for (size_t i = index; i < kNumBuckets; ++i) { + if (freeList[i].empty()) { + continue; + } + + // Take the smallest available buddy and split until we reach the target size. + UntypedBuffer buffer = freeList[i].back(); + freeList[i].pop_back(); + + while (i > index) { + --i; + uint64_t halfSize = 1ULL << (MIN_K + i); + // Return the upper half to the free list, keep the lower half to keep splitting. + freeList[i].emplace_back(buffer, halfSize, halfSize); + buffer = UntypedBuffer(buffer, halfSize, 0); + } + return buffer; + } + + return nullptr; + } + + void deallocate(const UntypedBuffer& whole, UntypedBuffer buffer, const char* tooSmallError, const char* ownershipError) { + // Compute the buddy bucket for this size class. + size_t index = sizeToIndex(buffer.getSize(), tooSmallError); + if (index >= kNumBuckets) { + throw std::runtime_error("Invalid buffer size for deallocation"); + } + // Validate the slice belongs to this superblock. + const uint64_t base = whole.getPhysAddr(); + const uint64_t totalSize = whole.getSize(); + uint64_t size = buffer.getSize(); + uint64_t offset = buffer.getPhysAddr() - base; + if (offset + size > totalSize) { + throw std::runtime_error(ownershipError); + } + + // Coalesce with free buddy blocks while possible. + size_t i = index; + while (i + 1 < kNumBuckets) { + const uint64_t buddyOffset = offset ^ size; + auto& bucket = freeList[i]; + size_t buddyIndex = bucket.size(); + // Linear search for the buddy in this bucket. + for (size_t j = 0; j < bucket.size(); ++j) { + if (bucket[j].getPhysAddr() - base == buddyOffset) { + buddyIndex = j; + break; + } + } + if (buddyIndex == bucket.size()) { + break; + } + + // Remove buddy from free list (swap-pop). + if (buddyIndex + 1 != bucket.size()) { + bucket[buddyIndex] = bucket.back(); + } + bucket.pop_back(); + // Merge into next size class. + offset = std::min(offset, buddyOffset); + size <<= 1; + ++i; + } + + // Insert the final (possibly coalesced) block into its bucket. + freeList[i].emplace_back(whole, size, offset); + } + + bool isFree(const UntypedBuffer& whole, const char* tooSmallError) const { + // Simplified check: rely on the full-size bucket as the indicator. + size_t index = sizeToIndex(whole.getSize(), tooSmallError); + assert(index < kNumBuckets); + return freeList[index].size() == 1; + } +}; + +/** + * @brief Superblock managing 2 MB -- 64 MB sub-allocations via buddy system. + */ +class LargeBlockSuperblock : public LargeBlock, private BuddySuperblockBase<21, 26> { + using Buddy = BuddySuperblockBase<21, 26>; // 2MB - 64MB +public: + static constexpr size_t MAX_SIZE = 1ULL << Buddy::kMax; // 64MB + + LargeBlockSuperblock(vrtd::Device& device, BufferAllocType type, BufferAllocDir dir, uint64_t size, HBMRegion region = HBMRegion::NON_HBM); + ~LargeBlockSuperblock() override; + + UntypedBuffer allocate(uint64_t size); + void deallocate(UntypedBuffer buffer); + bool isFree() const; +}; + +/** + * @brief Allocation from a LargeBlockSuperblock (2 MB -- 64 MB). + */ +class MediumBlock : public Block { + std::unique_ptr untypedBuffer; + LargeBlockSuperblock *backingBlockSuperblock; +public: + MediumBlock(LargeBlockSuperblock *backingSuperblock, UntypedBuffer untypedBuffer); + virtual ~MediumBlock() override; + + UntypedBuffer *getUntypedBuffer() const noexcept override; +}; + +/** + * @brief Superblock managing 4 KB -- 2 MB sub-allocations via buddy system. + */ +class MediumBlockSuperblock : public MediumBlock, private BuddySuperblockBase<12, 21> { + using Buddy = BuddySuperblockBase<12, 21>; // 4KB - 2MB +public: + static constexpr size_t MAX_SIZE = 1ULL << Buddy::kMax; // 2MB + + MediumBlockSuperblock(LargeBlockSuperblock *backingSuperblock, UntypedBuffer untypedBuffer); + ~MediumBlockSuperblock() override; + + UntypedBuffer allocate(uint64_t size); + void deallocate(UntypedBuffer buffer); + bool isFree() const; +}; + +/** + * @brief Allocation from a MediumBlockSuperblock (up to 2 MB). + */ +class SmallBlock : public Block { + std::unique_ptr untypedBuffer; + MediumBlockSuperblock *backingBlockSuperblock; +public: + SmallBlock(MediumBlockSuperblock *backingBlockSuperblock, UntypedBuffer untypedBuffer); + ~SmallBlock() override; + + UntypedBuffer *getUntypedBuffer() const noexcept override; +}; + +/** + * @brief Top-level allocator dispatching to the buddy-system hierarchy. + */ +class Allocator { + std::vector> largeBlockSuperblocks; + std::vector> mediumBlockSuperblocks; +public: + Allocator(); + ~Allocator(); + + std::unique_ptr allocate(vrtd::Device& device, BufferAllocType type, BufferAllocDir dir, uint64_t size, HBMRegion region = HBMRegion::NON_HBM); + void deallocate(std::unique_ptr block); +}; + +} // namespace vrt + +#endif // VRT_ALLOCATOR_HPP diff --git a/vrt/include/vrt/buffer.hpp b/vrt/include/vrt/buffer.hpp new file mode 100644 index 00000000..edf509d8 --- /dev/null +++ b/vrt/include/vrt/buffer.hpp @@ -0,0 +1,505 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file buffer.hpp + * @brief Buffer — typed host-accessible memory with device synchronization. + */ + +#ifndef VRT_BUFFER_HPP +#define VRT_BUFFER_HPP + +#include +#include +#include + +#include +#include +#include +#include +#include + +namespace vrt { + +namespace detail { +inline uint64_t reserveFakePhysAddr(uint64_t sizeBytes, MemoryRangeType rangeType) { + // Match linker simulation address windows from run_pre.tcl: + // HBM/HBM_VNOC: 0x4000_0000_00 + // DDR: 0x6000_0000_000 + static std::atomic nextHbm{0x4000000000ull}; + static std::atomic nextDdr{0x60000000000ull}; + const uint64_t aligned = (sizeBytes + 0xfff) & ~0xfffull; + if (rangeType == MemoryRangeType::DDR) { + return nextDdr.fetch_add(aligned, std::memory_order_relaxed); + } + return nextHbm.fetch_add(aligned, std::memory_order_relaxed); +} +} // namespace detail + +/** + * @brief Enum class representing the type of synchronization. + */ +enum class SyncType { + HOST_TO_DEVICE, ///< Synchronize from host to device + DEVICE_TO_HOST, ///< Synchronize from device to host +}; + +/** + * @brief Class representing a buffer. + * + * This class provides an interface for managing a buffer in a device. + * It supports memory mapped QDMA connections. + * + * @tparam T The type of the elements in the buffer. + */ +template +class Buffer { + public: + /** + * @brief Constructor for Buffer. + * @param device VRT Device of the buffer. + * @param size The size of the buffer. + * @param type The type of memory range. + */ + Buffer(Device device, size_t size, MemoryRangeType type); + + /** + * @brief Constructor for Buffer. + * @param device VRT Device of the buffer. + * @param size The size of the buffer. + * @param type The type of memory range. + * @param port The HBM port number. Only valid when type is MemoryRangeType::HBM. + */ + Buffer(Device device, size_t size, MemoryRangeType type, uint8_t port); + + /** + * @brief Constructor for Buffer from a MemoryConfig. + * @param device VRT Device of the buffer. + * @param size The size of the buffer. + * @param config Memory configuration, typically obtained via Kernel::portMemoryConfig() + * or Kernel::argMemoryConfig(). + */ + Buffer(Device device, size_t size, MemoryConfig config); + + /** + * @brief Destructor for Buffer. + */ + ~Buffer(); + + /** + * @brief Gets a pointer to the buffer. + * @return A pointer to the buffer. + */ + T* get() const; + + /** + * @brief Overloads the subscript operator to access buffer elements. + * @param index The index of the element to access. + * @return A reference to the element at the specified index. + */ + T& operator[](size_t index); + + /** + * @brief Overloads the subscript operator to access buffer elements (const version). + * @param index The index of the element to access. + * @return A const reference to the element at the specified index. + */ + const T& operator[](size_t index) const; + + /** + * @brief Gets the memory range type of the buffer. + * @return The memory range type. + */ + MemoryRangeType getMemoryRangeType() const; + + /** + * @brief Gets the HBM port number of the buffer. + * @return The HBM port number, or 0 if no specific port was set. + */ + uint8_t getHBMPort() const; + + /** + * @brief Gets the physical address of the buffer. + * @return The physical address of the buffer. + */ + uint64_t getPhysAddr() const; + + /** + * @brief Gets the lower 32 bits of the physical address of the buffer. + * @return The lower 32 bits of the physical address of the buffer. + */ + uint32_t getPhysAddrLow() const; + + /** + * @brief Gets the upper 32 bits of the physical address of the buffer. + * @return The upper 32 bits of the physical address of the buffer. + */ + uint32_t getPhysAddrHigh() const; + + /** + * @brief Synchronizes the buffer. + * @param syncType The type of synchronization. + */ + void sync(SyncType syncType); + + std::string getName(); + + Buffer(const Buffer&) = delete; + Buffer& operator=(const Buffer&) = delete; + Buffer(Buffer&& other) noexcept; + Buffer& operator=(Buffer&& other) noexcept; + + private: + static BufferAllocType resolveAllocType(MemoryRangeType type, bool hasPort); + static HBMRegion resolveRegion(MemoryRangeType type, bool hasPort, uint8_t port); + void initAllocate(); + + uint64_t startAddress; ///< The starting address of the buffer + T* localBuffer; ///< Pointer to the local buffer + size_t size; ///< The size of the buffer + MemoryRangeType type; ///< The type of memory range + uint8_t hbmPort = 0; ///< HBM port number + bool hasPort = false; ///< Whether an explicit HBM port was specified + Device device; ///< The device associated with the buffer + std::unique_ptr block; ///< Allocator block (hardware only) + UntypedBuffer* view; ///< Cached view into the allocator block + bool ownsLocalBuffer; ///< Whether localBuffer should be deleted + std::size_t index; // Member variable to store the index of the buffer + static std::size_t bufferIndex; // Static variable to track the buffer index +}; + +template +size_t Buffer::bufferIndex = 0; + +template +Buffer::Buffer(Device device, size_t size, MemoryRangeType type) + : startAddress(0), + localBuffer(nullptr), + size(size), + type(type), + device(device), + block(nullptr), + view(nullptr), + ownsLocalBuffer(false), + index(bufferIndex++) { + if (type == MemoryRangeType::HBM) { + throw std::invalid_argument("HBM buffers require an explicit port. Use Buffer(device, size, MemoryRangeType::HBM, port)"); + } + initAllocate(); +} + +template +Buffer::Buffer(Device device, size_t size, MemoryRangeType type, uint8_t port) + : startAddress(0), + localBuffer(nullptr), + size(size), + type(type), + hbmPort(port), + hasPort(true), + device(device), + block(nullptr), + view(nullptr), + ownsLocalBuffer(false), + index(bufferIndex++) { + if (type != MemoryRangeType::HBM) { + throw std::invalid_argument("The port argument is only valid for HBM buffers. Use Buffer(device, size, type) for DDR or HBM_VNOC"); + } + initAllocate(); +} + +template +Buffer::Buffer(Device device, size_t size, MemoryConfig config) + : startAddress(0), + localBuffer(nullptr), + size(size), + type(config.type), + hbmPort(config.hbmPort.value_or(0)), + hasPort(config.hbmPort.has_value()), + device(device), + block(nullptr), + view(nullptr), + ownsLocalBuffer(false), + index(bufferIndex++) { + initAllocate(); +} + +template +void Buffer::initAllocate() { + Platform platform = this->device.getPlatform(); + if (platform == Platform::HARDWARE) { + BufferAllocType allocType = resolveAllocType(type, hasPort); + HBMRegion region = resolveRegion(type, hasPort, hbmPort); + block = this->device.getHandle()->getAllocator()->allocate(this->device.getHandle()->getVrtdDevice(), allocType, + BufferAllocDir::Bidirectional, + size * sizeof(T), region); + if (!block) { + throw std::bad_alloc(); + } + view = block->getUntypedBuffer(); + startAddress = view->getPhysAddr(); + localBuffer = static_cast(view->data()); + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, + "Allocated buffer final_space_bytes={} phys_addr={x}", + view->getSize(), startAddress); + } else { + startAddress = detail::reserveFakePhysAddr(size * sizeof(T), type); + localBuffer = new T[size]; + ownsLocalBuffer = true; + if (platform == Platform::EMULATION) { + // send initial buffer so it is populated in the emulation environment + std::shared_ptr server = this->device.getHandle()->getZmqServer(); + std::vector sendData; + std::size_t dataSize = size * sizeof(T); + sendData.resize(dataSize); + std::memcpy(sendData.data(), localBuffer, dataSize); + server->sendBuffer(std::to_string(getPhysAddr()), sendData); + } + } +} + +template +Buffer::~Buffer() { + if (block) { + device.getHandle()->getAllocator()->deallocate(std::move(block)); + } + if (ownsLocalBuffer && localBuffer != nullptr) { + delete[] localBuffer; + } +} + +template +T* Buffer::get() const { + return localBuffer; +} + +template +T& Buffer::operator[](size_t index) { + if (index >= size) { + throw std::out_of_range("Index out of range"); + } + return localBuffer[index]; +} + +template +const T& Buffer::operator[](size_t index) const { + if (index >= size) { + throw std::out_of_range("Index out of range"); + } + return localBuffer[index]; +} + +template +uint64_t Buffer::getPhysAddr() const { + return startAddress; +} + +template +uint32_t Buffer::getPhysAddrLow() const { + return startAddress & 0xFFFFFFFF; +} + +template +uint32_t Buffer::getPhysAddrHigh() const { + return (startAddress >> 32) & 0xFFFFFFFF; +} + +template +MemoryRangeType Buffer::getMemoryRangeType() const { + return type; +} + +template +uint8_t Buffer::getHBMPort() const { + return hbmPort; +} + +template +std::string Buffer::getName() { + return "buffer_" + std::to_string(index); +} + +template +void Buffer::sync(SyncType syncType) { + Platform platform = device.getPlatform(); + if (platform == Platform::HARDWARE) { + if (view == nullptr) { + throw std::runtime_error("Buffer view unavailable for hardware sync"); + } + uint64_t totalSize = size * sizeof(T); + if (syncType == SyncType::HOST_TO_DEVICE) { + view->syncToDevice(0, totalSize); + } else if (syncType == SyncType::DEVICE_TO_HOST) { + view->syncToHost(0, totalSize); + } else { + throw std::invalid_argument("Invalid sync type"); + } + } else if (platform == Platform::EMULATION) { + std::shared_ptr server = device.getHandle()->getZmqServer(); + if (syncType == SyncType::HOST_TO_DEVICE) { + std::vector sendData; + std::size_t dataSize = size * sizeof(T); + sendData.resize(dataSize); + std::memcpy(sendData.data(), localBuffer, dataSize); + server->sendBuffer(std::to_string(getPhysAddr()), sendData); + } else if (syncType == SyncType::DEVICE_TO_HOST) { + std::vector recvData = server->fetchBuffer(std::to_string(getPhysAddr())); + if ((recvData.size() % sizeof(T)) != 0) { + throw std::runtime_error("Received emulation buffer size is not aligned to element size"); + } + const size_t newSize = recvData.size() / sizeof(T); + if (newSize != size) { + T* resized = new T[newSize]; + std::memcpy(resized, recvData.data(), recvData.size()); + if (ownsLocalBuffer && localBuffer != nullptr) { + delete[] localBuffer; + } + localBuffer = resized; + ownsLocalBuffer = true; + size = newSize; + } else { + std::memcpy(localBuffer, recvData.data(), recvData.size()); + } + + } else { + throw std::invalid_argument("Invalid sync type"); + } + + } else if (platform == Platform::SIMULATION) { + std::shared_ptr server = device.getHandle()->getZmqServer(); + if (syncType == SyncType::HOST_TO_DEVICE) { + std::vector sendData; + std::size_t dataSize = size * sizeof(T); + sendData.resize(dataSize); + std::memcpy(sendData.data(), localBuffer, dataSize); + server->sendBufferSim(getPhysAddr(), sendData); + } else if (syncType == SyncType::DEVICE_TO_HOST) { + std::vector recvData; + server->fetchBufferSim(getPhysAddr(), size * sizeof(T), recvData); + if ((recvData.size() % sizeof(T)) != 0) { + throw std::runtime_error("Received simulation buffer size is not aligned to element size"); + } + const size_t newSize = recvData.size() / sizeof(T); + if (newSize != size) { + T* resized = new T[newSize]; + std::memcpy(resized, recvData.data(), recvData.size()); + if (ownsLocalBuffer && localBuffer != nullptr) { + delete[] localBuffer; + } + localBuffer = resized; + ownsLocalBuffer = true; + size = newSize; + } else { + std::memcpy(localBuffer, recvData.data(), recvData.size()); + } + } else { + throw std::invalid_argument("Invalid sync type"); + } + } +} +template +Buffer::Buffer(Buffer&& other) noexcept + : startAddress(other.startAddress), + localBuffer(other.localBuffer), + size(other.size), + type(other.type), + hbmPort(other.hbmPort), + hasPort(other.hasPort), + device(other.device), + block(std::move(other.block)), + view(other.view), + ownsLocalBuffer(other.ownsLocalBuffer), + index(other.index) { + if (block) { + view = block->getUntypedBuffer(); + localBuffer = static_cast(view->data()); + } + other.startAddress = 0; + other.localBuffer = nullptr; + other.size = 0; + other.device = Device{}; + other.view = nullptr; + other.ownsLocalBuffer = false; +} + +template +Buffer& Buffer::operator=(Buffer&& other) noexcept { + if (this != &other) { + if (ownsLocalBuffer && localBuffer) { + delete[] localBuffer; + } + + if (block) { + device.getHandle()->getAllocator()->deallocate(std::move(block)); + } + + device = other.device; + size = other.size; + type = other.type; + hbmPort = other.hbmPort; + hasPort = other.hasPort; + index = other.index; + startAddress = other.startAddress; + localBuffer = other.localBuffer; + block = std::move(other.block); + view = other.view; + ownsLocalBuffer = other.ownsLocalBuffer; + + if (block) { + view = block->getUntypedBuffer(); + localBuffer = static_cast(view->data()); + } + other.startAddress = 0; + other.localBuffer = nullptr; + other.size = 0; + other.device = Device{}; + other.view = nullptr; + other.ownsLocalBuffer = false; + } + return *this; +} + +template +BufferAllocType Buffer::resolveAllocType(MemoryRangeType type, bool hasPort) { + switch (type) { + case MemoryRangeType::DDR: + return BufferAllocType::Ddr; + case MemoryRangeType::HBM: + return hasPort ? BufferAllocType::Hbm : BufferAllocType::HbmVnoc; + case MemoryRangeType::HBM_VNOC: + return BufferAllocType::HbmVnoc; + default: + return BufferAllocType::Ddr; + } +} + +template +HBMRegion Buffer::resolveRegion(MemoryRangeType type, bool hasPort, uint8_t port) { + if (type == MemoryRangeType::HBM && hasPort) { + if (port > static_cast(HBMRegion::HBM63)) { + throw std::out_of_range("HBM port out of range"); + } + return static_cast(port); + } + return HBMRegion::NON_HBM; +} + +} // namespace vrt + +#endif // BUFFER_HPP diff --git a/vrt/include/vrt/device.hpp b/vrt/include/vrt/device.hpp new file mode 100644 index 00000000..c5387784 --- /dev/null +++ b/vrt/include/vrt/device.hpp @@ -0,0 +1,337 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file device.hpp + * @brief Device class — entry point for V80 hardware interaction. + */ + +#ifndef VRT_DEVICE_HPP +#define VRT_DEVICE_HPP + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace vrt { + +/** + * @brief Enumeration for device programming types. + * + * This enum represents the different methods that can be used to program a device. + */ +enum class ProgramType { + FLASH, ///< Program the device using flash memory + JTAG ///< Program the device using JTAG interface +}; + +/** + * @brief Path to the JTAG programming script. + * + * This macro defines the path to the shell script used for programming devices via JTAG. + */ +#define JTAG_PROGRAM_PATH "/usr/local/vrt/jtag_program.sh " + +/** + * @brief Path to the QDMA queue setup script. + * + * This macro defines the path to the shell script used for setting up QDMA queues. + */ + +/** + * @brief Delay in microseconds for partial boot process. + * + * This constant defines the delay time in microseconds that the system + * will wait during the partial boot process (4 seconds). + */ +#define DELAY_PARTIAL_BOOT (4 * 1000 * 1000) + +namespace impl { +/** + * @brief Class representing a device. + */ +class Device { + static constexpr uint64_t QDMA_LOGIC_BASE = 0x20100020000; ///< Base address for QDMA logic + static constexpr uint32_t QDMA_LOGIC_OFFSET = 0x1000; /// Offset for QDMA logic + static constexpr uint32_t CLOCK_MAX_FREQ = 333333333; + uint8_t bar = 0; ///< Base Address Register (BAR) + uint64_t offset = 0; ///< Offset for memory operations + uint16_t pci_bdf = 0; ///< PCI Bus:Device.Function identifier + std::string systemMap; ///< Path to the system map file + std::string bdf; ///< Bus:Device.Function identifier + std::string bdfFull; ///< Domain:Bus:Device.Function identifier + std::string pdiPath; ///< Path to the PDI file + std::vector pdiPaths; ///< Paths to PDI files discovered in archive + Vrtbin vrtbin; ///< Vrtbin object for handling VRTBIN operations + uint64_t clockFreq = 0; ///< Clock frequency + ProgramType programType{}; ///< Type of programming + std::map kernels; ///< Map of kernel names to Kernel objects + Allocator* allocator = nullptr; ///< Allocator object + Platform platform{}; ///< Platform information + std::shared_ptr zmqServer; ///< ZeroMQ server object + std::vector qdmaConnections; ///< Vector of QDMA connections + std::vector qdmaIntfs; ///< Vector of QDMA interfaces for streaming + std::shared_ptr vrtdSession; ///< vrtd session for hardware access + std::optional vrtdDevice; ///< vrtd device handle (requires session) + std::thread runtimeThread; ///< sw_emu/sim runtime launcher thread + bool cleanupDone = false; ///< Guard to make cleanup idempotent + public: + QdmaIntf qdmaIntf; ///< QDMA interface object + + /** + * @brief Constructor for Device. + * @param bdf The Bus:Device.Function identifier. + * @param vrtbinPath The path to the VRTBIN file. + * @param program Flag indicating whether to program the device. + */ + Device(const std::string& bdf, const std::string& vrtbinPath, bool program = true, + ProgramType programType = ProgramType::FLASH); + + Device() = delete; + Device(Device&) = delete; + Device(Device&&) = delete; + + /** + * @brief Gets a kernel by name. + * @param name The name of the kernel. + * @return The Kernel object. + */ + vrt::Kernel getKernel(const std::string& name); + + /** + * @brief Gets the Bus:Device.Function identifier. + * @return The Bus:Device.Function identifier. + */ + std::string getBdf(); + + /** + * @brief Programs the device. + */ + void programDevice(); + + /** + * @brief Destructor for Device. + */ + ~Device(); + + /** + * @brief Parses the system map file. + */ + void parseSystemMap(); + + /** + * @brief Cleans up the device. + */ + void cleanup(); + /** + * @brief Sets device clock frequency. + */ + void setFrequency(uint64_t freq); + + /** + * @brief Gets the clock frequency. + */ + uint64_t getFrequency(); + + /** + * @brief Gets the maximum frequency. + */ + uint64_t getMaxFrequency(); + + /** + * @brief Finds the VRTBIN type from system map. + */ + void findVrtbinType(); + + /** + * @brief Finds the platform from system map. + */ + void findPlatform(); + + /** + * @brief Gets the platform. + */ + Platform getPlatform(); + + /** + * @brief Gets the ZMQ server. + */ + std::shared_ptr getZmqServer(); + + /** + * @brief Gets the Allocator instance. + */ + Allocator* getAllocator(); + + /** + * @brief Gets the underlying vrtd device handle (hardware only). + */ + vrtd::Device& getVrtdDevice(); + + /** + * @brief Gets the underlying vrtd device handle (hardware only). + */ + const vrtd::Device& getVrtdDevice() const; + + /** + * @brief Gets the QDMA connections. + */ + std::vector getQdmaConnections(); + + // /** + // * @brief Gets the QDMA logic instance. + // */ + // QdmaLogic* getQdmaLogic(); + + /** + * @brief Gets the QDMA streaming interfaces. + */ + std::vector getQdmaInterfaces(); +}; +} // namespace impl + +/** + * @brief Public handle to a V80 device with move semantics. + * + * Thin wrapper around impl::Device providing the user-facing API for + * device initialization, kernel retrieval, frequency control, and cleanup. + */ +class Device { + std::shared_ptr handle; + + public: + /** + * @brief Default constructor for an empty device. + */ + Device() = default; + + /** + * @brief Constructor for Device. + * @param bdf The Bus:Device.Function identifier. + * @param vrtbinPath The path to the VRTBIN file. + * @param program Flag indicating whether to program the device. + */ + Device(const std::string& bdf, const std::string& vrtbinPath, bool program = true, + ProgramType programType = ProgramType::FLASH) : handle(new impl::Device(bdf, vrtbinPath, program, programType)) {} + + /** + * @brief Constructor from a device handle. + * @param handle The handle device handle + */ + Device(std::shared_ptr handle) : handle(handle) {} + + /** + * @brief Default copy constructor + */ + Device(const Device&) = default; + + /** + * @brief Default copy assignment + */ + Device& operator=(const Device&) = default; + + /** + * @brief Default move constructor + */ + Device(Device&&) = default; + + /** + * @brief Default move assignment + */ + Device& operator=(Device&&) = default; + + /** + * @brief Gets a kernel by name. + * @param name The name of the kernel. + * @return The Kernel object. + */ + vrt::Kernel getKernel(const std::string& name) { + return handle->getKernel(name); + } + + /** + * @brief Gets the Bus:Device.Function identifier. + * @return The Bus:Device.Function identifier. + */ + std::string + getBdf() { + return handle->getBdf(); + } + + /** + * @brief Sets device clock frequency. + */ + void setFrequency(uint64_t freq) { handle->setFrequency(freq); } + + /** + * @brief Cleans up device-side resources (simulation/emulation/hardware helpers). + */ + void cleanup() { + if (handle) { + handle->cleanup(); + } + } + + /** + * @brief Gets the clock frequency. + */ + uint64_t getFrequency() { return handle->getFrequency(); } + + /** + * @brief Gets the maximum frequency. + */ + uint64_t getMaxFrequency() { return handle->getMaxFrequency(); } + + /** + * @brief Gets the platform. + */ + Platform getPlatform() { return handle->getPlatform(); } + + /** + * @brief Return the internal device handle. + */ + std::shared_ptr getHandle() const { return handle; } +}; + +} // namespace vrt + +#endif // VRT_DEVICE_HPP diff --git a/vrt/include/driver/qdma_logic.hpp b/vrt/include/vrt/driver/qdma_logic.hpp similarity index 86% rename from vrt/include/driver/qdma_logic.hpp rename to vrt/include/vrt/driver/qdma_logic.hpp index 21126e8b..b61689da 100644 --- a/vrt/include/driver/qdma_logic.hpp +++ b/vrt/include/vrt/driver/qdma_logic.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,9 +18,9 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef QDMA_LOGIC_HPP -#define QDMA_LOGIC_HPP -#include "api/kernel.hpp" +#ifndef VRT_QDMA_LOGIC_HPP +#define VRT_QDMA_LOGIC_HPP +#include namespace vrt { @@ -37,12 +37,11 @@ class QdmaLogic : public Kernel { /** * @brief Constructor for QdmaLogic. * - * @param device Pointer to the AMI device. * @param name Name of the QDMA kernel. * @param baseAddr Base address of the QDMA kernel in device memory. * @param range Memory range allocated to the QDMA kernel. */ - QdmaLogic(ami_device* device, const std::string& name, uint64_t baseAddr, uint64_t range); + QdmaLogic(const std::string& name, uint64_t baseAddr, uint64_t range); /** * @brief Sets QDMA queue parameters. @@ -57,4 +56,4 @@ class QdmaLogic : public Kernel { } // namespace vrt -#endif // QDMA_LOGIC_HPP \ No newline at end of file +#endif // VRT_QDMA_LOGIC_HPP diff --git a/vrt/include/vrt/kernel.hpp b/vrt/include/vrt/kernel.hpp new file mode 100644 index 00000000..04ec52aa --- /dev/null +++ b/vrt/include/vrt/kernel.hpp @@ -0,0 +1,590 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file kernel.hpp + * @brief Kernel class — hardware kernel execution and argument management. + */ + +#ifndef VRT_KERNEL_HPP +#define VRT_KERNEL_HPP + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +namespace vrt { +class Device; +template +class Buffer; + +/** + * @brief Kernel argument metadata parsed from system_map.xml. + */ +struct FunctionalArg { + uint32_t idx = 0; ///< Argument index + std::string name; ///< Argument name + std::string type; ///< C type (e.g. "int", "float*") + uint32_t offset = 0; ///< Register offset for this argument + uint32_t range = 32; ///< Bit width (32 or 64; 0 treated as 32) + bool readable = false; ///< Whether the argument register is readable + bool writable = false; ///< Whether the argument register is writable + std::string port; ///< AXI port name (for memory arguments) +}; + +/** + * @brief Class representing a kernel. + */ +class Kernel { + uint8_t bar = 0; ///< Base Address Register (BAR) + std::string name; ///< Name of the kernel + uint64_t baseAddr = 0; ///< Base address of the kernel + uint64_t range = 0; ///< Address range of the kernel + std::vector registers; ///< List of registers in the kernel + std::vector functionalArgs; ///< Parsed function arguments from system_map.xml + size_t currentArgIndex = 0; ///< Current call argument index + std::string deviceBdf; ///< BDF of the device + Platform platform = Platform::UNKNOWN; ///< Platform of the device + std::shared_ptr server; ///< Pointer to ZeroMQ server for communication + std::map registerMap; ///< Map of register offsets to values + std::map setArgValues; ///< Values assigned through setArg(idx/name, value) + std::optional vrtdBar; ///< vrtd BAR handle for hardware access + /// Cached BAR file mapping. Wrapped in shared_ptr because BarFile is + /// non-copyable and Kernel currently uses defaulted copy semantics. + /// TODO: Consider making Kernel move-only and using unique_ptr instead. + std::shared_ptr vrtdBarFile; + + vrtd::BarFile& getOrOpenBarFile(); + std::vector emuCallArgKinds; ///< Optional EMU arg kind metadata from emu_manifest.json + std::map emuFetchScalarArgByOffset; ///< Optional EMU fetch routing by register offset + std::map connections; ///< Port-to-target memory mappings from system_map.xml + + template + struct HasPhysAddr : std::false_type {}; + + template + struct HasPhysAddr().getPhysAddr())>> + : std::true_type {}; + + template + struct HasMemoryInfo : std::false_type {}; + + template + struct HasMemoryInfo().getMemoryRangeType()), + decltype(std::declval().getHBMPort())>> + : std::true_type {}; + + void validateBufferMemoryType(const FunctionalArg& argMeta, MemoryRangeType memType, + uint8_t hbmPort) const; + + template + void validateBufferArg(const FunctionalArg& argMeta, const T& arg, std::true_type) const { + validateBufferMemoryType(argMeta, arg.getMemoryRangeType(), arg.getHBMPort()); + } + + template + void validateBufferArg(const FunctionalArg& /*argMeta*/, const T& /*arg*/, + std::false_type) const {} + + template + static uint64_t resolveKernelArgImpl(T&& arg, std::true_type) { + return static_cast(arg.getPhysAddr()); + } + + template + static decltype(auto) resolveKernelArgImpl(T&& arg, std::false_type) { + return std::forward(arg); + } + + template + static decltype(auto) resolveKernelArg(T&& arg) { + using ArgT = std::remove_reference_t; + return resolveKernelArgImpl(std::forward(arg), HasPhysAddr{}); + } + + static uint32_t argWordCount(const FunctionalArg& arg) { + const uint32_t bits = (arg.range == 0) ? 32u : arg.range; + return std::max(1u, (bits + 31u) / 32u); + } + + static uint32_t argWordValue(uint64_t value, uint32_t wordIdx) { + if (wordIdx == 0) return static_cast(value & 0xFFFFFFFFULL); + if (wordIdx == 1) return static_cast((value >> 32) & 0xFFFFFFFFULL); + return 0u; + } + + static std::string normalizeArgType(std::string value) { + std::transform(value.begin(), value.end(), value.begin(), [](unsigned char c) { + return static_cast(std::tolower(c)); + }); + return value; + } + + void ensureFunctionalArgsForCall(std::size_t providedArgCount, std::string_view opName) const { + if (providedArgCount == 0) { + return; + } + if (functionalArgs.empty()) { + throwArgApiMisuse( + "This kernel has no functional_args metadata in system_map.xml, " + "so argument-based launch is unavailable.", + opName); + } + if (providedArgCount > functionalArgs.size()) { + throwArgApiMisuse( + "Too many positional arguments were provided (" + std::to_string(providedArgCount) + + "); kernel metadata defines " + std::to_string(functionalArgs.size()) + + " functional argument(s).", + opName); + } + } + + std::string buildArgApiUsageMessage(std::string_view reason, std::string_view opName) const; + [[noreturn]] void throwArgApiMisuse(std::string_view reason, std::string_view opName) const; + void ensureNoSetArgValuesWhenPassingArgs(std::size_t providedArgCount, std::string_view opName) const; + void ensureSetArgValuesCompleteForLaunch(std::string_view opName) const; + const FunctionalArg& functionalArgByIdx(uint32_t idx) const; + uint32_t functionalArgIdxByName(std::string_view argName) const; + void setArgResolved(uint32_t idx, uint64_t value); + void writeArgToRegisterMap(const FunctionalArg& argMeta, uint64_t value); + void writeArgToSimulation(const FunctionalArg& argMeta, uint64_t value); + void writeArgToEmulation(Json::Value& command, const FunctionalArg& argMeta, uint64_t value) const; + void applySetArgsToRegisterMap(); + void applySetArgsToSimulation(); + void applySetArgsToEmulation(Json::Value& command) const; + public: + /** + * @brief Constructor for Kernel. + * @param name The name of the kernel. + * @param baseAddr The base address of the kernel. + * @param range The address range of the kernel. + * @param registers The list of registers in the kernel. + * @param functionalArgs Parsed function-argument metadata from system_map.xml. + */ + Kernel(const std::string& name, uint64_t baseAddr, uint64_t range, + const std::vector& registers, + const std::vector& functionalArgs = {}); + + /** + * @brief Default constructor for Kernel. + */ + Kernel() = default; + + /** + * @brief Default copy constructor for Kernel. + */ + Kernel(const Kernel&) = default; + + /** + * @brief Default move constructor for Kernel. + */ + Kernel(Kernel&&) = default; + + /** + * @brief Constructor for Kernel using a Device object. + * @param device The Device object. + * @param kernelName The name of the kernel. + */ + Kernel(vrt::Device device, const std::string& kernelName); + + /** + * @brief Sets the vrtd BAR handle for hardware access. + * @param bar The vrtd BAR handle. + */ + void setVrtdBar(const std::optional& bar); + + /** + * @brief Sets the ZeroMQ server for emulation and simulation. + * @param server The ZeroMQ server handle. + */ + void setServer(std::shared_ptr server); + + /** + * @brief Writes a value to a register. + * @param offset The offset of the register. + * @param value The value to write. + */ + void write(uint32_t offset, uint32_t value); + + /** + * @brief Reads a value from a register. + * @param offset The offset of the register. + * @return The value read from the register. + */ + uint32_t read(uint32_t offset); + + /** + * @brief Waits for the kernel to complete. + */ + void wait(); + + /** + * @brief Starts the kernel. + * @param autorestart Flag indicating whether to enable autorestart. + */ + void startKernel(bool autorestart = false); + + /** + * @brief Sets the platform for the kernel. + * @param platform The platform to set. + */ + void setPlatform(Platform platform); + + /** + * @brief Sets parsed function argument metadata. + */ + void setFunctionalArgs(const std::vector& args); + + /** + * @brief Returns true when function argument metadata is available. + */ + bool hasFunctionalArgs() const; + + /** + * @brief Get information about the functional arguments. + */ + const std::vector& getFunctionalArgs() const; + + /** + * @brief Sets EMU call argument kinds loaded from emu_manifest.json. + * Index corresponds to argN in EMU call JSON. + */ + void setEmuCallArgKinds(const std::vector& kinds); + /** + * @brief Sets EMU scalar fetch routing keyed by register offset. + * Used by Kernel::read() in EMULATION mode. + */ + void setEmuFetchScalarArgByOffset(const std::map& routes); + + /** + * @brief Sets port-to-target memory connection mappings from system_map.xml. + */ + void setConnections(const std::map& conns); + + /** + * @brief Returns the memory configuration for a named AXI port. + * + * Looks up the port in the kernel's connection map (populated from system_map.xml) + * and returns a MemoryConfig that can be passed directly to the Buffer constructor. + * + * @param portName The AXI port name (e.g. "m_axi_gmem0"). + * @throws std::runtime_error if the port has no connection entry. + */ + MemoryConfig portMemoryConfig(std::string_view portName) const; + + /** + * @brief Returns the memory configuration for a named kernel argument. + * + * Resolves the argument to its AXI port via functional_args metadata and then + * delegates to portMemoryConfig(). The returned MemoryConfig can be passed + * directly to the Buffer constructor. + * + * @param argName The argument name from functional_args metadata. + * @throws std::runtime_error if the argument is not found or has no AXI port. + */ + MemoryConfig argMemoryConfig(std::string_view argName) const; + + /** + * @brief Set argument value by argument index from functional_args metadata. + */ + template + void setArg(int idx, T&& value) { + if (idx < 0) { + throwArgApiMisuse("setArg(index, value) received a negative argument index.", + "setArg"); + } + using RawT = std::remove_cv_t>; + if constexpr (HasMemoryInfo::value) { + const FunctionalArg& argMeta = functionalArgByIdx(static_cast(idx)); + validateBufferArg(argMeta, value, HasMemoryInfo{}); + } + decltype(auto) resolvedValue = resolveKernelArg(std::forward(value)); + setArgResolved(static_cast(idx), static_cast(resolvedValue)); + } + + /** + * @brief Set argument value by argument name from functional_args metadata. + */ + template + void setArg(std::string_view argName, T&& value) { + using RawT = std::remove_cv_t>; + if constexpr (HasMemoryInfo::value) { + uint32_t idx = functionalArgIdxByName(argName); + const FunctionalArg& argMeta = functionalArgByIdx(idx); + validateBufferArg(argMeta, value, HasMemoryInfo{}); + } + decltype(auto) resolvedValue = resolveKernelArg(std::forward(value)); + setArgResolved(functionalArgIdxByName(argName), static_cast(resolvedValue)); + } + + /** + * @brief Writes batch register to PCIe BAR. + */ + void writeBatch(); + + /** + * @brief Calls the kernel and waits for it to complete. + * @param args The arguments to pass to the kernel. + */ + template + void call(Args&&... args) { + const std::size_t providedArgCount = sizeof...(Args); + currentArgIndex = 0; + registerMap.clear(); + ensureNoSetArgValuesWhenPassingArgs(providedArgCount, "call"); + ensureFunctionalArgsForCall(providedArgCount, "call"); + + if (platform == Platform::HARDWARE) { + if constexpr (sizeof...(Args) > 0) { + (processArg(std::forward(args)), ...); + this->writeBatch(); + } else if (!setArgValues.empty()) { + ensureSetArgValuesCompleteForLaunch("call"); + applySetArgsToRegisterMap(); + this->writeBatch(); + } else if (!functionalArgs.empty()) { + throwArgApiMisuse( + "call() was invoked without positional args and no setArg values were provided, " + "but this kernel has functional arguments.", + "call"); + } + this->startKernel(); + this->wait(); + } else if (platform == Platform::EMULATION) { + Json::Value command; + command["command"] = "call"; + command["function"] = name; + if constexpr (sizeof...(Args) > 0) { + (processEmuArg(std::forward(args), command), ...); + } else if (!setArgValues.empty()) { + ensureSetArgValuesCompleteForLaunch("call"); + applySetArgsToEmulation(command); + } else if (!functionalArgs.empty()) { + throwArgApiMisuse( + "call() was invoked without positional args and no setArg values were provided, " + "but this kernel has functional arguments.", + "call"); + } + server->sendCommand(command); + } else if (platform == Platform::SIMULATION) { + if constexpr (sizeof...(Args) > 0) { + (processSimArg(std::forward(args)), ...); + } else if (!setArgValues.empty()) { + ensureSetArgValuesCompleteForLaunch("call"); + applySetArgsToSimulation(); + } else if (!functionalArgs.empty()) { + throwArgApiMisuse( + "call() was invoked without positional args and no setArg values were provided, " + "but this kernel has functional arguments.", + "call"); + } + this->startKernel(); + this->wait(); + } + } + + /** + * @brief Starts the kernel. + */ + void start(); + + /** + * @brief Starts the kernel with arguments. + * @param args The arguments to pass to the kernel. + */ + template + void start(Args&&... args) { + const std::size_t providedArgCount = sizeof...(Args); + currentArgIndex = 0; + registerMap.clear(); + ensureNoSetArgValuesWhenPassingArgs(providedArgCount, "start"); + ensureFunctionalArgsForCall(providedArgCount, "start"); + if (platform == Platform::HARDWARE) { + if constexpr (sizeof...(Args) > 0) { + (processArg(std::forward(args)), ...); + this->writeBatch(); + } else if (!setArgValues.empty()) { + ensureSetArgValuesCompleteForLaunch("start"); + applySetArgsToRegisterMap(); + this->writeBatch(); + } else if (!functionalArgs.empty()) { + throwArgApiMisuse( + "start() was invoked without positional args and no setArg values were provided, " + "but this kernel has functional arguments.", + "start"); + } + this->startKernel(); + + } else if (platform == Platform::EMULATION) { + Json::Value command; + command["command"] = "start"; + command["function"] = name; + if constexpr (sizeof...(Args) > 0) { + (processEmuArg(std::forward(args), command), ...); + } else if (!setArgValues.empty()) { + ensureSetArgValuesCompleteForLaunch("start"); + applySetArgsToEmulation(command); + } else if (!functionalArgs.empty()) { + throwArgApiMisuse( + "start() was invoked without positional args and no setArg values were provided, " + "but this kernel has functional arguments.", + "start"); + } + server->sendCommand(command); + } else if (platform == Platform::SIMULATION) { + if constexpr (sizeof...(Args) > 0) { + (processSimArg(std::forward(args)), ...); + } else if (!setArgValues.empty()) { + ensureSetArgValuesCompleteForLaunch("start"); + applySetArgsToSimulation(); + } else if (!functionalArgs.empty()) { + throwArgApiMisuse( + "start() was invoked without positional args and no setArg values were provided, " + "but this kernel has functional arguments.", + "start"); + } + this->startKernel(); + } + } + /** + * @brief Helper method which processes an argument. + * @tparam T The type of the argument. + * @param arg The argument to process. + */ + template + void processArg(T&& arg) { + if (currentArgIndex >= functionalArgs.size()) { + throwArgApiMisuse( + "Positional argument index " + std::to_string(currentArgIndex) + + " exceeds available functional_args entries.", + "start/call"); + } + + const FunctionalArg& argMeta = functionalArgs.at(currentArgIndex); + using RawT = std::remove_cv_t>; + validateBufferArg(argMeta, arg, HasMemoryInfo{}); + decltype(auto) resolvedArg = resolveKernelArg(std::forward(arg)); + const uint64_t value = static_cast(resolvedArg); + writeArgToRegisterMap(argMeta, value); + currentArgIndex++; + } + + /** + * @brief Helper method which processes an argument for simulation. + * @tparam T The type of the argument. + * @param arg The argument to process. + */ + template + void processSimArg(T&& arg) { + if (currentArgIndex >= functionalArgs.size()) { + throwArgApiMisuse( + "Positional argument index " + std::to_string(currentArgIndex) + + " exceeds available functional_args entries.", + "start/call"); + } + + const FunctionalArg& argMeta = functionalArgs.at(currentArgIndex); + using RawT = std::remove_cv_t>; + validateBufferArg(argMeta, arg, HasMemoryInfo{}); + decltype(auto) resolvedArg = resolveKernelArg(std::forward(arg)); + const uint64_t value = static_cast(resolvedArg); + writeArgToSimulation(argMeta, value); + currentArgIndex++; + } + + /** + * @brief Helper method which processes an argument for emulation. + * @tparam T The type of the argument. + * @param arg The argument to process. + * @param command The JSON command to update. + */ + template + void processEmuArg(T&& arg, Json::Value& command) { + if (currentArgIndex >= functionalArgs.size()) { + throwArgApiMisuse( + "Positional argument index " + std::to_string(currentArgIndex) + + " exceeds available functional_args entries.", + "start/call"); + } + + const FunctionalArg& argMeta = functionalArgs.at(currentArgIndex); + using RawT = std::remove_cv_t>; + validateBufferArg(argMeta, arg, HasMemoryInfo{}); + decltype(auto) resolvedArg = resolveKernelArg(std::forward(arg)); + writeArgToEmulation(command, argMeta, static_cast(resolvedArg)); + currentArgIndex++; + } + + /** + * @brief Getter for the kernel name. + * @return The name of the kernel. + */ + std::string getName() const; + + /** + * @brief Getter for the kernel base physical address. + * @return The physical base address of the kernel. + */ + uint64_t getPhysAddr() const; + + /** + * @brief Destructor for Kernel. + */ + ~Kernel(); + + /** + * @brief Copy assignment operator. + * + * @param other The kernel to copy from. + * @return Reference to this kernel. + */ + Kernel& operator=(const Kernel& other) = default; + + /** + * @brief Move assignment operator. + * + * @param other The kernel to move from. + * @return Reference to this kernel. + */ + Kernel& operator=(Kernel&& other) noexcept = default; +}; + +} // namespace vrt + +#endif // VRT_KERNEL_HPP diff --git a/vrt/include/vrt/parser/utilization_data.hpp b/vrt/include/vrt/parser/utilization_data.hpp new file mode 100644 index 00000000..4ac196b7 --- /dev/null +++ b/vrt/include/vrt/parser/utilization_data.hpp @@ -0,0 +1,102 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file utilization_data.hpp + * @brief Data structures for FPGA resource utilization reports. + */ + +#ifndef VRT_UTILIZATION_DATA_HPP +#define VRT_UTILIZATION_DATA_HPP + +#include +#include +#include +#include + +namespace vrt { + +/** + * @brief FPGA resource counts and optional utilization percentages. + */ +struct ResourceMetrics { + uint32_t totalPplocs = 0; ///< Total physical placement locations + uint32_t totalLuts = 0; ///< Total look-up tables used + uint32_t lutram = 0; ///< LUTs used as distributed RAM + uint32_t srl = 0; ///< LUTs used as shift registers + uint32_t ff = 0; ///< Flip-flops used + uint32_t ramb36 = 0; ///< 36 Kb block RAMs used + uint32_t ramb18 = 0; ///< 18 Kb block RAMs used + uint32_t ramb = 0; ///< Total block RAMs used + uint32_t uram = 0; ///< UltraRAMs used + uint32_t dsp = 0; ///< DSP slices used + + std::optional totalLutsPct; ///< LUT utilization percentage + std::optional lutramPct; ///< LUTRAM utilization percentage + std::optional srlPct; ///< SRL utilization percentage + std::optional ffPct; ///< FF utilization percentage + std::optional ramb36Pct; ///< RAMB36 utilization percentage + std::optional ramb18Pct; ///< RAMB18 utilization percentage + std::optional uramPct; ///< URAM utilization percentage + std::optional dspPct; ///< DSP utilization percentage +}; + +/** + * @brief Per-instance resource metrics for a single module. + */ +struct UtilizationCell { + std::string instance; ///< Module instance name + std::string module; ///< Module definition name + std::string pr; ///< Partial reconfiguration region + ResourceMetrics metrics; ///< Resource counts for this instance +}; + +/** + * @brief Hierarchical grouping of user logic and framework overhead cells. + */ +struct Subhierarchy { + std::vector cells; ///< User logic cells + std::vector slashLogic; ///< SLASH framework overhead cells + ResourceMetrics subhierarchySum; ///< Aggregated metrics for user logic + ResourceMetrics slashLogicSum; ///< Aggregated metrics for framework logic +}; + +/** + * @brief Top-level utilization block (e.g. SLASH framework or service layer). + */ +struct UtilizationBlock { + std::string name; ///< Block name + std::string instance; ///< Block instance name + std::string pr; ///< Partial reconfiguration region + ResourceMetrics totals; ///< Block-level resource totals + std::optional subhierarchy; ///< Detailed breakdown (if available) +}; + +/** + * @brief Complete FPGA design utilization report. + */ +struct UtilizationReport { + UtilizationBlock slash; ///< SLASH framework block (always present) + std::optional serviceLayer; ///< Optional service layer block +}; + +} // namespace vrt + +#endif // VRT_UTILIZATION_DATA_HPP diff --git a/vrt/include/vrt/parser/utilization_parser.hpp b/vrt/include/vrt/parser/utilization_parser.hpp new file mode 100644 index 00000000..726a027c --- /dev/null +++ b/vrt/include/vrt/parser/utilization_parser.hpp @@ -0,0 +1,63 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRT_UTILIZATION_PARSER_HPP +#define VRT_UTILIZATION_PARSER_HPP + +#include +#include + +#include + +#include + +namespace vrt { + +/** + * @brief Parses a report_utilization.xml file into a UtilizationReport. + */ +class UtilizationParser { + std::string filename; + xmlDocPtr document = nullptr; + UtilizationReport report; + + public: + /** + * @brief Constructor for UtilizationParser. + * @param filePath Path to the report_utilization*.xml file. + */ + explicit UtilizationParser(const std::string& filePath); + + /** + * @brief Parses the XML document and populates the internal report. + */ + void parse(); + + /** + * @brief Returns the parsed utilization report. + */ + const UtilizationReport& getReport() const; + + ~UtilizationParser(); +}; + +} // namespace vrt + +#endif // VRT_UTILIZATION_PARSER_HPP diff --git a/vrt/include/parser/xml_parser.hpp b/vrt/include/vrt/parser/xml_parser.hpp similarity index 83% rename from vrt/include/parser/xml_parser.hpp rename to vrt/include/vrt/parser/xml_parser.hpp index aa5d7a27..2c41fce6 100644 --- a/vrt/include/parser/xml_parser.hpp +++ b/vrt/include/vrt/parser/xml_parser.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef XML_PARSER_HPP -#define XML_PARSER_HPP +#ifndef VRT_XML_PARSER_HPP +#define VRT_XML_PARSER_HPP #include #include @@ -29,22 +29,13 @@ #include #include -#include "api/kernel.hpp" // Include the Kernel class -#include "qdma/qdma_connection.hpp" -#include "utils/platform.hpp" +#include // Include the Kernel class +#include +#include namespace vrt { class Kernel; -/** - * @brief Enum class for the different types of VRT bins. - */ -enum class VrtbinType { - FLAT, - SEGMENTED - // PARTIAL when implemented -}; - /** * @brief Class for parsing XML files to extract kernel information. */ @@ -55,7 +46,6 @@ class XMLParser { xmlNode* workingNode; ///< Pointer to the current working node in the XML document. std::map kernels; ///< Map of kernel names to Kernel objects. uint64_t clockFrequency; ///< The clock frequency of the device. - VrtbinType vrtbinType; ///< The VRT bin type of the device. Platform platform; ///< The platform of the device. std::vector qdmaConnections; ///< Vector of QDMA connections. @@ -90,12 +80,6 @@ class XMLParser { */ uint64_t getClockFrequency(); - /** - * @brief Gets the VRT bin type of the device. - * @return The VRT bin type of the device. - */ - VrtbinType getVrtbinType(); - /** * @brief Gets the platform of the device. * @return The platform of the device. @@ -116,4 +100,4 @@ class XMLParser { } // namespace vrt -#endif // XML_PARSER_HPP \ No newline at end of file +#endif // VRT_XML_PARSER_HPP \ No newline at end of file diff --git a/vrt/include/qdma/pcie_driver_handler.hpp b/vrt/include/vrt/qdma/pcie_driver_handler.hpp similarity index 92% rename from vrt/include/qdma/pcie_driver_handler.hpp rename to vrt/include/vrt/qdma/pcie_driver_handler.hpp index 35d0246b..9fd90616 100644 --- a/vrt/include/qdma/pcie_driver_handler.hpp +++ b/vrt/include/vrt/qdma/pcie_driver_handler.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef PCIE_DRIVER_HANDLER_HPP -#define PCIE_DRIVER_HANDLER_HPP +#ifndef VRT_PCIE_DRIVER_HANDLER_HPP +#define VRT_PCIE_DRIVER_HANDLER_HPP #include #include @@ -27,7 +27,8 @@ #include #include -#include "utils/logger.hpp" +#include + namespace vrt { /** * @brief Class for handling PCIe driver commands. @@ -76,4 +77,4 @@ class PcieDriverHandler { } // namespace vrt -#endif // PCIE_DRIVER_HANDLER_HPP \ No newline at end of file +#endif // VRT_PCIE_DRIVER_HANDLER_HPP \ No newline at end of file diff --git a/vrt/include/qdma/qdma_connection.hpp b/vrt/include/vrt/qdma/qdma_connection.hpp similarity index 94% rename from vrt/include/qdma/qdma_connection.hpp rename to vrt/include/vrt/qdma/qdma_connection.hpp index f4f6de77..0dfef055 100644 --- a/vrt/include/qdma/qdma_connection.hpp +++ b/vrt/include/vrt/qdma/qdma_connection.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,10 +18,11 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef QDMA_CONNECTION_HPP -#define QDMA_CONNECTION_HPP +#ifndef VRT_QDMA_CONNECTION_HPP +#define VRT_QDMA_CONNECTION_HPP #include +#include namespace vrt { @@ -93,4 +94,4 @@ class QdmaConnection { }; } // namespace vrt -#endif // QDMA_CONNECTION_HPP \ No newline at end of file +#endif // VRT_QDMA_CONNECTION_HPP \ No newline at end of file diff --git a/vrt/include/qdma/qdma_intf.hpp b/vrt/include/vrt/qdma/qdma_intf.hpp similarity index 72% rename from vrt/include/qdma/qdma_intf.hpp rename to vrt/include/vrt/qdma/qdma_intf.hpp index 11520033..922aa69a 100644 --- a/vrt/include/qdma/qdma_intf.hpp +++ b/vrt/include/vrt/qdma/qdma_intf.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef QDMA_INTF_HPP -#define QDMA_INTF_HPP +#ifndef VRT_QDMA_INTF_HPP +#define VRT_QDMA_INTF_HPP #include #include @@ -27,19 +27,23 @@ #include #include +#include #include -#include "utils/logger.hpp" +#include +#include + +#include #define RW_MAX_SIZE 0x7ffff000 ///< Maximum size for read/write operations #define GB_DIV 1000000000 ///< Divider for gigabytes #define MB_DIV 1000000 ///< Divider for megabytes #define KB_DIV 1000 ///< Divider for kilobytes #define NSEC_DIV 1000000000 ///< Divider for nanoseconds -#define QMAX_PATH "/sys/bus/pci/devices/0000:%s:00.1/qdma/qmax" ///< Path for QMAX -#define QDMA_QUEUE_NAME "qdma%s001" ///< Format for QDMA queue name -#define QDMA_DEFAULT_QUEUE "/dev/qdma%s001-MM-0" ///< Default QDMA queue -#define QDMA_DEFAULT_ST_QUEUE "/dev/qdma%s001-ST-%u" ///< Default stream queue + +namespace vrtd { +class Device; +} namespace vrt { /** @@ -48,7 +52,8 @@ namespace vrt { class QdmaIntf { uint8_t queueIdx; ///< Queue index std::string bdf; ///< Bus:Device.Function identifier - std::string queueName; ///< Queue name + std::optional qpair; ///< vrtd qpair (streaming) + int qpairFd = -1; ///< Cached qpair fd /** * @brief Writes data from a buffer to a device. @@ -75,39 +80,19 @@ class QdmaIntf { * @param bdf The BDF to strip. * @return The stripped bus part. */ - char* strip(const char* bdf); - - /** - * @brief Creates a QDMA queue. - * @param bdf The BDF of the device. - * @return The name of the created queue. - */ - char* create_qdma_queue(const char* bdf); - - /** - * @brief Deletes a QDMA queue. - * @param bdf The BDF of the device. - * @return 0 on success, -1 on failure. - */ - int delete_qdma_queue(const char* bdf); - - // Static instance pointer - static QdmaIntf* instance; public: /** * @brief Constructor of the QdmaIntf class * @param bdf The BDF (Bus:Device.Function) of the device. */ - QdmaIntf(const std::string& bdf); - /** - * @brief Constructor of the QdmaIntf class with queue index - * @brief Assumes all queues are stream type - * @param bdf The BDF (Bus:Device.Function) of the device. - * @param queueIdx The index of the queue. + * @brief Constructor of the QdmaIntf class using vrtd qpair (streaming). + * @param device The vrtd device handle. + * @param queueIdx The stream queue index (from system map). + * @param direction Stream direction (H2C or C2H). */ - QdmaIntf(const std::string& bdf, const uint32_t queueIdx); + QdmaIntf(const vrtd::Device& device, const uint32_t queueIdx, StreamDirection direction); /** * @brief Default constructor for QdmaIntf. @@ -142,4 +127,4 @@ class QdmaIntf { }; } // namespace vrt -#endif // QDMA_INTF_HPP \ No newline at end of file +#endif // VRT_QDMA_INTF_HPP diff --git a/vrt/include/register/register.hpp b/vrt/include/vrt/register/register.hpp similarity index 95% rename from vrt/include/register/register.hpp rename to vrt/include/vrt/register/register.hpp index c3f839a4..b51fea1f 100644 --- a/vrt/include/register/register.hpp +++ b/vrt/include/vrt/register/register.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef REGISTER_HPP -#define REGISTER_HPP +#ifndef VRT_REGISTER_HPP +#define VRT_REGISTER_HPP #include #include @@ -115,4 +115,4 @@ class Register { } // namespace vrt -#endif // REGISTER_HPP \ No newline at end of file +#endif // VRT_REGISTER_HPP \ No newline at end of file diff --git a/vrt/include/api/streaming_buffer.hpp b/vrt/include/vrt/streaming_buffer.hpp similarity index 81% rename from vrt/include/api/streaming_buffer.hpp rename to vrt/include/vrt/streaming_buffer.hpp index ef041a34..a37525de 100644 --- a/vrt/include/api/streaming_buffer.hpp +++ b/vrt/include/vrt/streaming_buffer.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,12 +18,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef STREAMING_BUFFER_HPP -#define STREAMING_BUFFER_HPP +#ifndef VRT_STREAMING_BUFFER_HPP +#define VRT_STREAMING_BUFFER_HPP #include -#include "api/device.hpp" +#include "device.hpp" #include "qdma/qdma_connection.hpp" #include "qdma/qdma_intf.hpp" #include "utils/platform.hpp" @@ -95,22 +95,22 @@ class StreamingBuffer { void sync(); private: - T* localBuffer; ///< Pointer to the local buffer. - size_t size; ///< Size of the buffer. - StreamDirection syncType; ///< Synchronization type (direction). - Device device; ///< Device associated with the buffer. - Kernel kernel; ///< Kernel associated with the buffer. - std::size_t index; ///< Index of the buffer. - std::string name; ///< Name of the buffer. - std::string portName; ///< Name of the port associated with the buffer. - QdmaIntf* qdmaInterface; ///< Pointer to the QDMA interface. + T* localBuffer; ///< Pointer to the local buffer. + size_t size; ///< Size of the buffer. + StreamDirection syncType; ///< Synchronization type (direction). + Device device; ///< Device associated with the buffer. + Kernel kernel; ///< Kernel associated with the buffer. + std::size_t index; ///< Index of the buffer. + std::string name; ///< Name of the buffer. + std::string portName; ///< Name of the port associated with the buffer. + QdmaIntf* qdmaInterface = nullptr; ///< Pointer to the QDMA interface. }; template StreamingBuffer::StreamingBuffer(Device device, Kernel kernel, const std::string& portName, size_t size) : device(device), size(size), kernel(kernel), portName(portName) { - std::vector qdmaConnections = device.getQdmaConnections(); + std::vector qdmaConnections = device.getHandle()->getQdmaConnections(); bool gotQdma = false; for (const auto& con : qdmaConnections) { if (con.getKernel() == kernel.getName() && portName == con.getInterface()) { @@ -129,7 +129,7 @@ StreamingBuffer::StreamingBuffer(Device device, Kernel kernel, const std::str localBuffer = new T[size]; Platform platform = device.getPlatform(); if (platform == Platform::HARDWARE) { - for (auto& qdmaIntf : device.getQdmaInterfaces()) { + for (auto& qdmaIntf : device.getHandle()->getQdmaInterfaces()) { if (qdmaIntf->getQueueIdx() == index) { qdmaInterface = qdmaIntf; } @@ -162,7 +162,7 @@ template void StreamingBuffer::sync() { Platform platform = device.getPlatform(); if (platform == Platform::EMULATION) { - ZmqServer* server = device.getZmqServer(); + auto server = device.getHandle()->getZmqServer(); if (syncType == StreamDirection::HOST_TO_DEVICE) { std::vector sendData; std::size_t dataSize = size * sizeof(T); @@ -176,10 +176,13 @@ void StreamingBuffer::sync() { std::memcpy(localBuffer, recvData.data(), recvData.size()); } } else if (platform == Platform::HARDWARE) { + if (qdmaInterface == nullptr) { + throw std::runtime_error("QDMA interface not initialized for streaming buffer"); + } if (syncType == StreamDirection::HOST_TO_DEVICE) { qdmaInterface->write_buff(reinterpret_cast(localBuffer), 0, size * sizeof(T)); } else { - throw std::runtime_error("C2H streaming buffer not implemented in hardware."); + qdmaInterface->read_buff(reinterpret_cast(localBuffer), 0, size * sizeof(T)); } } else { throw std::runtime_error("Streaming buffer not implemented for this platform."); @@ -192,4 +195,4 @@ std::string StreamingBuffer::getName() const { } } // namespace vrt -#endif // STREAMING_BUFFER_HPP \ No newline at end of file +#endif // VRT_STREAMING_BUFFER_HPP diff --git a/vrt/include/utils/filesystem_cache.hpp b/vrt/include/vrt/utils/filesystem_cache.hpp similarity index 94% rename from vrt/include/utils/filesystem_cache.hpp rename to vrt/include/vrt/utils/filesystem_cache.hpp index cee8b30e..800c52fd 100644 --- a/vrt/include/utils/filesystem_cache.hpp +++ b/vrt/include/vrt/utils/filesystem_cache.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef FILESYSTEM_CACHE_HPP -#define FILESYSTEM_CACHE_HPP +#ifndef VRT_FILESYSTEM_CACHE_HPP +#define VRT_FILESYSTEM_CACHE_HPP #include @@ -74,4 +74,4 @@ class FilesystemCache { static std::filesystem::path getRuntimePath(); }; -#endif // FILESYSTEM_CACHE_HPP +#endif // VRT_FILESYSTEM_CACHE_HPP diff --git a/vrt/include/utils/logger.hpp b/vrt/include/vrt/utils/logger.hpp similarity index 98% rename from vrt/include/utils/logger.hpp rename to vrt/include/vrt/utils/logger.hpp index bafa7fb1..0edcd649 100644 --- a/vrt/include/utils/logger.hpp +++ b/vrt/include/vrt/utils/logger.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef LOGGER_HPP -#define LOGGER_HPP +#ifndef VRT_LOGGER_HPP +#define VRT_LOGGER_HPP #include #include @@ -214,4 +214,4 @@ class Logger { } // namespace vrt -#endif // LOGGER_HPP \ No newline at end of file +#endif // VRT_LOGGER_HPP \ No newline at end of file diff --git a/vrt/include/utils/platform.hpp b/vrt/include/vrt/utils/platform.hpp similarity index 85% rename from vrt/include/utils/platform.hpp rename to vrt/include/vrt/utils/platform.hpp index f6fa647c..13615c74 100644 --- a/vrt/include/utils/platform.hpp +++ b/vrt/include/vrt/utils/platform.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,13 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef PLATFORM_HPP -#define PLATFORM_HPP +/** + * @file platform.hpp + * @brief Platform enum for hardware, emulation, and simulation targets. + */ + +#ifndef VRT_PLATFORM_HPP +#define VRT_PLATFORM_HPP namespace vrt { /** @@ -37,4 +42,4 @@ enum class Platform { } // namespace vrt -#endif // PLATFORM_HPP \ No newline at end of file +#endif // VRT_PLATFORM_HPP \ No newline at end of file diff --git a/vrt/include/utils/zmq_server.hpp b/vrt/include/vrt/utils/zmq_server.hpp similarity index 83% rename from vrt/include/utils/zmq_server.hpp rename to vrt/include/vrt/utils/zmq_server.hpp index 6bde78fa..8ce447b5 100644 --- a/vrt/include/utils/zmq_server.hpp +++ b/vrt/include/vrt/utils/zmq_server.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,8 +18,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef ZMQ_SERVER_HPP -#define ZMQ_SERVER_HPP +#ifndef VRT_ZMQ_SERVER_HPP +#define VRT_ZMQ_SERVER_HPP #include @@ -27,7 +27,7 @@ #include #include -#include "utils/logger.hpp" +#include namespace vrt { @@ -76,6 +76,28 @@ class ZmqServer { */ uint32_t fetchScalar(const std::string& function, const std::string& argIdx); + /** + * @brief Fetches a scalar value from the server with an optional register offset hint. + * + * The offset is used by EMU runtimes that support manifest route disambiguation for split + * registers (e.g., low/high words of 64-bit AXI-Lite values). + * + * @param function The function name associated with the scalar value. + * @param argIdx The argument index or identifier. + * @param offset The kernel register offset being read. + * @return The requested scalar value. + */ + uint32_t fetchScalar(const std::string& function, const std::string& argIdx, uint32_t offset); + + /** + * @brief Reads an emulated kernel register by function instance and register offset. + * + * @param function The kernel instance name. + * @param offset The AXI-Lite register offset. + * @return The 32-bit register value. + */ + uint32_t readRegister(const std::string& function, uint32_t offset); + /** * @brief Fetches a named buffer from the server. * @@ -169,4 +191,4 @@ class ZmqServer { } // namespace vrt -#endif // ZMQ_SERVER_HPP \ No newline at end of file +#endif // VRT_ZMQ_SERVER_HPP diff --git a/vrt/include/api/vrtbin.hpp b/vrt/include/vrt/vrtbin.hpp similarity index 56% rename from vrt/include/api/vrtbin.hpp rename to vrt/include/vrt/vrtbin.hpp index eecca0b0..ac797608 100644 --- a/vrt/include/api/vrtbin.hpp +++ b/vrt/include/vrt/vrtbin.hpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,21 +18,24 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef VRTBIN_HPP -#define VRTBIN_HPP +#ifndef VRT_VRTBIN_HPP +#define VRT_VRTBIN_HPP #include +#include +#include #include #include #include #include #include #include +#include -#include "parser/xml_parser.hpp" -#include "utils/logger.hpp" -#include "utils/platform.hpp" -#include "utils/filesystem_cache.hpp" +#include +#include +#include +#include namespace vrt { @@ -40,14 +43,15 @@ namespace vrt { * @brief Class for handling VRTBIN operations. */ class Vrtbin { - std::string vrtbinPath; ///< Path to the VRTBIN file + std::string vrtbinPath; ///< Path to the VRTBIN tar file std::string systemMapPath; ///< Path to the system map file - std::string versionPath; ///< Path to the version file std::string pdiPath; ///< Path to the PDI file - std::string uuid; ///< UUID of the VRTBIN - std::string tempExtractPath = FilesystemCache::getCachePath(); ///< Temporary extraction path + std::vector pdiPaths; ///< Paths to all discovered PDI files + std::string tempExtractPath; ///< Temporary extraction path std::string emulationExecPath; ///< Path to the emulation executable + std::string emulationManifestPath; ///< Path to emu manifest (if present) std::string simulationExecPath; ///< Path to the simulation executable + std::string utilizationReportPath; ///< Path to utilization report (if present) Platform platform; ///< Platform type /** * @brief Copies a file from source to destination. @@ -55,6 +59,11 @@ class Vrtbin { * @param destination The destination file path. */ void copy(const std::string& source, const std::string& destination); + void discoverPdiFiles(); + std::filesystem::path findExtractedFile(const std::string& filename) const; + std::filesystem::path findExtractedFileByPrefix(const std::string& prefix, + const std::string& extension) const; + static std::string sanitizeForPath(const std::string& input); public: /** @@ -82,15 +91,10 @@ class Vrtbin { std::string getPdiPath(); /** - * @brief Gets the UUID of the VRTBIN. - * @return The UUID of the VRTBIN. + * @brief Gets the paths to all discovered PDI files. + * @return A list of paths to PDI files. */ - std::string getUUID(); - - /** - * @brief Extracts the UUID from the VRTBIN file. - */ - void extractUUID(); + std::vector getPdiPaths(); /** * @brief Gets the emulation executable file. @@ -98,13 +102,45 @@ class Vrtbin { */ std::string getEmulationExec(); + /** + * @brief Gets the emulation manifest file (if present in EMU vrtbin). + * @return The path to the emulation manifest file, or empty string if absent. + */ + std::string getEmulationManifest(); + /** * @brief Gets the simulation executable file. * @return The path to the simulation executable file. */ std::string getSimulationExec(); + + /** + * @brief Gets the path to the utilization report (if present in the vbin). + * @return The path to the utilization report, or empty string if absent. + */ + std::string getUtilizationReportPath() const; + + /** + * @brief Gets the platform type parsed from the system map. + * @return The platform type. + */ + Platform getPlatform() const; + + /** + * @brief Gets the path to the system map last loaded on a bdf. + * @param bdf The bdf to query. + * @return The path to the system map. + */ + static std::string getSystemMapPathFromBdf(const std::string& bdf); + + /** + * @brief Gets the path to the utilization report last loaded on a bdf. + * @param bdf The bdf to query. + * @return The path to the utilization report. + */ + static std::string getUtilizationReportPathFromBdf(const std::string& bdf); }; } // namespace vrt -#endif // VRTBIN_HPP \ No newline at end of file +#endif // VRT_VRTBIN_HPP diff --git a/vrt/scripts/program.tcl b/vrt/scripts/program.tcl deleted file mode 100644 index 835793a4..00000000 --- a/vrt/scripts/program.tcl +++ /dev/null @@ -1,41 +0,0 @@ -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - -if { $argc != 1 } { - puts "Usage: program.tcl " - exit 1 -} - -set program_file [lindex $argv 0] - -open_hw_manager -connect_hw_server -allow_non_jtag -open_hw_target -current_hw_device [get_hw_devices xcv80_1] -refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcv80_1] 0] - -set_property PROBES.FILE {} [get_hw_devices xcv80_1] -set_property FULL_PROBES.FILE {} [get_hw_devices xcv80_1] -set_property PROGRAM.FILE $program_file [get_hw_devices xcv80_1] -program_hw_devices [get_hw_devices xcv80_1] -refresh_hw_device [lindex [get_hw_devices xcv80_1] 0] -close_hw_target -close_hw_manager -exit \ No newline at end of file diff --git a/vrt/scripts/setup_queues.sh b/vrt/scripts/setup_queues.sh deleted file mode 100755 index c2e46f58..00000000 --- a/vrt/scripts/setup_queues.sh +++ /dev/null @@ -1,81 +0,0 @@ -#!/bin/bash - -# ################################################################################################## -# The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software -# and associated documentation files (the "Software"), to deal in the Software without restriction, -# including without limitation the rights to use, copy, modify, merge, publish, distribute, -# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or -# substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT -# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -# ################################################################################################## - - -usage() { - echo "Usage: $0 [--mm ] [--st ] [--dir ]" - exit 1 -} - -if [ $# -lt 1 ]; then - usage -fi - -BDF=$1 -shift - -BDF_PCI="${BDF/.0/.1}" -BDF_QDMA="${BDF:0:2}${BDF:3:2}1" -PATH=$PATH:/usr/local/sbin - -echo "Starting QDMA queue..." >> /var/log/setup_queues.log -echo "Setting qmax..." >> /var/log/setup_queues.log -echo 4096 > /sys/bus/pci/devices/0000\:${BDF_PCI}/qdma/qmax - -while [[ $# -gt 0 ]]; do - key="$1" - case $key in - --mm) - QUEUE_ID="$2" - MM_DIRECTION="$3" - echo "Adding MM queue with ID $QUEUE_ID and direction $MM_DIRECTION..." >> /var/log/setup_queues.log - dma-ctl qdma${BDF_QDMA} q add idx $QUEUE_ID mode mm dir $MM_DIRECTION >> /var/log/setup_queues.log - sleep 1 - dma-ctl qdma${BDF_QDMA} q start idx $QUEUE_ID idx_ringsz 15 dir $MM_DIRECTION >> /var/log/setup_queues.log - sleep 1 - chmod 666 /dev/qdma${BDF_QDMA}-MM-$QUEUE_ID - shift # past argument - shift # past value - shift # past direction - ;; - --st) - QUEUE_ID="$2" - shift # past argument - shift # past value - ;; - --dir) - DIRECTION="$2" - echo "Adding Stream queue with ID $QUEUE_ID and direction $DIRECTION..." >> /var/log/setup_queues.log - dma-ctl qdma${BDF_QDMA} q add idx $QUEUE_ID mode st dir $DIRECTION >> /var/log/setup_queues.log - sleep 1 - dma-ctl qdma${BDF_QDMA} q start idx $QUEUE_ID idx_ringsz 15 dir $DIRECTION >> /var/log/setup_queues.log - sleep 1 - chmod 666 /dev/qdma${BDF_QDMA}-ST-$QUEUE_ID - shift # past argument - shift # past value - ;; - *) - echo "Unknown option $key" - usage - ;; - esac -done \ No newline at end of file diff --git a/vrt/src/allocator/allocator.cpp b/vrt/src/allocator/allocator.cpp index 98c4c809..5dea4d83 100644 --- a/vrt/src/allocator/allocator.cpp +++ b/vrt/src/allocator/allocator.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,247 +18,312 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "allocator/allocator.hpp" +/** + * @file allocator.cpp + * @brief Memory allocator implementation. + */ + +#include + +#include + +#include +#include namespace vrt { -Superblock::Superblock(uint64_t startAddress, uint64_t size) - : startAddress(startAddress), size(size), offset(0) {} - -uint64_t Superblock::allocate(uint64_t size) { - if (!freeList.empty()) { - uint64_t addr = freeList.back(); - freeList.pop_back(); - return addr; +namespace { + +bool matchesAllocation(const UntypedBuffer* buffer, BufferAllocType type, BufferAllocDir dir, + HBMRegion region) { + if (buffer == nullptr) { + return false; } - if (offset + size > this->size) { - throw std::bad_alloc(); + + if (buffer->getAllocType() != type || buffer->getAllocDir() != dir) { + return false; + } + + // Region is meaningful only for explicit HBM allocations. + if (type == BufferAllocType::Hbm) { + return buffer->getHBMRegion() == region; } - uint64_t addr = startAddress + offset; - offset += size; - return addr; + + return true; } -void Superblock::deallocate(uint64_t addr) {} +} // namespace + + +UntypedBuffer::UntypedBuffer(std::nullptr_t) noexcept + : backingBuffer(nullptr), + size(0), + offset(0) +{} -MemoryRange::MemoryRange(uint64_t startAddress, uint64_t size) - : startAddress(startAddress), size(size), offset(0) {} +UntypedBuffer::UntypedBuffer(vrtd::Buffer* backingBuffer, uint64_t size, uint64_t offset) + : backingBuffer(backingBuffer), + // Default to full backing size when size is "max" sentinel. + size(size == std::numeric_limits::max() ? backingBuffer->getSize() : size), + // Offset is relative to the backing buffer base. + offset(offset) +{} -Allocator::Allocator(uint64_t superblockSize) : superblockSize(superblockSize) { - addMemoryRange(MemoryRangeType::HBM, HBM_START, HBM_SIZE); - addMemoryRange(MemoryRangeType::DDR, DDR_START, DDR_SIZE); +UntypedBuffer::UntypedBuffer(const UntypedBuffer& parent, uint64_t size, uint64_t offset) + : backingBuffer(parent.backingBuffer), + // Size defaults to parent size when size is "max" sentinel. + size(size == std::numeric_limits::max() ? parent.size : size), + // Child offsets are relative to the parent slice. + offset(parent.offset + offset) +{} + +UntypedBuffer::~UntypedBuffer() {} + +BufferAllocType UntypedBuffer::getAllocType() const noexcept { + return backingBuffer->getAllocType(); } -void Allocator::addMemoryRange(MemoryRangeType type, uint64_t startAddress, uint64_t size) { - memoryRanges.emplace(type, MemoryRange(startAddress, size)); +BufferAllocDir UntypedBuffer::getAllocDir() const noexcept { + return backingBuffer->getAllocDir(); } -uint64_t Allocator::allocate(uint64_t size, MemoryRangeType type) { - if (type == MemoryRangeType::HBM) { - return allocate(size, type, 0); - } - auto it = memoryRanges.find(type); - if (it == memoryRanges.end()) { - throw std::out_of_range("Invalid memory range type"); +HBMRegion UntypedBuffer::getHBMRegion() const noexcept { + // Only HBM allocations encode a region in the alloc arg. + if (getAllocType() != BufferAllocType::Hbm) { + return HBMRegion::NON_HBM; } + return static_cast(backingBuffer->getAllocArg()); +} - MemoryRange& range = it->second; +uint64_t UntypedBuffer::getSize() const noexcept { + return size; +} - if (size < superblockSize / 2) { - for (auto& superblock : range.superblocks) { - try { - uint64_t addr = superblock.allocate(size); - addrToSuperblock[addr] = &superblock; - return addr; - } catch (const std::bad_alloc&) { - continue; - } - } - if (range.offset + superblockSize > range.size) { - throw std::bad_alloc(); - } - range.superblocks.emplace_back(range.startAddress + range.offset, superblockSize); - range.offset += superblockSize; - uint64_t addr = range.superblocks.back().allocate(size); - addrToSuperblock[addr] = &range.superblocks.back(); - return addr; - } else { - if (!range.freeList.empty()) { - uint64_t addr = range.freeList.back(); - range.freeList.pop_back(); - return addr; - } - if (range.offset + size > range.size) { - throw std::bad_alloc(); - } - uint64_t addr = range.startAddress; - while (addr + size <= range.startAddress + range.size) { - bool isOccupied = std::any_of( - range.usedMemoryBlocks.begin(), range.usedMemoryBlocks.end(), - [addr, size](const std::pair& block) { - return (addr >= block.first && addr < block.first + block.second) || - (addr + size > block.first && addr + size <= block.first + block.second); - }); - - if (!isOccupied) { - range.usedMemoryBlocks.push_back({addr, size}); - return addr; - } +uint64_t UntypedBuffer::getPhysAddr() const noexcept { + // Physical address is backing base + slice offset. + return backingBuffer->getPhysAddr() + offset; +} - addr += size; - } +void* UntypedBuffer::data() const noexcept { + // Host pointer is backing base + slice offset. + return static_cast(backingBuffer->data()) + offset; +} - throw std::bad_alloc(); +void UntypedBuffer::syncToDevice(uint64_t offset, uint64_t size) { + // Clamp sync size and validate bounds against this slice. + uint64_t syncSize = (size == std::numeric_limits::max()) ? this->size - offset : size; + if (offset + syncSize > this->size) { + throw std::out_of_range("Sync range exceeds buffer size"); } + // Forward to backing buffer with adjusted offset. + backingBuffer->syncToDevice(this->offset + offset, syncSize); } -void Allocator::deallocate(uint64_t addr) { - auto it = addrToSuperblock.find(addr); - if (it != addrToSuperblock.end()) { - it->second->deallocate(addr); - addrToSuperblock.erase(it); - } else { - for (auto& [type, range] : memoryRanges) { - if (addr >= range.startAddress && addr < range.startAddress + range.size) { - range.freeList.push_back(addr); - return; - } - } +void UntypedBuffer::syncToHost(uint64_t offset, uint64_t size) { + // Clamp sync size and validate bounds against this slice. + uint64_t syncSize = (size == std::numeric_limits::max()) ? this->size - offset : size; + if (offset + syncSize > this->size) { + throw std::out_of_range("Sync range exceeds buffer size"); } + // Forward to backing buffer with adjusted offset. + backingBuffer->syncFromDevice(this->offset + offset, syncSize); } -uint64_t Allocator::allocate(uint64_t size, MemoryRangeType type, uint8_t port) { - auto it = memoryRanges.find(type); - if (it == memoryRanges.end()) { - throw std::out_of_range("Invalid memory range type"); - } +bool UntypedBuffer::operator==(std::nullptr_t) const noexcept { + return backingBuffer == nullptr; +} + +bool UntypedBuffer::operator!=(std::nullptr_t) const noexcept { + return backingBuffer != nullptr; +} - if (port > 31) { - throw std::out_of_range("Invalid port number"); +bool operator==(std::nullptr_t, const UntypedBuffer& buffer) noexcept { + return buffer.backingBuffer == nullptr; +} + +bool operator!=(std::nullptr_t, const UntypedBuffer& buffer) noexcept { + return buffer.backingBuffer != nullptr; +} + +Block::Block() = default; +Block::~Block() = default; + +LargeBlock::LargeBlock(vrtd::Device& device, BufferAllocType type, BufferAllocDir dir, uint64_t size, HBMRegion region) + // Back large blocks with a dedicated device buffer. + : backingBuffer(std::make_unique( + device.openBuffer(type, size, static_cast(region), dir))), + untypedBuffer(std::make_unique(backingBuffer.get(), size)) {} + +LargeBlock::~LargeBlock() = default; + +UntypedBuffer *LargeBlock::getUntypedBuffer() const noexcept { + return untypedBuffer.get(); +} + +MediumBlock::MediumBlock(LargeBlockSuperblock *backingSuperblock, UntypedBuffer untypedBuffer) + // Medium blocks are carved out of a large-block superblock. + : backingBlockSuperblock(backingSuperblock), + untypedBuffer(std::make_unique(untypedBuffer)) {} + +MediumBlock::~MediumBlock() { + // Return the slice to the backing superblock. + backingBlockSuperblock->deallocate(*untypedBuffer); +} + +UntypedBuffer *MediumBlock::getUntypedBuffer() const noexcept { + return untypedBuffer.get(); +} + +SmallBlock::SmallBlock(MediumBlockSuperblock *backingBlockSuperblock, UntypedBuffer untypedBuffer) + // Small blocks are carved out of a medium-block superblock. + : backingBlockSuperblock(backingBlockSuperblock), + untypedBuffer(std::make_unique(untypedBuffer)) {} + +SmallBlock::~SmallBlock() { + // Return the slice to the backing superblock. + backingBlockSuperblock->deallocate(*untypedBuffer); +} + +UntypedBuffer *SmallBlock::getUntypedBuffer() const noexcept { + return untypedBuffer.get(); +} + +LargeBlockSuperblock::LargeBlockSuperblock(vrtd::Device& device, BufferAllocType type, BufferAllocDir dir, uint64_t size, HBMRegion region) + : LargeBlock(device, type, dir, size, region) { + Buddy::seed(*getUntypedBuffer(), + "Size too small for LargeBlockSuperblock", + "LargeBlockSuperblock size exceeds maximum bucket size"); +} + +LargeBlockSuperblock::~LargeBlockSuperblock() { + if (!isFree()) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "LargeBlockSuperblock destroyed while not all memory was deallocated"); + std::abort(); } +} - if (type != MemoryRangeType::HBM) { - return allocate(size, type); +UntypedBuffer LargeBlockSuperblock::allocate(uint64_t size) { + return Buddy::allocate(size, "Size too small for LargeBlockSuperblock"); +} + +void LargeBlockSuperblock::deallocate(UntypedBuffer buffer) { + Buddy::deallocate(*getUntypedBuffer(), buffer, + "Size too small for LargeBlockSuperblock", + "Buffer does not belong to this LargeBlockSuperblock"); +} + +bool LargeBlockSuperblock::isFree() const { + return Buddy::isFree(*getUntypedBuffer(), "Size too small for LargeBlockSuperblock"); +} + +MediumBlockSuperblock::MediumBlockSuperblock(LargeBlockSuperblock *backingSuperblock, UntypedBuffer untypedBuffer) + : MediumBlock(backingSuperblock, untypedBuffer) { + Buddy::seed(*getUntypedBuffer(), + "Size too small for MediumBlockSuperblock", + "MediumBlockSuperblock size exceeds maximum bucket size"); +} + +MediumBlockSuperblock::~MediumBlockSuperblock() { + if (!isFree()) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "MediumBlockSuperblock destroyed while not all memory was deallocated"); + std::abort(); } +} - MemoryRange& range = it->second; - uint64_t portBaseAddress = HBM_START + port * HBM_PORT_SIZE; - uint64_t portEndAddress = - portBaseAddress + 2 * HBM_PORT_SIZE * 8; // allow moving to next port (aligned at 64bit) +UntypedBuffer MediumBlockSuperblock::allocate(uint64_t size) { + return Buddy::allocate(size, "Size too small for MediumBlockSuperblock"); +} + +void MediumBlockSuperblock::deallocate(UntypedBuffer buffer) { + Buddy::deallocate(*getUntypedBuffer(), buffer, + "Size too small for MediumBlockSuperblock", + "Buffer does not belong to this MediumBlockSuperblock"); +} - if (size < superblockSize / 2) { - for (auto& superblock : range.superblocks) { - if (superblock.startAddress < portBaseAddress || - superblock.startAddress >= portBaseAddress + HBM_PORT_SIZE) { +bool MediumBlockSuperblock::isFree() const { + return Buddy::isFree(*getUntypedBuffer(), "Size too small for MediumBlockSuperblock"); +} + +Allocator::Allocator() = default; +Allocator::~Allocator() = default; + +std::unique_ptr Allocator::allocate(vrtd::Device& device, BufferAllocType type, BufferAllocDir dir, uint64_t size, HBMRegion region) { + if (size > LargeBlockSuperblock::MAX_SIZE) { + return std::make_unique(device, type, dir, size, region); + } + + if (size > MediumBlockSuperblock::MAX_SIZE) { + for (auto& superblock : largeBlockSuperblocks) { + if (!matchesAllocation(superblock->getUntypedBuffer(), type, dir, region)) { continue; } try { - uint64_t addr = superblock.allocate(size); - addrToSuperblock[addr] = &superblock; - return addr; + UntypedBuffer buffer = superblock->allocate(size); + return std::make_unique(superblock.get(), buffer); } catch (const std::bad_alloc&) { continue; } } - if (range.offset + superblockSize > range.size) { - throw std::bad_alloc(); - } - uint64_t sbs = superblockSize; - // Check if the range is already occupied in usedMemoryBlocks - bool isOccupied = - std::any_of(range.usedMemoryBlocks.begin(), range.usedMemoryBlocks.end(), - [portBaseAddress, sbs](const std::pair& block) { - return (portBaseAddress >= block.first && - portBaseAddress < block.first + block.second) || - (portBaseAddress + sbs > block.first && - portBaseAddress + sbs <= block.first + block.second); - }); - - if (!isOccupied) { - // Allocate a new superblock from portBaseAddress - range.superblocks.emplace_back(portBaseAddress, superblockSize); - uint64_t addr = range.superblocks.back().allocate(size); - addrToSuperblock[addr] = &range.superblocks.back(); - range.usedMemoryBlocks.push_back({addr, superblockSize}); - return addr; - } else { - // Find the next free block - uint64_t nextFreeAddress = portBaseAddress; - for (const auto& block : range.usedMemoryBlocks) { - if (nextFreeAddress >= block.first && - nextFreeAddress < block.first + block.second) { - nextFreeAddress = block.first + block.second; - } - } - // Check if the next free block is within the range - if (nextFreeAddress + superblockSize <= range.startAddress + range.size) { - range.superblocks.emplace_back(nextFreeAddress, superblockSize); - uint64_t addr = range.superblocks.back().allocate(size); - addrToSuperblock[addr] = &range.superblocks.back(); - range.usedMemoryBlocks.push_back({addr, size}); - return addr; - } else { - throw std::bad_alloc(); - } - } - - } else { - if (!range.freeList.empty()) { - auto it = - std::find_if(range.freeList.begin(), range.freeList.end(), - [portBaseAddress](uint64_t addr) { return addr > portBaseAddress; }); + largeBlockSuperblocks.emplace_back( + std::make_unique(device, type, dir, LargeBlockSuperblock::MAX_SIZE, region)); + UntypedBuffer buffer = largeBlockSuperblocks.back()->allocate(size); + return std::make_unique(largeBlockSuperblocks.back().get(), buffer); + } - if (it != range.freeList.end()) { - uint64_t foundAddress = *it; - range.freeList.erase(it); // Remove the allocated address from the free list - return foundAddress; - } + for (auto& superblock : mediumBlockSuperblocks) { + if (!matchesAllocation(superblock->getUntypedBuffer(), type, dir, region)) { + continue; } - // Search in usedMemoryBlocks for the next free address within the port range - uint64_t nextFreeAddress = portBaseAddress; - for (const auto& block : range.usedMemoryBlocks) { - if (block.first + block.second >= portBaseAddress && - block.first + block.second < portEndAddress) { - nextFreeAddress = block.first + block.second; - } + try { + UntypedBuffer buffer = superblock->allocate(size); + return std::make_unique(superblock.get(), buffer); + } catch (const std::bad_alloc&) { + continue; } + } - // Check if the next free block is within the port range - if (nextFreeAddress + size <= portEndAddress) { - range.usedMemoryBlocks.push_back( - {nextFreeAddress, size}); // Keep track of the used block - return nextFreeAddress; + for (auto& superblock : largeBlockSuperblocks) { + if (!matchesAllocation(superblock->getUntypedBuffer(), type, dir, region)) { + continue; } - - // Allocate from portBaseAddress - uint64_t addr = portBaseAddress; - while (addr + size <= range.startAddress + range.size) { - // Check if the address range is occupied - bool isOccupied = std::any_of( - range.usedMemoryBlocks.begin(), range.usedMemoryBlocks.end(), - [addr, size](const std::pair& block) { - return (addr >= block.first && addr < block.first + block.second) || - (addr + size > block.first && addr + size <= block.first + block.second); - }); - - if (!isOccupied) { - range.usedMemoryBlocks.push_back({addr, size}); // Keep track of the used block - return addr; - } - - addr += size; // Move to the next block + try { + UntypedBuffer backing = superblock->allocate(MediumBlockSuperblock::MAX_SIZE); + mediumBlockSuperblocks.emplace_back( + std::make_unique(superblock.get(), backing)); + UntypedBuffer buffer = mediumBlockSuperblocks.back()->allocate(size); + return std::make_unique(mediumBlockSuperblocks.back().get(), buffer); + } catch (const std::bad_alloc&) { + continue; } - - throw std::bad_alloc(); } + + largeBlockSuperblocks.emplace_back( + std::make_unique(device, type, dir, LargeBlockSuperblock::MAX_SIZE, region)); + UntypedBuffer backing = largeBlockSuperblocks.back()->allocate(MediumBlockSuperblock::MAX_SIZE); + mediumBlockSuperblocks.emplace_back( + std::make_unique(largeBlockSuperblocks.back().get(), backing)); + UntypedBuffer buffer = mediumBlockSuperblocks.back()->allocate(size); + return std::make_unique(mediumBlockSuperblocks.back().get(), buffer); } -uint64_t Allocator::getSize(MemoryRangeType type) const { - auto it = memoryRanges.find(type); - if (it == memoryRanges.end()) { - throw std::out_of_range("Invalid memory range type"); - } - return it->second.size; +void Allocator::deallocate(std::unique_ptr block) { + block.reset(); + + mediumBlockSuperblocks.erase( + std::remove_if(mediumBlockSuperblocks.begin(), mediumBlockSuperblocks.end(), + [](const std::unique_ptr& superblock) { + return superblock->isFree(); + }), + mediumBlockSuperblocks.end()); + + largeBlockSuperblocks.erase( + std::remove_if(largeBlockSuperblocks.begin(), largeBlockSuperblocks.end(), + [](const std::unique_ptr& superblock) { + return superblock->isFree(); + }), + largeBlockSuperblocks.end()); } } // namespace vrt diff --git a/vrt/src/api/device.cpp b/vrt/src/api/device.cpp deleted file mode 100644 index 18ba7d39..00000000 --- a/vrt/src/api/device.cpp +++ /dev/null @@ -1,410 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "api/device.hpp" - -#include "utils/filesystem_cache.hpp" - -namespace vrt { - -Device::Device(const std::string& bdf, const std::string& vrtbinPath, bool program, - ProgramType programType) - : vrtbin(vrtbinPath, bdf), clkWiz(nullptr, "", 0, 0, 0), pcieHandler(bdf) { - lockPcieDevice(bdf); - this->bdf = bdf; - this->allocator = new Allocator(4096); - this->systemMap = this->vrtbin.getSystemMapPath(); - this->pdiPath = this->vrtbin.getPdiPath(); - this->programType = programType; - this->qdmaIntf = QdmaIntf(bdf); - this->zmqServer = std::make_shared(); - findPlatform(); - if (platform == Platform::HARDWARE) { - createAmiDev(); - findVrtbinType(); - if (program) { - programDevice(); - } - parseSystemMap(); - this->clkWiz.setRateHz(200000000, false); - } else if (platform == Platform::EMULATION) { - parseSystemMap(); - std::string emulationExecPath = this->vrtbin.getEmulationExec() + " >/dev/null"; - - std::thread([emulationExecPath]() { std::system(emulationExecPath.c_str()); }).detach(); - - } else { - parseSystemMap(); - std::string simulationExecPath = this->vrtbin.getSimulationExec() + " >/dev/null"; - - std::thread([simulationExecPath]() { std::system(simulationExecPath.c_str()); }).detach(); - Json::Value command; - command["command"] = "start"; - zmqServer->sendCommand(command); - } - for (auto& qdmaCon : qdmaConnections) { - qdmaIntfs.emplace_back(new QdmaIntf(bdf, qdmaCon.getQid())); - } -} - -Device::~Device() { - unlockPcieDevice(bdf); -} - -void Device::parseSystemMap() { - XMLParser parser(systemMap); - parser.parseXML(); - clockFreq = parser.getClockFrequency(); - this->platform = parser.getPlatform(); - this->clkWiz = ClkWiz(dev, "clk_wiz", CLK_WIZ_BASE, CLK_WIZ_OFFSET, clockFreq); - this->clkWiz.setPlatform(platform); - kernels = parser.getKernels(); - for (auto& kernel : kernels) { - kernel.second.setDevice(dev); - } - this->qdmaConnections = parser.getQdmaConnections(); -} - -Kernel Device::getKernel(const std::string& name) { return kernels[name]; } - -void Device::cleanup() { - if (platform == Platform::HARDWARE) { - for (auto qdmaIntf_ : qdmaIntfs) { - delete qdmaIntf_; - } - ami_dev_delete(&dev); - unlockPcieDevice(bdf); - } else if (platform == Platform::EMULATION || platform == Platform::SIMULATION) { - Json::Value exit; - exit["command"] = "exit"; - zmqServer->sendCommand(exit); - } -} - -std::string Device::getBdf() { return bdf; } - -void Device::programDevice() { - if (vrtbinType == VrtbinType::FLAT) { - if (programType == ProgramType::FLASH) { - char current_uuid[33]; - std::string logic_uuid = vrtbin.getUUID(); - int found_current_uuid = AMI_STATUS_ERROR; - found_current_uuid = ami_dev_read_uuid(dev, current_uuid); - if (found_current_uuid == AMI_STATUS_OK) { - std::string current_uuid_str(current_uuid); - current_uuid_str = current_uuid_str.substr(0, 32); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Current UUID: {}", - current_uuid_str); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "New UUID: {}", - logic_uuid); - if (current_uuid_str == logic_uuid) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Device already programmed with the same image"); - bootDevice(); - return; - } - } - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Programming device {} in FLASH mode...This might take a while", - bdf); - if (ami_prog_download_pdi(dev, pdiPath.c_str(), 0, 1, nullptr, false) != - AMI_STATUS_OK) { - throw std::runtime_error("Failed to program device"); - } - bootDevice(); - } else { - int found_current_uuid = AMI_STATUS_ERROR; - char current_uuid[33]; - std::string logic_uuid = vrtbin.getUUID(); - found_current_uuid = ami_dev_read_uuid(dev, current_uuid); - if (found_current_uuid == AMI_STATUS_OK) { - std::string current_uuid_str(current_uuid); - current_uuid_str = current_uuid_str.substr(0, 32); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Current UUID: {}", - current_uuid_str); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "New UUID: {}", - logic_uuid); - if (current_uuid_str == logic_uuid) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Device already programmed with the same image"); - bootDevice(); - return; - } - } - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Programming device {} in JTAG mode...This might take a while", bdf); - std::string cmd = JTAG_PROGRAM_PATH + pdiPath; - system(cmd.c_str()); - bootDevice(); - } - } else if (vrtbinType == VrtbinType::SEGMENTED) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Programming device {} in SEGMENTED mode...This might take a while", - bdf); - char current_uuid[33]; - std::string logic_uuid = vrtbin.getUUID(); - int found_current_uuid = AMI_STATUS_ERROR; - found_current_uuid = ami_dev_read_uuid(dev, current_uuid); - if (found_current_uuid == AMI_STATUS_OK) { - std::string current_uuid_str(current_uuid); - current_uuid_str = current_uuid_str.substr(0, 32); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Current UUID: {}", - current_uuid_str); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "New UUID: {}", - logic_uuid); - if (current_uuid_str == logic_uuid) { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Device already programmed with the same image"); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Refreshing qdma handle"); - pcieHandler.execute(PcieDriverHandler::Command::HOTPLUG); - XMLParser parser(systemMap); - parser.parseXML(); - auto qdmaConns = parser.getQdmaConnections(); - std::string cmd = "sudo bash " + std::string(QDMA_SETUP_QUEUES) + bdf + " --mm 0 bi"; - for (auto& qdmaConn : qdmaConns) { - uint32_t qid = qdmaConn.getQid(); - std::string direction = - (qdmaConn.getDirection() == StreamDirection::HOST_TO_DEVICE ? "h2c" - : "c2h"); - cmd += " --st " + std::to_string(qid) + " --dir " + direction; - } - system(cmd.c_str()); - return; - } - } - bootDevice(); - } -} - -void Device::bootDevice() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Booting device..."); - if (vrtbinType == VrtbinType::FLAT) { - if (programType == ProgramType::FLASH) { - int ret = ami_prog_device_boot(&dev, 1); - if (ret != AMI_STATUS_OK && geteuid() == 0) { // for root users this should not matter - throw std::runtime_error("Failed to boot device"); - } else { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Booting into PDI..."); - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Writing PMC GPIO..."); - ami_mem_bar_write(dev, 0, 0x1040000, 1); - destroyAmiDev(); - pcieHandler.execute(PcieDriverHandler::Command::REMOVE); - pcieHandler.execute(PcieDriverHandler::Command::TOGGLE_SBR); - usleep(5000000); - pcieHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieHandler.execute(PcieDriverHandler::Command::HOTPLUG); - createAmiDev(); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "New PDI booted successfully"); - XMLParser parser(systemMap); - parser.parseXML(); - auto qdmaConns = parser.getQdmaConnections(); - std::string cmd = "sudo bash " + std::string(QDMA_SETUP_QUEUES) + bdf + " --mm 0 bi"; - for (auto& qdmaConn : qdmaConns) { - uint32_t qid = qdmaConn.getQid(); - std::string direction = - (qdmaConn.getDirection() == StreamDirection::HOST_TO_DEVICE ? "h2c" - : "c2h"); - cmd += " --st " + std::to_string(qid) + " --dir " + direction; - } - system(cmd.c_str()); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "QDMA queues setup successfully"); - } - } else { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Booting into PDI..."); - destroyAmiDev(); - pcieHandler.execute(PcieDriverHandler::Command::REMOVE); - pcieHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieHandler.execute(PcieDriverHandler::Command::HOTPLUG); - createAmiDev(); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "New PDI booted successfully"); - XMLParser parser(systemMap); - parser.parseXML(); - auto qdmaConns = parser.getQdmaConnections(); - std::string cmd = "sudo bash " + std::string(QDMA_SETUP_QUEUES) + bdf + " --mm 0 bi"; - for (auto& qdmaConn : qdmaConns) { - uint32_t qid = qdmaConn.getQid(); - std::string direction = - (qdmaConn.getDirection() == StreamDirection::HOST_TO_DEVICE ? "h2c" : "c2h"); - cmd += " --st " + std::to_string(qid) + " --dir " + direction; - } - system(cmd.c_str()); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "QDMA queues setup successfully"); - } - } else if (vrtbinType == VrtbinType::SEGMENTED) { - int ret = ami_prog_device_boot( - &dev, 1); // make sure we are on partition one, this contains the segmented base pdi - if (ret != AMI_STATUS_OK && geteuid() == 0) { - throw std::runtime_error("Failed to boot into base segmented PDI"); - } else { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Booting into base segmented PDI..."); - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Writing PMC GPIO..."); - // PMC GPIO. this is needed for reset PDI into partition 1 - ami_mem_bar_write(dev, 0, 0x1040000, 1); - destroyAmiDev(); - pcieHandler.execute(PcieDriverHandler::Command::REMOVE); - pcieHandler.execute(PcieDriverHandler::Command::TOGGLE_SBR); - usleep(5000000); - pcieHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieHandler.execute(PcieDriverHandler::Command::HOTPLUG); - createAmiDev(); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Base segmented PDI booted successfully"); - if (ami_prog_download_pdi(dev, pdiPath.c_str(), 0, 1, nullptr, true) != AMI_STATUS_OK) { - throw std::runtime_error("Failed to program partial device"); - } - destroyAmiDev(); - pcieHandler.execute(PcieDriverHandler::Command::REMOVE); - usleep(2 * DELAY_PARTIAL_BOOT); // enough time for the device to reset - pcieHandler.execute(PcieDriverHandler::Command::RESCAN); - pcieHandler.execute(PcieDriverHandler::Command::HOTPLUG); - createAmiDev(); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "PLD PDI booted successfully"); - XMLParser parser(systemMap); - parser.parseXML(); - auto qdmaConns = parser.getQdmaConnections(); - std::string cmd = "sudo bash " + std::string(QDMA_SETUP_QUEUES) + bdf + " --mm 0 bi"; - for (auto& qdmaConn : qdmaConns) { - uint32_t qid = qdmaConn.getQid(); - std::string direction = - (qdmaConn.getDirection() == StreamDirection::HOST_TO_DEVICE ? "h2c" : "c2h"); - cmd += " --st " + std::to_string(qid) + " --dir " + direction; - } - system(cmd.c_str()); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "QDMA queues setup successfully"); - } - } -} - -void Device::getNewHandle() { - ami_device* new_dev = NULL; - int ret = AMI_STATUS_ERROR; - ret = ami_dev_find_next(&new_dev, AMI_PCI_BUS(pci_bdf), AMI_PCI_DEV(pci_bdf), - AMI_PCI_FUNC(pci_bdf), NULL); - if (ret == AMI_STATUS_OK) { - if (ami_sensor_discover(new_dev) == AMI_STATUS_OK) { - dev = new_dev; - } else { - throw std::runtime_error("Failed to discover sensors"); - } - } else { - throw std::runtime_error("Failed to find device"); - } -} - -void Device::createAmiDev() { - if (ami_dev_find(bdf.c_str(), &dev) != AMI_STATUS_OK) { - throw std::runtime_error("Failed to find device " + bdf); - } - ami_dev_get_pci_bdf(dev, &pci_bdf); - if (ami_dev_request_access(dev) != AMI_STATUS_OK) { - throw std::runtime_error("Failed to request elevated access to device"); - } -} - -void Device::destroyAmiDev() { ami_dev_delete(&dev); } - -void Device::setFrequency(uint64_t freq) { - if (platform == Platform::HARDWARE) { - if (freq > clockFreq) { - utils::Logger::log(utils::LogLevel::WARN, __PRETTY_FUNCTION__, - "Setting frequency {}, which is higher than max frequency {}", freq, - clockFreq); - } - clkWiz.setRateHz(200000000); - } -} - -uint64_t Device::getFrequency() { - if (platform == Platform::HARDWARE) { - return clkWiz.getClockRate(); - } else { - return 0; - } -} - -uint64_t Device::getMaxFrequency() { - if (platform == Platform::HARDWARE) { - return clockFreq; - } else { - return 0; - } -} - -ami_device* Device::getAmiDev() { return dev; } - -void Device::findVrtbinType() { - XMLParser parser(systemMap); - parser.parseXML(); - this->vrtbinType = parser.getVrtbinType(); -} - -void Device::findPlatform() { - XMLParser parser(systemMap); - parser.parseXML(); - this->platform = parser.getPlatform(); -} - -Platform Device::getPlatform() { return platform; } - -std::shared_ptr Device::getZmqServer() { return zmqServer; } - -std::vector Device::getQdmaConnections() { return qdmaConnections; } - -Allocator* Device::getAllocator() { return allocator; } - -std::vector Device::getQdmaInterfaces() { return qdmaIntfs; } - -void Device::lockPcieDevice(const std::string& bdf) { - std::string lockFile = FilesystemCache::getRuntimePath() / ("pcie_device_" + bdf + ".lock"); - int fd = open(lockFile.c_str(), O_CREAT | O_WRONLY, 0666); - if (fd == -1) { - throw std::runtime_error("Failed to lock PCIe device " + bdf); - } - int ret = flock(fd, LOCK_EX | LOCK_NB); - if (ret < 0) { - close(fd); - throw std::runtime_error("Device " + bdf + " locked by another instance"); - } -} - -void Device::unlockPcieDevice(const std::string& bdf) { - std::string lockFile = FilesystemCache::getRuntimePath() / ("pcie_device_" + bdf + ".lock"); - int fd = open(lockFile.c_str(), O_WRONLY, 0666); - if (fd == -1) { - throw std::runtime_error("Failed to lock PCIe device " + bdf); - } - int ret = flock(fd, LOCK_UN); - if (ret < 0) { - throw std::runtime_error("Device " + bdf + " cannot be unlocked"); - } - close(fd); -} - -} // namespace vrt diff --git a/vrt/src/api/kernel.cpp b/vrt/src/api/kernel.cpp deleted file mode 100644 index 3aaa6e8f..00000000 --- a/vrt/src/api/kernel.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "api/kernel.hpp" - -#include "api/device.hpp" - -namespace vrt { - -Kernel::Kernel(ami_device* device, const std::string& name, uint64_t baseAddr, uint64_t range, - const std::vector& registers) { - this->dev = device; - this->name = name; - this->baseAddr = baseAddr; - this->range = range; - this->registers = registers; -} - -Kernel::Kernel(Device& device, const std::string& kernelName) - : Kernel(device.getKernel(kernelName)) { - deviceBdf = device.getBdf(); - this->platform = device.getPlatform(); - this->server = device.getZmqServer(); -} - -void Kernel::write(uint32_t offset, uint32_t value) { - if (platform == Platform::HARDWARE) { - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Writing to device {} kernel: {} at offset: {x} value: {x}", deviceBdf, - name, offset, value); - uint32_t* buf = (uint32_t*)calloc(1, sizeof(uint32_t)); - *buf = value; - if (buf) { - int ret = ami_mem_bar_write(dev, bar, baseAddr - BASE_BAR_ADDR + offset, buf[0]); - if (ret != AMI_STATUS_OK) { - throw std::runtime_error("Failed to write to device"); - } - } - free(buf); - } else if (platform == Platform::SIMULATION) { - server->sendScalar(baseAddr + offset, value); - } -} - -uint32_t Kernel::read(uint32_t offset) { - if (platform == Platform::HARDWARE) { - if (offset != 0) - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Reading from device {} kernel: {} at offset: {x}", deviceBdf, name, - offset); - uint32_t* buf = (uint32_t*)calloc(1, sizeof(uint32_t)); - if (buf) { - int ret = ami_mem_bar_read(dev, bar, baseAddr - BASE_BAR_ADDR + offset, &buf[0]); - if (ret != AMI_STATUS_OK) { - throw std::runtime_error("Failed to read from device"); - } - } - uint32_t value = buf[0]; - free(buf); - return value; - } else if (platform == Platform::EMULATION) { - currentRegisterIndex = 4; - std::size_t argIdx = 0; - while (currentRegisterIndex < registers.size()) { - std::regex re(".*_\\d+$"); - if (std::regex_match(registers.at(currentRegisterIndex).getRegisterName(), re)) { - currentRegisterIndex += 2; - } else { - if (registers.at(currentRegisterIndex).getOffset() == offset) { - return server->fetchScalar(name, "arg" + std::to_string(argIdx)); - } - currentRegisterIndex++; - } - argIdx++; - } - } else if (platform == Platform::SIMULATION) { - return server->fetchScalarSim(baseAddr + offset); - } - return 0; -} - -void Kernel::setDevice(ami_device* device) { this->dev = device; } - -void Kernel::wait() { - if (platform == Platform::EMULATION) { - return; - } - while (read(0x00) == 1 || read(0x00) == 0x81) { - } -} - -void Kernel::startKernel(bool autorestart) { - if (autorestart) { - write(0x00, 0x81); - } else { - write(0x00, 0x01); - } -} - -Kernel::~Kernel() {} - -void Kernel::setPlatform(Platform platform) { this->platform = platform; } - -void Kernel::writeBatch() { - uint32_t noOfPhysicalRegisters = - (registers.at(registers.size() - 1).getOffset() + sizeof(uint32_t)) / sizeof(uint32_t); - uint32_t* buf = (uint32_t*)calloc(noOfPhysicalRegisters, sizeof(uint32_t)); - for (std::size_t i = 4; i < noOfPhysicalRegisters; i++) { - buf[i] = registerMap[i * sizeof(uint32_t)]; - // buf[i] = registerMap[registers.at(i).getOffset()]; - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Kernel {}, reg at offset {x}, value: {x}", name, i * sizeof(uint32_t), - buf[i]); - } - ami_mem_bar_write_range(dev, bar, baseAddr - BASE_BAR_ADDR, noOfPhysicalRegisters, buf); - free(buf); -} -std::string Kernel::getName() const { return name; } - -} // namespace vrt diff --git a/vrt/src/api/vrtbin.cpp b/vrt/src/api/vrtbin.cpp deleted file mode 100644 index caaef2c3..00000000 --- a/vrt/src/api/vrtbin.cpp +++ /dev/null @@ -1,143 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "api/vrtbin.hpp" - -namespace vrt { -Vrtbin::Vrtbin(std::string vrtbinPath, const std::string& bdf) { - this->vrtbinPath = vrtbinPath; - if (!std::filesystem::exists(vrtbinPath)) { - throw std::runtime_error(vrtbinPath + " does not exist"); - } - char* ami_home_cstr = getenv("AMI_HOME"); - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "AMI_HOME: {}", ami_home_cstr); - if (ami_home_cstr == nullptr) { - throw std::runtime_error("AMI_HOME environment variable not set"); - } - std::string ami_home(getenv("AMI_HOME")); - if (!ami_home.empty() && ami_home.back() != '/') { - ami_home += '/'; - } - std::string cmd = "mkdir -p " + ami_home + bdf; - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Running command: {}", cmd); - system(cmd.c_str()); - this->systemMapPath = ami_home + bdf + "/system_map.xml"; - extract(); - std::string tempSystemMapPath = tempExtractPath + "/system_map.xml"; - XMLParser parser(tempSystemMapPath); - parser.parseXML(); - this->platform = parser.getPlatform(); - if (this->platform == Platform::HARDWARE) { - this->versionPath = ami_home + bdf + "/version.json"; - this->pdiPath = tempExtractPath + "/design.pdi"; - copy(tempExtractPath + "/system_map.xml", systemMapPath); - copy(tempExtractPath + "/version.json", versionPath); - copy(tempExtractPath + "/report_utilization.xml", - ami_home + bdf + "/report_utilization.xml"); - extractUUID(); - } else if (this->platform == Platform::EMULATION) { - copy(tempExtractPath + "/system_map.xml", systemMapPath); - emulationExecPath = tempExtractPath + "/vpp_emu"; - - } else { - copy(tempExtractPath + "/system_map.xml", systemMapPath); - simulationExecPath = tempExtractPath + "/vpp_sim"; - } -} - -void Vrtbin::extract() { - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Extracting vrtbin: {}", - vrtbinPath); - std::string command = "tar -xvf " + vrtbinPath + " -C " + tempExtractPath + " 2>&1"; - std::array buffer; - std::string result; - - std::unique_ptr pipe(popen(command.c_str(), "r"), pclose); - if (!pipe) { - throw std::runtime_error("popen() failed!"); - } - - while (fgets(buffer.data(), buffer.size(), pipe.get()) != nullptr) { - result += buffer.data(); - } -} - -void Vrtbin::copy(const std::string& source, const std::string& destination) { - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Copying file {} to {}", source, - destination); - std::ifstream src(source, std::ios::binary); - if (!src) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Error opening source file: {}", source); - throw std::runtime_error("Error opening source file"); - } - - std::ofstream dest(destination, std::ios::binary); - if (!dest) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Error opening destination file: {}", destination); - throw std::runtime_error("Error opening destination file"); - } - - dest << src.rdbuf(); - - if (!src) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Error reading from source file: {}", source); - throw std::runtime_error("Error reading from source file"); - } - - if (!dest) { - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Error writing to destination file: {}", destination); - throw std::runtime_error("Error writing to destination file"); - } -} - -std::string Vrtbin::getSystemMapPath() { return systemMapPath; } -std::string Vrtbin::getPdiPath() { return pdiPath; } - -std::string Vrtbin::getUUID() { return uuid; } - -void Vrtbin::extractUUID() { - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Extracting UUID from version.json"); - std::ifstream jsonFile(tempExtractPath + "/version.json"); - if (!jsonFile.is_open()) { - uuid = ""; - } - std::string line; - while (std::getline(jsonFile, line)) { - std::size_t pos = line.find("\"logic_uuid\":"); - if (pos != std::string::npos) { - std::size_t start = line.find("\"", pos + 13) + 1; - std::size_t end = line.find("\"", start); - uuid = line.substr(start, end - start); - break; - } - } - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "UUID is: {}", uuid); - jsonFile.close(); -} - -std::string Vrtbin::getEmulationExec() { return emulationExecPath; } - -std::string Vrtbin::getSimulationExec() { return simulationExecPath; } -} // namespace vrt \ No newline at end of file diff --git a/vrt/src/device.cpp b/vrt/src/device.cpp new file mode 100644 index 00000000..5b709f55 --- /dev/null +++ b/vrt/src/device.cpp @@ -0,0 +1,442 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file device.cpp + * @brief Device class implementation. + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +namespace vrt { +namespace impl { + +namespace { + +// Normalize a user-supplied BDF to board-level "DDDD:BB:DD" for vrtd lookup. +// Strips function digit (.F) if present, prepends domain 0000: if missing. +std::string normalizeBdfForVrtd(const std::string& bdf) { + std::string result = bdf; + + // Strip function digit + auto dot = result.rfind('.'); + if (dot != std::string::npos) { + std::cerr << "Warning: BDF '" << bdf + << "' contains a PF function number; " + << "stripping " << result.substr(dot) + << " — use board address instead" + << std::endl; + result = result.substr(0, dot); + } + + // Prepend domain if missing (only one colon means short BDF) + const auto firstColon = result.find(':'); + const auto lastColon = result.rfind(':'); + if (firstColon == std::string::npos || firstColon == lastColon) { + result = "0000:" + result; + } + return result; +} + +// Normalize a user-supplied BDF to board-level "BB:DD" (no domain, no function). +std::string normalizeBdfLegacy(const std::string& bdf) { + std::string result = bdf; + + // Strip function digit + auto dot = result.rfind('.'); + if (dot != std::string::npos) { + result = result.substr(0, dot); + } + + // Strip domain + const auto firstColon = result.find(':'); + const auto lastColon = result.rfind(':'); + if (firstColon != std::string::npos && firstColon != lastColon) { + result = result.substr(firstColon + 1); + } + return result; +} + +std::string shellQuote(const std::string& value) { + std::string quoted = "'"; + for (char c : value) { + if (c == '\'') { + quoted += "'\\''"; + } else { + quoted += c; + } + } + quoted += "'"; + return quoted; +} + +std::string makeExecFromBinaryDirCommand(const std::string& execPath) { + const std::filesystem::path path(execPath); + const std::string dir = path.parent_path().string(); + const std::string file = path.filename().string(); + if (dir.empty() || file.empty()) { + return shellQuote(execPath); + } + return "cd " + shellQuote(dir) + " && exec ./" + shellQuote(file); +} + +bool parseEmuArgIndex(const std::string& argName, std::size_t& outIdx) { + if (argName.size() < 4 || argName.rfind("arg", 0) != 0) { + return false; + } + std::size_t value = 0; + bool hasDigit = false; + for (std::size_t i = 3; i < argName.size(); ++i) { + unsigned char c = static_cast(argName[i]); + if (!std::isdigit(c)) { + return false; + } + hasDigit = true; + value = value * 10 + static_cast(c - '0'); + } + if (!hasDigit) { + return false; + } + outIdx = value; + return true; +} + +void applyEmuManifestToKernels(const std::string& manifestPath, std::map& kernels) { + if (manifestPath.empty()) { + throw std::runtime_error("EMU manifest missing from vrtbin"); + } + + std::ifstream in(manifestPath); + if (!in.is_open()) { + throw std::runtime_error("EMU manifest path unreadable: " + manifestPath); + } + + Json::Value root; + Json::Reader reader; + if (!reader.parse(in, root) || !root.isObject()) { + throw std::runtime_error("Failed to parse EMU manifest: " + manifestPath); + } + + std::size_t appliedCallKinds = 0; + std::size_t appliedFetchRoutes = 0; + + const Json::Value manifestKernels = root["kernels"]; + if (!manifestKernels.isArray()) { + throw std::runtime_error("EMU manifest missing required array: kernels"); + } + if (manifestKernels.isArray()) { + for (const auto& k : manifestKernels) { + if (!k.isObject()) continue; + const std::string instance = k.get("instance", "").asString(); + if (instance.empty()) continue; + auto it = kernels.find(instance); + if (it == kernels.end()) continue; + + std::vector kinds; + const Json::Value callArgs = k["call_args"]; + if (callArgs.isArray()) { + for (const auto& ca : callArgs) { + if (!ca.isObject()) continue; + const std::string argName = ca.get("arg", "").asString(); + const std::string kind = ca.get("kind", "").asString(); + std::size_t idx = 0; + if (kind.empty() || !parseEmuArgIndex(argName, idx)) continue; + if (idx >= kinds.size()) { + kinds.resize(idx + 1); + } + kinds[idx] = kind; + } + } + if (!kinds.empty()) { + it->second.setEmuCallArgKinds(kinds); + appliedCallKinds += 1; + } + } + } + + std::map> fetchRoutesByKernel; + const Json::Value fetch = root["fetch"]; + if (!fetch.isObject()) { + throw std::runtime_error("EMU manifest missing required object: fetch"); + } + const Json::Value fetchScalar = fetch["scalar"]; + if (!fetchScalar.isArray()) { + throw std::runtime_error("EMU manifest missing required array: fetch.scalar"); + } + if (fetchScalar.isArray()) { + for (const auto& route : fetchScalar) { + if (!route.isObject()) continue; + const std::string functionName = route.get("function", "").asString(); + const std::string argName = route.get("arg", "").asString(); + if (functionName.empty() || argName.empty()) continue; + const Json::Value source = route["source"]; + if (!source.isObject()) continue; + const Json::Value regOff = source["register_offset"]; + if (!regOff.isUInt() && !regOff.isInt()) continue; + const uint32_t offset = regOff.asUInt(); + fetchRoutesByKernel[functionName][offset] = argName; + } + } + + for (auto& kv : fetchRoutesByKernel) { + auto it = kernels.find(kv.first); + if (it == kernels.end()) continue; + it->second.setEmuFetchScalarArgByOffset(kv.second); + appliedFetchRoutes += kv.second.size(); + } + + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, + "Applied EMU manifest metadata: call-kind kernels={}, fetch routes={}", + appliedCallKinds, appliedFetchRoutes); +} + +} // namespace + +Device::Device(const std::string& bdf, const std::string& vrtbinPath, bool program, + ProgramType programType) + : vrtbin(vrtbinPath, bdf) { + this->bdf = normalizeBdfLegacy(bdf); + this->bdfFull = normalizeBdfForVrtd(bdf); + this->allocator = new Allocator(); + this->systemMap = this->vrtbin.getSystemMapPath(); + this->pdiPath = this->vrtbin.getPdiPath(); + this->pdiPaths = this->vrtbin.getPdiPaths(); + this->programType = programType; + this->zmqServer = std::make_shared(); + this->platform = vrtbin.getPlatform(); + if (platform == Platform::HARDWARE) { + vrtdSession = std::make_shared(); + vrtdDevice = vrtdSession->getDeviceByBdf(bdfFull); + if (program) { + programDevice(); + } + parseSystemMap(); + if (program && !kernels.empty()) { + sleep(1); // wait for device to be ready after programming before accessing BAR + + } + if (vrtdDevice.has_value()) { + if (clockFreq > CLOCK_MAX_FREQ) { + utils::Logger::log(utils::LogLevel::WARN, __PRETTY_FUNCTION__, + "Clock frequency {} exceeds maximum frequency {}", clockFreq, CLOCK_MAX_FREQ); + vrtdDevice->setUserClockRate(static_cast(CLOCK_MAX_FREQ)); + } + } + } else if (platform == Platform::EMULATION) { + parseSystemMap(); + applyEmuManifestToKernels(this->vrtbin.getEmulationManifest(), kernels); + std::string emulationExecPath = this->vrtbin.getEmulationExec(); + if (emulationExecPath.empty()) { + throw std::runtime_error("Emulation executable vpp_emu not found in vrtbin"); + } + if (::access(emulationExecPath.c_str(), X_OK) != 0) { + throw std::runtime_error("Emulation executable is not runnable: " + emulationExecPath + + " (" + std::strerror(errno) + ")"); + } + + const std::string emuCommand = makeExecFromBinaryDirCommand(emulationExecPath); + runtimeThread = std::thread([emuCommand]() { + int rc = std::system(emuCommand.c_str()); + if (rc != 0) { + utils::Logger::log(utils::LogLevel::WARN, __PRETTY_FUNCTION__, + "Emulation process exited with code {}", rc); + } + }); + + } else { + parseSystemMap(); + std::string simulationExecPath = this->vrtbin.getSimulationExec(); + if (simulationExecPath.empty()) { + throw std::runtime_error("Simulation executable vpp_sim not found in vrtbin"); + } + if (::access(simulationExecPath.c_str(), X_OK) != 0) { + throw std::runtime_error("Simulation executable is not runnable: " + + simulationExecPath + " (" + std::strerror(errno) + ")"); + } + + const std::string simCommand = makeExecFromBinaryDirCommand(simulationExecPath); + runtimeThread = std::thread([simCommand]() { + int rc = std::system(simCommand.c_str()); + if (rc != 0) { + utils::Logger::log(utils::LogLevel::WARN, __PRETTY_FUNCTION__, + "Simulation process exited with code {}", rc); + } + }); + Json::Value command; + command["command"] = "start"; + zmqServer->sendCommand(command); + } + if (platform == Platform::HARDWARE && vrtdDevice.has_value()) { + for (auto& qdmaCon : qdmaConnections) { + qdmaIntfs.emplace_back(new QdmaIntf(*vrtdDevice, qdmaCon.getQid(), + qdmaCon.getDirection())); + } + } +} + +Device::~Device() { + cleanup(); + delete allocator; + allocator = nullptr; +} + +void Device::parseSystemMap() { + XMLParser parser(systemMap); + parser.parseXML(); + clockFreq = parser.getClockFrequency(); + this->platform = parser.getPlatform(); + kernels = parser.getKernels(); + + std::optional barHandle = std::nullopt; + if (platform == Platform::HARDWARE && vrtdDevice.has_value()) { + barHandle = vrtdDevice->getBar(bar); + } + + for (auto&kernel : kernels) { + kernel.second.setPlatform(platform); + kernel.second.setVrtdBar(barHandle); + kernel.second.setServer(zmqServer); + } + this->qdmaConnections = parser.getQdmaConnections(); +} + +Kernel Device::getKernel(const std::string& name) { + auto it = kernels.find(name); + if (it == kernels.end()) { + throw std::runtime_error("Kernel '" + name + "' not found in system_map metadata"); + } + return it->second; +} + +void Device::cleanup() { + if (cleanupDone) { + return; + } + cleanupDone = true; + + if (platform == Platform::HARDWARE) { + for (auto qdmaIntf_ : qdmaIntfs) { + delete qdmaIntf_; + } + qdmaIntfs.clear(); + } else if (platform == Platform::EMULATION || platform == Platform::SIMULATION) { + Json::Value exit; + exit["command"] = "exit"; + zmqServer->sendCommand(exit); + } + if (runtimeThread.joinable()) { + runtimeThread.join(); + } +} + +std::string Device::getBdf() { return bdf; } + +void Device::programDevice() { + if (pdiPaths.empty() && !pdiPath.empty()) { + pdiPaths.push_back(pdiPath); + } + if (pdiPaths.empty()) { + throw std::runtime_error("No PDI files found for programming"); + } + + for (const auto& pdi : pdiPaths) { + utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, + "Programming PDI via vrtd design writer {}", pdi); + getVrtdDevice().designWriteFile(pdi); + } +} + +void Device::setFrequency(uint64_t freq) { + if (platform == Platform::HARDWARE) { + if (freq > clockFreq) { + utils::Logger::log(utils::LogLevel::WARN, __PRETTY_FUNCTION__, + "Setting frequency {}, which is higher than max frequency {}", freq, + clockFreq); + } + if (freq > std::numeric_limits::max()) { + throw std::runtime_error("Requested frequency exceeds vrtd clock API limits"); + } + getVrtdDevice().setUserClockRate(static_cast(freq)); + } +} + +uint64_t Device::getFrequency() { + if (platform == Platform::HARDWARE) { + return getVrtdDevice().getUserClockRate(); + } else { + return 0; + } +} + +uint64_t Device::getMaxFrequency() { + if (platform == Platform::HARDWARE) { + return clockFreq; + } else { + return 0; + } +} + +void Device::findPlatform() { + XMLParser parser(systemMap); + parser.parseXML(); + this->platform = parser.getPlatform(); +} + +Platform Device::getPlatform() { return platform; } + +std::shared_ptr Device::getZmqServer() { return zmqServer; } + +std::vector Device::getQdmaConnections() { return qdmaConnections; } + +Allocator* Device::getAllocator() { return allocator; } + +vrtd::Device& Device::getVrtdDevice() { + if (!vrtdDevice.has_value()) { + throw std::runtime_error("vrtd device not initialized"); + } + return *vrtdDevice; +} + +const vrtd::Device& Device::getVrtdDevice() const { + if (!vrtdDevice.has_value()) { + throw std::runtime_error("vrtd device not initialized"); + } + return *vrtdDevice; +} + +std::vector Device::getQdmaInterfaces() { return qdmaIntfs; } + +} // namespace impl +} // namespace vrt diff --git a/vrt/src/driver/clk_wiz.cpp b/vrt/src/driver/clk_wiz.cpp deleted file mode 100644 index 47440582..00000000 --- a/vrt/src/driver/clk_wiz.cpp +++ /dev/null @@ -1,259 +0,0 @@ -/** - * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT - * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "driver/clk_wiz.hpp" - -namespace vrt { - -ClkWiz::ClkWiz(ami_device* device, const std::string& name, uint64_t baseAddr, uint64_t range, - uint64_t clockFreq) - : Kernel(device, name, baseAddr, range, std::vector{}) { - instancePtr = new XClk_Wiz; - instancePtr->Config.BaseAddr = baseAddr; - instancePtr->Config.PrimInClkFreq = 100000000; - instancePtr->MinErr = 50000; - this->clockFrequency = clockFreq; -} - -uint64_t ClkWiz::getVco() { - uint32_t Div; - uint64_t Fvco; - uint32_t Edge; - uint32_t Low; - uint32_t High; - uint32_t Mult; - uint32_t reg = read(XCLK_WIZ_REG1_OFFSET); - Edge = !!(reg & XCLK_WIZ_REG1_EDGE_MASK); - reg = read(XCLK_WIZ_REG2_OFFSET); - Low = reg & XCLK_WIZ_CLKFBOUT_L_MASK; - High = (reg & XCLK_WIZ_CLKFBOUT_H_MASK) >> XCLK_WIZ_CLKFBOUT_H_SHIFT; - Mult = Low + High + Edge; - reg = read(XCLK_WIZ_REG13_OFFSET); - Low = reg & XCLK_WIZ_CLKFBOUT_L_MASK; - High = (reg & XCLK_WIZ_CLKFBOUT_H_MASK) >> XCLK_WIZ_CLKFBOUT_H_SHIFT; - reg = read(XCLK_WIZ_REG12_OFFSET); - Edge = !!(reg & XCLK_WIZ_EDGE_MASK); - Div = Low + High + Edge; - if (!Mult) Mult = 1; - if (!Div) Div = 1; - Fvco = instancePtr->Config.PrimInClkFreq * Mult / Div; - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "VCO value is: {}", Fvco); - return Fvco; -} - -uint64_t ClkWiz::getClockRate() { - uint32_t Reg; - uint32_t Leaf; - uint64_t Fvco; - uint64_t Freq; - uint32_t RegisterOffset; - uint32_t Edge; - uint32_t Low; - uint32_t High; - uint32_t DivO; - uint32_t P5en; - uint32_t Prediv; - - Fvco = getVco(); - Freq = instancePtr->Config.PrimInClkFreq * instancePtr->MVal / instancePtr->DVal / - instancePtr->OVal; - return Freq; -} - -void ClkWiz::calculateDivisorsHz(uint64_t SetRate) { - uint32_t m; - uint32_t d; - uint32_t Div; - uint64_t Fvco; - uint64_t Freq; - uint64_t Diff; - uint64_t Minerr = instancePtr->MinErr; - uint64_t VcoMin; - uint64_t VcoMax; - uint32_t Platform; - uint32_t Mmin; - uint32_t Mmax; - uint32_t Dmin; - uint32_t Dmax; - uint32_t Omin; - uint32_t Omax; - - VcoMin = XCLK_VCO_MIN; - VcoMax = XCLK_VCO_MAX; - Mmin = XCLK_M_MIN; - Mmax = XCLK_M_MAX; - Dmin = XCLK_D_MIN; - Dmax = XCLK_D_MAX; - Omin = XCLK_O_MIN; - Omax = XCLK_O_MAX; - for (m = Mmin; m <= Mmax; m++) { - for (d = Dmin; d <= Dmax; d++) { - Fvco = instancePtr->Config.PrimInClkFreq * m / d; - if (Fvco >= VcoMin * XCLK_MHZ && Fvco <= VcoMax * XCLK_MHZ) { - for (Div = Omin; Div <= Omax; Div++) { - Freq = Fvco / Div; - - if (Freq > SetRate) { - Diff = Freq - SetRate; - } else { - Diff = SetRate - Freq; - } - if (Diff < Minerr) { - instancePtr->MVal = m; - instancePtr->DVal = d; - instancePtr->OVal = Div; - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "M: {}, D: {}, O: {}", m, d, Div); - return; - } - } - } - } - } -} - -void ClkWiz::updateO() { - uint32_t HighTime; - uint32_t DivEdge; - uint32_t Reg; - uint32_t P5Enable; - uint32_t P5fEdge; - uint32_t RegisterOffset; - - if (instancePtr->OVal > XCLK_O_MAX) { - instancePtr->OVal = XCLK_O_MAX; - } - RegisterOffset = - XCLK_WIZ_REG3_OFFSET + 0 * 8; // indicate clock id, needs to be tested to see what value - HighTime = (instancePtr->OVal / 4); - Reg = XCLK_WIZ_REG3_PREDIV2 | XCLK_WIZ_REG3_USED | XCLK_WIZ_REG3_MX; - if (instancePtr->OVal % 4 <= 1) { - DivEdge = 0; - } else { - DivEdge = 1; - } - Reg |= (DivEdge << 8); - P5fEdge = instancePtr->OVal % 2; - P5Enable = instancePtr->OVal % 2; - Reg = Reg | P5Enable << XCLK_WIZ_CLKOUT0_P5EN_SHIFT | P5fEdge << XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT; - write(RegisterOffset, Reg); - Reg = HighTime | HighTime << 8; - RegisterOffset = RegisterOffset + 4; - write(RegisterOffset, Reg); - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "O value is: {}", - instancePtr->OVal); -} - -void ClkWiz::updateD() { - uint32_t HighTime; - uint32_t DivEdge; - uint32_t Reg; - - HighTime = (instancePtr->DVal / 2); - Reg = 0; - Reg = Reg & ~(1 << XCLK_WIZ_REG12_EDGE_SHIFT); - DivEdge = instancePtr->DVal % 2; - Reg = Reg | DivEdge << XCLK_WIZ_REG12_EDGE_SHIFT; - write(XCLK_WIZ_REG12_OFFSET, Reg); - Reg = HighTime | HighTime << 8; - write(XCLK_WIZ_REG13_OFFSET, Reg); - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "D value is: {}", - instancePtr->DVal); -} - -void ClkWiz::updateM() { - uint32_t HighTime; - uint32_t DivEdge; - uint32_t Reg; - write(XCLK_WIZ_REG25_OFFSET, 0); - - DivEdge = instancePtr->MVal % 2; - HighTime = instancePtr->MVal / 2; - Reg = HighTime | HighTime << 8; - write(XCLK_WIZ_REG2_OFFSET, Reg); - Reg = XCLK_WIZ_REG1_PREDIV2 | XCLK_WIZ_REG1_EN | XCLK_WIZ_REG1_MX; - - if (DivEdge) { - Reg = Reg | (1 << XCLK_WIZ_REG1_EDGE_SHIFT); - } else { - Reg = Reg & ~(1 << XCLK_WIZ_REG1_EDGE_SHIFT); - } - write(XCLK_WIZ_REG1_OFFSET, Reg); - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "M value is: {}", - instancePtr->MVal); -} - -uint32_t ClkWiz::waitForLock() { - uint32_t count = 0; - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Waiting for clock lock"); - while (!read(XCLK_WIZ_REG4_OFFSET) & 1) { - if (count == 1000) { - utils::Logger::log( - utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Error: Timeout waiting for clock lock. Probably values not set correctly"); - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "Trying default frequency, 200MHz"); - } - usleep(100); - count++; - } - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Clock locked"); - return 0; -} - -void ClkWiz::setRateHzInternal(uint64_t rate) { - uint32_t Reg; - calculateDivisorsHz(rate); - updateO(); - updateD(); - updateM(); - // weird values no one knows where they come from :) - write(XCLK_WIZ_REG11_OFFSET, 0x2e); - write(XCLK_WIZ_REG14_OFFSET, 0xe80); - write(XCLK_WIZ_REG15_OFFSET, 0x4271); - write(XCLK_WIZ_REG16_OFFSET, 0x43e9); - write(XCLK_WIZ_REG17_OFFSET, 0x001C); - write(XCLK_WIZ_REG26_OFFSET, 0x0001); -} -void ClkWiz::setRateHz(uint64_t rate_, bool verbose) { - if (verbose) - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Setting clock at: {} MHz", - std::to_string((double)rate_ / 1000000.0f)); - - // start dynamic reconfig - utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Starting dynamic reconfiguration"); - write(XCLK_WIZ_REG25_OFFSET, 0); - setRateHzInternal(rate_); - write(XCLK_WIZ_RECONFIG_OFFSET, (XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR)); - uint32_t status = waitForLock(); - if (status != 0) { - uint32_t reg = read(XCLK_WIZ_REG4_OFFSET); - utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, - "Error: Clock not locked : {x}", reg); - throw std::runtime_error("Clock not locked"); - } - uint64_t rate = getClockRate(); - if (verbose) - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, - "User clock frequency set at: {} MHz", - std::to_string((double)rate / 1000000.0f)); -} -} // namespace vrt \ No newline at end of file diff --git a/vrt/src/driver/qdma_logic.cpp b/vrt/src/driver/qdma_logic.cpp index b005199c..cea58bfe 100644 --- a/vrt/src/driver/qdma_logic.cpp +++ b/vrt/src/driver/qdma_logic.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,12 +18,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "driver/qdma_logic.hpp" +#include namespace vrt { -QdmaLogic::QdmaLogic(ami_device* device, const std::string& name, uint64_t baseAddr, uint64_t range) - : Kernel(device, name, baseAddr, range, std::vector{}) {} +QdmaLogic::QdmaLogic(const std::string& name, uint64_t baseAddr, uint64_t range) + : Kernel(name, baseAddr, range, std::vector{}) {} void QdmaLogic::setValues(uint16_t qid, uint32_t length) { uint32_t regVal = 0; @@ -32,4 +32,4 @@ void QdmaLogic::setValues(uint16_t qid, uint32_t length) { write(0x00, regVal); } -} // namespace vrt \ No newline at end of file +} // namespace vrt diff --git a/vrt/src/kernel.cpp b/vrt/src/kernel.cpp new file mode 100644 index 00000000..ca91dfc6 --- /dev/null +++ b/vrt/src/kernel.cpp @@ -0,0 +1,503 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file kernel.cpp + * @brief Kernel class implementation. + */ + +#include + +#include + +#include +#include + +namespace vrt { +namespace { + +MemoryConfig parseMemoryTarget(const std::string& target) { + if (target.rfind("DDR", 0) == 0) { + return {MemoryRangeType::DDR, std::nullopt}; + } + if (target.rfind("HBM", 0) == 0) { + std::string bankStr = target.substr(3); + if (!bankStr.empty()) { + return {MemoryRangeType::HBM, static_cast(std::stoul(bankStr))}; + } + return {MemoryRangeType::HBM_VNOC, std::nullopt}; + } + if (target.rfind("MEM", 0) == 0) { + return {MemoryRangeType::HBM_VNOC, std::nullopt}; + } + throw std::runtime_error("Unknown memory target '" + target + "'"); +} + +uint64_t resolveBarOffset(uint64_t absoluteAddr, uint64_t accessSize, uint64_t barLen) { + if (barLen == 0) { + throw std::runtime_error("BAR length is zero"); + } + + // Design model: BAR maps a contiguous AXI window. Kernel base addresses + // are absolute within that window; register offsets are relative to kernel base. + const uint64_t barWindowBase = absoluteAddr - (absoluteAddr % barLen); + const uint64_t barOffset = absoluteAddr - barWindowBase; + if (barOffset + accessSize > barLen) { + throw std::runtime_error("BAR access out of range"); + } + return barOffset; +} + +} // namespace + +Kernel::Kernel(const std::string& name, uint64_t baseAddr, uint64_t range, + const std::vector& registers, + const std::vector& functionalArgs) { + this->name = name; + this->baseAddr = baseAddr; + this->range = range; + this->registers = registers; + this->functionalArgs = functionalArgs; + std::sort(this->functionalArgs.begin(), this->functionalArgs.end(), + [](const FunctionalArg& a, const FunctionalArg& b) { return a.idx < b.idx; }); +} + +Kernel::Kernel(Device device, const std::string& kernelName) + : Kernel(device.getKernel(kernelName)) {} + +vrtd::BarFile& Kernel::getOrOpenBarFile() { + if (!vrtdBar.has_value()) { + throw std::runtime_error("vrtd BAR handle not initialized"); + } + if (!vrtdBarFile || vrtdBarFile->isClosed()) { + vrtdBarFile = std::make_shared(vrtdBar->openBarFile()); + } + return *vrtdBarFile; +} + +void Kernel::write(uint32_t offset, uint32_t value) { + if (platform == Platform::HARDWARE) { + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, + "Writing to device {} kernel: {} at offset: {x} value: {x}", deviceBdf, + name, offset, value); + auto& barFile = getOrOpenBarFile(); + const uint64_t absoluteAddr = baseAddr + static_cast(offset); + uint64_t barOffset = resolveBarOffset(absoluteAddr, sizeof(uint32_t), barFile.getLen()); + auto ptr = barFile.getPtr(vrtd::BarFile::Direction::Write, + static_cast(barOffset)); + *ptr = value; + return; + } else if (platform == Platform::SIMULATION) { + server->sendScalar(baseAddr + offset, value); + } +} + +uint32_t Kernel::read(uint32_t offset) { + if (platform == Platform::HARDWARE) { + if (offset != 0) + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, + "Reading from device {} kernel: {} at offset: {x}", deviceBdf, name, + offset); + auto& barFile = getOrOpenBarFile(); + const uint64_t absoluteAddr = baseAddr + static_cast(offset); + uint64_t barOffset = resolveBarOffset(absoluteAddr, sizeof(uint32_t), barFile.getLen()); + auto ptr = barFile.getPtr(vrtd::BarFile::Direction::Read, + static_cast(barOffset)); + return *ptr; + } else if (platform == Platform::EMULATION) { + return server->readRegister(name, offset); + } else if (platform == Platform::SIMULATION) { + return server->fetchScalarSim(baseAddr + offset); + } + return 0; +} + +void Kernel::setVrtdBar(const std::optional& bar) { this->vrtdBar = bar; } + +void Kernel::setServer(std::shared_ptr server) { this->server = server; } + +void Kernel::setFunctionalArgs(const std::vector& args) { + functionalArgs = args; + std::sort(functionalArgs.begin(), functionalArgs.end(), + [](const FunctionalArg& a, const FunctionalArg& b) { return a.idx < b.idx; }); +} + +bool Kernel::hasFunctionalArgs() const { return !functionalArgs.empty(); } + +const std::vector& Kernel::getFunctionalArgs() const { + return functionalArgs; +} + +std::string Kernel::buildArgApiUsageMessage(std::string_view reason, std::string_view opName) const { + std::ostringstream oss; + oss << "Kernel argument API misuse for kernel '" << name << "': " << reason << "\n"; + oss << "Usage model:\n"; + oss << "1) Positional launch: kernel." << opName << "(arg0, arg1, ...)\n"; + oss << "2) Staged launch: kernel.setArg(idx_or_name, value) ... then kernel." << opName << "()\n"; + oss << "Rules:\n"; + oss << "- Choose exactly one style per launch; do not mix setArg(...) with " + << opName << "(...)\n"; + oss << "- If " << opName + << "() is used (no positional args) and functional_args exist, every writable arg must be set via setArg\n"; + oss << "- If no functional_args metadata exists, argument APIs are unavailable; use write(offset, value) then " + << opName << "()\n"; + + if (!functionalArgs.empty()) { + oss << "Expected functional_args:\n"; + for (const FunctionalArg& arg : functionalArgs) { + oss << " - idx=" << arg.idx << ", name='" << arg.name << "', type='" << arg.type + << "', offset=0x" << std::hex << arg.offset << std::dec + << ", range_bits=" << arg.range << "\n"; + } + } + + return oss.str(); +} + +[[noreturn]] void Kernel::throwArgApiMisuse(std::string_view reason, std::string_view opName) const { + throw std::runtime_error(buildArgApiUsageMessage(reason, opName)); +} + +void Kernel::ensureNoSetArgValuesWhenPassingArgs(std::size_t providedArgCount, + std::string_view opName) const { + if (providedArgCount > 0 && !setArgValues.empty()) { + throwArgApiMisuse( + "Positional arguments were passed while staged setArg(...) values are already present.", + opName); + } +} + +void Kernel::ensureSetArgValuesCompleteForLaunch(std::string_view opName) const { + std::vector missing; + for (const FunctionalArg& argMeta : functionalArgs) { + if (!argMeta.writable) { + continue; + } + if (setArgValues.find(argMeta.idx) == setArgValues.end()) { + missing.push_back("'" + argMeta.name + "'(idx " + std::to_string(argMeta.idx) + ")"); + } + } + if (!missing.empty()) { + std::ostringstream reason; + reason << "Not all functional args were provided via setArg before " << opName << "(). Missing: "; + for (std::size_t i = 0; i < missing.size(); ++i) { + if (i != 0) { + reason << ", "; + } + reason << missing[i]; + } + throwArgApiMisuse(reason.str(), opName); + } +} + +const FunctionalArg& Kernel::functionalArgByIdx(uint32_t idx) const { + auto it = std::find_if(functionalArgs.begin(), functionalArgs.end(), + [idx](const FunctionalArg& arg) { return arg.idx == idx; }); + if (it == functionalArgs.end()) { + throwArgApiMisuse("setArg(idx, value) referenced unknown arg index " + std::to_string(idx) + + ".", + "setArg"); + } + return *it; +} + +uint32_t Kernel::functionalArgIdxByName(std::string_view argName) const { + if (argName.empty()) { + throwArgApiMisuse("setArg(name, value) received an empty argument name.", "setArg"); + } + + const std::string requestedName(argName); + bool found = false; + uint32_t foundIdx = 0; + for (const FunctionalArg& argMeta : functionalArgs) { + if (argMeta.name == requestedName) { + if (found) { + throwArgApiMisuse("setArg(name, value) matched multiple args for name '" + + requestedName + "'.", + "setArg"); + } + found = true; + foundIdx = argMeta.idx; + } + } + + // Vitis HLS appends _r to m_axi (buffer) register names. + // Allow users to use the original HLS parameter name (e.g. "in" -> "in_r"). + if (!found) { + const std::string withSuffix = requestedName + "_r"; + for (const FunctionalArg& argMeta : functionalArgs) { + if (argMeta.name == withSuffix) { + if (found) { + throwArgApiMisuse("setArg(name, value) matched multiple args for name '" + + requestedName + "' (resolved to '" + withSuffix + "').", + "setArg"); + } + found = true; + foundIdx = argMeta.idx; + } + } + } + + if (!found) { + throwArgApiMisuse("setArg(name, value) referenced unknown arg name '" + requestedName + + "'.", + "setArg"); + } + return foundIdx; +} + +void Kernel::setArgResolved(uint32_t idx, uint64_t value) { + if (functionalArgs.empty()) { + throwArgApiMisuse( + "setArg(...) was used but this kernel has no functional_args metadata in system_map.xml.", + "setArg"); + } + const FunctionalArg& argMeta = functionalArgByIdx(idx); + setArgValues[argMeta.idx] = value; +} + +void Kernel::writeArgToRegisterMap(const FunctionalArg& argMeta, uint64_t value) { + const uint32_t words = argWordCount(argMeta); + for (uint32_t i = 0; i < words; ++i) { + const uint32_t off = argMeta.offset + i * sizeof(uint32_t); + registerMap[off] = argWordValue(value, i); + } +} + +void Kernel::writeArgToSimulation(const FunctionalArg& argMeta, uint64_t value) { + const uint32_t words = argWordCount(argMeta); + for (uint32_t i = 0; i < words; ++i) { + const uint32_t off = argMeta.offset + i * sizeof(uint32_t); + write(off, argWordValue(value, i)); + } +} + +void Kernel::writeArgToEmulation(Json::Value& command, const FunctionalArg& argMeta, + uint64_t value) const { + const std::string emuKind = normalizeArgType(argMeta.type); + const uint32_t emuArgIdx = argMeta.idx; + + if (emuKind == "buffer") { + command["args"]["arg" + std::to_string(emuArgIdx)]["type"] = "buffer"; + command["args"]["arg" + std::to_string(emuArgIdx)]["name"] = std::to_string(value); + return; + } + if (emuKind == "scalar") { + command["args"]["arg" + std::to_string(emuArgIdx)]["type"] = "scalar"; + command["args"]["arg" + std::to_string(emuArgIdx)]["value"] = + static_cast(value); + return; + } + throw std::runtime_error("Unsupported functional arg type '" + argMeta.type + + "' for kernel '" + name + "' at idx " + + std::to_string(argMeta.idx)); +} + +void Kernel::applySetArgsToRegisterMap() { + registerMap.clear(); + for (const FunctionalArg& argMeta : functionalArgs) { + if (!argMeta.writable) { + continue; + } + const uint64_t value = setArgValues.at(argMeta.idx); + writeArgToRegisterMap(argMeta, value); + } +} + +void Kernel::applySetArgsToSimulation() { + for (const FunctionalArg& argMeta : functionalArgs) { + if (!argMeta.writable) { + continue; + } + const uint64_t value = setArgValues.at(argMeta.idx); + writeArgToSimulation(argMeta, value); + } +} + +void Kernel::applySetArgsToEmulation(Json::Value& command) const { + for (const FunctionalArg& argMeta : functionalArgs) { + if (!argMeta.writable) { + continue; + } + const uint64_t value = setArgValues.at(argMeta.idx); + writeArgToEmulation(command, argMeta, value); + } +} + +void Kernel::setEmuCallArgKinds(const std::vector& kinds) { emuCallArgKinds = kinds; } + +void Kernel::setEmuFetchScalarArgByOffset(const std::map& routes) { + emuFetchScalarArgByOffset = routes; +} + +void Kernel::setConnections(const std::map& conns) { + connections = conns; +} + +void Kernel::validateBufferMemoryType(const FunctionalArg& argMeta, MemoryRangeType memType, + uint8_t hbmPort) const { + if (argMeta.port.empty()) { + return; + } + auto it = connections.find(argMeta.port); + if (it == connections.end()) { + return; + } + const std::string& target = it->second; + + if (target.rfind("DDR", 0) == 0) { + if (memType != MemoryRangeType::DDR) { + throw std::runtime_error( + "Memory type mismatch for kernel '" + name + "' argument '" + argMeta.name + + "' (port " + argMeta.port + "): target is " + target + + " but buffer is not DDR"); + } + } else if (target.rfind("HBM", 0) == 0) { + if (memType == MemoryRangeType::DDR) { + throw std::runtime_error( + "Memory type mismatch for kernel '" + name + "' argument '" + argMeta.name + + "' (port " + argMeta.port + "): target is " + target + + " but buffer is DDR"); + } + if (memType == MemoryRangeType::HBM_VNOC) { + throw std::runtime_error( + "Memory type mismatch for kernel '" + name + "' argument '" + argMeta.name + + "' (port " + argMeta.port + "): target is " + target + + " but buffer is HBM_VNOC (use a specific HBM region buffer)"); + } + // HBM with specific bank — extract bank number and verify exact match + std::string bankStr = target.substr(3); + if (!bankStr.empty()) { + unsigned long expectedBank = std::stoul(bankStr); + if (static_cast(hbmPort) != expectedBank) { + throw std::runtime_error( + "Memory type mismatch for kernel '" + name + "' argument '" + argMeta.name + + "' (port " + argMeta.port + "): target is " + target + + " but buffer is HBM" + std::to_string(hbmPort)); + } + } + } else if (target == "MEM") { + if (memType != MemoryRangeType::HBM_VNOC && memType != MemoryRangeType::HBM) { + throw std::runtime_error( + "Memory type mismatch for kernel '" + name + "' argument '" + argMeta.name + + "' (port " + argMeta.port + "): target is MEM but buffer is DDR" + " (use an HBM_VNOC or HBM buffer)"); + } + } +} + +MemoryConfig Kernel::portMemoryConfig(std::string_view portName) const { + auto it = connections.find(std::string(portName)); + if (it == connections.end()) { + throw std::runtime_error("Kernel '" + name + "' has no memory connection for port '" + + std::string(portName) + "'"); + } + return parseMemoryTarget(it->second); +} + +MemoryConfig Kernel::argMemoryConfig(std::string_view argName) const { + const uint32_t idx = functionalArgIdxByName(argName); + const FunctionalArg& arg = functionalArgByIdx(idx); + if (arg.port.empty()) { + throw std::runtime_error("Kernel '" + name + "' argument '" + std::string(argName) + + "' has no associated AXI port"); + } + return portMemoryConfig(arg.port); +} + +void Kernel::wait() { + if (platform == Platform::EMULATION) { + Json::Value command; + command["command"] = "wait"; + command["function"] = name; + server->sendCommand(command); + return; + } + // ap_ctrl_hs: wait for ap_done (CTRL[1]) instead of checking exact control word values. + while ((read(0x00) & 0x2u) == 0u) { + } +} + +void Kernel::start() { this->start<>(); } + +void Kernel::startKernel(bool autorestart) { + if (autorestart) { + write(0x00, 0x81); + } else { + write(0x00, 0x01); + } +} + +Kernel::~Kernel() {} + +void Kernel::setPlatform(Platform platform) { this->platform = platform; } + +void Kernel::writeBatch() { + if (platform != Platform::HARDWARE) { + return; + } + if (registerMap.empty()) { + return; + } + + uint32_t maxOffset = 0; + for (const auto& [offset, _] : registerMap) { + maxOffset = std::max(maxOffset, offset); + } + uint32_t noOfPhysicalRegisters = (maxOffset + sizeof(uint32_t)) / sizeof(uint32_t); + + uint32_t* buf = (uint32_t*)calloc(noOfPhysicalRegisters, sizeof(uint32_t)); + for (const auto& [offset, value] : registerMap) { + const std::size_t wordIdx = static_cast(offset / sizeof(uint32_t)); + if (wordIdx >= noOfPhysicalRegisters) { + continue; + } + buf[wordIdx] = value; + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, + "Kernel {}, reg at offset {x}, value: {x}", name, offset, value); + } + vrtd::BarFile* barFilePtr = nullptr; + try { + barFilePtr = &getOrOpenBarFile(); + } catch (...) { + free(buf); + throw; + } + auto& barFile = *barFilePtr; + uint64_t byteCount = static_cast(noOfPhysicalRegisters) * sizeof(uint32_t); + uint64_t barOffset = 0; + try { + barOffset = resolveBarOffset(baseAddr, byteCount, barFile.getLen()); + } catch (const std::runtime_error&) { + free(buf); + throw std::runtime_error("BAR write range out of range"); + } + auto ptr = barFile.getPtr(vrtd::BarFile::Direction::Write, + static_cast(barOffset)); + for (uint32_t i = 0; i < noOfPhysicalRegisters; ++i) { + ptr[i] = buf[i]; + } + free(buf); + return; +} +std::string Kernel::getName() const { return name; } +uint64_t Kernel::getPhysAddr() const { return baseAddr; } + +} // namespace vrt diff --git a/vrt/src/parser/utilization_parser.cpp b/vrt/src/parser/utilization_parser.cpp new file mode 100644 index 00000000..d724542d --- /dev/null +++ b/vrt/src/parser/utilization_parser.cpp @@ -0,0 +1,188 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include + +namespace vrt { + +namespace { + +std::string getNodeProp(xmlNode* node, const char* propName) { + if (node == nullptr) { + return ""; + } + xmlChar* prop = xmlGetProp(node, BAD_CAST propName); + if (prop == nullptr) { + return ""; + } + std::string out(reinterpret_cast(prop)); + xmlFree(prop); + return out; +} + +uint32_t parseU32(const std::string& text) { + if (text.empty()) { + return 0; + } + return static_cast(std::stoul(text, nullptr, 0)); +} + +std::optional parseOptionalFloat(const std::string& text) { + if (text.empty()) { + return std::nullopt; + } + return std::stof(text); +} + +ResourceMetrics parseResourceMetrics(xmlNode* node) { + ResourceMetrics m; + m.totalPplocs = parseU32(getNodeProp(node, "total_pplocs")); + m.totalLuts = parseU32(getNodeProp(node, "total_luts")); + m.lutram = parseU32(getNodeProp(node, "lutram")); + m.srl = parseU32(getNodeProp(node, "srl")); + m.ff = parseU32(getNodeProp(node, "ff")); + m.ramb36 = parseU32(getNodeProp(node, "ramb36")); + m.ramb18 = parseU32(getNodeProp(node, "ramb18")); + m.ramb = parseU32(getNodeProp(node, "ramb")); + m.uram = parseU32(getNodeProp(node, "uram")); + m.dsp = parseU32(getNodeProp(node, "dsp")); + + m.totalLutsPct = parseOptionalFloat(getNodeProp(node, "total_luts_pct")); + m.lutramPct = parseOptionalFloat(getNodeProp(node, "lutram_pct")); + m.srlPct = parseOptionalFloat(getNodeProp(node, "srl_pct")); + m.ffPct = parseOptionalFloat(getNodeProp(node, "ff_pct")); + m.ramb36Pct = parseOptionalFloat(getNodeProp(node, "ramb36_pct")); + m.ramb18Pct = parseOptionalFloat(getNodeProp(node, "ramb18_pct")); + m.uramPct = parseOptionalFloat(getNodeProp(node, "uram_pct")); + m.dspPct = parseOptionalFloat(getNodeProp(node, "dsp_pct")); + return m; +} + +/// Parse a or element whose metrics live in a child . +UtilizationCell parseCellWithTotals(xmlNode* node) { + UtilizationCell cell; + cell.instance = getNodeProp(node, "instance"); + cell.module = getNodeProp(node, "module"); + for (xmlNode* child = node->children; child; child = child->next) { + if (child->type == XML_ELEMENT_NODE && + xmlStrcmp(child->name, BAD_CAST "totals") == 0) { + cell.metrics = parseResourceMetrics(child); + break; + } + } + return cell; +} + +/// Parse the element containing , , , sums. +UtilizationBlock parseSlashBlock(xmlNode* slashNode) { + UtilizationBlock block; + block.name = "slash"; + Subhierarchy sub; + + for (xmlNode* child = slashNode->children; child; child = child->next) { + if (child->type != XML_ELEMENT_NODE) { + continue; + } + if (xmlStrcmp(child->name, BAD_CAST "totals") == 0) { + block.totals = parseResourceMetrics(child); + } else if (xmlStrcmp(child->name, BAD_CAST "kernels") == 0) { + for (xmlNode* k = child->children; k; k = k->next) { + if (k->type == XML_ELEMENT_NODE && + xmlStrcmp(k->name, BAD_CAST "kernel") == 0) { + sub.cells.push_back(parseCellWithTotals(k)); + } + } + } else if (xmlStrcmp(child->name, BAD_CAST "slash_logic") == 0) { + for (xmlNode* c = child->children; c; c = c->next) { + if (c->type == XML_ELEMENT_NODE && + xmlStrcmp(c->name, BAD_CAST "cell") == 0) { + sub.slashLogic.push_back(parseCellWithTotals(c)); + } + } + } else if (xmlStrcmp(child->name, BAD_CAST "kernel_sum") == 0) { + sub.subhierarchySum = parseResourceMetrics(child); + } else if (xmlStrcmp(child->name, BAD_CAST "slash_logic_sum") == 0) { + sub.slashLogicSum = parseResourceMetrics(child); + } + } + + block.subhierarchy = std::move(sub); + return block; +} + +/// Parse a element (totals only, no subhierarchy). +UtilizationBlock parseServiceLayerBlock(xmlNode* node) { + UtilizationBlock block; + block.name = "service_layer"; + for (xmlNode* child = node->children; child; child = child->next) { + if (child->type == XML_ELEMENT_NODE && + xmlStrcmp(child->name, BAD_CAST "totals") == 0) { + block.totals = parseResourceMetrics(child); + break; + } + } + return block; +} + +} // namespace + +UtilizationParser::UtilizationParser(const std::string& filePath) : filename(filePath) { + document = xmlReadFile(filePath.c_str(), nullptr, 0); + if (document == nullptr) { + throw std::runtime_error("Failed to parse utilization XML: " + filePath); + } +} + +void UtilizationParser::parse() { + xmlNode* root = xmlDocGetRootElement(document); + if (root == nullptr) { + throw std::runtime_error("Utilization XML has no root element: " + filename); + } + + bool foundSlash = false; + for (xmlNode* node = root->children; node; node = node->next) { + if (node->type != XML_ELEMENT_NODE) { + continue; + } + + if (xmlStrcmp(node->name, BAD_CAST "slash") == 0) { + report.slash = parseSlashBlock(node); + foundSlash = true; + } else if (xmlStrcmp(node->name, BAD_CAST "service_layer") == 0) { + report.serviceLayer = parseServiceLayerBlock(node); + } + } + + if (!foundSlash) { + throw std::runtime_error("Utilization report missing required 'slash' block: " + filename); + } +} + +const UtilizationReport& UtilizationParser::getReport() const { return report; } + +UtilizationParser::~UtilizationParser() { + if (document != nullptr) { + xmlFreeDoc(document); + } +} + +} // namespace vrt diff --git a/vrt/src/parser/xml_parser.cpp b/vrt/src/parser/xml_parser.cpp index 3db612ff..bb2549cc 100644 --- a/vrt/src/parser/xml_parser.cpp +++ b/vrt/src/parser/xml_parser.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,13 +18,73 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "parser/xml_parser.hpp" +#include + +#include namespace vrt { + +namespace { + +std::string getNodeContent(xmlNode* node) { + if (node == nullptr) { + return ""; + } + xmlChar* content = xmlNodeGetContent(node); + if (content == nullptr) { + return ""; + } + std::string out(reinterpret_cast(content)); + xmlFree(content); + return out; +} + +std::string getNodeProp(xmlNode* node, const char* propName) { + if (node == nullptr) { + return ""; + } + xmlChar* prop = xmlGetProp(node, BAD_CAST propName); + if (prop == nullptr) { + return ""; + } + std::string out(reinterpret_cast(prop)); + xmlFree(prop); + return out; +} + +uint32_t parseU32(const std::string& text, uint32_t defaultValue = 0) { + if (text.empty()) { + return defaultValue; + } + return static_cast(std::stoul(text, nullptr, 0)); +} + +uint64_t parseU64(const std::string& text, uint64_t defaultValue = 0) { + if (text.empty()) { + return defaultValue; + } + return static_cast(std::stoull(text, nullptr, 0)); +} + +bool parseBoolInt(const std::string& text, bool defaultValue = false) { + if (text.empty()) { + return defaultValue; + } + return std::stoi(text, nullptr, 0) != 0; +} + +} // namespace + XMLParser::XMLParser(const std::string& file_path) { this->filename = file_path; this->document = xmlReadFile(this->filename.c_str(), NULL, 0); + if (this->document == nullptr) { + throw std::runtime_error("Failed to parse XML file: " + file_path); + } this->rootNode = xmlDocGetRootElement(this->document); + if (this->rootNode == nullptr) { + throw std::runtime_error("XML file has no root element: " + file_path); + } this->workingNode = rootNode->children; } @@ -36,47 +96,75 @@ void XMLParser::parseXML() { std::string baseAddress; std::string range; std::vector registers; + std::vector functionalArgs; + std::map connections; for (xmlNode* childNode = kernelNode->children; childNode; childNode = childNode->next) { if (childNode->type == XML_ELEMENT_NODE) { if (xmlStrcmp(childNode->name, BAD_CAST "Name") == 0) { - name = (const char*)xmlNodeGetContent(childNode); + name = getNodeContent(childNode); } else if (xmlStrcmp(childNode->name, BAD_CAST "BaseAddress") == 0) { - baseAddress = (const char*)xmlNodeGetContent(childNode); + baseAddress = getNodeContent(childNode); } else if (xmlStrcmp(childNode->name, BAD_CAST "Range") == 0) { - range = (const char*)xmlNodeGetContent(childNode); + range = getNodeContent(childNode); } else if (xmlStrcmp(childNode->name, BAD_CAST "register") == 0) { - std::string offset = (const char*)xmlGetProp(childNode, BAD_CAST "offset"); - std::string regName = (const char*)xmlGetProp(childNode, BAD_CAST "name"); - std::string access = (const char*)xmlGetProp(childNode, BAD_CAST "access"); - std::string description = - (const char*)xmlGetProp(childNode, BAD_CAST "description"); - std::string regRange = (const char*)xmlGetProp(childNode, BAD_CAST "range"); + std::string offset = getNodeProp(childNode, "offset"); + std::string regName = getNodeProp(childNode, "name"); + std::string access = getNodeProp(childNode, "access"); + std::string description = getNodeProp(childNode, "description"); + std::string regRange = getNodeProp(childNode, "range"); Register reg; - reg.setOffset(std::stoi(offset, nullptr, 16)); + reg.setOffset(parseU32(offset)); reg.setRegisterName(regName); reg.setRW(access); reg.setDescription(description); - reg.setWidth(std::stoi(regRange)); + reg.setWidth(parseU32(regRange, 32)); registers.push_back(reg); + } else if (xmlStrcmp(childNode->name, BAD_CAST "connection") == 0) { + std::string connPort = getNodeProp(childNode, "port"); + std::string connTarget = getNodeProp(childNode, "target"); + if (!connPort.empty() && !connTarget.empty()) { + connections[connPort] = connTarget; + } + } else if (xmlStrcmp(childNode->name, BAD_CAST "functional_args") == 0) { + for (xmlNode* argNode = childNode->children; argNode; + argNode = argNode->next) { + if (argNode->type != XML_ELEMENT_NODE || + xmlStrcmp(argNode->name, BAD_CAST "arg") != 0) { + continue; + } + FunctionalArg arg; + arg.idx = parseU32(getNodeProp(argNode, "idx")); + arg.name = getNodeProp(argNode, "name"); + arg.type = getNodeProp(argNode, "type"); + arg.offset = parseU32(getNodeProp(argNode, "offset")); + arg.range = parseU32(getNodeProp(argNode, "range"), 32); + arg.readable = parseBoolInt(getNodeProp(argNode, "r")); + arg.writable = parseBoolInt(getNodeProp(argNode, "w")); + arg.port = getNodeProp(argNode, "port"); + functionalArgs.push_back(arg); + } } } } - auto ba = std::stoull(baseAddress, nullptr, 16); - auto r = std::stoull(range, nullptr, 16); - Kernel kernel((ami_device*)nullptr, name, ba, r, registers); + std::sort(functionalArgs.begin(), functionalArgs.end(), + [](const FunctionalArg& a, const FunctionalArg& b) { + return a.idx < b.idx; + }); + auto ba = parseU64(baseAddress); + auto r = parseU64(range); + Kernel kernel(name, ba, r, registers, functionalArgs); + if (!connections.empty()) { + kernel.setConnections(connections); + } kernels[name] = kernel; } else if (kernelNode->type == XML_ELEMENT_NODE && xmlStrcmp(kernelNode->name, BAD_CAST "ClockFrequency") == 0) { - std::string clkFreq = (const char*)xmlNodeGetContent(kernelNode); - this->clockFrequency = std::stoull(clkFreq); - } else if (kernelNode->type == XML_ELEMENT_NODE && - xmlStrcmp(kernelNode->name, BAD_CAST "Type") == 0) { - std::string type = (const char*)xmlNodeGetContent(kernelNode); - this->vrtbinType = (type == "Full") ? VrtbinType::FLAT : VrtbinType::SEGMENTED; + std::string clkFreq = getNodeContent(kernelNode); + this->clockFrequency = parseU64(clkFreq); } else if (kernelNode->type == XML_ELEMENT_NODE && xmlStrcmp(kernelNode->name, BAD_CAST "Platform") == 0) { - std::string platform_ = (const char*)xmlNodeGetContent(kernelNode); + std::string platform_ = getNodeContent(kernelNode); this->platform = (platform_ == "Hardware") ? Platform::HARDWARE : (platform_ == "Emulation") ? Platform::EMULATION : (platform_ == "Simulation") ? Platform::SIMULATION @@ -92,13 +180,13 @@ void XMLParser::parseXML() { childNode = childNode->next) { if (childNode->type == XML_ELEMENT_NODE) { if (xmlStrcmp(childNode->name, BAD_CAST "kernel") == 0) { - kernelName = (const char*)xmlNodeGetContent(childNode); + kernelName = getNodeContent(childNode); } else if (xmlStrcmp(childNode->name, BAD_CAST "interface") == 0) { - qdmaStream = (const char*)xmlNodeGetContent(childNode); + qdmaStream = getNodeContent(childNode); } else if (xmlStrcmp(childNode->name, BAD_CAST "direction") == 0) { - syncTypeStr = (const char*)xmlNodeGetContent(childNode); + syncTypeStr = getNodeContent(childNode); } else if (xmlStrcmp(childNode->name, BAD_CAST "qid") == 0) { - qid = std::stoi(std::string((const char*)xmlNodeGetContent(childNode))); + qid = parseU32(getNodeContent(childNode)); } } } @@ -111,8 +199,6 @@ std::map XMLParser::getKernels() { return kernels; } uint64_t XMLParser::getClockFrequency() { return this->clockFrequency; } -VrtbinType XMLParser::getVrtbinType() { return this->vrtbinType; } - Platform XMLParser::getPlatform() { return this->platform; } std::vector XMLParser::getQdmaConnections() { return this->qdmaConnections; } @@ -121,7 +207,6 @@ XMLParser::~XMLParser() { if (this->document != nullptr) { xmlFreeDoc(this->document); } - xmlCleanupParser(); } -} // namespace vrt \ No newline at end of file +} // namespace vrt diff --git a/vrt/src/qdma/pcie_driver_handler.cpp b/vrt/src/qdma/pcie_driver_handler.cpp index 301ebd95..cf45e2a0 100644 --- a/vrt/src/qdma/pcie_driver_handler.cpp +++ b/vrt/src/qdma/pcie_driver_handler.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,7 +18,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "qdma/pcie_driver_handler.hpp" +#include namespace vrt { diff --git a/vrt/src/qdma/qdma_connection.cpp b/vrt/src/qdma/qdma_connection.cpp index 05280277..eb840462 100644 --- a/vrt/src/qdma/qdma_connection.cpp +++ b/vrt/src/qdma/qdma_connection.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,7 +18,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "qdma/qdma_connection.hpp" +#include namespace vrt { QdmaConnection::QdmaConnection(const std::string& kernel, uint32_t qid, diff --git a/vrt/src/qdma/qdma_intf.cpp b/vrt/src/qdma/qdma_intf.cpp index 704f06e7..780fb766 100644 --- a/vrt/src/qdma/qdma_intf.cpp +++ b/vrt/src/qdma/qdma_intf.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,81 +18,51 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "qdma/qdma_intf.hpp" +#include -namespace vrt { - -QdmaIntf::QdmaIntf(const std::string& bdf) { - this->queueIdx = 0; - this->bdf = bdf; - char* bus = strip(bdf.c_str()); +#include +#include - char formattedQueueName[256]; - sprintf(formattedQueueName, QDMA_DEFAULT_QUEUE, bus); - queueName = std::string(formattedQueueName); - free(bus); +namespace { +constexpr uint32_t kQdmaModeSt = 1u; +constexpr uint32_t kQdmaDirH2C = 1u << 0; +constexpr uint32_t kQdmaDirC2H = 1u << 1; +constexpr uint32_t kQdmaRingSzIdx = 0u; } -QdmaIntf::QdmaIntf(const std::string& bdf, const uint32_t queueIdx) { - this->bdf = bdf; - char* bus = strip(bdf.c_str()); - - char formattedQueueName[256]; - sprintf(formattedQueueName, QDMA_DEFAULT_ST_QUEUE, bus, queueIdx); - queueName = std::string(formattedQueueName); - free(bus); +namespace vrt { - this->queueIdx = queueIdx; +QdmaIntf::QdmaIntf(const vrtd::Device& device, const uint32_t queueIdx, StreamDirection direction) + : queueIdx(queueIdx) { + struct slash_qdma_qpair_add qpair_cfg = {0}; + qpair_cfg.size = sizeof(qpair_cfg); + qpair_cfg.mode = kQdmaModeSt; + qpair_cfg.h2c_ring_sz = kQdmaRingSzIdx; + qpair_cfg.c2h_ring_sz = kQdmaRingSzIdx; + qpair_cfg.cmpt_ring_sz = kQdmaRingSzIdx; + qpair_cfg.dir_mask = (direction == StreamDirection::HOST_TO_DEVICE) + ? kQdmaDirH2C + : kQdmaDirC2H; + + qpair = device.createQdmaQpair(qpair_cfg); + qpair->start(); + qpairFd = qpair->fd(O_CLOEXEC); } -QdmaIntf::~QdmaIntf() {} - -char* QdmaIntf::strip(const char* bdf) { - char* output = (char*)malloc(3 * sizeof(char)); - if (sscanf(bdf, "%2[^:]", output) == 1) { - output[2] = '\0'; +QdmaIntf::~QdmaIntf() { + if (qpairFd >= 0) { + close(qpairFd); + qpairFd = -1; } - return output; -} - -char* QdmaIntf::create_qdma_queue(const char* bdf) { - char* id = strip(bdf); - char qdma_queue_name[12]; - sprintf(qdma_queue_name, QDMA_QUEUE_NAME, id); - char cmd_add[256]; - sprintf(cmd_add, "dma-ctl %s q add idx 0 mode mm dir bi > /dev/null", qdma_queue_name); - system(cmd_add); - usleep(1000); - char cmd_start[256]; - sprintf(cmd_start, "dma-ctl %s q start idx 0 idx_ringsz 15 dir bi > /dev/null", - qdma_queue_name); - system(cmd_start); - usleep(1000); - char* output = (char*)malloc(256 * sizeof(char)); - sprintf(output, QDMA_DEFAULT_QUEUE, id); - free(id); - return output; -} - -int QdmaIntf::delete_qdma_queue(const char* bdf) { - usleep(100000); - char* id = strip(bdf); - char cmd_stop[256]; - char qdma_queue_name[12]; - sprintf(qdma_queue_name, QDMA_QUEUE_NAME, id); - sprintf(cmd_stop, "dma-ctl %s q stop idx 0 dir bi > /dev/null", qdma_queue_name); - system(cmd_stop); - usleep(1000); - char cmd_del[256]; - sprintf(cmd_del, "dma-ctl %s q del idx 0 dir bi > /dev/null", qdma_queue_name); - system(cmd_del); - usleep(1000); - free(id); - return EXIT_SUCCESS; } ssize_t QdmaIntf::write_from_buffer(const char* fname, char* buffer, uint64_t size, uint64_t base) { - int fd = open(queueName.c_str(), O_WRONLY); + if (qpairFd < 0) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "QDMA streaming not initialized"); + return -EIO; + } + int fd = qpairFd; ssize_t rc; uint64_t count = 0; char* buf = buffer; @@ -140,12 +110,16 @@ ssize_t QdmaIntf::write_from_buffer(const char* fname, char* buffer, uint64_t si fname); return -EIO; } - close(fd); return count; } ssize_t QdmaIntf::read_to_buffer(const char* fname, char* buffer, uint64_t size, uint64_t base) { - int fd = open(queueName.c_str(), O_RDONLY); + if (qpairFd < 0) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "QDMA streaming not initialized"); + return -EIO; + } + int fd = qpairFd; ssize_t rc; uint64_t count = 0; char* buf = buffer; @@ -193,24 +167,21 @@ ssize_t QdmaIntf::read_to_buffer(const char* fname, char* buffer, uint64_t size, fname); return -EIO; } - close(fd); return count; } void QdmaIntf::write_buff(char* buffer, uint64_t start_addr, uint64_t size) { utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Writing buffer with size: {x} to {} at address {x}", size, queueName, - start_addr); - write_from_buffer(queueName.c_str(), buffer, size, start_addr); + "Writing buffer with size: {x} at address {x}", size, start_addr); + write_from_buffer("qdma-qpair", buffer, size, start_addr); } void QdmaIntf::read_buff(char* buffer, uint64_t start_addr, uint64_t size) { utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, - "Reading buffer with size: {x} to {} at address {x}", size, queueName, - start_addr); - read_to_buffer(queueName.c_str(), buffer, size, start_addr); + "Reading buffer with size: {x} at address {x}", size, start_addr); + read_to_buffer("qdma-qpair", buffer, size, start_addr); } uint32_t QdmaIntf::getQueueIdx() { return queueIdx; } -} // namespace vrt \ No newline at end of file +} // namespace vrt diff --git a/vrt/src/register/register.cpp b/vrt/src/register/register.cpp index 762dbf8a..885f5e66 100644 --- a/vrt/src/register/register.cpp +++ b/vrt/src/register/register.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,7 +18,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "register/register.hpp" +#include namespace vrt { diff --git a/vrt/src/utils/filesystem_cache.cpp b/vrt/src/utils/filesystem_cache.cpp index aaf54232..e4d465be 100644 --- a/vrt/src/utils/filesystem_cache.cpp +++ b/vrt/src/utils/filesystem_cache.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,7 +18,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "utils/filesystem_cache.hpp" +#include #include #include diff --git a/vrt/src/utils/logger.cpp b/vrt/src/utils/logger.cpp index 56d99004..cddcd9c7 100644 --- a/vrt/src/utils/logger.cpp +++ b/vrt/src/utils/logger.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,7 +18,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "utils/logger.hpp" +#include #include diff --git a/vrt/src/utils/zmq_server.cpp b/vrt/src/utils/zmq_server.cpp index d2afa5b4..f8b9b5ff 100644 --- a/vrt/src/utils/zmq_server.cpp +++ b/vrt/src/utils/zmq_server.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,7 +18,10 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "utils/zmq_server.hpp" +#include + +#include +#include namespace vrt { @@ -39,7 +42,10 @@ void ZmqServer::sendBuffer(const std::string& name, const std::vector& socket.send(data, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in sendBuffer"); + } std::string replyStr(static_cast(reply.data()), reply.size()); } @@ -51,16 +57,29 @@ void ZmqServer::sendCommand(const Json::Value& command) { memcpy(request.data(), commandStr.data(), commandStr.size()); socket.send(request, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in sendCommand"); + } std::string replyStr(static_cast(reply.data()), reply.size()); + if (replyStr != "OK") { + throw std::runtime_error("ZMQ command failed: " + replyStr); + } } uint32_t ZmqServer::fetchScalar(const std::string& function, const std::string& argIdx) { + return fetchScalar(function, argIdx, std::numeric_limits::max()); +} + +uint32_t ZmqServer::fetchScalar(const std::string& function, const std::string& argIdx, uint32_t offset) { Json::Value command; command["command"] = "fetch"; command["type"] = "scalar"; command["function"] = function; command["arg"] = argIdx; + if (offset != std::numeric_limits::max()) { + command["offset"] = offset; + } Json::StreamWriterBuilder writer; std::string commandStr = Json::writeString(writer, command); @@ -70,13 +89,64 @@ uint32_t ZmqServer::fetchScalar(const std::string& function, const std::string& socket.send(request, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in fetchScalar"); + } std::string replyStr(static_cast(reply.data()), reply.size()); Json::Value response; Json::Reader reader; - reader.parse(replyStr, response); + if (!reader.parse(replyStr, response)) { + throw std::runtime_error("Invalid scalar fetch reply (not JSON): " + replyStr); + } + if (response.isObject() && response.isMember("error")) { + throw std::runtime_error("Scalar fetch failed: " + response["error"].asString()); + } + if (!response.isUInt() && !response.isInt()) { + throw std::runtime_error("Invalid scalar fetch reply type"); + } + return response.asUInt(); +} + +uint32_t ZmqServer::readRegister(const std::string& function, uint32_t offset) { + Json::Value command; + command["command"] = "read_register"; + command["function"] = function; + command["offset"] = offset; + + Json::StreamWriterBuilder writer; + std::string commandStr = Json::writeString(writer, command); + zmq::message_t request(commandStr.size()); + memcpy(request.data(), commandStr.c_str(), commandStr.size()); + socket.send(request, zmq::send_flags::none); + + zmq::message_t reply; + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in readRegister"); + } + std::string replyStr(static_cast(reply.data()), reply.size()); + + Json::Value response; + Json::Reader reader; + if (!reader.parse(replyStr, response)) { + throw std::runtime_error("Invalid read_register reply (not JSON): " + replyStr); + } + if (response.isObject() && response.isMember("error")) { + std::string err = response["error"].asString(); + if (response.isMember("function")) { + err += " function=" + response["function"].asString(); + } + if (response.isMember("offset")) { + err += " offset=" + std::to_string(response["offset"].asUInt()); + } + throw std::runtime_error("read_register failed: " + err); + } + if (!response.isUInt() && !response.isInt()) { + throw std::runtime_error("Invalid read_register reply type"); + } return response.asUInt(); } @@ -94,7 +164,10 @@ std::vector ZmqServer::fetchBuffer(const std::string& name) { socket.send(request, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in fetchBuffer"); + } std::string replyStr(static_cast(reply.data()), reply.size()); Json::Value response; @@ -123,7 +196,10 @@ void ZmqServer::sendStream(const std::string& name, const std::vector& socket.send(data, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in sendStream"); + } std::string replyStr(static_cast(reply.data()), reply.size()); } @@ -141,7 +217,10 @@ std::vector ZmqServer::fetchStream(const std::string& name, size_t size socket.send(request, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in fetchStream"); + } std::vector buffer(reply.size()); memcpy(buffer.data(), reply.data(), reply.size()); return buffer; @@ -164,7 +243,10 @@ void ZmqServer::fetchBufferSim(uint64_t addr, uint64_t size, std::vector(reply.data()), reply.size()); Json::Value response; @@ -190,7 +272,10 @@ uint32_t ZmqServer::fetchScalarSim(uint64_t addr) { socket.send(request, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in fetchScalarSim"); + } std::string replyStr(static_cast(reply.data()), reply.size()); Json::Value response; @@ -212,7 +297,10 @@ void ZmqServer::sendBufferSim(uint64_t addr, const std::vector& buffer) socket.send(dataMsg, zmq::send_flags::none); zmq::message_t reply; - socket.recv(reply); + auto recvResult = socket.recv(reply); + if (!recvResult) { + throw std::runtime_error("ZMQ recv failed in sendBufferSim"); + } std::string replyStr(static_cast(reply.data()), reply.size()); } @@ -225,4 +313,4 @@ void ZmqServer::sendScalar(uint64_t addr, uint32_t value) { sendCommand(command); } -} // namespace vrt \ No newline at end of file +} // namespace vrt diff --git a/vrt/src/vrtbin.cpp b/vrt/src/vrtbin.cpp new file mode 100644 index 00000000..837fa256 --- /dev/null +++ b/vrt/src/vrtbin.cpp @@ -0,0 +1,578 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file vrtbin.cpp + * @brief Vrtbin archive extraction and metadata discovery. + */ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +namespace vrt { + +namespace { + +constexpr std::size_t TAR_BLOCK_SIZE = 512; +constexpr char TAR_LONGNAME_TYPE = 'L'; + +struct TarHeader { + char name[100]; + char mode[8]; + char uid[8]; + char gid[8]; + char size[12]; + char mtime[12]; + char chksum[8]; + char typeflag; + char linkname[100]; + char magic[6]; + char version[2]; + char uname[32]; + char gname[32]; + char devmajor[8]; + char devminor[8]; + char prefix[155]; + char pad[12]; +}; +static_assert(sizeof(TarHeader) == TAR_BLOCK_SIZE, "Invalid tar header size"); + +bool isZeroBlock(const std::array& block) { + return std::all_of(block.begin(), block.end(), [](char c) { return c == '\0'; }); +} + +bool hasGzipMagic(const std::string& path) { + std::ifstream file(path, std::ios::binary); + if (!file.is_open()) { + return false; + } + std::array magic{}; + file.read(reinterpret_cast(magic.data()), static_cast(magic.size())); + return file.gcount() == static_cast(magic.size()) && magic[0] == 0x1Fu && + magic[1] == 0x8Bu; +} + +uint64_t parseOctal(const char* field, std::size_t len) { + uint64_t value = 0; + bool seenDigit = false; + for (std::size_t i = 0; i < len; ++i) { + const unsigned char c = static_cast(field[i]); + if (c == '\0' || c == ' ') { + if (seenDigit) { + break; + } + continue; + } + if (c < '0' || c > '7') { + break; + } + seenDigit = true; + value = (value << 3) | static_cast(c - '0'); + } + return value; +} + +std::string readField(const char* field, std::size_t len) { + std::size_t n = 0; + while (n < len && field[n] != '\0') { + ++n; + } + return std::string(field, field + n); +} + +void streamSkip(std::istream& stream, uint64_t size) { + static constexpr std::streamsize CHUNK = 1 << 20; + while (size > 0) { + const std::streamsize chunk = + static_cast(std::min(size, static_cast(CHUNK))); + stream.ignore(chunk); + if (stream.gcount() != chunk) { + throw std::runtime_error("Unexpected EOF while skipping tar payload"); + } + size -= static_cast(chunk); + } +} + +void streamCopy(std::istream& src, std::ostream& dst, uint64_t size) { + std::array buffer{}; + while (size > 0) { + const std::size_t chunk = static_cast( + std::min(size, static_cast(buffer.size()))); + src.read(buffer.data(), static_cast(chunk)); + if (src.gcount() != static_cast(chunk)) { + throw std::runtime_error("Unexpected EOF while reading tar entry"); + } + dst.write(buffer.data(), static_cast(chunk)); + if (!dst) { + throw std::runtime_error("Failed writing extracted tar entry"); + } + size -= static_cast(chunk); + } +} + +void decompressGzipToTar(const std::string& gzipPath, const std::filesystem::path& tarPath) { + gzFile gz = gzopen(gzipPath.c_str(), "rb"); + if (gz == nullptr) { + throw std::runtime_error("Cannot open gzip archive: " + gzipPath); + } + + std::ofstream out(tarPath, std::ios::binary | std::ios::trunc); + if (!out.is_open()) { + gzclose(gz); + throw std::runtime_error("Failed to create temporary tar stream: " + tarPath.string()); + } + + std::array buffer{}; + while (true) { + const int bytesRead = gzread(gz, buffer.data(), static_cast(buffer.size())); + if (bytesRead > 0) { + out.write(buffer.data(), static_cast(bytesRead)); + if (!out) { + gzclose(gz); + throw std::runtime_error("Failed writing temporary tar stream: " + + tarPath.string()); + } + continue; + } + if (bytesRead == 0) { + break; + } + + int zerr = Z_OK; + const char* zmsg = gzerror(gz, &zerr); + const std::string err = zmsg == nullptr ? "unknown gzip error" : zmsg; + gzclose(gz); + throw std::runtime_error("Failed to decompress gzip archive: " + err); + } + + const int closeRc = gzclose(gz); + if (closeRc != Z_OK) { + throw std::runtime_error("Failed to finalize gzip decompression"); + } +} + +bool hasValidTarChecksum(const std::array& raw) { + TarHeader header{}; + std::memcpy(&header, raw.data(), sizeof(header)); + const uint64_t expected = parseOctal(header.chksum, sizeof(header.chksum)); + + uint64_t actual = 0; + for (std::size_t i = 0; i < raw.size(); ++i) { + if (i >= 148 && i < 156) { + actual += static_cast(' '); + } else { + actual += static_cast(raw[i]); + } + } + return expected == actual; +} + +std::filesystem::path sanitizeArchivePath(const std::string& entryName) { + std::filesystem::path path(entryName); + path = path.lexically_normal(); + if (path.empty() || path == ".") { + return {}; + } + if (path.is_absolute()) { + throw std::runtime_error("Tar archive contains absolute path entry: " + entryName); + } + for (const auto& part : path) { + if (part == "..") { + throw std::runtime_error("Tar archive contains parent path traversal: " + entryName); + } + } + return path; +} + +bool isRegularTarType(char typeflag) { + return typeflag == REGTYPE || typeflag == AREGTYPE || typeflag == '\0'; +} + +std::filesystem::perms tarModeToPerms(uint64_t mode) { + std::filesystem::perms perms = std::filesystem::perms::none; + if ((mode & 0400u) != 0u) perms |= std::filesystem::perms::owner_read; + if ((mode & 0200u) != 0u) perms |= std::filesystem::perms::owner_write; + if ((mode & 0100u) != 0u) perms |= std::filesystem::perms::owner_exec; + if ((mode & 0040u) != 0u) perms |= std::filesystem::perms::group_read; + if ((mode & 0020u) != 0u) perms |= std::filesystem::perms::group_write; + if ((mode & 0010u) != 0u) perms |= std::filesystem::perms::group_exec; + if ((mode & 0004u) != 0u) perms |= std::filesystem::perms::others_read; + if ((mode & 0002u) != 0u) perms |= std::filesystem::perms::others_write; + if ((mode & 0001u) != 0u) perms |= std::filesystem::perms::others_exec; + if ((mode & 04000u) != 0u) perms |= std::filesystem::perms::set_uid; + if ((mode & 02000u) != 0u) perms |= std::filesystem::perms::set_gid; + if ((mode & 01000u) != 0u) perms |= std::filesystem::perms::sticky_bit; + return perms; +} + +} // namespace + +Vrtbin::Vrtbin(std::string vrtbinPath, const std::string& bdf) { + this->vrtbinPath = vrtbinPath; + if (!std::filesystem::exists(vrtbinPath)) { + throw std::runtime_error(vrtbinPath + " does not exist"); + } + + const std::filesystem::path metadataPath = + FilesystemCache::getCachePath() / ("metadata_" + sanitizeForPath(bdf)); + std::error_code metadataEc; + std::filesystem::create_directories(metadataPath, metadataEc); + if (metadataEc) { + throw std::runtime_error("Failed to initialize metadata path: " + metadataPath.string()); + } + + this->tempExtractPath = + (FilesystemCache::getCachePath() / ("vrtbin_" + sanitizeForPath(bdf))).string(); + this->systemMapPath = (metadataPath / "system_map.xml").string(); + + extract(); + discoverPdiFiles(); + + const std::filesystem::path tempSystemMapPath = findExtractedFile("system_map.xml"); + if (tempSystemMapPath.empty()) { + throw std::runtime_error("system_map.xml not found in tar archive: " + vrtbinPath); + } + XMLParser parser(tempSystemMapPath.string()); + parser.parseXML(); + this->platform = parser.getPlatform(); + copy(tempSystemMapPath.string(), systemMapPath); + + const std::filesystem::path reportPath = + findExtractedFileByPrefix("report_utilization", ".xml"); + if (!reportPath.empty()) { + utilizationReportPath = (metadataPath / "report_utilization.xml").string(); + copy(reportPath.string(), utilizationReportPath); + } + + if (this->platform == Platform::HARDWARE) { + if (pdiPaths.empty()) { + throw std::runtime_error("No .pdi files found in tar archive: " + vrtbinPath); + } + } else if (this->platform == Platform::EMULATION) { + const std::filesystem::path emuPath = findExtractedFile("vpp_emu"); + emulationExecPath = emuPath.empty() ? std::string() : emuPath.string(); + const std::filesystem::path emuManifestPath = findExtractedFile("emu_manifest.json"); + if (!emuManifestPath.empty()) { + emulationManifestPath = (metadataPath / "emu_manifest.json").string(); + copy(emuManifestPath.string(), emulationManifestPath); + } + + } else { + const std::filesystem::path simPath = findExtractedFile("vpp_sim"); + simulationExecPath = simPath.empty() ? std::string() : simPath.string(); + } +} + +void Vrtbin::extract() { + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Extracting vrtbin: {}", + vrtbinPath); + std::error_code ec; + std::filesystem::remove_all(tempExtractPath, ec); + std::filesystem::create_directories(tempExtractPath, ec); + if (ec) { + throw std::runtime_error("Failed to initialize extraction path: " + tempExtractPath); + } + + std::filesystem::path archivePath = vrtbinPath; + bool cleanupArchivePath = false; + if (hasGzipMagic(vrtbinPath)) { + archivePath = std::filesystem::path(tempExtractPath).parent_path() / + (std::filesystem::path(tempExtractPath).filename().string() + ".tmp.tar"); + cleanupArchivePath = true; + try { + decompressGzipToTar(vrtbinPath, archivePath); + } catch (...) { + std::error_code cleanupEc; + std::filesystem::remove(archivePath, cleanupEc); + throw; + } + } + auto cleanupArchive = [&]() { + if (!cleanupArchivePath) { + return; + } + std::error_code cleanupEc; + std::filesystem::remove(archivePath, cleanupEc); + }; + + std::ifstream archive(archivePath, std::ios::binary); + if (!archive.is_open()) { + cleanupArchive(); + throw std::runtime_error("Cannot open tar archive: " + archivePath.string()); + } + + try { + std::string pendingLongName; + while (true) { + std::array raw{}; + archive.read(raw.data(), static_cast(raw.size())); + if (archive.gcount() == 0) { + break; + } + if (archive.gcount() != static_cast(raw.size())) { + throw std::runtime_error("Invalid tar archive: truncated header"); + } + if (isZeroBlock(raw)) { + break; + } + if (!hasValidTarChecksum(raw)) { + throw std::runtime_error("Invalid tar archive: header checksum mismatch"); + } + + TarHeader header{}; + std::memcpy(&header, raw.data(), sizeof(header)); + + uint64_t payloadSize = parseOctal(header.size, sizeof(header.size)); + const uint64_t headerSize = payloadSize; + char typeflag = header.typeflag; + std::string entryName; + if (!pendingLongName.empty()) { + entryName = pendingLongName; + pendingLongName.clear(); + } else { + std::string name = readField(header.name, sizeof(header.name)); + std::string prefix = readField(header.prefix, sizeof(header.prefix)); + entryName = prefix.empty() ? name : (prefix + "/" + name); + } + + if (typeflag == TAR_LONGNAME_TYPE) { + std::string longName(payloadSize, '\0'); + if (payloadSize > 0) { + archive.read(longName.data(), static_cast(payloadSize)); + if (archive.gcount() != static_cast(payloadSize)) { + throw std::runtime_error("Invalid tar archive: truncated long name"); + } + } + std::size_t nul = longName.find('\0'); + if (nul != std::string::npos) { + longName.resize(nul); + } + pendingLongName = longName; + payloadSize = 0; + } else { + const std::filesystem::path relPath = sanitizeArchivePath(entryName); + if (!relPath.empty()) { + const std::filesystem::path outPath = + std::filesystem::path(tempExtractPath) / relPath; + if (typeflag == DIRTYPE) { + std::filesystem::create_directories(outPath); + } else if (isRegularTarType(typeflag)) { + const auto parent = outPath.parent_path(); + if (!parent.empty()) { + std::filesystem::create_directories(parent); + } + std::ofstream out(outPath, std::ios::binary | std::ios::trunc); + if (!out.is_open()) { + throw std::runtime_error("Failed to create extracted file: " + + outPath.string()); + } + streamCopy(archive, out, payloadSize); + out.flush(); + if (!out) { + throw std::runtime_error("Failed writing extracted file: " + + outPath.string()); + } + out.close(); + if (!out) { + throw std::runtime_error("Failed closing extracted file: " + + outPath.string()); + } + std::error_code permEc; + const uint64_t mode = parseOctal(header.mode, sizeof(header.mode)); + std::filesystem::permissions( + outPath, tarModeToPerms(mode), + std::filesystem::perm_options::replace, permEc); + if (permEc) { + throw std::runtime_error( + "Failed setting permissions on extracted file " + outPath.string() + + ": " + permEc.message()); + } + payloadSize = 0; + } + } + } + + if (payloadSize > 0) { + streamSkip(archive, payloadSize); + } + const uint64_t padding = + (TAR_BLOCK_SIZE - (headerSize % TAR_BLOCK_SIZE)) % TAR_BLOCK_SIZE; + if (padding > 0) { + streamSkip(archive, padding); + } + } + } catch (...) { + cleanupArchive(); + throw; + } + cleanupArchive(); +} + +void Vrtbin::copy(const std::string& source, const std::string& destination) { + utils::Logger::log(utils::LogLevel::DEBUG, __PRETTY_FUNCTION__, "Copying file {} to {}", source, + destination); + std::ifstream src(source, std::ios::binary); + if (!src) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Error opening source file: {}", source); + throw std::runtime_error("Error opening source file"); + } + + std::ofstream dest(destination, std::ios::binary); + if (!dest) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Error opening destination file: {}", destination); + throw std::runtime_error("Error opening destination file"); + } + + dest << src.rdbuf(); + + if (!src) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Error reading from source file: {}", source); + throw std::runtime_error("Error reading from source file"); + } + + if (!dest) { + utils::Logger::log(utils::LogLevel::ERROR, __PRETTY_FUNCTION__, + "Error writing to destination file: {}", destination); + throw std::runtime_error("Error writing to destination file"); + } +} + +std::string Vrtbin::getSystemMapPath() { return systemMapPath; } +std::string Vrtbin::getPdiPath() { return pdiPath; } +std::vector Vrtbin::getPdiPaths() { return pdiPaths; } + +std::string Vrtbin::getEmulationExec() { return emulationExecPath; } + +std::string Vrtbin::getEmulationManifest() { return emulationManifestPath; } + +std::string Vrtbin::getSimulationExec() { return simulationExecPath; } + +Platform Vrtbin::getPlatform() const { return platform; } + +void Vrtbin::discoverPdiFiles() { + pdiPaths.clear(); + + if (!std::filesystem::exists(tempExtractPath)) { + return; + } + + for (const auto& entry : + std::filesystem::recursive_directory_iterator(tempExtractPath)) { + if (!entry.is_regular_file()) { + continue; + } + std::string ext = entry.path().extension().string(); + std::transform(ext.begin(), ext.end(), ext.begin(), + [](unsigned char c) { return static_cast(std::tolower(c)); }); + if (ext == ".pdi") { + pdiPaths.push_back(entry.path().string()); + } + } + + std::sort(pdiPaths.begin(), pdiPaths.end()); + if (pdiPaths.empty()) { + pdiPath.clear(); + return; + } + + auto preferred = std::find_if(pdiPaths.begin(), pdiPaths.end(), [](const std::string& p) { + return std::filesystem::path(p).filename() == "design.pdi"; + }); + if (preferred != pdiPaths.end() && preferred != pdiPaths.begin()) { + std::iter_swap(pdiPaths.begin(), preferred); + } + pdiPath = pdiPaths.front(); +} + +std::filesystem::path Vrtbin::findExtractedFile(const std::string& filename) const { + const std::filesystem::path direct = std::filesystem::path(tempExtractPath) / filename; + if (std::filesystem::exists(direct)) { + return direct; + } + if (!std::filesystem::exists(tempExtractPath)) { + return {}; + } + for (const auto& entry : + std::filesystem::recursive_directory_iterator(tempExtractPath)) { + if (entry.is_regular_file() && entry.path().filename() == filename) { + return entry.path(); + } + } + return {}; +} + +std::string Vrtbin::sanitizeForPath(const std::string& input) { + std::string out; + out.reserve(input.size()); + for (char c : input) { + if (std::isalnum(static_cast(c)) != 0) { + out.push_back(c); + } else { + out.push_back('_'); + } + } + return out.empty() ? std::string("default") : out; +} + +std::string Vrtbin::getUtilizationReportPath() const { return utilizationReportPath; } + +std::filesystem::path Vrtbin::findExtractedFileByPrefix(const std::string& prefix, + const std::string& extension) const { + if (!std::filesystem::exists(tempExtractPath)) { + return {}; + } + for (const auto& entry : std::filesystem::recursive_directory_iterator(tempExtractPath)) { + if (!entry.is_regular_file()) { + continue; + } + const std::string fname = entry.path().filename().string(); + if (fname.size() >= prefix.size() && fname.rfind(prefix, 0) == 0 && + entry.path().extension().string() == extension) { + return entry.path(); + } + } + return {}; +} + +std::string Vrtbin::getSystemMapPathFromBdf(const std::string& bdf) { + return (FilesystemCache::getCachePath() / ("metadata_" + sanitizeForPath(bdf)) / "system_map.xml").string(); +} + +std::string Vrtbin::getUtilizationReportPathFromBdf(const std::string& bdf) { + return (FilesystemCache::getCachePath() / ("metadata_" + sanitizeForPath(bdf)) / + "report_utilization.xml") + .string(); +} + +} // namespace vrt diff --git a/vrt/tests/CMakeLists.txt b/vrt/tests/CMakeLists.txt new file mode 100644 index 00000000..267425e6 --- /dev/null +++ b/vrt/tests/CMakeLists.txt @@ -0,0 +1,92 @@ +include(FetchContent) +FetchContent_Declare( + googletest + URL https://github.com/google/googletest/archive/refs/tags/v1.17.0.zip +) +FetchContent_MakeAvailable(googletest) + +enable_testing() + +include(GoogleTest) + +add_custom_target(unit_tests) + +macro(add_vrt_test test_name test_source) + add_executable(${test_name} ${test_source}) + target_link_libraries(${test_name} PRIVATE GTest::gtest_main GTest::gmock vrt::vrt) + gtest_discover_tests(${test_name}) + add_dependencies(unit_tests ${test_name}) +endmacro() + +add_vrt_test(register_test register_test.cpp) +add_vrt_test(qdma_connection_test qdma_connection_test.cpp) +add_vrt_test(logger_test logger_test.cpp) +add_vrt_test(utilization_data_test utilization_data_test.cpp) +add_vrt_test(filesystem_cache_test filesystem_cache_test.cpp) +add_vrt_test(xml_parser_test xml_parser_test.cpp) +add_vrt_test(utilization_parser_test utilization_parser_test.cpp) +add_vrt_test(kernel_test kernel_test.cpp) +add_vrt_test(vrtbin_test vrtbin_test.cpp) + +# --- Stub VBIN generation --- +set(STUB_VBIN_DIR ${CMAKE_CURRENT_SOURCE_DIR}/fixtures/stub_vbin) + +set(STUB_EMU_VBIN ${CMAKE_CURRENT_BINARY_DIR}/stub_emu.vbin) +add_custom_command( + OUTPUT ${STUB_EMU_VBIN} + COMMAND ${CMAKE_COMMAND} -E rm -rf ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging + COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging + COMMAND ${CMAKE_COMMAND} -E copy + ${STUB_VBIN_DIR}/system_map_emu.xml + ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging/system_map.xml + COMMAND ${CMAKE_COMMAND} -E copy + ${STUB_VBIN_DIR}/emu_manifest.json + ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging/emu_manifest.json + COMMAND ${CMAKE_COMMAND} -E copy + ${STUB_VBIN_DIR}/vrt_stub_server.py + ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging/vpp_emu + COMMAND chmod +x ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging/vpp_emu + COMMAND tar cf ${STUB_EMU_VBIN} + -C ${CMAKE_CURRENT_BINARY_DIR}/stub_emu_staging . + DEPENDS + ${STUB_VBIN_DIR}/system_map_emu.xml + ${STUB_VBIN_DIR}/emu_manifest.json + ${STUB_VBIN_DIR}/vrt_stub_server.py + COMMENT "Creating emulation stub VBIN" +) + +set(STUB_SIM_VBIN ${CMAKE_CURRENT_BINARY_DIR}/stub_sim.vbin) +add_custom_command( + OUTPUT ${STUB_SIM_VBIN} + COMMAND ${CMAKE_COMMAND} -E rm -rf ${CMAKE_CURRENT_BINARY_DIR}/stub_sim_staging + COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/stub_sim_staging + COMMAND ${CMAKE_COMMAND} -E copy + ${STUB_VBIN_DIR}/system_map_sim.xml + ${CMAKE_CURRENT_BINARY_DIR}/stub_sim_staging/system_map.xml + COMMAND ${CMAKE_COMMAND} -E copy + ${STUB_VBIN_DIR}/vrt_stub_server.py + ${CMAKE_CURRENT_BINARY_DIR}/stub_sim_staging/vpp_sim + COMMAND chmod +x ${CMAKE_CURRENT_BINARY_DIR}/stub_sim_staging/vpp_sim + COMMAND tar cf ${STUB_SIM_VBIN} + -C ${CMAKE_CURRENT_BINARY_DIR}/stub_sim_staging . + DEPENDS + ${STUB_VBIN_DIR}/system_map_sim.xml + ${STUB_VBIN_DIR}/vrt_stub_server.py + COMMENT "Creating simulation stub VBIN" +) + +add_custom_target(stub_vbins DEPENDS ${STUB_EMU_VBIN} ${STUB_SIM_VBIN}) + +macro(add_vrt_vbin_test test_name test_source) + add_executable(${test_name} ${test_source}) + target_link_libraries(${test_name} PRIVATE GTest::gtest_main GTest::gmock vrt::vrt) + target_compile_definitions(${test_name} PRIVATE + STUB_EMU_VBIN_PATH="${STUB_EMU_VBIN}" + STUB_SIM_VBIN_PATH="${STUB_SIM_VBIN}") + add_dependencies(${test_name} stub_vbins) + gtest_discover_tests(${test_name}) + add_dependencies(unit_tests ${test_name}) +endmacro() + +add_vrt_vbin_test(vrtbin_integration_test vrtbin_integration_test.cpp) +add_vrt_vbin_test(device_test device_test.cpp) diff --git a/vrt/tests/device_test.cpp b/vrt/tests/device_test.cpp new file mode 100644 index 00000000..a433cb8c --- /dev/null +++ b/vrt/tests/device_test.cpp @@ -0,0 +1,231 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "test_helpers.hpp" + +using ::testing::Contains; + +// The vbin integration tests launch a Python ZeroMQ stub server +// (tests/fixtures/stub_vbin/vrt_stub_server.py) to emulate the FPGA runtime, which requires +// pyzmq. This meta-test verifies the dependency is present and fails fast with a clear +// diagnostic if it is missing. +TEST(PythonEnvTest, PyzmqIsImportable) { + int rc = std::system("python3 -c 'import zmq' >/dev/null 2>&1"); + int exit_status = WIFEXITED(rc) ? WEXITSTATUS(rc) : -1; + ASSERT_EQ(exit_status, 0) + << "pyzmq is not importable in the active Python environment.\n" + << "It is required by the Python stub server used by the VRT vbin integration tests.\n" + << "Install it with: pip install pyzmq"; +} + +class DeviceTest : public ::testing::Test, public ::testing::WithParamInterface { + protected: + std::filesystem::path tmpDir; + ScopedEnv* envCache = nullptr; + vrt::Platform platform; + vrt::Device device; + + void SetUp() override { + tmpDir = makeTempDir("device-test"); + envCache = new ScopedEnv("SLASH_CACHE_PATH", tmpDir.string()); + + platform = GetParam(); + std::array supported_platforms{vrt::Platform::EMULATION, vrt::Platform::SIMULATION}; + EXPECT_THAT(supported_platforms, Contains(platform)); + + std::string vbin_path; + if (platform == vrt::Platform::EMULATION) { + vbin_path = STUB_EMU_VBIN_PATH; + } else { + vbin_path = STUB_SIM_VBIN_PATH; + } + device = vrt::Device("0000:00:00", vbin_path, false); + std::this_thread::sleep_for(std::chrono::milliseconds(500)); + } + + void TearDown() override { + device.cleanup(); + delete envCache; + std::filesystem::remove_all(tmpDir); + } +}; + +TEST_P(DeviceTest, Construction) { + SUCCEED(); +} + +TEST_P(DeviceTest, GetPlatform) { + EXPECT_EQ(device.getPlatform(), platform); +} + +TEST_P(DeviceTest, GetFrequency) { + EXPECT_EQ(device.getFrequency(), 0u); +} + +TEST_P(DeviceTest, GetKernelVadd) { + auto kernel = device.getKernel("vadd"); + EXPECT_EQ(kernel.getName(), "vadd"); + EXPECT_EQ(kernel.getPhysAddr(), 0x10000u); +} + +TEST_P(DeviceTest, GetKernelPassthrough) { + auto kernel = device.getKernel("passthrough"); + EXPECT_EQ(kernel.getName(), "passthrough"); + EXPECT_EQ(kernel.getPhysAddr(), 0x20000u); +} + +TEST_P(DeviceTest, GetKernelUnknownThrows) { + EXPECT_THROW(device.getKernel("nonexistent"), std::runtime_error); +} + +TEST_P(DeviceTest, GetQdmaConnections) { + auto conns = device.getHandle()->getQdmaConnections(); + ASSERT_EQ(conns.size(), 2u); + EXPECT_EQ(conns[0].getKernel(), "vadd"); + EXPECT_EQ(conns[0].getInterface(), "axis_in"); + EXPECT_EQ(conns[0].getDirection(), vrt::StreamDirection::HOST_TO_DEVICE); + EXPECT_EQ(conns[0].getQid(), 0u); + EXPECT_EQ(conns[1].getInterface(), "axis_out"); + EXPECT_EQ(conns[1].getDirection(), vrt::StreamDirection::DEVICE_TO_HOST); + EXPECT_EQ(conns[1].getQid(), 1u); +} + +TEST_P(DeviceTest, KernelWrite) { + auto kernel = device.getKernel("vadd"); + EXPECT_NO_THROW(kernel.write(0x10, 0xDEAD)); +} + +TEST_P(DeviceTest, KernelRead) { + auto kernel = device.getKernel("vadd"); + uint32_t val = kernel.read(0x10); + EXPECT_EQ(val, 0u); +} + +TEST_P(DeviceTest, BufferDDRConstruction) { + EXPECT_NO_THROW({ + vrt::Buffer buf(device, 64, vrt::MemoryRangeType::DDR); + }); +} + +TEST_P(DeviceTest, BufferHBMWithPort) { + EXPECT_NO_THROW({ + vrt::Buffer buf(device, 64, vrt::MemoryRangeType::HBM, 0); + }); +} + +TEST_P(DeviceTest, BufferHBMVnoc) { + EXPECT_NO_THROW({ + vrt::Buffer buf(device, 64, vrt::MemoryRangeType::HBM_VNOC); + }); +} + +TEST_P(DeviceTest, BufferSyncRoundTrip) { + vrt::Buffer buf(device, 4, vrt::MemoryRangeType::DDR); + buf[0] = 10; + buf[1] = 20; + buf[2] = 30; + buf[3] = 40; + buf.sync(vrt::SyncType::HOST_TO_DEVICE); + buf[0] = 0; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + buf.sync(vrt::SyncType::DEVICE_TO_HOST); + EXPECT_EQ(buf[0], 10); + EXPECT_EQ(buf[1], 20); + EXPECT_EQ(buf[2], 30); + EXPECT_EQ(buf[3], 40); +} + +TEST_P(DeviceTest, StreamingBufferH2D) { + if (platform == vrt::Platform::SIMULATION) { + GTEST_SKIP(); + } + auto kernel = device.getKernel("vadd"); + vrt::StreamingBuffer sbuf(device, kernel, "axis_in", 16); + sbuf[0] = 42; + EXPECT_NO_THROW(sbuf.sync()); +} + +TEST_P(DeviceTest, StreamingBufferD2H) { + if (platform == vrt::Platform::SIMULATION) { + GTEST_SKIP(); + } + auto kernel = device.getKernel("vadd"); + vrt::StreamingBuffer sbuf(device, kernel, "axis_out", 16); + EXPECT_NO_THROW(sbuf.sync()); +} + +TEST_P(DeviceTest, StreamingBufferWrongPortThrows) { + if (platform == vrt::Platform::SIMULATION) { + GTEST_SKIP(); + } + auto kernel = device.getKernel("vadd"); + EXPECT_THROW( + vrt::StreamingBuffer(device, kernel, "nonexistent_port", 16), + std::runtime_error); +} + +TEST_P(DeviceTest, StreamingBufferThrowsNotImplemented) { + if (platform != vrt::Platform::SIMULATION) { + GTEST_SKIP(); + } + auto kernel = device.getKernel("vadd"); + vrt::StreamingBuffer sbuf(device, kernel, "axis_in", 16); + EXPECT_THROW(sbuf.sync(), std::runtime_error); +} + +TEST_P(DeviceTest, KernelVaddRoundTrip) { + constexpr int N = 4; + vrt::Kernel kernel = device.getKernel("vadd"); + vrt::Buffer in1(device, N, vrt::MemoryRangeType::HBM, 0); + vrt::Buffer in2(device, N, vrt::MemoryRangeType::DDR); + vrt::Buffer out(device, N, vrt::MemoryRangeType::HBM_VNOC); + + for (int i = 0; i < N; ++i) { + in1[i] = i + 1; + in2[i] = (i + 1) * 10; + } + in1.sync(vrt::SyncType::HOST_TO_DEVICE); + in2.sync(vrt::SyncType::HOST_TO_DEVICE); + + kernel.setArg(0, static_cast(in1.getPhysAddr())); + kernel.setArg(1, static_cast(in2.getPhysAddr())); + kernel.setArg(2, static_cast(out.getPhysAddr())); + kernel.setArg(3, static_cast(N)); + ASSERT_NO_THROW(kernel.call()); + + out.sync(vrt::SyncType::DEVICE_TO_HOST); + for (int i = 0; i < N; ++i) { + EXPECT_EQ(out[i], in1[i] + in2[i]); + } +} + +INSTANTIATE_TEST_SUITE_P(DeviceTestSuite, DeviceTest, ::testing::Values(vrt::Platform::EMULATION, vrt::Platform::SIMULATION)); diff --git a/vrt/tests/filesystem_cache_test.cpp b/vrt/tests/filesystem_cache_test.cpp new file mode 100644 index 00000000..dd86926a --- /dev/null +++ b/vrt/tests/filesystem_cache_test.cpp @@ -0,0 +1,130 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +#include +#include + +#include "test_helpers.hpp" + +class FilesystemCacheTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + + ScopedEnv* envSlashCache = nullptr; + ScopedEnv* envXdgCache = nullptr; + ScopedEnv* envHome = nullptr; + ScopedEnv* envSlashRuntime = nullptr; + ScopedEnv* envXdgRuntime = nullptr; + + void SetUp() override { tmpDir = makeTempDir("fscache-test"); } + + void TearDown() override { + delete envSlashCache; + delete envXdgCache; + delete envHome; + delete envSlashRuntime; + delete envXdgRuntime; + std::filesystem::remove_all(tmpDir); + } + + void clearCacheEnvVars() { + envSlashCache = new ScopedEnv("SLASH_CACHE_PATH"); + envXdgCache = new ScopedEnv("XDG_CACHE_HOME"); + envHome = new ScopedEnv("HOME"); + } + + void clearRuntimeEnvVars() { + envSlashRuntime = new ScopedEnv("SLASH_RUNTIME_PATH"); + envXdgRuntime = new ScopedEnv("XDG_RUNTIME_DIR"); + } +}; + +TEST_F(FilesystemCacheTest, CachePathFromSlashCachePath) { + clearCacheEnvVars(); + std::string target = (tmpDir / "slash-cache").string(); + ScopedEnv env("SLASH_CACHE_PATH", target); + auto path = FilesystemCache::getCachePath(); + EXPECT_EQ(path, std::filesystem::path(target)); +} + +TEST_F(FilesystemCacheTest, CachePathFromXdgCacheHome) { + clearCacheEnvVars(); + std::string xdg = (tmpDir / "xdg-cache").string(); + ScopedEnv env("XDG_CACHE_HOME", xdg); + auto path = FilesystemCache::getCachePath(); + EXPECT_EQ(path, std::filesystem::path(xdg) / "SLASH" / "vrt"); +} + +TEST_F(FilesystemCacheTest, CachePathFromHome) { + clearCacheEnvVars(); + std::string home = (tmpDir / "home").string(); + ScopedEnv env("HOME", home); + auto path = FilesystemCache::getCachePath(); + EXPECT_EQ(path, std::filesystem::path(home) / ".cache" / "SLASH" / "vrt"); +} + +TEST_F(FilesystemCacheTest, CachePathFallback) { + clearCacheEnvVars(); + auto path = FilesystemCache::getCachePath(); + std::string expected = "/tmp/SLASH-cache-" + std::to_string(getuid()) + "/vrt"; + EXPECT_EQ(path, std::filesystem::path(expected)); +} + +TEST_F(FilesystemCacheTest, RuntimePathFromSlashRuntimePath) { + clearRuntimeEnvVars(); + std::string target = (tmpDir / "slash-runtime").string(); + ScopedEnv env("SLASH_RUNTIME_PATH", target); + auto path = FilesystemCache::getRuntimePath(); + EXPECT_EQ(path, std::filesystem::path(target)); +} + +TEST_F(FilesystemCacheTest, RuntimePathFromXdgRuntimeDir) { + clearRuntimeEnvVars(); + std::string xdg = (tmpDir / "xdg-runtime").string(); + ScopedEnv env("XDG_RUNTIME_DIR", xdg); + auto path = FilesystemCache::getRuntimePath(); + EXPECT_EQ(path, std::filesystem::path(xdg) / "SLASH" / "vrt"); +} + +TEST_F(FilesystemCacheTest, RuntimePathFallback) { + clearRuntimeEnvVars(); + ScopedEnv envHome("HOME"); + auto path = FilesystemCache::getRuntimePath(); + std::string expected = "/tmp/SLASH-run-" + std::to_string(getuid()) + "/vrt"; + EXPECT_EQ(path, std::filesystem::path(expected)); +} + +TEST_F(FilesystemCacheTest, CachePathCreatesDirectory) { + clearCacheEnvVars(); + std::string target = (tmpDir / "new-cache-dir").string(); + ScopedEnv env("SLASH_CACHE_PATH", target); + auto path = FilesystemCache::getCachePath(); + EXPECT_TRUE(std::filesystem::is_directory(path)); +} + +TEST_F(FilesystemCacheTest, RuntimePathCreatesDirectory) { + clearRuntimeEnvVars(); + std::string target = (tmpDir / "new-runtime-dir").string(); + ScopedEnv env("SLASH_RUNTIME_PATH", target); + auto path = FilesystemCache::getRuntimePath(); + EXPECT_TRUE(std::filesystem::is_directory(path)); +} diff --git a/vrt/tests/fixtures/stub_vbin/emu_manifest.json b/vrt/tests/fixtures/stub_vbin/emu_manifest.json new file mode 100644 index 00000000..2fd5b5c4 --- /dev/null +++ b/vrt/tests/fixtures/stub_vbin/emu_manifest.json @@ -0,0 +1,30 @@ +{ + "kernels": [ + { + "instance": "vadd", + "call_args": [ + {"arg": "arg0", "kind": "buffer"}, + {"arg": "arg1", "kind": "buffer"}, + {"arg": "arg2", "kind": "buffer"}, + {"arg": "arg3", "kind": "scalar"} + ] + }, + { + "instance": "passthrough", + "call_args": [ + {"arg": "arg0", "kind": "scalar"} + ] + } + ], + "fetch": { + "scalar": [ + { + "function": "vadd", + "arg": "size", + "source": { + "register_offset": 40 + } + } + ] + } +} diff --git a/vrt/tests/fixtures/stub_vbin/system_map_emu.xml b/vrt/tests/fixtures/stub_vbin/system_map_emu.xml new file mode 100644 index 00000000..95128896 --- /dev/null +++ b/vrt/tests/fixtures/stub_vbin/system_map_emu.xml @@ -0,0 +1,45 @@ + + + Emulation + 100000000 + + + vadd + 0x10000 + 0x1000 + + + + + + + + + + + + + + passthrough + 0x20000 + 0x1000 + + + + + + + + vadd + axis_in + HostToDevice + 0 + + + + vadd + axis_out + DeviceToHost + 1 + + diff --git a/vrt/tests/fixtures/stub_vbin/system_map_sim.xml b/vrt/tests/fixtures/stub_vbin/system_map_sim.xml new file mode 100644 index 00000000..8489c1a3 --- /dev/null +++ b/vrt/tests/fixtures/stub_vbin/system_map_sim.xml @@ -0,0 +1,45 @@ + + + Simulation + 100000000 + + + vadd + 0x10000 + 0x1000 + + + + + + + + + + + + + + passthrough + 0x20000 + 0x1000 + + + + + + + + vadd + axis_in + HostToDevice + 0 + + + + vadd + axis_out + DeviceToHost + 1 + + diff --git a/vrt/tests/fixtures/stub_vbin/vrt_stub_server.py b/vrt/tests/fixtures/stub_vbin/vrt_stub_server.py new file mode 100644 index 00000000..e712e07b --- /dev/null +++ b/vrt/tests/fixtures/stub_vbin/vrt_stub_server.py @@ -0,0 +1,154 @@ +#!/usr/bin/env python3 +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## +import json +import struct +import zmq + +# Kernel base addresses (must match system_map.xml) +VADD_BASE = 0x10000 + +# Functional arg register offsets relative to kernel base (must match system_map.xml) +VADD_IN1_OFFSET = 0x10 +VADD_IN2_OFFSET = 0x18 +VADD_OUT_OFFSET = 0x20 +VADD_SIZE_OFFSET = 0x28 + + +def run_vadd(buffers, in1_key, in2_key, out_key, size): + """Add two int32 buffers and store the result.""" + in1_bytes = buffers.get(in1_key, b"\x00" * (size * 4)) + in2_bytes = buffers.get(in2_key, b"\x00" * (size * 4)) + + n = min(size, len(in1_bytes) // 4, len(in2_bytes) // 4) + in1 = struct.unpack_from(f"<{n}i", in1_bytes) + in2 = struct.unpack_from(f"<{n}i", in2_bytes) + out = [a + b for a, b in zip(in1, in2)] + buffers[out_key] = struct.pack(f"<{n}i", *out) + + +def reconstruct_64bit(registers, base, offset): + """Reconstruct a 64-bit address from two consecutive 32-bit register writes.""" + lo = registers.get(base + offset, 0) + hi = registers.get(base + offset + 4, 0) + return (hi << 32) | lo + + +def main(): + context = zmq.Context() + socket = context.socket(zmq.REP) + socket.bind("tcp://*:5555") + + buffers = {} + streams = {} + registers = {} + + while True: + frames = [socket.recv()] + while socket.getsockopt(zmq.RCVMORE): + frames.append(socket.recv()) + + try: + message = json.loads(frames[0]) + except (json.JSONDecodeError, UnicodeDecodeError): + socket.send(b"OK") + continue + + command = message.get("command", "") + + if command == "exit": + socket.send(b"OK") + break + + elif command == "populate": + key = message.get("name", str(message.get("addr", ""))) + if len(frames) > 1: + buffers[key] = frames[1] + socket.send(b"OK") + + elif command == "stream_in": + key = message.get("name", "") + if len(frames) > 1: + streams[key] = frames[1] + socket.send(b"OK") + + elif command == "stream_out": + key = message.get("name", "") + size = message.get("size", 0) + data = streams.get(key, b"\x00" * size) + socket.send(data) + + elif command == "fetch": + typ = message.get("type", "") + if typ == "buffer": + key = message.get("name", str(message.get("addr", ""))) + if key in buffers: + data = list(buffers[key]) + else: + size = message.get("size", 0) + data = [0] * size + socket.send_string(json.dumps(data)) + else: + address = int(message.get("addr", message.get("name", ""))) + val = registers.get(address, 0) + socket.send_string(json.dumps(val)) + + elif command == "read_register": + socket.send_string("0") + + elif command == "reg": + address = int(message.get("addr", 0)) + val = int(message.get("val", 0)) + + if val & 0x1 and address == VADD_BASE: + # ap_start written to vadd CTRL — reconstruct args and run + in1_addr = reconstruct_64bit(registers, VADD_BASE, VADD_IN1_OFFSET) + in2_addr = reconstruct_64bit(registers, VADD_BASE, VADD_IN2_OFFSET) + out_addr = reconstruct_64bit(registers, VADD_BASE, VADD_OUT_OFFSET) + size_val = registers.get(VADD_BASE + VADD_SIZE_OFFSET, 0) + run_vadd(buffers, str(in1_addr), str(in2_addr), str(out_addr), size_val) + registers[address] = 0x6 # ap_done | ap_idle + else: + registers[address] = val + socket.send(b"OK") + + elif command == "call": + function = message.get("function", "") + arguments = message.get("args", {}) + if function == "vadd": + in1_name = arguments.get("arg0", {}).get("name", "") + in2_name = arguments.get("arg1", {}).get("name", "") + out_name = arguments.get("arg2", {}).get("name", "") + size_val = arguments.get("arg3", {}).get("value", 0) + run_vadd(buffers, in1_name, in2_name, out_name, size_val) + socket.send(b"OK") + + elif command == "wait": + socket.send(b"OK") + + else: + socket.send(b"OK") + + socket.close() + context.term() + + +if __name__ == "__main__": + main() diff --git a/vrt/tests/kernel_test.cpp b/vrt/tests/kernel_test.cpp new file mode 100644 index 00000000..823429fa --- /dev/null +++ b/vrt/tests/kernel_test.cpp @@ -0,0 +1,215 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#include + +static vrt::FunctionalArg makeArg(uint32_t idx, const std::string& name, const std::string& type, + uint32_t offset, uint32_t range = 32, bool readable = false, + bool writable = true, const std::string& port = "") { + vrt::FunctionalArg a; + a.idx = idx; + a.name = name; + a.type = type; + a.offset = offset; + a.range = range; + a.readable = readable; + a.writable = writable; + a.port = port; + return a; +} + +static vrt::Kernel makeTestKernel(const std::vector& args = {}, + const std::string& name = "testKernel", + uint64_t baseAddr = 0x1000, uint64_t range = 0x100) { + std::vector regs; + return vrt::Kernel(name, baseAddr, range, regs, args); +} + +TEST(KernelConstructTest, FiveArgConstructor) { + auto k = makeTestKernel(); + EXPECT_EQ(k.getName(), "testKernel"); + EXPECT_EQ(k.getPhysAddr(), 0x1000u); +} + +TEST(KernelConstructTest, HasFunctionalArgsTrue) { + auto k = makeTestKernel({makeArg(0, "a", "int", 0x10)}); + EXPECT_TRUE(k.hasFunctionalArgs()); +} + +TEST(KernelConstructTest, HasFunctionalArgsFalse) { + auto k = makeTestKernel(); + EXPECT_FALSE(k.hasFunctionalArgs()); +} + +TEST(KernelConstructTest, FunctionalArgsSortedOnConstruction) { + auto k = makeTestKernel( + {makeArg(2, "c", "int", 0x20), makeArg(0, "a", "int", 0x10), makeArg(1, "b", "int", 0x18)}); + auto& args = k.getFunctionalArgs(); + ASSERT_EQ(args.size(), 3u); + EXPECT_EQ(args[0].idx, 0u); + EXPECT_EQ(args[1].idx, 1u); + EXPECT_EQ(args[2].idx, 2u); +} + +TEST(KernelConstructTest, SetAndGetFunctionalArgs) { + auto k = makeTestKernel(); + std::vector newArgs = {makeArg(0, "x", "int", 0x10)}; + k.setFunctionalArgs(newArgs); + EXPECT_TRUE(k.hasFunctionalArgs()); + EXPECT_EQ(k.getFunctionalArgs().size(), 1u); + EXPECT_EQ(k.getFunctionalArgs()[0].name, "x"); +} + +TEST(KernelArgLookupTest, SetArgByIdx) { + auto k = makeTestKernel({makeArg(0, "input", "scalar", 0x10, 32)}); + EXPECT_NO_THROW(k.setArg(0, 42)); +} + +TEST(KernelArgLookupTest, SetArgByName) { + auto k = makeTestKernel({makeArg(0, "input", "scalar", 0x10, 32)}); + EXPECT_NO_THROW(k.setArg("input", 42)); +} + +TEST(KernelArgLookupTest, SetArgByNameWithRSuffix) { + auto k = makeTestKernel({makeArg(0, "input_r", "buffer", 0x10, 64)}); + EXPECT_NO_THROW(k.setArg("input", static_cast(0xDEAD))); +} + +TEST(KernelArgLookupTest, SetArgEmptyNameThrows) { + auto k = makeTestKernel({makeArg(0, "input", "scalar", 0x10)}); + EXPECT_THROW(k.setArg("", 42), std::runtime_error); +} + +TEST(KernelArgLookupTest, SetArgNameNotFoundThrows) { + auto k = makeTestKernel({makeArg(0, "input", "scalar", 0x10)}); + EXPECT_THROW(k.setArg("nonexistent", 42), std::runtime_error); +} + +TEST(KernelArgLookupTest, SetArgIdxNotFoundThrows) { + auto k = makeTestKernel({makeArg(0, "input", "scalar", 0x10)}); + EXPECT_THROW(k.setArg(99, 42), std::runtime_error); +} + +TEST(KernelArgLookupTest, SetArgNegativeIndexThrows) { + auto k = makeTestKernel({makeArg(0, "input", "scalar", 0x10)}); + EXPECT_THROW(k.setArg(-1, 42), std::runtime_error); +} + +TEST(KernelArgLookupTest, SetArgNoMetadataThrows) { + auto k = makeTestKernel(); + EXPECT_THROW(k.setArg(0, 42), std::runtime_error); +} + +TEST(KernelArgValidationTest, EnsureSetArgValuesComplete) { + auto k = makeTestKernel( + {makeArg(0, "a", "scalar", 0x10, 32), makeArg(1, "b", "scalar", 0x14, 32)}); + k.setArg(0, 1); + k.setArg(1, 2); + // With no platform set (UNKNOWN), call() skips all branches — validation is + // only exercised inside platform-specific blocks, so this tests that setArg + // itself succeeds for complete argument sets. + EXPECT_NO_THROW(k.call()); +} + +TEST(KernelArgValidationTest, EnsureSetArgValuesMissingThrows) { + auto k = makeTestKernel( + {makeArg(0, "a", "scalar", 0x10, 32), makeArg(1, "b", "scalar", 0x14, 32)}); + k.setPlatform(vrt::Platform::HARDWARE); + k.setArg(0, 1); + EXPECT_THROW(k.call(), std::runtime_error); +} + +TEST(KernelArgValidationTest, ReadOnlyArgNotRequiredForLaunch) { + auto k = makeTestKernel({makeArg(0, "a", "scalar", 0x10, 32, true, true), + makeArg(1, "status", "scalar", 0x14, 32, true, false)}); + k.setPlatform(vrt::Platform::HARDWARE); + k.setArg(0, 1); + // status is read-only (writable=false), so only "a" needs to be set. + // call() should reach ensureSetArgValuesCompleteForLaunch, which skips + // read-only args, then try writeBatch which throws because no BAR is set. + // The key assertion: it does NOT throw about a missing "status" arg. + EXPECT_THROW(k.call(), std::runtime_error); + try { + k.call(); + } catch (const std::runtime_error& e) { + std::string msg = e.what(); + EXPECT_EQ(msg.find("status"), std::string::npos) << "Should not require read-only arg"; + EXPECT_NE(msg.find("BAR"), std::string::npos) << "Should fail at BAR access, not arg validation"; + } +} + +TEST(KernelMemoryConfigTest, PortMemoryConfigDDR) { + auto k = makeTestKernel({makeArg(0, "in", "buffer", 0x10, 64, false, true, "m_axi_gmem0")}); + k.setConnections({{"m_axi_gmem0", "DDR"}}); + auto cfg = k.portMemoryConfig("m_axi_gmem0"); + EXPECT_EQ(cfg.type, vrt::MemoryRangeType::DDR); + EXPECT_FALSE(cfg.hbmPort.has_value()); +} + +TEST(KernelMemoryConfigTest, PortMemoryConfigHBM) { + auto k = makeTestKernel({makeArg(0, "in", "buffer", 0x10, 64, false, true, "m_axi_gmem0")}); + k.setConnections({{"m_axi_gmem0", "HBM3"}}); + auto cfg = k.portMemoryConfig("m_axi_gmem0"); + EXPECT_EQ(cfg.type, vrt::MemoryRangeType::HBM); + ASSERT_TRUE(cfg.hbmPort.has_value()); + EXPECT_EQ(cfg.hbmPort.value(), 3u); +} + +TEST(KernelMemoryConfigTest, PortMemoryConfigHBMVnoc) { + auto k = makeTestKernel(); + k.setConnections({{"port0", "HBM"}}); + auto cfg = k.portMemoryConfig("port0"); + EXPECT_EQ(cfg.type, vrt::MemoryRangeType::HBM_VNOC); +} + +TEST(KernelMemoryConfigTest, PortMemoryConfigMEM) { + auto k = makeTestKernel(); + k.setConnections({{"port0", "MEM"}}); + auto cfg = k.portMemoryConfig("port0"); + EXPECT_EQ(cfg.type, vrt::MemoryRangeType::HBM_VNOC); +} + +TEST(KernelMemoryConfigTest, PortMemoryConfigUnknownTargetThrows) { + auto k = makeTestKernel(); + k.setConnections({{"port0", "INVALID"}}); + EXPECT_THROW(k.portMemoryConfig("port0"), std::runtime_error); +} + +TEST(KernelMemoryConfigTest, PortMemoryConfigNoConnectionThrows) { + auto k = makeTestKernel(); + k.setConnections({{"port0", "DDR"}}); + EXPECT_THROW(k.portMemoryConfig("nonexistent"), std::runtime_error); +} + +TEST(KernelMemoryConfigTest, ArgMemoryConfigByName) { + auto k = makeTestKernel({makeArg(0, "input", "buffer", 0x10, 64, false, true, "m_axi_gmem0")}); + k.setConnections({{"m_axi_gmem0", "DDR"}}); + auto cfg = k.argMemoryConfig("input"); + EXPECT_EQ(cfg.type, vrt::MemoryRangeType::DDR); +} + +TEST(KernelMemoryConfigTest, ArgMemoryConfigNoPortThrows) { + auto k = makeTestKernel({makeArg(0, "scalar_arg", "scalar", 0x10, 32, false, true, "")}); + k.setConnections({}); + EXPECT_THROW(k.argMemoryConfig("scalar_arg"), std::runtime_error); +} diff --git a/vrt/tests/logger_test.cpp b/vrt/tests/logger_test.cpp new file mode 100644 index 00000000..3280c22e --- /dev/null +++ b/vrt/tests/logger_test.cpp @@ -0,0 +1,146 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +#include +#include +#include +#include +#include + +#include "test_helpers.hpp" + +class LoggerTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + std::string logFile; + + void SetUp() override { + tmpDir = makeTempDir("logger-test"); + logFile = (tmpDir / "test.log").string(); + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::DEBUG); + vrt::utils::Logger::setOutput(logFile); + } + + void TearDown() override { + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::INFO); + std::filesystem::remove_all(tmpDir); + } + + std::string readLog() { + std::ifstream ifs(logFile); + return std::string((std::istreambuf_iterator(ifs)), + std::istreambuf_iterator()); + } +}; + +TEST_F(LoggerTest, GeneralPlaceholder) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "hello {}", "world"); + EXPECT_NE(readLog().find("hello world"), std::string::npos); +} + +TEST_F(LoggerTest, GeneralPlaceholderInt) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "value={}", 42); + EXPECT_NE(readLog().find("value=42"), std::string::npos); +} + +TEST_F(LoggerTest, HexPlaceholder) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "addr={x}", 255); + std::string log = readLog(); + EXPECT_NE(log.find("0xff"), std::string::npos); +} + +TEST_F(LoggerTest, BinaryPlaceholder) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "bits={b}", + static_cast(5)); + std::string log = readLog(); + EXPECT_NE(log.find("0b00000101"), std::string::npos); +} + +TEST_F(LoggerTest, OctalPlaceholder) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "oct={o}", 8); + std::string log = readLog(); + EXPECT_NE(log.find("0o"), std::string::npos); +} + +TEST_F(LoggerTest, MultiplePlaceholders) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "{} + {} = {}", 1, 2, 3); + EXPECT_NE(readLog().find("1 + 2 = 3"), std::string::npos); +} + +TEST_F(LoggerTest, NoPlaceholders) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "literal message"); + EXPECT_NE(readLog().find("literal message"), std::string::npos); +} + +TEST_F(LoggerTest, TooFewArgsThrows) { + EXPECT_THROW( + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "{} {}", "only_one"), + std::runtime_error); +} + +TEST_F(LoggerTest, TooManyArgsThrows) { + EXPECT_THROW(vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "{}", 1, 2), + std::runtime_error); +} + +TEST_F(LoggerTest, SetLogLevelFilters) { + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::WARN); + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "should not appear"); + EXPECT_TRUE(readLog().empty()); +} + +TEST_F(LoggerTest, NoneBlocksAll) { + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::NONE); + vrt::utils::Logger::log(vrt::utils::LogLevel::ERROR, "test", "blocked"); + vrt::utils::Logger::log(vrt::utils::LogLevel::WARN, "test", "blocked"); + EXPECT_TRUE(readLog().empty()); +} + +TEST_F(LoggerTest, WarnLevelPassesWarn) { + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::WARN); + vrt::utils::Logger::log(vrt::utils::LogLevel::WARN, "test", "warn msg"); + EXPECT_NE(readLog().find("warn msg"), std::string::npos); +} + +TEST_F(LoggerTest, ErrorLevelBlockedByWarnThreshold) { + vrt::utils::Logger::setLogLevel(vrt::utils::LogLevel::WARN); + vrt::utils::Logger::log(vrt::utils::LogLevel::ERROR, "test", "error msg"); + EXPECT_EQ(readLog().find("error msg"), std::string::npos); +} + +TEST_F(LoggerTest, SetOutputToFile) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "file output"); + std::string log = readLog(); + EXPECT_FALSE(log.empty()); + EXPECT_NE(log.find("file output"), std::string::npos); +} + +TEST_F(LoggerTest, SetOutputInvalidPathFallsBack) { + EXPECT_NO_THROW(vrt::utils::Logger::setOutput("/nonexistent/path/log.txt")); +} + +TEST_F(LoggerTest, TimestampFormat) { + vrt::utils::Logger::log(vrt::utils::LogLevel::INFO, "test", "ts check"); + std::string log = readLog(); + std::regex tsPattern(R"(\d{4}-\d{2}-\d{2} \d{2}:\d{2}:\d{2}\.\d{3})"); + EXPECT_TRUE(std::regex_search(log, tsPattern)); +} diff --git a/submodules/v80-vitis-flow/src/xml_parser/area_estimates.cpp b/vrt/tests/qdma_connection_test.cpp similarity index 52% rename from submodules/v80-vitis-flow/src/xml_parser/area_estimates.cpp rename to vrt/tests/qdma_connection_test.cpp index 91e9395a..dfac64b6 100644 --- a/submodules/v80-vitis-flow/src/xml_parser/area_estimates.cpp +++ b/vrt/tests/qdma_connection_test.cpp @@ -1,6 +1,6 @@ /** * The MIT License (MIT) - * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -17,26 +17,30 @@ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ +#include +#include -#include "area_estimates.hpp" - -void AreaEstimates::addResource(Resource resource) { this->usedResources.emplace_back(resource); } +TEST(QdmaConnectionTest, HostToDeviceDirection) { + vrt::QdmaConnection conn("myKernel", 0, "axis_port", "HostToDevice"); + EXPECT_EQ(conn.getDirection(), vrt::StreamDirection::HOST_TO_DEVICE); +} -void AreaEstimates::addAvailableResource(Resource resource) { - this->availableResources.emplace_back(resource); +TEST(QdmaConnectionTest, DeviceToHostDirection) { + vrt::QdmaConnection conn("myKernel", 1, "axis_port", "DeviceToHost"); + EXPECT_EQ(conn.getDirection(), vrt::StreamDirection::DEVICE_TO_HOST); } -std::vector AreaEstimates::getUsedResources() { return this->usedResources; } +TEST(QdmaConnectionTest, GetKernel) { + vrt::QdmaConnection conn("testKernel", 3, "iface0", "HostToDevice"); + EXPECT_EQ(conn.getKernel(), "testKernel"); +} -std::vector AreaEstimates::getAvailableResources() { return this->availableResources; } +TEST(QdmaConnectionTest, GetQid) { + vrt::QdmaConnection conn("k", 42, "iface0", "HostToDevice"); + EXPECT_EQ(conn.getQid(), 42u); +} -void AreaEstimates::print() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Resource utilization"); - for (auto el : usedResources) { - el.print(); - } - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Available resources"); - for (auto el : availableResources) { - el.print(); - } -} \ No newline at end of file +TEST(QdmaConnectionTest, GetInterface) { + vrt::QdmaConnection conn("k", 0, "my_interface", "DeviceToHost"); + EXPECT_EQ(conn.getInterface(), "my_interface"); +} diff --git a/vrt/tests/register_test.cpp b/vrt/tests/register_test.cpp new file mode 100644 index 00000000..60915b69 --- /dev/null +++ b/vrt/tests/register_test.cpp @@ -0,0 +1,67 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +TEST(RegisterTest, ParameterizedConstructor) { + vrt::Register reg("CTRL", 0x10, 32, "RW", "Control register"); + EXPECT_EQ(reg.getRegisterName(), "CTRL"); + EXPECT_EQ(reg.getOffset(), 0x10u); + EXPECT_EQ(reg.getWidth(), 32u); + EXPECT_EQ(reg.getRW(), "RW"); + EXPECT_EQ(reg.getDescription(), "Control register"); +} + +TEST(RegisterTest, DefaultConstructor) { + vrt::Register reg; + EXPECT_EQ(reg.getRegisterName(), ""); + EXPECT_EQ(reg.getRW(), ""); + EXPECT_EQ(reg.getDescription(), ""); +} + +TEST(RegisterTest, SetRegisterName) { + vrt::Register reg; + reg.setRegisterName("STATUS"); + EXPECT_EQ(reg.getRegisterName(), "STATUS"); +} + +TEST(RegisterTest, SetOffset) { + vrt::Register reg; + reg.setOffset(0x20); + EXPECT_EQ(reg.getOffset(), 0x20u); +} + +TEST(RegisterTest, SetWidth) { + vrt::Register reg; + reg.setWidth(64); + EXPECT_EQ(reg.getWidth(), 64u); +} + +TEST(RegisterTest, SetRW) { + vrt::Register reg; + reg.setRW("RO"); + EXPECT_EQ(reg.getRW(), "RO"); +} + +TEST(RegisterTest, SetDescription) { + vrt::Register reg; + reg.setDescription("Status register for monitoring"); + EXPECT_EQ(reg.getDescription(), "Status register for monitoring"); +} diff --git a/vrt/tests/test_helpers.hpp b/vrt/tests/test_helpers.hpp new file mode 100644 index 00000000..f8568182 --- /dev/null +++ b/vrt/tests/test_helpers.hpp @@ -0,0 +1,82 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef VRT_TEST_HELPERS_HPP +#define VRT_TEST_HELPERS_HPP + +#include +#include +#include +#include +#include + +class ScopedEnv { + public: + explicit ScopedEnv(const char* name, std::optional value = std::nullopt) + : name_(name) { + const char* prev = std::getenv(name); + if (prev) { + oldValue_ = prev; + } + if (value) { + setenv(name, value->c_str(), 1); + } else { + unsetenv(name); + } + } + + ~ScopedEnv() { + if (oldValue_) { + setenv(name_.c_str(), oldValue_->c_str(), 1); + } else { + unsetenv(name_.c_str()); + } + } + + ScopedEnv(const ScopedEnv&) = delete; + ScopedEnv& operator=(const ScopedEnv&) = delete; + + private: + std::string name_; + std::optional oldValue_; +}; + +inline std::filesystem::path makeTempDir(const std::string& prefix) { + std::string tmpl = (std::filesystem::temp_directory_path() / (prefix + "-XXXXXX")).string(); + char* result = mkdtemp(tmpl.data()); + if (!result) { + throw std::runtime_error("Failed to create temp directory"); + } + return result; +} + +inline std::string writeTempFile(const std::filesystem::path& dir, const std::string& name, + const std::string& content) { + auto path = dir / name; + std::filesystem::create_directories(path.parent_path()); + std::ofstream ofs(path); + if (!ofs) { + throw std::runtime_error("Failed to create temp file: " + path.string()); + } + ofs << content; + ofs.close(); + return path.string(); +} + +#endif // VRT_TEST_HELPERS_HPP diff --git a/vrt/tests/utilization_data_test.cpp b/vrt/tests/utilization_data_test.cpp new file mode 100644 index 00000000..84aad4fc --- /dev/null +++ b/vrt/tests/utilization_data_test.cpp @@ -0,0 +1,76 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +TEST(UtilizationDataTest, ResourceMetricsDefaults) { + vrt::ResourceMetrics m{}; + EXPECT_EQ(m.totalPplocs, 0u); + EXPECT_EQ(m.totalLuts, 0u); + EXPECT_EQ(m.lutram, 0u); + EXPECT_EQ(m.srl, 0u); + EXPECT_EQ(m.ff, 0u); + EXPECT_EQ(m.ramb36, 0u); + EXPECT_EQ(m.ramb18, 0u); + EXPECT_EQ(m.ramb, 0u); + EXPECT_EQ(m.uram, 0u); + EXPECT_EQ(m.dsp, 0u); +} + +TEST(UtilizationDataTest, OptionalFieldsDefaultToNullopt) { + vrt::ResourceMetrics m{}; + EXPECT_FALSE(m.totalLutsPct.has_value()); + EXPECT_FALSE(m.lutramPct.has_value()); + EXPECT_FALSE(m.srlPct.has_value()); + EXPECT_FALSE(m.ffPct.has_value()); + EXPECT_FALSE(m.ramb36Pct.has_value()); + EXPECT_FALSE(m.ramb18Pct.has_value()); + EXPECT_FALSE(m.uramPct.has_value()); + EXPECT_FALSE(m.dspPct.has_value()); +} + +TEST(UtilizationDataTest, ResourceMetricsAssignment) { + vrt::ResourceMetrics m{}; + m.totalLuts = 1000; + m.totalLutsPct = 5.2f; + EXPECT_EQ(m.totalLuts, 1000u); + ASSERT_TRUE(m.totalLutsPct.has_value()); + EXPECT_FLOAT_EQ(m.totalLutsPct.value(), 5.2f); +} + +TEST(UtilizationDataTest, UtilizationCellConstruction) { + vrt::UtilizationCell cell; + cell.instance = "k0"; + cell.module = "myKernel"; + cell.pr = "pblock_0"; + cell.metrics.totalLuts = 400; + EXPECT_EQ(cell.instance, "k0"); + EXPECT_EQ(cell.module, "myKernel"); + EXPECT_EQ(cell.metrics.totalLuts, 400u); +} + +TEST(UtilizationDataTest, UtilizationReportSlashPresent) { + vrt::UtilizationReport report; + report.slash.name = "slash"; + report.slash.totals.totalLuts = 500; + EXPECT_EQ(report.slash.name, "slash"); + EXPECT_EQ(report.slash.totals.totalLuts, 500u); + EXPECT_FALSE(report.serviceLayer.has_value()); +} diff --git a/vrt/tests/utilization_parser_test.cpp b/vrt/tests/utilization_parser_test.cpp new file mode 100644 index 00000000..dc2bdfa2 --- /dev/null +++ b/vrt/tests/utilization_parser_test.cpp @@ -0,0 +1,162 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +#include + +#include "test_helpers.hpp" + +class UtilizationParserTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + + void SetUp() override { tmpDir = makeTempDir("util-parser-test"); } + void TearDown() override { std::filesystem::remove_all(tmpDir); } + + std::string writeXml(const std::string& content) { + return writeTempFile(tmpDir, "utilization.xml", content); + } +}; + +TEST_F(UtilizationParserTest, ParseSlashBlock) { + auto path = writeXml(R"( + + + + +)"); + vrt::UtilizationParser parser(path); + parser.parse(); + auto& report = parser.getReport(); + EXPECT_EQ(report.slash.name, "slash"); + EXPECT_EQ(report.slash.totals.totalLuts, 1000u); + EXPECT_EQ(report.slash.totals.ff, 500u); + EXPECT_EQ(report.slash.totals.dsp, 10u); + EXPECT_EQ(report.slash.totals.ramb36, 5u); + EXPECT_EQ(report.slash.totals.ramb18, 3u); + EXPECT_EQ(report.slash.totals.uram, 2u); +} + +TEST_F(UtilizationParserTest, ParseSlashBlockWithKernels) { + auto path = writeXml(R"( + + + + + + + + + + +)"); + vrt::UtilizationParser parser(path); + parser.parse(); + auto& report = parser.getReport(); + ASSERT_TRUE(report.slash.subhierarchy.has_value()); + ASSERT_EQ(report.slash.subhierarchy->cells.size(), 1u); + EXPECT_EQ(report.slash.subhierarchy->cells[0].instance, "k0"); + EXPECT_EQ(report.slash.subhierarchy->cells[0].module, "myKernel"); + EXPECT_EQ(report.slash.subhierarchy->cells[0].metrics.totalLuts, 400u); + EXPECT_EQ(report.slash.subhierarchy->subhierarchySum.totalLuts, 400u); +} + +TEST_F(UtilizationParserTest, ParseSlashBlockWithSlashLogic) { + auto path = writeXml(R"( + + + + + + + + + + +)"); + vrt::UtilizationParser parser(path); + parser.parse(); + auto& sub = parser.getReport().slash.subhierarchy; + ASSERT_TRUE(sub.has_value()); + ASSERT_EQ(sub->slashLogic.size(), 1u); + EXPECT_EQ(sub->slashLogic[0].instance, "sl0"); + EXPECT_EQ(sub->slashLogicSum.totalLuts, 100u); +} + +TEST_F(UtilizationParserTest, ParseServiceLayer) { + auto path = writeXml(R"( + + + + + + + +)"); + vrt::UtilizationParser parser(path); + parser.parse(); + auto& report = parser.getReport(); + ASSERT_TRUE(report.serviceLayer.has_value()); + EXPECT_EQ(report.serviceLayer->name, "service_layer"); + EXPECT_EQ(report.serviceLayer->totals.totalLuts, 200u); + EXPECT_EQ(report.serviceLayer->totals.ff, 150u); +} + +TEST_F(UtilizationParserTest, ParseResourceMetricsPercentages) { + auto path = writeXml(R"( + + + + +)"); + vrt::UtilizationParser parser(path); + parser.parse(); + auto& m = parser.getReport().slash.totals; + ASSERT_TRUE(m.totalLutsPct.has_value()); + EXPECT_FLOAT_EQ(m.totalLutsPct.value(), 5.2f); + ASSERT_TRUE(m.ffPct.has_value()); + EXPECT_FLOAT_EQ(m.ffPct.value(), 3.1f); + EXPECT_FALSE(m.dspPct.has_value()); +} + +TEST_F(UtilizationParserTest, MissingSlashBlockThrows) { + auto path = writeXml(R"( +)"); + vrt::UtilizationParser parser(path); + EXPECT_THROW(parser.parse(), std::runtime_error); +} + +TEST_F(UtilizationParserTest, InvalidXmlThrows) { + auto path = writeTempFile(tmpDir, "bad.xml", "not valid xml <<<<"); + EXPECT_THROW(vrt::UtilizationParser parser(path), std::runtime_error); +} + +TEST_F(UtilizationParserTest, SlashBlockWithoutServiceLayer) { + auto path = writeXml(R"( + + + + +)"); + vrt::UtilizationParser parser(path); + parser.parse(); + EXPECT_FALSE(parser.getReport().serviceLayer.has_value()); +} diff --git a/vrt/tests/vrtbin_integration_test.cpp b/vrt/tests/vrtbin_integration_test.cpp new file mode 100644 index 00000000..d3c86879 --- /dev/null +++ b/vrt/tests/vrtbin_integration_test.cpp @@ -0,0 +1,112 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#include + +#include "test_helpers.hpp" + +class VrtbinEmuTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + ScopedEnv* envCache = nullptr; + + void SetUp() override { + tmpDir = makeTempDir("vrtbin-emu-test"); + envCache = new ScopedEnv("SLASH_CACHE_PATH", tmpDir.string()); + } + + void TearDown() override { + delete envCache; + std::filesystem::remove_all(tmpDir); + } +}; + +TEST_F(VrtbinEmuTest, ExtractAndFindSystemMap) { + vrt::Vrtbin vrtbin(STUB_EMU_VBIN_PATH, "0000:00:00"); + EXPECT_FALSE(vrtbin.getSystemMapPath().empty()); + EXPECT_TRUE(std::filesystem::exists(vrtbin.getSystemMapPath())); +} + +TEST_F(VrtbinEmuTest, DetectsPlatformEmulation) { + vrt::Vrtbin vrtbin(STUB_EMU_VBIN_PATH, "0000:00:00"); + EXPECT_EQ(vrtbin.getPlatform(), vrt::Platform::EMULATION); +} + +TEST_F(VrtbinEmuTest, FindsEmulationExec) { + vrt::Vrtbin vrtbin(STUB_EMU_VBIN_PATH, "0000:00:00"); + EXPECT_FALSE(vrtbin.getEmulationExec().empty()); + EXPECT_TRUE(std::filesystem::exists(vrtbin.getEmulationExec())); +} + +TEST_F(VrtbinEmuTest, FindsEmulationManifest) { + vrt::Vrtbin vrtbin(STUB_EMU_VBIN_PATH, "0000:00:00"); + EXPECT_FALSE(vrtbin.getEmulationManifest().empty()); + EXPECT_TRUE(std::filesystem::exists(vrtbin.getEmulationManifest())); +} + +TEST_F(VrtbinEmuTest, NoPdiFilesForEmulation) { + vrt::Vrtbin vrtbin(STUB_EMU_VBIN_PATH, "0000:00:00"); + EXPECT_TRUE(vrtbin.getPdiPaths().empty()); +} + +class VrtbinSimTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + ScopedEnv* envCache = nullptr; + + void SetUp() override { + tmpDir = makeTempDir("vrtbin-sim-test"); + envCache = new ScopedEnv("SLASH_CACHE_PATH", tmpDir.string()); + } + + void TearDown() override { + delete envCache; + std::filesystem::remove_all(tmpDir); + } +}; + +TEST_F(VrtbinSimTest, ExtractAndFindSystemMap) { + vrt::Vrtbin vrtbin(STUB_SIM_VBIN_PATH, "0000:00:00"); + EXPECT_FALSE(vrtbin.getSystemMapPath().empty()); + EXPECT_TRUE(std::filesystem::exists(vrtbin.getSystemMapPath())); +} + +TEST_F(VrtbinSimTest, DetectsPlatformSimulation) { + vrt::Vrtbin vrtbin(STUB_SIM_VBIN_PATH, "0000:00:00"); + EXPECT_EQ(vrtbin.getPlatform(), vrt::Platform::SIMULATION); +} + +TEST_F(VrtbinSimTest, FindsSimulationExec) { + vrt::Vrtbin vrtbin(STUB_SIM_VBIN_PATH, "0000:00:00"); + EXPECT_FALSE(vrtbin.getSimulationExec().empty()); + EXPECT_TRUE(std::filesystem::exists(vrtbin.getSimulationExec())); +} + +TEST_F(VrtbinSimTest, NoPdiFilesForSimulation) { + vrt::Vrtbin vrtbin(STUB_SIM_VBIN_PATH, "0000:00:00"); + EXPECT_TRUE(vrtbin.getPdiPaths().empty()); +} + +TEST(VrtbinErrorTest, NonexistentVbinThrows) { + EXPECT_THROW(vrt::Vrtbin("/nonexistent/path.vbin", "0000:00:00"), std::runtime_error); +} diff --git a/vrt/tests/vrtbin_test.cpp b/vrt/tests/vrtbin_test.cpp new file mode 100644 index 00000000..1734e71d --- /dev/null +++ b/vrt/tests/vrtbin_test.cpp @@ -0,0 +1,75 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +#include +#include + +#include "test_helpers.hpp" + +class VrtbinHelperTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + ScopedEnv* envSlashCache = nullptr; + + void SetUp() override { + tmpDir = makeTempDir("vrtbin-test"); + envSlashCache = new ScopedEnv("SLASH_CACHE_PATH", tmpDir.string()); + } + + void TearDown() override { + delete envSlashCache; + std::filesystem::remove_all(tmpDir); + } +}; + +TEST_F(VrtbinHelperTest, GetSystemMapPathFromBdf) { + auto path = vrt::Vrtbin::getSystemMapPathFromBdf("0000:01:00.0"); + EXPECT_NE(path.find("metadata_0000_01_00_0"), std::string::npos); + EXPECT_NE(path.find("system_map.xml"), std::string::npos); +} + +TEST_F(VrtbinHelperTest, GetUtilizationReportPathFromBdf) { + auto path = vrt::Vrtbin::getUtilizationReportPathFromBdf("0000:01:00.0"); + EXPECT_NE(path.find("metadata_0000_01_00_0"), std::string::npos); + EXPECT_NE(path.find("report_utilization.xml"), std::string::npos); +} + +TEST_F(VrtbinHelperTest, SanitizeAlnum) { + auto path = vrt::Vrtbin::getSystemMapPathFromBdf("abc123"); + EXPECT_NE(path.find("metadata_abc123"), std::string::npos); +} + +TEST_F(VrtbinHelperTest, SanitizeSpecialChars) { + auto path = vrt::Vrtbin::getSystemMapPathFromBdf("0000:01:00.0"); + EXPECT_NE(path.find("metadata_0000_01_00_0"), std::string::npos); + EXPECT_EQ(path.find(":"), std::string::npos); +} + +TEST_F(VrtbinHelperTest, SanitizeEmpty) { + auto path = vrt::Vrtbin::getSystemMapPathFromBdf(""); + EXPECT_NE(path.find("metadata_default"), std::string::npos); +} + +TEST_F(VrtbinHelperTest, PathStartsWithCacheDir) { + auto path = vrt::Vrtbin::getSystemMapPathFromBdf("test"); + EXPECT_EQ(path.rfind(tmpDir.string(), 0), 0u); +} diff --git a/vrt/tests/xml_parser_test.cpp b/vrt/tests/xml_parser_test.cpp new file mode 100644 index 00000000..94b002b4 --- /dev/null +++ b/vrt/tests/xml_parser_test.cpp @@ -0,0 +1,246 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#include + +#include "test_helpers.hpp" + +class XMLParserTest : public ::testing::Test { + protected: + std::filesystem::path tmpDir; + + void SetUp() override { tmpDir = makeTempDir("xml-parser-test"); } + void TearDown() override { std::filesystem::remove_all(tmpDir); } + + std::string writeXml(const std::string& content) { + return writeTempFile(tmpDir, "system_map.xml", content); + } +}; + +TEST_F(XMLParserTest, ParseSingleKernel) { + auto path = writeXml(R"( + + + vadd + 0x1000 + 0x100 + + 300000000 + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto kernels = parser.getKernels(); + ASSERT_EQ(kernels.count("vadd"), 1u); + EXPECT_EQ(kernels["vadd"].getName(), "vadd"); + EXPECT_EQ(kernels["vadd"].getPhysAddr(), 0x1000u); +} + +TEST_F(XMLParserTest, ParseKernelRegisters) { + auto path = writeXml(R"( + + + k + 0x0 + 0x100 + + + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto kernels = parser.getKernels(); + ASSERT_EQ(kernels.count("k"), 1u); +} + +TEST_F(XMLParserTest, ParseKernelFunctionalArgs) { + auto path = writeXml(R"( + + + k + 0x0 + 0x100 + + + + + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto kernels = parser.getKernels(); + ASSERT_EQ(kernels.count("k"), 1u); + auto& args = kernels["k"].getFunctionalArgs(); + ASSERT_EQ(args.size(), 1u); + EXPECT_EQ(args[0].idx, 0u); + EXPECT_EQ(args[0].name, "input"); + EXPECT_EQ(args[0].type, "buffer"); + EXPECT_EQ(args[0].offset, 0x10u); + EXPECT_EQ(args[0].range, 64u); + EXPECT_FALSE(args[0].readable); + EXPECT_TRUE(args[0].writable); + EXPECT_EQ(args[0].port, "m_axi_gmem0"); +} + +TEST_F(XMLParserTest, FunctionalArgsSortedByIdx) { + auto path = writeXml(R"( + + + k + 0x0 + 0x100 + + + + + + + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto kernels = parser.getKernels(); + auto& args = kernels["k"].getFunctionalArgs(); + ASSERT_EQ(args.size(), 3u); + EXPECT_EQ(args[0].idx, 0u); + EXPECT_EQ(args[1].idx, 1u); + EXPECT_EQ(args[2].idx, 2u); +} + +TEST_F(XMLParserTest, ParseClockFrequency) { + auto path = writeXml(R"( + + 250000000 + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + EXPECT_EQ(parser.getClockFrequency(), 250000000u); +} + +TEST_F(XMLParserTest, ParsePlatformHardware) { + auto path = writeXml(R"( +Hardware)"); + vrt::XMLParser parser(path); + parser.parseXML(); + EXPECT_EQ(parser.getPlatform(), vrt::Platform::HARDWARE); +} + +TEST_F(XMLParserTest, ParsePlatformEmulation) { + auto path = writeXml(R"( +Emulation)"); + vrt::XMLParser parser(path); + parser.parseXML(); + EXPECT_EQ(parser.getPlatform(), vrt::Platform::EMULATION); +} + +TEST_F(XMLParserTest, ParsePlatformSimulation) { + auto path = writeXml(R"( +Simulation)"); + vrt::XMLParser parser(path); + parser.parseXML(); + EXPECT_EQ(parser.getPlatform(), vrt::Platform::SIMULATION); +} + +TEST_F(XMLParserTest, ParsePlatformUnknownThrows) { + auto path = writeXml(R"( +SomethingWeird)"); + vrt::XMLParser parser(path); + EXPECT_THROW(parser.parseXML(), std::runtime_error); +} + +TEST_F(XMLParserTest, ParseQdmaConnections) { + auto path = writeXml(R"( + + Hardware + + myKernel + axis_port + HostToDevice + 3 + +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto conns = parser.getQdmaConnections(); + ASSERT_EQ(conns.size(), 1u); + EXPECT_EQ(conns[0].getKernel(), "myKernel"); + EXPECT_EQ(conns[0].getInterface(), "axis_port"); + EXPECT_EQ(conns[0].getDirection(), vrt::StreamDirection::HOST_TO_DEVICE); + EXPECT_EQ(conns[0].getQid(), 3u); +} + +TEST_F(XMLParserTest, ParseMultipleKernels) { + auto path = writeXml(R"( + + + k1 + 0x1000 + 0x100 + + + k2 + 0x2000 + 0x200 + + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto kernels = parser.getKernels(); + EXPECT_EQ(kernels.size(), 2u); + EXPECT_EQ(kernels.count("k1"), 1u); + EXPECT_EQ(kernels.count("k2"), 1u); +} + +TEST_F(XMLParserTest, InvalidXmlFileThrows) { + auto path = writeTempFile(tmpDir, "bad.xml", "not valid xml <<<<"); + EXPECT_THROW(vrt::XMLParser parser(path), std::runtime_error); +} + +TEST_F(XMLParserTest, EmptySystemMap) { + auto path = writeXml(R"( +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + EXPECT_TRUE(parser.getKernels().empty()); + EXPECT_TRUE(parser.getQdmaConnections().empty()); +} + +TEST_F(XMLParserTest, ParseKernelConnections) { + auto path = writeXml(R"( + + + k + 0x0 + 0x100 + + + + Hardware +)"); + vrt::XMLParser parser(path); + parser.parseXML(); + auto kernels = parser.getKernels(); + ASSERT_EQ(kernels.count("k"), 1u); +} diff --git a/vrt/vrtd/CMakeLists.txt b/vrt/vrtd/CMakeLists.txt new file mode 100644 index 00000000..554552e3 --- /dev/null +++ b/vrt/vrtd/CMakeLists.txt @@ -0,0 +1,161 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +cmake_minimum_required(VERSION 3.16) + +# Read version from packaging/version +file(READ "${CMAKE_CURRENT_SOURCE_DIR}/../../packaging/version" VRTD_VERSION) +string(STRIP "${VRTD_VERSION}" VRTD_VERSION) + +# Parse into components +string(REPLACE "." ";" VERSION_LIST "${VRTD_VERSION}") +list(GET VERSION_LIST 0 VRTD_VERSION_MAJOR) +list(GET VERSION_LIST 1 VRTD_VERSION_MINOR) +list(GET VERSION_LIST 2 VRTD_VERSION_PATCH) + +message(STATUS "VRTD version: ${VRTD_VERSION} (${VRTD_VERSION_MAJOR}.${VRTD_VERSION_MINOR}.${VRTD_VERSION_PATCH})") + +project(vrtd + VERSION ${VRTD_VERSION} + LANGUAGES C CXX +) + +# Optionally build examples +option(VRTD_BUILD_EXAMPLES "Build example executables" OFF) +option(VRTD_BUILD_TESTS "Build unit tests" OFF) +option(VRTD_INCLUDE_LIBSLASH "Include libslash subdirectory instead of building from system" OFF) +option(BUILD_SHARED_LIBS "Build shared libraries" ON) + +option(ENABLE_SANITIZERS "Build with AddressSanitizer and UBSan" OFF) +if(ENABLE_SANITIZERS) + add_compile_options(-fsanitize=address,undefined -fno-omit-frame-pointer) + add_link_options(-fsanitize=address,undefined) +endif() + +option(ENABLE_COVERAGE "Build with gcov coverage instrumentation" OFF) +if(ENABLE_COVERAGE) + if(ENABLE_SANITIZERS) + message(FATAL_ERROR "ENABLE_COVERAGE and ENABLE_SANITIZERS cannot be used together") + endif() + add_compile_options(--coverage -fno-inline) + add_link_options(--coverage) +endif() + + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) + +if(VRTD_INCLUDE_LIBSLASH) + add_subdirectory(../../driver/libslash libslash) +else() + find_package(slash REQUIRED) +endif() + +include(${CMAKE_CURRENT_SOURCE_DIR}/cmake/ami.cmake) + +find_package(Threads REQUIRED) +find_package(PkgConfig REQUIRED) + +# Find libsystemd +pkg_check_modules(SYSTEMD REQUIRED IMPORTED_TARGET libsystemd) + +# Find libinih +pkg_check_modules(INIH REQUIRED IMPORTED_TARGET inih) + +add_subdirectory(src) + +add_subdirectory(libvrtd) +add_subdirectory(libvrtdpp) + +if(VRTD_BUILD_TESTS) + add_subdirectory(tests) +endif() + +#if(VRTD_BUILD_EXAMPLES) +# add_subdirectory(examples) +#endif() + +# -------- Installation: headers and library -------- +# Public headers are under include/ (layout: include/vrtd/*.h) +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/libvrtd/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + DIRECTORY "${PROJECT_SOURCE_DIR}/libvrtdpp/include/" + DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + TARGETS libvrtd libvrtdpp + EXPORT vrtdTargets + ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}" + LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}" + INCLUDES DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" +) + +install( + TARGETS vrtd + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" +) + +# -------- CMake package configuration -------- +# Generate the version file +write_basic_package_version_file( + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfigVersion.cmake" + VERSION ${PROJECT_VERSION} + COMPATIBILITY SameMinorVersion +) + +# Configure the main package config from template +configure_package_config_file( + "${PROJECT_SOURCE_DIR}/cmake/vrtdConfig.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfig.cmake" + INSTALL_DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrtd" +) + +# Export targets for *install* tree +install( + EXPORT vrtdTargets + NAMESPACE vrtd:: + FILE vrtdTargets.cmake + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrtd" +) + +# Install the config + version files +install( + FILES + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfig.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/vrtdConfigVersion.cmake" + DESTINATION "${CMAKE_INSTALL_LIBDIR}/cmake/vrtd" +) + +# Export targets for *build* tree so a project can use this directory directly +export( + EXPORT vrtdTargets + NAMESPACE vrtd:: + FILE "${CMAKE_CURRENT_BINARY_DIR}/vrtdTargets.cmake" +) diff --git a/vrt/vrtd/README.md b/vrt/vrtd/README.md new file mode 100644 index 00000000..0c17ed63 --- /dev/null +++ b/vrt/vrtd/README.md @@ -0,0 +1,122 @@ +# vrtd — V80 Runtime Daemon + +vrtd is a systemd-managed daemon written in C (gnu11) that multiplexes +access to AMD Alveo V80 FPGA devices managed by the SLASH kernel +module. It communicates with client applications over an AF_UNIX +socket using a binary request/response protocol, passing device file +descriptors out-of-band via `SCM_RIGHTS`. + +## Architecture + +vrtd sits between the client libraries and the low-level driver stack: + +``` +libvrtdpp (C++ RAII wrapper) +libvrtd (C wire-protocol client library) +──────── AF_UNIX / SOCK_SEQPACKET ──────── +vrtd (this daemon) +libslash (driver wrapper) +Linux kernel module (slash) +AMD Alveo V80 hardware +``` + +Key responsibilities: + +- Sysfs-based automatic device discovery at startup +- Per-client DMA buffer management (HBM and DDR) with automatic + cleanup on disconnect +- FPGA bitstream programming via the design writer subsystem +- Clock frequency control via AXI clock wizard +- PCIe hotplug (secondary bus reset) support +- Role-based access control with per-device granularity +- Systemd integration: socket activation, watchdog, sd-event loop, + journal logging + +## Directory layout + +| Path | Contents | +|------|----------| +| `src/` | Daemon source code (C11) | +| `include/vrtd/` | Public wire-protocol headers shared with libvrtd | +| `libvrtd/` | C client library for the vrtd wire protocol | +| `libvrtdpp/` | C++ RAII wrapper around libvrtd | +| `conf/` | Default configuration file (`vrtd.conf`) | +| `systemd/` | systemd service and socket unit files | +| `sysusers/` | systemd-sysusers configuration (vrtd user/group) | +| `udev/` | udev rules for device permissions | +| `cmake/` | CMake config-file templates | + +## Building + +**Prerequisites:** libslash must be installed first (or built in-tree +with `-DVRTD_INCLUDE_LIBSLASH=ON`). System dependencies: + +```bash +sudo apt install cmake pkg-config libsystemd-dev libinih-dev +``` + +**Build:** + +```bash +cd vrt/vrtd +cmake -B build -S . -G Ninja +cmake --build build +sudo cmake --install build +``` + +## Running + +```bash +# Manual +sudo vrtd + +# Production (systemd) +sudo systemctl enable --now vrtd +``` + +The daemon reads its configuration from `/etc/vrt/vrtd.conf` (see +`conf/vrtd.conf` for the default format). The configuration file uses +an INI-style format to define roles, user permissions, and per-device +access rules. + +## Minimum toolchain versions + +The baseline is Ubuntu 22.04 LTS/RHEL 9. Lower versions may work but are +untested and may break in any update. + +| Dependency | Minimum version | +|------------|-----------------| +| CMake | 3.22.1 | +| GCC | 11.4.0 | +| glibc | 2.35 | +| Linux | 5.15.0 | +| libsystemd | 249.11 | + +Developers contributing to vrtd are encouraged to make use of useful +extensions and capabilities as long as they are supported by the +versions listed above. + +## Coding conventions + +**Read this section before writing C code for this daemon.** + +This daemon is not written in standard/POSIX C, but instead leans +heavily on C11, libsystemd, glibc features, Linux syscall features, +and GNU compiler extensions (also supported by Clang). The goal is not +to write a portable application, but a modern systemd daemon using all +the tools at our disposal. + +The language version is **C11** with GNU extensions (`-std=gnu11`). +C23 features should not be used unless they are available as GNU +extensions. + +All `.c` source files must start with `#define _GNU_SOURCE` after the +copyright header and before including any other headers. + +For the complete coding style guide — error handling, macros, ownership +rules, RAII patterns, GNU extensions, naming, and formatting — see +**[STYLE.md](STYLE.md)**. + +## License + +MIT — see [LICENSE](../../LICENSE). diff --git a/vrt/vrtd/STYLE.md b/vrt/vrtd/STYLE.md new file mode 100644 index 00000000..783ae4fa --- /dev/null +++ b/vrt/vrtd/STYLE.md @@ -0,0 +1,406 @@ +# vrtd Coding Style + +This document describes the coding conventions used throughout vrtd. +They are descriptive — documenting patterns already established in the +codebase — not aspirational. Contributors should follow them for +consistency, clarity, and correctness. + +## Language and toolchain + +vrtd is **not** written in portable POSIX C. It intentionally uses C11, +GNU compiler extensions (supported by both GCC and Clang), glibc +features, libsystemd, and Linux-specific syscalls. The goal is a modern +systemd daemon that leverages all the tools at our disposal. + +The language standard is **C11** with GNU extensions (`-std=gnu11`). +C23 features should not be used unless they are available as GNU +extensions under `-std=gnu11`. + +The minimum required versions are those shipped by Ubuntu 22.04 LTS: + +| Dependency | Minimum version | +|------------|-----------------| +| CMake | 3.22.1 | +| GCC | 11.4.0 | +| glibc | 2.35 | +| Linux | 5.15.0 | +| libsystemd | 249.11 | + +All `.c` source files must start with `#define _GNU_SOURCE` after the +copyright header and before including any other headers. + +## Error handling + +There is no generally idiomatic way to do error handling in C. Each +project uses its own convention. The following is the convention for +vrtd. + +### Return value convention + +Functions that can fail return an `int`: `-1` for failure, `0` for +success. + +- If a function would naturally be `void` but can fail, make it return + `int` instead. +- If a function would naturally return a non-`int` type but can fail, + return `int` and pass the result via a pointer parameter. +- Do not use integers of smaller sizes for the return value. The value + is returned as a constant, checked immediately, and never used again + — it will only ever live in a register. +- Do **not** return other negative values as failures. The error + handling macros check `== -1` specifically. + +When a function needs to return a value but can also fail, prefer +the pointer-out pattern: + +```c +/* Before: cannot signal failure */ +double div(double x, double y) +{ + return x / y; +} + +/* After: returns -1 on failure, result via pointer */ +int div_safe(double x, double y, double *result) +{ + if (y == 0.0) { + return -1; + } + + if (result == NULL) { + /* Caller does not need the result — not an error. */ + return 0; + } + + *result = x / y; + + return 0; +} +``` + +Use this pattern also when `-1` is a valid value for an `int` result. + +### The PROPAGATE_ERROR macro family + +`utils.h` provides a set of macros that make error handling more +ergonomic. Each macro evaluates an expression, checks the result +against a type-specific failure condition, and — if the check fails — +optionally logs a message via `sd_journal_print` and returns `-1` from +the calling function. + +| Macro | Failure condition | Logging | +|-------|-------------------|---------| +| `PROPAGATE_ERROR(expr)` | `== -1` | None | +| `PROPAGATE_ERROR_NULL(expr)` | `== NULL` | None | +| `PROPAGATE_ERROR_SD(expr)` | `< 0` | None | +| `PROPAGATE_ERROR_LOG(expr, LVL, FMT, ...)` | `== -1` | `sd_journal_print` | +| `PROPAGATE_ERROR_NULL_LOG(expr, LVL, FMT, ...)` | `== NULL` | `sd_journal_print` | +| `PROPAGATE_ERROR_STDC_LOG(expr, LVL, FMT, ...)` | `== -1` | Appends `: %m` (strerror) | +| `PROPAGATE_ERROR_NULL_STDC_LOG(expr, LVL, FMT, ...)` | `== NULL` | Appends `: %m` (strerror) | +| `PROPAGATE_ERROR_SD_LOG(expr, LVL, FMT, ...)` | `< 0` | Appends systemd error string | + +The three conventions handled are: +- **POSIX** (`== -1`): used by most vrtd internal functions. +- **NULL** (`== NULL`): used for allocation and pointer-returning functions. +- **systemd** (`< 0`): used for `sd_*` library calls that return negative errno. + +Example: + +```c +int foo(void) +{ + int ret = bar(); + PROPAGATE_ERROR(ret); + + /* bar() succeeded — continue. */ + + ret = open_resource(); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to open resource"); + + return 0; +} +``` + +If `bar()` returns `-1`, `foo()` immediately returns `-1`. If +`open_resource()` returns `-1`, `foo()` logs the error (with `errno` +context) and returns `-1`. + +### goto-based cleanup + +When a function acquires multiple resources and `PROPAGATE_ERROR` alone +cannot release them, use a `goto fail` pattern with a cleanup label: + +```c +int multi_resource_init(struct thing *t) +{ + /* Zero-initialise so cleanup is safe on early failure. */ + *t = (struct thing) { + .fd = -1, + .buf = NULL, + .resource_acquired = false, + }; + + int ret = acquire_first(t); + if (ret == -1) { + goto fail; + } + + t->resource_acquired = true; + + ret = acquire_second(t); + if (ret == -1) { + goto fail; + } + + return 0; + +fail: + cleanup_thing(t); + return -1; +} +``` + +The cleanup function inspects flags and sentinel values (like `fd == -1` +or `resource_acquired == false`) to safely skip resources that were +never acquired. + +## Resource management (RAII in C) + +### The `_cleanup_` macro + +vrtd uses `__attribute__((cleanup))` for automatic resource cleanup +when variables go out of scope — RAII-style resource management in C: + +```c +#define _cleanup_(FOO) __attribute__((cleanup(FOO))) +``` + +When a variable annotated with `_cleanup_(fn)` goes out of scope, the +compiler calls `fn` with a pointer to that variable. + +### Standard cleanup functions + +| Function | Type | Action | +|----------|------|--------| +| `cleanup_free` | `void *` | `free()` + NULL | +| `cleanup_argv` | `char **` | Frees each string, then the array, + NULL | + +Module-specific cleanup functions follow the naming convention: +- `cleanup_(T *)` — primary cleanup (e.g. `cleanup_buffer`, + `cleanup_role`) +- `cleanup_p(T **)` — indirect variant for use with `_cleanup_`; + calls `cleanup_(*p)` and NULLs `*p` + +### Usage + +```c +_cleanup_(cleanup_free) +char *name = NULL; + +int ret = asprintf(&name, "device-%u", id); +PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Allocation failed"); + +/* name is automatically freed when this scope exits, + whether by return, goto, or reaching the closing brace. */ +``` + +## Ownership conventions + +### Struct member annotations + +Annotate struct members with comments to document who is responsible +for freeing a resource: + +```c +struct buffer { + struct slash_qdma *qdma; /* non-owning */ + struct device_memory_map *map; /* non-owning */ + uint64_t client_id; /* owning connection id */ + int fd; /* owning (must be closed) */ +}; +``` + +- `/* non-owning */` — borrowed reference; the struct must not free it. +- `/* owning */` — the struct is responsible for releasing it. + +### Partial initialization tracking + +When a constructor acquires multiple resources, use boolean flags to +track which resources were successfully created: + +```c +struct buffer { + /* ... */ + bool allocation_valid; /* address-space allocation exists */ + bool qpair_created; /* QDMA queue pair exists */ +}; +``` + +Zero-initialize the struct (via designated initializers) before +beginning the multi-step setup. The cleanup function checks the flags +to skip resources that were never acquired: + +```c +*buf = (struct buffer) { + .fd = -1, + .allocation_valid = false, + .qpair_created = false, +}; +``` + +### Ownership transfer + +The `push_move` function (generated by `DECLARE_OWNING_PTR_ARRAY`) +transfers ownership of a pointer into the array by NULLing the source. +This prevents double-free: + +```c +struct widget *w = widget_new(); +widget_array_push_move(&widgets, &w); +/* w is now NULL — only the array owns the widget. */ +``` + +## Type-safe generic data structures + +`array.h` provides macro-generated dynamic arrays in two flavors. + +### `DECLARE_ARRAY(name, T)` + +Declares a value-type dynamic array. Elements are copied on push and +not individually freed on array destruction. + +```c +DECLARE_ARRAY(int_array, int) + +struct int_array arr = int_array_init(); +int_array_push(&arr, 42); +printf("len=%zu, first=%d\n", arr.len, arr.d[0]); +int_array_free(&arr); +``` + +### `DECLARE_OWNING_PTR_ARRAY(name, T, cleanup)` + +Declares a pointer-type dynamic array that owns its elements. On +destruction (or element removal), each element is passed through the +cleanup function. + +```c +DECLARE_OWNING_PTR_ARRAY(widget_array, struct widget *, cleanup_widget) + +struct widget_array widgets = widget_array_init(); +struct widget *w = widget_new(); +widget_array_push_move(&widgets, &w); /* w is now NULL */ +widget_array_free(&widgets); /* calls cleanup_widget on each */ +``` + +### Generated API + +Both macros generate: `_init`, `_push`, `_pop`, `_pop_safe`, `_resize`, +`_shrink_to_fit`, `_zero`, `_free`. + +`DECLARE_OWNING_PTR_ARRAY` additionally generates: `_push_move`, +`_rm_by_reference`. + +### Pre-declared array types + +| Type | Element | Flavor | +|------|---------|--------| +| `int_array` | `int` | value | +| `uint_array` | `unsigned int` | value | +| `gid_t_array` | `gid_t` | value | +| `str_array` | `char *` | owning (freed with `free`) | + +## GNU extensions + +The following GCC/Clang extensions are used throughout vrtd: + +| Extension | vrtd usage | Purpose | +|-----------|-----------|---------| +| `__attribute__((cleanup))` | `_cleanup_(fn)` | RAII-style automatic cleanup | +| `__attribute__((warn_unused_result))` | `NODISCARD` | Force callers to check return values | +| `__auto_type` | `PROPAGATE_ERROR_*`, `max`, `min` | Type inference without double-evaluation | +| Statement expressions `({ })` | `max(a,b)`, `min(a,b)`, `PROPAGATE_ERROR_*` | Multi-statement macros that yield a value | +| `__builtin_expect` | `likely(x)`, `unlikely(x)` | Branch prediction hints | +| `__builtin_clz`, `__builtin_clzll` | `bit_ceil_u32`, `bit_ceil_u64` | Count leading zeros for power-of-two rounding | +| `_Generic` | `bit_ceil(n)` | Type-generic dispatch (C11, used with GCC builtins) | +| `##__VA_ARGS__` | `PROPAGATE_ERROR_*_LOG` | Suppress trailing comma with zero variadic args | +| `_GNU_SOURCE` glibc | `reallocarray`, `asprintf`, `strerrordesc_np`, `%m` | Extended libc functions | + +## Naming conventions + +| Element | Convention | Examples | +|---------|-----------|----------| +| Functions, variables | `snake_case` | `buffer_create`, `client_id` | +| Module prefixes | `_` | `buffer_`, `allocator_`, `auth_`, `config_`, `cleanup_` | +| Cleanup functions | `cleanup_` / `cleanup_p` | `cleanup_buffer`, `cleanup_bufferp` | +| Macros, constants | `UPPER_CASE` | `PROPAGATE_ERROR`, `LOG`, `HBM_REGIONS` | +| Struct types | `struct snake_case` (no typedefs) | `struct buffer`, `struct client` | +| Enum values | `UPPER_CASE` with type prefix | `ALLOCATION_TYPE_DDR`, `ALLOCATION_RESULT_SUCCESS` | +| Header guards | `VRTD__H` | `VRTD_UTILS_H`, `VRTD_BUFFER_H` | + +## Formatting + +- **Indentation**: 4 spaces. No tabs. +- **Control flow braces**: opening brace on the same line. + ```c + if (ret == -1) { + return -1; + } + ``` +- **Function definition braces**: opening brace on its own line. + ```c + int buffer_create(struct buffer *buf) + { + /* ... */ + } + ``` + Short `static inline` helpers in headers may use same-line braces. +- **Designated initializers**: always used for struct initialization. + ```c + *buf = (struct buffer) { + .fd = -1, + .allocation_valid = false, + }; + ``` + +## File structure + +### Source files (`.c`) + +1. MIT license header (block comment) +2. Doxygen `@file` / `@brief` comment +3. `#define _GNU_SOURCE` +4. Local (project) headers with quotes: `"buffer.h"`, `"utils.h"` +5. System headers with angle brackets: ``, `` +6. systemd headers: ``, `` +7. File-scope constants and static prototypes +8. Function implementations + +### Header files (`.h`) + +1. MIT license header +2. Doxygen `@file` / `@brief` / `@section` documentation +3. Include guard (`#ifndef VRTD__H`) +4. Includes (same ordering as `.c`) +5. Constants and macro definitions +6. Type definitions (structs, enums) +7. Function declarations with Doxygen `@brief` / `@param` / `@return` +8. Static inline implementations (cleanup helpers, utilities) +9. `#endif` + +## Logging + +All daemon logging goes through the `LOG` macro, which is shorthand for +`sd_journal_print` (cast to `void` to suppress unused-result warnings): + +```c +LOG(LOG_ERR, "Failed to open device %s", path); +LOG(LOG_DEBUG, "Buffer allocated: addr=0x%llx size=%llu", addr, size); +``` + +Log levels follow the syslog convention: `LOG_CRIT`, `LOG_ERR`, +`LOG_WARNING`, `LOG_INFO`, `LOG_DEBUG`. + +Prefer the `_LOG` variants of the `PROPAGATE_ERROR` macros over a +manual `LOG` + `return -1` pair when the error propagation pattern +fits — they are more concise and harder to get wrong. diff --git a/vrt/vrtd/cmake/ami.cmake b/vrt/vrtd/cmake/ami.cmake new file mode 100644 index 00000000..93b1abe6 --- /dev/null +++ b/vrt/vrtd/cmake/ami.cmake @@ -0,0 +1,68 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +set(AMI_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../submodules/AVED/sw/AMI") +set(AMI_API_DIR "${AMI_DIR}/api") +set(AMI_API_SRC_DIR "${AMI_API_DIR}/src") +set(AMI_API_INCLUDE_DIR "${AMI_API_DIR}/include") + +add_library( + ami + + STATIC + + "${AMI_API_SRC_DIR}/ami.c" + "${AMI_API_SRC_DIR}/ami_device.c" + "${AMI_API_SRC_DIR}/ami_eeprom_access.c" + "${AMI_API_SRC_DIR}/ami_mem_access.c" + "${AMI_API_SRC_DIR}/ami_mfg_info.c" + "${AMI_API_SRC_DIR}/ami_module_access.c" + "${AMI_API_SRC_DIR}/ami_program.c" + "${AMI_API_SRC_DIR}/ami_sensor.c" +) + +target_include_directories( + ami + + PUBLIC + ${AMI_API_INCLUDE_DIR} + # AMI_API_SRC_DIR is exposed as PUBLIC rather than PRIVATE so that vrtd can + # include ami_ioctl.h and ami_device_internal.h directly. This is necessary + # because ami_prog_device_boot() (the natural public API for setting the boot + # partition) internally calls ami_dev_hot_reset(), which performs its own + # remove-device / toggle-SBR / rescan sequence by opening the PCI config-space + # sysfs file (O_RDWR on /sys/bus/pci/devices//config). That file is + # mode 0600 and owned by root, so the open fails with EBADF when vrtd runs as + # the unprivileged 'vrtd' user. Even if we granted the capability required to + # open it, ami_dev_hot_reset would still conflict with vrtd's own hotplug + # reset sequence (slash_hotplug_remove / slash_hotplug_toggle_sbr / + # slash_hotplug_rescan), resulting in the device being reset twice. + # + # The correct behaviour for vrtd is to issue the AMI_IOC_DEVICE_BOOT ioctl + # only (to set the AMC firmware boot partition), and then let vrtd manage the + # full hotplug reset itself. There is no public AMI API that does just the + # ioctl without the embedded hot-reset, so we call it directly from reset.c + # using the internal headers. The AMI library is a static library consumed + # exclusively by vrtd, so widening the include visibility has no impact on + # other consumers. + ${AMI_API_SRC_DIR} +) + +add_library(ami::ami ALIAS ami) diff --git a/examples/05_perf/hls/Makefile b/vrt/vrtd/cmake/vrtdConfig.cmake.in similarity index 83% rename from examples/05_perf/hls/Makefile rename to vrt/vrtd/cmake/vrtdConfig.cmake.in index ee05056d..6edcd9f8 100644 --- a/examples/05_perf/hls/Makefile +++ b/vrt/vrtd/cmake/vrtdConfig.cmake.in @@ -18,17 +18,12 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -TARGET=ip -DEVICE=xcv80-lsva4737-2MHP-e-S +@PACKAGE_INIT@ -PERF_BUILD_DIR=build_perf.$(DEVICE) +include(CMakeFindDependencyMacro) -all: $(PERF_BUILD_DIR) +# If you have dependencies, call find_dependency() here. +# e.g.: find_dependency(Threads) +find_dependency(slash) -$(PERF_BUILD_DIR): - if [ ! -d "$(PERF_BUILD_DIR)" ]; then \ - vitis_hls build.tcl -tclargs $(TARGET) $(DEVICE) perf; \ - fi - -clean: - rm -rf $(PERF_BUILD_DIR) vitis_hls.log \ No newline at end of file +include("${CMAKE_CURRENT_LIST_DIR}/vrtdTargets.cmake") diff --git a/vrt/vrtd/conf/vrtd.conf b/vrt/vrtd/conf/vrtd.conf new file mode 100644 index 00000000..aaab3618 --- /dev/null +++ b/vrt/vrtd/conf/vrtd.conf @@ -0,0 +1,47 @@ +; ################################################################################################## +; The MIT License (MIT) +; Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy of this software +; and associated documentation files (the "Software"), to deal in the Software without restriction, +; including without limitation the rights to use, copy, modify, merge, publish, distribute, +; sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in all copies or +; substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +; NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +; NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +; DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; ################################################################################################## +include-glob = vrtd.conf.d/*.conf + +; Full access role: grants all subsystem permissions on all devices. +; Uses the new per-device sub-section syntax with the "any" wildcard. +[role:fullaccess] +query-devices = yes + +[role:fullaccess:any] +bar-access = full +qdma = yes +buffer = yes +design-write = yes +clock = yes +pcie-hotplug = yes +raw-mem-access = yes + +; Info-only role: can enumerate and query devices but not access them. +[role:info] +query-devices = yes + +[user:root] +role = fullaccess + +[group:vrtadmin] +role = fullaccess + +[user:*] +role = info diff --git a/vrt/vrtd/include/vrtd/wire.h b/vrt/vrtd/include/vrtd/wire.h new file mode 100644 index 00000000..4749afd4 --- /dev/null +++ b/vrt/vrtd/include/vrtd/wire.h @@ -0,0 +1,457 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file wire.h + * @brief On‑wire protocol for vrtd (V80 Runtime Daemon). + * + * Transport: + * - UNIX domain sockets (AF_UNIX, SOCK_SEQPACKET). Messages are record‑oriented. + * - File descriptors may be sent out‑of‑band using SCM_RIGHTS. + * + * Framing: + * - Each message = { header, body }. + * - Total size (header + body) MUST be <= VRTD_MSG_MAX_SIZE. + * + * Sequencing: + * - Requests carry a client‑chosen @ref vrtd_req_header::seqno that is echoed + * unmodified by the server in @ref vrtd_resp_header::seqno. + * + * Versioning/Extensibility: + * - Unknown opcodes result in VRTD_RET_BAD_REQUEST. + * - New fields may be added at the *end* of messages; older peers must ignore + * trailing bytes up to @ref vrtd_resp_header::size. + * + * Security: + * - Server enforces permissions; failures surface as VRTD_RET_AUTH_ERROR. + */ + +#ifndef VRTD_WIRE_H +#define VRTD_WIRE_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Maximum total size (header + body) for any vrtd message in bytes. */ +#define VRTD_MSG_MAX_SIZE 4096 + +/** + * @brief Operations the client can request from the server. + * @note Unknown/unsupported opcodes yield VRTD_RET_BAD_REQUEST. + */ +enum vrtd_opcode { + /** Query the number of SLASH devices. */ + VRTD_REQ_GET_NUM_DEVICES, + + /** Query basic information about a device. */ + VRTD_REQ_GET_DEVICE_INFO, + + /** Query metadata about a device BAR. */ + VRTD_REQ_GET_BAR_INFO, + + /** Obtain a device BAR file descriptor via SCM_RIGHTS. */ + VRTD_REQ_GET_BAR_FD, + + /** Query QDMA capabilities of a device. */ + VRTD_REQ_QDMA_GET_INFO, + + /** Create a QDMA qpair on a device. */ + VRTD_REQ_QDMA_QPAIR_ADD, + + /** Apply an operation (start/stop/del) to a QDMA qpair. */ + VRTD_REQ_QDMA_QPAIR_OP, + + /** Obtain a read/write file descriptor for a QDMA qpair. */ + VRTD_REQ_QDMA_QPAIR_GET_FD, + + /** Perform a design writer transfer by passing an input fd via SCM_RIGHTS. */ + VRTD_REQ_DESIGN_WRITE, + + /** Get or set a clock rate for the service/user region. */ + VRTD_REQ_CLOCK_OP, + + /** Open a buffer (allocation + QDMA qpair) and return a qpair fd. */ + VRTD_REQ_BUFFER_OPEN, + + /** Close a buffer (release allocation + QDMA qpair). */ + VRTD_REQ_BUFFER_CLOSE, + + /** Query a device index by PCI BDF. */ + VRTD_REQ_GET_DEVICE_BY_BDF, + + /** Perform a PCIe hotplug operation for a device. */ + VRTD_REQ_DEVICE_HOTPLUG_OP, + + /** Query sensor information for a device via AMI. */ + VRTD_REQ_GET_SENSOR_INFO, + + /** Open a raw buffer (QDMA qpair at caller-specified device address, bypassing allocator). */ + VRTD_REQ_BUFFER_OPEN_RAW, +}; + +/** + * @brief Return codes for vrtd operations. + * + * @warning VRTD_RET_BAD_LIB_CALL and VRTD_RET_BAD_CONN are **client‑local** + * and are never returned by the server on the wire. + */ + +enum vrtd_ret { + VRTD_RET_OK, + VRTD_RET_BAD_LIB_CALL, ///< Bad library call to libvrtd. This code will not be returned on the wire. + VRTD_RET_BAD_CONN, ///< libvrtd could not connect to vrtd. This code will not be returned on the wire. + VRTD_RET_BAD_REQUEST, ///< Malformed request. + VRTD_RET_INVALID_ARGUMENT, ///< Invalid argument. + VRTD_RET_NOEXIST, ///< Requested resource does not exist. + VRTD_RET_INTERNAL_ERROR, ///< Internal error in the vrtd daemon. Check the vrtd log. + VRTD_RET_AUTH_ERROR, ///< User does not have permission to execute request. + VRTD_RET_BUSY, ///< Requested resource is busy. +}; + +/** + * @brief Allocation types for buffer requests. + */ +enum vrtd_alloc_type { + VRTD_ALLOC_TYPE_DDR = 0, + VRTD_ALLOC_TYPE_HBM = 1, + VRTD_ALLOC_TYPE_HBM_VNOC = 2, +}; + +/** + * @brief Direction for data transfers for allocated buffer. + */ +enum vrtd_alloc_dir { + VRTD_ALLOC_DIR_BIDIRECTIONAL = 0, + VRTD_ALLOC_DIR_HOST_TO_DEVICE = 1, + VRTD_ALLOC_DIR_DEVICE_TO_HOST = 2, +}; + +#define VRTD_PCI_BDF_LEN 32 + +struct vrtd_pci_info { + char bdf[VRTD_PCI_BDF_LEN]; + uint16_t vendor_id; + uint16_t device_id; + uint16_t subsystem_vendor_id; + uint16_t subsystem_device_id; +} __attribute__((packed)); + +struct vrtd_req_header { + uint16_t size; ///< Size of the request body (not including the header). + uint16_t opcode; ///< See @ref vrtd_opcode. + uint32_t seqno; ///< Sequence number (this will simply be echoed by the server in the response header). +} __attribute__((packed)); + +struct vrtd_resp_header { + uint16_t size; ///< Size of the response body (not including the header). + uint16_t ret; ///< See @ref vrtd_ret. + uint32_t seqno; ///< Sequence number (this is simply echoed from the request header). +} __attribute__((packed)); + +/** + * @brief Placeholder body to avoid empty-struct ABI pitfalls across C/C++. + * @note Must be set to zero by clients; servers must ignore its value. + */ +struct vrtd_req_get_num_devices { + uint8_t zero; +} __attribute__((packed)); + + +struct vrtd_resp_get_num_devices { + uint32_t num_devices; ///< Number of SLASH devices known to the server. They are identified by numbers in the range [0, n). +} __attribute__((packed)); + + +struct vrtd_req_get_device_info { + uint32_t dev_number; ///< The device for which to get info. An index in the range [0, n). +} __attribute__((packed)); + +struct vrtd_device_info { + char name[128]; ///< The name of the device. + struct vrtd_pci_info pci; ///< PCIe metadata (BDF and IDs). +} __attribute__((packed)); + +struct vrtd_resp_get_device_info { + struct vrtd_device_info info; +} __attribute__((packed)); + +struct vrtd_req_get_device_by_bdf { + char bdf[VRTD_PCI_BDF_LEN]; ///< PCI BDF string (e.g., 0000:65:00.0) +} __attribute__((packed)); + +struct vrtd_resp_get_device_by_bdf { + uint32_t dev_number; ///< Device index (0-based). +} __attribute__((packed)); + +struct vrtd_req_get_bar_info { + uint32_t dev_number; ///< The device for which to get info. An index in the range [0, n). + uint8_t bar_number; ///< The BAR for which to get info. An index in the range [0, 6). +} __attribute__((packed)); + +struct vrtd_resp_get_bar_info { + struct slash_ioctl_bar_info bar_info; ///< The structure with BAR information. +} __attribute__((packed)); + +struct vrtd_req_get_bar_fd { + uint32_t dev_number; ///< The device for who's BAR to get a file descriptor. An index in the range [0, n). + uint8_t bar_number; ///< The BAR for which to get a file descriptor. An index in the range [0, 6). +} __attribute__((packed)); + +/** + * @brief Response to VRTD_REQ_GET_BAR_FD. + * + * The BAR file descriptor is sent out-of-band via SCM_RIGHTS in the same + * message and is present only when @ref vrtd_resp_header::ret == VRTD_RET_OK. + */ +struct vrtd_resp_get_bar_fd { + uint64_t len; ///< Size of the BAR address space; suitable for mmap. +} __attribute__((packed)); + +/** + * @brief Request QDMA capability information for a device. + * + * Complementary to @c slash_qdma_info; this wraps the libslash QDMA + * info query and exposes it over the vrtd protocol. + */ +struct vrtd_req_qdma_get_info { + uint32_t dev_number; ///< The device for which to get QDMA info. An index in the range [0, n). +} __attribute__((packed)); + +struct vrtd_resp_qdma_get_info { + struct slash_qdma_info info; ///< QDMA capabilities for the device. +} __attribute__((packed)); + +/** + * @brief Request creation of a QDMA qpair. + * + * The @c slash_qdma_qpair_add payload is passed through to the kernel + * and the resulting qid is returned in the response. + */ +struct vrtd_req_qdma_qpair_add { + uint32_t dev_number; ///< Device index (0-based). + struct slash_qdma_qpair_add add; ///< Qpair creation parameters. +} __attribute__((packed)); + +struct vrtd_resp_qdma_qpair_add { + struct slash_qdma_qpair_add add; ///< Echoed qpair parameters with qid filled in. +} __attribute__((packed)); + +/** + * @brief Request an operation on an existing QDMA qpair. + * + * @ref op uses the same numeric values as @c SLASH_QDMA_QUEUE_OP_START and friends. + */ +struct vrtd_req_qdma_qpair_op { + uint32_t dev_number; ///< Device index (0-based). + uint32_t qid; ///< Qpair identifier as returned by qpair_add. + uint32_t op; ///< One of SLASH_QDMA_QUEUE_OP_{START,STOP,DEL}. +} __attribute__((packed)); + +struct vrtd_resp_qdma_qpair_op { + uint8_t zero; ///< Placeholder to avoid empty-struct ABI issues. +} __attribute__((packed)); + +/** + * @brief Request a read/write file descriptor for a QDMA qpair. + * + * The qpair FD is sent out-of-band via SCM_RIGHTS when + * @ref vrtd_resp_header::ret == VRTD_RET_OK. + */ +struct vrtd_req_qdma_qpair_get_fd { + uint32_t dev_number; ///< Device index (0-based). + uint32_t qid; ///< Qpair identifier as returned by qpair_add. + uint32_t flags; ///< Only O_CLOEXEC is currently honored. +} __attribute__((packed)); + +struct vrtd_resp_qdma_qpair_get_fd { + uint8_t zero; ///< Placeholder; all data is carried via SCM_RIGHTS. +} __attribute__((packed)); + +/** + * @brief Request a buffer (allocation + QDMA qpair) and a qpair FD. + * + * The qpair FD is sent out-of-band via SCM_RIGHTS when + * @ref vrtd_resp_header::ret == VRTD_RET_OK. + */ +struct vrtd_req_buffer_open { + uint32_t dev_number; ///< Device index (0-based). + uint32_t alloc_type; ///< One of enum vrtd_alloc_type. + uint32_t alloc_dir; ///< One of enum vrtd_alloc_dir. + uint64_t alloc_arg; ///< Allocation argument (HBM region index for HBM). + uint64_t size; ///< Requested size in bytes. +} __attribute__((packed)); + +struct vrtd_resp_buffer_open { + uint64_t size; ///< Allocated size in bytes (rounded up to subregion). + uint64_t phys_addr; ///< Device physical address of the allocation. +} __attribute__((packed)); + +/** + * @brief Request closing a buffer (release allocation + QDMA qpair). + */ +struct vrtd_req_buffer_close { + uint32_t dev_number; ///< Device index (0-based). + uint64_t phys_addr; ///< Device physical address of the allocation. + uint64_t size; ///< Allocated size in bytes. +} __attribute__((packed)); + +struct vrtd_resp_buffer_close { + uint8_t zero; ///< Placeholder to avoid empty-struct ABI issues. +} __attribute__((packed)); + +/** + * @brief Request a raw buffer (QDMA qpair at caller-specified device address). + * + * Bypasses the allocator entirely — the caller is responsible for ensuring the + * address is valid and not in use. Requires the @c raw-mem-access permission. + * + * The qpair FD is sent out-of-band via SCM_RIGHTS when + * @ref vrtd_resp_header::ret == VRTD_RET_OK. + */ +struct vrtd_req_buffer_open_raw { + uint32_t dev_number; ///< Device index (0-based). + uint32_t alloc_dir; ///< One of enum vrtd_alloc_dir. + uint64_t phys_addr; ///< Caller-specified device physical address (bypasses allocator). + uint64_t size; ///< Size in bytes. +} __attribute__((packed)); + +struct vrtd_resp_buffer_open_raw { + uint8_t zero; ///< Placeholder; all data is carried via SCM_RIGHTS. +} __attribute__((packed)); + +/** + * @brief Request a design writer transfer. + * + * The input file descriptor is sent out-of-band via SCM_RIGHTS. + */ +struct vrtd_req_design_write { + uint32_t dev_number; ///< Device index (0-based). +} __attribute__((packed)); + +struct vrtd_resp_design_write { + uint8_t zero; ///< Placeholder; all data is carried via SCM_RIGHTS. +} __attribute__((packed)); + +enum vrtd_device_hotplug_op { + VRTD_DEVICE_HOTPLUG_OP_RESCAN = 0, + VRTD_DEVICE_HOTPLUG_OP_REMOVE = 1, + VRTD_DEVICE_HOTPLUG_OP_TOGGLE_SBR = 2, + VRTD_DEVICE_HOTPLUG_OP_HOTPLUG = 3, + VRTD_DEVICE_HOTPLUG_OP_RESET_SEQUENCE = 4, +}; + +/** + * @brief Request a PCIe hotplug operation for a device. + * + * For board-level operations (RESCAN, RESET_SEQUENCE), only dev_number + * and op are required; the function field is ignored. + * + * For PF-level operations (REMOVE, TOGGLE_SBR, HOTPLUG), the function + * field selects the PCI physical function (0-7). These operations are + * SLASH-agnostic shortcuts to the kernel hotplug interface. + */ +struct vrtd_req_device_hotplug_op { + uint32_t dev_number; ///< Device index (0-based). + uint8_t op; ///< One of vrtd_device_hotplug_op. + uint8_t function; ///< PCI function number (0-7) for PF-level ops. +} __attribute__((packed)); + +struct vrtd_resp_device_hotplug_op { + uint8_t zero; ///< Placeholder to avoid empty-struct ABI issues. +} __attribute__((packed)); + +enum vrtd_clock_region { + VRTD_CLOCK_REGION_SERVICE = 0, + VRTD_CLOCK_REGION_USER = 1, +}; + +enum vrtd_clock_op { + VRTD_CLOCK_OP_GET = 0, + VRTD_CLOCK_OP_SET = 1, +}; + +/** + * @brief Request a clock operation (get/set) for a region. + */ +struct vrtd_req_clock_op { + uint32_t dev_number; ///< Device index (0-based). + uint32_t rate_hz; ///< Desired rate for SET; ignored for GET. + uint8_t op; ///< One of vrtd_clock_op. + uint8_t region; ///< One of vrtd_clock_region. +} __attribute__((packed)); + +struct vrtd_resp_clock_op { + uint32_t rate_hz; ///< Current/achieved rate for GET/SET. +} __attribute__((packed)); + +/** + * @brief Maximum number of sensor entries that fit in a single response message. + */ +#define VRTD_SENSOR_MAX_ENTRIES \ + ((VRTD_MSG_MAX_SIZE - sizeof(struct vrtd_resp_header) - sizeof(uint32_t)) \ + / sizeof(struct vrtd_sensor_entry)) + +/** + * @brief A single sensor reading. + * + * Each entry corresponds to one (sensor-name, sensor-type) pair. + * For example, "vccint" may produce separate entries for temperature, + * voltage, current, and power. + */ +struct vrtd_sensor_entry { + char name[64]; ///< Sensor name (e.g., "vccint"). + uint8_t type; ///< Sensor type bitmask (1=temp, 2=current, 4=voltage, 8=power). + uint8_t status; ///< Sensor status (0x01 = OK, see AMI sensor status codes). + int8_t unit_mod; ///< Unit modifier exponent (e.g., -3 for milli-). + uint8_t _pad; ///< Reserved, must be zero. + int32_t value; ///< Sensor reading (apply 10^unit_mod to get base unit value). +} __attribute__((packed)); + +/** + * @brief Request sensor information for a device. + * + * The daemon opens an AMI handle, discovers sensors, reads their values, + * and returns them all in the response. + */ +struct vrtd_req_get_sensor_info { + uint32_t dev_number; ///< Device index (0-based). +} __attribute__((packed)); + +/** + * @brief Response to VRTD_REQ_GET_SENSOR_INFO. + * + * Contains a variable number of sensor entries. The actual response size + * is sizeof(num_sensors) + num_sensors * sizeof(struct vrtd_sensor_entry). + */ +struct vrtd_resp_get_sensor_info { + uint32_t num_sensors; ///< Number of sensor entries following. + struct vrtd_sensor_entry sensors[]; ///< Variable-length array of sensor entries. +} __attribute__((packed)); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // VRTD_WIRE_H diff --git a/vrt/vrtd/libvrtd/CMakeLists.txt b/vrt/vrtd/libvrtd/CMakeLists.txt new file mode 100644 index 00000000..734c1cbb --- /dev/null +++ b/vrt/vrtd/libvrtd/CMakeLists.txt @@ -0,0 +1,21 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_subdirectory(src) diff --git a/vrt/vrtd/libvrtd/doc/Doxyfile b/vrt/vrtd/libvrtd/doc/Doxyfile new file mode 100644 index 00000000..1e6f06a2 --- /dev/null +++ b/vrt/vrtd/libvrtd/doc/Doxyfile @@ -0,0 +1,44 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# Doxyfile for libvrtd — generates XML for Sphinx/Breathe integration. +# Covers both the C client API (vrtd.h) and the shared wire protocol (wire.h). + +PROJECT_NAME = "libvrtd" +PROJECT_BRIEF = "C client library for the V80 Runtime Daemon" + +OUTPUT_DIRECTORY = ./docs + +# ../include picks up vrtd/vrtd.h; ../../include picks up vrtd/wire.h +INPUT = ../include ../../include +RECURSIVE = YES +FILE_PATTERNS = *.h + +EXTRACT_ALL = YES +EXTRACT_STATIC = YES +OPTIMIZE_OUTPUT_FOR_C = YES + +MACRO_EXPANSION = YES +PREDEFINED = __attribute__(x)= + +GENERATE_HTML = NO +GENERATE_LATEX = NO +GENERATE_XML = YES +XML_OUTPUT = xml diff --git a/vrt/vrtd/libvrtd/include/vrtd/vrtd.h b/vrt/vrtd/libvrtd/include/vrtd/vrtd.h new file mode 100644 index 00000000..76cf2541 --- /dev/null +++ b/vrt/vrtd/libvrtd/include/vrtd/vrtd.h @@ -0,0 +1,587 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file vrtd.h + * @brief C client API for the V80 Runtime Daemon (vrtd). + * + * This library (libvrtd) provides a client interface to the VRT daemon (vrtd), + * which multiplexes access to SLASH-managed FPGA devices + * with permission control and multi‑tenancy. + * + * Stack overview: + * slash (kernel module) <- libslash <- vrtd <- libvrtd <- libvrtdpp <- libvrt + * + * Most functions return a #vrtd_ret code. On success, functions return + * #VRTD_RET_OK and populate their output parameters. + */ + +#ifndef LIBVRTD_VRTD_H +#define LIBVRTD_VRTD_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @def VRTD_STANDARD_PATH + * @brief Default UNIX domain socket path for the vrtd daemon. + */ +#define VRTD_STANDARD_PATH "/run/vrtd.sock" + +struct vrtd_buffer; + + +/** + * @brief Connect to the vrtd UNIX domain socket. + * + * Creates a SOCK_SEQPACKET connection to the vrtd daemon at @p path. + * + * @param path Absolute path to the vrtd socket (e.g. ::VRTD_STANDARD_PATH). + * Must not be NULL. + * @return On success, a non‑negative file descriptor to the socket. The caller + * owns this descriptor and must close it with @c close(). + * @return On failure, returns -1 and sets @c errno. + */ +int vrtd_connect(const char *path); + + +/** + * @brief Send a raw vrtd protocol request and receive the response. + * + * This is a low‑level escape hatch for issuing arbitrary protocol opcodes. + * Most users should prefer higher‑level helpers (e.g., vrtd_get_* functions). + * + * @param fd Connected vrtd socket file descriptor. + * @param opcode Protocol opcode to send (see @ref vrtd_opcode in wire.h). + * @param body Pointer to request body buffer (may be NULL if @p body_size == 0). + * @param body_size Size of request body in bytes. + * @param resp_buf Buffer to receive the response body (may be NULL if no body expected). + * @param resp_bufsz Size of @p resp_buf in bytes. + * @param resp_fd Optional; if non‑NULL and the response carries a file + * descriptor (e.g., GET_BAR_FD), the received FD will be + * stored here. Otherwise ignored. + * @param req_fd Optional; if non‑NULL and @p *req_fd >= 0, the FD will + * be sent to the daemon via SCM_RIGHTS. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * + * @warning The request size must not exceed the protocol limit + * (e.g., @c VRTD_MSG_MAX_SIZE - sizeof(struct vrtd_req_header)). + * @note On success, @p resp_buf contains exactly the response body bytes. + * @note @p resp_fd and @p req_fd are optional. + */ +enum vrtd_ret vrtd_raw_request( + int fd, + uint16_t opcode, + const void *body, uint16_t body_size, + void *resp_buf, size_t resp_bufsz, + int *resp_fd, + const int *req_fd +); + + +/** + * @brief Query the number of available devices. + * + * @param fd Connected vrtd socket file descriptor. + * @param num_devices_out Output pointer to receive the device count. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p num_devices_out must not be NULL. + */ +enum vrtd_ret vrtd_get_num_devices( + int fd, + uint32_t *num_devices_out +); + +/** + * @brief Get information about a device (name + PCI info). + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param info_out Output device info (name + PCI metadata). + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p info_out must not be NULL. + */ +enum vrtd_ret vrtd_get_device_info( + int fd, + uint32_t dev, + struct vrtd_device_info *info_out +); + +/** + * @brief Look up a device index by PCI BDF. + * + * @param fd Connected vrtd socket file descriptor. + * @param bdf PCI BDF string (e.g., "0000:65:00.0"). + * @param dev_out Output device index. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p bdf and @p dev_out must not be NULL. + */ +enum vrtd_ret vrtd_get_device_by_bdf( + int fd, + const char *bdf, + uint32_t *dev_out +); + +/** + * @brief Retrieve information about a device BAR (Base Address Register). + * + * Complementary to vrtd_get_bar_fd(); this returns metadata only. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param bar BAR index. + * @param bar_info_out Output pointer for BAR info (layout, permissions, etc.). + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p bar_info_out must not be NULL. + */ +enum vrtd_ret vrtd_get_bar_info( + int fd, + uint32_t dev, + uint8_t bar, + struct slash_ioctl_bar_info *bar_info_out +); + +/** + * @brief Obtain a file descriptor for a device BAR, suitable for @c mmap(). + * + * Complementary to vrtd_get_bar_info(); this returns a handle to the BAR memory. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param bar BAR index. + * @param fd_out Output pointer to receive the BAR file descriptor. + * @param len_out Output pointer to receive the BAR length in bytes. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p fd_out and @p len_out must not be NULL. + * @note The caller owns the returned FD and should close it when no longer needed + * (or use vrtd_open_bar_file()/vrtd_close_bar_file()). + */ +enum vrtd_ret vrtd_get_bar_fd( + int fd, + uint32_t dev, + uint8_t bar, + int *fd_out, + uint64_t *len_out +); + +/** + * @brief Open a BAR and map it into the process address space. + * + * Convenience helper that requests a BAR FD and performs @c mmap() into + * @p bar_file_out->map with length @p bar_file_out->len. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param bar BAR index. + * @param bar_file_out Output structure receiving the BAR FD, length and mapping. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p bar_file_out must not be NULL. + * @post On success, @p bar_file_out->fd is valid and @p bar_file_out->map is + * a writable shared mapping of size @p bar_file_out->len. + * @warning The caller must later call vrtd_close_bar_file() to unmap and close. + */ +enum vrtd_ret vrtd_open_bar_file( + int fd, + uint32_t dev, + uint8_t bar, + struct slash_bar_file *bar_file_out +); + +/** + * @brief Unmap and close resources acquired by vrtd_open_bar_file(). + * + * Safe to call with NULL and safe to call multiple times; on first successful + * call it unmaps, closes the FD, and clears @p bar_file_out->map. + * + * @param bar_file_out Pointer previously filled by vrtd_open_bar_file(). + */ +void vrtd_close_bar_file( + struct slash_bar_file *bar_file_out +); + +/** + * @brief Query QDMA capabilities for a device. + * + * Thin wrapper around the vrtd QDMA GET_INFO opcode. On success, + * fills @p info_out with the kernel's view of the QDMA device. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param info_out Output pointer for QDMA capability information. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p info_out must not be NULL. + */ +enum vrtd_ret vrtd_qdma_get_info( + int fd, + uint32_t dev, + struct slash_qdma_info *info_out +); + +/** + * @brief Create a QDMA qpair on a device. + * + * On success, @p qpair_inout is updated with the kernel‑assigned qid. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param qpair_inout In/out QDMA qpair parameters (see slash_qdma_qpair_add). + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p qpair_inout must not be NULL. + */ +enum vrtd_ret vrtd_qdma_qpair_add( + int fd, + uint32_t dev, + struct slash_qdma_qpair_add *qpair_inout +); + +/** + * @brief Start, stop, or delete a QDMA qpair. + * + * Convenience wrappers around the QDMA qpair OP opcode. + */ +enum vrtd_ret vrtd_qdma_qpair_start( + int fd, + uint32_t dev, + uint32_t qid +); + +enum vrtd_ret vrtd_qdma_qpair_stop( + int fd, + uint32_t dev, + uint32_t qid +); + +enum vrtd_ret vrtd_qdma_qpair_del( + int fd, + uint32_t dev, + uint32_t qid +); + +/** + * @brief Obtain a read/write file descriptor for a QDMA qpair. + * + * The descriptor can be used with read()/write() for C2H/H2C data transfer. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param qid Qpair identifier as returned by vrtd_qdma_qpair_add(). + * @param flags OR of O_CLOEXEC and 0 (other flags are rejected by the daemon). + * @param fd_out Output pointer to receive the qpair file descriptor. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p fd_out must not be NULL. + */ +enum vrtd_ret vrtd_qdma_qpair_get_fd( + int fd, + uint32_t dev, + uint32_t qid, + uint32_t flags, + int *fd_out +); + +/** + * @brief Open a buffer (allocation + QDMA qpair) and obtain its FD. + * + * Requests a device memory allocation and creates a QDMA qpair for it. + * The returned file descriptor is owned by the caller and should be closed + * when no longer needed. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param alloc_type Allocation type (one of enum vrtd_alloc_type). + * @param alloc_dir QDMA direction (one of enum vrtd_alloc_dir). + * @param alloc_arg Allocation argument (HBM region index for HBM). + * @param size_in Requested size in bytes. + * @param buffer_out Output pointer to receive the allocated buffer handle. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p buffer_out must not be NULL. + * @note The returned buffer must be released with @c vrtd_buffer_destroy(). + */ +enum vrtd_ret vrtd_buffer_open( + int fd, + uint32_t dev, + uint32_t alloc_type, + uint32_t alloc_dir, + uint64_t alloc_arg, + uint64_t size_in, + struct vrtd_buffer **buffer_out +); + +/** + * @brief Open a raw buffer (QDMA qpair at caller-specified device address) via vrtd. + * + * Bypasses the allocator entirely — the caller is responsible for ensuring the + * address is valid and not in use. Requires the @c raw-mem-access permission. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param phys_addr Caller-specified device physical address. + * @param size Size in bytes. + * @param alloc_dir One of #vrtd_alloc_dir. + * @param buffer_out Output parameter set to the new buffer handle on success. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p buffer_out must not be NULL. + * @note The returned buffer must be released with @c vrtd_buffer_destroy(). + */ +enum vrtd_ret vrtd_buffer_open_raw( + int fd, + uint32_t dev, + uint64_t phys_addr, + uint64_t size, + uint32_t alloc_dir, + struct vrtd_buffer **buffer_out +); + +/** + * @brief Close a buffer (release allocation + QDMA qpair) via vrtd. + * + * On success or failure, the local buffer is destroyed and must not be used. + * + * @param buffer Buffer handle returned by @c vrtd_buffer_open(). + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p buffer must not be NULL. + */ +enum vrtd_ret vrtd_buffer_close( + struct vrtd_buffer *buffer +); + +/** + * @brief Perform a design writer transfer for a device. + * + * The input FD is sent to the daemon via SCM_RIGHTS. On success the daemon + * takes ownership of the FD and blocks until the transfer completes. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param input_fd Input file descriptor to read from. + * + * @return #VRTD_RET_OK on success; #VRTD_RET_BUSY if a transfer is in progress; + * otherwise a #vrtd_ret error code. + * @pre @p input_fd must be a valid, readable file descriptor. + */ +enum vrtd_ret vrtd_design_write( + int fd, + uint32_t dev, + int input_fd +); + +/** + * @brief Open a file and perform a design writer transfer for a device. + * + * Convenience helper that opens @p path read-only and passes the FD to the + * daemon via vrtd_design_write(). The FD is closed before returning. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param path Path to the input file to transfer. + * + * @return #VRTD_RET_OK on success; #VRTD_RET_BUSY if a transfer is in progress; + * otherwise a #vrtd_ret error code. + * @pre @p path must not be NULL. + */ +enum vrtd_ret vrtd_design_write_file( + int fd, + uint32_t dev, + const char *path +); + +/** + * @brief Perform a PCIe hotplug operation for a device. + * + * For board-level operations (RESCAN, RESET_SEQUENCE), @p function is ignored. + * For PF-level operations (REMOVE, TOGGLE_SBR, HOTPLUG), @p function selects + * the PCI physical function (0-7). + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0-based). + * @param op One of vrtd_device_hotplug_op. + * @param function PCI function number (0-7) for PF-level ops. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + */ +enum vrtd_ret vrtd_device_hotplug_op( + int fd, + uint32_t dev, + uint8_t op, + uint8_t function +); + +enum vrtd_ret vrtd_device_hotplug_rescan( + int fd, + uint32_t dev +); + +enum vrtd_ret vrtd_device_hotplug_remove( + int fd, + uint32_t dev, + uint8_t function +); + +enum vrtd_ret vrtd_device_hotplug_toggle_sbr( + int fd, + uint32_t dev, + uint8_t function +); + +enum vrtd_ret vrtd_device_hotplug_hotplug( + int fd, + uint32_t dev, + uint8_t function +); + +/** + * @brief Get the clock rate for a device region. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param region One of vrtd_clock_region. + * @param rate_hz_out Output pointer for the current rate in Hz. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p rate_hz_out must not be NULL. + */ +enum vrtd_ret vrtd_clock_get_rate( + int fd, + uint32_t dev, + uint32_t region, + uint32_t *rate_hz_out +); + +/** + * @brief Set the clock rate for a device region. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0‑based). + * @param region One of vrtd_clock_region. + * @param rate_hz_in Requested rate in Hz. + * @param rate_hz_out Output pointer for the achieved rate in Hz. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p rate_hz_out must not be NULL. + */ +enum vrtd_ret vrtd_clock_set_rate( + int fd, + uint32_t dev, + uint32_t region, + uint32_t rate_hz_in, + uint32_t *rate_hz_out +); + + +struct vrtd_buffer { + int sock_fd; + uint32_t dev; + + uint32_t alloc_type; + uint32_t alloc_dir; + uint64_t alloc_arg; + + uint64_t size; + uint64_t phys_addr; + int qpair_fd; + void *buf; +}; + +enum vrtd_ret vrtd_buffer_create_raw( + int sock_fd, + uint32_t dev, + uint32_t alloc_type, + uint32_t alloc_dir, + uint64_t alloc_arg, + uint64_t size, + uint64_t phys_addr, + int qpair_fd, + struct vrtd_buffer **buffer_out +); + +/** + * @brief Destroy a local buffer handle. + * + * This does not notify the daemon. Use @c vrtd_buffer_close() to release + * the server-side allocation. + */ +enum vrtd_ret vrtd_buffer_destroy( + struct vrtd_buffer *buffer +); + +enum vrtd_ret vrtd_buffer_sync_to_device( + struct vrtd_buffer *buffer, + uint64_t offset, + uint64_t size +); + +enum vrtd_ret vrtd_buffer_sync_from_device( + struct vrtd_buffer *buffer, + uint64_t offset, + uint64_t size +); + + +/** + * @brief Query sensor information for a device. + * + * Retrieves all sensor readings (temperature, power, voltage, current) for + * the specified device. The daemon queries sensors on-demand via AMI. + * + * The response is a variable-length message: a uint32_t sensor count + * followed by that many vrtd_sensor_entry structs. The caller provides + * a buffer large enough to hold the expected response. + * + * @param fd Connected vrtd socket file descriptor. + * @param dev Device index (0-based). + * @param entries_out Output buffer for sensor entries. + * @param max_entries Maximum number of entries @p entries_out can hold. + * @param num_entries_out Output pointer for the actual number of entries returned. + * + * @return #VRTD_RET_OK on success; otherwise a #vrtd_ret error code. + * @pre @p entries_out and @p num_entries_out must not be NULL. + */ +enum vrtd_ret vrtd_get_sensor_info( + int fd, + uint32_t dev, + struct vrtd_sensor_entry *entries_out, + uint32_t max_entries, + uint32_t *num_entries_out +); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // LIBVRTD_VRTD_H diff --git a/vrt/vrtd/libvrtd/src/CMakeLists.txt b/vrt/vrtd/libvrtd/src/CMakeLists.txt new file mode 100644 index 00000000..0ec9d005 --- /dev/null +++ b/vrt/vrtd/libvrtd/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_library( + libvrtd + + ${CMAKE_CURRENT_SOURCE_DIR}/buffer.c + ${CMAKE_CURRENT_SOURCE_DIR}/requests.c +) + +target_include_directories(libvrtd + PUBLIC + $ + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) + +# CMake prepends lib for libraries so libvrtd would be output as liblibvrtd otherwise +set_target_properties(libvrtd PROPERTIES OUTPUT_NAME vrtd VERSION ${PROJECT_VERSION} SOVERSION ${PROJECT_VERSION_MAJOR}) + +target_link_libraries(libvrtd + PUBLIC + slash::slash +) + +add_library(vrtd::libvrtd ALIAS libvrtd) diff --git a/vrt/vrtd/libvrtd/src/buffer.c b/vrt/vrtd/libvrtd/src/buffer.c new file mode 100644 index 00000000..b810de2c --- /dev/null +++ b/vrt/vrtd/libvrtd/src/buffer.c @@ -0,0 +1,261 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file buffer.c + * + * DMA buffer lifecycle management for the vrtd C client library. + * + * Buffers are host-side memory regions used for DMA transfers to/from + * the FPGA. Each buffer is backed by an anonymous mmap (preferring + * 2 MB hugepages for TLB efficiency, with automatic fallback to + * regular pages) and associated with a QDMA queue pair fd for + * performing the actual H2C / C2H transfers. + * + * Sync operations (sync_to_device / sync_from_device) transfer data + * between the host buffer and FPGA memory in TRANSFER_STEP_SIZE (4 KB) + * chunks using positional I/O on the QDMA qpair fd. + * + * Buffer lifecycle: + * 1. vrtd_buffer_open() -- daemon allocates, returns qpair fd + * 2. vrtd_buffer_create_raw() -- client mmaps host memory + * 3. vrtd_buffer_sync_to/from_device() -- DMA transfers + * 4. vrtd_buffer_close() -- tells daemon to free, unmaps locally + */ + +#define _GNU_SOURCE + +#include + +#include +#include +#include +#include +#include +#include + + +#include + +#ifndef MAP_HUGE_SHIFT +#define MAP_HUGE_SHIFT 26 +#endif + +#ifndef MAP_HUGE_2MB +#define MAP_HUGE_2MB (21UL << MAP_HUGE_SHIFT) +#endif + +#define TRANSFER_STEP_SIZE (4ULL * 1024ULL) // 4K + +enum vrtd_ret vrtd_buffer_create_raw( + int sock_fd, + uint32_t dev, + uint32_t alloc_type, + uint32_t alloc_dir, + uint64_t alloc_arg, + uint64_t size, + uint64_t phys_addr, + int qpair_fd, + struct vrtd_buffer **buffer_out +) { + if (buffer_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_buffer *buffer = (struct vrtd_buffer *) malloc(sizeof(struct vrtd_buffer)); + if (buffer == NULL) { + return VRTD_RET_INTERNAL_ERROR; + } + + buffer->buf = mmap( + NULL, /* address (let the kernel choose) */ + size, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB | MAP_HUGE_2MB | MAP_POPULATE, + -1, /* fd */ + 0 /* offset */ + ); + if (buffer->buf == MAP_FAILED) { + // Huge pages are an optimization, not a hard requirement. + // Fall back to normal anonymous mapping when hugepage mmap fails. + buffer->buf = mmap( + NULL, /* address (let the kernel choose) */ + size, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS | MAP_POPULATE, + -1, /* fd */ + 0 /* offset */ + ); + if (buffer->buf == MAP_FAILED) { + free(buffer); + return VRTD_RET_INTERNAL_ERROR; + } + } + + buffer->sock_fd = sock_fd; + buffer->dev = dev; + buffer->alloc_type = alloc_type; + buffer->alloc_dir = alloc_dir; + buffer->alloc_arg = alloc_arg; + buffer->size = size; + buffer->phys_addr = phys_addr; + buffer->qpair_fd = qpair_fd; + + *buffer_out = buffer; + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_buffer_destroy( + struct vrtd_buffer *buffer +) { + if (buffer == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + if (buffer->qpair_fd >= 0) { + (void) close(buffer->qpair_fd); + } + + if (buffer->buf != NULL) { + (void) munmap(buffer->buf, buffer->size); + } + + free(buffer); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_buffer_close( + struct vrtd_buffer *buffer +) +{ + if (buffer == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_buffer_close req = { + .dev_number = buffer->dev, + .phys_addr = buffer->phys_addr, + .size = buffer->size, + }; + struct vrtd_resp_buffer_close resp = {0}; + + enum vrtd_ret ret = vrtd_raw_request( + buffer->sock_fd, + VRTD_REQ_BUFFER_CLOSE, + &req, + sizeof(req), + &resp, + sizeof(resp), + NULL, + NULL + ); + + enum vrtd_ret destroy_ret = vrtd_buffer_destroy(buffer); + if (ret != VRTD_RET_OK) { + return ret; + } + return destroy_ret; +} + +enum vrtd_ret vrtd_buffer_sync_to_device( + struct vrtd_buffer *buffer, + uint64_t offset, + uint64_t size +) { + if (buffer == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + if (buffer->alloc_dir == VRTD_ALLOC_DIR_DEVICE_TO_HOST) { + return VRTD_RET_INVALID_ARGUMENT; + } + + assert(buffer->qpair_fd >= 0); + assert(buffer->buf != NULL); + assert(buffer->size % TRANSFER_STEP_SIZE == 0); + assert(buffer->phys_addr % TRANSFER_STEP_SIZE == 0); + + uint64_t effective_offset = offset - (offset % TRANSFER_STEP_SIZE); + uint64_t end_offset = offset + size; + + off_t ret = lseek(buffer->qpair_fd, buffer->phys_addr + effective_offset, SEEK_SET); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } + + for (uint64_t curr_offset = effective_offset; curr_offset < end_offset; curr_offset += TRANSFER_STEP_SIZE) { + ssize_t bytes_written = 0; + while (bytes_written < TRANSFER_STEP_SIZE) { + ssize_t bw = write(buffer->qpair_fd, + (uint8_t *) buffer->buf + curr_offset + bytes_written, + TRANSFER_STEP_SIZE - bytes_written); + if (bw == -1) { + return VRTD_RET_INTERNAL_ERROR; + } + bytes_written += bw; + } + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_buffer_sync_from_device( + struct vrtd_buffer *buffer, + uint64_t offset, + uint64_t size +) { + if (buffer == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + if (buffer->alloc_dir == VRTD_ALLOC_DIR_HOST_TO_DEVICE) { + return VRTD_RET_INVALID_ARGUMENT; + } + + assert(buffer->qpair_fd >= 0); + assert(buffer->buf != NULL); + assert(buffer->size % TRANSFER_STEP_SIZE == 0); + assert(buffer->phys_addr % TRANSFER_STEP_SIZE == 0); + + uint64_t effective_offset = offset - (offset % TRANSFER_STEP_SIZE); + uint64_t end_offset = offset + size; + + off_t ret = lseek(buffer->qpair_fd, buffer->phys_addr + effective_offset, SEEK_SET); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } + + for (uint64_t curr_offset = effective_offset; curr_offset < end_offset; curr_offset += TRANSFER_STEP_SIZE) { + ssize_t bytes_read = 0; + while (bytes_read < TRANSFER_STEP_SIZE) { + ssize_t br = read(buffer->qpair_fd, + (uint8_t *) buffer->buf + curr_offset + bytes_read, + TRANSFER_STEP_SIZE - bytes_read); + if (br == -1) { + return VRTD_RET_INTERNAL_ERROR; + } + bytes_read += br; + } + } + + return VRTD_RET_OK; +} diff --git a/vrt/vrtd/libvrtd/src/requests.c b/vrt/vrtd/libvrtd/src/requests.c new file mode 100644 index 00000000..b03c863a --- /dev/null +++ b/vrt/vrtd/libvrtd/src/requests.c @@ -0,0 +1,813 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file requests.c + * + * Wire protocol request/response marshalling for the vrtd C client library. + * + * Each public vrtd_*() function builds a wire protocol message (header + + * body), sends it to the daemon over the AF_UNIX SOCK_SEQPACKET socket, + * and receives the response. File descriptors (BAR fds, QDMA qpair fds) + * are passed out-of-band via SCM_RIGHTS ancillary data on the Unix socket. + * + * The protocol is strictly request-response: one sendmsg() followed by + * one recvmsg(). Sequence numbers are included for future pipelining + * but currently always set to 1. + * + * All functions are synchronous and thread-safe only if each thread uses + * its own connection fd (obtained from vrtd_connect()). + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/** + * vrtd_recv_response() - Receive a response message from the daemon. + * @fd: Connection socket. + * @resp_body_buf: Buffer for the response body (may be NULL if no body expected). + * @resp_bufsz: Size of @resp_body_buf. + * @resp_fd: If non-NULL, receives an out-of-band file descriptor + * sent by the daemon via SCM_RIGHTS (e.g. a BAR fd or + * QDMA qpair fd). Set to -1 if no fd was received. + * + * Uses recvmsg() with scatter-gather I/O: the header and body are read + * into separate buffers in a single system call. MSG_CMSG_CLOEXEC + * ensures any received fd is close-on-exec. + * + * Return: VRTD_RET_OK on success, or an error code. + */ +static enum vrtd_ret vrtd_recv_response( + int fd, + void *resp_body_buf, + size_t resp_bufsz, + int *resp_fd +) +{ + struct vrtd_resp_header rh = {0}; + + struct iovec riov[2]; + riov[0].iov_base = &rh; + riov[0].iov_len = sizeof(rh); + riov[1].iov_base = resp_body_buf; + riov[1].iov_len = resp_bufsz; + + char cbuf[CMSG_SPACE(sizeof(int))]; + struct msghdr rmsg = { + .msg_iov = riov, + .msg_iovlen = resp_bufsz ? 2 : 1, + .msg_control = resp_fd ? cbuf : NULL, + .msg_controllen = resp_fd ? sizeof(cbuf) : 0, + }; + + if (resp_fd) { + *resp_fd = -1; + } + + ssize_t rn = recvmsg(fd, &rmsg, MSG_CMSG_CLOEXEC); + if (rn == -1) { + return VRTD_RET_BAD_CONN; + } + + if (rmsg.msg_flags & MSG_TRUNC) { + return VRTD_RET_BAD_LIB_CALL; + } + if (rmsg.msg_flags & MSG_CTRUNC) { + return VRTD_RET_BAD_LIB_CALL; + } + + if ((size_t)rn < sizeof(rh)) { + return VRTD_RET_BAD_CONN; + } + + size_t expect = sizeof(rh) + rh.size; + if ((size_t) rn != expect) { + return VRTD_RET_BAD_CONN; + } + + /* Extract file descriptor from SCM_RIGHTS ancillary data, if any. */ + for (struct cmsghdr *c = CMSG_FIRSTHDR(&rmsg); c != NULL; c = CMSG_NXTHDR(&rmsg, c)) { + if (c->cmsg_level == SOL_SOCKET && c->cmsg_type == SCM_RIGHTS && c->cmsg_len >= CMSG_LEN(sizeof(int))) { + assert(resp_fd != NULL); + memcpy(resp_fd, CMSG_DATA(c), sizeof(int)); + break; + } + } + + return (enum vrtd_ret) rh.ret; +} + +int vrtd_connect(const char *path) +{ + if (path == NULL) { + errno = EINVAL; + return -1; + } + + int fd = socket(AF_UNIX, SOCK_SEQPACKET | SOCK_CLOEXEC, 0); + if (fd == -1) { + return -1; + } + + struct sockaddr_un sun = {0}; + sun.sun_family = AF_UNIX; + if (strlen(path) >= sizeof(sun.sun_path)) { + errno = ENAMETOOLONG; + close(fd); + return -1; + } + strcpy(sun.sun_path, path); + + int ret = connect(fd, (struct sockaddr *) &sun, sizeof(sun)); + if (ret == -1) { + close(fd); + return -1; + } + + return fd; +} + +/** + * vrtd_raw_request() - Send a request and receive the response. + * @fd: Connection socket (from vrtd_connect()). + * @opcode: Wire protocol opcode (VRTD_REQ_*). + * @req_body: Request body payload (may be NULL if @req_size is 0). + * @req_size: Size of @req_body in bytes. + * @resp_body_buf: Buffer for the response body. + * @resp_bufsz: Size of @resp_body_buf. + * @resp_fd: If non-NULL, receives an out-of-band fd from the daemon. + * @req_fd: If non-NULL and *req_fd >= 0, sends this fd to the daemon + * via SCM_RIGHTS (e.g. a bitstream fd for design_write). + * + * Builds a request message (header + body), optionally attaches an fd + * via SCM_RIGHTS ancillary data, sends it with sendmsg(), then waits + * for the response via vrtd_recv_response(). + * + * Return: VRTD_RET_OK on success, or an error code. + */ +enum vrtd_ret vrtd_raw_request( + int fd, + uint16_t opcode, + const void *req_body, uint16_t req_size, + void *resp_body_buf, size_t resp_bufsz, + int *resp_fd, + const int *req_fd +) +{ + if (req_size > VRTD_MSG_MAX_SIZE - sizeof(struct vrtd_req_header)) { errno = EMSGSIZE; return -1; } + + /* ---- Send ---- */ + struct vrtd_req_header h = { + .size = req_size, + .opcode= opcode, + .seqno = 1, + }; + + struct iovec siov[2]; + siov[0].iov_base = &h; + siov[0].iov_len = sizeof(h); + siov[1].iov_base = (void*) req_body; + siov[1].iov_len = req_size; + + char cbuf[CMSG_SPACE(sizeof(int))]; + struct msghdr smsg = { + .msg_iov = siov, + .msg_iovlen = req_size ? 2 : 1, + .msg_control = NULL, + .msg_controllen = 0, + }; + + if (req_fd && *req_fd >= 0) { + smsg.msg_control = cbuf; + smsg.msg_controllen = sizeof(cbuf); + + struct cmsghdr *cmsg = CMSG_FIRSTHDR(&smsg); + cmsg->cmsg_level = SOL_SOCKET; + cmsg->cmsg_type = SCM_RIGHTS; + cmsg->cmsg_len = CMSG_LEN(sizeof(int)); + memcpy(CMSG_DATA(cmsg), req_fd, sizeof(int)); + } + + ssize_t sn = sendmsg(fd, &smsg, MSG_NOSIGNAL); + if (sn == -1) { + return VRTD_RET_BAD_CONN; + } + if ((size_t) sn != sizeof(h) + req_size) { + return VRTD_RET_BAD_CONN; + } + + return vrtd_recv_response(fd, resp_body_buf, resp_bufsz, resp_fd); +} + + +enum vrtd_ret vrtd_get_num_devices(int fd, uint32_t *out) +{ + if (out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_resp_get_num_devices resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_NUM_DEVICES, + NULL, 0, + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *out = resp.num_devices; + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_device_info(int fd, uint32_t dev, struct vrtd_device_info *info_out) +{ + if (info_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_device_info req = { + .dev_number = dev, + }; + struct vrtd_resp_get_device_info resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_DEVICE_INFO, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + memcpy(info_out, &resp.info, sizeof(*info_out)); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_device_by_bdf(int fd, const char *bdf, uint32_t *dev_out) +{ + if (bdf == NULL || dev_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_device_by_bdf req = {0}; + strncpy(req.bdf, bdf, sizeof(req.bdf) - 1); + req.bdf[sizeof(req.bdf) - 1] = '\0'; + + struct vrtd_resp_get_device_by_bdf resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_DEVICE_BY_BDF, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *dev_out = resp.dev_number; + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_bar_info(int fd, uint32_t dev, uint8_t bar, struct slash_ioctl_bar_info *bar_info_out) +{ + if (bar_info_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_bar_info req = { + .dev_number = dev, + .bar_number = bar, + }; + struct vrtd_resp_get_bar_info resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_BAR_INFO, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + memcpy(bar_info_out, &resp.bar_info, sizeof(struct slash_ioctl_bar_info)); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_get_bar_fd(int fd, uint32_t dev, uint8_t bar, int *fd_out, uint64_t *len_out) +{ + if (fd_out == NULL || len_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_bar_fd req = { + .dev_number = dev, + .bar_number = bar, + }; + struct vrtd_resp_get_bar_fd resp = {0}; + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_BAR_FD, + &req, sizeof(req), + &resp, sizeof(resp), + fd_out, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *len_out = resp.len; + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_qdma_get_info(int fd, uint32_t dev, struct slash_qdma_info *info_out) +{ + if (info_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_qdma_get_info req = { + .dev_number = dev, + }; + struct vrtd_resp_qdma_get_info resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_GET_INFO, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + memcpy(info_out, &resp.info, sizeof(struct slash_qdma_info)); + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_qdma_qpair_add(int fd, uint32_t dev, struct slash_qdma_qpair_add *qpair_inout) +{ + if (qpair_inout == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_qdma_qpair_add req = { + .dev_number = dev, + .add = *qpair_inout, + }; + struct vrtd_resp_qdma_qpair_add resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_QPAIR_ADD, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *qpair_inout = resp.add; + + return VRTD_RET_OK; +} + +static enum vrtd_ret vrtd_qdma_qpair_op(int fd, uint32_t dev, uint32_t qid, uint32_t op) +{ + struct vrtd_req_qdma_qpair_op req = { + .dev_number = dev, + .qid = qid, + .op = op, + }; + struct vrtd_resp_qdma_qpair_op resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_QPAIR_OP, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_qdma_qpair_start(int fd, uint32_t dev, uint32_t qid) +{ + return vrtd_qdma_qpair_op(fd, dev, qid, SLASH_QDMA_QUEUE_OP_START); +} + +enum vrtd_ret vrtd_qdma_qpair_stop(int fd, uint32_t dev, uint32_t qid) +{ + return vrtd_qdma_qpair_op(fd, dev, qid, SLASH_QDMA_QUEUE_OP_STOP); +} + +enum vrtd_ret vrtd_qdma_qpair_del(int fd, uint32_t dev, uint32_t qid) +{ + return vrtd_qdma_qpair_op(fd, dev, qid, SLASH_QDMA_QUEUE_OP_DEL); +} + +enum vrtd_ret vrtd_qdma_qpair_get_fd( + int fd, + uint32_t dev, + uint32_t qid, + uint32_t flags, + int *fd_out +) +{ + if (fd_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_qdma_qpair_get_fd req = { + .dev_number = dev, + .qid = qid, + .flags = flags, + }; + struct vrtd_resp_qdma_qpair_get_fd resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_QDMA_QPAIR_GET_FD, + &req, sizeof(req), + &resp, sizeof(resp), + fd_out, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_buffer_open( + int fd, + uint32_t dev, + uint32_t alloc_type, + uint32_t alloc_dir, + uint64_t alloc_arg, + uint64_t size_in, + struct vrtd_buffer **buffer_out +) +{ + if (buffer_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + *buffer_out = NULL; + + struct vrtd_req_buffer_open req = { + .dev_number = dev, + .alloc_type = alloc_type, + .alloc_dir = alloc_dir, + .alloc_arg = alloc_arg, + .size = size_in, + }; + struct vrtd_resp_buffer_open resp = {0}; + + int qpair_fd = -1; + int ret = vrtd_raw_request(fd, VRTD_REQ_BUFFER_OPEN, + &req, sizeof(req), + &resp, sizeof(resp), + &qpair_fd, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + if (qpair_fd < 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + ret = vrtd_buffer_create_raw( + fd, + dev, + alloc_type, + alloc_dir, + alloc_arg, + resp.size, + resp.phys_addr, + qpair_fd, + buffer_out + ); + if (ret != VRTD_RET_OK) { + (void) close(qpair_fd); + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_buffer_open_raw( + int fd, + uint32_t dev, + uint64_t phys_addr, + uint64_t size, + uint32_t alloc_dir, + struct vrtd_buffer **buffer_out +) +{ + if (buffer_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + *buffer_out = NULL; + + struct vrtd_req_buffer_open_raw req = { + .dev_number = dev, + .alloc_dir = alloc_dir, + .phys_addr = phys_addr, + .size = size, + }; + struct vrtd_resp_buffer_open_raw resp = {0}; + + int qpair_fd = -1; + int ret = vrtd_raw_request(fd, VRTD_REQ_BUFFER_OPEN_RAW, + &req, sizeof(req), + &resp, sizeof(resp), + &qpair_fd, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + if (qpair_fd < 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + ret = vrtd_buffer_create_raw( + fd, + dev, + 0, /* alloc_type: not used for raw buffers */ + alloc_dir, + 0, /* alloc_arg: not used for raw buffers */ + size, + phys_addr, + qpair_fd, + buffer_out + ); + if (ret != VRTD_RET_OK) { + (void) close(qpair_fd); + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_design_write( + int fd, + uint32_t dev, + int input_fd +) +{ + if (input_fd < 0) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_design_write req = { + .dev_number = dev, + }; + struct vrtd_resp_design_write resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_DESIGN_WRITE, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, &input_fd); + if (ret != VRTD_RET_OK) { + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_design_write_file( + int fd, + uint32_t dev, + const char *path +) +{ + if (path == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + int input_fd = open(path, O_RDONLY | O_CLOEXEC); + if (input_fd < 0) { + return VRTD_RET_BAD_LIB_CALL; + } + + enum vrtd_ret ret = vrtd_design_write(fd, dev, input_fd); + (void) close(input_fd); + return ret; +} + +enum vrtd_ret vrtd_device_hotplug_op( + int fd, + uint32_t dev, + uint8_t op, + uint8_t function +) +{ + struct vrtd_req_device_hotplug_op req = { + .dev_number = dev, + .op = op, + .function = function, + }; + struct vrtd_resp_device_hotplug_op resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_DEVICE_HOTPLUG_OP, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_device_hotplug_rescan(int fd, uint32_t dev) +{ + return vrtd_device_hotplug_op(fd, dev, VRTD_DEVICE_HOTPLUG_OP_RESCAN, 0); +} + +enum vrtd_ret vrtd_device_hotplug_remove(int fd, uint32_t dev, uint8_t function) +{ + return vrtd_device_hotplug_op(fd, dev, VRTD_DEVICE_HOTPLUG_OP_REMOVE, function); +} + +enum vrtd_ret vrtd_device_hotplug_toggle_sbr(int fd, uint32_t dev, uint8_t function) +{ + return vrtd_device_hotplug_op(fd, dev, VRTD_DEVICE_HOTPLUG_OP_TOGGLE_SBR, function); +} + +enum vrtd_ret vrtd_device_hotplug_hotplug(int fd, uint32_t dev, uint8_t function) +{ + return vrtd_device_hotplug_op(fd, dev, VRTD_DEVICE_HOTPLUG_OP_HOTPLUG, function); +} + +enum vrtd_ret vrtd_clock_get_rate( + int fd, + uint32_t dev, + uint32_t region, + uint32_t *rate_hz_out +) +{ + if (rate_hz_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_clock_op req = { + .dev_number = dev, + .region = region, + .op = VRTD_CLOCK_OP_GET, + .rate_hz = 0, + }; + struct vrtd_resp_clock_op resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_CLOCK_OP, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *rate_hz_out = resp.rate_hz; + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_clock_set_rate( + int fd, + uint32_t dev, + uint32_t region, + uint32_t rate_hz_in, + uint32_t *rate_hz_out +) +{ + if (rate_hz_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_clock_op req = { + .dev_number = dev, + .region = region, + .op = VRTD_CLOCK_OP_SET, + .rate_hz = rate_hz_in, + }; + struct vrtd_resp_clock_op resp = {0}; + + int ret = vrtd_raw_request(fd, VRTD_REQ_CLOCK_OP, + &req, sizeof(req), + &resp, sizeof(resp), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + *rate_hz_out = resp.rate_hz; + return VRTD_RET_OK; +} + +enum vrtd_ret vrtd_open_bar_file( + int fd, + uint32_t dev, + uint8_t bar, + struct slash_bar_file *bar_file_out +) { + if (bar_file_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + int bar_fd = -1; + size_t len = 0; + enum vrtd_ret ret = vrtd_get_bar_fd(fd, dev,bar, &bar_file_out->fd, &bar_file_out->len); + if (ret != VRTD_RET_OK) { + return ret; + } + + bar_file_out->map = mmap(NULL, bar_file_out->len, PROT_READ | PROT_WRITE, MAP_SHARED, bar_file_out->fd, 0); + if (bar_file_out->map == MAP_FAILED) { + bar_file_out->map = NULL; + close(fd); + return VRTD_RET_INTERNAL_ERROR; + } + + return VRTD_RET_OK; +} + +void vrtd_close_bar_file(struct slash_bar_file *bar_file) +{ + if (bar_file == NULL) { + return; + } + + if (bar_file->map != NULL) { + munmap(bar_file->map, bar_file->len); + close(bar_file->fd); + + bar_file->map = NULL; + } +} + +enum vrtd_ret vrtd_get_sensor_info( + int fd, + uint32_t dev, + struct vrtd_sensor_entry *entries_out, + uint32_t max_entries, + uint32_t *num_entries_out +) +{ + if (entries_out == NULL || num_entries_out == NULL) { + return VRTD_RET_BAD_LIB_CALL; + } + + struct vrtd_req_get_sensor_info req = { + .dev_number = dev, + }; + + /* + * The response is variable-length: a uint32_t count followed by + * sensor entries. We receive into a stack buffer sized to the + * maximum the protocol can carry. + */ + uint8_t resp_buf[VRTD_MSG_MAX_SIZE - sizeof(struct vrtd_resp_header)]; + memset(resp_buf, 0, sizeof(resp_buf)); + + int ret = vrtd_raw_request(fd, VRTD_REQ_GET_SENSOR_INFO, + &req, sizeof(req), + resp_buf, sizeof(resp_buf), + NULL, NULL); + if (ret != VRTD_RET_OK) { + return ret; + } + + /* Parse the variable-length response. */ + struct vrtd_resp_get_sensor_info *resp = (struct vrtd_resp_get_sensor_info *)resp_buf; + uint32_t count = resp->num_sensors; + + if (count > max_entries) { + count = max_entries; + } + + memcpy(entries_out, resp->sensors, count * sizeof(struct vrtd_sensor_entry)); + *num_entries_out = count; + + return VRTD_RET_OK; +} diff --git a/vrt/vrtd/libvrtdpp/CMakeLists.txt b/vrt/vrtd/libvrtdpp/CMakeLists.txt new file mode 100644 index 00000000..734c1cbb --- /dev/null +++ b/vrt/vrtd/libvrtdpp/CMakeLists.txt @@ -0,0 +1,21 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +add_subdirectory(src) diff --git a/vrt/vrtd/libvrtdpp/doc/Doxyfile b/vrt/vrtd/libvrtdpp/doc/Doxyfile new file mode 100644 index 00000000..90ee066e --- /dev/null +++ b/vrt/vrtd/libvrtdpp/doc/Doxyfile @@ -0,0 +1,39 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# Doxyfile for libvrtdpp — generates XML for Sphinx/Breathe integration. + +PROJECT_NAME = "libvrtdpp" +PROJECT_BRIEF = "C++ client library for the V80 Runtime Daemon" + +OUTPUT_DIRECTORY = ./docs + +INPUT = ../include +RECURSIVE = YES +FILE_PATTERNS = *.hpp + +EXTRACT_ALL = YES +EXTRACT_STATIC = YES +OPTIMIZE_OUTPUT_FOR_C = NO + +GENERATE_HTML = NO +GENERATE_LATEX = NO +GENERATE_XML = YES +XML_OUTPUT = xml diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/bar.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/bar.hpp new file mode 100644 index 00000000..0a75845b --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/bar.hpp @@ -0,0 +1,117 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BAR_HPP +#define VRTD_BAR_HPP + +#include +#include +#include +#include + +#include + +namespace vrtd { + +/** + * @brief Value-type metadata handle for a device BAR (Base Address Register). + * + * Provides discovery information and a convenience method to open/map the BAR. + * + * @par Semantics + * - @c isUsable(): this BAR is currently accessible/mappable to the caller. + * - @c isInUse(): this BAR is leased by another tenant (currently always false). + * - @c getStartAddress(), @c getLength(): physical address and size in **bytes**. + * + * @par Lifetime + * A @c Bar becomes invalid if its originating @c Session is closed or moved. + * Any subsequent member call will throw. + * + * @par Thread safety + * Methods are thread-safe and may be called concurrently; they synchronize + * on the originating @c Session. + */ +class Bar { +public: + ~Bar() = default; + + Bar(const Bar&) = default; + Bar& operator=(const Bar&) = default; + Bar(Bar&&) noexcept = default; + Bar& operator=(Bar&&) noexcept = default; + + /** + * @brief Zero-based device index that owns this BAR. + */ + uint32_t getDeviceNum() const noexcept; + + /** + * @brief Zero-based BAR index on the device. + */ + uint8_t getNum() const noexcept; + + /** + * @brief Whether this BAR is currently usable (mappable) by the caller. + */ + bool isUsable() const noexcept; + + /** + * @brief Whether this BAR is currently in use by another tenant. + * + * @note In the current implementation this always returns false. + */ + bool isInUse() const noexcept; + + /** + * @brief Physical start address of the BAR. + */ + uint64_t getStartAddress() const noexcept; + + /** + * @brief Length/size of the BAR (bytes). + */ + uint64_t getLength() const noexcept; + + /** + * @brief Open and @c mmap() this BAR, returning an owning @c BarFile. + * + * @return @c BarFile that RAII-owns the FD and mapping; its destructor + * unmaps and closes automatically. + * @throws vrtd::Error on failure. + */ + BarFile openBarFile() const; +private: + // Only allow the Session class to generate this class + friend class Session; + Bar(uint32_t deviceNum, uint8_t num, bool usable, bool inUse, uint64_t startAddress, uint64_t length, std::function fOpenBarFile) noexcept; + + uint32_t deviceNum; + uint8_t num; + bool usable; + bool inUse; + uint64_t startAddress; + uint64_t length; + + std::function fOpenBarFile; +}; + +} // namespace vrtd + +#endif // VRTD_BAR_HPP \ No newline at end of file diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/bar_file.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file.hpp new file mode 100644 index 00000000..9d85cf1b --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file.hpp @@ -0,0 +1,200 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BAR_FILE_HPP +#define VRTD_BAR_FILE_HPP + +#include + +#include + +#include +#include + +namespace vrtd { + +/** + * @brief Owning RAII handle for a mapped BAR region. + * + * Encapsulates a @c slash_bar_file containing the BAR mapping (@c map) and + * length (@c len). Provides typed access via @c getPtr() which brackets + * memory access with the appropriate @c slash_bar_file_start_* / + * @c slash_bar_file_end_* calls. Direct raw access is available via + * @c getRawPtr(), but requires manual bracketing. + * + * @warning Not thread-safe. At most one memory operation (read or write) + * may be active at a time per @c BarFile instance. Concurrent + * calls to @c getPtr() / @c getRawPtr() on the same object are + * not allowed. + * + * @note Move-only; copying is disabled. The moved-from object is closed. + */ +class BarFile { +public: +/** + * @brief Destructor. + * + * Releases the mapping and FD if still open. + * + * @warning If a memory operation is still in progress (i.e., a live + * @c BarFilePtr returned by @c getPtr() has not been destroyed), + * the destructor may throw (e.g., to signal improper usage). + * Users must ensure all @c BarFilePtr instances are destroyed + * before destroying or closing the @c BarFile. + */ + ~BarFile(); + + BarFile(const BarFile&) = delete; + BarFile& operator=(const BarFile&) = delete; + + /** + * @brief Move constructor; transfers ownership and closes the source. + */ + BarFile(BarFile&&) noexcept; + + /** + * @brief Move assignment; closes current, then takes ownership. + */ + BarFile& operator=(BarFile&&) noexcept; + + /** + * @brief Size of the mapped BAR in bytes. + */ + size_t getLen() const noexcept; + + /** + * @brief Get a raw volatile pointer into the mapping. + * + * @param address Byte offset from the start of the mapping (default 0). + * @return @c volatile void* pointing at @p address inside the mapping. + * + * @warning Using the raw pointer requires the caller to manually bracket + * accesses with @c slash_bar_file_start_read() / @c _end_read() or + * @c slash_bar_file_start_write() / @c _end_write() as appropriate. + * Prefer @c getPtr() for RAII-safe access. + * + * @throws std::runtime_error if the file is closed or @p address is out of range. + */ + volatile void *getRawPtr(size_t address = 0) const noexcept; + + /** + * @brief Close the mapping and underlying FD. + * + * After a successful close, @c isClosed() returns true and further + * operations will throw. + * + * @warning Not idempotent/noexcept by design: if a memory operation is + * still in progress (i.e., a @c BarFilePtr is alive), this + * function may throw to signal misuse. + */ + void close(); + + /** + * @brief Whether the BAR has been closed. + */ + bool isClosed() const noexcept; + +private: + friend class Session; + explicit BarFile(slash_bar_file barFile) noexcept; + + slash_bar_file barFile; + + // Internal single-operation guards (non-thread-safe). + bool reading{}; + bool writing{}; + bool closed{}; + +public: + /** + * @brief Direction of an access session. + */ + enum class Direction { + Read, + Write, + }; + + /** + * @brief Acquire a typed RAII pointer into the BAR mapping. + * + * Starts a read or write session (depending on @p direction) and returns + * a move-only @c BarFilePtr that will automatically end the session on + * destruction. Only one operation (read or write) may be active at a time. + * + * @tparam T Element type. Must be an object type; recommended to be + * trivially copyable/standard-layout. Accesses are through + * @c volatile pointers to model device memory semantics. + * @param direction Whether this is a read or write operation. + * @param address Byte offset into the mapping where @c T is addressed. + * + * @return @c BarFilePtr owning the access session. + * + * @throws std::runtime_error if: + * - the file is closed, + * - @p address is out of range, + * - another read/write operation is already in progress, + * - @p direction is invalid. + * + * @warning The caller is responsible for alignment correctness. + */ + template + BarFilePtr getPtr(Direction direction, size_t address = 0) { + if (closed) { + throw std::runtime_error("Memory operation on closed bar file"); + } + + if (address >= barFile.len) { + throw std::runtime_error("Bad address"); + } + + if (reading || writing) { + throw std::runtime_error("Memory operation already in progress"); + } + + volatile uint8_t *p = static_cast(barFile.map); + volatile T *paddr = reinterpret_cast(&p[address]); + + std::function callback{}; + + if (direction == Direction::Read) { + slash_bar_file_start_read(&barFile); + reading = true; + callback = [&]{ + slash_bar_file_end_read(&barFile); + reading = false; + }; + } else if (direction == Direction::Write) { + slash_bar_file_start_write(&barFile); + writing = true; + callback = [&]{ + slash_bar_file_end_write(&barFile); + writing = false; + }; + } else { + throw std::runtime_error("Bad direction"); + } + + return BarFilePtr(paddr, callback); + } +}; + +} // namespace vrtd + +#endif // VRTD_BAR_FILE_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/bar_file_ptr.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file_ptr.hpp new file mode 100644 index 00000000..298292ca --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/bar_file_ptr.hpp @@ -0,0 +1,137 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BAR_FILE_PTR_HPP +#define VRTD_BAR_FILE_PTR_HPP + +#include +#include +#include +#include + +namespace vrtd { + +/** + * @brief Move-only RAII pointer for BAR memory access sessions. + * + * A @c BarFilePtr behaves like a @c volatile T* while it is alive and + * runs a stored callback when destroyed exactly once (used to end the + * read/write session started by @c BarFile::getPtr()). + * + * @tparam T Object type for element access (must satisfy @c std::is_object_v). + * + * @warning Not thread-safe. Intended to be short-lived and used on a + * single thread that owns the corresponding @c BarFile operation. + */ +template +class BarFilePtr { + static_assert(std::is_object_v, "T must be an object type"); +public: + using element_type = T; + using pointer = volatile T*; + using callback_t = std::function; + + /** + * @brief Construct from a raw volatile pointer and optional destructor callback. + * + * @param p Raw volatile pointer within the BAR mapping. + * @param cb Callback to run on destruction (e.g., to end a read/write session). + */ + explicit BarFilePtr(pointer p = nullptr, callback_t cb = {}) noexcept + : p_(p), cb_(std::move(cb)) {} + + // move-only (ensures callback runs at most once) + BarFilePtr(BarFilePtr&& other) noexcept + : p_(other.p_), cb_(std::move(other.cb_)) { + other.p_ = nullptr; + other.cb_ = nullptr; + } + BarFilePtr& operator=(BarFilePtr&& other) noexcept { + if (this != &other) { + run_callback(); + p_ = other.p_; + cb_ = std::move(other.cb_); + other.p_ = nullptr; + other.cb_ = nullptr; + } + return *this; + } + + BarFilePtr(const BarFilePtr&) = delete; + BarFilePtr& operator=(const BarFilePtr&) = delete; + + /** + * @brief Destructor; runs the callback at most once if present. + */ + ~BarFilePtr() { run_callback(); } + + // ---- implicit conversions (only these two) ---- + /** + * @brief Implicit conversion to volatile T*. + */ + operator pointer() const noexcept { return p_; } + /** + * @brief Implicit conversion to volatile void*. + */ + operator volatile void*() const noexcept { return p_; } + + // ---- pointer-like interface ---- + pointer get() const noexcept { return p_; } + volatile T& operator*() const noexcept { return *p_; } + pointer operator->() const noexcept { return p_; } + + // index (useful for arrays / pointer arithmetic) + volatile T& operator[](std::size_t i) const noexcept { return p_[i]; } + + /** + * @brief returns true if non-null. + */ + explicit operator bool() const noexcept { return p_ != nullptr; } + + // comparisons + friend bool operator==(const BarFilePtr& a, const BarFilePtr& b) noexcept { return a.p_ == b.p_; } + friend bool operator!=(const BarFilePtr& a, const BarFilePtr& b) noexcept { return !(a == b); } + friend bool operator==(const BarFilePtr& a, std::nullptr_t) noexcept { return a.p_ == nullptr; } + friend bool operator==(std::nullptr_t, const BarFilePtr& a) noexcept { return a.p_ == nullptr; } + friend bool operator!=(const BarFilePtr& a, std::nullptr_t) noexcept { return a.p_ != nullptr; } + friend bool operator!=(std::nullptr_t, const BarFilePtr& a) noexcept { return a.p_ != nullptr; } + + // optional: compare directly with a raw volatile T* + friend bool operator==(const BarFilePtr& a, pointer p) noexcept { return a.p_ == p; } + friend bool operator==(pointer p, const BarFilePtr& a) noexcept { return a.p_ == p; } + friend bool operator!=(const BarFilePtr& a, pointer p) noexcept { return a.p_ != p; } + friend bool operator!=(pointer p, const BarFilePtr& a) noexcept { return a.p_ != p; } + +private: + void run_callback() noexcept { + if (cb_) { + auto cb = std::move(cb_); + cb_ = nullptr; // ensure single fire + cb(); + } + } + + pointer p_ = nullptr; + callback_t cb_ = nullptr; +}; + +} // namsepace vrtd + +#endif // VRTD_BAR_FILE_PTR_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/buffer.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/buffer.hpp new file mode 100644 index 00000000..8748d379 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/buffer.hpp @@ -0,0 +1,177 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_BUFFER_HPP +#define VRTD_BUFFER_HPP + +#include +#include + +#include + +struct vrtd_buffer; + +namespace vrtd { + +/** + * @brief Allocation type for buffers. + */ +enum class BufferAllocType : uint32_t { + Ddr = VRTD_ALLOC_TYPE_DDR, + Hbm = VRTD_ALLOC_TYPE_HBM, + HbmVnoc = VRTD_ALLOC_TYPE_HBM_VNOC, +}; + +/** + * @brief Direction for QDMA transfers for a buffer. + */ +enum class BufferAllocDir : uint32_t { + Bidirectional = VRTD_ALLOC_DIR_BIDIRECTIONAL, + HostToDevice = VRTD_ALLOC_DIR_HOST_TO_DEVICE, + DeviceToHost = VRTD_ALLOC_DIR_DEVICE_TO_HOST, +}; + +/** + * @brief RAII wrapper for a vrtd buffer allocation. + * + * A @c Buffer owns the underlying @c vrtd_buffer, including its qpair FD and + * host-side staging buffer. Destruction closes the FD and releases the mapping. + * + * @note Move-only; copying is disabled. The moved-from object is closed. + */ +class Buffer { +public: + ~Buffer(); + + Buffer(const Buffer&) = delete; + Buffer& operator=(const Buffer&) = delete; + + Buffer(Buffer&& other) noexcept; + Buffer& operator=(Buffer&& other) noexcept; + + /** + * @brief Device index owning this buffer. + */ + uint32_t getDeviceNum() const noexcept; + + /** + * @brief Allocation type requested for this buffer. + */ + BufferAllocType getAllocType() const noexcept; + + /** + * @brief QDMA transfer direction for this buffer. + */ + BufferAllocDir getAllocDir() const noexcept; + + /** + * @brief Allocation argument (HBM region index for HBM allocations). + */ + uint64_t getAllocArg() const noexcept; + + /** + * @brief Allocated size in bytes (rounded to subregions). + */ + uint64_t getSize() const noexcept; + + /** + * @brief Physical device address for this allocation. + */ + uint64_t getPhysAddr() const noexcept; + + /** + * @brief Pointer to the host staging buffer. + */ + void *data() const noexcept; + + + /** + * @brief Pointer to the host staging buffer. + */ + void *data() noexcept; + + /** + * @brief Borrow the owned file descriptor without transferring ownership. + * + * @warning Do not close the returned FD directly unless you have called + * @c releaseFd(). Prefer @c close(). + */ + int getFd() const noexcept; + + /** + * @brief Release qpair FD ownership to the caller. + * + * The buffer remains valid, but will no longer close the FD on destruction. + */ + int releaseFd() noexcept; + + /** + * @brief Close and destroy the buffer via vrtd (idempotent). + * + * Releases the server-side allocation and local staging buffer. Errors + * are ignored to preserve noexcept semantics. + */ + void close() noexcept; + + /** + * @brief Whether the buffer has been closed or destroyed. + */ + bool isClosed() const noexcept; + + /** + * @brief Sync host buffer contents to the device. + * + * @throws vrtd::Error on error. + */ + void syncToDevice(uint64_t offset, uint64_t size); + + /** + * @brief Sync device contents into the host buffer. + * + * @throws vrtd::Error on error. + */ + void syncFromDevice(uint64_t offset, uint64_t size); + + /** + * @brief Obtain a std::fstream bound to this buffer FD. + * + * @param mode Standard iostream open mode (defaults to in|out|binary). + * @return A @c std::fstream owning its own FD. + * + * @throws std::runtime_error if the buffer is closed or the stream cannot be opened. + * + * @note Implementation is Linux-specific and relies on @c /proc/self/fd. + */ + std::fstream fstream( + std::ios_base::openmode mode = + std::ios_base::in | std::ios_base::out | std::ios_base::binary + ) const; + +private: + friend class Session; + + explicit Buffer(struct vrtd_buffer *buffer) noexcept; + + struct vrtd_buffer *buffer{nullptr}; +}; + +} // namespace vrtd + +#endif // VRTD_BUFFER_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/device.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/device.hpp new file mode 100644 index 00000000..8123a7f1 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/device.hpp @@ -0,0 +1,385 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_DEVICE_HPP +#define VRTD_DEVICE_HPP + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +namespace vrtd { + +enum class ClockRegion : uint32_t { + Service = VRTD_CLOCK_REGION_SERVICE, + User = VRTD_CLOCK_REGION_USER, +}; + +enum class HotplugOp : uint8_t { + Rescan = VRTD_DEVICE_HOTPLUG_OP_RESCAN, + Remove = VRTD_DEVICE_HOTPLUG_OP_REMOVE, + ToggleSbr = VRTD_DEVICE_HOTPLUG_OP_TOGGLE_SBR, + Hotplug = VRTD_DEVICE_HOTPLUG_OP_HOTPLUG, + ResetSequence = VRTD_DEVICE_HOTPLUG_OP_RESET_SEQUENCE, +}; + +/** + * @brief A single sensor reading returned by Device::getSensorInfo(). + */ +struct SensorEntry { + std::string name; ///< Sensor name (e.g., "vccint"). + uint8_t type; ///< Sensor type bitmask (1=temp, 2=current, 4=voltage, 8=power). + uint8_t status; ///< Sensor status code (0x01 = OK). + int8_t unitMod; ///< Unit modifier exponent (e.g., -3 for milli-). + int32_t value; ///< Sensor reading (apply 10^unitMod to get base unit value). +}; + +/** + * @brief Value-type handle describing a vrtd device. + * + * A @c Device carries its device number, name, and PCI metadata and routes operations back + * through its originating @c Session. + * + * @par Lifetime + * A @c Device becomes invalid if its originating @c Session is closed or moved. + * Any subsequent member call will throw. + * + * @par Thread safety + * Methods are thread-safe and may be called concurrently; they synchronize + * on the originating @c Session. + */ +class Device { +public: + ~Device() = default; + + Device(const Device&) = default; + Device& operator=(const Device&) = default; + Device(Device&&) noexcept = default; + Device& operator=(Device&&) noexcept = default; + + /** + * @brief Zero-based device index as seen by vrtd. + */ + uint32_t getNum() const noexcept; + + /** + * @brief Human-readable device name. + * + * Stable for the lifetime of the @c Device object. + */ + const std::string& getName() const noexcept; + + /** + * @brief PCI BDF string for this device. + */ + const std::string& getBdf() const noexcept; + + /** + * @brief PCI vendor ID. + */ + uint16_t getVendorId() const noexcept; + + /** + * @brief PCI device ID. + */ + uint16_t getDeviceId() const noexcept; + + /** + * @brief PCI subsystem vendor ID. + */ + uint16_t getSubsystemVendorId() const noexcept; + + /** + * @brief PCI subsystem device ID. + */ + uint16_t getSubsystemDeviceId() const noexcept; + + /** + * @brief Access a device BAR by index. + * + * @param num BAR index. + * @return Metadata handle for the requested BAR. + * @throws vrtd::Error on error (e.g., invalid index or unusable session). + * + * @par Notes + * The returned @c Bar becomes invalid if the originating @c Session is + * later closed or moved. + */ + Bar getBar(uint8_t num) const; + + /** + * @brief Create a QDMA qpair on this device. + * + * Returns an owning @c QdmaQpair that will automatically delete + * the qpair on destruction. + * + * @param cfg Qpair configuration parameters. The returned qpair + * exposes @c getQid(). + * @return An owning @c QdmaQpair. + * @throws vrtd::Error on error. + * + * @par Notes + * The returned @c QdmaQpair becomes invalid if the originating + * @c Session is later closed or moved. + */ + QdmaQpair createQdmaQpair(const struct slash_qdma_qpair_add& cfg) const; + + /** + * @brief Open a buffer (allocation + QDMA qpair) on this device. + * + * Returns an owning @c Buffer that closes the returned FD on destruction. + * + * @param allocType Allocation type for the buffer. + * @param size Requested size in bytes. + * @param allocArg Allocation argument (HBM region index for HBM). + * @param allocDir QDMA transfer direction. + * @return An owning @c Buffer. + * @throws vrtd::Error on error. + */ + Buffer openBuffer(BufferAllocType allocType, + uint64_t size, + uint64_t allocArg = 0, + BufferAllocDir allocDir = BufferAllocDir::Bidirectional) const; + + /** + * @brief Convenience helper for DDR allocations. + */ + Buffer openDdrBuffer(uint64_t size, BufferAllocDir allocDir = BufferAllocDir::Bidirectional) const { + return openBuffer(BufferAllocType::Ddr, size, 0, allocDir); + } + + /** + * @brief Convenience helper for HBM allocations (fixed region). + */ + Buffer openHbmBuffer(uint32_t region, + uint64_t size, + BufferAllocDir allocDir = BufferAllocDir::Bidirectional) const { + return openBuffer(BufferAllocType::Hbm, size, region, allocDir); + } + + /** + * @brief Convenience helper for HBM VNOC allocations. + */ + Buffer openHbmVnocBuffer(uint64_t size, + BufferAllocDir allocDir = BufferAllocDir::Bidirectional) const { + return openBuffer(BufferAllocType::HbmVnoc, size, 0, allocDir); + } + + /** + * @brief Open a raw buffer (QDMA qpair at caller-specified device address, bypasses allocator). + * + * Requires the @c raw-mem-access permission on this device. + * The caller is responsible for ensuring the address is valid and not in use. + * + * @param phys_addr Device physical address. + * @param size Size in bytes. + * @param allocDir QDMA transfer direction. + * @return An owning @c Buffer. + * @throws vrtd::Error on error. + */ + Buffer openRawBuffer(uint64_t phys_addr, + uint64_t size, + BufferAllocDir allocDir = BufferAllocDir::Bidirectional) const; + + /** + * @brief Perform a PCIe hotplug operation for this device. + * + * For board-level operations (Rescan, ResetSequence), @p function is ignored. + * For PF-level operations (Remove, ToggleSbr, Hotplug), @p function selects + * the PCI physical function (0-7). + * + * @param op One of HotplugOp. + * @param function PCI function number (0-7) for PF-level ops. + * @throws vrtd::Error on error. + */ + void hotplugOp(HotplugOp op, uint8_t function = 0) const; + + /** + * @brief Convenience helper for bus rescan. + */ + void hotplugRescan() const { + hotplugOp(HotplugOp::Rescan); + } + + /** + * @brief Convenience helper for remove. + * @param function PCI function number (0-7). Required. + */ + void hotplugRemove(uint8_t function) const { + hotplugOp(HotplugOp::Remove, function); + } + + /** + * @brief Convenience helper for SBR toggle. + * @param function PCI function number (0-7). Required. + */ + void hotplugToggleSbr(uint8_t function) const { + hotplugOp(HotplugOp::ToggleSbr, function); + } + + /** + * @brief Convenience helper for a remove+rescan hotplug cycle. + * @param function PCI function number (0-7). Required. + */ + void hotplug(uint8_t function) const { + hotplugOp(HotplugOp::Hotplug, function); + } + + /** + * @brief Perform a design writer transfer using an input file descriptor. + * + * The daemon takes ownership of the FD and blocks until the transfer completes. + * + * @throws vrtd::Error on error. + */ + void designWrite(int input_fd) const; + + /** + * @brief Perform a design writer transfer from a file path. + * + * Convenience helper that opens the path and passes the FD to the daemon. + * + * @throws vrtd::Error on error. + */ + void designWriteFile(std::string_view path) const; + + /** + * @brief Get the clock rate for a region. + * + * @param region Clock region. + * @return Current rate in Hz. + * @throws vrtd::Error on error. + */ + uint32_t getClockRate(ClockRegion region) const; + + // TODO: getClockRateMHz() + + /** + * @brief Set the clock rate for a region. + * + * @param region Clock region. + * @param rate_hz Requested rate in Hz. + * @return Achieved rate in Hz. + * @throws vrtd::Error on error. + */ + uint32_t setClockRate(ClockRegion region, uint32_t rate_hz) const; + + /** + * @brief Convenience helper for service region get. + * @see getClockRate + */ + uint32_t getServiceClockRate() const { + return getClockRate(ClockRegion::Service); + } + + /** + * @brief Convenience helper for service region set. + * @see setClockRate + */ + uint32_t setServiceClockRate(uint32_t rate_hz) const { + return setClockRate(ClockRegion::Service, rate_hz); + } + + /** + * @brief Convenience helper for user region get. + * @see getClockRate + */ + uint32_t getUserClockRate() const { + return getClockRate(ClockRegion::User); + } + + /** + * @brief Convenience helper for user region set. + * @see setClockRate + */ + uint32_t setUserClockRate(uint32_t rate_hz) const { + return setClockRate(ClockRegion::User, rate_hz); + } + + /** + * @brief Query all sensor readings for this device. + * + * Returns current values and statuses for all sensors (temperature, + * power, voltage, current) discovered via the AMI interface. + * + * @return Vector of sensor entries. + * @throws vrtd::Error on error. + */ + std::vector getSensorInfo() const; + + + // reconfigureUserRegion() + // reconfigureServiceRegion() + // setUserRegionFrequency() + // setServiceRegionFrequency() + + +private: + // Only allow the Session class to generate this class + friend class Session; + Device(uint32_t num, + std::string_view name, + std::string_view bdf, + uint16_t vendorId, + uint16_t deviceId, + uint16_t subsystemVendorId, + uint16_t subsystemDeviceId, + std::function fGetBar, + std::function fCreateQdmaQpair, + std::function fOpenBuffer, + std::function fOpenBufferRaw, + std::function fHotplugOp, + std::function fDesignWrite, + std::function fDesignWriteFile, + std::function fGetClockRate, + std::function fSetClockRate, + std::function(const Device&)> fGetSensorInfo); + + uint32_t num; + std::string name; + std::string bdf; + uint16_t vendorId = 0; + uint16_t deviceId = 0; + uint16_t subsystemVendorId = 0; + uint16_t subsystemDeviceId = 0; + + std::function fGetBar; + std::function fCreateQdmaQpair; + std::function fOpenBuffer; + std::function fOpenBufferRaw; + std::function fHotplugOp; + std::function fDesignWrite; + std::function fDesignWriteFile; + std::function fGetClockRate; + std::function fSetClockRate; + std::function(const Device&)> fGetSensorInfo; +}; + +} + +#endif // VRTD_DEVICE_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/error.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/error.hpp new file mode 100644 index 00000000..ff95217e --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/error.hpp @@ -0,0 +1,75 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_ERROR_H +#define VRTD_ERROR_H + +#include + +#include + +namespace vrtd { + +/** + * @brief Exception type for libvrtd/libvrtd++ operations. + * + * Wraps a @c vrtd_ret code and exposes a human-readable, static message via + * @c what(). Use @c getErrorCode() to branch on a specific error. + * + * @note Transport/socket issues in the C++ layer are mapped to + * @c VRTD_RET_BAD_CONN. + * @note The message returned by @c what() is a static string mapped from the + * code (e.g., "Authentication error") and does not allocate. + */ +class Error : public std::exception { +private: + vrtd_ret errorCode; + +public: + /** + * @brief Construct an Error with the given code. + * @param errorCode A value from @c vrtd_ret. + */ + explicit Error(vrtd_ret errorCode) noexcept; + + ~Error() = default; + + Error(const Error&) = default; + Error& operator=(const Error&) = default; + Error(Error&&) noexcept = default; + Error& operator=(Error&&) noexcept = default; + + /** + * @brief Retrieve the underlying error code. + */ + vrtd_ret getErrorCode() const noexcept; + + /** + * @brief Human-readable description corresponding to @c errorCode. + * + * @return Pointer to a static, null-terminated string. The storage is + * valid for the lifetime of the program. + */ + const char *what() const noexcept override; +}; + +} + +#endif //VRTD_ERROR_H diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/qdma_qpair.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/qdma_qpair.hpp new file mode 100644 index 00000000..713a6a16 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/qdma_qpair.hpp @@ -0,0 +1,125 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_QDMA_QPAIR_HPP +#define VRTD_QDMA_QPAIR_HPP + +#include +#include +#include +#include + +namespace vrtd { + +/** + * @brief RAII wrapper for a QDMA queue pair (qpair). + * + * A @c QdmaQpair owns a qpair created through a @c Session. It provides + * convenience methods to start/stop the qpair and to obtain a read/write + * file descriptor. On destruction, it requests deletion of the qpair. + * + * @warning A @c QdmaQpair becomes invalid if its originating @c Session + * is closed or moved; methods will throw in that case. The + * destructor never throws and will silently ignore errors when + * attempting to delete the qpair. + */ +class QdmaQpair { +public: + ~QdmaQpair(); + + QdmaQpair(const QdmaQpair&) = delete; + QdmaQpair& operator=(const QdmaQpair&) = delete; + + QdmaQpair(QdmaQpair&& other) noexcept; + QdmaQpair& operator=(QdmaQpair&& other) noexcept; + + /** + * @brief Device index owning this qpair. + */ + uint32_t getDeviceNum() const noexcept { return devNum; } + + /** + * @brief Qpair identifier as assigned by the kernel. + */ + uint32_t getQid() const noexcept { return qid; } + + /** + * @brief Start the qpair. + * + * @throws vrtd::Error on error. + */ + void start(); + + /** + * @brief Stop the qpair. + * + * @throws vrtd::Error on error. + */ + void stop(); + + /** + * @brief Obtain a read/write file descriptor for this qpair. + * + * @param flags OR of O_CLOEXEC and 0 (other flags may be rejected). + * @return New file descriptor owned by the caller. + * @throws vrtd::Error on error. + */ + int fd(uint32_t flags = O_CLOEXEC); + + /** + * @brief Obtain a std::fstream bound to this qpair. + * + * @param flags OR of O_CLOEXEC and 0 (other flags may be rejected). + * @param mode Standard iostream open mode (defaults to in|out|binary). + * @return A @c std::fstream owning a new file descriptor for this qpair. + * + * @throws vrtd::Error or std::runtime_error on error. + * + * @note Implementation is Linux-specific and relies on @c /proc/self/fd. + */ + std::fstream fstream( + uint32_t flags = O_CLOEXEC, + std::ios_base::openmode mode = + std::ios_base::in | std::ios_base::out | std::ios_base::binary + ); + +private: + friend class Session; + + QdmaQpair(uint32_t devNum, + uint32_t qid, + std::function fStart, + std::function fStop, + std::function fDelete, + std::function fOpenFd) noexcept; + + uint32_t devNum{}; + uint32_t qid{}; + bool owned{true}; + + std::function fStart; + std::function fStop; + std::function fDelete; + std::function fOpenFd; +}; + +} // namespace vrtd + +#endif // VRTD_QDMA_QPAIR_HPP diff --git a/vrt/vrtd/libvrtdpp/include/vrtd/session.hpp b/vrt/vrtd/libvrtdpp/include/vrtd/session.hpp new file mode 100644 index 00000000..e2dbbac2 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/include/vrtd/session.hpp @@ -0,0 +1,310 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_SESSION_HPP +#define VRTD_SESSION_HPP + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +namespace vrtd { + + +/** + * @brief Owning session/connection to the V Runtime Daemon (vrtd). + * + * A @c Session wraps a connected libvrtd socket and provides typed, exception-based + * access to devices and BARs. All public member functions are thread-safe; calls + * synchronize on an internal @c std::mutex. + * + * @par Exceptions + * Most member functions throw #vrtd::Error on failure. The destructor never throws. + * + * @par Lifetime and moves + * - The session is non-copyable and movable. + * - Moving a session leaves the moved-from object in the closed state + * (i.e., @c isClosed()==true and @c operator bool() == false). + * - **Important:** Any @c Device or @c Bar previously obtained from a session becomes + * invalid once that session is closed or moved; subsequent operations on those + * objects will throw. + */ +class Session { +public: + /** + * @brief Construct and connect to the vrtd socket. + * + * @param socket_path Filesystem path to the vrtd UNIX socket. + * Defaults to the standard path. + * @throws vrtd::Error if the connection cannot be established. + */ + explicit Session(const char *socket_path = VRTD_STANDARD_PATH); + + /** + * @brief Destructor; closes the session if still open. + */ + ~Session() noexcept; + + Session(const Session&) = delete; + Session& operator=(const Session&) = delete; + + /** + * @brief Move-construct a session. + * + * The moved-from session becomes closed. + * + * @param other The session to move from. + */ + Session(Session&& other) noexcept; + + /** + * @brief Move-assign a session. + * + * Closes any existing connection, then takes ownership from @p other. + * The moved-from session becomes closed. + * + * @param other The session to move from. + */ + Session& operator=(Session&& other) noexcept; + + /** + * @brief Number of devices visible via vrtd. + * @return Device count. + * @throws vrtd::Error on error. + * + * @par Thread safety + * Safe for concurrent calls across threads. + */ + uint32_t getNumDevices() const; + + /** + * @brief Retrieve a device handle by index. + * + * @param i Zero-based device index; must be less than @c getNumDevices(). + * @return A lightweight @c Device value referring back to this session. + * @throws vrtd::Error if @p i is out of range or if the session is not usable. + * + * @par Notes + * The returned @c Device becomes invalid if this session is later closed or moved. + */ + Device getDevice(size_t i) const; + + /** + * @brief Retrieve a device handle by PCI BDF string. + * + * @param bdf PCI BDF string (e.g., "0000:65:00.0"). + * @return A lightweight @c Device value referring back to this session. + * @throws vrtd::Error if the device cannot be found or if the session is not usable. + */ + Device getDeviceByBdf(std::string_view bdf) const; + + /** + * @brief Query QDMA capabilities for a device. + * + * @param device Device for which to query QDMA info. + * @return A copy of the QDMA capability struct as reported by the daemon. + * @throws vrtd::Error on error. + */ + struct slash_qdma_info getQdmaInfo(const Device& device) const; + + /** + * @brief Explicitly close the session. + * + * Idempotent. After closing, @c isClosed()==true and further operations + * on this session or on previously obtained @c Device/@c Bar objects will throw. + */ + void close() noexcept; + + /** + * @brief Whether the session is closed. + */ + bool isClosed() const noexcept; + + /** + * @brief Truthiness conversion. + * + * @return @c true if the session is open (not closed). + */ + explicit operator bool() const noexcept; +private: + int fd; + mutable std::unique_ptr m; + + /** + * @internal Obtains a BAR for @p device. Called via @c Device::getBar(). + */ + Bar getBar(const Device& device, uint8_t bar_number) const; + + /** + * @internal Opens and mmaps a BAR file. Called via @c Bar::openBarFile(). + */ + BarFile openBarFile(const Bar &bar) const; + + /** + * @internal Create a QDMA qpair on a device. + * + * Returns an owning @c QdmaQpair that will automatically delete + * the qpair on destruction. + * + * @param device Device on which to create the qpair. + * @param cfg Qpair configuration parameters. The returned qpair + * exposes @c getQid(). + * @return An owning @c QdmaQpair. + * @throws vrtd::Error on error. + */ + QdmaQpair createQdmaQpair( + const Device& device, + const struct slash_qdma_qpair_add& cfg + ) const; + + /** + * @internal Open a buffer (allocation + QDMA qpair). + * + * @param device Device on which to allocate. + * @param allocType Allocation type. + * @param size Requested size in bytes. + * @param allocArg Allocation argument (HBM region index for HBM). + * @param allocDir QDMA transfer direction. + * @return An owning @c Buffer. + * @throws vrtd::Error on error. + */ + Buffer openBuffer( + const Device& device, + BufferAllocType allocType, + uint64_t size, + uint64_t allocArg, + BufferAllocDir allocDir + ) const; + + /** + * @internal Open a raw buffer (QDMA qpair at caller-specified device address). + * + * @param device Device on which to create the qpair. + * @param phys_addr Caller-specified device physical address (bypasses allocator). + * @param size Size in bytes. + * @param allocDir QDMA transfer direction. + * @return An owning @c Buffer. + * @throws vrtd::Error on error. + */ + Buffer openBufferRaw( + const Device& device, + uint64_t phys_addr, + uint64_t size, + BufferAllocDir allocDir + ) const; + + /** + * @internal Perform a PCIe hotplug operation. + * + * For board-level operations (Rescan, ResetSequence), @p function is ignored. + * For PF-level operations (Remove, ToggleSbr, Hotplug), @p function selects + * the PCI physical function (0-7). + * + * @param device Device target. + * @param op One of vrtd::HotplugOp. + * @param function PCI function number (0-7) for PF-level ops. + * @throws vrtd::Error on error. + */ + void hotplugOp(const Device& device, HotplugOp op, + uint8_t function = 0) const; + + /** + * @internal Perform a design writer transfer using an input FD. + * + * @param device Device owning the design writer. + * @param input_fd Input file descriptor to transfer from. + * @throws vrtd::Error on error. + */ + void designWrite(const Device& device, int input_fd) const; + + /** + * @internal Perform a design writer transfer using a file path. + * + * @param device Device owning the design writer. + * @param path Input file path to transfer from. + * @throws vrtd::Error on error. + */ + void designWriteFile(const Device& device, std::string_view path) const; + + /** + * @internal Get clock rate for a region. + * + * @param device Device owning the clock. + * @param region One of vrtd_clock_region. + * @return Current rate in Hz. + * @throws vrtd::Error on error. + */ + uint32_t getClockRate(const Device& device, ClockRegion region) const; + + /** + * @internal Set clock rate for a region. + * + * @param device Device owning the clock. + * @param region One of vrtd_clock_region. + * @param rate_hz Requested rate in Hz. + * @return Achieved rate in Hz. + * @throws vrtd::Error on error. + */ + uint32_t setClockRate(const Device& device, ClockRegion region, uint32_t rate_hz) const; + + /** + * @internal Start, stop or delete an existing QDMA qpair. + * + * Convenience wrappers around the vrtd QDMA queue-op requests, used by + * @c QdmaQpair via the callbacks injected by @c createQdmaQpair(). + * + * @throws vrtd::Error on error. + */ + void startQdmaQpair(const Device& device, uint32_t qid) const; + void stopQdmaQpair (const Device& device, uint32_t qid) const; + void deleteQdmaQpair(const Device& device, uint32_t qid) const; + + /** + * @internal Obtain a read/write file descriptor for a QDMA qpair. + * + * @param device Device owning the qpair. + * @param qid Qpair identifier as returned by @c createQdmaQpair(). + * @param flags OR of O_CLOEXEC and 0 (other flags may be rejected). + * @return A new file descriptor referring to the qpair, owned by the caller. + * @throws vrtd::Error on error. + */ + int openQdmaQpairFd(const Device& device, uint32_t qid, uint32_t flags = 0) const; + + /** + * @internal Query sensor information for a device. + * + * @param device Device to query sensors for. + * @return Vector of sensor entries. + * @throws vrtd::Error on error. + */ + std::vector getSensorInfo(const Device& device) const; +}; + +} + +#endif // VRTD_SESSION_HPP diff --git a/examples/01_aximm/hls/build.tcl b/vrt/vrtd/libvrtdpp/src/CMakeLists.txt similarity index 53% rename from examples/01_aximm/hls/build.tcl rename to vrt/vrtd/libvrtdpp/src/CMakeLists.txt index 6b32d0a6..b777fade 100644 --- a/examples/01_aximm/hls/build.tcl +++ b/vrt/vrtd/libvrtdpp/src/CMakeLists.txt @@ -1,6 +1,6 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, @@ -18,61 +18,41 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -set command [lindex $argv 0] -set device [lindex $argv 1] -set ipname [lindex $argv 2] - -set do_sim 0 -set do_syn 0 -set do_export 0 -set do_cosim 0 - -switch $command { - "sim" { - set do_sim 1 - } - "syn" { - set do_syn 1 - } - "ip" { - set do_syn 1 - set do_export 1 - } - "cosim" { - set do_syn 1 - set do_cosim 1 - } - "all" { - set do_sim 1 - set do_syn 1 - set do_export 1 - set do_cosim 1 - } - default { - puts "Unrecognized command" - exit - } -} - - -open_project build_${ipname}.${device} -file copy -force $ipname.cpp build_${ipname}.${device}/$ipname.cpp -add_files $ipname.cpp -cflags "-std=c++14" - -set_top $ipname - -open_solution sol1 - -if {$do_syn} { - set_part $device - create_clock -period 4 -name default - config_interface -m_axi_addr64=true - csynth_design -} - -if {$do_export} { - config_export -format ip_catalog - export_design -} - -exit \ No newline at end of file +add_library( + libvrtdpp + + ${CMAKE_CURRENT_SOURCE_DIR}/buffer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/bar_file.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/bar.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/qdma_qpair.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/device.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/error.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/session.cpp +) + +target_include_directories(libvrtdpp + PUBLIC + $ + $ + $ + $ + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR} +) + +# CMake prepends lib for libraries so libvrtdpp would be output as liblibvrtdpp otherwise +set_target_properties(libvrtdpp PROPERTIES + OUTPUT_NAME vrtdpp + VERSION ${PROJECT_VERSION} + SOVERSION ${PROJECT_VERSION_MAJOR} +) + +set_target_properties(libvrtdpp PROPERTIES + CXX_STANDARD 20 + CXX_STANDARD_REQUIRED YES + CXX_EXTENSIONS YES +) + +target_link_libraries(libvrtdpp PUBLIC libvrtd) + +add_library(vrtd::libvrtdpp ALIAS libvrtdpp) diff --git a/vrt/vrtd/libvrtdpp/src/bar.cpp b/vrt/vrtd/libvrtdpp/src/bar.cpp new file mode 100644 index 00000000..39b2c66b --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/bar.cpp @@ -0,0 +1,75 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file bar.cpp + * + * Implementation of the vrtd::Bar C++ wrapper. + * + * Bar is a lightweight value-type that holds PCI BAR metadata (number, + * physical start address, length, usable/in-use flags) plus a callback + * for opening a memory-mapped BarFile. It is constructed by Session + * when the user queries device BARs and does not own any kernel + * resources itself. + */ + +#include + +namespace vrtd { + +Bar::Bar(uint32_t deviceNum, uint8_t num, bool usable, bool inUse, uint64_t startAddress, uint64_t length, std::function fOpenBarFile) noexcept { + this->deviceNum = deviceNum; + this->num = num; + this->usable = usable; + this->inUse = inUse; + this->startAddress = startAddress; + this->length = length; + this->fOpenBarFile = fOpenBarFile; +} + +uint32_t Bar::getDeviceNum() const noexcept { + return deviceNum; +} + +uint8_t Bar::getNum() const noexcept { + return num; +} + +bool Bar::isUsable() const noexcept { + return usable; +} + +bool Bar::isInUse() const noexcept { + return inUse; +} + +uint64_t Bar::getStartAddress() const noexcept { + return startAddress; +} + +uint64_t Bar::getLength() const noexcept { + return length; +} + +BarFile Bar::openBarFile() const { + return fOpenBarFile(*this); +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/bar_file.cpp b/vrt/vrtd/libvrtdpp/src/bar_file.cpp new file mode 100644 index 00000000..524191d3 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/bar_file.cpp @@ -0,0 +1,108 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file bar_file.cpp + * + * Implementation of the vrtd::BarFile C++ wrapper. + * + * BarFile provides RAII management of a memory-mapped PCI BAR region. + * It wraps a slash_bar_file (fd + mmap pointer + length) obtained from + * the daemon, and unmaps/closes on destruction. + * + * Move semantics are fully supported; copying is disabled. + */ + +#include + +#include +#include +#include + +#include + +namespace vrtd { + +BarFile::BarFile(slash_bar_file barFile) noexcept { + this->barFile = barFile; +} + +BarFile::~BarFile() { + close(); +} + +BarFile::BarFile(BarFile&& other) noexcept { + barFile = std::exchange(other.barFile, {}); + reading = std::exchange(other.reading, false); + writing = std::exchange(other.writing, false); + closed = std::exchange(other.closed, true); +} + +BarFile& BarFile::operator=(BarFile&& other) noexcept { + close(); + + barFile = std::exchange(other.barFile, {}); + reading = std::exchange(other.reading, false); + writing = std::exchange(other.writing, false); + closed = std::exchange(other.closed, true); + + return *this; +} + +void BarFile::close() { + if (closed) { + return; + } + + if (reading || writing) { + throw std::runtime_error("Bar file closed while in memory operation"); + } + + munmap(barFile.map, barFile.len); + ::close(barFile.fd); +} + +bool BarFile::isClosed() const noexcept { + return closed; +} + +size_t BarFile::getLen() const noexcept { + if (closed) { + return 0; + } + + return barFile.len; +} + +volatile void *BarFile::getRawPtr(size_t address) const noexcept { + if (closed) { + return nullptr; + } + + if (address >= barFile.len) { + return nullptr; + } + + volatile uint8_t *p = static_cast(barFile.map); + + return &p[address]; +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/buffer.cpp b/vrt/vrtd/libvrtdpp/src/buffer.cpp new file mode 100644 index 00000000..0c68ff22 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/buffer.cpp @@ -0,0 +1,198 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file buffer.cpp + * + * Implementation of the vrtd::Buffer C++ wrapper. + * + * Buffer provides RAII ownership of a @c vrtd_buffer obtained from the + * daemon via libvrtd. It wraps the host-side mmap, the QDMA queue pair + * fd, and the device-side physical address into a single movable object. + * + * Key features: + * - Move-only semantics (no copies); destruction calls vrtd_buffer_close(). + * - @c syncToDevice() / @c syncFromDevice() for DMA transfers. + * - @c fstream() opens a std::fstream on the qpair fd via + * @c /proc/self/fd/, allowing stream-style I/O on the DMA channel. + * - @c releaseFd() transfers qpair fd ownership to the caller. + */ + +#include +#include +#include + +#include +#include +#include + +namespace vrtd { + +Buffer::Buffer(struct vrtd_buffer *buffer) noexcept + : buffer(buffer) +{ +} + +Buffer::~Buffer() +{ + close(); +} + +Buffer::Buffer(Buffer&& other) noexcept + : buffer(other.buffer) +{ + other.buffer = nullptr; +} + +Buffer& Buffer::operator=(Buffer&& other) noexcept +{ + if (this == &other) { + return *this; + } + + close(); + + buffer = other.buffer; + other.buffer = nullptr; + + return *this; +} + +uint32_t Buffer::getDeviceNum() const noexcept +{ + return buffer ? buffer->dev : 0u; +} + +BufferAllocType Buffer::getAllocType() const noexcept +{ + if (buffer == nullptr) { + return BufferAllocType::Ddr; + } + return static_cast(buffer->alloc_type); +} + +BufferAllocDir Buffer::getAllocDir() const noexcept +{ + if (buffer == nullptr) { + return BufferAllocDir::Bidirectional; + } + return static_cast(buffer->alloc_dir); +} + +uint64_t Buffer::getAllocArg() const noexcept +{ + return buffer ? buffer->alloc_arg : 0u; +} + +uint64_t Buffer::getSize() const noexcept +{ + return buffer ? buffer->size : 0u; +} + +uint64_t Buffer::getPhysAddr() const noexcept +{ + return buffer ? buffer->phys_addr : 0u; +} + +void *Buffer::data() const noexcept +{ + return buffer ? buffer->buf : nullptr; +} + +void *Buffer::data() noexcept +{ + return buffer ? buffer->buf : nullptr; +} + +int Buffer::getFd() const noexcept +{ + return buffer ? buffer->qpair_fd : -1; +} + +int Buffer::releaseFd() noexcept +{ + if (buffer == nullptr) { + return -1; + } + int ret = buffer->qpair_fd; + buffer->qpair_fd = -1; + return ret; +} + +void Buffer::close() noexcept +{ + if (buffer != nullptr) { + (void) vrtd_buffer_close(buffer); + buffer = nullptr; + } +} + +bool Buffer::isClosed() const noexcept +{ + return buffer == nullptr; +} + +std::fstream Buffer::fstream(std::ios_base::openmode mode) const +{ + if (isClosed()) { + throw std::runtime_error("Buffer is closed"); + } + + int fd = getFd(); + if (fd < 0) { + throw std::runtime_error("Buffer FD is invalid"); + } + + std::string path = "/proc/self/fd/" + std::to_string(fd); + + std::fstream stream; + stream.open(path, mode); + if (!stream.is_open()) { + throw std::runtime_error("Failed to open fstream for buffer"); + } + + return stream; +} + +void Buffer::syncToDevice(uint64_t offset, uint64_t size) +{ + if (buffer == nullptr) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + + enum vrtd_ret ret = vrtd_buffer_sync_to_device(buffer, offset, size); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Buffer::syncFromDevice(uint64_t offset, uint64_t size) +{ + if (buffer == nullptr) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + + enum vrtd_ret ret = vrtd_buffer_sync_from_device(buffer, offset, size); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +} // namespace vrtd diff --git a/vrt/vrtd/libvrtdpp/src/device.cpp b/vrt/vrtd/libvrtdpp/src/device.cpp new file mode 100644 index 00000000..f45cda24 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/device.cpp @@ -0,0 +1,134 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +namespace vrtd { + +Device::Device(uint32_t num, + std::string_view name, + std::string_view bdf, + uint16_t vendorId, + uint16_t deviceId, + uint16_t subsystemVendorId, + uint16_t subsystemDeviceId, + std::function fGetBar, + std::function fCreateQdmaQpair, + std::function fOpenBuffer, + std::function fOpenBufferRaw, + std::function fHotplugOp, + std::function fDesignWrite, + std::function fDesignWriteFile, + std::function fGetClockRate, + std::function fSetClockRate, + std::function(const Device&)> fGetSensorInfo) { + this->num = num; + this->name = name; + this->bdf = bdf; + this->vendorId = vendorId; + this->deviceId = deviceId; + this->subsystemVendorId = subsystemVendorId; + this->subsystemDeviceId = subsystemDeviceId; + this->fGetBar = fGetBar; + this->fCreateQdmaQpair = fCreateQdmaQpair; + this->fOpenBuffer = fOpenBuffer; + this->fOpenBufferRaw = fOpenBufferRaw; + this->fHotplugOp = fHotplugOp; + this->fDesignWrite = fDesignWrite; + this->fDesignWriteFile = fDesignWriteFile; + this->fGetClockRate = fGetClockRate; + this->fSetClockRate = fSetClockRate; + this->fGetSensorInfo = fGetSensorInfo; +} + +uint32_t Device::getNum() const noexcept { + return num; +} + +const std::string& Device::getName() const noexcept { + return name; +} + +const std::string& Device::getBdf() const noexcept { + return bdf; +} + +uint16_t Device::getVendorId() const noexcept { + return vendorId; +} + +uint16_t Device::getDeviceId() const noexcept { + return deviceId; +} + +uint16_t Device::getSubsystemVendorId() const noexcept { + return subsystemVendorId; +} + +uint16_t Device::getSubsystemDeviceId() const noexcept { + return subsystemDeviceId; +} + +Bar Device::getBar(uint8_t num) const { + return fGetBar(*this, num); +} + +QdmaQpair Device::createQdmaQpair(const struct slash_qdma_qpair_add& cfg) const { + return fCreateQdmaQpair(*this, cfg); +} + +Buffer Device::openBuffer(BufferAllocType allocType, + uint64_t size, + uint64_t allocArg, + BufferAllocDir allocDir) const { + return fOpenBuffer(*this, allocType, size, allocArg, allocDir); +} + +Buffer Device::openRawBuffer(uint64_t phys_addr, + uint64_t size, + BufferAllocDir allocDir) const { + return fOpenBufferRaw(*this, phys_addr, size, allocDir); +} + +void Device::hotplugOp(HotplugOp op, uint8_t function) const { + fHotplugOp(*this, op, function); +} + +void Device::designWrite(int input_fd) const { + fDesignWrite(*this, input_fd); +} + +void Device::designWriteFile(std::string_view path) const { + fDesignWriteFile(*this, path); +} + +uint32_t Device::getClockRate(ClockRegion region) const { + return fGetClockRate(*this, region); +} + +uint32_t Device::setClockRate(ClockRegion region, uint32_t rate_hz) const { + return fSetClockRate(*this, region, rate_hz); +} + +std::vector Device::getSensorInfo() const { + return fGetSensorInfo(*this); +} + +} diff --git a/smi/include/commands/list_command.hpp b/vrt/vrtd/libvrtdpp/src/error.cpp similarity index 51% rename from smi/include/commands/list_command.hpp rename to vrt/vrtd/libvrtdpp/src/error.cpp index 5f54dd91..a63ff729 100644 --- a/smi/include/commands/list_command.hpp +++ b/vrt/vrtd/libvrtdpp/src/error.cpp @@ -18,46 +18,54 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef LIST_COMMAND_HPP -#define LIST_COMMAND_HPP - -#include - /** - * @brief Class for listing available V80 devices. + * @file error.cpp * - * The ListCommand class provides functionality to list available devices - * that match the specified vendor and device IDs. + * Implementation of the vrtd::Error exception class. + * + * Error wraps a @c vrtd_ret error code (from the C wire protocol) into + * a C++ @c std::exception. The @c what() override translates the + * numeric code into a human-readable string for diagnostics. */ -class ListCommand { - public: - /** - * @brief Constructor for ListCommand. - * - * @param vendorId The vendor ID to filter devices by. - * @param deviceId The device ID to filter devices by. - */ - ListCommand(uint16_t vendorId, uint16_t deviceId); - - /** - * @brief Executes the list command. - * - * This method lists all available devices that match the specified - * vendor and device IDs. - */ - void execute() const; - - private: - uint16_t vendorId; ///< The vendor ID to filter devices by. - uint16_t deviceId; ///< The device ID to filter devices by. - - /** - * @brief Lists all matching devices. - * - * This method performs the actual listing of devices that match the - * specified vendor and device IDs. - */ - void listDevices() const; -}; - -#endif // LIST_COMMAND_HPP \ No newline at end of file + +#include + +namespace vrtd { + +Error::Error(vrtd_ret errorCode) noexcept { + this->errorCode = errorCode; +} + +vrtd_ret Error::getErrorCode() const noexcept { + return errorCode; +} + +const char *Error::what() const noexcept { + switch (errorCode) { + case VRTD_RET_BAD_LIB_CALL: + return "Bad library call"; + + case VRTD_RET_BAD_CONN: + return "Bad connection to daemon"; + + case VRTD_RET_BAD_REQUEST: + return "Bad request"; + + case VRTD_RET_INVALID_ARGUMENT: + return "Invalid argument"; + + case VRTD_RET_NOEXIST: + return "Requested resouce doesn't exist"; + + case VRTD_RET_INTERNAL_ERROR: + return "Internal error in vrtd daemon or local libvrtd"; + + case VRTD_RET_AUTH_ERROR: + return "Missing permission"; + + default: + return "Unknown error"; + } +} + +} diff --git a/vrt/vrtd/libvrtdpp/src/qdma_qpair.cpp b/vrt/vrtd/libvrtdpp/src/qdma_qpair.cpp new file mode 100644 index 00000000..12ef5828 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/qdma_qpair.cpp @@ -0,0 +1,168 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file qdma_qpair.cpp + * + * Implementation of the vrtd::QdmaQpair C++ wrapper. + * + * QdmaQpair manages the lifecycle of a QDMA queue pair obtained from + * the vrtd daemon. It uses the **callback injection** pattern: the + * Session that creates the QdmaQpair provides start/stop/delete/openFd + * callbacks that issue the appropriate wire protocol requests. This + * keeps QdmaQpair decoupled from Session while still enabling RAII + * cleanup (stop + delete on destruction). + */ + +#include + +#include +#include +#include +#include + +namespace vrtd { + +QdmaQpair::QdmaQpair(uint32_t devNum, + uint32_t qid, + std::function fStart, + std::function fStop, + std::function fDelete, + std::function fOpenFd) noexcept + : devNum(devNum) + , qid(qid) + , owned(true) + , fStart(std::move(fStart)) + , fStop(std::move(fStop)) + , fDelete(std::move(fDelete)) + , fOpenFd(std::move(fOpenFd)) +{ +} + +QdmaQpair::~QdmaQpair() +{ + if (!owned) { + return; + } + + if (!fDelete || qid == 0) { + return; + } + + try { + fDelete(*this); + } catch (...) { + // Destructors must not throw; ignore errors on best-effort delete. + } +} + +QdmaQpair::QdmaQpair(QdmaQpair&& other) noexcept + : devNum(other.devNum) + , qid(other.qid) + , owned(other.owned) + , fStart(std::move(other.fStart)) + , fStop(std::move(other.fStop)) + , fDelete(std::move(other.fDelete)) + , fOpenFd(std::move(other.fOpenFd)) +{ + other.owned = false; + other.qid = 0; +} + +QdmaQpair& QdmaQpair::operator=(QdmaQpair&& other) noexcept +{ + if (this == &other) { + return *this; + } + + // Drop current ownership (best-effort delete in destructor semantics) + if (owned && fDelete && qid != 0) { + try { + fDelete(*this); + } catch (...) { + // ignore + } + } + + devNum = other.devNum; + qid = other.qid; + owned = other.owned; + fStart = std::move(other.fStart); + fStop = std::move(other.fStop); + fDelete= std::move(other.fDelete); + fOpenFd= std::move(other.fOpenFd); + + other.owned = false; + other.qid = 0; + + return *this; +} + +void QdmaQpair::start() +{ + if (!fStart) { + throw std::runtime_error("QDMA qpair start not available"); + } + + fStart(*this); +} + +void QdmaQpair::stop() +{ + if (!fStop) { + throw std::runtime_error("QDMA qpair stop not available"); + } + + fStop(*this); +} + +int QdmaQpair::fd(uint32_t flags) +{ + if (!fOpenFd) { + throw std::runtime_error("QDMA qpair fd() not available"); + } + + return fOpenFd(*this, flags); +} + +std::fstream QdmaQpair::fstream(uint32_t flags, std::ios_base::openmode mode) +{ + int qfd = fd(flags); + + try { + std::string path = "/proc/self/fd/" + std::to_string(qfd); + + std::fstream stream; + stream.open(path, mode); + + ::close(qfd); + + if (!stream.is_open()) { + throw std::runtime_error("Failed to open fstream for QDMA qpair"); + } + + return stream; + } catch (...) { + ::close(qfd); + throw; + } +} + +} // namespace vrtd diff --git a/vrt/vrtd/libvrtdpp/src/session.cpp b/vrt/vrtd/libvrtdpp/src/session.cpp new file mode 100644 index 00000000..d2e69fd9 --- /dev/null +++ b/vrt/vrtd/libvrtdpp/src/session.cpp @@ -0,0 +1,519 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file session.cpp + * + * Implementation of the vrtd::Session C++ wrapper. + * + * Session manages a single AF_UNIX connection to the vrtd daemon, + * providing thread-safe request dispatch (via an internal mutex) and + * RAII resource management. + * + * The key design pattern is **callback injection**: when creating QDMA + * queue pairs or other resources, Session passes lambdas that capture + * the session fd. This allows resource objects (QdmaQpair, etc.) to + * issue their own cleanup requests to the daemon when destroyed, + * without holding a direct reference to the Session. + */ + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#include "vrtd/wire.h" +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +namespace vrtd { + +Session::Session(const char *socketPath) +: m(std::make_unique()) { + fd = vrtd_connect(socketPath); + + if (fd == -1) { + throw std::runtime_error(std::string("Failed to open socket ") + strerrordesc_np(errno)); + } +} + +Session::~Session() noexcept +{ + close(); +} + +Session::Session(Session&& other) noexcept +{ + if (!other.isClosed()) { + std::lock_guard lk(*other.m); + + fd = std::exchange(other.fd, -1); + m = std::exchange(other.m, nullptr); + } else { + fd = -1; + m = nullptr; + } +} + +Session& Session::operator=(Session&& other) noexcept +{ + close(); + + if (!other.isClosed()) { + std::lock_guard lk(*other.m); + + fd = std::exchange(other.fd, -1); + m = std::exchange(other.m, nullptr); + } + + return *this; +} + +uint32_t Session::getNumDevices() const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + uint32_t numDevices; + + auto ret = vrtd_get_num_devices(fd, &numDevices); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return numDevices; +} + +Device Session::getDevice(size_t i) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + vrtd_device_info info = {}; + + auto ret = vrtd_get_device_info(fd, i, &info); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return Device( + i, + {info.name, strnlen(info.name, sizeof(info.name))}, + {info.pci.bdf, strnlen(info.pci.bdf, sizeof(info.pci.bdf))}, + info.pci.vendor_id, + info.pci.device_id, + info.pci.subsystem_vendor_id, + info.pci.subsystem_device_id, + [&](const Device& device, uint8_t num) { return getBar(device, num); }, + [&](const Device& device, const slash_qdma_qpair_add& cfg) { return createQdmaQpair(device, cfg); }, + [&](const Device& device, BufferAllocType type, uint64_t size, uint64_t arg, BufferAllocDir dir) { + return openBuffer(device, type, size, arg, dir); + }, + [&](const Device& device, uint64_t phys_addr, uint64_t size, BufferAllocDir dir) { + return openBufferRaw(device, phys_addr, size, dir); + }, + [&](const Device& device, HotplugOp op, uint8_t function) { return hotplugOp(device, op, function); }, + [&](const Device& device, int input_fd) { return designWrite(device, input_fd); }, + [&](const Device& device, std::string_view path) { return designWriteFile(device, path); }, + [&](const Device& device, ClockRegion region) { return getClockRate(device, region); }, + [&](const Device& device, ClockRegion region, uint32_t rate_hz) { return setClockRate(device, region, rate_hz); }, + [&](const Device& device) { return getSensorInfo(device); } + ); +} + +Device Session::getDeviceByBdf(std::string_view bdf) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + // Normalize to board-level BDF (DDDD:BB:DD) to match how the daemon + // stores devices. Strip function digit if present, and prepend domain + // 0000: if only one colon (short BDF like "03:00"). + std::string bdf_str(bdf); + + // Strip function digit (.F) + auto dot = bdf_str.rfind('.'); + if (dot != std::string::npos) { + std::cerr << "Warning: BDF '" << bdf + << "' contains a PF function number; " + << "stripping " << bdf_str.substr(dot) + << " — use board address (e.g. " + << bdf_str.substr(0, dot) << ") instead" + << std::endl; + bdf_str = bdf_str.substr(0, dot); + } + + // Prepend default domain if missing + if (bdf_str.find(':') == bdf_str.rfind(':')) { + bdf_str = "0000:" + bdf_str; + } + + uint32_t dev_num = 0; + auto ret = vrtd_get_device_by_bdf(fd, bdf_str.c_str(), &dev_num); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + vrtd_device_info info = {}; + ret = vrtd_get_device_info(fd, dev_num, &info); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return Device( + dev_num, + {info.name, strnlen(info.name, sizeof(info.name))}, + {info.pci.bdf, strnlen(info.pci.bdf, sizeof(info.pci.bdf))}, + info.pci.vendor_id, + info.pci.device_id, + info.pci.subsystem_vendor_id, + info.pci.subsystem_device_id, + [&](const Device& device, uint8_t num) { return getBar(device, num); }, + [&](const Device& device, const slash_qdma_qpair_add& cfg) { return createQdmaQpair(device, cfg); }, + [&](const Device& device, BufferAllocType type, uint64_t size, uint64_t arg, BufferAllocDir dir) { + return openBuffer(device, type, size, arg, dir); + }, + [&](const Device& device, uint64_t phys_addr, uint64_t size, BufferAllocDir dir) { + return openBufferRaw(device, phys_addr, size, dir); + }, + [&](const Device& device, HotplugOp op, uint8_t function) { return hotplugOp(device, op, function); }, + [&](const Device& device, int input_fd) { return designWrite(device, input_fd); }, + [&](const Device& device, std::string_view path) { return designWriteFile(device, path); }, + [&](const Device& device, ClockRegion region) { return getClockRate(device, region); }, + [&](const Device& device, ClockRegion region, uint32_t rate_hz) { return setClockRate(device, region, rate_hz); }, + [&](const Device& device) { return getSensorInfo(device); } + ); +} + +Bar Session::getBar(const Device& device, uint8_t num) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_ioctl_bar_info barInfo; + + auto ret = vrtd_get_bar_info(fd, device.getNum(), num, &barInfo); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return Bar(device.getNum(), num, barInfo.usable, barInfo.in_use, barInfo.start_address, barInfo.length, [&](const Bar&bar) { return openBarFile(bar); } ); +} + +BarFile Session::openBarFile(const Bar& bar) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_bar_file barFile; + + auto ret = vrtd_open_bar_file(fd, bar.getDeviceNum(), bar.getNum(), &barFile); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return BarFile(barFile); +} + +slash_qdma_info Session::getQdmaInfo(const Device& device) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_qdma_info info; + auto ret = vrtd_qdma_get_info(fd, device.getNum(), &info); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return info; +} + +QdmaQpair Session::createQdmaQpair( + const Device& device, + const slash_qdma_qpair_add& cfg +) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + slash_qdma_qpair_add tmp = cfg; + auto ret = vrtd_qdma_qpair_add(fd, device.getNum(), &tmp); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return QdmaQpair( + device.getNum(), + tmp.qid, + [this, device](const QdmaQpair& qp) { startQdmaQpair(device, qp.getQid()); }, + [this, device](const QdmaQpair& qp) { stopQdmaQpair(device, qp.getQid()); }, + [this, device](const QdmaQpair& qp) { deleteQdmaQpair(device, qp.getQid()); }, + [this, device](const QdmaQpair& qp, uint32_t flags) { return openQdmaQpairFd(device, qp.getQid(), flags); } + ); +} + +Buffer Session::openBuffer( + const Device& device, + BufferAllocType allocType, + uint64_t size, + uint64_t allocArg, + BufferAllocDir allocDir +) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + struct vrtd_buffer *raw = nullptr; + auto ret = vrtd_buffer_open( + fd, + device.getNum(), + static_cast(allocType), + static_cast(allocDir), + allocArg, + size, + &raw + ); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + if (raw == nullptr) { + throw Error(VRTD_RET_INTERNAL_ERROR); + } + + return Buffer(raw); +} + +Buffer Session::openBufferRaw( + const Device& device, + uint64_t phys_addr, + uint64_t size, + BufferAllocDir allocDir +) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + struct vrtd_buffer *raw = nullptr; + auto ret = vrtd_buffer_open_raw( + fd, + device.getNum(), + phys_addr, + size, + static_cast(allocDir), + &raw + ); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + if (raw == nullptr) { + throw Error(VRTD_RET_INTERNAL_ERROR); + } + + return Buffer(raw); +} + +void Session::hotplugOp(const Device& device, HotplugOp op, + uint8_t function) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_device_hotplug_op(fd, device.getNum(), + static_cast(op), function); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Session::designWrite(const Device& device, int input_fd) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_design_write(fd, device.getNum(), input_fd); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Session::designWriteFile(const Device& device, std::string_view path) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + std::string path_str(path); + auto ret = vrtd_design_write_file(fd, device.getNum(), path_str.c_str()); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +uint32_t Session::getClockRate(const Device& device, ClockRegion region) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + uint32_t rate = 0; + auto ret = vrtd_clock_get_rate(fd, device.getNum(), static_cast(region), &rate); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return rate; +} + +uint32_t Session::setClockRate(const Device& device, ClockRegion region, uint32_t rate_hz) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + uint32_t achieved = 0; + auto ret = vrtd_clock_set_rate(fd, device.getNum(), static_cast(region), rate_hz, &achieved); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return achieved; +} + +void Session::startQdmaQpair(const Device& device, uint32_t qid) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_qdma_qpair_start(fd, device.getNum(), qid); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Session::stopQdmaQpair(const Device& device, uint32_t qid) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_qdma_qpair_stop(fd, device.getNum(), qid); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +void Session::deleteQdmaQpair(const Device& device, uint32_t qid) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + auto ret = vrtd_qdma_qpair_del(fd, device.getNum(), qid); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } +} + +int Session::openQdmaQpairFd(const Device& device, uint32_t qid, uint32_t flags) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + int qfd = -1; + auto ret = vrtd_qdma_qpair_get_fd(fd, device.getNum(), qid, flags, &qfd); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + return qfd; +} + +std::vector Session::getSensorInfo(const Device& device) const { + if (isClosed()) { + throw Error(VRTD_RET_BAD_LIB_CALL); + } + std::lock_guard lk(*m); + + struct vrtd_sensor_entry entries[VRTD_SENSOR_MAX_ENTRIES]; + uint32_t count = 0; + + auto ret = vrtd_get_sensor_info(fd, device.getNum(), entries, + VRTD_SENSOR_MAX_ENTRIES, &count); + if (ret != VRTD_RET_OK) { + throw Error(ret); + } + + std::vector result; + result.reserve(count); + for (uint32_t i = 0; i < count; i++) { + result.push_back(SensorEntry{ + std::string(entries[i].name, strnlen(entries[i].name, sizeof(entries[i].name))), + entries[i].type, + entries[i].status, + entries[i].unit_mod, + entries[i].value + }); + } + + return result; +} + +void Session::close() noexcept { + if (isClosed()) { + return; + } + + ::close(fd); + fd = -1; + m = nullptr; +} + +bool Session::isClosed() const noexcept { + if (fd == -1 || !m) { + return true; + } else { + return false; + } +} + +} diff --git a/vrt/vrtd/src/CMakeLists.txt b/vrt/vrtd/src/CMakeLists.txt new file mode 100644 index 00000000..60685591 --- /dev/null +++ b/vrt/vrtd/src/CMakeLists.txt @@ -0,0 +1,71 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +# Static library containing all daemon logic (everything except main.c). +# Used by both the vrtd executable and the unit test targets. +add_library(vrtd_core STATIC + ${CMAKE_CURRENT_SOURCE_DIR}/accept.c + ${CMAKE_CURRENT_SOURCE_DIR}/allocator.c + ${CMAKE_CURRENT_SOURCE_DIR}/auth.c + ${CMAKE_CURRENT_SOURCE_DIR}/buffer.c + ${CMAKE_CURRENT_SOURCE_DIR}/clock.c + ${CMAKE_CURRENT_SOURCE_DIR}/config.c + ${CMAKE_CURRENT_SOURCE_DIR}/design_writer.c + ${CMAKE_CURRENT_SOURCE_DIR}/device.c + ${CMAKE_CURRENT_SOURCE_DIR}/hotplug.c + ${CMAKE_CURRENT_SOURCE_DIR}/reset.c + ${CMAKE_CURRENT_SOURCE_DIR}/serve.c + ${CMAKE_CURRENT_SOURCE_DIR}/signals.c + ${CMAKE_CURRENT_SOURCE_DIR}/utils.c +) + +set_target_properties(vrtd_core PROPERTIES + C_STANDARD 11 + C_STANDARD_REQUIRED YES + C_EXTENSIONS YES +) + +target_include_directories(vrtd_core + PUBLIC + $ + $ + ${CMAKE_CURRENT_SOURCE_DIR} +) + +target_link_libraries(vrtd_core + PUBLIC + ami::ami + slash::slash + PkgConfig::SYSTEMD + PkgConfig::INIH + Threads::Threads +) + +# Daemon executable +add_executable(vrtd ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +target_link_libraries(vrtd PRIVATE vrtd_core) + +set_target_properties(vrtd PROPERTIES + VERSION ${PROJECT_VERSION} + SOVERSION ${PROJECT_VERSION_MAJOR} +) + +add_executable(vrtd::vrtd ALIAS vrtd) diff --git a/vrt/vrtd/src/accept.c b/vrt/vrtd/src/accept.c new file mode 100644 index 00000000..2e14ece1 --- /dev/null +++ b/vrt/vrtd/src/accept.c @@ -0,0 +1,292 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file accept.c + * @brief New client connection handling for the vrtd daemon. + * + * When a client connects to vrtd's Unix domain socket (AF_UNIX / SOCK_SEQPACKET), + * this module accepts the connection, extracts the peer's credentials (UID/GIDs), + * and initialises a struct client that represents the connection for the lifetime + * of the session. + * + * Credential extraction is security-critical: the UID comes from SO_PEERCRED + * (kernel-verified, unforgeable), and the full set of supplementary GIDs is + * obtained via getgrouplist() so that role-based access control in the config + * layer can match against any group the connecting user belongs to. + */ + +#define _GNU_SOURCE + +#include "accept.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "utils.h" +#include "serve.h" +#include "state.h" + +static int create_client_event(sd_event_source *listener_event_source, int cfd, struct vrtd *state, struct client **clientp); +static int populate_uid_gid(int cfd, struct client *client); + +/** + * sd_event I/O callback invoked when a new client connects to the listening socket. + * + * Because the listening socket is non-blocking and edge-triggered events are + * possible, we loop calling accept4() until EAGAIN/EWOULDBLOCK to drain all + * pending connections in a single callback invocation. Each accepted + * connection is wrapped in a struct client, registered with the event loop + * for further I/O, and appended to state->clients. + */ +int on_event_new_connection(sd_event_source *s, int fd, uint32_t revents, void *userdata) +{ + struct vrtd *state = userdata; + + assert(state != NULL); + + if (!(revents & EPOLLIN)) { + return 0; + } + + /* Drain all pending connections from the accept queue. */ + for (;;) { + struct sockaddr_un peer; + socklen_t peerlen = sizeof(peer); + int cfd = accept4(fd, (struct sockaddr*)&peer, &peerlen, SOCK_NONBLOCK | SOCK_CLOEXEC); + if (cfd == -1) { + if (errno == EINTR) { + continue; + } + if (errno == EAGAIN || errno == EWOULDBLOCK) { + break; /* all pending connections accepted */ + } + LOG(LOG_ERR, "accept4() failed: %m"); + return -1; + } + + _cleanup_(cleanup_clientp) + struct client *client = NULL; + int ret = create_client_event(s, cfd, state, &client); + if (ret == -1) { + close(cfd); + continue; + } + + assert(client != NULL); + + ret = client_ptr_array_push_move(&state->clients, &client); + if (ret == -1) { + LOG(LOG_ERR, "Failed to allocate memory when adding new client"); + continue; + } + } + + return 0; +} + + +/** + * Allocate a struct client for an accepted connection and register it with + * the sd_event loop for read/hangup events. + * + * On success, *clientp is set to the new client (caller takes ownership via + * the cleanup attribute). On failure, the event source is automatically + * disabled and unreffed by the _cleanup_ attribute on @source, and the + * client is freed by the _cleanup_ attribute on @client. + * + * Initialisation steps: + * 1. Allocate and zero-initialise the client struct. + * 2. Register the client fd with EPOLLIN|EPOLLRDHUP so we are notified + * of incoming messages and peer disconnections. + * 3. Extract peer credentials (UID + supplementary GIDs) via + * populate_uid_gid() for later role-based access checks. + * 4. Assign a monotonically increasing connection ID (conn_id) used as + * the client_id for buffer/allocator ownership tracking. + */ +static int create_client_event(sd_event_source *listener_event_source, int cfd, struct vrtd *state, struct client **clientp) +{ + *clientp = calloc(1, sizeof **clientp); + PROPAGATE_ERROR_NULL_STDC_LOG(clientp, LOG_ERR, "Out of memory allocating client data"); + + _cleanup_(cleanup_clientp) + struct client *client = *clientp; + + _cleanup_(cleanup_free) + char *description = NULL; + + // If something fails, we should disable + unref. + _cleanup_(sd_event_source_disable_unrefp) + sd_event_source *source = NULL; + + sd_event *ev = sd_event_source_get_event(listener_event_source); + PROPAGATE_ERROR_NULL_LOG(ev, LOG_ERR, "Failed to get event for source"); + + int ret = sd_event_add_io(ev, &source, cfd, EPOLLIN | EPOLLRDHUP, on_client_io, client); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to add client as event source"); + + /* Build a human-readable description for the event source (used by + * sd_event debugging/logging). SO_PEERCRED is queried here purely + * for the description string; the authoritative credential extraction + * happens in populate_uid_gid() below. */ + { + struct ucred cred; + socklen_t clen = sizeof(cred); + if (getsockopt(cfd, SOL_SOCKET, SO_PEERCRED, &cred, &clen) == 0) { + ret = asprintf(&description, "client fd=%d pid=%d uid=%d gid=%d", + cfd, (int)cred.pid, (int)cred.uid, (int)cred.gid); + } else { + ret = asprintf(&description, "client fd=%d", cfd); + } + } + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to allocate description for client"); + + ret = populate_uid_gid(cfd, client); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to obtain user/group information for lcient"); + + ret = sd_event_source_set_description(source, description); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not set description for client fd"); + + /* Assign a unique, non-zero connection ID. IDs are monotonically + * increasing; on overflow we wrap to 1 (0 is reserved as "no owner" + * in the allocator's client_id tracking). */ + state->next_conn_id++; + if (state->next_conn_id == 0) { + state->next_conn_id = 1; + } + + /* Finish initialising the client struct fields. */ + client->fd = cfd; + client->in_fd = -1; /* no ancillary fd received yet */ + client->conn_id = state->next_conn_id; + LOG(LOG_DEBUG, "New client connection uid=%u conn_id=%llu fd=%d", (unsigned int)client->uid, (unsigned long long)client->conn_id, cfd); + client->state = state; + client->event_source = source; + + // Nothing went wrong. Do not unref. + source = NULL; + + // Nothing went wrong. Do not remove client. + client = NULL; + + return 0; +} + +/** + * Extract the connecting client's UID and full set of supplementary GIDs. + * + * The UID and primary GID are obtained from the kernel via SO_PEERCRED on the + * Unix socket -- this is unforgeable by the peer. We then resolve the + * username through getpwuid_r() and call getgrouplist() to retrieve all + * supplementary groups the user belongs to. The complete GID list is stored + * in client->gids so the config/role layer can grant permissions based on + * any group membership, not just the primary GID. + * + * The function updates client->uid and client->gids atomically: if any step + * fails after we begin writing, we roll back to the "unset" state + * (uid == (uid_t)-1, empty gids) so partial credentials are never visible. + */ +static +int populate_uid_gid(int cfd, struct client *client) +{ + if (!client || cfd < 0) { + LOG(LOG_ERR, "populate_uid_gid: invalid arguments"); + return -1; + } + + /* Step 1: Obtain the peer's PID, UID and primary GID from the kernel + * via SO_PEERCRED. This is the only trustworthy source of identity + * for a Unix domain socket peer. */ + struct ucred cred = {0}; + socklen_t len = sizeof(cred); + int rc = getsockopt(cfd, SOL_SOCKET, SO_PEERCRED, &cred, &len); + PROPAGATE_ERROR_STDC_LOG(rc, LOG_ERR, "SO_PEERCRED failed"); + + uid_t new_uid = cred.uid; + + /* Step 2: Resolve the UID to a username so we can call getgrouplist(). + * _SC_GETPW_R_SIZE_MAX may return -1 on some systems; we clamp to a + * sensible default of 16 KiB in that case. */ + long buflen = sysconf(_SC_GETPW_R_SIZE_MAX); + if (buflen <= 0 || buflen > (1 << 20)) buflen = 16384; + + _cleanup_(cleanup_free) char *pwbuf = malloc((size_t)buflen); + PROPAGATE_ERROR_NULL_STDC_LOG(pwbuf, LOG_ERR, "malloc pwbuf"); + + struct passwd pwent, *pw = NULL; + int pr = getpwuid_r(new_uid, &pwent, pwbuf, (size_t)buflen, &pw); + if (pr != 0 || !pw) { + LOG(LOG_ERR, "getpwuid_r(%u) failed: %s", + (unsigned)new_uid, + pr ? strerrordesc_np(pr) : "not found"); + return -1; + } + + /* Step 3: Retrieve all supplementary GIDs. We call getgrouplist() + * twice: once with a NULL buffer to learn the required count (it will + * return -1 and set ngroups), then again with a properly sized buffer. + * This two-pass approach avoids hard-coding NGROUPS_MAX. */ + int ngroups = 0; + (void)getgrouplist(pw->pw_name, cred.gid, NULL, &ngroups); /* expected to return -1 */ + if (ngroups <= 0) { + LOG(LOG_ERR, "getgrouplist probe returned non-positive size for user %s", pw->pw_name); + return -1; + } + + _cleanup_(cleanup_free) gid_t *groups = malloc((size_t)ngroups * sizeof(gid_t)); + PROPAGATE_ERROR_NULL_STDC_LOG(groups, LOG_ERR, "malloc groups[%d]", ngroups); + + int gl = getgrouplist(pw->pw_name, cred.gid, groups, &ngroups); + if (gl < 0 || ngroups <= 0) { + LOG(LOG_ERR, "getgrouplist fetch failed for user %s", pw->pw_name); + return -1; + } + + /* Step 4: Commit the credentials to the client struct. We defer all + * mutations until this point so that earlier failures leave the client + * in its prior state. From here on, any failure triggers a manual + * rollback to the "unset" state. */ + gid_t_array_free(&client->gids); + client->uid = new_uid; + + for (int i = 0; i < ngroups; ++i) { + int r = gid_t_array_push(&client->gids, groups[i]); + if (r == -1) { + LOG(LOG_ERR, "gid_t_array_push failed at index %d", i); + // Roll back to consistent "unset" state + gid_t_array_free(&client->gids); + client->uid = (uid_t)-1; + return -1; + } + } + + return 0; +} diff --git a/submodules/v80-vitis-flow/src/bd_builder/map_entry.cpp b/vrt/vrtd/src/accept.h similarity index 70% rename from submodules/v80-vitis-flow/src/bd_builder/map_entry.cpp rename to vrt/vrtd/src/accept.h index 95f0914d..48a907ee 100644 --- a/submodules/v80-vitis-flow/src/bd_builder/map_entry.cpp +++ b/vrt/vrtd/src/accept.h @@ -18,18 +18,13 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "map_entry.hpp" +#ifndef VRTD_ACCEPT_H +#define VRTD_ACCEPT_H -MapEntry::MapEntry(std::string name, uint64_t base_addr, uint64_t range) { - this->name = name; - this->baseAddress = base_addr; - this->range = range; -} +#include -std::string MapEntry::getName() { return name; } +#include -uint64_t MapEntry::getBaseAddr() { return baseAddress; } -uint64_t MapEntry::getRange() { return range; } +int on_event_new_connection(sd_event_source *s, int fd, uint32_t revents, void *userdata); -std::vector MapEntry::getRegisters() { return registers; } -void MapEntry::setRegisters(std::vector registers) { this->registers = registers; } \ No newline at end of file +#endif // VRTD_ACCEPT_H diff --git a/vrt/vrtd/src/allocator.c b/vrt/vrtd/src/allocator.c new file mode 100644 index 00000000..1f9df622 --- /dev/null +++ b/vrt/vrtd/src/allocator.c @@ -0,0 +1,308 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file allocator.c + * @brief QDMA device memory allocation tracker for DDR and HBM regions. + * + * The V80 FPGA exposes two classes of device-side memory -- DDR and HBM -- + * each divided into fixed-size regions (512 MiB). Every region is further + * split into subregions (64 MiB) which are the minimum allocation granularity. + * + * Allocation tracking uses a simple bitmap-like scheme: each subregion stores + * the owning client's connection ID (0 == free). To allocate N bytes the + * allocator rounds up to the next subregion boundary, then scans for a + * contiguous run of free subregions within a single region using a sliding + * window. This first-fit-per-region strategy keeps the logic O(regions * + * subregions) and avoids external fragmentation across region boundaries. + * + * Freeing validates that every subregion in the range is owned by the + * requesting client before clearing ownership, preventing use-after-free + * and cross-client interference. + * + * The allocator itself is stateless beyond the device_memory_map struct; + * create/destroy simply calloc/free that struct. + */ + +#define _GNU_SOURCE + +#include "allocator.h" + +#include + +/** + * Create a new device memory map with all subregions marked as free. + * + * calloc zero-initialises the struct, which means every client_id slot + * starts at 0 (the "free" sentinel). + * + * @return Heap-allocated map, or NULL on allocation failure. + */ +struct device_memory_map *device_memory_map_create(void) +{ + return calloc(1, sizeof(struct device_memory_map)); +} + +/** Free a device memory map. NULL-safe. */ +void device_memory_map_cleanup(struct device_memory_map *map) +{ + if (map == NULL) { + return; + } + + free(map); +} + +/** + * Allocate contiguous device memory from a DDR or HBM region. + * + * The requested @size is rounded up to the next multiple of SUBREGION_SIZE + * (64 MiB). The allocator performs a first-fit scan: it walks subregions + * within each candidate region, counting consecutive free slots; when the + * run length reaches the required count, the subregions are stamped with + * @client_id and the device-side base address is returned. + * + * For ALLOCATION_TYPE_HBM (non-VNOC), @arg selects the specific HBM region + * index (0..63). For DDR and HBM_VNOC, @arg is ignored and all regions are + * scanned. + * + * @param map The device memory map to allocate from. + * @param type DDR, HBM (pinned region), or HBM_VNOC (any HBM region). + * @param size [in/out] Requested size; updated to the rounded-up allocated size. + * @param arg HBM region index for ALLOCATION_TYPE_HBM; unused otherwise. + * @param client_id Non-zero connection ID that will own the allocation. + * @param addr_out [out] Device-side base address of the allocation. + * @return ALLOCATION_RESULT_SUCCESS, _NO_MEMORY, or _BAD_ARGUMENT. + */ +enum allocation_result device_memory_map_allocate(struct device_memory_map *map, + enum allocation_type type, + uint64_t *size, + uint64_t arg, + uint64_t client_id, + uint64_t *addr_out) + +{ + if (map == NULL || size == NULL || addr_out == NULL || *size == 0) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + /* Round up to whole subregions (64 MiB granularity). */ + uint64_t num_subregions = (*size + SUBREGION_SIZE - 1) / SUBREGION_SIZE; + + if (client_id == 0) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + switch (type) { + case ALLOCATION_TYPE_DDR: { + if (num_subregions > SUBREGIONS_PER_REGION) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + /* Scan all DDR regions for a contiguous run of free subregions + * (first-fit across regions, first-fit within each region). */ + for (size_t region_idx = 0; region_idx < DDR_REGIONS; region_idx++) { + size_t contiguous_free = 0; + for (size_t subregion_idx = 0; subregion_idx < SUBREGIONS_PER_REGION; subregion_idx++) { + if (map->ddr_regions[region_idx].client_id[subregion_idx] == 0) { + contiguous_free++; + if (contiguous_free == num_subregions) { + // Found a suitable block + size_t start_subregion = subregion_idx + 1 - num_subregions; + for (size_t i = 0; i < num_subregions; i++) { + map->ddr_regions[region_idx].client_id[start_subregion + i] = client_id; + } + *addr_out = DDR_START_ADDRESS + (region_idx * REGION_SIZE) + + (start_subregion * SUBREGION_SIZE); + *size = num_subregions * SUBREGION_SIZE; + return ALLOCATION_RESULT_SUCCESS; + } + } else { + contiguous_free = 0; + } + } + } + // No suitable block found + return ALLOCATION_RESULT_NO_MEMORY; + } + + case ALLOCATION_TYPE_HBM: { + /* HBM (non-VNOC): the caller specifies exactly which HBM region + * to allocate from via @arg. Useful when the FPGA design routes + * a particular AXI master to a specific HBM pseudo-channel. */ + if (arg >= HBM_REGIONS || num_subregions > SUBREGIONS_PER_REGION) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + size_t region_idx = (size_t)arg; + + if (region_idx >= HBM_REGIONS) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + size_t contiguous_free = 0; + for (size_t subregion_idx = 0; subregion_idx < SUBREGIONS_PER_REGION; subregion_idx++) { + if (map->hbm_regions[region_idx].client_id[subregion_idx] == 0) { + contiguous_free++; + if (contiguous_free == num_subregions) { + size_t start_subregion = subregion_idx + 1 - num_subregions; + for (size_t i = 0; i < num_subregions; i++) { + map->hbm_regions[region_idx].client_id[start_subregion + i] = client_id; + } + *addr_out = HBM_START_ADDRESS + (region_idx * REGION_SIZE) + + (start_subregion * SUBREGION_SIZE); + *size = num_subregions * SUBREGION_SIZE; + return ALLOCATION_RESULT_SUCCESS; + } + } else { + contiguous_free = 0; + } + } + + return ALLOCATION_RESULT_NO_MEMORY; + } + + case ALLOCATION_TYPE_HBM_VNOC: { + /* HBM via VNoC: the caller does not care which HBM region is used, + * so we scan all HBM regions (first-fit) to find available space. */ + if (num_subregions > SUBREGIONS_PER_REGION) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + /* Scan all HBM regions for a contiguous block of free subregions. */ + for (size_t region_idx = 0; region_idx < HBM_REGIONS; region_idx++) { + size_t contiguous_free = 0; + for (size_t subregion_idx = 0; subregion_idx < SUBREGIONS_PER_REGION; subregion_idx++) { + if (map->hbm_regions[region_idx].client_id[subregion_idx] == 0) { + contiguous_free++; + if (contiguous_free == num_subregions) { + size_t start_subregion = subregion_idx + 1 - num_subregions; + for (size_t i = 0; i < num_subregions; i++) { + map->hbm_regions[region_idx].client_id[start_subregion + i] = client_id; + } + *addr_out = HBM_START_ADDRESS + (region_idx * REGION_SIZE) + + (start_subregion * SUBREGION_SIZE); + *size = num_subregions * SUBREGION_SIZE; + return ALLOCATION_RESULT_SUCCESS; + } + } else { + contiguous_free = 0; + } + } + } + + return ALLOCATION_RESULT_NO_MEMORY; + } + + } + + return ALLOCATION_RESULT_BAD_ARGUMENT; +} + +/** + * Release a previously allocated device memory region. + * + * The function validates that every subregion in the [addr, addr+size) range + * is owned by @client_id before clearing any ownership. This two-pass + * approach (verify first, then clear) prevents partial frees when the + * caller provides mismatched parameters. + * + * @param map The device memory map. + * @param type Memory type (DDR or HBM/HBM_VNOC). + * @param addr Device-side base address returned by allocate. + * @param size Size of the allocation to free. + * @param client_id The owning connection ID; must match all subregions. + * @return ALLOCATION_RESULT_SUCCESS or _BAD_ARGUMENT. + */ +enum allocation_result device_memory_map_free(struct device_memory_map *map, + enum allocation_type type, + uint64_t addr, + uint64_t size, + uint64_t client_id) +{ + if (map == NULL || size == 0 || client_id == 0) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + uint64_t base; + uint64_t max_size; + struct ddr_region_data *ddr_regions = NULL; + struct hbm_region_data *hbm_regions = NULL; + + switch (type) { + case ALLOCATION_TYPE_DDR: + base = DDR_START_ADDRESS; + max_size = DDR_REGIONS * REGION_SIZE; + ddr_regions = map->ddr_regions; + break; + case ALLOCATION_TYPE_HBM: + case ALLOCATION_TYPE_HBM_VNOC: + base = HBM_START_ADDRESS; + max_size = HBM_REGIONS * REGION_SIZE; + hbm_regions = map->hbm_regions; + break; + default: + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + if (addr < base || addr >= base + max_size) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + /* Compute the offset relative to the memory class base and verify + * it is subregion-aligned (addresses must have been returned by allocate). */ + uint64_t offset = addr - base; + if ((offset % SUBREGION_SIZE) != 0) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + uint64_t num_subregions = (size + SUBREGION_SIZE - 1) / SUBREGION_SIZE; + size_t region_idx = (size_t)(offset / REGION_SIZE); + size_t start_subregion = (size_t)((offset % REGION_SIZE) / SUBREGION_SIZE); + + if (num_subregions > SUBREGIONS_PER_REGION || + start_subregion + num_subregions > SUBREGIONS_PER_REGION) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + + /* Two-pass free: first verify all subregions belong to this client, + * then clear ownership. This avoids a partial free if any subregion + * has been freed already or belongs to a different client. */ + if (ddr_regions != NULL) { + for (size_t i = 0; i < num_subregions; i++) { + if (ddr_regions[region_idx].client_id[start_subregion + i] != client_id) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + } + for (size_t i = 0; i < num_subregions; i++) { + ddr_regions[region_idx].client_id[start_subregion + i] = 0; + } + return ALLOCATION_RESULT_SUCCESS; + } + + for (size_t i = 0; i < num_subregions; i++) { + if (hbm_regions[region_idx].client_id[start_subregion + i] != client_id) { + return ALLOCATION_RESULT_BAD_ARGUMENT; + } + } + for (size_t i = 0; i < num_subregions; i++) { + hbm_regions[region_idx].client_id[start_subregion + i] = 0; + } + return ALLOCATION_RESULT_SUCCESS; +} diff --git a/vrt/vrtd/src/allocator.h b/vrt/vrtd/src/allocator.h new file mode 100644 index 00000000..1b13466b --- /dev/null +++ b/vrt/vrtd/src/allocator.h @@ -0,0 +1,196 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file allocator.h + * @brief Device memory map allocator for HBM and DDR address ranges. + * + * The SLASH V80 FPGA exposes two classes of on-board memory to userspace: + * - @b HBM (High Bandwidth Memory) -- 64 regions starting at 0x4000000000. + * - @b DDR -- 64 regions starting at 0x60000000000. + * + * Each region is 512 MB and is subdivided into 8 subregions of 64 MB each. + * Subregion tracking is per-client: each subregion records the connection ID + * of the client that allocated it (0 = free). This allows automatic cleanup + * when a client disconnects. + * + * Allocation granularity is one subregion (64 MB). Requested sizes are + * rounded up to the next subregion boundary. For non-VNOC HBM allocations, + * the caller specifies a region index; for DDR and HBM-VNOC, the allocator + * finds the first available contiguous run of subregions. + * + * The allocator is purely a bookkeeping structure -- it does not perform any + * hardware I/O. Actual DMA setup is handled by the buffer layer. + */ + +#ifndef VRTD_ALLOCATOR_H +#define VRTD_ALLOCATOR_H + +#include +#include + +/** @brief Number of HBM regions available on the device. */ +// Regions are 512MB +// Subregions are 64MB +#define HBM_REGIONS 64 +/** @brief Number of DDR regions available on the device. */ +#define DDR_REGIONS 64 +/** @brief Base device address of the HBM address space. */ +#define HBM_START_ADDRESS 0x4000000000ULL +/** @brief Base device address of the DDR address space. */ +#define DDR_START_ADDRESS 0x60000000000ULL +/** @brief Size of one region in bytes (512 MB). */ +#define REGION_SIZE (512UL * 1024 * 1024) +/** @brief Size of one subregion in bytes (64 MB). */ +#define SUBREGION_SIZE (64UL * 1024 * 1024) +/** @brief Number of subregions within each region (REGION_SIZE / SUBREGION_SIZE = 8). */ +#define SUBREGIONS_PER_REGION (REGION_SIZE / SUBREGION_SIZE) + +/** + * @brief Per-region subregion ownership tracking for DDR memory. + * + * Each element of @c client_id tracks the owner of one 64 MB subregion. + * A value of 0 indicates the subregion is free. + */ +struct ddr_region_data { + /** @brief Owner connection ID for each subregion (0 = free). */ + uint64_t client_id[SUBREGIONS_PER_REGION]; // 0 if free, non-zero owner connection id if allocated +}; + +/** + * @brief Per-region subregion ownership tracking for HBM memory. + * + * Identical layout to @c ddr_region_data but used for the HBM address space. + */ +struct hbm_region_data { + /** @brief Owner connection ID for each subregion (0 = free). */ + uint64_t client_id[SUBREGIONS_PER_REGION]; // 0 if free, non-zero owner connection id if allocated +}; + +/** + * @brief Complete memory map for one SLASH FPGA device. + * + * Contains subregion ownership arrays for all DDR and HBM regions. + * One instance exists per device and is shared (non-owning) with all + * buffers allocated on that device. + */ +struct device_memory_map { + /** @brief Subregion ownership data for all DDR regions. */ + struct ddr_region_data ddr_regions[DDR_REGIONS]; + /** @brief Subregion ownership data for all HBM regions. */ + struct hbm_region_data hbm_regions[HBM_REGIONS]; +}; + +/** + * @brief Memory type selector for allocation requests. + */ +enum allocation_type { + /** @brief Allocate from DDR memory. */ + ALLOCATION_TYPE_DDR, + /** @brief Allocate from HBM memory (caller specifies region index). */ + ALLOCATION_TYPE_HBM, + /** @brief Allocate from HBM memory via VNOC (auto region selection). */ + ALLOCATION_TYPE_HBM_VNOC, +}; + +/** + * @brief Allocate and zero-initialize a device memory map. + * @return Heap-allocated memory map on success, NULL on allocation failure. + */ +struct device_memory_map *device_memory_map_create(void); + +/** + * @brief Release a device memory map. + * @param map Pointer to the memory map to free. May be NULL (no-op). + */ +void device_memory_map_cleanup(struct device_memory_map *map); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param mapp Address of a @c struct @c device_memory_map pointer. + */ +static inline +void device_memory_map_cleanupp(struct device_memory_map **mapp) +{ + device_memory_map_cleanup(*mapp); + *mapp = NULL; +} + +/** + * @brief Result codes for allocation and free operations. + */ +enum allocation_result { + /** @brief Operation succeeded. */ + ALLOCATION_RESULT_SUCCESS = 0, + /** @brief Not enough contiguous subregions available. */ + ALLOCATION_RESULT_NO_MEMORY = 1, + /** @brief Invalid argument (e.g. region index out of range, zero size). */ + ALLOCATION_RESULT_BAD_ARGUMENT = 2, +}; + +/** + * @brief Allocate a contiguous range of subregions from the device memory map. + * + * For ALLOCATION_TYPE_HBM (non-VNOC), @p arg specifies the HBM region index (0-63). + * For ALLOCATION_TYPE_DDR and ALLOCATION_TYPE_HBM_VNOC, @p arg is ignored and the + * allocator searches for the first fit. + * + * @param map The device memory map to allocate from. + * @param type Memory type (DDR, HBM, or HBM_VNOC). + * @param[in,out] size On input, the requested size in bytes. + * On output, the actual allocated size (rounded up to the nearest + * subregion boundary). + * @param arg Type-specific argument (HBM region index for non-VNOC HBM). + * @param client_id Connection ID of the allocating client (recorded for ownership). + * @param[out] addr_out Receives the base device address of the allocation. + * @return ALLOCATION_RESULT_SUCCESS, ALLOCATION_RESULT_NO_MEMORY, or + * ALLOCATION_RESULT_BAD_ARGUMENT. + */ +// For ALLOCATION_TYPE_HBM (non-VNOC), arg specifies the HBM region index (0-63). +// Otherwise, arg is ignored. +// size is input as the requested size, and output as the allocated size (rounded up to +// the nearest subregion). +enum allocation_result device_memory_map_allocate(struct device_memory_map *map, + enum allocation_type type, + uint64_t *size, + uint64_t arg, + uint64_t client_id, + uint64_t *addr_out); + +/** + * @brief Free a previously allocated range of subregions. + * + * Marks the subregions covered by [@p addr, @p addr + @p size) as free, + * but only if they are currently owned by @p client_id. + * + * @param map The device memory map. + * @param type Memory type of the original allocation. + * @param addr Base device address of the allocation to free. + * @param size Size of the allocation in bytes. + * @param client_id Connection ID of the client that owns the allocation. + * @return ALLOCATION_RESULT_SUCCESS or ALLOCATION_RESULT_BAD_ARGUMENT. + */ +enum allocation_result device_memory_map_free(struct device_memory_map *map, + enum allocation_type type, + uint64_t addr, + uint64_t size, + uint64_t client_id); + +#endif // VRTD_ALLOCATOR_H diff --git a/vrt/vrtd/src/array.h b/vrt/vrtd/src/array.h new file mode 100644 index 00000000..7d9a6bd4 --- /dev/null +++ b/vrt/vrtd/src/array.h @@ -0,0 +1,353 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file array.h + * @brief Type-safe dynamic array macros for C. + * + * This header provides a macro system for declaring strongly-typed, heap-backed + * dynamic arrays. Two flavors are offered: + * + * - @c DECLARE_ARRAY(name, T) -- a plain dynamic array of value type @p T. + * Elements are copied by value on push and not individually freed on array + * destruction. + * + * - @c DECLARE_OWNING_PTR_ARRAY(name, T, cleanup) -- a dynamic array of + * pointer type @p T that @em owns its elements. On array destruction (or + * element removal), each element is passed through the @p cleanup function + * to free its resources. + * + * Both macros generate an inline API following the naming convention + * @c name_init, @c name_push, @c name_pop, @c name_resize, @c name_free, etc. + * + * @par Capacity strategy + * The backing buffer grows in powers of two (via @c bit_ceil) to amortize + * reallocation cost. A hysteresis check avoids thrashing when the length + * oscillates around a power-of-two boundary. + * + * @par Usage example + * @code + * // Declare a dynamic array of int: + * DECLARE_ARRAY(int_array, int) + * + * // Use it: + * struct int_array arr = int_array_init(); + * int_array_push(&arr, 42); + * int_array_push(&arr, 7); + * printf("len=%zu, first=%d\n", arr.len, arr.d[0]); // len=2, first=42 + * int_array_free(&arr); + * + * // Declare an owning pointer array with per-element cleanup: + * DECLARE_OWNING_PTR_ARRAY(widget_array, struct widget *, cleanup_widget) + * + * struct widget_array widgets = widget_array_init(); + * struct widget *w = widget_new(); + * widget_array_push_move(&widgets, &w); // w is now NULL, array owns it + * widget_array_free(&widgets); // calls cleanup_widget on each element + * @endcode + */ + +#ifndef VRTD_ARRAY_H +#define VRTD_ARRAY_H + +#include +#include +#include + +#include + +#include "utils.h" + +/** + * @brief Internal implementation macro shared by DECLARE_ARRAY and DECLARE_OWNING_PTR_ARRAY. + * + * Generates the struct definition and common operations: init, resize, push, + * pop, pop_safe, zero, shrink_to_fit, rm_by_value_impl, and free_impl. + * + * @param T_ARRAY Name of the generated array struct. + * @param T Element type. + */ +// DECLARE_ARRAY declares a dynamic array of type T. +// +// Access is done directly via a.d[i] and a.len. The 0-value is the 0-len array. +// +#define DECLARE_ARRAY_IMPL(T_ARRAY, T) \ + struct T_ARRAY { \ + /** @brief Pointer to the heap-allocated element storage. */ \ + T *d; \ + /** @brief Number of elements currently in the array. */ \ + size_t len; \ + /** @brief Allocated capacity (always a power of two, or zero). */ \ + size_t cap; \ + }; \ + \ + /** @brief Return a zero-initialized (empty) array. */ \ + static inline \ + struct T_ARRAY T_ARRAY##_init(void) { \ + return (struct T_ARRAY) { \ + .d = NULL, \ + .len = 0, \ + .cap = 0, \ + }; \ + } \ + \ + /** @brief Resize the array to exactly @p len elements, reallocating if needed. + * @param arr The array to resize. + * @param len The new length. + * @return 0 on success, -1 on allocation failure. */ \ + static inline NODISCARD \ + int T_ARRAY##_resize(struct T_ARRAY *arr, size_t len) \ + { \ + size_t cap = likely(len > 0) ? bit_ceil(len) : 0; \ + T *d; \ + \ + /* Don't constantly reallocate for add-remove 1024-1025 elements */ \ + /* This may reallocate unnecessarily (once) for tightened arrays but this is fine */ \ + /* Tighthening should only be done for arrays that will keep their size for a long time */ \ + /* Otherwise we'd have to complicate this hot comparison */ \ + if (cap == arr->cap || cap == (arr->cap >> 1)) { \ + arr->len = len; \ + return 0; \ + } \ + \ + d = (T *) reallocarray(arr->d, cap, sizeof(T)); \ + if (unlikely(d == NULL && cap != 0)) { \ + return -1; \ + } \ + \ + arr->d = d; \ + arr->len = len; \ + arr->cap = cap; \ + \ + return 0; \ + } \ + \ + /** @brief Append an element to the end of the array. + * @param arr The array to push to. + * @param v The value to append. + * @return 0 on success, -1 on allocation failure. */ \ + static inline NODISCARD \ + int T_ARRAY##_push(struct T_ARRAY *arr, T v) { \ + if (unlikely(T_ARRAY##_resize(arr, arr->len + 1) == -1)) { \ + return -1; \ + } \ + arr->d[arr->len - 1] = v; \ + return 0; \ + } \ + \ + /** @brief Remove and optionally return the last element. + * @param arr The array to pop from. + * @param out If non-NULL, receives the removed element. + * @return 0 on success, -1 if the array is empty or resize fails. */ \ + static inline int T_ARRAY##_pop(struct T_ARRAY *arr, T *out) { \ + if (arr->len == 0) { \ + return -1; \ + } \ + \ + if (out != NULL) { \ + *out = arr->d[arr->len - 1]; \ + } \ + \ + return T_ARRAY##_resize(arr, arr->len - 1); \ + } \ + \ + /** @brief Remove and optionally return the last element (no-op if empty, no resize). + * @param arr The array to pop from. + * @param out If non-NULL, receives the removed element. */ \ + static inline void T_ARRAY##_pop_safe(struct T_ARRAY *arr, T *out) { \ + if (arr->len == 0) { \ + return; \ + } \ + \ + if (out != NULL) { \ + *out = arr->d[arr->len - 1]; \ + } \ + \ + arr->len--; \ + } \ + \ + /** @brief Zero all bytes in the allocated capacity (not just len elements). + * @param arr The array to zero. */ \ + static inline \ + void T_ARRAY##_zero(struct T_ARRAY *arr) \ + { \ + memset(arr->d, 0, arr->cap * sizeof(T)); \ + } \ + \ + /** @brief Reallocate backing storage to exactly fit the current length. + * @param arr The array to shrink. + * @return 0 on success, -1 on allocation failure. */ \ + static inline \ + int T_ARRAY##_shrink_to_fit(struct T_ARRAY *arr) \ + { \ + T *d; \ + \ + d = (T *) reallocarray(arr->d, arr->len, sizeof(T)); \ + if (unlikely(d == NULL && arr->len != 0)) { \ + return -1; \ + } \ + \ + arr->d = d; \ + arr->cap = arr->len; \ + \ + return 0; \ + } \ + \ + /** @brief Remove all occurrences of @p value from the array (compacting). Internal impl. + * @param arr The array to compact. + * @param value The value to remove. */ \ + static inline \ + void T_ARRAY##_rm_by_value_impl(struct T_ARRAY *arr, T value) \ + { \ + size_t j = 0; \ + for (size_t i = 0; i < arr->len; i++) { \ + if (arr->d[i] == value) { \ + continue; \ + } \ + \ + arr->d[j++] = arr->d[i]; \ + } \ + \ + arr->len = j; \ + } \ + \ + /** @brief Free the backing storage and reset the array to empty. Internal impl. + * @param arr The array to free. */ \ + static inline \ + void T_ARRAY##_free_impl(struct T_ARRAY *arr) \ + { \ + free(arr->d); \ + \ + arr->d = NULL; \ + arr->len = 0; \ + arr->cap = 0; \ + } + +/** + * @brief Declare a non-owning dynamic array of value type @p T. + * + * Generates struct @p T_ARRAY and inline functions: _init, _resize, _push, + * _pop, _pop_safe, _zero, _shrink_to_fit, _free, _freep, _rm_by_value. + * + * @param T_ARRAY Name for the generated array struct. + * @param T Element type (must be copyable by assignment). + */ +#define DECLARE_ARRAY(T_ARRAY, T) \ + DECLARE_ARRAY_IMPL(T_ARRAY, T) \ + \ + /** @brief Free the array's backing storage and reset to empty. + * @param arr The array to free. */ \ + static inline \ + void T_ARRAY##_free(struct T_ARRAY *arr) \ + { \ + T_ARRAY##_free_impl(arr); \ + } \ +\ + /** @brief Cleanup helper for use with __attribute__((cleanup)). + * @param arr Address of a struct T_ARRAY pointer. */ \ + static inline \ + void T_ARRAY##_freep(struct T_ARRAY **arr) \ + { \ + T_ARRAY##_free(*arr); \ + *arr = NULL; \ + } \ + \ + /** @brief Remove all occurrences of @p value from the array (compacting, no cleanup). + * @param arr The array to compact. + * @param value The value to remove. */ \ + static inline \ + void T_ARRAY##_rm_by_value(struct T_ARRAY *arr, T value) \ + { \ + T_ARRAY##_rm_by_value_impl(arr, value); \ + } + +/** + * @brief Declare an owning dynamic array of pointer type @p T with per-element cleanup. + * + * Like DECLARE_ARRAY, but additionally generates: + * - @c _push_move: transfers ownership of a pointer into the array (NULLs the source). + * - @c _free: calls @p CLEANUP on every element before freeing the storage. + * - @c _rm_by_reference: removes an element by pointer equality, calling @p CLEANUP on it. + * + * @param T_ARRAY Name for the generated array struct. + * @param T Element type (must be a pointer type). + * @param CLEANUP Function called on each element during destruction, signature: void CLEANUP(T). + */ +#define DECLARE_OWNING_PTR_ARRAY(T_ARRAY, T, CLEANUP) \ + DECLARE_ARRAY_IMPL(T_ARRAY, T) \ + \ + /** @brief Transfer ownership of @p *ptr into the array. Sets *ptr to NULL on success. + * @param arr The array to push to. + * @param ptr Address of the pointer to move in (set to NULL on success). + * @return 0 on success, -1 on allocation failure (*ptr unchanged). */ \ + static inline \ + int T_ARRAY##_push_move(struct T_ARRAY *arr, T *ptr) \ + { \ + int ret = T_ARRAY##_push(arr, *ptr); \ + if (unlikely(ret == -1)) { \ + return -1; \ + } \ + \ + *ptr = NULL; \ + \ + return 0; \ + } \ + \ + /** @brief Free the array, calling CLEANUP on each element first. + * @param arr The array to free. */ \ + static inline \ + void T_ARRAY##_free(struct T_ARRAY *arr) \ + { \ + for (size_t i = 0; i < arr->len; ++i) { \ + CLEANUP(arr->d[i]); \ + } \ + \ + T_ARRAY##_free_impl(arr); \ + } \ + \ + /** @brief Remove an element by pointer equality, calling CLEANUP on it. Compacts the array. + * @param arr The array to remove from. + * @param value The pointer to find and remove. */ \ + static inline \ + void T_ARRAY##_rm_by_reference(struct T_ARRAY *arr, T value) \ + { \ + size_t j = 0; \ + for (size_t i = 0; i < arr->len; i++) { \ + if (arr->d[i] == value) { \ + CLEANUP(arr->d[i]); \ + continue; \ + } \ + arr->d[j++] = arr->d[i]; \ + } \ + arr->len = j; \ + } + +/* Pre-declared array types used throughout the daemon. */ + +/** @brief Dynamic array of int values. */ +DECLARE_ARRAY(int_array, int) +/** @brief Dynamic array of unsigned int values. */ +DECLARE_ARRAY(uint_array, unsigned int) +/** @brief Dynamic array of gid_t values (POSIX group IDs). */ +DECLARE_ARRAY(gid_t_array, gid_t) +/** @brief Owning dynamic array of heap-allocated strings (freed with free()). */ +DECLARE_OWNING_PTR_ARRAY(str_array, char *, free) + +#endif // VRTD_ARRAY_H diff --git a/vrt/vrtd/src/auth.c b/vrt/vrtd/src/auth.c new file mode 100644 index 00000000..db65dc4d --- /dev/null +++ b/vrt/vrtd/src/auth.c @@ -0,0 +1,900 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file auth.c + * @brief Per-request authorization enforcement for vrtd. + * + * This file implements the authorization layer of the V80 Runtime Daemon + * (vrtd). Every incoming client request passes through one of the + * auth_request_*() functions before the daemon executes the corresponding + * operation. Each function checks that the client's effective role grants + * the required permissions. + * + * Permission model: + * - A connected client carries a UID and a set of GIDs (obtained from the + * Unix domain socket credentials at connection time). + * - On the first authorization check, ensure_role() lazily constructs the + * client's effective (merged) role by combining: + * 1. The **default user** roles (applied to every client). + * 2. Any **user-specific** roles whose UID matches the client's UID. + * 3. Any **group-specific** roles whose GID matches one of the client's + * supplementary GIDs. + * Merging uses logical OR for each permission flag, so the client receives + * the union (most permissive) of all applicable roles. + * - The merged role is cached on the client struct for the lifetime of + * the connection. + * + * Authorization check categories: + * - **Query-only** operations (get_device_info, get_device_by_bdf, + * get_num_devices, get_bar_info, qdma_get_info): require only the + * `query` permission. + * - **Device-access** operations (get_bar_fd, qdma_qpair_add/op/get_fd, + * buffer_open/close, design_write, clock_op): require `query` plus + * the corresponding per-device per-subsystem permission (bar, qdma, + * buffer, design-write, clock) as defined in the role's device_policies. + * - **Hotplug** operations (device_hotplug_op): require `query` plus + * per-device pcie-hotplug permission or the global pcie_hotplug flag. + * + * Return convention for auth_request_*() functions: + * - 1 = authorized (proceed with the operation) + * - 0 = denied (the daemon should send an error response) + * - <0 = internal error (propagated via PROPAGATE_ERROR) + */ + +#define _GNU_SOURCE + +#include "auth.h" +#include "config.h" +#include "device.h" +#include "state.h" +#include "utils.h" + +#include +#include +#include +#include + +int ensure_role(struct client *client); + +/** + * @brief Identifies which subsystem permission to check on a device. + */ +enum auth_subsystem { + AUTH_SUBSYSTEM_BAR, + AUTH_SUBSYSTEM_QDMA, + AUTH_SUBSYSTEM_BUFFER, + AUTH_SUBSYSTEM_DESIGN_WRITE, + AUTH_SUBSYSTEM_CLOCK, + AUTH_SUBSYSTEM_PCIE_HOTPLUG, + AUTH_SUBSYSTEM_RAW_MEM_ACCESS, +}; + +/** + * @brief Human-readable names for auth_subsystem values (for log messages). + */ +static const char *auth_subsystem_name(enum auth_subsystem subsystem) +{ + switch (subsystem) { + case AUTH_SUBSYSTEM_BAR: return "bar-access"; + case AUTH_SUBSYSTEM_QDMA: return "qdma"; + case AUTH_SUBSYSTEM_BUFFER: return "buffer"; + case AUTH_SUBSYSTEM_DESIGN_WRITE: return "design-write"; + case AUTH_SUBSYSTEM_CLOCK: return "clock"; + case AUTH_SUBSYSTEM_PCIE_HOTPLUG: return "pcie-hotplug"; + case AUTH_SUBSYSTEM_RAW_MEM_ACCESS: return "raw-mem-access"; + default: return "unknown"; + } +} + +/** + * @brief Check whether a device_policy grants a specific subsystem permission. + */ +static bool device_policy_check(const struct device_policy *dp, enum auth_subsystem subsystem) +{ + switch (subsystem) { + case AUTH_SUBSYSTEM_BAR: return dp->bar; + case AUTH_SUBSYSTEM_QDMA: return dp->qdma; + case AUTH_SUBSYSTEM_BUFFER: return dp->buffer; + case AUTH_SUBSYSTEM_DESIGN_WRITE: return dp->design_write; + case AUTH_SUBSYSTEM_CLOCK: return dp->clock; + case AUTH_SUBSYSTEM_PCIE_HOTPLUG: return dp->pcie_hotplug; + case AUTH_SUBSYSTEM_RAW_MEM_ACCESS: return dp->raw_mem_access; + default: return false; + } +} + +/** + * @brief Build a comma-separated string of all role names applicable to a client. + * + * Iterates through the default user's roles, user-specific roles (matched by + * UID), and group-specific roles (matched by GID) to produce a human-readable + * summary. This is used in denial log messages to help administrators + * understand which roles a client actually has. + * + * @param client The client whose roles should be collected. + * @return Heap-allocated comma-separated role name string, or NULL if the + * client has no roles or on allocation failure. Caller must free(). + */ +static char *auth_collect_role_names(const struct client *client) +{ + assert(client->state != NULL); + assert(client->state->config != NULL); + const struct config *config = client->state->config; + + char *roles_str = NULL; + size_t roles_len = 0; + bool any_role = false; + + #define APPEND_ROLE(r) \ + do { \ + const char *rname = (r)->name; \ + if (rname == NULL) break; \ + size_t rlen = strlen(rname); \ + size_t need = roles_len + (any_role ? 2 : 0) + rlen + 1; \ + char *tmp = realloc(roles_str, need); \ + if (tmp == NULL) { free(roles_str); return NULL; } \ + roles_str = tmp; \ + if (any_role) { \ + memcpy(roles_str + roles_len, ", ", 2); \ + roles_len += 2; \ + } \ + memcpy(roles_str + roles_len, rname, rlen + 1); \ + roles_len += rlen; \ + any_role = true; \ + } while (0) + + /* Collect roles from the default (wildcard) user -- these apply to everyone. */ + if (config->default_user != NULL) { + for (size_t i = 0; i < config->default_user->roles.len; i++) { + APPEND_ROLE(config->default_user->roles.d[i]); + } + } + + /* Collect roles from user entries matching this client's UID. */ + for (size_t i = 0; i < config->users.len; i++) { + const struct user_config *uc = config->users.d[i]; + if (uc == NULL || uc->uid != client->uid) { + continue; + } + for (size_t j = 0; j < uc->roles.len; j++) { + APPEND_ROLE(uc->roles.d[j]); + } + } + + /* Collect roles from group entries matching any of the client's GIDs. */ + for (size_t i = 0; i < config->groups.len; i++) { + const struct group_config *gc = config->groups.d[i]; + if (gc == NULL) { + continue; + } + for (size_t j = 0; j < client->gids.len; j++) { + if (gc->gid != client->gids.d[j]) { + continue; + } + for (size_t k = 0; k < gc->roles.len; k++) { + APPEND_ROLE(gc->roles.d[k]); + } + break; + } + } + + #undef APPEND_ROLE + + return roles_str; +} + +/** + * @brief Log a permission-denied message with the client's identity and roles. + * + * Emits a LOG_WARNING with the denied operation and the specific permission + * that was missing, then a LOG_INFO listing all roles the client holds (to + * aid debugging and auditing). + * + * @param client The client that was denied. + * @param operation Human-readable name of the denied operation. + * @param missing_permission The specific permission flag the client lacks. + */ +static void auth_log_denied( + struct client *client, + const char *operation, + const char *missing_permission +) +{ + char pwbuf[1024]; + const char *username = uid_to_username(client->uid, pwbuf, sizeof(pwbuf)); + + LOG( + LOG_WARNING, + "Permission denied for uid %u(%s): '%s' requires '%s'", + (unsigned int) client->uid, + username, + operation, + missing_permission + ); + + char *roles_str = auth_collect_role_names(client); + if (roles_str != NULL) { + LOG( + LOG_INFO, + "User uid %u(%s) has roles: %s", + (unsigned int) client->uid, + username, + roles_str + ); + free(roles_str); + } else { + LOG( + LOG_INFO, + "User uid %u(%s) has no roles", + (unsigned int) client->uid, + username + ); + } +} + +/* ======================================================================== + * Per-device, per-subsystem authorization check + * + * This is the core authorization helper for all device-access operations. + * It resolves the target device's BDF from the device index, then looks up + * the client's role for a matching device_policy entry (exact BDF match + * first, then "any" wildcard fallback). + * ======================================================================== */ + +/** + * @brief Check whether the client's role grants a specific subsystem + * permission on the device identified by @p dev_number. + * + * Resolution logic: + * 1. Verify the client has the "query" permission (prerequisite for all + * device operations). + * 2. Resolve @p dev_number to the device's board-level BDF string. + * 3. Search the role's device_policies for an exact BDF match. + * 4. If no exact match, search for an "any" wildcard entry. + * 5. Check the requested subsystem flag on the matching policy. + * 6. For PCIE_HOTPLUG, also check the global role->pcie_hotplug flag. + * + * @param client The requesting client (carries the role and device state). + * @param dev_number The 0-based device index from the request body. + * @param subsystem Which subsystem permission to check. + * @param operation Human-readable operation name (for denial logging). + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +static int auth_check_device_permission( + struct client *client, + uint32_t dev_number, + enum auth_subsystem subsystem, + const char *operation +) +{ + assert(client != NULL); + assert(client->role != NULL); + + /* All device-access operations require the query permission. */ + if (!client->role->query) { + auth_log_denied(client, operation, "query"); + return 0; + } + + /* Resolve device index to BDF string. */ + assert(client->state != NULL); + if (dev_number >= client->state->devices.len) { + /* Invalid device index -- this is a request validation error, + * not an auth error, but deny it here for safety. */ + return 0; + } + + const struct device *dev = client->state->devices.d[dev_number]; + assert(dev != NULL); + const char *dev_bdf = dev->pci_info.bdf; + + /* Search for a device_policy matching this device's BDF. */ + const struct device_policy *dp = NULL; + const struct device_policy *any_dp = NULL; + + for (size_t i = 0; i < client->role->device_policies.len; i++) { + const struct device_policy *candidate = client->role->device_policies.d[i]; + if (strcmp(candidate->bdf, dev_bdf) == 0) { + dp = candidate; + break; + } + if (strcmp(candidate->bdf, "any") == 0) { + any_dp = candidate; + } + } + + /* Fall back to "any" wildcard if no exact match. */ + if (dp == NULL) { + dp = any_dp; + } + + if (dp == NULL) { + /* No device policy matches -- denied. */ + char denied_msg[128]; + snprintf(denied_msg, sizeof(denied_msg), "%s (device %s)", + auth_subsystem_name(subsystem), dev_bdf); + auth_log_denied(client, operation, denied_msg); + return 0; + } + + if (!device_policy_check(dp, subsystem)) { + char denied_msg[128]; + snprintf(denied_msg, sizeof(denied_msg), "%s (device %s)", + auth_subsystem_name(subsystem), dev_bdf); + auth_log_denied(client, operation, denied_msg); + return 0; + } + + return 1; +} + +/* ======================================================================== + * Query-only authorization checks + * + * These operations only require the "query" permission, which allows + * enumerating and inspecting devices without modifying state or accessing + * device memory. + * ======================================================================== */ + +/** + * @brief Authorize a get_device_info request. + * + * Requires: query permission. + * + * @param client The requesting client. + * @param req_body The request payload (unused for auth, present for signature consistency). + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + auth_log_denied(client, "get_device_info", "query"); + return 0; + } +} + +/** + * @brief Authorize a get_device_by_bdf request. + * + * Requires: query permission. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_get_device_by_bdf( + struct client *client, + const struct vrtd_req_get_device_by_bdf *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + auth_log_denied(client, "get_device_by_bdf", "query"); + return 0; + } +} + +/** + * @brief Authorize a get_num_devices request. + * + * Requires: query permission. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + auth_log_denied(client, "get_num_devices", "query"); + return 0; + } +} + +/** + * @brief Authorize a get_bar_info request. + * + * Requires: query permission. This only retrieves BAR metadata (size, + * address); it does not grant memory-mapped access. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + auth_log_denied(client, "get_bar_info", "query"); + return 0; + } +} + +/* ======================================================================== + * Device-access authorization checks + * + * These operations provide direct access to device resources (BAR file + * descriptors, QDMA queue pairs, DMA buffers, design programming, clocks). + * Each operation checks the corresponding per-device per-subsystem permission + * via auth_check_device_permission(). + * ======================================================================== */ + +/** + * @brief Authorize a get_bar_fd request (memory-mapped BAR access). + * + * Requires: query + bar-access permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_BAR, "get_bar_fd" + ); +} + +/** + * @brief Authorize a qdma_get_info request (QDMA subsystem query). + * + * Requires: query permission only (informational, no data-plane access). + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + auth_log_denied(client, "qdma_get_info", "query"); + return 0; + } +} + +/** + * @brief Authorize a qdma_qpair_add request (create a QDMA queue pair). + * + * Requires: query + qdma permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_QDMA, "qdma_qpair_add" + ); +} + +/** + * @brief Authorize a qdma_qpair_op request (start/stop a QDMA queue pair). + * + * Requires: query + qdma permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_QDMA, "qdma_qpair_op" + ); +} + +/** + * @brief Authorize a qdma_qpair_get_fd request (get fd for a QDMA queue pair). + * + * Requires: query + qdma permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_QDMA, "qdma_qpair_get_fd" + ); +} + +/** + * @brief Authorize a buffer_open request (allocate a DMA buffer). + * + * Requires: query + buffer permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_buffer_open( + struct client *client, + const struct vrtd_req_buffer_open *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_BUFFER, "buffer_open" + ); +} + +/** + * @brief Authorize a buffer_open_raw request (open a raw DMA buffer, bypassing the allocator). + * + * Requires: query + raw-mem-access permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_buffer_open_raw( + struct client *client, + const struct vrtd_req_buffer_open_raw *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_RAW_MEM_ACCESS, "buffer_open_raw" + ); +} + +/** + * @brief Authorize a buffer_close request (release a DMA buffer). + * + * Requires: query + buffer permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_buffer_close( + struct client *client, + const struct vrtd_req_buffer_close *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_BUFFER, "buffer_close" + ); +} + +/** + * @brief Authorize a design_write request (program an FPGA bitstream). + * + * Requires: query + design-write permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_design_write( + struct client *client, + const struct vrtd_req_design_write *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_DESIGN_WRITE, "design_write" + ); +} + +/* ======================================================================== + * Hotplug authorization check + * + * PCIe hotplug is a destructive control-plane operation (removing/adding + * devices from the bus). It requires a per-device pcie-hotplug flag in a + * device_policy (specified via [role:name:bdf] or [role:name:any]). + * ======================================================================== */ + +/** + * @brief Authorize a device_hotplug_op request (PCIe hot-plug/remove). + * + * Requires: query + pcie-hotplug permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_device_hotplug_op( + struct client *client, + const struct vrtd_req_device_hotplug_op *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_PCIE_HOTPLUG, "device_hotplug_op" + ); +} + +/** + * @brief Authorize a clock_op request (read/modify device clock settings). + * + * Requires: query + clock permission on the target device. + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_clock_op( + struct client *client, + const struct vrtd_req_clock_op *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + return auth_check_device_permission( + client, req_body->dev_number, AUTH_SUBSYSTEM_CLOCK, "clock_op" + ); +} + +/** + * @brief Authorize a get_sensor_info request. + * + * Requires: query permission only (informational, read-only sensor data). + * + * @param client The requesting client. + * @param req_body The request payload. + * @return 1 if authorized, 0 if denied, <0 on internal error. + */ +int auth_request_get_sensor_info( + struct client *client, + const struct vrtd_req_get_sensor_info *req_body +) +{ + assert(client != NULL); + assert(req_body != NULL); + + int ret = ensure_role(client); + PROPAGATE_ERROR(ret); + + assert(client->role != NULL); + + if (client->role->query) { + return 1; + } else { + auth_log_denied(client, "get_sensor_info", "query"); + return 0; + } +} + +/* ======================================================================== + * Role resolution (lazy, per-client) + * + * ensure_role() is called at the top of every auth_request_*() function. + * On first invocation for a given client it builds the merged effective role; + * on subsequent calls it returns immediately (the role is cached on the + * client struct). + * + * Merging order: + * 1. Start with an empty role (all permissions false). + * 2. OR in the default_user's roles (wildcard -- applies to everyone). + * 3. OR in roles from any [user:] entry whose UID matches the + * client's UID. + * 4. OR in roles from any [group:] entry whose GID matches one + * of the client's supplementary GIDs. + * + * Because merging uses OR, a permission granted by any single matching + * role cannot be revoked by another role (highest privilege wins). + * ======================================================================== */ + +/** + * @brief Lazily construct the merged effective role for a client. + * + * If client->role is already set, returns immediately. Otherwise, creates a + * new role via role_merge_new() and merges in permissions from all applicable + * sources: default user roles, UID-matched user roles, and GID-matched group + * roles. + * + * The resulting role is stored on client->role and persists for the lifetime + * of the client connection (it is freed when the client is cleaned up). + * + * @param client The client whose role should be resolved. + * @return 0 on success, <0 on allocation or merge error. + */ +int ensure_role(struct client *client) +{ + assert(client != NULL); + + /* If a role has already been computed for this client, use the cached one. */ + if (client->role != NULL) { + return 0; + } + + _cleanup_(cleanup_free) + char *role_name = NULL; + + int ret = asprintf(&role_name, "Internal role for user: %u", (unsigned int) client->uid); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Allocation error when creating internal role for user"); + + _cleanup_(cleanup_rolep) + struct role *role = NULL; + + ret = role_merge_new(&role, "TODO: Change this string"); + PROPAGATE_ERROR(ret); + + assert(client->state != NULL); + assert(client->state->config != NULL); + + const struct config *config = client->state->config; + + /* Step 1: merge in default user roles (apply to every client). */ + ret = role_merge_add_array(role, &config->default_user->roles); + PROPAGATE_ERROR(ret); + + /* Step 2: merge in roles from user entries matching this client's UID. */ + for (size_t i = 0; i < config->users.len; i++) { + const struct user_config *user_config = config->users.d[i]; + assert(user_config != NULL); + + if (user_config->uid == client->uid) { + ret = role_merge_add_array(role, &user_config->roles); + PROPAGATE_ERROR(ret); + } + } + + /* Step 3: merge in roles from group entries matching any of the client's GIDs. */ + for (size_t i = 0; i < config->groups.len; i++) { + const struct group_config *group_config = config->groups.d[i]; + assert(group_config != NULL); + + for (size_t j = 0; j < client->gids.len; j++) { + gid_t gid = client->gids.d[j]; + + if (group_config->gid == gid) { + ret = role_merge_add_array(role, &group_config->roles); + PROPAGATE_ERROR(ret); + } + } + } + + /* Transfer ownership of the merged role to the client. */ + client->role = role; + role = NULL; + + return 0; +} diff --git a/vrt/vrtd/src/auth.h b/vrt/vrtd/src/auth.h new file mode 100644 index 00000000..b7d9d5c1 --- /dev/null +++ b/vrt/vrtd/src/auth.h @@ -0,0 +1,293 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file auth.h + * @brief Role-based authorization checks for vrtd client requests. + * + * Every request received from a client passes through a corresponding + * @c auth_request_* function before execution. These functions consult the + * client's assigned @c struct @c role to decide whether the operation is + * permitted. + * + * The permission model works as follows: + * - Each client is assigned a merged role at connection time (based on + * UID/GID lookups against the daemon configuration). + * - The role contains: + * - A set of allowed device indices (or a wildcard "allow any" flag). + * - A BAR-level access policy controlling which BARs may be mmap'd. + * - Boolean flags for query, PCIe hotplug, and other operation classes. + * - An @c auth_request_* function returns 0 if the request is authorized, + * or populates the client's outbound buffer with an ACCESS_DENIED response + * and returns a non-zero value to short-circuit the handler. + * + * Every auth function follows the same signature convention: + * @code + * int auth_request_(struct client *client, + * const struct vrtd_req_ *req_body); + * @endcode + */ + +#ifndef VRTD_AUTH_H +#define VRTD_AUTH_H + +#include "serve.h" + +/** + * @brief Authorize a GET_DEVICE_INFO request. + * + * Checks that the client's role permits querying and accessing the + * specified device index. + * + * @param client The requesting client (carries the role and response buffer). + * @param req_body The parsed request body containing the target device index. + * @return 0 if authorized, non-zero if denied (response buffer populated). + */ +int auth_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body +); + +/** + * @brief Authorize a GET_DEVICE_BY_BDF request. + * + * Checks that the client's role permits querying devices by PCI + * Bus/Device/Function address. + * + * @param client The requesting client. + * @param req_body The parsed request body containing the target BDF. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_get_device_by_bdf( + struct client *client, + const struct vrtd_req_get_device_by_bdf *req_body +); + +/** + * @brief Authorize a GET_NUM_DEVICES request. + * + * Checks that the client's role permits device enumeration queries. + * + * @param client The requesting client. + * @param req_body The parsed request body (may be empty for this query). + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body +); + +/** + * @brief Authorize a GET_BAR_INFO request. + * + * Checks that the client's role permits accessing the specified device + * and querying BAR metadata. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device and BAR indices. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body +); + +/** + * @brief Authorize a GET_BAR_FD request. + * + * Checks that the client's role permits mmap access to the requested BAR + * on the specified device, per the role's per-device bar-access policy. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device and BAR indices. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body +); + +/** + * @brief Authorize a QDMA_GET_INFO request. + * + * Checks that the client's role permits querying QDMA subsystem + * information on the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing the target device index. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body +); + +/** + * @brief Authorize a QDMA_QPAIR_ADD request. + * + * Checks that the client's role permits adding a QDMA queue pair + * on the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index and queue parameters. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body +); + +/** + * @brief Authorize a QDMA_QPAIR_OP request (start/stop/delete). + * + * Checks that the client's role permits queue pair lifecycle operations + * on the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index and queue ID. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body +); + +/** + * @brief Authorize a QDMA_QPAIR_GET_FD request. + * + * Checks that the client's role permits obtaining a file descriptor for + * a QDMA queue pair on the specified device (fd is passed via SCM_RIGHTS). + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index and queue ID. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body +); + +/** + * @brief Authorize a BUFFER_OPEN request. + * + * Checks that the client's role permits allocating a DMA buffer + * (HBM or DDR) on the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index, size, and memory type. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_buffer_open( + struct client *client, + const struct vrtd_req_buffer_open *req_body +); + +/** + * @brief Authorize a BUFFER_OPEN_RAW request. + * + * Checks that the client's role permits opening a raw DMA buffer + * (bypassing the allocator) on the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index and address. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_buffer_open_raw( + struct client *client, + const struct vrtd_req_buffer_open_raw *req_body +); + +/** + * @brief Authorize a BUFFER_CLOSE request. + * + * Checks that the client's role permits deallocating a DMA buffer + * and that the buffer belongs to this client. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index and buffer address. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_buffer_close( + struct client *client, + const struct vrtd_req_buffer_close *req_body +); + +/** + * @brief Authorize a DESIGN_WRITE request (FPGA bitstream programming). + * + * Checks that the client's role permits writing a bitstream to the + * specified device. The bitstream file descriptor is received via + * SCM_RIGHTS ancillary data. + * + * @param client The requesting client. + * @param req_body The parsed request body containing the target device index. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_design_write( + struct client *client, + const struct vrtd_req_design_write *req_body +); + +/** + * @brief Authorize a DEVICE_HOTPLUG_OP request (PCIe SBR toggle). + * + * Checks that the client's role has the @c pcie_hotplug permission + * for the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing the target device index. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_device_hotplug_op( + struct client *client, + const struct vrtd_req_device_hotplug_op *req_body +); + +/** + * @brief Authorize a CLOCK_OP request (get/set clock frequency). + * + * Checks that the client's role permits clock control operations + * on the specified device. + * + * @param client The requesting client. + * @param req_body The parsed request body containing device index and clock parameters. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_clock_op( + struct client *client, + const struct vrtd_req_clock_op *req_body +); + +/** + * @brief Authorize a GET_SENSOR_INFO request. + * + * Checks that the client's role permits querying sensor information + * on the specified device. This is a query-only operation. + * + * @param client The requesting client. + * @param req_body The parsed request body containing the target device index. + * @return 0 if authorized, non-zero if denied. + */ +int auth_request_get_sensor_info( + struct client *client, + const struct vrtd_req_get_sensor_info *req_body +); + +#endif // VRTD_AUTH_H diff --git a/vrt/vrtd/src/buffer.c b/vrt/vrtd/src/buffer.c new file mode 100644 index 00000000..5a30076e --- /dev/null +++ b/vrt/vrtd/src/buffer.c @@ -0,0 +1,424 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file buffer.c + * @brief Buffer lifecycle management: allocate, initialise, and free QDMA-backed + * device memory buffers. + * + * A "buffer" in vrtd ties together three resources: + * + * 1. A device memory allocation (DDR or HBM subregions tracked by the + * allocator in allocator.c). + * 2. A QDMA queue pair (qpair) that provides the DMA channel for host<->device + * data movement to/from that allocation. + * 3. A file descriptor obtained from the QDMA driver that the client can + * mmap() or read()/write() against. + * + * buffer_create() orchestrates acquiring all three; cleanup_buffer() tears + * them down in reverse order, tolerating partial initialisation so that the + * error path from buffer_init() can safely call it. + */ + +#include "buffer.h" +#include "utils.h" + +#include +#include +#include +#include +#include + +#include + +/* QDMA queue configuration constants. */ +#define VRTD_QDMA_Q_MODE_MM 0u /* Memory-mapped (MM) mode */ +#define VRTD_QDMA_DIR_H2C (1u << 0) /* Host-to-Card direction */ +#define VRTD_QDMA_DIR_C2H (1u << 1) /* Card-to-Host direction */ +#define VRTD_QDMA_RING_SZ_IDX 0u /* Default ring size index */ + +/** + * Initialise a buffer: allocate device memory, create a QDMA queue pair, + * start the queue, and obtain a file descriptor for host-side access. + * + * Initialisation proceeds in strict order: + * 1. Allocate device memory via the allocator (sets buf->addr, buf->size). + * 2. Translate the requested transfer direction into QDMA direction flags. + * 3. Add a QDMA queue pair configured for memory-mapped (MM) mode with the + * appropriate direction mask (H2C, C2H, or both). + * 4. Start the queue pair so DMA transfers can be issued. + * 5. Obtain a file descriptor (O_CLOEXEC) from the QDMA driver for the + * queue; this fd is later passed to the client for data transfer. + * + * On any failure, cleanup_buffer() is called which safely tears down + * whichever resources were successfully acquired (using the allocation_valid + * and qpair_created flags to track partial progress). + * + * @return 0 on success, -1 on failure (errno set, buffer cleaned up). + */ +static int buffer_init(struct buffer *buf, + struct slash_qdma *qdma, + struct device_memory_map *map, + enum allocation_type alloc_type, + enum vrtd_alloc_dir alloc_dir, + uint64_t size, + uint64_t alloc_arg, + uint64_t client_id, + const struct slash_qdma_qpair_add *qpair_params) +{ + if (buf == NULL) { + errno = EINVAL; + LOG(LOG_ERR, "Failed to initialize buffer: invalid output pointer"); + return -1; + } + + /* Zero-initialise all fields so cleanup_buffer() can safely inspect + * the flags (allocation_valid, qpair_created) on early failure. */ + *buf = (struct buffer) { + .qdma = qdma, + .map = map, + .alloc_type = alloc_type, + .alloc_arg = alloc_arg, + .alloc_dir = alloc_dir, + .client_id = client_id, + .addr = 0, + .size = 0, + .qid = 0, + .fd = -1, + .allocation_valid = false, + .qpair_created = false, + }; + + if (qdma == NULL || map == NULL || size == 0 || client_id == 0) { + errno = EINVAL; + LOG( + LOG_ERR, + "Failed to initialize buffer: invalid arguments (qdma=%p map=%p size=%llu client_id=%llu)", + (void *)qdma, + (void *)map, + (unsigned long long)size, + (unsigned long long)client_id + ); + goto fail; + } + + /* Map the vrtd allocation direction enum to QDMA hardware direction flags. */ + uint32_t dir_mask = 0; + switch (alloc_dir) { + case VRTD_ALLOC_DIR_BIDIRECTIONAL: + dir_mask = VRTD_QDMA_DIR_H2C | VRTD_QDMA_DIR_C2H; + break; + case VRTD_ALLOC_DIR_HOST_TO_DEVICE: + dir_mask = VRTD_QDMA_DIR_H2C; + break; + case VRTD_ALLOC_DIR_DEVICE_TO_HOST: + dir_mask = VRTD_QDMA_DIR_C2H; + break; + default: + errno = EINVAL; + LOG( + LOG_ERR, + "Failed to initialize buffer: invalid allocation direction %u", + (unsigned int)alloc_dir + ); + goto fail; + } + + /* Step 1: Reserve device memory subregions from the allocator. + * alloc_size may be rounded up to the next 64 MiB boundary. */ + uint64_t alloc_size = size; + uint64_t alloc_addr = 0; + enum allocation_result ares = device_memory_map_allocate( + map, + alloc_type, + &alloc_size, + alloc_arg, + client_id, + &alloc_addr + ); + if (ares != ALLOCATION_RESULT_SUCCESS) { + errno = (ares == ALLOCATION_RESULT_NO_MEMORY) ? ENOMEM : EINVAL; + LOG( + LOG_ERR, + "Failed to allocate device memory for buffer (result=%d alloc_type=%u size=%llu alloc_arg=%llu client_id=%llu): %m", + (int)ares, + (unsigned int)alloc_type, + (unsigned long long)size, + (unsigned long long)alloc_arg, + (unsigned long long)client_id + ); + goto fail; + } + + buf->addr = alloc_addr; + buf->size = alloc_size; + buf->allocation_valid = true; + + /* Step 2: Configure and create a QDMA queue pair. If the caller + * supplied custom qpair parameters (e.g. streaming mode), use those; + * otherwise default to memory-mapped mode with the smallest ring size. */ + struct slash_qdma_qpair_add qpair = {0}; + if (qpair_params != NULL) { + qpair = *qpair_params; + } else { + qpair.mode = VRTD_QDMA_Q_MODE_MM; + qpair.h2c_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.c2h_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.cmpt_ring_sz = VRTD_QDMA_RING_SZ_IDX; + } + qpair.dir_mask = dir_mask; + qpair.size = sizeof(qpair); + + if (slash_qdma_qpair_add(qdma, &qpair) != 0) { + LOG(LOG_ERR, "Failed to add buffer qpair: %m"); + goto fail; + } + + buf->qid = qpair.qid; + buf->qpair_created = true; + + /* Step 3: Start the queue pair so DMA transfers can be issued. */ + if (slash_qdma_qpair_start(qdma, buf->qid) != 0) { + LOG(LOG_ERR, "Failed to start buffer qpair %u: %m", buf->qid); + goto fail; + } + + /* Step 4: Obtain a file descriptor for the queue. The client will use + * this fd (passed over the Unix socket via SCM_RIGHTS) to perform + * read/write/mmap against the QDMA queue. */ + int fd = slash_qdma_qpair_get_fd(qdma, buf->qid, O_CLOEXEC); + if (fd < 0) { + LOG(LOG_ERR, "Failed to get fd for buffer qpair %u: %m", buf->qid); + goto fail; + } + buf->fd = fd; + + LOG(LOG_DEBUG, "Buffer initialized addr=0x%llx size=%llu qid=%u", (unsigned long long)buf->addr, (unsigned long long)buf->size, buf->qid); + return 0; + +fail: + cleanup_buffer(buf); + return -1; +} + +/** + * Allocate and fully initialise a new buffer. + * + * This is the primary public entry point. It heap-allocates a struct buffer, + * then delegates to buffer_init() which acquires the device memory, QDMA + * qpair, and file descriptor. On failure the buffer is freed and NULL is + * returned. + * + * @return Heap-allocated, fully initialised buffer, or NULL on failure. + */ +struct buffer *buffer_create(struct slash_qdma *qdma, + struct device_memory_map *map, + enum allocation_type alloc_type, + enum vrtd_alloc_dir alloc_dir, + uint64_t size, + uint64_t alloc_arg, + uint64_t client_id, + const struct slash_qdma_qpair_add *qpair_params) +{ + struct buffer *buf = calloc(1, sizeof(*buf)); + if (buf == NULL) { + LOG(LOG_ERR, "Failed to allocate buffer: %m"); + return NULL; + } + + if (buffer_init(buf, qdma, map, alloc_type, alloc_dir, size, alloc_arg, client_id, qpair_params) != 0) { + LOG(LOG_ERR, "Failed to initialize buffer: %m"); + return NULL; + } + + return buf; +} + +/** + * Allocate a buffer at a caller-specified device address, bypassing the allocator. + * + * Skips device_memory_map_allocate() and goes directly to QDMA queue pair creation + * with the provided address and size. Sets allocation_valid=false so cleanup_buffer() + * will not attempt to free anything from the memory map. + * + * @return Heap-allocated buffer on success, NULL on failure (errno set). + */ +struct buffer *buffer_create_raw(struct slash_qdma *qdma, + uint64_t phys_addr, + uint64_t size, + enum vrtd_alloc_dir alloc_dir) +{ + if (qdma == NULL || size == 0) { + errno = EINVAL; + return NULL; + } + + uint32_t dir_mask = 0; + switch (alloc_dir) { + case VRTD_ALLOC_DIR_BIDIRECTIONAL: + dir_mask = VRTD_QDMA_DIR_H2C | VRTD_QDMA_DIR_C2H; + break; + case VRTD_ALLOC_DIR_HOST_TO_DEVICE: + dir_mask = VRTD_QDMA_DIR_H2C; + break; + case VRTD_ALLOC_DIR_DEVICE_TO_HOST: + dir_mask = VRTD_QDMA_DIR_C2H; + break; + default: + errno = EINVAL; + LOG(LOG_ERR, "buffer_create_raw: invalid allocation direction %u", (unsigned int)alloc_dir); + return NULL; + } + + struct buffer *buf = calloc(1, sizeof(*buf)); + if (buf == NULL) { + LOG(LOG_ERR, "buffer_create_raw: failed to allocate buffer struct: %m"); + return NULL; + } + + *buf = (struct buffer) { + .qdma = qdma, + .map = NULL, + .alloc_type = 0, + .alloc_arg = 0, + .alloc_dir = alloc_dir, + .client_id = 0, + .addr = phys_addr, + .size = size, + .qid = 0, + .fd = -1, + .allocation_valid = false, /* no allocator reservation to free */ + .qpair_created = false, + }; + + struct slash_qdma_qpair_add qpair = {0}; + qpair.mode = VRTD_QDMA_Q_MODE_MM; + qpair.h2c_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.c2h_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.cmpt_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.dir_mask = dir_mask; + qpair.size = sizeof(qpair); + + if (slash_qdma_qpair_add(qdma, &qpair) != 0) { + LOG(LOG_ERR, "buffer_create_raw: failed to add qpair: %m"); + free(buf); + return NULL; + } + + buf->qid = qpair.qid; + buf->qpair_created = true; + + if (slash_qdma_qpair_start(qdma, buf->qid) != 0) { + LOG(LOG_ERR, "buffer_create_raw: failed to start qpair %u: %m", buf->qid); + cleanup_buffer(buf); + return NULL; + } + + int fd = slash_qdma_qpair_get_fd(qdma, buf->qid, O_CLOEXEC); + if (fd < 0) { + LOG(LOG_ERR, "buffer_create_raw: failed to get fd for qpair %u: %m", buf->qid); + cleanup_buffer(buf); + return NULL; + } + buf->fd = fd; + + LOG(LOG_DEBUG, "Raw buffer created phys_addr=0x%llx size=%llu qid=%u", + (unsigned long long)phys_addr, (unsigned long long)size, buf->qid); + return buf; +} + +/** + * Tear down a buffer and release all associated resources. + * + * Resources are released in reverse acquisition order: + * 1. Close the file descriptor (if open). + * 2. Stop and delete the QDMA queue pair (if created). + * 3. Free the device memory allocation (if valid). + * 4. Zero all fields and free the struct. + * + * Each step is guarded by its corresponding flag (fd >= 0, + * qpair_created, allocation_valid) so this function is safe to call + * after partial initialisation. NULL-safe. + */ +void cleanup_buffer(struct buffer *buf) +{ + if (buf == NULL) { + return; + } + + LOG(LOG_DEBUG, "Freeing buffer addr=0x%llx size=%llu qid=%u", (unsigned long long)buf->addr, (unsigned long long)buf->size, buf->qid); + + /* Close the QDMA queue fd first, before stopping the queue. */ + if (buf->fd >= 0) { + (void) close(buf->fd); + buf->fd = -1; + } + + /* Stop and delete the QDMA queue pair. Errors are logged but + * otherwise ignored -- we are on the teardown path and must continue + * releasing remaining resources. */ + if (buf->qpair_created && buf->qdma != NULL) { + if (slash_qdma_qpair_stop(buf->qdma, buf->qid) != 0) { + LOG( + LOG_WARNING, + "Error stopping buffer qpair %u: %m (ignored)", + buf->qid + ); + } + if (slash_qdma_qpair_del(buf->qdma, buf->qid) != 0) { + LOG( + LOG_WARNING, + "Error deleting buffer qpair %u: %m (ignored)", + buf->qid + ); + } + } + + /* Return the device memory subregions to the allocator. */ + if (buf->allocation_valid && buf->map != NULL) { + if (device_memory_map_free( + buf->map, + buf->alloc_type, + buf->addr, + buf->size, + buf->client_id + ) != ALLOCATION_RESULT_SUCCESS) { + LOG( + LOG_WARNING, + "Error freeing buffer allocation (addr=0x%llx size=%llu): %m (ignored)", + (unsigned long long)buf->addr, + (unsigned long long)buf->size + ); + } + } + + /* Zero all fields so a stale pointer dereference is more likely to + * crash cleanly rather than silently corrupt state. */ + buf->qdma = NULL; + buf->map = NULL; + buf->qpair_created = false; + buf->allocation_valid = false; + buf->addr = 0; + buf->size = 0; + buf->qid = 0; + buf->fd = -1; + + free(buf); +} diff --git a/vrt/vrtd/src/buffer.h b/vrt/vrtd/src/buffer.h new file mode 100644 index 00000000..6834222b --- /dev/null +++ b/vrt/vrtd/src/buffer.h @@ -0,0 +1,153 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file buffer.h + * @brief DMA buffer management for SLASH FPGA devices. + * + * A @c struct @c buffer represents a single DMA-accessible memory region + * allocated from a device's HBM or DDR address space. The lifecycle is: + * + * 1. @b Allocation -- @c buffer_create reserves address space from the + * device memory map, creates a QDMA queue pair for data transfer, + * and records ownership (the client connection ID that requested it). + * 2. @b Use -- The client reads/writes through the QDMA queue pair fd. + * 3. @b Deallocation -- @c cleanup_buffer tears down the QDMA queue pair, + * releases the address-space reservation, and closes the fd. + * + * When a client disconnects, all buffers owned by that connection ID are + * automatically freed. + */ + +#ifndef VRTD_BUFFER_H +#define VRTD_BUFFER_H + +#include +#include + +#include + +#include "allocator.h" +#include "array.h" +#include "vrtd/wire.h" + +/** + * @brief A single DMA buffer allocated on a SLASH FPGA device. + * + * Tracks both the memory allocation metadata and the QDMA queue pair + * used to transfer data to/from the buffer. + */ +struct buffer { + /** @brief QDMA subsystem handle (non-owning, borrowed from the parent device). */ + struct slash_qdma *qdma; /* non-owning */ + /** @brief Device memory map used for address allocation (non-owning). */ + struct device_memory_map *map; /* non-owning */ + /** @brief Memory type of this allocation (DDR, HBM, or HBM_VNOC). */ + enum allocation_type alloc_type; + /** @brief Type-specific allocation argument (e.g. HBM region index for non-VNOC HBM). */ + uint64_t alloc_arg; + /** @brief DMA transfer direction (host-to-card, card-to-host, or bidirectional). */ + enum vrtd_alloc_dir alloc_dir; + /** @brief Connection ID of the client that owns this buffer. + * Used for automatic cleanup on client disconnect. */ + uint64_t client_id; /* owning connection id */ + /** @brief Base device address of the allocated memory region. */ + uint64_t addr; + /** @brief Size of the allocated memory region in bytes (rounded up to subregion granularity). */ + uint64_t size; + /** @brief QDMA queue ID assigned to this buffer's queue pair. */ + uint32_t qid; + /** @brief File descriptor for the QDMA queue pair character device. + * Passed to the client via SCM_RIGHTS for direct data transfer. */ + int fd; + /** @brief True if the address-space allocation in the memory map is valid and must be freed. */ + bool allocation_valid; + /** @brief True if the QDMA queue pair has been created and must be torn down on cleanup. */ + bool qpair_created; +}; + +/** + * @brief Allocate a new DMA buffer on a device. + * + * Reserves address space from the device memory map, creates a QDMA queue + * pair, and starts the queue pair so it is immediately usable. + * + * @param qdma QDMA subsystem handle (borrowed). + * @param map Device memory map for address allocation (borrowed). + * @param alloc_type Memory type to allocate (DDR, HBM, or HBM_VNOC). + * @param alloc_dir DMA transfer direction. + * @param size Requested buffer size in bytes (may be rounded up). + * @param alloc_arg Type-specific argument (HBM region index for non-VNOC HBM). + * @param client_id Connection ID of the owning client. + * @param qpair_params QDMA queue pair configuration parameters. + * @return Heap-allocated buffer on success, NULL on failure. + */ +struct buffer *buffer_create(struct slash_qdma *qdma, + struct device_memory_map *map, + enum allocation_type alloc_type, + enum vrtd_alloc_dir alloc_dir, + uint64_t size, + uint64_t alloc_arg, + uint64_t client_id, + const struct slash_qdma_qpair_add *qpair_params); + +/** + * @brief Allocate a new DMA buffer at a caller-specified device address (bypasses allocator). + * + * Creates a QDMA queue pair at the given physical address without consulting the + * allocator. The caller is responsible for ensuring the address is valid and not + * in use. @c allocation_valid is set to false so cleanup_buffer() will not + * attempt to release anything from the memory map. + * + * @param qdma QDMA subsystem handle (borrowed). + * @param phys_addr Caller-specified device physical address. + * @param size Size in bytes. + * @param alloc_dir DMA transfer direction. + * @return Heap-allocated buffer on success, NULL on failure (errno set). + */ +struct buffer *buffer_create_raw(struct slash_qdma *qdma, + uint64_t phys_addr, + uint64_t size, + enum vrtd_alloc_dir alloc_dir); + +/** + * @brief Release all resources owned by a buffer. + * + * Stops and deletes the QDMA queue pair, frees the address-space reservation, + * and closes the queue pair fd. + * + * @param buf Pointer to the buffer to clean up. May be NULL (no-op). + */ +void cleanup_buffer(struct buffer *buf); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param bufp Address of a @c struct @c buffer pointer. + */ +static inline +void cleanup_bufferp(struct buffer **bufp) +{ + cleanup_buffer(*bufp); + *bufp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(buffer_ptr_array, struct buffer *, cleanup_buffer); + +#endif // VRTD_BUFFER_H diff --git a/vrt/vrtd/src/clock.c b/vrt/vrtd/src/clock.c new file mode 100644 index 00000000..cd908fb3 --- /dev/null +++ b/vrt/vrtd/src/clock.c @@ -0,0 +1,1141 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file clock.c + * @brief Xilinx Clocking Wizard IP configuration via AXI memory-mapped registers. + * + * This module drives the Xilinx Clocking Wizard (MMCM/PLL) IP cores on the + * AMD Alveo V80 FPGA. The clock wizards are accessed through BAR4 of the PCI + * device, with two independent wizard instances mapped at different offsets: + * + * - USER region wizard at BAR4 + 0x00000000 (user-logic clock domain) + * - SERVICE region wizard at BAR4 + 0x00010000 (infrastructure/service clock domain) + * + * Each wizard instance exposes AXI-lite registers for reading the current + * clock configuration and programming new multiplier (M), divider (D), and + * output divider (O) values. The frequency synthesis formula is: + * + * f_VCO = f_primary_in * M / D + * f_out = f_VCO / O_effective + * + * where f_primary_in is the reference clock (100 MHz by default) and + * O_effective accounts for the half-cycle and edge encoding of the output + * divider register fields. + * + * The overall flow for setting a new clock rate is: + * 1. Generate candidate (M, D, O) tuples that produce frequencies close + * to the target, subject to VCO range constraints (2160-4320 MHz). + * 2. Sort candidates by frequency error, then by output divider quality + * (divisible-by-4 preferred, then even, then higher VCO for jitter). + * 3. For each candidate in order, program the M/D/O registers into the + * clock wizard, write common tail configuration, and trigger + * reconfiguration. + * 4. Poll the lock status register until the PLL/MMCM locks or a + * timeout expires. + * 5. On lock, read back the achieved frequency and return it to the caller. + * + * Register offsets and bit field definitions are derived from the Xilinx + * xclk_wiz_hw.h header. Hardware-specific magic values are marked with + * TODO comments for future documentation. + */ + +#include "clock.h" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "utils.h" + +/* + * Xilinx Clocking Wizard AXI register offsets. + * Sourced from xclk_wiz_hw.h in the Xilinx driver headers. + */ +#define XCLK_WIZ_RECONFIG_OFFSET 0x00000014u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG1_OFFSET 0x00000330u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG2_OFFSET 0x00000334u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG3_OFFSET 0x00000338u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG4_OFFSET 0x0000033Cu /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG11_OFFSET 0x00000378u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG12_OFFSET 0x00000380u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG13_OFFSET 0x00000384u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG14_OFFSET 0x00000398u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG15_OFFSET 0x0000039Cu /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG16_OFFSET 0x000003A0u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG17_OFFSET 0x000003A8u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG19_OFFSET 0x000003CCu /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG25_OFFSET 0x000003F0u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG26_OFFSET 0x000003FCu /* TODO(vserbu): explain this register offset/bit field */ + +/* + * Bit masks and shift constants for clock wizard register fields. + */ +#define XCLK_WIZ_LOCK 0x1u /* Lock status bit in REG4 */ +#define XCLK_WIZ_RECONFIG_LOAD 0x1u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_RECONFIG_SADDR 0x2u /* TODO(vserbu): explain this register offset/bit field */ + +#define XCLK_WIZ_REG1_EDGE_MASK 0x100u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_CLKFBOUT_L_MASK 0xFFu /* Low byte: low-time count for feedback divider */ +#define XCLK_WIZ_CLKFBOUT_H_MASK 0xFF00u /* High byte: high-time count for feedback divider */ +#define XCLK_WIZ_CLKFBOUT_H_SHIFT 8u + +#define XCLK_WIZ_EDGE_MASK (1u << 10) /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_P5EN_MASK (1u << 8) /* TODO(vserbu): explain this register offset/bit field */ + +#define XCLK_WIZ_REG3_PREDIV2 (1u << 11) /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG3_USED (1u << 12) /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG3_MX (1u << 9) /* TODO(vserbu): explain this register offset/bit field */ + +#define XCLK_WIZ_REG1_PREDIV2 (1u << 12) /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG1_EN (1u << 9) /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG1_MX (1u << 10) /* TODO(vserbu): explain this register offset/bit field */ + +#define XCLK_WIZ_CLKOUT0_P5EN_SHIFT 13u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT 15u /* TODO(vserbu): explain this register offset/bit field */ +#define XCLK_WIZ_REG12_EDGE_SHIFT 10u /* TODO(vserbu): explain this register offset/bit field */ + +#define XCLK_MHZ 1000000ull + +/* + * Versal MMCM/PLL parameter limits. + * M = feedback multiplier, D = input divider, O = output divider. + * VCO frequency must stay within [VCO_MIN, VCO_MAX] MHz. + */ +#define XCLK_M_MIN 4u +#define XCLK_M_MAX 432u +#define XCLK_D_MIN 1u +#define XCLK_D_MAX 123u +#define XCLK_VCO_MIN 2160u /* Minimum VCO frequency in MHz */ +#define XCLK_VCO_MAX 4320u /* Maximum VCO frequency in MHz */ +#define XCLK_O_MIN 2u +#define XCLK_O_MAX 511u + +/* Default configuration values for the clock driver. */ +#define CLOCK_DRIVER_DEFAULT_PRIM_IN_HZ 100000000u /* 100 MHz reference clock */ +#define CLOCK_DRIVER_DEFAULT_MIN_ERR_HZ 500000u /* 0.5 MHz acceptable error */ +#define CLOCK_DRIVER_DEFAULT_MAX_CANDIDATES 50u /* Max M/D/O tuples to evaluate */ +#define CLOCK_DRIVER_DEFAULT_O_WINDOW 6u /* Search window around estimated O */ +#define CLOCK_DRIVER_DEFAULT_LOCK_TIMEOUT_MS 200u /* PLL lock polling timeout */ + +/** + * Initialize a clock driver struct, opening the BAR4 mapping for register access. + * + * @param clk Pre-allocated clock_driver struct to initialize. + * @param ctl Opened libslash control device (non-owning reference stored). + * @return 0 on success, -1 on error (errno set). + */ +static int clock_driver_init(struct clock_driver *clk, struct slash_ctldev *ctl) +{ + if (clk == NULL || ctl == NULL) { + errno = EINVAL; + return -1; + } + + *clk = (struct clock_driver) { + .ctl = ctl, + .bar = NULL, + .regs = NULL, + .len = 0, + .prim_in_hz = CLOCK_DRIVER_DEFAULT_PRIM_IN_HZ, + .m = 0, + .d = 0, + .o = 0, + .min_err_hz = CLOCK_DRIVER_DEFAULT_MIN_ERR_HZ, + }; + + /* Open BAR4 which contains the clock wizard register windows. */ + clk->bar = slash_bar_file_open(ctl, CLOCK_DRIVER_BAR_NUMBER, O_CLOEXEC); + if (clk->bar == NULL) { + return -1; + } + + /* Map the BAR into the process address space for direct MMIO register access. */ + clk->regs = (volatile uint32_t *) clk->bar->map; + clk->len = clk->bar->len; + if (clk->regs == NULL || clk->len == 0) { + return -1; + } + + return 0; +} + +/** + * Allocate and initialize a clock driver instance. + * + * Opens BAR4 on the device referenced by @p ctl and prepares the driver + * for clock frequency queries and programming. + * + * @param ctl Opened libslash control device. + * @return Heap-allocated clock_driver on success, NULL on error (logged). + * Caller must free with cleanup_clock_driver(). + */ +struct clock_driver *clock_driver_create(struct slash_ctldev *ctl) +{ + struct clock_driver *clk = calloc(1, sizeof(*clk)); + if (clk == NULL) { + LOG(LOG_ERR, "Failed to allocate clock driver: %m"); + return NULL; + } + + if (clock_driver_init(clk, ctl) != 0) { + LOG(LOG_ERR, "Failed to initialize clock driver: %m"); + cleanup_clock_driver(clk); + return NULL; + } + + return clk; +} + +/** + * Destroy a clock driver, closing its BAR mapping and freeing memory. + * + * Safe to call with NULL (no-op). The ctl pointer is non-owning and + * is simply cleared without being closed. + * + * @param clk Clock driver to destroy, or NULL. + */ +void cleanup_clock_driver(struct clock_driver *clk) +{ + if (clk == NULL) { + return; + } + + if (clk->bar != NULL) { + (void) slash_bar_file_close(clk->bar); + clk->bar = NULL; + } + + clk->regs = NULL; + clk->len = 0; + clk->ctl = NULL; + + free(clk); +} + +/** + * Validate that a 32-bit register access at @p offset is within the + * mapped BAR region. + * + * @return 0 if in bounds, -1 with errno set on error. + */ +static int clock_driver_check_bounds(const struct clock_driver *clk, uint32_t offset) +{ + if (clk == NULL || clk->regs == NULL) { + errno = EINVAL; + return -1; + } + if (offset + sizeof(uint32_t) > clk->len) { + errno = EOVERFLOW; + return -1; + } + return 0; +} + +/** + * Read a 32-bit register from the clock wizard BAR mapping. + * + * @param clk Clock driver with valid regs pointer. + * @param offset Byte offset into the BAR (converted to uint32_t index internally). + * @return The 32-bit register value. + */ +static inline uint32_t clock_driver_r32(struct clock_driver *clk, uint32_t offset) +{ + return clk->regs[offset / sizeof(uint32_t)]; +} + +/** + * Write a 32-bit value to a clock wizard register in the BAR mapping. + * + * @param clk Clock driver with valid regs pointer. + * @param offset Byte offset into the BAR. + * @param value Value to write. + */ +static inline void clock_driver_w32(struct clock_driver *clk, uint32_t offset, uint32_t value) +{ + clk->regs[offset / sizeof(uint32_t)] = value; +} + +/** + * Compute the absolute BAR offset for a register within a given clock + * wizard instance. + * + * @param wizard_offset Base offset of the wizard (USER or SERVICE region). + * @param reg_offset Register offset within the wizard. + * @return Combined byte offset into the BAR. + */ +static inline uint32_t clock_driver_reg(uint32_t wizard_offset, uint32_t reg_offset) +{ + return wizard_offset + reg_offset; +} + +/** + * Check that the entire register range of a clock wizard instance + * (up through REG26, the highest used offset) fits within the BAR mapping. + */ +static int clock_driver_check_wizard_bounds(const struct clock_driver *clk, uint32_t wizard_offset) +{ + return clock_driver_check_bounds(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG26_OFFSET)); +} + +/** + * Read the current VCO frequency from the clock wizard registers. + * + * Computes VCO frequency as: + * f_VCO = f_primary_in * M / D + * + * where M (multiplier) is decoded from REG1/REG2 (feedback path) and + * D (input divider) is decoded from REG12/REG13. + * + * The multiplier and divider are each encoded as a pair of low-time and + * high-time counts plus an edge bit: + * effective_value = low_count + high_count + edge_bit + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance in BAR4. + * @return VCO frequency in Hz. + */ +static uint64_t clock_driver_get_vco_hz(struct clock_driver *clk, uint32_t wizard_offset) +{ + /* Read the multiplier (M) from REG1 (edge bit) and REG2 (low/high counts). */ + uint32_t reg = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG1_OFFSET)); + uint32_t edge = (reg & XCLK_WIZ_REG1_EDGE_MASK) ? 1u : 0u; /* TODO(vserbu): explain this register offset/bit field */ + + reg = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG2_OFFSET)); + uint32_t low = reg & XCLK_WIZ_CLKFBOUT_L_MASK; + uint32_t high = (reg & XCLK_WIZ_CLKFBOUT_H_MASK) >> XCLK_WIZ_CLKFBOUT_H_SHIFT; + uint32_t mult = low + high + edge; + if (mult == 0) { + mult = 1; + } + + /* Read the input divider (D) from REG13 (low/high counts) and REG12 (edge bit). */ + reg = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG13_OFFSET)); + low = reg & XCLK_WIZ_CLKFBOUT_L_MASK; + high = (reg & XCLK_WIZ_CLKFBOUT_H_MASK) >> XCLK_WIZ_CLKFBOUT_H_SHIFT; + + reg = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG12_OFFSET)); + edge = (reg & XCLK_WIZ_EDGE_MASK) ? 1u : 0u; /* TODO(vserbu): explain this register offset/bit field */ + + uint32_t div = low + high + edge; + if (div == 0) { + div = 1; + } + + /* f_VCO = f_primary_in * M / D */ + return ((uint64_t)clk->prim_in_hz * mult) / div; +} + +/** + * Read the current output clock rate for a specific clock output. + * + * Computes: + * f_out = f_VCO / O_effective + * + * The output divider (O) is read from a per-clock-output "leaf" register + * pair. The effective output divider accounts for prediv2, p5en, and edge + * encoding: + * O_effective = (prediv + 1) * (high + low + edge) + (prediv * p5en) + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance. + * @param clock_id Output clock index (0-based). Outputs 0-2 use REG3-based + * offsets; outputs 3+ use REG19-based offsets. + * @return Output frequency in Hz. + */ +static uint64_t clock_driver_get_rate_hz(struct clock_driver *clk, uint32_t wizard_offset, uint32_t clock_id) +{ + uint64_t fvco = clock_driver_get_vco_hz(clk, wizard_offset); + + /* + * Compute the register offset for this clock output's leaf divider. + * Clock outputs 0-2 are packed starting at REG3 (8 bytes apart); + * clock outputs 3+ start at REG19 (also 8 bytes apart). + */ + uint32_t leaf_off = (clock_id < 3) + ? (XCLK_WIZ_REG3_OFFSET + clock_id * 8u) + : (XCLK_WIZ_REG19_OFFSET + clock_id * 8u); + uint32_t reg_off = clock_driver_reg(wizard_offset, leaf_off); + + /* First register of the leaf pair: edge, p5en, prediv2 flags. */ + uint32_t reg = clock_driver_r32(clk, reg_off); + uint32_t edge = (reg & (1u << XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT)) ? 1u : 0u; /* TODO(vserbu): explain this register offset/bit field */ + uint32_t p5en = (reg & XCLK_WIZ_P5EN_MASK) ? 1u : 0u; /* TODO(vserbu): explain this register offset/bit field */ + uint32_t prediv = (reg & XCLK_WIZ_REG3_PREDIV2) ? 1u : 0u; /* TODO(vserbu): explain this register offset/bit field */ + + /* Second register of the leaf pair: low-time and high-time counts. */ + uint32_t reg2 = clock_driver_r32(clk, reg_off + 4u); + uint32_t low = reg2 & XCLK_WIZ_CLKFBOUT_L_MASK; + uint32_t high = (reg2 & XCLK_WIZ_CLKFBOUT_H_MASK) >> XCLK_WIZ_CLKFBOUT_H_SHIFT; + + /* + * Decode the effective output divider from the register fields. + * leaf = high_count + low_count + edge + * divo = (prediv + 1) * leaf + (prediv * p5en) + */ + uint32_t leaf = high + low + edge; + uint32_t divo = (prediv + 1u) * leaf + (prediv * p5en); + if (divo == 0) { + divo = 1; + } + + return fvco / divo; +} + +/** + * Compute the effective output divider that will be produced by + * programming a given O value into the clock wizard registers. + * + * This mirrors the encoding logic in clock_driver_update_o(): the O value + * is decomposed into high_time, edge, and p5en fields, then the effective + * divider is reconstructed as it would be read back from hardware: + * high_time = O / 4 + * edge = O % 2 + * p5en = (O % 4 <= 1) ? 0 : 1 + * leaf = high_time * 2 + edge + * divo = 2 * leaf + p5en + * + * @param o Raw output divider value (clamped to XCLK_O_MAX). + * @return Effective divider ratio. + */ +static uint32_t clock_driver_effective_divo_from_o(uint32_t o) +{ + if (o > XCLK_O_MAX) { + o = XCLK_O_MAX; + } + + uint32_t high_time = o / 4u; + uint32_t edge = o % 2u; + uint32_t p5en = ((o % 4u) <= 1u) ? 0u : 1u; + uint32_t leaf = (high_time * 2u) + edge; + uint32_t divo = (2u * leaf) + p5en; + if (divo == 0) { + divo = 1u; + } + + return divo; +} + +/** + * Log the current state of all relevant clock wizard registers for debugging. + * + * Reads and logs the multiplier, divider, leaf output, status, and + * reconfiguration registers, along with computed VCO and output frequencies. + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance. + * @param clock_id Output clock index being inspected. + * @param stage Human-readable label for the log entry (e.g., "before_program"). + */ +static void clock_driver_log_state( + struct clock_driver *clk, + uint32_t wizard_offset, + uint32_t clock_id, + const char *stage +) +{ + uint32_t leaf_off = (clock_id < 3) + ? (XCLK_WIZ_REG3_OFFSET + clock_id * 8u) + : (XCLK_WIZ_REG19_OFFSET + clock_id * 8u); + uint32_t leaf_reg_off = clock_driver_reg(wizard_offset, leaf_off); + + uint32_t reg1 = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG1_OFFSET)); + uint32_t reg2 = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG2_OFFSET)); + uint32_t reg12 = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG12_OFFSET)); + uint32_t reg13 = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG13_OFFSET)); + uint32_t leaf0 = clock_driver_r32(clk, leaf_reg_off); + uint32_t leaf1 = clock_driver_r32(clk, leaf_reg_off + 4u); + uint32_t status = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG4_OFFSET)); + uint32_t reconfig = clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_RECONFIG_OFFSET)); + + uint64_t fvco_hz = clock_driver_get_vco_hz(clk, wizard_offset); + uint64_t rate_hz = clock_driver_get_rate_hz(clk, wizard_offset, clock_id); + + LOG( + LOG_INFO, + "clock_driver[%s]: wiz=0x%08x clk=%u prim_in_hz=%u fvco_hz=%" PRIu64 + " rate_hz=%" PRIu64 " status=0x%08x reconfig=0x%08x reg1=0x%08x reg2=0x%08x" + " reg12=0x%08x reg13=0x%08x leaf0=0x%08x leaf1=0x%08x", + stage, + wizard_offset, + clock_id, + clk->prim_in_hz, + fvco_hz, + rate_hz, + status, + reconfig, + reg1, + reg2, + reg12, + reg13, + leaf0, + leaf1 + ); +} + +/** + * Program the output divider (O) registers for a specific clock output. + * + * Encodes clk->o into the leaf register pair for clock_id: + * - First register: control flags (PREDIV2, USED, MX) and edge/p5 encoding. + * - Second register: high_time in both low and high bytes. + * + * @param clk Clock driver with clk->o set to the desired O value. + * @param wizard_offset Base offset of the wizard instance. + * @param clock_id Output clock index. + */ +static void clock_driver_update_o(struct clock_driver *clk, uint32_t wizard_offset, uint32_t clock_id) +{ + uint32_t o = clk->o; + if (o > XCLK_O_MAX) { + o = XCLK_O_MAX; + } + + /* Compute register offset for this clock output's leaf divider pair. */ + uint32_t leaf_off = (clock_id < 3) + ? (XCLK_WIZ_REG3_OFFSET + clock_id * 8u) + : (XCLK_WIZ_REG19_OFFSET + clock_id * 8u); + uint32_t reg_off = clock_driver_reg(wizard_offset, leaf_off); + + /* Encode O into high_time, div_edge, p5_enable, and p5f_edge fields. */ + uint32_t high_time = o / 4u; + uint32_t reg = XCLK_WIZ_REG3_PREDIV2 | XCLK_WIZ_REG3_USED | XCLK_WIZ_REG3_MX; /* TODO(vserbu): explain this register offset/bit field */ + + uint32_t div_edge = ((o % 4u) <= 1u) ? 0u : 1u; + reg |= (div_edge << 8u); /* TODO(vserbu): explain this register offset/bit field */ + + uint32_t p5f_edge = o % 2u; + uint32_t p5_enable = o % 2u; + reg |= (p5_enable << XCLK_WIZ_CLKOUT0_P5EN_SHIFT) | + (p5f_edge << XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT); /* TODO(vserbu): explain this register offset/bit field */ + + clock_driver_w32(clk, reg_off, reg); + clock_driver_w32(clk, reg_off + 4u, (high_time | (high_time << 8u))); /* TODO(vserbu): explain this register offset/bit field */ +} + +/** + * Program the input divider (D) registers of the clock wizard. + * + * Encodes clk->d into REG12 (edge bit) and REG13 (high/low time counts). + * + * @param clk Clock driver with clk->d set to the desired D value. + * @param wizard_offset Base offset of the wizard instance. + */ +static void clock_driver_update_d(struct clock_driver *clk, uint32_t wizard_offset) +{ + uint32_t d = clk->d; + uint32_t high_time = d / 2u; + + uint32_t reg = 0; + reg &= ~(1u << XCLK_WIZ_REG12_EDGE_SHIFT); /* TODO(vserbu): explain this register offset/bit field */ + uint32_t div_edge = d % 2u; + reg |= (div_edge << XCLK_WIZ_REG12_EDGE_SHIFT); + + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG12_OFFSET), reg); + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG13_OFFSET), (high_time | (high_time << 8u))); /* TODO(vserbu): explain this register offset/bit field */ +} + +/** + * Program the feedback multiplier (M) registers of the clock wizard. + * + * Encodes clk->m into REG25 (clear), REG2 (high/low time counts), and + * REG1 (control flags and edge bit). + * + * @param clk Clock driver with clk->m set to the desired M value. + * @param wizard_offset Base offset of the wizard instance. + */ +static void clock_driver_update_m(struct clock_driver *clk, uint32_t wizard_offset) +{ + uint32_t m = clk->m; + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG25_OFFSET), 0); /* TODO(vserbu): explain this register offset/bit field */ + + uint32_t div_edge = m % 2u; + uint32_t high_time = m / 2u; + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG2_OFFSET), (high_time | (high_time << 8u))); /* TODO(vserbu): explain this register offset/bit field */ + + uint32_t reg = XCLK_WIZ_REG1_PREDIV2 | XCLK_WIZ_REG1_EN | XCLK_WIZ_REG1_MX; /* TODO(vserbu): explain this register offset/bit field */ + if (div_edge) { + reg |= (1u << 8u); /* TODO(vserbu): explain this register offset/bit field */ + } else { + reg &= ~(1u << 8u); /* TODO(vserbu): explain this register offset/bit field */ + } + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG1_OFFSET), reg); +} + +/** + * Write the common tail registers required after programming M, D, and O. + * + * These register values are fixed/magic configuration needed by the Xilinx + * Clocking Wizard to finalize a reconfiguration sequence. They configure + * filter and lock detection parameters for the MMCM/PLL. + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance. + */ +static void clock_driver_program_common_tail(struct clock_driver *clk, uint32_t wizard_offset) +{ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG11_OFFSET), 0x2Eu); /* TODO(vserbu): explain this register offset/bit field */ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG14_OFFSET), 0xE80u); /* TODO(vserbu): explain this register offset/bit field */ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG15_OFFSET), 0x4271u); /* TODO(vserbu): explain this register offset/bit field */ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG16_OFFSET), 0x43E9u); /* TODO(vserbu): explain this register offset/bit field */ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG17_OFFSET), 0x001Cu); /* TODO(vserbu): explain this register offset/bit field */ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG26_OFFSET), 0x0001u); /* TODO(vserbu): explain this register offset/bit field */ +} + +/** + * Trigger the clock wizard's dynamic reconfiguration sequence. + * + * Writes the LOAD and SADDR bits to the reconfiguration register, which + * causes the wizard to latch the newly programmed M/D/O values and begin + * the PLL/MMCM re-lock process. + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance. + */ +static void clock_driver_trigger_reconfig(struct clock_driver *clk, uint32_t wizard_offset) +{ + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_RECONFIG_OFFSET), + (XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR)); +} + +/** + * Poll the clock wizard lock status register until the PLL/MMCM locks + * or the timeout expires. + * + * Uses CLOCK_MONOTONIC to measure elapsed time. Polls with 100 us sleep + * intervals between reads. + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance. + * @param timeout_ms Maximum time to wait for lock, in milliseconds. + * @return 0 if lock acquired, -1 on timeout (errno = ETIMEDOUT) or clock error. + */ +static int clock_driver_wait_for_lock(struct clock_driver *clk, uint32_t wizard_offset, uint32_t timeout_ms) +{ + struct timespec start; + if (clock_gettime(CLOCK_MONOTONIC, &start) != 0) { + return -1; + } + + for (;;) { + /* Check the LOCK bit in the status register (REG4). */ + if ((clock_driver_r32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG4_OFFSET)) & XCLK_WIZ_LOCK) != 0u) { + return 0; + } + + /* Compute elapsed time and check against timeout. */ + struct timespec now; + if (clock_gettime(CLOCK_MONOTONIC, &now) != 0) { + return -1; + } + + time_t sec = now.tv_sec - start.tv_sec; + long nsec_signed = now.tv_nsec - start.tv_nsec; + if (nsec_signed < 0) { + sec -= 1; + nsec_signed += 1000000000l; + } + + uint64_t elapsed_ms = (uint64_t)sec * 1000ull; + uint64_t nsec = (uint64_t)nsec_signed; + elapsed_ms += nsec / 1000000ull; + + if (elapsed_ms > timeout_ms) { + errno = ETIMEDOUT; + return -1; + } + + (void) usleep(100); + } +} + +/** + * Program the M, D, and O values into the clock wizard, trigger + * reconfiguration, and wait for PLL/MMCM lock. + * + * This is the core "apply configuration" routine. It writes all divider + * registers, writes the common tail configuration, triggers reconfiguration, + * then polls for lock. + * + * @param clk Clock driver with m, d, o fields set. + * @param wizard_offset Base offset of the wizard instance. + * @param clock_id Output clock index. + * @param timeout_ms Lock timeout in milliseconds. + * @param ok Output: set to 0 on success, remains -1 on failure. + * @return Achieved output frequency in Hz (only valid when *ok == 0). + */ +static uint64_t clock_driver_program_mdo_and_reconfig( + struct clock_driver *clk, + uint32_t wizard_offset, + uint32_t clock_id, + uint32_t timeout_ms, + int *ok +) +{ + *ok = -1; + + clock_driver_w32(clk, clock_driver_reg(wizard_offset, XCLK_WIZ_REG25_OFFSET), 0); /* TODO(vserbu): explain this register offset/bit field */ + + /* Program output divider, input divider, and feedback multiplier. */ + clock_driver_update_o(clk, wizard_offset, clock_id); + clock_driver_update_d(clk, wizard_offset); + clock_driver_update_m(clk, wizard_offset); + clock_driver_program_common_tail(clk, wizard_offset); + + /* Trigger the dynamic reconfiguration and wait for PLL lock. */ + clock_driver_trigger_reconfig(clk, wizard_offset); + + if (clock_driver_wait_for_lock(clk, wizard_offset, timeout_ms) != 0) { + return 0; + } + + *ok = 0; + return clock_driver_get_rate_hz(clk, wizard_offset, clock_id); +} + +/** + * A candidate (M, D, O) tuple for clock frequency synthesis. + * + * Used during the search for the best divider configuration to reach a + * target frequency. Candidates are ranked by frequency error, then by + * output divider quality (divisible by 4, then even), then by VCO frequency. + */ +struct clock_candidate { + uint64_t diff_hz; /* Absolute frequency error: |achieved - target| */ + uint64_t achieved_hz; /* Frequency this candidate produces */ + uint32_t m; /* Feedback multiplier */ + uint32_t d; /* Input divider */ + uint32_t o; /* Output divider */ + uint64_t fvco_hz; /* VCO frequency for this M/D combination */ +}; + +/** + * Compare two clock candidates for sorting. + * + * Ordering priority (best first): + * 1. Smallest frequency error (diff_hz). + * 2. O divisible by 4 (stable, easy-to-represent output divisors). + * 3. Even O values (better duty cycle symmetry). + * 4. Higher VCO frequency (better jitter performance). + * 5. Smaller O value (tie-breaker). + * + * @return Negative if a < b, positive if a > b, 0 if equal. + */ +static int clock_driver_candidate_cmp( + const struct clock_candidate *a, + const struct clock_candidate *b +) +{ + if (a->diff_hz != b->diff_hz) { + return (a->diff_hz < b->diff_hz) ? -1 : 1; + } + + // Prefer o divisible by 4 (stable/easy-to-represent output divisors). + uint32_t ao4 = (a->o % 4u == 0u) ? 0u : 1u; + uint32_t bo4 = (b->o % 4u == 0u) ? 0u : 1u; + if (ao4 != bo4) { + return (ao4 < bo4) ? -1 : 1; + } + + // Then prefer even o, then higher VCO for better jitter behavior. + uint32_t ao2 = (a->o % 2u == 0u) ? 0u : 1u; + uint32_t bo2 = (b->o % 2u == 0u) ? 0u : 1u; + if (ao2 != bo2) { + return (ao2 < bo2) ? -1 : 1; + } + + if (a->fvco_hz != b->fvco_hz) { + return (a->fvco_hz > b->fvco_hz) ? -1 : 1; + } + + if (a->o != b->o) { + return (a->o < b->o) ? -1 : 1; + } + + return 0; +} + +/** + * Generate and rank candidate (M, D, O) tuples for a target frequency. + * + * Exhaustively searches over all valid M and D values. For each (M, D) pair + * that produces a VCO within the allowed range [2160, 4320] MHz, it evaluates + * O values in a window around the estimated optimal O. Candidates are + * maintained in a bounded buffer (max_candidates), replacing the worst + * candidate when the buffer is full and a better one is found. + * + * After generation, candidates are sorted best-first using + * clock_driver_candidate_cmp() (selection sort). + * + * The frequency for each candidate is computed as: + * achieved_hz = (prim_in_hz * M / D) / O + * + * @param clk Clock driver (provides prim_in_hz). + * @param target_hz Desired output frequency in Hz. + * @param cands Output array of candidates (caller-allocated). + * @param max_candidates Maximum number of candidates to retain. + * @return Number of candidates generated (0 if none found). + */ +static size_t clock_driver_generate_candidates( + struct clock_driver *clk, + uint32_t target_hz, + struct clock_candidate *cands, + size_t max_candidates +) +{ + if (clk == NULL || target_hz == 0 || cands == NULL || max_candidates == 0) { + return 0; + } + + uint64_t vco_min_hz = (uint64_t)XCLK_VCO_MIN * XCLK_MHZ; + uint64_t vco_max_hz = (uint64_t)XCLK_VCO_MAX * XCLK_MHZ; + size_t count = 0; + + /* Iterate over all valid (M, D) pairs. */ + for (uint32_t m = XCLK_M_MIN; m <= XCLK_M_MAX; ++m) { + uint64_t numerator = (uint64_t)clk->prim_in_hz * m; + for (uint32_t d = XCLK_D_MIN; d <= XCLK_D_MAX; ++d) { + uint64_t fvco_hz = numerator / d; + + /* Skip (M, D) pairs whose VCO falls outside allowed range. */ + if (fvco_hz < vco_min_hz || fvco_hz > vco_max_hz) { + continue; + } + + /* + * Estimate the ideal O for this VCO, then search a window around it. + * o_est = round(f_VCO / target_hz) + */ + uint64_t o_est = (fvco_hz + target_hz / 2u) / target_hz; + if (o_est < XCLK_O_MIN) { + o_est = XCLK_O_MIN; + } else if (o_est > XCLK_O_MAX) { + o_est = XCLK_O_MAX; + } + + uint32_t o_lo = (o_est > CLOCK_DRIVER_DEFAULT_O_WINDOW) + ? (uint32_t)(o_est - CLOCK_DRIVER_DEFAULT_O_WINDOW) + : XCLK_O_MIN; + if (o_lo < XCLK_O_MIN) { + o_lo = XCLK_O_MIN; + } + + uint32_t o_hi = (uint32_t)(o_est + CLOCK_DRIVER_DEFAULT_O_WINDOW); + if (o_hi > XCLK_O_MAX) { + o_hi = XCLK_O_MAX; + } + + for (uint32_t o = o_lo; o <= o_hi; ++o) { + uint64_t achieved_hz = fvco_hz / o; + uint64_t diff_hz = (achieved_hz > target_hz) + ? (achieved_hz - target_hz) + : (target_hz - achieved_hz); + struct clock_candidate candidate = { + .diff_hz = diff_hz, + .achieved_hz = achieved_hz, + .m = m, + .d = d, + .o = o, + .fvco_hz = fvco_hz, + }; + + /* If buffer has room, just append. */ + if (count < max_candidates) { + cands[count++] = candidate; + continue; + } + + /* Buffer full: replace the worst candidate if this one is better. */ + size_t worst_index = 0; + for (size_t i = 1; i < count; ++i) { + if (clock_driver_candidate_cmp(&cands[worst_index], &cands[i]) < 0) { + worst_index = i; + } + } + if (clock_driver_candidate_cmp(&candidate, &cands[worst_index]) < 0) { + cands[worst_index] = candidate; + } + } + } + } + + /* Sort candidates best-first (selection sort). */ + for (size_t i = 0; i < count; ++i) { + for (size_t j = i + 1; j < count; ++j) { + if (clock_driver_candidate_cmp(&cands[j], &cands[i]) < 0) { + struct clock_candidate tmp = cands[i]; + cands[i] = cands[j]; + cands[j] = tmp; + } + } + } + + return count; +} + +/** + * Attempt to set the clock output to a target frequency. + * + * Generates candidate (M, D, O) tuples, then tries each in ranked order: + * programs the wizard, triggers reconfiguration, and waits for lock. The + * first candidate that achieves lock is accepted and its achieved frequency + * is written back to *rate_hz_inout. + * + * @param clk Clock driver. + * @param wizard_offset Base offset of the wizard instance (USER or SERVICE). + * @param clock_id Output clock index. + * @param rate_hz_inout On entry: target frequency in Hz. On success: achieved + * frequency in Hz. + * @return 0 on success, -1 on error (no valid candidates or all timed out). + */ +static int clock_driver_try_set_rate_hz( + struct clock_driver *clk, + uint32_t wizard_offset, + uint32_t clock_id, + uint32_t *rate_hz_inout +) +{ + if (clk == NULL || rate_hz_inout == NULL || *rate_hz_inout == 0) { + errno = EINVAL; + LOG( + LOG_WARNING, + "clock_driver: invalid set_rate arguments (clk=%p rate_ptr=%p rate_hz=%u)", + (void *)clk, + (void *)rate_hz_inout, + (rate_hz_inout != NULL) ? *rate_hz_inout : 0u + ); + return -1; + } + + struct clock_candidate candidates[CLOCK_DRIVER_DEFAULT_MAX_CANDIDATES]; + size_t count = clock_driver_generate_candidates( + clk, + *rate_hz_inout, + candidates, + CLOCK_DRIVER_DEFAULT_MAX_CANDIDATES + ); + if (count == 0) { + errno = ERANGE; + LOG( + LOG_WARNING, + "clock_driver: failed to calculate divisors for request_hz=%u: %m", + *rate_hz_inout + ); + return -1; + } + + /* Try each candidate in priority order until one achieves PLL lock. */ + for (size_t i = 0; i < count; ++i) { + const struct clock_candidate *cand = &candidates[i]; + clk->m = cand->m; + clk->d = cand->d; + clk->o = cand->o; + + uint64_t predicted_fvco_hz = ((uint64_t)clk->prim_in_hz * clk->m) / clk->d; + uint32_t predicted_divo = clock_driver_effective_divo_from_o(clk->o); + uint64_t predicted_rate_hz = predicted_fvco_hz / predicted_divo; + LOG( + LOG_INFO, + "clock_driver: request_hz=%u trying candidate=%zu/%zu m=%u d=%u o=%u est_hz=%" PRIu64 + " diff_hz=%" PRIu64 " predicted_divo=%u predicted_rate_hz=%" PRIu64, + *rate_hz_inout, + i + 1u, + count, + clk->m, + clk->d, + clk->o, + cand->achieved_hz, + cand->diff_hz, + predicted_divo, + predicted_rate_hz + ); + + clock_driver_log_state(clk, wizard_offset, clock_id, "before_program"); + + int ok = 0; + uint64_t reported = clock_driver_program_mdo_and_reconfig( + clk, wizard_offset, clock_id, CLOCK_DRIVER_DEFAULT_LOCK_TIMEOUT_MS, &ok + ); + + clock_driver_log_state(clk, wizard_offset, clock_id, "after_program"); + + if (ok == 0) { + LOG( + LOG_INFO, + "clock_driver: set_rate request_hz=%u reported_hz=%" PRIu64 + " m=%u d=%u o=%u candidate=%zu/%zu", + *rate_hz_inout, + reported, + clk->m, + clk->d, + clk->o, + i + 1u, + count + ); + *rate_hz_inout = (uint32_t)reported; + return 0; + } + + LOG( + LOG_WARNING, + "clock_driver: lock timeout request_hz=%u candidate=%zu/%zu m=%u d=%u o=%u timeout_ms=%u", + *rate_hz_inout, + i + 1u, + count, + clk->m, + clk->d, + clk->o, + CLOCK_DRIVER_DEFAULT_LOCK_TIMEOUT_MS + ); + } + + errno = ETIMEDOUT; + return -1; +} + +/** + * Get the current clock frequency of the SERVICE region. + * + * The service region wizard is at BAR4 + 0x00010000. This reads the + * output clock rate without modifying any registers. + * + * @param clk Clock driver. + * @param rate_hz_out Receives the current service clock frequency in Hz. + * @return 0 on success, -1 on error. + */ +int clock_driver_get_service_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_out) +{ + if (rate_hz_out == NULL) { + errno = EINVAL; + return -1; + } + if (clock_driver_check_wizard_bounds(clk, CLOCK_DRIVER_SERVICE_REGION_WIZARD_OFFSET) != 0) { + return -1; + } + + uint64_t rate = clock_driver_get_rate_hz( + clk, + CLOCK_DRIVER_SERVICE_REGION_WIZARD_OFFSET, + CLOCK_DRIVER_WIZARD_CLKOUT_ID + ); + *rate_hz_out = (uint32_t)rate; + return 0; +} + +/** + * Set the clock frequency of the SERVICE region. + * + * Programs the service region clock wizard (BAR4 + 0x00010000) to produce + * a frequency as close as possible to the requested rate. + * + * @param clk Clock driver. + * @param rate_hz_inout On entry: desired frequency in Hz. On success: + * actual achieved frequency in Hz. + * @return 0 on success, -1 on error (logged). + */ +int clock_driver_set_service_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_inout) +{ + if (clock_driver_check_wizard_bounds(clk, CLOCK_DRIVER_SERVICE_REGION_WIZARD_OFFSET) != 0) { + LOG(LOG_ERR, "clock_driver: service region wizard bounds check failed: %m"); + return -1; + } + int ret = clock_driver_try_set_rate_hz( + clk, + CLOCK_DRIVER_SERVICE_REGION_WIZARD_OFFSET, + CLOCK_DRIVER_WIZARD_CLKOUT_ID, + rate_hz_inout + ); + if (ret != 0) { + LOG( + LOG_WARNING, + "clock_driver: failed to set service region frequency request_hz=%u: %m", + (rate_hz_inout != NULL) ? *rate_hz_inout : 0u + ); + } + return ret; +} + +/** + * Get the current clock frequency of the USER region. + * + * The user region wizard is at BAR4 + 0x00000000. This reads the + * output clock rate without modifying any registers. + * + * @param clk Clock driver. + * @param rate_hz_out Receives the current user clock frequency in Hz. + * @return 0 on success, -1 on error. + */ +int clock_driver_get_user_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_out) +{ + if (rate_hz_out == NULL) { + errno = EINVAL; + return -1; + } + if (clock_driver_check_wizard_bounds(clk, CLOCK_DRIVER_USER_REGION_WIZARD_OFFSET) != 0) { + return -1; + } + + uint64_t rate = clock_driver_get_rate_hz( + clk, + CLOCK_DRIVER_USER_REGION_WIZARD_OFFSET, + CLOCK_DRIVER_WIZARD_CLKOUT_ID + ); + *rate_hz_out = (uint32_t)rate; + return 0; +} + +/** + * Set the clock frequency of the USER region. + * + * Programs the user region clock wizard (BAR4 + 0x00000000) to produce + * a frequency as close as possible to the requested rate. + * + * @param clk Clock driver. + * @param rate_hz_inout On entry: desired frequency in Hz. On success: + * actual achieved frequency in Hz. + * @return 0 on success, -1 on error (logged). + */ +int clock_driver_set_user_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_inout) +{ + if (clock_driver_check_wizard_bounds(clk, CLOCK_DRIVER_USER_REGION_WIZARD_OFFSET) != 0) { + LOG(LOG_ERR, "clock_driver: user region wizard bounds check failed: %m"); + return -1; + } + int ret = clock_driver_try_set_rate_hz( + clk, + CLOCK_DRIVER_USER_REGION_WIZARD_OFFSET, + CLOCK_DRIVER_WIZARD_CLKOUT_ID, + rate_hz_inout + ); + if (ret != 0) { + LOG( + LOG_WARNING, + "clock_driver: failed to set user region frequency request_hz=%u: %m", + (rate_hz_inout != NULL) ? *rate_hz_inout : 0u + ); + } + return ret; +} diff --git a/vrt/vrtd/src/clock.h b/vrt/vrtd/src/clock.h new file mode 100644 index 00000000..a5ca212c --- /dev/null +++ b/vrt/vrtd/src/clock.h @@ -0,0 +1,162 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file clock.h + * @brief AXI clock wizard driver for SLASH FPGA devices. + * + * The V80 FPGA exposes two independent clock wizard regions inside PCI BAR4: + * - @b User region (offset 0x00000000): controls the user-logic clock. + * - @b Service region (offset 0x00010000): controls the service/infrastructure clock. + * + * Each clock wizard is an AXI-mapped Xilinx Clocking Wizard IP core that + * provides a programmable output frequency derived from a fixed primary + * input clock. The driver computes optimal MMCM divider settings (M, D, O) + * to achieve the requested frequency with minimum error. + */ + +#ifndef VRTD_CLOCK_H +#define VRTD_CLOCK_H + +#include +#include + +#include + +/** @brief PCI BAR index where the clock wizard registers are located. */ +// BAR index used by the clock driver. +#define CLOCK_DRIVER_BAR_NUMBER 4 + +/** + * @name Clock wizard region offsets within BAR4. + * Each region contains the AXI register set for one clock wizard instance. + * @{ + */ +/** @brief Register offset of the user-region clock wizard inside BAR4. */ +// Clock wizard register windows inside BAR4. +#define CLOCK_DRIVER_USER_REGION_WIZARD_OFFSET 0x00000000u +/** @brief Register offset of the service-region clock wizard inside BAR4. */ +#define CLOCK_DRIVER_SERVICE_REGION_WIZARD_OFFSET 0x00010000u +/** @} */ + +/** @brief Output clock index within each wizard (clk_out1 = index 0). */ +// Each wizard exposes clk_out1 as output index 0. +#define CLOCK_DRIVER_WIZARD_CLKOUT_ID 0u + +/** + * @brief Clock driver state for one SLASH FPGA device. + * + * Manages the memory-mapped AXI clock wizard register region and caches + * the MMCM parameters used to synthesize the current output frequency. + */ +struct clock_driver { + /** @brief libslash control device handle (non-owning, borrowed from struct device). */ + struct slash_ctldev *ctl; /* non-owning */ + /** @brief Memory-mapped BAR4 file handle (owning, opened by the clock driver). */ + struct slash_bar_file *bar; /* owning */ + /** @brief Pointer to the memory-mapped clock wizard AXI register bank (volatile for MMIO). */ + volatile uint32_t *regs; + /** @brief Length in bytes of the mapped register region. */ + size_t len; + /** @brief Primary input clock frequency in Hz (fixed, read from hardware). */ + uint32_t prim_in_hz; + /** @brief MMCM feedback multiplier (M value in the clocking equation). */ + uint32_t m; + /** @brief MMCM input divider (D value in the clocking equation). */ + uint32_t d; + /** @brief MMCM output divider (O value in the clocking equation). + * Output frequency = prim_in_hz * M / (D * O). */ + uint32_t o; + /** @brief Minimum frequency error in Hz achieved by the current M/D/O settings. */ + uint32_t min_err_hz; +}; + +/** + * @brief Create and initialize a clock driver for the given device. + * + * Opens BAR4, maps the register region, and reads the primary input + * clock frequency from hardware. + * + * @param ctl libslash control device handle (borrowed, must outlive the clock_driver). + * @return Heap-allocated clock_driver on success, NULL on failure. + */ +struct clock_driver *clock_driver_create(struct slash_ctldev *ctl); + +/** + * @brief Release all resources owned by the clock driver (BAR mapping). + * @param clk Pointer to the clock_driver to clean up. May be NULL (no-op). + */ +void cleanup_clock_driver(struct clock_driver *clk); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param clkp Address of a @c struct @c clock_driver pointer. + */ +static inline +void cleanup_clock_driverp(struct clock_driver **clkp) +{ + cleanup_clock_driver(*clkp); + *clkp = NULL; +} + +/** + * @brief Read the current service-region clock frequency. + * @param clk The clock driver instance. + * @param[out] rate_hz_out Receives the current frequency in Hz. + * @return 0 on success, -1 on error. + */ +int clock_driver_get_service_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_out); + +/** + * @brief Set the service-region clock to the requested frequency. + * + * The driver finds the closest achievable frequency by searching MMCM + * divider space. On return, @p rate_hz_inout is updated to the actual + * frequency achieved (which may differ slightly from the request). + * + * @param clk The clock driver instance. + * @param[in,out] rate_hz_inout On entry, the desired frequency in Hz. + * On exit, the actual frequency achieved. + * @return 0 on success, -1 on error. + */ +int clock_driver_set_service_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_inout); + +/** + * @brief Read the current user-region clock frequency. + * @param clk The clock driver instance. + * @param[out] rate_hz_out Receives the current frequency in Hz. + * @return 0 on success, -1 on error. + */ +int clock_driver_get_user_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_out); + +/** + * @brief Set the user-region clock to the requested frequency. + * + * Behaves identically to @c clock_driver_set_service_region_rate_hz but + * targets the user-region clock wizard. + * + * @param clk The clock driver instance. + * @param[in,out] rate_hz_inout On entry, the desired frequency in Hz. + * On exit, the actual frequency achieved. + * @return 0 on success, -1 on error. + */ +int clock_driver_set_user_region_rate_hz(struct clock_driver *clk, uint32_t *rate_hz_inout); + +#endif // VRTD_CLOCK_H diff --git a/vrt/vrtd/src/config.c b/vrt/vrtd/src/config.c new file mode 100644 index 00000000..c3ee0490 --- /dev/null +++ b/vrt/vrtd/src/config.c @@ -0,0 +1,1460 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file config.c + * @brief INI configuration loader for vrtd role-based access control. + * + * This file implements the configuration subsystem for the V80 Runtime Daemon + * (vrtd). The daemon uses an INI-style configuration file (parsed via inih) to + * define: + * + * - **Roles**: named permission bundles that control what operations a client + * may perform (e.g. query devices, access BARs, perform PCIe hotplug). + * - **Users**: system user accounts mapped (by UID) to one or more roles. + * - **Groups**: system groups mapped (by GID) to one or more roles. + * - **Default user** (wildcard `*`): roles that apply to every client, + * regardless of UID/GID match. + * + * A single client may match multiple roles (via user entry, group entries, and + * the default user). At authorization time the effective permission set is the + * **union** of all matched roles -- i.e. highest privilege wins. Role merging + * is performed by role_merge_add_role() which ORs the boolean permission + * fields. + * + * Configuration loading flow (config_load): + * 1. Determine config file path from $VRTD_CONFIG or the compiled-in + * default (/etc/vrt/vrtd.conf). + * 2. Parse the INI file via inih; the callback dispatches each key/value + * to the appropriate handler based on section type: + * - Top-level `include` / `include-glob`: recursively parse other files. + * - `[role:]`: create / update a role definition. + * - `[user:]` or `[user:*]`: map a user (or wildcard) to roles. + * - `[group:]`: map a group to roles. + * 3. After all files are parsed, resolve the role name strings stored in + * each user/group config to pointers into the role array + * (assign_users_roles / assign_groups_roles). + * + * The config supports circular-include detection via a visited_files list, and + * glob-based includes for drop-in configuration directories. + */ + +#define _GNU_SOURCE + +#define VRTD_DEFAULT_CONFIG_PATH "/etc/vrt/vrtd.conf" + +#include "array.h" +#include "config.h" +#include "utils.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// This is on Ubuntu +static_assert(INI_HANDLER_LINENO == 0, "vrtd does not support INI_HANDLER_LINENO = 1"); + +/** + * Sentinel user name for the default (wildcard) user entry. + * Any client that does not match a specific [user:] section will still + * receive the roles assigned to [user:*]. + */ +static const char DEFAULT_USER_NAME[] = "*"; + +/** + * @brief Transient state carried through a single config_load() invocation. + * + * @param config Pointer to the config being populated. + * @param visited_files Canonical paths of files already parsed, used to + * prevent infinite include cycles. + */ +struct config_parse_state { + struct config *config; + + struct str_array visited_files; +}; + +/* Forward declarations for internal helpers. */ +static int parse_file_glob(struct config_parse_state *state, const char *pattern); +static int resolve_relative_pattern(struct config_parse_state *state, const char *pattern, char **abs_pattern); +static int parse_file(struct config_parse_state *state, const char *path); +static int parse_file_unique(struct config_parse_state *state, const char *path); +static int parse_config_callback(void *user, const char *section, const char *name, const char *value); +static int role_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value); +static int role_add_value(struct role *role, const char *name, const char *value); +static int role_device_find_and_add_value(struct config *config, const char *role_name, const char *dev_selector, const char *name, const char *value); +static int device_policy_add_value(struct device_policy *dp, const char *name, const char *value); +static int user_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value); +static int user_add_value(struct user_config *user, const char *name, const char *value); +static int group_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value); +static int group_add_value(struct group_config *group, const char *name, const char *value); +static int set_user_uid(uid_t *uid, const char *name); +static int set_group_gid(gid_t *gid, const char *name); +static int assign_users_roles(struct config *config); +static int assign_user_roles(struct config *config, struct user_config *user); +static int assign_groups_roles(struct config *config); +static int assign_group_roles(struct config *config, struct group_config *group); +static struct role *role_find_or_create(struct config *config, const char *role_name); +static int normalize_bdf(const char *input, char *out, size_t out_len); +static struct device_policy *find_device_policy(const struct device_policy_ptr_array *policies, const char *bdf); +static int find_or_create_device_policy(struct device_policy_ptr_array *policies, const char *bdf, struct device_policy **out); + +/* ======================================================================== + * Cleanup helpers + * + * These functions are used with the _cleanup_ GCC attribute to provide + * automatic resource cleanup on scope exit (RAII-style). Each frees all + * owned memory within the given struct and NULLs dangling pointers. + * ======================================================================== */ + +/** + * @brief Free all resources owned by a device_policy. + * + * Releases the BDF string and the struct itself. + * + * @param dp Pointer to the device_policy to clean up, or NULL (no-op). + */ +void cleanup_device_policy(struct device_policy *dp) +{ + if (dp == NULL) { + return; + } + + free(dp->bdf); + dp->bdf = NULL; + + free(dp); +} + +/** + * @brief Free all resources owned by a role. + * + * Releases the role name string, the device_policies array, and the role + * struct itself. + * + * @param role Pointer to the role to clean up, or NULL (no-op). + */ +void cleanup_role(struct role *role) +{ + if (role == NULL) { + return; + } + + free(role->name); + role->name = NULL; + + device_policy_ptr_array_free(&role->device_policies); + + free(role); +} + +/** + * @brief Free all resources owned by a user_config. + * + * Releases the user name, the role_names string array (used during parsing), + * the resolved roles reference array, and the struct itself. + * + * @param user Pointer to the user_config to clean up, or NULL (no-op). + */ +void cleanup_user_config(struct user_config *user) +{ + if (user == NULL) { + return; + } + + free(user->name); + user->name = NULL; + + str_array_free(&user->role_names); + role_ref_array_free(&user->roles); + + free(user); +} + +/** + * @brief Free all resources owned by a group_config. + * + * Releases the group name, role_names, resolved roles, and the struct itself. + * + * @param group Pointer to the group_config to clean up, or NULL (no-op). + */ +void cleanup_group_config(struct group_config *group) +{ + if (group == NULL) { + return; + } + + free(group->name); + group->name = NULL; + + str_array_free(&group->role_names); + role_ref_array_free(&group->roles); + + free(group); +} + +/** + * @brief Free all resources owned by a config. + * + * Releases the roles array (which owns the role structs), the default user, + * the users array, and the groups array. + * + * @param config Pointer to the config to clean up, or NULL (no-op). + */ +void cleanup_config(struct config *config) +{ + if (config == NULL) { + return; + } + + role_ptr_array_free(&config->roles); + + cleanup_user_config(config->default_user); + + user_config_ptr_array_free(&config->users); + group_config_ptr_array_free(&config->groups); + + free(config); +} + +/** + * @brief Clean up the stack-allocated parse state. + * + * Frees the visited_files string array. The config pointer is simply NULLed + * (ownership is transferred to the caller on success). + * + * @param state Pointer to the parse state to clean up. + */ +static inline +void cleanup_parse_state_stack(struct config_parse_state *state) +{ + state->config = NULL; + + str_array_free(&state->visited_files); +} + +/* ======================================================================== + * Role merging + * + * A client can hold multiple roles (from user entries, group entries, and + * the default user). The effective permission set is the union (logical OR) + * of all individual roles. These helpers construct the merged role. + * ======================================================================== */ + +/** + * @brief Allocate a new empty role with the given name. + * + * All permission flags start as false/zero. The caller receives ownership + * of the role via *rolep. + * + * @param[out] rolep Receives the newly allocated role. + * @param name Human-readable name for the role (copied). + * @return 0 on success, -1 on allocation failure. + */ +int role_merge_new(struct role **rolep, const char *name) +{ + assert(rolep != NULL); + + _cleanup_(cleanup_rolep) + struct role *role = calloc(1, sizeof *role); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Error allocating new role"); + + _cleanup_(cleanup_free) + char *s = strdup(name); + PROPAGATE_ERROR_NULL_STDC_LOG(s, LOG_ERR, "Error allocating new role"); + + role->name = s; + s = NULL; + + *rolep = role; + role = NULL; + + return 0; +} + +/** + * @brief Merge a source role's permissions into a destination role. + * + * For each boolean permission field, the destination retains `true` if either + * the destination or source had it set ("highest privilege wins" via OR). + * Per-device policies are merged by BDF: for each source device_policy, + * a matching entry in the destination is found (or created), and each + * subsystem flag is ORed independently. + * + * @param dst The role accumulating permissions (modified in place). + * @param src The role whose permissions are being merged in. + * @return 0 on success, -1 if either argument is NULL or on allocation error. + */ +int role_merge_add_role(struct role *dst, const struct role *src) +{ + if (dst == NULL || src == NULL) { + assert(false); + return -1; + } + + /* Highest privilege wins => OR the global booleans. */ + dst->query = dst->query || src->query; + + /* Merge per-device policies: find-or-create in dst, OR each subsystem flag. */ + for (size_t i = 0; i < src->device_policies.len; i++) { + const struct device_policy *src_dp = src->device_policies.d[i]; + assert(src_dp != NULL); + + struct device_policy *dst_dp = NULL; + int ret = find_or_create_device_policy(&dst->device_policies, src_dp->bdf, &dst_dp); + PROPAGATE_ERROR(ret); + + dst_dp->bar = dst_dp->bar || src_dp->bar; + dst_dp->qdma = dst_dp->qdma || src_dp->qdma; + dst_dp->buffer = dst_dp->buffer || src_dp->buffer; + dst_dp->design_write = dst_dp->design_write || src_dp->design_write; + dst_dp->clock = dst_dp->clock || src_dp->clock; + dst_dp->pcie_hotplug = dst_dp->pcie_hotplug || src_dp->pcie_hotplug; + dst_dp->raw_mem_access = dst_dp->raw_mem_access || src_dp->raw_mem_access; + } + + return 0; +} + +/** + * @brief Merge an array of roles into a destination role. + * + * Iterates over @p roles and calls role_merge_add_role() for each element, + * accumulating the union of all permissions into @p dst. + * + * @param dst The role accumulating permissions. + * @param roles Array of role pointers to merge in. + * @return 0 on success, -1 on error. + */ +int role_merge_add_array(struct role *dst, const struct role_ref_array *roles) +{ + if (dst == NULL || roles == NULL) { + assert(false); + return -1; + } + + for (size_t i = 0; i < roles->len; ++i) { + const struct role *r = roles->d[i]; + assert(r != NULL); + + int ret = role_merge_add_role(dst, r); + PROPAGATE_ERROR(ret); + } + + return 0; +} + + + +/** + * @brief Load the vrtd configuration from disk. + * + * Entry point for the configuration subsystem. Performs the following steps: + * 1. Allocates a config struct and the default (wildcard) user entry. + * 2. Determines the config file path: first checks the VRTD_CONFIG + * environment variable, then falls back to VRTD_DEFAULT_CONFIG_PATH + * (/etc/vrt/vrtd.conf). + * 3. Parses the config file (and any included files) via inih callbacks, + * populating config->roles, config->users, config->groups, and + * config->default_user with parsed role names. + * 4. Resolves the string-based role references in each user and group + * to actual role struct pointers (assign_users_roles / assign_groups_roles). + * 5. On success, transfers ownership of the config to the caller via *configp. + * On error, all allocated memory is automatically freed via _cleanup_. + * + * @param[out] configp Receives the fully loaded configuration. Caller owns it + * and must eventually free it with cleanup_config(). + * @return 0 on success, -1 on error. + */ +int config_load(struct config **configp) +{ + _cleanup_(cleanup_parse_state_stack) + struct config_parse_state state = {0}; + + // Cleanup on error + _cleanup_(cleanup_configp) + struct config *config = calloc(1, sizeof(**configp)); + + config->default_user = calloc(1, sizeof(*config->default_user)); + PROPAGATE_ERROR_NULL_LOG(config->default_user, LOG_ERR, "Memory error assigning default user"); + + config->default_user->name = strdup(DEFAULT_USER_NAME); + PROPAGATE_ERROR_NULL_LOG(config->default_user->name, LOG_ERR, "Memory error assigning default user name"); + + state.config = config; + + const char *path = getenv("VRTD_CONFIG"); + if (path == NULL || path[0] == '\0') { + path = VRTD_DEFAULT_CONFIG_PATH; + } + + int ret = parse_file(&state, path); + + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to parse config file"); + + /* Phase 2: resolve role name strings to role struct pointers. */ + ret = assign_users_roles(config); + PROPAGATE_ERROR(ret); + + ret = assign_groups_roles(config); + PROPAGATE_ERROR(ret); + + LOG(LOG_INFO, "Configuration loaded successfully"); + + // No error, do not cleanup + *configp = config; + config = NULL; + + return 0; +} + +/** + * @brief Resolve a relative glob/include pattern against the current config file's directory. + * + * If @p pattern is a relative path (does not start with '/') and there is a + * current file being parsed (tracked in state->visited_files), this function + * constructs an absolute path by prepending the directory of the current + * config file. + * + * If @p pattern is already absolute or there is no current file context, + * *abs_pattern is set to NULL and the caller should use @p pattern directly. + * + * @param state Current parse state (provides the visited_files stack). + * @param pattern The include pattern from the config file. + * @param[out] abs_pattern Receives the heap-allocated absolute pattern, or NULL. + * Caller must free() if non-NULL. + * @return 0 on success, -1 on allocation failure. + */ +static int resolve_relative_pattern(struct config_parse_state *state, const char *pattern, char **abs_pattern) +{ + *abs_pattern = NULL; + + if (pattern[0] == '/' || state->visited_files.len == 0) { + return 0; + } + + /* Use the most recently entered config file as the base directory. */ + const char *current_file = state->visited_files.d[state->visited_files.len - 1]; + + _cleanup_(cleanup_free) + char *dir = strdup(current_file); + PROPAGATE_ERROR_NULL_STDC_LOG(dir, LOG_ERR, "Error resolving glob pattern %s", pattern); + + /* Truncate after the last '/' to get the directory portion. */ + char *slash = strrchr(dir, '/'); + if (slash == NULL) { + return 0; + } + slash[1] = '\0'; + + int r = asprintf(abs_pattern, "%s%s", dir, pattern); + PROPAGATE_ERROR_LOG(r, LOG_ERR, "Error resolving glob pattern %s", pattern); + + return 0; +} + +/** + * @brief Expand a glob pattern and parse each matched config file. + * + * Used to implement `include-glob = ` directives. Relative patterns + * are resolved against the directory of the currently-parsed config file. + * If no files match the pattern, this is silently treated as success. + * + * @param state Current parse state. + * @param pattern A shell glob pattern (e.g. "/etc/vrt/conf.d/*.conf"). + * @return 0 on success, -1 on error parsing any matched file. + */ +static int parse_file_glob(struct config_parse_state *state, const char *pattern) +{ + _cleanup_(globfree) + glob_t glob_state; + memset(&glob_state, 0, sizeof(glob_state)); + + /* Resolve relative patterns against the including config file's directory. */ + _cleanup_(cleanup_free) + char *abs_pattern = NULL; + int r = resolve_relative_pattern(state, pattern, &abs_pattern); + PROPAGATE_ERROR(r); + if (abs_pattern != NULL) { + pattern = abs_pattern; + } + + int ret = glob(pattern, GLOB_ERR, NULL, &glob_state); + if (ret == GLOB_NOMATCH) { + return 0; + } else if (ret != 0) { + LOG( + LOG_WARNING, + "Error matching pattern %s: %s", + pattern, + glob_err_to_string(ret) + ); + + return 0; + } + + for (size_t i = 0; i < glob_state.gl_pathc; i++) { + ret = parse_file(state, glob_state.gl_pathv[i]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Found by pattern %s", pattern); + } + + return 0; +} + +/** + * @brief Parse a config file, with circular-include detection. + * + * Resolves the given path to its canonical form, then checks whether this + * file has already been parsed (by searching state->visited_files). If it + * has, the function returns immediately to avoid infinite include loops. + * Otherwise, the canonical path is recorded and the file is parsed. + * + * @param state Current parse state. + * @param path Path to the config file (may be relative or contain symlinks). + * @return 0 on success, -1 on error. + */ +static int parse_file(struct config_parse_state *state, const char *path) +{ + _cleanup_(cleanup_free) + char *full_path = realpath(path, NULL); + PROPAGATE_ERROR_NULL_STDC_LOG(full_path, LOG_ERR, "Error obtaining the cannonical path for %s", path); + + /* Check for circular includes: skip if we have already visited this file. */ + for (size_t i = 0; i < state->visited_files.len; i++) { + if (strcmp(full_path, state->visited_files.d[i]) == 0) { + /* We have already parsed this file -- exit as OK */ + return 0; + } + } + + char *full_path_ref = full_path; + + int ret = str_array_push_move(&state->visited_files, &full_path); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Error processing %s", full_path); + + LOG(LOG_DEBUG, "Parsing config file %s", full_path_ref); + + ret = parse_file_unique(state, full_path_ref); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Error parsing file %s", full_path_ref); + + return 0; +} + +/** + * @brief Invoke the inih parser on a single config file. + * + * Wraps ini_parse() and translates its error codes into log messages. + * The parse_config_callback is called for each key/value pair encountered. + * + * @param state Current parse state (passed as user data to the callback). + * @param path Canonical path to the file to parse. + * @return 0 on success, -1 on parse error or file-open failure. + */ +static int parse_file_unique(struct config_parse_state *state, const char *path) +{ + int ret = ini_parse(path, parse_config_callback, state); + if (ret != 0) { + if (ret > 0) { + LOG(LOG_ERR, "Parse error at %s:%d", path, ret); + return -1; + } else if (ret == -1) { + LOG(LOG_ERR, "Could not open file %s", path); + return -1; + } else if (ret == -2) { + LOG(LOG_ERR, "Out of memory reading file %s", path); + return -1; + } else { + LOG(LOG_WARNING, "Unknown error reading file %s", path); + return 0; + } + } + + return 0; +} + +/** + * @brief inih callback: dispatches each INI key/value to the right handler. + * + * Section formats and their handlers: + * - Top-level (empty section): + * `include = ` -> parse_file() (recursive include) + * `include-glob = ` -> parse_file_glob() (glob-based include) + * `enable-mock-device = ` -> sets config->mock_device + * - `[role:]` -> role_find_and_add_value() (role permission keys) + * - `[user:]` -> user_find_and_add_value() (user-to-role mapping) + * - `[group:]` -> group_find_and_add_value() (group-to-role mapping) + * + * Uses inih convention: returns 1 on success, 0 on error. + * + * @param user Opaque pointer to config_parse_state. + * @param section INI section name (e.g. "role:admin", "user:jdoe", ""). + * @param name Key name within the section. + * @param value Value string associated with the key. + * @return 1 on success, 0 on error (per inih convention). + */ +// This callback uses 0 for error and 1 for success, as per inih spec +static int parse_config_callback(void *user, const char *section, const char *name, const char *value) +{ + #define MATCH(s, n) (strcmp(section, s) == 0 && strcmp(name, n) == 0) + /** + * MATCH_OBJECT: matches sections of the form "prefix:objname". + * On match, sets the local `n` pointer to the substring after the colon + * (the object's name). For example, [role:admin] yields objname = "admin". + */ + #define MATCH_OBJECT(c, n) \ + ({ const char *colon__ = strchr(section, ':'); \ + colon__ && (size_t)(colon__ - section) == strlen(c) && \ + memcmp(section, (c), strlen(c)) == 0 && \ + (n = colon__ + 1, n[0] != '\0'); \ + }) + + int ret; + const char *objname; + struct config_parse_state *state = user; + + if (MATCH("", "include")) { + ret = parse_file(state, value); + if (ret == -1) { + return 0; + } + } else if (MATCH("", "include-glob")) { + ret = parse_file_glob(state, value); + if (ret == -1) { + return 0; + } + } else if (MATCH("", "enable-mock-device")) { + state->config->mock_device = string_to_bool(value); + } else if (MATCH_OBJECT("role", objname)) { + /* Check if objname contains a device selector (e.g. "admin:0000:03:00"). + * Role names must not contain colons, so the first colon in objname + * separates the role name from the device selector. */ + const char *dev_sep = strchr(objname, ':'); + if (dev_sep != NULL) { + char *role_name = strndup(objname, (size_t)(dev_sep - objname)); + if (role_name == NULL) { + LOG(LOG_ERR, "Could not allocate role name"); + return 0; + } + const char *dev_selector = dev_sep + 1; + ret = role_device_find_and_add_value(state->config, role_name, dev_selector, name, value); + free(role_name); + } else { + ret = role_find_and_add_value(state->config, objname, name, value); + } + if (ret == -1) { + return 0; + } + } else if (MATCH_OBJECT("user", objname)) { + ret = user_find_and_add_value(state->config, objname, name, value); + if (ret == -1) { + return 0; + } + } else if (MATCH_OBJECT("group", objname)) { + ret = group_find_and_add_value(state->config, objname, name, value); + if (ret == -1) { + return 0; + } + } else { + LOG(LOG_WARNING, "Unknown section/key: [%s] %s", section, name); + return 1; + } + + return 1; + + #undef MATCH + #undef MATCH_OBJECT +} + +/* ======================================================================== + * Role parsing + * + * Roles are defined in INI sections like [role:admin]. Each key sets a + * permission flag on the role struct. If the role already exists (from an + * earlier key or included file), the new value is applied to the existing + * role; otherwise a new role is created and appended to config->roles. + * ======================================================================== */ + +/** + * @brief Find or create a role by name and set a key/value on it. + * + * Searches config->roles for a role with the given objname. If found, applies + * the key/value via role_add_value(). If not found, allocates a new role, + * applies the value, and appends it to config->roles. + * + * @param config The global config being built. + * @param objname Role name (from the section header, e.g. "admin"). + * @param name Key name (e.g. "pcie-hotplug", "bar-access", "device"). + * @param value Value string (e.g. "yes", "full", "any"). + * @return 0 on success, -1 on error. + */ +static int role_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value) +{ + for (size_t i = 0; i < config->roles.len; ++i) { + if (strcmp(config->roles.d[i]->name, objname) == 0) { + return role_add_value(config->roles.d[i], name, value); + } + } + + _cleanup_(cleanup_rolep) + struct role *role = calloc(1, sizeof *role); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Could not allocate role"); + + role->name = strdup(objname); + PROPAGATE_ERROR_NULL_STDC_LOG(role->name, LOG_ERR, "Could not allocate role name"); + + int ret = role_add_value(role, name, value); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Invalid key/value for role %s: '%s' = '%s'", objname, name, value); + + ret = role_ptr_array_push_move(&config->roles, &role); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not store role %s", objname); + + return 0; +} + +/** + * @brief Apply a single key/value pair to a role (global section keys). + * + * Handles keys that appear in a plain @c [role:\] section (without a + * device selector). Supported keys: + * - "query-devices":"yes" | "no" -- controls device enumeration / info queries. + * + * All other permissions (bar-access, qdma, buffer, design-write, clock, + * pcie-hotplug) must be specified in device-scoped sections + * @c [role:\:\]. + * + * @param role The role to modify. + * @param name Key name. + * @param value Value string. + * @return 0 on success, -1 on unknown key or invalid value. + */ +static int role_add_value(struct role *role, const char *name, const char *value) +{ + if (strcmp(name, "query-devices") == 0) { + if (strcmp(value, "yes") == 0) { + role->query = true; + return 0; + } else if (strcmp(value, "no") == 0) { + role->query = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for role query-devices: '%s'", value); + return -1; + } + } else { + LOG(LOG_ERR, "Unknown role key: '%s'", name); + return -1; + } +} + +/* ======================================================================== + * BDF normalization and device policy helpers + * + * These utilities support the per-device permission model. BDF strings + * are normalized to the canonical "DDDD:BB:DD" board-level format. + * Device policies are stored in a per-role array and looked up by BDF. + * ======================================================================== */ + +/** + * @brief Normalize a BDF string to canonical board-level form "DDDD:BB:DD". + * + * Handles: + * - "any" is passed through unchanged. + * - Short-form "BB:DD" is expanded to "0000:BB:DD". + * - Full-form "DDDD:BB:DD" is copied as-is. + * - A trailing ".F" function suffix is stripped (board-level only). + * + * @param input The raw BDF string from the config file. + * @param out Output buffer for the normalized BDF. + * @param out_len Size of the output buffer (must be >= 13 for "DDDD:BB:DD\0"). + * @return 0 on success, -1 on invalid format or buffer too small. + */ +static int normalize_bdf(const char *input, char *out, size_t out_len) +{ + assert(input != NULL); + assert(out != NULL); + + if (strcmp(input, "any") == 0) { + if (out_len < 4) { + return -1; + } + strcpy(out, "any"); + return 0; + } + + /* Work on a mutable copy so we can strip function suffix. */ + char buf[64]; + size_t len = strlen(input); + if (len >= sizeof(buf)) { + LOG(LOG_ERR, "BDF string too long: '%s'", input); + return -1; + } + memcpy(buf, input, len + 1); + + /* Strip ".F" function suffix if present. */ + char *dot = strrchr(buf, '.'); + if (dot != NULL) { + *dot = '\0'; + } + + /* Count colons to determine format. */ + int colons = 0; + for (const char *p = buf; *p; p++) { + if (*p == ':') { + colons++; + } + } + + if (colons == 1) { + /* Short-form "BB:DD" -> "0000:BB:DD" */ + int ret = snprintf(out, out_len, "0000:%s", buf); + if (ret < 0 || (size_t)ret >= out_len) { + LOG(LOG_ERR, "BDF buffer too small for '%s'", input); + return -1; + } + } else if (colons == 2) { + /* Full-form "DDDD:BB:DD" */ + if (strlen(buf) >= out_len) { + LOG(LOG_ERR, "BDF buffer too small for '%s'", input); + return -1; + } + strcpy(out, buf); + } else { + LOG(LOG_ERR, "Invalid BDF format: '%s'", input); + return -1; + } + + return 0; +} + +/** + * @brief Find an existing device_policy by BDF in the policies array. + * + * @param policies The array to search. + * @param bdf The normalized BDF string to match. + * @return Pointer to the matching device_policy, or NULL if not found. + */ +static struct device_policy *find_device_policy( + const struct device_policy_ptr_array *policies, + const char *bdf +) +{ + for (size_t i = 0; i < policies->len; i++) { + if (strcmp(policies->d[i]->bdf, bdf) == 0) { + return policies->d[i]; + } + } + return NULL; +} + +/** + * @brief Find or create a device_policy entry for the given BDF. + * + * Searches the policies array for an existing entry with the given BDF. + * If not found, allocates a new device_policy with all flags false and + * appends it to the array. + * + * @param policies The array to search/modify. + * @param bdf The normalized BDF string. + * @param[out] out Receives the found or newly created device_policy. + * @return 0 on success, -1 on allocation error. + */ +static int find_or_create_device_policy( + struct device_policy_ptr_array *policies, + const char *bdf, + struct device_policy **out +) +{ + struct device_policy *dp = find_device_policy(policies, bdf); + if (dp != NULL) { + *out = dp; + return 0; + } + + /* Allocate a new device_policy with all flags false. */ + dp = calloc(1, sizeof(*dp)); + PROPAGATE_ERROR_NULL_STDC_LOG(dp, LOG_ERR, "Could not allocate device_policy"); + + dp->bdf = strdup(bdf); + if (dp->bdf == NULL) { + free(dp); + LOG(LOG_ERR, "Could not allocate BDF string: %s", strerror(errno)); + return -1; + } + + int ret = device_policy_ptr_array_push(policies, dp); + if (ret != 0) { + free(dp->bdf); + free(dp); + LOG(LOG_ERR, "Could not store device_policy: %s", strerror(errno)); + return -1; + } + + *out = dp; + return 0; +} + +/** + * @brief Find or create a role by name in the config. + * + * Searches config->roles for an existing role with the given name. + * If not found, allocates a new role and appends it to the array. + * + * @param config The global config being built. + * @param role_name Name of the role to find or create. + * @return Pointer to the role, or NULL on allocation error. + */ +static struct role *role_find_or_create(struct config *config, const char *role_name) +{ + for (size_t i = 0; i < config->roles.len; ++i) { + if (strcmp(config->roles.d[i]->name, role_name) == 0) { + return config->roles.d[i]; + } + } + + struct role *role = calloc(1, sizeof(*role)); + if (role == NULL) { + LOG(LOG_ERR, "Could not allocate role: %s", strerror(errno)); + return NULL; + } + + role->name = strdup(role_name); + if (role->name == NULL) { + free(role); + LOG(LOG_ERR, "Could not allocate role name: %s", strerror(errno)); + return NULL; + } + + int ret = role_ptr_array_push(&config->roles, role); + if (ret != 0) { + free(role->name); + free(role); + LOG(LOG_ERR, "Could not store role %s: %s", role_name, strerror(errno)); + return NULL; + } + + return role; +} + +/** + * @brief Handle a key/value from a device-scoped role section [role:name:bdf]. + * + * Finds or creates the role, normalizes the device selector BDF, finds or + * creates the device_policy entry, and sets the appropriate flag. + * + * @param config The global config being built. + * @param role_name The role name (portion before the device selector). + * @param dev_selector The device selector ("any", "0000:03:00", "03:00", etc.). + * @param name Key name (e.g. "bar-access", "qdma", "buffer"). + * @param value Value string (e.g. "full", "yes", "no"). + * @return 0 on success, -1 on error. + */ +static int role_device_find_and_add_value( + struct config *config, + const char *role_name, + const char *dev_selector, + const char *name, + const char *value +) +{ + struct role *role = role_find_or_create(config, role_name); + PROPAGATE_ERROR_NULL_LOG(role, LOG_ERR, "Could not find or create role %s", role_name); + + /* Normalize the device selector to canonical BDF form. */ + char normalized_bdf[32]; + int ret = normalize_bdf(dev_selector, normalized_bdf, sizeof(normalized_bdf)); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Invalid device selector '%s' for role %s", dev_selector, role_name); + + struct device_policy *dp = NULL; + ret = find_or_create_device_policy(&role->device_policies, normalized_bdf, &dp); + PROPAGATE_ERROR(ret); + + ret = device_policy_add_value(dp, name, value); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Invalid key/value for role %s device %s: '%s' = '%s'", + role_name, normalized_bdf, name, value); + + return 0; +} + +/** + * @brief Apply a single key/value pair to a device_policy. + * + * Supported keys: + * - "bar-access": "full" -- grants BAR mmap access. + * - "qdma": "yes" | "no" -- controls QDMA queue pair operations. + * - "buffer": "yes" | "no" -- controls DMA buffer operations. + * - "design-write": "yes" | "no" -- controls FPGA bitstream programming. + * - "clock": "yes" | "no" -- controls clock get/set operations. + * - "pcie-hotplug": "yes" | "no" -- controls per-device hotplug operations. + * - "raw-mem-access": "yes" | "no" -- controls raw DMA buffer open (bypasses allocator). + * + * @param dp The device_policy to modify. + * @param name Key name. + * @param value Value string. + * @return 0 on success, -1 on unknown key or invalid value. + */ +static int device_policy_add_value(struct device_policy *dp, const char *name, const char *value) +{ + if (strcmp(name, "bar-access") == 0) { + if (strcmp(value, "full") == 0) { + dp->bar = true; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device bar-access: '%s'", value); + return -1; + } + } else if (strcmp(name, "qdma") == 0) { + if (strcmp(value, "yes") == 0) { + dp->qdma = true; + return 0; + } else if (strcmp(value, "no") == 0) { + dp->qdma = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device qdma: '%s'", value); + return -1; + } + } else if (strcmp(name, "buffer") == 0) { + if (strcmp(value, "yes") == 0) { + dp->buffer = true; + return 0; + } else if (strcmp(value, "no") == 0) { + dp->buffer = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device buffer: '%s'", value); + return -1; + } + } else if (strcmp(name, "design-write") == 0) { + if (strcmp(value, "yes") == 0) { + dp->design_write = true; + return 0; + } else if (strcmp(value, "no") == 0) { + dp->design_write = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device design-write: '%s'", value); + return -1; + } + } else if (strcmp(name, "clock") == 0) { + if (strcmp(value, "yes") == 0) { + dp->clock = true; + return 0; + } else if (strcmp(value, "no") == 0) { + dp->clock = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device clock: '%s'", value); + return -1; + } + } else if (strcmp(name, "pcie-hotplug") == 0) { + if (strcmp(value, "yes") == 0) { + dp->pcie_hotplug = true; + return 0; + } else if (strcmp(value, "no") == 0) { + dp->pcie_hotplug = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device pcie-hotplug: '%s'", value); + return -1; + } + } else if (strcmp(name, "raw-mem-access") == 0) { + if (strcmp(value, "yes") == 0) { + dp->raw_mem_access = true; + return 0; + } else if (strcmp(value, "no") == 0) { + dp->raw_mem_access = false; + return 0; + } else { + LOG(LOG_ERR, "Invalid value for device raw-mem-access: '%s'", value); + return -1; + } + } else { + LOG(LOG_ERR, "Unknown device policy key: '%s'", name); + return -1; + } +} + +/* ======================================================================== + * User parsing + * + * Users are defined in INI sections like [user:jdoe]. The special name "*" + * refers to the default (wildcard) user whose roles apply to every client. + * Each user section maps to one or more `role = ` entries. + * The UID is resolved from the system passwd database at parse time. + * ======================================================================== */ + +/** + * @brief Find or create a user config by name and set a key/value on it. + * + * The wildcard user "*" is stored in config->default_user rather than the + * users array. For named users, this function searches the existing users + * array; if not found, it creates a new user_config, resolves the UID via + * getpwnam_r, and appends it to config->users. + * + * @param config The global config being built. + * @param objname User name (from section header) or "*" for default. + * @param name Key name (currently only "role" is supported). + * @param value Value string (e.g. the role name to assign). + * @return 0 on success, -1 on error. + */ +static int user_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value) +{ + /* The wildcard user "*" is stored separately as default_user. */ + if (strcmp(objname, "*") == 0) { + return user_add_value(config->default_user, name, value); + } + + for (size_t i = 0; i < config->users.len; ++i) { + if (strcmp(config->users.d[i]->name, objname) == 0) { + return user_add_value(config->users.d[i], name, value); + } + } + + _cleanup_(cleanup_user_configp) + struct user_config *user = calloc(1, sizeof *user); + PROPAGATE_ERROR_NULL_STDC_LOG(user, LOG_ERR, "Could not allocate user"); + + user->name = strdup(objname); + PROPAGATE_ERROR_NULL_STDC_LOG(user->name, LOG_ERR, "Could not allocate user name"); + + /* Resolve the system UID for this username at config-load time. */ + int ret = set_user_uid(&user->uid, objname); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Could not find uid for user %s", objname); + + ret = user_add_value(user, name, value); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Invalid key/value for user %s: '%s' = '%s'", objname, name, value); + + ret = user_config_ptr_array_push_move(&config->users, &user); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not store user %s", objname); + + return 0; +} + +/** + * @brief Apply a single key/value pair to a user config. + * + * Currently the only supported key is "role", which appends a role name + * string to the user's role_names list. Multiple `role = ` lines + * allow a user to hold several roles (whose permissions are merged at + * authorization time). + * + * @param user The user config to modify. + * @param name Key name (must be "role"). + * @param value The role name to add. + * @return 0 on success, -1 on unknown key or allocation failure. + */ +static int user_add_value(struct user_config *user, const char *name, const char *value) +{ + if (strcmp(name, "role") == 0) { + _cleanup_(cleanup_free) + char *role = strdup(value); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Could not allocate role name"); + + int ret = str_array_push_move(&user->role_names, &role); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not store role name for user"); + + return 0; + } else { + return -1; + } +} + +/* ======================================================================== + * Group parsing + * + * Groups are defined in INI sections like [group:fpga-users]. Each group + * section maps to one or more `role = ` entries. The GID is + * resolved from the system group database at parse time. At authorization + * time, if any of the client's supplementary GIDs matches a group's GID, + * that group's roles are merged into the client's effective permissions. + * ======================================================================== */ + +/** + * @brief Find or create a group config by name and set a key/value on it. + * + * Searches config->groups for an existing group with the given name. If not + * found, allocates a new group_config, resolves the GID via getgrnam_r, and + * appends it to config->groups. + * + * @param config The global config being built. + * @param objname Group name (from section header, e.g. "fpga-users"). + * @param name Key name (currently only "role" is supported). + * @param value Value string (e.g. the role name to assign). + * @return 0 on success, -1 on error. + */ +static int group_find_and_add_value(struct config *config, const char *objname, const char *name, const char *value) +{ + for (size_t i = 0; i < config->groups.len; ++i) { + if (strcmp(config->groups.d[i]->name, objname) == 0) { + return group_add_value(config->groups.d[i], name, value); + } + } + + _cleanup_(cleanup_group_configp) + struct group_config *group = calloc(1, sizeof *group); + PROPAGATE_ERROR_NULL_STDC_LOG(group, LOG_ERR, "Could not allocate group"); + + group->name = strdup(objname); + PROPAGATE_ERROR_NULL_STDC_LOG(group->name, LOG_ERR, "Could not allocate group name"); + + /* Resolve the system GID for this group name at config-load time. */ + int ret = set_group_gid(&group->gid, objname); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Could not find gid for group %s", objname); + + ret = group_add_value(group, name, value); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Invalid key/value for group %s: '%s' = '%s'", objname, name, value); + + ret = group_config_ptr_array_push_move(&config->groups, &group); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not store group %s", objname); + + return 0; +} + +/** + * @brief Apply a single key/value pair to a group config. + * + * Currently the only supported key is "role", which appends a role name + * to the group's role_names list. + * + * @param group The group config to modify. + * @param name Key name (must be "role"). + * @param value The role name to add. + * @return 0 on success, -1 on unknown key or allocation failure. + */ +static int group_add_value(struct group_config *group, const char *name, const char *value) +{ + if (strcmp(name, "role") == 0) { + _cleanup_(cleanup_free) + char *role = strdup(value); + PROPAGATE_ERROR_NULL_STDC_LOG(role, LOG_ERR, "Could not allocate role name"); + + int ret = str_array_push_move(&group->role_names, &role); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not store role name for group"); + + return 0; + } else { + return -1; + } +} + +/* ======================================================================== + * UID / GID resolution + * + * These helpers look up a system user or group by name (via the reentrant + * POSIX getpwnam_r / getgrnam_r) and extract the numeric UID or GID. They + * handle ERANGE by doubling the buffer and retrying, and EINTR by retrying + * in place. + * ======================================================================== */ + +/** + * @brief Resolve a username to its numeric UID via getpwnam_r. + * + * @param[out] uid Receives the resolved UID. + * @param name The username to look up. + * @return 0 on success, -1 if the user is not found or on system error. + */ +static int set_user_uid(uid_t *uid, const char *name) +{ + size_t bufsz = BUFSIZ; + int ret; + struct passwd pwd; + struct passwd *result; + + do { + char *buf = malloc(bufsz); + PROPAGATE_ERROR_NULL_STDC_LOG(buf, LOG_ERR, "Failed malloc in get_user_uid"); + +retry: + ret = getpwnam_r(name, &pwd, buf, bufsz, &result); + if (ret == EINTR) { + goto retry; + } + + free(buf); + + bufsz *= 2; + } while (ret == ERANGE); + + PROPAGATE_ERROR_NULL_STDC_LOG(result, LOG_ERR, "User %s not found", name); + + *uid = result->pw_uid; + return 0; +} + +/** + * @brief Resolve a group name to its numeric GID via getgrnam_r. + * + * @param[out] gid Receives the resolved GID. + * @param name The group name to look up. + * @return 0 on success, -1 if the group is not found or on system error. + */ +static int set_group_gid(gid_t *gid, const char *name) +{ + size_t bufsz = BUFSIZ; + int ret; + struct group pwd; + struct group *result; + + do { + char *buf = malloc(bufsz); + PROPAGATE_ERROR_NULL_STDC_LOG(buf, LOG_ERR, "Failed malloc in set_group_gid"); + +retry: + ret = getgrnam_r(name, &pwd, buf, bufsz, &result); + if (ret == EINTR) { + goto retry; + } + + free(buf); + + bufsz *= 2; + } while (ret == ERANGE); + + PROPAGATE_ERROR_NULL_STDC_LOG(result, LOG_ERR, "Group %s not found", name); + + *gid = result->gr_gid; + return 0; +} + +/* ======================================================================== + * Role assignment (post-parse phase) + * + * During INI parsing, user and group configs accumulate role names as + * strings (role_names array). After all files are parsed, these functions + * resolve each name to a pointer into config->roles, populating the `roles` + * reference array. This two-phase approach allows roles to be defined in + * any order or across multiple included files. + * ======================================================================== */ + +/** + * @brief Resolve role name references for all users (including the default user). + * + * @param config The fully parsed config with populated role_names arrays. + * @return 0 on success, -1 on error. + */ +static int assign_users_roles(struct config *config) +{ + /* Resolve the default (wildcard) user first. */ + int ret = assign_user_roles(config, config->default_user); + PROPAGATE_ERROR(ret); + + for (size_t i = 0; i < config->users.len; i++) { + ret = assign_user_roles(config, config->users.d[i]); + PROPAGATE_ERROR(ret); + } + + return 0; +} + +/** + * @brief Resolve role name references for a single user config. + * + * For each role name string in user->role_names, searches config->roles for + * a matching role and pushes a reference pointer into user->roles. If a role + * name is not found, a warning is logged but processing continues (the user + * simply will not receive that role's permissions). + * + * @param config The global config (provides the roles array to search). + * @param user The user config whose role names are being resolved. + * @return 0 on success, -1 on allocation error. + */ +static int assign_user_roles(struct config *config, struct user_config *user) +{ + for (size_t j = 0; j < user->role_names.len; j++) { + bool found_role_name = false; + + for (size_t k = 0; k < config->roles.len; k++) { + if (strcmp(user->role_names.d[j], config->roles.d[k]->name) == 0) { + int ret = role_ref_array_push(&user->roles, config->roles.d[k]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed allocation in assign_user_roles"); + + found_role_name = true; + break; + } + } + + if (!found_role_name) { + LOG(LOG_WARNING, "Failed to find user role %s for user %s", user->role_names.d[j], user->name); + } + } + + return 0; +} + +/** + * @brief Resolve role name references for all groups. + * + * @param config The fully parsed config with populated role_names arrays. + * @return 0 on success, -1 on error. + */ +static int assign_groups_roles(struct config *config) +{ + for (size_t i = 0; i < config->groups.len; i++) { + int ret = assign_group_roles(config, config->groups.d[i]); + PROPAGATE_ERROR(ret); + } + + return 0; +} + +/** + * @brief Resolve role name references for a single group config. + * + * Mirrors assign_user_roles() but operates on a group_config. Unresolved + * role names produce a warning but do not cause a hard failure. + * + * @param config The global config (provides the roles array to search). + * @param group The group config whose role names are being resolved. + * @return 0 on success, -1 on allocation error. + */ +static int assign_group_roles(struct config *config, struct group_config *group) +{ + for (size_t j = 0; j < group->role_names.len; j++) { + bool found_role_name = false; + + for (size_t k = 0; k < config->roles.len; k++) { + if (strcmp(group->role_names.d[j], config->roles.d[k]->name) == 0) { + int ret = role_ref_array_push(&group->roles, config->roles.d[k]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed allocation in assign_group_roles"); + + found_role_name = true; + break; + } + } + + if (!found_role_name) { + LOG(LOG_WARNING, "Failed to find group role %s for group %s", group->role_names.d[j], group->name); + } + } + + return 0; +} diff --git a/vrt/vrtd/src/config.h b/vrt/vrtd/src/config.h new file mode 100644 index 00000000..2e36045e --- /dev/null +++ b/vrt/vrtd/src/config.h @@ -0,0 +1,318 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file config.h + * @brief Configuration data model for the vrtd daemon. + * + * The daemon reads a configuration file that defines: + * - Named @em roles, each granting a specific set of permissions (which + * devices may be accessed, which BARs, whether queries or PCIe hotplug + * operations are allowed). + * - @em User entries that map a system UID to one or more roles. + * - @em Group entries that map a system GID to one or more roles. + * - A @em default user entry applied when no explicit UID/GID match is found. + * + * Role names inside user/group entries are resolved lazily: the config parser + * stores the names first, then links them to the actual @c struct @c role + * objects in a second pass via @c role_merge_add_array. + */ + +#ifndef VRTD_CONFIG_H +#define VRTD_CONFIG_H + +#include +#include + +#include "array.h" + +/** + * @brief Per-device permission flags. + * + * Each device_policy entry maps a device (identified by board-level BDF + * string, e.g. "0000:03:00") to a set of subsystem-level permissions. + * The special BDF string "any" acts as a wildcard matching all devices. + * + * During authorization, the auth layer looks up the target device's BDF + * in the role's device_policies array: first an exact match, then a + * fallback to the "any" entry if present. + */ +struct device_policy { + /** @brief Normalized BDF string ("DDDD:BB:DD") or "any" (heap-allocated, owning). */ + char *bdf; /* owning */ + /** @brief If true, the client may mmap BAR regions on this device. */ + bool bar; + /** @brief If true, the client may create/operate QDMA queue pairs on this device. */ + bool qdma; + /** @brief If true, the client may allocate/release DMA buffers on this device. */ + bool buffer; + /** @brief If true, the client may program FPGA bitstreams on this device. */ + bool design_write; + /** @brief If true, the client may get/set clock frequencies on this device. */ + bool clock; + /** @brief If true, the client may perform PCIe hotplug operations on this device. */ + bool pcie_hotplug; + /** @brief If true, the client may open raw DMA buffers at caller-specified device addresses (bypasses allocator). */ + bool raw_mem_access; +}; + +/** + * @brief Release all resources owned by a device_policy (bdf string). + * @param dp Pointer to the device_policy to clean up. + */ +void cleanup_device_policy(struct device_policy *dp); + +/** @brief Owning array of device_policy pointers. */ +DECLARE_OWNING_PTR_ARRAY(device_policy_ptr_array, struct device_policy *, cleanup_device_policy) + +/** + * @brief A named permission set that governs what a client may do. + * + * Roles are the central unit of the vrtd access-control model. Each + * connecting client is assigned a merged role derived from its UID and GID + * credentials. The role determines: + * - Which devices the client may access and with which subsystem + * permissions, via the @c device_policies array. + * - Whether the client may issue informational queries (@c query). + * + * Per-device permissions (bar-access, qdma, buffer, design-write, clock, + * pcie-hotplug) are specified in the config file using sub-sections of the + * form @c [role:\:\], where @c \ is a board-level PCI + * address or "any". + */ +struct role { + /** @brief Human-readable name of this role (heap-allocated, owning). */ + char *name; /* owning */ + + /** @brief Per-device permission policies (owning array). */ + struct device_policy_ptr_array device_policies; + + /** @brief If true, the role permits device enumeration and info queries. */ + bool query; +}; + +/** + * @brief Release all resources owned by a role (name string, device_policies array). + * @param role Pointer to the role to clean up. + */ +void cleanup_role(struct role *role); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param rolep Address of a @c struct @c role pointer. + */ +static inline +void cleanup_rolep(struct role **rolep) +{ + if (rolep == NULL) { + return; + } + + cleanup_role(*rolep); + + *rolep = NULL; +} + +/** @brief Non-owning array of role pointers (for referencing roles without ownership). */ +DECLARE_ARRAY(role_ref_array, struct role *) +/** @brief Owning array of role pointers (frees roles on cleanup). */ +DECLARE_OWNING_PTR_ARRAY(role_ptr_array, struct role *, cleanup_role) + +/** + * @brief Maps a system user (by UID) to a set of roles. + * + * During configuration loading, role names are stored in @c role_names for + * lazy resolution. After all roles are parsed, @c roles is populated with + * direct pointers. + */ +struct user_config { + /** @brief Username string (heap-allocated, owning). */ + char *name; /* owning */ + /** @brief Numeric user ID resolved from @c name via getpwnam(). */ + uid_t uid; + + /** @brief Role names from the config file, used for lazy resolution. */ + struct str_array role_names; /* Used for lazy loading roles */ + /** @brief Resolved role pointers (non-owning references into config.roles). */ + struct role_ref_array roles; +}; + +/** + * @brief Release all resources owned by a user_config. + * @param user Pointer to the user_config to clean up. + */ +void cleanup_user_config(struct user_config *user); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param userp Address of a @c struct @c user_config pointer. + */ +static inline +void cleanup_user_configp(struct user_config **userp) +{ + if (userp == NULL) { + return; + } + + cleanup_user_config(*userp); + + *userp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(user_config_ptr_array, struct user_config *, cleanup_user_config) + +/** + * @brief Maps a system group (by GID) to a set of roles. + * + * Analogous to @c struct @c user_config, but keyed on GID. Role names are + * lazily resolved the same way. + */ +struct group_config { + /** @brief Group name string (heap-allocated, owning). */ + char *name; /* owning */ + /** @brief Numeric group ID resolved from @c name via getgrnam(). */ + gid_t gid; + + /** @brief Role names from the config file, used for lazy resolution. */ + struct str_array role_names; /* Used for lazy loading roles */ + /** @brief Resolved role pointers (non-owning references into config.roles). */ + struct role_ref_array roles; +}; + +/** + * @brief Release all resources owned by a group_config. + * @param group Pointer to the group_config to clean up. + */ +void cleanup_group_config(struct group_config *group); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param groupp Address of a @c struct @c group_config pointer. + */ +static inline +void cleanup_group_configp(struct group_config **groupp) +{ + if (groupp == NULL) { + return; + } + + cleanup_group_config(*groupp); + + *groupp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(group_config_ptr_array, struct group_config *, cleanup_group_config) + +/** + * @brief Top-level daemon configuration container. + * + * Owns all roles, user mappings, and group mappings. The @c default_user + * entry (if present) is applied to any connecting client whose UID/GIDs do + * not match an explicit user or group entry. + */ +struct config { + /** @brief All defined roles (owning array). */ + struct role_ptr_array roles; + + /** @brief Fallback user entry applied when no UID/GID match is found (non-owning, + * points into @c users or is a standalone allocation). */ + struct user_config *default_user; + + /** @brief Per-UID user configuration entries (owning array). */ + struct user_config_ptr_array users; + /** @brief Per-GID group configuration entries (owning array). */ + struct group_config_ptr_array groups; + + /** @brief If true, use mock devices instead of real hardware (for testing). */ + bool mock_device; +}; + +/** + * @brief Release all resources owned by the config (roles, users, groups). + * @param config Pointer to the config to clean up. + */ +void cleanup_config(struct config *config); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param configp Address of a @c struct @c config pointer. + */ +static inline +void cleanup_configp(struct config **configp) +{ + if (configp == NULL) { + return; + } + + cleanup_config(*configp); + + *configp = NULL; +} + +/** + * @brief Load the daemon configuration from the default config file. + * + * Parses the configuration file, resolves UIDs/GIDs, and lazily links role + * name references to actual @c struct @c role objects. + * + * @param[out] config On success, receives a heap-allocated config. Caller + * must free with cleanup_config(). + * @return 0 on success, -1 on error (logged via sd_journal). + */ +int config_load(struct config **config); + +/** + * @brief Allocate a new empty role and assign it a name. + * + * Used during configuration loading and role merging to create a fresh role + * that can then be populated via @c role_merge_add_role. + * + * @param[out] rolep Receives the newly allocated role on success. + * @param name Name to assign to the role (copied). + * @return 0 on success, -1 on allocation failure. + */ +int role_merge_new(struct role **rolep, const char *name); + +/** + * @brief Merge permissions from one role into another (union of permissions). + * + * Adds @p src's device_policies and boolean permissions into @p dst. + * This implements the "most permissive wins" merging semantic: boolean + * flags are ORed, and per-device policy entries are merged by BDF with + * each subsystem flag ORed independently. + * + * @param dst Destination role to merge into (modified in place). + * @param src Source role to merge from (not modified). + * @return 0 on success, -1 on error. + */ +int role_merge_add_role(struct role *dst, const struct role *src); + +/** + * @brief Merge an array of roles into a single destination role. + * + * Iterates over @p roles and calls @c role_merge_add_role for each entry. + * + * @param dst Destination role to merge into. + * @param roles Array of role pointers to merge from. + * @return 0 on success, -1 on error. + */ +int role_merge_add_array(struct role *dst, const struct role_ref_array *roles); + +#endif // VRTD_CONFIG_H diff --git a/vrt/vrtd/src/design_writer.c b/vrt/vrtd/src/design_writer.c new file mode 100644 index 00000000..98170d4b --- /dev/null +++ b/vrt/vrtd/src/design_writer.c @@ -0,0 +1,916 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file design_writer.c + * @brief Asynchronous bitstream programming for AMD Alveo V80 FPGA devices via QDMA. + * + * This module implements the design_writer, which transfers FPGA bitstream data + * from a file descriptor to the device over a QDMA (Queue-based Direct Memory + * Access) memory-mapped (MM) channel. + * + * Threading model + * --------------- + * The design_writer uses a dedicated worker thread that runs for the lifetime + * of the design_writer object. The main thread (or any caller thread) submits + * work by handing over a file descriptor containing the bitstream data; the + * worker thread performs the potentially long-running QDMA transfer in the + * background. + * + * Producer-consumer pattern + * ------------------------- + * The interaction between the caller and the worker follows a simple + * single-slot producer-consumer protocol protected by a mutex + condvar: + * + * 1. Caller invokes design_writer_submit_fd_async() to enqueue a bitstream + * fd. This sets writer->input_fd and writer->busy, then signals the + * condvar so the worker wakes up. + * + * 2. The worker thread (design_writer_thread) waits on the condvar for + * input_fd >= 0. When signalled, it takes ownership of the fd, releases + * the mutex, reads the entire bitstream into a page-aligned buffer, and + * writes it to the QDMA device fd at the fixed bitstream address + * (VRTD_DESIGN_WRITER_SEEK_ADDR). + * + * 3. On completion (success or failure), the worker clears busy, stores any + * error in last_error, and broadcasts the condvar so that any thread + * blocked in design_writer_submit_fd() or design_writer_poll_result() + * can observe the result. + * + * The caller may choose between: + * - design_writer_submit_fd() -- synchronous: blocks until transfer + * completes. + * - design_writer_submit_fd_async() + design_writer_poll_result() + * -- asynchronous: submit, then poll for + * completion at the caller's pace. + * + * QDMA transfer strategy + * ---------------------- + * At creation time, design_writer_open_qpair() allocates a QDMA queue pair in + * Host-to-Card (H2C) memory-mapped mode, starts it, and obtains a file + * descriptor for the queue. The bitstream is then written via standard POSIX + * write()/lseek() calls on that fd at offset VRTD_DESIGN_WRITER_SEEK_ADDR + * (0x102100000), which the QDMA subsystem translates into DMA writes to the + * FPGA's configuration memory. The entire bitstream (up to 1 GiB) is read + * into a contiguous, page-aligned userspace buffer first, then written out in + * whatever chunks the kernel accepts. + * + * Error propagation + * ----------------- + * Errors that occur inside the worker thread are captured as an errno value in + * writer->last_error. The main thread retrieves this value either by: + * - Returning from design_writer_submit_fd(), which checks last_error after + * the condvar wait. + * - Calling design_writer_poll_result(), which snapshots both the busy flag + * and last_error under the mutex. + * If the writer is torn down (stop == true) while a transfer is in flight, + * poll_result reports ECANCELED. + * + * Lifecycle + * --------- + * design_writer_create() -- allocate + init (qpair, mutex/cond, thread) + * ... submit / poll ... + * cleanup_design_writer() -- signal stop, join thread, release qpair, free + */ + +#define _GNU_SOURCE + +#include "design_writer.h" +#include "utils.h" + +#include +#include +#include +#include +#include +#include + +#include +#include + + +/* QDMA queue pair configuration constants */ +#define VRTD_QDMA_Q_MODE_MM 0u /* Memory-mapped (MM) mode for the QDMA queue */ +#define VRTD_QDMA_DIR_H2C (1u << 0) /* Host-to-Card direction flag */ +#define VRTD_QDMA_DIR_C2H (1u << 1) /* Card-to-Host direction flag (unused here) */ +#define VRTD_QDMA_RING_SZ_IDX 9u /* Ring size index used for H2C/C2H/completion rings */ + +/* + * The fixed QDMA address at which bitstream data must be written. + * This is the device-side offset where the FPGA configuration logic + * expects the bitstream payload. + */ +#define VRTD_DESIGN_WRITER_SEEK_ADDR 0x102100000ull + +/* Maximum bitstream size accepted by the design writer (1 GiB). */ +#define VRTD_DESIGN_WRITER_MAX_BYTES (1ull * 1024 * 1024 * 1024) // 1 GiB + +/* Chunk size hint (currently unused in the write loop, which lets the kernel choose). */ +#define VRTD_DESIGN_WRITER_CHUNK_BYTES 4096u + +/* Allocation granularity when reading the bitstream file into memory (2 MiB steps). */ +#define READ_ENTIRE_FILE_ALLOCATION_STEP (2 * 1024 * 1024) // 2 MiB + +static int design_writer_open_qpair(struct design_writer *writer); +static void design_writer_release_qpair(struct design_writer *writer); + +/** + * Reallocate a page-aligned buffer to a new size, copying existing data. + * + * @param bufp Pointer to the current buffer pointer (updated on success). + * @param old_size Number of bytes of valid data to copy from the old buffer. + * @param new_size Desired size of the new allocation (must be >= old_size). + * @return 0 on success, -1 on allocation failure. + * + * The new buffer is aligned to 4096 bytes (page-aligned) as required by + * QDMA DMA transfers. The old buffer is freed after the copy. + */ +static int realloc_alligned_memory(void **bufp, size_t old_size, size_t new_size) +{ + void *new_buf; + int ret = posix_memalign(&new_buf, 4096, new_size); + if (ret != 0) { + PROPAGATE_ERROR_LOG(-1, LOG_ERR, "Failed to allocate memory: %s", strerrordesc_np(ret)); + } + + memcpy(new_buf, *bufp, old_size); + + free(*bufp); + *bufp = new_buf; + return 0; +} + +/** + * Read the entire contents of a file descriptor into a page-aligned buffer. + * + * @param fd Open file descriptor to read from (not closed by this function). + * @param bufp Output: on success, receives a pointer to a page-aligned buffer + * containing the file data. The caller is responsible for freeing + * it with free(). + * @return The number of bytes read on success, or -1 on error. + * + * The buffer grows in READ_ENTIRE_FILE_ALLOCATION_STEP (2 MiB) increments. + * If the total file size exceeds VRTD_DESIGN_WRITER_MAX_BYTES (1 GiB), the + * read is aborted with an error. The buffer is always page-aligned (4096) + * to satisfy QDMA DMA alignment requirements. + */ +static ssize_t read_entire_file(int fd, void **bufp) +{ + size_t capacity = READ_ENTIRE_FILE_ALLOCATION_STEP; + size_t size = 0; + + _cleanup_(cleanup_free) + uint8_t *buf; + int ret = posix_memalign((void **)&buf, 4096, capacity); + if (ret != 0) { + PROPAGATE_ERROR_LOG(-1, LOG_ERR, "Failed to allocate memory for file buffer: %s", strerrordesc_np(ret)); + } + + for (;;) { + ssize_t n = read(fd, buf + size, capacity - size); + if (n == 0) { // EOF + break; + } + if (n == -1) { + if (errno == EINTR) { + continue; + } + PROPAGATE_ERROR_STDC_LOG(-1, LOG_ERR, "Failed to read file"); + } + size += (size_t)n; + + /* Grow the buffer if full */ + if (size == capacity) { + capacity += READ_ENTIRE_FILE_ALLOCATION_STEP; + ret = realloc_alligned_memory((void **)&buf, size, capacity); + PROPAGATE_ERROR(ret); + } + + /* Enforce the maximum bitstream size limit */ + if (capacity > VRTD_DESIGN_WRITER_MAX_BYTES) { + PROPAGATE_ERROR_LOG(-1, LOG_ERR, "File size exceeds design writer maximum supported size of %zu bytes", (size_t)VRTD_DESIGN_WRITER_MAX_BYTES); + } + } + + *bufp = buf; + buf = NULL; // ownership transferred to caller + + return (ssize_t)size; +} + +/** + * Write the full contents of a buffer to a file descriptor at a fixed position. + * + * Performs a seek-then-write loop, retrying on EINTR, until the entire buffer + * has been written. Each iteration logs progress for diagnostics. + * + * @param fd The QDMA queue pair file descriptor to write to. + * @param buf Source buffer containing bitstream data. + * @param len Number of bytes to write. + * @param pos The device-side starting offset (VRTD_DESIGN_WRITER_SEEK_ADDR). + * @return 0 on success, -1 on error (with errno set). + */ +static int write_all_at_pos(int fd, const void *buf, size_t len, off_t pos) +{ + size_t off = 0; + + while (off < len) { + LOG( + LOG_INFO, + "Attempting to write to design writer file descriptor at offset 0x%lx (progress: %zu/%zu)", + (unsigned long)(pos + off), off, len + ); + + off_t ret = lseek(fd, pos + off, SEEK_SET); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to seek design writer file descriptor to position 0x%lx", (unsigned long)(pos + off)); + + ssize_t n = write(fd, (const uint8_t *)buf + off, len - off); + if (n == -1) { + if (errno == EINTR) { + continue; + } + PROPAGATE_ERROR_STDC_LOG(-1, LOG_ERR, "Failed to write to design writer file descriptor"); + } + if (n == 0) { + errno = EIO; + PROPAGATE_ERROR_STDC_LOG(-1, LOG_ERR, "Short write to design writer file descriptor"); + } + + off += (size_t)n; + + LOG( + LOG_INFO, + "Design writer: wrote %zu bytes at offset 0x%lx (total written: %zu/%zu)", + (size_t)n, (unsigned long)(pos + off), off, len + ); + } + + return 0; +} + +/** + * Perform the complete bitstream transfer: read the input fd, write to QDMA. + * + * This is the core transfer routine called by the worker thread. It: + * 1. Reads the entire bitstream from @input_fd into a page-aligned buffer. + * 2. Writes the buffer to the QDMA device fd at VRTD_DESIGN_WRITER_SEEK_ADDR. + * + * The commented-out qpair open/release calls indicate that the qpair is now + * opened once at design_writer creation time and kept open for the lifetime + * of the writer, rather than being opened and closed per-transfer. + * + * @param writer The design_writer instance (provides the QDMA fd). + * @param input_fd File descriptor containing the bitstream data to program. + * @return 0 on success, -1 on error (errno set). + */ +static int design_writer_transfer(struct design_writer *writer, int input_fd) +{ + _cleanup_(cleanup_free) + void *file_data = NULL; + ssize_t bytes_read = read_entire_file(input_fd, &file_data); + PROPAGATE_ERROR_LOG(bytes_read, LOG_ERR, "Failed to read entire input file for design writer transfer"); + + // int ret = design_writer_open_qpair(writer); + // PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to initialize design writer qpair"); + + int ret = write_all_at_pos(writer->fd, file_data, (size_t)bytes_read, VRTD_DESIGN_WRITER_SEEK_ADDR); + int saved_errno = errno; + // design_writer_release_qpair(writer); + // errno = saved_errno; + // PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to transfer design writer payload"); + + return 0; +} + +/** + * Worker thread entry point for asynchronous bitstream programming. + * + * This thread runs for the entire lifetime of the design_writer. It follows + * a producer-consumer loop: + * + * 1. Wait on the condvar for either a new input_fd to be submitted or a + * stop request. + * 2. On stop, exit the loop and return. + * 3. On new input_fd, take ownership, enable cancellation (so that + * cleanup_design_writer can cancel us during a long transfer), then + * perform the QDMA transfer. + * 4. On completion, close the input fd, clear the busy flag, store the + * error result in last_error, and broadcast the condvar to wake any + * threads waiting for the result. + * + * Cancellation is disabled while touching shared state (input_fd, busy, + * last_error) and only enabled during the actual transfer to avoid leaving + * the mutex in a locked state if the thread is cancelled. + * + * @param arg Pointer to the owning design_writer struct. + * @return Always NULL. + */ +static void *design_writer_thread(void *arg) +{ + struct design_writer *writer = arg; + + (void) pthread_setcancelstate(PTHREAD_CANCEL_DISABLE, NULL); + (void) pthread_setcanceltype(PTHREAD_CANCEL_DEFERRED, NULL); + + for (;;) { + /* Wait for work: either an input fd to process or a stop signal */ + (void) pthread_mutex_lock(&writer->mutex); + while (!writer->stop && writer->input_fd < 0) { + (void) pthread_cond_wait(&writer->cond, &writer->mutex); + } + if (writer->stop) { + (void) pthread_mutex_unlock(&writer->mutex); + break; + } + + int input_fd = writer->input_fd; + (void) pthread_mutex_unlock(&writer->mutex); + + int transfer_errno = 0; + + /* + * Enable cancellation during the transfer so that + * design_writer_release_resources() can cancel a long-running + * transfer during teardown. + */ + (void) pthread_setcancelstate(PTHREAD_CANCEL_ENABLE, NULL); + LOG(LOG_INFO, "Design writer transfer starting"); + if (input_fd >= 0) { + if (design_writer_transfer(writer, input_fd) != 0) { + /* Capture the errno from the failed transfer */ + transfer_errno = (errno != 0) ? errno : EIO; + LOG( + LOG_WARNING, + "Design writer transfer failed: %m" + ); + } + (void) close(input_fd); + } + (void) pthread_setcancelstate(PTHREAD_CANCEL_DISABLE, NULL); + + /* + * Publish the result: clear busy, store the error, and wake + * any thread waiting in submit_fd() or poll_result(). + */ + (void) pthread_mutex_lock(&writer->mutex); + writer->input_fd = -1; + writer->busy = false; + writer->last_error = transfer_errno; + (void) pthread_cond_broadcast(&writer->cond); + (void) pthread_mutex_unlock(&writer->mutex); + } + + return NULL; +} + +/** + * Cleanup helper: close a file descriptor and reset it to -1. + */ +static void cleanup_close_fd(int *fdp) +{ + if (fdp == NULL || *fdp < 0) { + return; + } + + (void) close(*fdp); + *fdp = -1; +} + +/** + * Cleanup helper for _cleanup_ attribute: unlock a mutex pointer-to-pointer. + * + * Used with the _cleanup_ attribute to ensure a mutex is unlocked when the + * variable goes out of scope, providing exception-safe locking. + */ +static void cleanup_mutex_unlockp(pthread_mutex_t **mutexp) +{ + if (mutexp == NULL || *mutexp == NULL) { + return; + } + + (void) pthread_mutex_unlock(*mutexp); + *mutexp = NULL; +} + +/** + * Release the QDMA queue pair resources associated with the design writer. + * + * Stops the queue pair (if started), deletes it (if created), and closes + * the QDMA file descriptor. Errors during stop/delete are logged as + * warnings but do not prevent further cleanup. + * + * @param writer The design_writer whose qpair resources should be released. + */ +static void design_writer_release_qpair(struct design_writer *writer) +{ + if (writer == NULL) { + return; + } + + cleanup_close_fd(&writer->fd); + + if (writer->qpair_created && writer->qdma != NULL) { + if (writer->qpair_started && slash_qdma_qpair_stop(writer->qdma, writer->qid) == -1) { + LOG( + LOG_WARNING, + "Error stopping design writer qpair %u: %m (ignored)", + writer->qid + ); + } + + if (slash_qdma_qpair_del(writer->qdma, writer->qid) == -1) { + LOG( + LOG_WARNING, + "Error deleting design writer qpair %u: %m (ignored)", + writer->qid + ); + } + } + + writer->qid = 0; + writer->qpair_started = false; + writer->qpair_created = false; +} + +/** + * Tear down all resources owned by the design writer. + * + * This function orchestrates a clean shutdown: + * 1. Signal the worker thread to stop (set stop flag, broadcast condvar). + * 2. Cancel and join the worker thread. + * 3. Close any pending input fd. + * 4. Release the QDMA queue pair. + * 5. Destroy the mutex and condition variable. + * + * @param writer The design_writer to tear down. + */ +static void design_writer_release_resources(struct design_writer *writer) +{ + if (writer->mutex_initialized) { + (void) pthread_mutex_lock(&writer->mutex); + writer->stop = true; + if (writer->cond_initialized) { + (void) pthread_cond_broadcast(&writer->cond); + } + (void) pthread_mutex_unlock(&writer->mutex); + } + + if (writer->thread_started) { + (void) pthread_cancel(writer->thread); + (void) pthread_join(writer->thread, NULL); + writer->thread_started = false; + } + + cleanup_close_fd(&writer->input_fd); + design_writer_release_qpair(writer); + + writer->qdma = NULL; + + if (writer->cond_initialized) { + (void) pthread_cond_destroy(&writer->cond); + writer->cond_initialized = false; + } + if (writer->mutex_initialized) { + (void) pthread_mutex_destroy(&writer->mutex); + writer->mutex_initialized = false; + } +} + +/** + * Cleanup helper for _cleanup_ attribute: release design writer resources. + * + * Used as a rollback guard during design_writer_init(); if init fails + * partway through, this cleanup function ensures all partially-initialized + * resources are properly released. + */ +static void cleanup_design_writer_resourcesp(struct design_writer **writerp) +{ + if (writerp == NULL || *writerp == NULL) { + return; + } + + design_writer_release_resources(*writerp); +} + +/** + * Initialize the mutex and condition variable used for thread synchronization. + * + * @param writer The design_writer whose sync primitives should be initialized. + * @return 0 on success, -1 on failure. + */ +static int design_writer_init_sync_primitives(struct design_writer *writer) +{ + int pthread_ret = pthread_mutex_init(&writer->mutex, NULL); + int ret = pthread_ret == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_ERR, + "Failed to initialize design writer mutex (code=%d)", + pthread_ret + ); + writer->mutex_initialized = true; + + pthread_ret = pthread_cond_init(&writer->cond, NULL); + ret = pthread_ret == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_ERR, + "Failed to initialize design writer condition variable (code=%d)", + pthread_ret + ); + writer->cond_initialized = true; + + return 0; +} + +/** + * Set up a QDMA queue pair for bitstream transfer. + * + * Allocates a new QDMA queue pair in Memory-Mapped (MM) mode with + * Host-to-Card (H2C) direction, starts it, and obtains a file descriptor + * for performing write() calls that translate to DMA transfers. + * + * The queue pair configuration: + * - Mode: MM (memory-mapped, not streaming) + * - Direction: H2C only (host writes bitstream to card) + * - Ring size: Index 9 for all rings (H2C, C2H, completion) + * + * On failure, any partially-created queue pair is cleaned up before returning. + * + * @param writer The design_writer to set up the qpair for. + * @return 0 on success, -1 on failure. + */ +static int design_writer_open_qpair(struct design_writer *writer) +{ + struct slash_qdma_qpair_add qpair = {0}; + qpair.size = sizeof(qpair); + qpair.mode = VRTD_QDMA_Q_MODE_MM; + qpair.dir_mask = VRTD_QDMA_DIR_H2C; + qpair.h2c_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.c2h_ring_sz = VRTD_QDMA_RING_SZ_IDX; + qpair.cmpt_ring_sz = VRTD_QDMA_RING_SZ_IDX; + + int ret = slash_qdma_qpair_add(writer->qdma, &qpair); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to add design writer QDMA qpair"); + + writer->qid = qpair.qid; + writer->qpair_created = true; + writer->qpair_started = false; + + ret = slash_qdma_qpair_start(writer->qdma, writer->qid); + if (ret == -1) { + LOG(LOG_ERR, "Failed to start design writer QDMA qpair: %m"); + design_writer_release_qpair(writer); + return -1; + } + writer->qpair_started = true; + + /* Obtain the file descriptor for the started queue pair. + * Subsequent lseek()+write() calls on this fd perform DMA transfers + * to the device at the specified offset. */ + writer->fd = slash_qdma_qpair_get_fd(writer->qdma, writer->qid, O_CLOEXEC); + if (writer->fd == -1) { + LOG(LOG_ERR, "Failed to get design writer QDMA file descriptor: %m"); + design_writer_release_qpair(writer); + return -1; + } + + return 0; +} + +/** + * Create and start the worker thread for asynchronous bitstream transfers. + * + * @param writer The design_writer whose thread should be started. + * @return 0 on success, -1 on failure. + */ +static int design_writer_start_thread(struct design_writer *writer) +{ + int pthread_ret = pthread_create(&writer->thread, NULL, design_writer_thread, writer); + int ret = pthread_ret == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_ERR, + "Failed to create design writer thread (code=%d)", + pthread_ret + ); + + writer->thread_started = true; + return 0; +} + +/** + * Initialize a design_writer struct with all required resources. + * + * Performs the full initialization sequence: + * 1. Zero-initialize the struct and store the QDMA handle. + * 2. Open a QDMA queue pair (allocate, start, get fd). + * 3. Initialize synchronization primitives (mutex, condvar). + * 4. Start the worker thread. + * + * Uses a _cleanup_ rollback guard: if any step fails, all resources + * initialized up to that point are automatically released. + * + * @param writer Pre-allocated design_writer struct to initialize. + * @param qdma QDMA subsystem handle (non-owning reference; must outlive the writer). + * @return 0 on success, -1 on failure. + */ +static int design_writer_init(struct design_writer *writer, struct slash_qdma *qdma) +{ + PROPAGATE_ERROR_NULL_LOG(writer, LOG_ERR, "Failed to initialize design writer: invalid writer"); + PROPAGATE_ERROR_NULL_LOG(qdma, LOG_ERR, "Failed to initialize design writer: invalid qdma"); + + *writer = (struct design_writer) { + .qdma = qdma, + .qid = 0, + .fd = -1, + .qpair_created = false, + .qpair_started = false, + .thread = 0, + .input_fd = -1, + .busy = false, + .stop = false, + .last_error = 0, + .thread_started = false, + .mutex_initialized = false, + .cond_initialized = false, + }; + + /* Rollback guard: if any step below fails, cleanup_design_writer_resourcesp + * is invoked automatically to release everything initialized so far. */ + _cleanup_(cleanup_design_writer_resourcesp) + struct design_writer *writer_rollback = writer; + + int ret = design_writer_open_qpair(writer); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to initialize design writer qpair"); + + ret = design_writer_init_sync_primitives(writer); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to initialize design writer synchronization primitives"); + + ret = design_writer_start_thread(writer); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to start design writer worker thread"); + + /* Initialization succeeded -- disarm the rollback guard */ + writer_rollback = NULL; + + return 0; +} + +/** + * Internal creation helper that returns errors via return value. + * + * Allocates a design_writer on the heap and initializes it. On success, + * ownership is transferred to *writerp. On failure, all resources are + * cleaned up and *writerp is left unchanged. + * + * @param qdma QDMA subsystem handle. + * @param writerp Output pointer to receive the new design_writer. + * @return 0 on success, -1 on failure. + */ +static int design_writer_create_internal(struct slash_qdma *qdma, struct design_writer **writerp) +{ + PROPAGATE_ERROR_NULL_LOG(writerp, LOG_ERR, "Failed to create design writer: invalid output pointer"); + + _cleanup_(cleanup_design_writerp) + struct design_writer *writer = calloc(1, sizeof(*writer)); + PROPAGATE_ERROR_NULL_STDC_LOG(writer, LOG_ERR, "Failed to allocate design writer"); + + int ret = design_writer_init(writer, qdma); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to initialize design writer"); + + *writerp = writer; + writer = NULL; /* ownership transferred to caller */ + + return 0; +} + +/** + * Create a new design_writer for asynchronous bitstream programming. + * + * Allocates and fully initializes a design_writer, including: + * - A QDMA queue pair in H2C memory-mapped mode + * - A mutex and condition variable for thread synchronization + * - A background worker thread ready to accept bitstream transfers + * + * The returned writer is immediately ready for design_writer_submit_fd() or + * design_writer_submit_fd_async() calls. + * + * @param qdma QDMA subsystem handle (must remain valid for the lifetime of + * the returned writer). + * @return A fully initialized design_writer on success, or NULL on failure. + * The caller must eventually call cleanup_design_writer() to free it. + */ +struct design_writer *design_writer_create(struct slash_qdma *qdma) +{ + struct design_writer *writer = NULL; + if (design_writer_create_internal(qdma, &writer) == -1) { + return NULL; + } + + return writer; +} + +/** + * Submit a bitstream fd and block until the transfer completes. + * + * This is the synchronous convenience wrapper. It calls + * design_writer_submit_fd_async() to hand the fd to the worker thread, + * then waits on the condvar until the worker sets busy = false. + * + * On return, the fd has been consumed (closed by the worker thread) regardless + * of success or failure -- the caller must not close it. + * + * @param writer The design_writer instance. + * @param fd Open file descriptor containing the bitstream data. + * Ownership is transferred to the worker thread. + * @return 0 on success, -1 on failure (check logs for details). + */ +int design_writer_submit_fd(struct design_writer *writer, int fd) +{ + int ret = design_writer_submit_fd_async(writer, fd); + PROPAGATE_ERROR_LOG(ret, LOG_WARNING, "Failed to enqueue design write request"); + + int pthread_ret = pthread_mutex_lock(&writer->mutex); + ret = pthread_ret == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_ERR, + "Failed to lock design writer mutex (code=%d)", + pthread_ret + ); + _cleanup_(cleanup_mutex_unlockp) + pthread_mutex_t *locked_mutex = &writer->mutex; + + /* Block until the worker thread completes the transfer */ + while (writer->busy && !writer->stop) { + (void) pthread_cond_wait(&writer->cond, &writer->mutex); + } + + ret = writer->stop ? -1 : 0; + PROPAGATE_ERROR_LOG(ret, LOG_WARNING, "Design writer stopped before transfer completed"); + + /* Propagate any error captured by the worker thread */ + int last_error = writer->last_error; + ret = last_error == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_WARNING, + "Design writer transfer failed (code=%d)", + last_error + ); + + return 0; +} + +/** + * Submit a bitstream fd for asynchronous transfer (non-blocking). + * + * Enqueues the given file descriptor for the worker thread to process. + * The caller retains no ownership of @fd after this call succeeds -- the + * worker thread will close it when the transfer completes. + * + * Only one transfer may be in flight at a time. If the writer is already + * busy, stopping, or has a pending input fd, this call fails with -1. + * + * After calling this function, use design_writer_poll_result() to check + * whether the transfer has completed and retrieve any error. + * + * @param writer The design_writer instance. + * @param fd Open file descriptor containing bitstream data. + * Ownership transfers to the worker on success. + * @return 0 on success (fd enqueued), -1 on failure (writer busy/stopping, + * or invalid arguments). + */ +int design_writer_submit_fd_async(struct design_writer *writer, int fd) +{ + PROPAGATE_ERROR_NULL_LOG(writer, LOG_ERR, "design_writer_submit_fd_async called with null writer"); + PROPAGATE_ERROR_LOG( + (fd >= 0) ? 0 : -1, + LOG_ERR, + "design_writer_submit_fd_async called with invalid fd %d", + fd + ); + + int pthread_ret = pthread_mutex_lock(&writer->mutex); + int ret = pthread_ret == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_ERR, + "Failed to lock design writer mutex (code=%d)", + pthread_ret + ); + _cleanup_(cleanup_mutex_unlockp) + pthread_mutex_t *locked_mutex = &writer->mutex; + + /* Reject if the writer is busy, stopping, or already has a pending fd */ + ret = (writer->stop || writer->busy || writer->input_fd >= 0) ? -1 : 0; + PROPAGATE_ERROR_LOG(ret, LOG_WARNING, "Design writer is busy or stopping"); + + /* Hand off the fd to the worker thread */ + writer->input_fd = fd; + writer->busy = true; + writer->last_error = 0; + (void) pthread_cond_signal(&writer->cond); + + LOG(LOG_DEBUG, "Design write enqueued fd=%d", fd); + return 0; +} + +/** + * Poll for the result of an asynchronous bitstream transfer. + * + * Non-blocking check of whether the most recent transfer has completed. + * + * @param writer The design_writer instance. + * @param done Output: set to true if no transfer is in progress + * (either completed or never started), false if busy. + * @param last_error Output: 0 if the last transfer succeeded, an errno + * value if it failed, or ECANCELED if the writer was + * stopped while a transfer was in flight. + * @return 0 on success, -1 on failure (invalid arguments or mutex error). + */ +int design_writer_poll_result(struct design_writer *writer, bool *done, int *last_error) +{ + PROPAGATE_ERROR_NULL_LOG(writer, LOG_ERR, "design_writer_poll_result called with null writer"); + PROPAGATE_ERROR_NULL_LOG(done, LOG_ERR, "design_writer_poll_result called with null done pointer"); + PROPAGATE_ERROR_NULL_LOG(last_error, LOG_ERR, "design_writer_poll_result called with null last_error pointer"); + + int pthread_ret = pthread_mutex_lock(&writer->mutex); + int ret = pthread_ret == 0 ? 0 : -1; + PROPAGATE_ERROR_LOG( + ret, + LOG_ERR, + "Failed to lock design writer mutex (code=%d)", + pthread_ret + ); + _cleanup_(cleanup_mutex_unlockp) + pthread_mutex_t *locked_mutex = &writer->mutex; + + *done = !writer->busy; + if (writer->stop) { + *done = true; + *last_error = ECANCELED; + } else { + *last_error = writer->last_error; + } + + return 0; +} + +/** + * Check whether the design writer currently has a transfer in progress. + * + * Thread-safe query of the busy flag. + * + * @param writer The design_writer instance (NULL-safe: returns false). + * @return true if a transfer is in progress, false otherwise. + */ +bool design_writer_is_busy(struct design_writer *writer) +{ + if (writer == NULL) { + return false; + } + + (void) pthread_mutex_lock(&writer->mutex); + bool busy = writer->busy; + (void) pthread_mutex_unlock(&writer->mutex); + return busy; +} + +/** + * Destroy a design_writer and free all associated resources. + * + * Signals the worker thread to stop, joins it, releases the QDMA queue + * pair, destroys synchronization primitives, and frees the struct. + * + * After this call, @writer is invalid and must not be used. + * NULL-safe: calling with NULL is a no-op. + * + * @param writer The design_writer to destroy (may be NULL). + */ +void cleanup_design_writer(struct design_writer *writer) +{ + if (writer == NULL) { + return; + } + + design_writer_release_resources(writer); + free(writer); +} diff --git a/vrt/vrtd/src/design_writer.h b/vrt/vrtd/src/design_writer.h new file mode 100644 index 00000000..50b377c0 --- /dev/null +++ b/vrt/vrtd/src/design_writer.h @@ -0,0 +1,171 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file design_writer.h + * @brief Asynchronous FPGA bitstream writer for SLASH devices. + * + * Writing a bitstream to an FPGA can take several seconds. To avoid blocking + * the single-threaded event loop, the design_writer offloads the actual QDMA + * transfer to a background pthread and exposes an async polling API: + * + * 1. @c design_writer_submit_fd_async -- hand off a bitstream fd to the + * background thread. Returns immediately. + * 2. @c design_writer_poll_result -- non-blocking check: has the write + * finished? If yes, retrieves the result code. + * 3. The event loop re-arms a deferred timer to keep polling until done. + * + * A synchronous convenience wrapper (@c design_writer_submit_fd) is also + * provided for cases where blocking is acceptable. + */ + +#ifndef VRTD_DESIGN_WRITER_H +#define VRTD_DESIGN_WRITER_H + +#include +#include +#include + +#include + +/** + * @brief State for the asynchronous FPGA bitstream writer. + * + * Internally manages a dedicated pthread that performs the blocking QDMA + * write. Synchronization between the event-loop thread and the worker + * thread uses a mutex + condition variable pair. + */ +struct design_writer { + /** @brief QDMA subsystem handle (non-owning, borrowed from struct device). */ + struct slash_qdma *qdma; /* non-owning */ + /** @brief QDMA queue ID allocated for bitstream writes. */ + uint32_t qid; + /** @brief File descriptor for the QDMA queue pair character device. */ + int fd; + /** @brief True if the QDMA queue pair has been created. */ + bool qpair_created; + /** @brief True if the QDMA queue pair has been started. */ + bool qpair_started; + + /* Worker thread and synchronization primitives */ + + /** @brief Background worker pthread handle. */ + pthread_t thread; + /** @brief Mutex protecting shared state (input_fd, busy, stop, last_error). */ + pthread_mutex_t mutex; + /** @brief Condition variable signaled when new work is submitted or stop is requested. */ + pthread_cond_t cond; + + /** @brief Bitstream file descriptor passed to the worker thread for the current write. */ + int input_fd; + /** @brief True while the worker thread is performing a write operation. */ + bool busy; + /** @brief Set to true to request the worker thread to exit its loop and terminate. */ + bool stop; + /** @brief Result code from the most recent write (0 = success, negative = error). */ + int last_error; + + /* Initialization tracking flags */ + + /** @brief True if the worker pthread has been successfully started. */ + bool thread_started; + /** @brief True if @c mutex has been initialized (for cleanup safety). */ + bool mutex_initialized; + /** @brief True if @c cond has been initialized (for cleanup safety). */ + bool cond_initialized; +}; + +/** + * @brief Create and initialize a design writer for the given QDMA subsystem. + * + * Allocates a QDMA queue pair for bitstream transfer, initializes the + * mutex/condvar, and starts the background worker thread. + * + * @param qdma QDMA subsystem handle (borrowed, must outlive the design_writer). + * @return Heap-allocated design_writer on success, NULL on failure. + */ +struct design_writer *design_writer_create(struct slash_qdma *qdma); + +/** + * @brief Submit a bitstream file descriptor for asynchronous writing. + * + * Hands the fd to the background worker thread and returns immediately. + * Use @c design_writer_poll_result to check for completion. + * + * @param writer The design writer instance. + * @param fd Open file descriptor for the bitstream (caller retains ownership). + * @return 0 on success, -1 if the writer is already busy or on error. + */ +int design_writer_submit_fd_async(struct design_writer *writer, int fd); + +/** + * @brief Submit a bitstream file descriptor and block until the write completes. + * + * Synchronous convenience wrapper around the async API. Blocks the calling + * thread until the bitstream transfer finishes. + * + * @param writer The design writer instance. + * @param fd Open file descriptor for the bitstream. + * @return 0 on success, negative errno on failure. + */ +int design_writer_submit_fd(struct design_writer *writer, int fd); + +/** + * @brief Poll for completion of an asynchronous bitstream write. + * + * Non-blocking check. When the write has finished, @p done is set to true + * and @p last_error receives the result code. + * + * @param writer The design writer instance. + * @param[out] done Set to true if the write has completed, false if still in progress. + * @param[out] last_error Set to the write result (0 = success, negative = error) when done. + * @return 0 on success, -1 on mutex error. + */ +int design_writer_poll_result(struct design_writer *writer, bool *done, int *last_error); + +/** + * @brief Check whether the design writer is currently performing a write. + * @param writer The design writer instance. + * @return True if a write is in progress, false otherwise. + */ +bool design_writer_is_busy(struct design_writer *writer); + +/** + * @brief Release all resources owned by the design writer. + * + * Signals the worker thread to stop, joins it, destroys synchronization + * primitives, and tears down the QDMA queue pair. + * + * @param writer Pointer to the design_writer to clean up. May be NULL (no-op). + */ +void cleanup_design_writer(struct design_writer *writer); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param writerp Address of a @c struct @c design_writer pointer. + */ +static inline +void cleanup_design_writerp(struct design_writer **writerp) +{ + cleanup_design_writer(*writerp); + *writerp = NULL; +} + +#endif // VRTD_DESIGN_WRITER_H diff --git a/vrt/vrtd/src/device.c b/vrt/vrtd/src/device.c new file mode 100644 index 00000000..22c4f6df --- /dev/null +++ b/vrt/vrtd/src/device.c @@ -0,0 +1,585 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file device.c + * @brief Sysfs-based device discovery and initialization for SLASH FPGA devices. + * + * This module implements the device lifecycle for the vrtd daemon. It discovers + * AMD Alveo V80 (SLASH) devices by globbing /dev/slash_ctl* character device + * nodes exposed by the kernel driver, then opens each device by: + * + * 1. Opening the control device via libslash (slash_ctldev_open). + * 2. Locating the matching QDMA control device by PCI BDF (bus:device prefix) + * via sysfs enumeration under /sys/class/misc/. + * 3. Probing all six PCI BARs and memory-mapping the usable ones. + * 4. Initializing subsystem drivers: clock driver, design writer, memory map. + * + * Teardown (cleanup_device) releases resources in reverse order to ensure + * dependent subsystems are torn down before the underlying control device. + */ + +#define _GNU_SOURCE + +#include "device.h" +#include "allocator.h" +#include "clock.h" +#include "design_writer.h" +#include "hotplug.h" +#include "utils.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int devices_open(struct device_ptr_array *devices, size_t pathc, char ** paths); +static int device_open(struct device **d, const char *path); +static bool devices_contains_path(const struct device_ptr_array *devices, const char *path); +static int device_read_pci_info(struct device *d, struct vrtd_pci_info *out); + +/** + * Find the /dev/ path of the qdma_ctl device sharing the same PCI bus:device + * as the given BDF. Returns 0 on success (path written to out_path), -1 on + * failure or no match (out_path set to NULL). + * + * The lookup works by: + * 1. Extracting the bus:device prefix from ctl_bdf (e.g., "0000:65:00" from + * "0000:65:00.1"). + * 2. Globbing /sys/class/misc/slash_qdma_ctl_.* to find any QDMA + * misc device nodes registered by the kernel driver on the same PCI slot. + * 3. Reading the uevent file under the matched sysfs entry to extract the + * DEVNAME, and prepending "/dev/" to form the full device path. + * + * @param ctl_bdf PCI BDF string of the control device (e.g., "0000:65:00.1"). + * @param out_path On success, receives a heap-allocated string with the /dev/ + * path of the QDMA device. Set to NULL if no match is found + * (which is not an error). Caller must free. + * @return 0 on success (match found or no match), -1 on I/O or allocation error. + */ +static int find_qdma_dev_path_by_bdf(const char *ctl_bdf, char **out_path) +{ + *out_path = NULL; + + char prefix[VRTD_PCI_BDF_LEN]; + if (pci_bdf_prefix(ctl_bdf, prefix) != 0) { + return -1; + } + + /* Build a glob pattern to match any QDMA misc device on the same PCI slot. */ + _cleanup_(cleanup_free) + char *pattern = NULL; + if (asprintf(&pattern, "/sys/class/misc/slash_qdma_ctl_%s.*", prefix) < 0) { + return -1; + } + + _cleanup_(globfree) + glob_t g = {0}; + int ret = glob(pattern, GLOB_ERR, NULL, &g); + if (ret != 0) { + return (ret == GLOB_NOMATCH) ? 0 : -1; + } + + if (g.gl_pathc > 1) { + LOG( + LOG_WARNING, + "Multiple QDMA devices found for BDF prefix %s; using first match", + prefix + ); + } + + const char *entry = g.gl_pathv[0]; + + /* Read the uevent file to extract the kernel-assigned DEVNAME. */ + _cleanup_(cleanup_free) + char *uevent_path = NULL; + if (asprintf(&uevent_path, "%s/uevent", entry) < 0) { + return -1; + } + + FILE *f = fopen(uevent_path, "r"); + if (f == NULL) { + return -1; + } + + /* Parse uevent line-by-line looking for DEVNAME=. */ + char line[256]; + while (fgets(line, sizeof(line), f) != NULL) { + static const char devname_key[] = "DEVNAME="; + if (strncmp(line, devname_key, sizeof(devname_key) - 1) != 0) { + continue; + } + const char *devname = line + sizeof(devname_key) - 1; + size_t len = strlen(devname); + /* Strip trailing newline/carriage return characters. */ + while (len > 0 && (devname[len - 1] == '\n' || devname[len - 1] == '\r')) { + len--; + } + if (asprintf(out_path, "/dev/%.*s", (int)len, devname) < 0) { + *out_path = NULL; + fclose(f); + return -1; + } + fclose(f); + return 0; + } + fclose(f); + + return 0; +} + +/** + * Find the /dev/ path of a slash_ctl device by its full PCI BDF string. + * + * The slash_ctl misc device is registered by the kernel driver under a + * stable sysfs name derived from the full PCI BDF (including function number), + * e.g. /sys/class/misc/slash_ctl_0000:61:00.2. The corresponding /dev/ node + * uses an incrementing counter (slash_ctlN) that changes after each hotplug + * remove+rescan cycle. This function resolves the current /dev/ path by + * reading the DEVNAME entry from the stable sysfs uevent file. + * + * @param bdf Full PCI BDF string including function (e.g. "0000:61:00.2"). + * @param out_path On success, receives a heap-allocated string with the /dev/ + * path of the slash_ctl device. Set to NULL if the device is + * not yet registered (which is not an error). Caller must free. + * @return 0 on success (device found or not yet present), -1 on I/O or + * allocation error. + */ +int find_slash_ctl_dev_path_by_bdf(const char *bdf, char **out_path) +{ + *out_path = NULL; + + _cleanup_(cleanup_free) + char *uevent_path = NULL; + if (asprintf(&uevent_path, "/sys/class/misc/slash_ctl_%s/uevent", bdf) < 0) { + return -1; + } + + FILE *f = fopen(uevent_path, "r"); + if (f == NULL) { + /* Device not yet registered in sysfs — treat as no-match, not an error. */ + return 0; + } + + char line[256]; + while (fgets(line, sizeof(line), f) != NULL) { + static const char devname_key[] = "DEVNAME="; + if (strncmp(line, devname_key, sizeof(devname_key) - 1) != 0) { + continue; + } + const char *devname = line + sizeof(devname_key) - 1; + size_t len = strlen(devname); + while (len > 0 && (devname[len - 1] == '\n' || devname[len - 1] == '\r')) { + len--; + } + if (asprintf(out_path, "/dev/%.*s", (int)len, devname) < 0) { + *out_path = NULL; + fclose(f); + return -1; + } + fclose(f); + return 0; + } + fclose(f); + return 0; +} + +/** + * Discover all SLASH control devices and open them. + * + * Enumerates device nodes by globbing /dev/slash_ctl* and opens each one + * that is not already present in the @p devices array. New devices are + * appended to the array. + * + * @param devices Array of already-opened device pointers; newly discovered + * devices are appended here. May be empty on first call. + * @return 0 on success (including the case where no devices are found), + * -1 on glob or device-open error. + */ +int devices_discover_and_open(struct device_ptr_array *devices) +{ + _cleanup_(globfree) + glob_t g = {0}; + + int ret = glob("/dev/slash_ctl*", GLOB_ERR, NULL, &g); + + if (ret == GLOB_NOMATCH) { + LOG( + LOG_WARNING, + "No devices found matching /dev/slash_ctl*" + ); + return 0; // not an error: just no devices + } + + if (ret != 0) { + LOG( + LOG_ERR, + "Error matching pattern /dev/slash_ctl*: %s", + glob_err_to_string(ret) + ); + + return -1; + } + + LOG(LOG_INFO, "Discovered %zu device(s) matching /dev/slash_ctl*", g.gl_pathc); + + return devices_open(devices, g.gl_pathc, g.gl_pathv); +} + +/** + * Open a set of devices given their /dev/ paths. + * + * Iterates over @p paths, skipping any that are already present in + * @p devices (idempotent re-discovery). Each new device is opened via + * device_open() and appended to the array with ownership transfer. + * + * @param devices Owning array of device pointers. + * @param pathc Number of paths in @p paths. + * @param paths Array of /dev/ path strings. + * @return 0 on success, -1 on error (logged). + */ +static int devices_open(struct device_ptr_array *devices, size_t pathc, char **paths) +{ + for (size_t i = 0; i < pathc; ++i) { + const char *path = paths[i]; + + if (devices_contains_path(devices, path)) { + continue; // already opened, skip + } + + _cleanup_(cleanup_devicep) + struct device *d = NULL; + + int ret = device_open(&d, path); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to open device %s", path); + + ret = device_ptr_array_push_move(devices, &d); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to allocate memory for device data"); + } + + return 0; +} + +/** + * Open a single SLASH device and initialize all its subsystems. + * + * The initialization sequence is: + * 1. Allocate the device struct and duplicate the path string. + * 2. Open the libslash control device (slash_ctldev_open) for ioctl access. + * 3. Initialize the buffer tracking array. + * 4. Create the device memory map (for BAR-based address translation). + * 5. Create the clock driver (Xilinx clock wizard access via BAR4). + * 6. Read PCI info (BDF, vendor/device IDs) via ioctl, then locate and open + * the matching QDMA device by PCI BDF prefix. + * 7. If QDMA is available, create the design writer (bitstream programming). + * 8. Probe all six PCI BARs: read bar_info and mmap usable BARs. + * + * On success, ownership of the device is transferred to *out. + * On failure, all partially-initialized resources are cleaned up automatically + * via the _cleanup_ attribute on the local device pointer. + * + * @param out Receives the fully initialized device pointer. Must not be NULL. + * @param path /dev/ path of the control device (e.g., "/dev/slash_ctl0"). + * @return 0 on success, -1 on error (logged). + */ +static int device_open(struct device **out, const char *path) +{ + PROPAGATE_ERROR_NULL_LOG(out, LOG_ERR, "Internal error: bad call of device_open: null out"); + PROPAGATE_ERROR_NULL_LOG(path, LOG_ERR, "Internal error: bad call of device_open: null path"); + + _cleanup_(cleanup_devicep) + struct device *d = calloc(1, sizeof *d); + PROPAGATE_ERROR_NULL_STDC_LOG(d, LOG_ERR, "Failed to allocate memory for device data"); + + d->path = strdup(path); + PROPAGATE_ERROR_NULL_STDC_LOG(d->path, LOG_ERR, "Failed to allocate memory for device data"); + + /* Step 1: Open the libslash control device for ioctl-based communication. */ + d->ctl = slash_ctldev_open(path); + PROPAGATE_ERROR_NULL_STDC_LOG(d->ctl, LOG_ERR, "Error opening device %s", path); + + assert(d->ctl != NULL); + + /* Step 2: Initialize tracking structures and subsystem drivers. */ + d->buffers = buffer_ptr_array_init(); + + d->memory_map = device_memory_map_create(); + PROPAGATE_ERROR_NULL_STDC_LOG(d->memory_map, LOG_ERR, "Error creating device memory map for %s", path); + + d->clock_driver = clock_driver_create(d->ctl); + PROPAGATE_ERROR_NULL_STDC_LOG(d->clock_driver, LOG_ERR, "Error creating clock driver for %s", path); + + /* Step 3: Match the QDMA ctl device by PCI BDF (bus:device prefix). */ + { + struct vrtd_pci_info pci_info = {0}; + int pci_ret = device_read_pci_info(d, &pci_info); + if (pci_ret != 0) { + LOG( + LOG_WARNING, + "Could not read PCI info for %s; skipping QDMA lookup", + d->path + ); + } else { + _cleanup_(cleanup_free) + char *qdma_path = NULL; + int find_ret = find_qdma_dev_path_by_bdf(pci_info.bdf, &qdma_path); + if (find_ret != 0) { + LOG( + LOG_WARNING, + "Error searching for QDMA device for BDF %s (%s)", + pci_info.bdf, d->path + ); + } else if (qdma_path != NULL) { + d->qdma = slash_qdma_open(qdma_path); + if (d->qdma == NULL) { + LOG( + LOG_WARNING, + "Error opening QDMA device %s (for %s): %m", + qdma_path, d->path + ); + } else { + LOG( + LOG_INFO, + "Matched QDMA device %s for ctldev %s (BDF %s)", + qdma_path, d->path, pci_info.bdf + ); + /* QDMA available -- create the design writer for bitstream programming. */ + d->design_writer = design_writer_create(d->qdma); + PROPAGATE_ERROR_NULL_STDC_LOG(d->design_writer, LOG_ERR, "Error creating design writer for %s", d->path); + } + } else { + LOG( + LOG_WARNING, + "No QDMA device found for BDF %s (%s)", + pci_info.bdf, d->path + ); + } + } + } + + /* Step 4: Probe all PCI BARs (0-5). Read metadata and mmap usable ones. */ + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_info); i++) { + d->bar_info[i] = slash_bar_info_read(d->ctl, i); + if (d->bar_info[i] == NULL) { + LOG( + LOG_ERR, + "Error opening bar_info %zu on device %s: %m", + i, d->path + ); + continue; + } + + assert(d->bar_info[i] != NULL); + + /* Only open (mmap) BARs that the kernel driver marks as usable. */ + if (d->bar_info[i]->usable) { + d->bar_files[i] = slash_bar_file_open(d->ctl, i, O_CLOEXEC); + if (d->bar_files[i] == NULL) { + LOG( + LOG_ERR, + "Error opening bar_file %zu on device %s: %m", + i, d->path + ); + } + } + } + + /* Transfer ownership to caller; set local to NULL to prevent cleanup. */ + *out = d; + d = NULL; + + return 0; +} + +/** + * Read PCI identification info from the kernel driver via ioctl. + * + * Populates @p out with the device's BDF string, vendor/device IDs, and + * subsystem vendor/device IDs. Also caches the info in d->pci_info. + * + * @param d Device with an open control device (d->ctl). + * @param out Receives the PCI info. Zeroed before filling. + * @return 0 on success, -1 on error (logged). + */ +static int device_read_pci_info(struct device *d, struct vrtd_pci_info *out) +{ + PROPAGATE_ERROR_NULL_LOG(d, LOG_ERR, "Internal error: bad call of device_read_pci_info: null device"); + PROPAGATE_ERROR_NULL_LOG(d->ctl, LOG_ERR, "Internal error: bad call of device_read_pci_info: null device->ctl"); + + memset(out, 0, sizeof(*out)); + + struct slash_ioctl_device_info info = {0}; + info.size = sizeof(info); + + int ret = ioctl(d->ctl->fd, SLASH_CTLDEV_IOCTL_GET_DEVICE_INFO, &info); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Could not get bar info for device: %s", d->path); + + // Copy pci information + { + (void) strncpy(out->bdf, info.bdf, VRTD_PCI_BDF_LEN); + + /* Strip the function digit (.F) from the kernel's BDF string. + * vrtd identifies devices at the board level (DDDD:BB:DD), not + * at the individual physical function level. PF-specific BDFs + * are constructed on the fly when needed (e.g. for hotplug ioctls) + * using pci_bdf_set_function(). */ + { + char *dot = strrchr(out->bdf, '.'); + if (dot != NULL) { + LOG(LOG_INFO, + "Stripping PF function %s from kernel BDF %s; " + "device tracked as board %.*s", + dot, info.bdf, (int)(dot - out->bdf), out->bdf); + *dot = '\0'; + } + } + + out->vendor_id = info.vendor_id; + out->device_id = info.device_id; + out->subsystem_vendor_id = info.subsystem_vendor_id; + out->subsystem_device_id = info.subsystem_device_id; + + d->pci_info = *out; + } + + return 0; +} + +/** + * Check whether a device with the given /dev/ path is already in the array. + * + * Used during re-discovery to avoid opening the same device twice. + * + * @param devices Array of opened devices. + * @param path /dev/ path to search for. + * @return true if a device with a matching path exists, false otherwise. + */ +static bool devices_contains_path(const struct device_ptr_array *devices, const char *path) +{ + if (!devices || !path) return false; + + for (size_t i = 0; i < devices->len; ++i) { + const struct device *d = devices->d[i]; + if (d && d->path && strcmp(d->path, path) == 0) { + return true; + } + } + return false; +} + +/** + * Release all resources held by a device, in reverse initialization order. + * + * Teardown sequence: + * 1. Free DMA buffers. + * 2. Destroy the design writer (QDMA bitstream programming). + * 3. Destroy the device memory map. + * 4. Destroy the clock driver (BAR4 clock wizard access). + * 5. Close the QDMA device. + * 6. Close all opened BAR file mappings. + * 7. Free BAR info metadata. + * 8. Close the libslash control device. + * 9. Free the path string and the device struct itself. + * + * Safe to call with NULL (no-op). Errors during close are logged as + * warnings but do not prevent further cleanup. + * + * @param d Device to clean up, or NULL. + */ +void cleanup_device(struct device *d) +{ + if (d == NULL) { + return; + } + + LOG(LOG_DEBUG, "Cleaning up device %s", d->path ? d->path : "(unknown)"); + + buffer_ptr_array_free(&d->buffers); + + if (d->design_writer != NULL) { + cleanup_design_writer(d->design_writer); + d->design_writer = NULL; + } + + if (d->memory_map != NULL) { + device_memory_map_cleanup(d->memory_map); + d->memory_map = NULL; + } + + if (d->clock_driver != NULL) { + cleanup_clock_driver(d->clock_driver); + d->clock_driver = NULL; + } + + if (d->qdma != NULL) { + if (slash_qdma_close(d->qdma) != 0) { + LOG( + LOG_WARNING, + "Error closing qdma device for %s: %m (ignored)", + d->path ? d->path : "(unknown)" + ); + } + d->qdma = NULL; + } + + /* Close any opened BAR files */ + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_files); i++) { + if (d->bar_files[i] != NULL) { + if (slash_bar_file_close(d->bar_files[i]) != 0) { + LOG( + LOG_WARNING, + "Error closing bar_file %zu for %s: %m (ignored)", + i, d->path ? d->path : "(unknown)" + ); + } + d->bar_files[i] = NULL; + } + } + + /* Free bar info data */ + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_info); i++) { + if (d->bar_info[i] != NULL) { + slash_bar_info_free(d->bar_info[i]); + d->bar_info[i] = NULL; + } + } + + /* Close control device last */ + if (d->ctl != NULL) { + if (slash_ctldev_close(d->ctl) != 0) { + LOG( + LOG_WARNING, + "Error closing ctldevice %s: %m (ignored)", + d->path ? d->path : "(unknown)" + ); + } + d->ctl = NULL; + } + + free(d->path); + d->path = NULL; + + free(d); +} diff --git a/vrt/vrtd/src/device.h b/vrt/vrtd/src/device.h new file mode 100644 index 00000000..abad8c5d --- /dev/null +++ b/vrt/vrtd/src/device.h @@ -0,0 +1,129 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file device.h + * @brief SLASH FPGA device representation for the vrtd daemon. + * + * Each physical SLASH V80 FPGA device discovered at daemon startup is + * represented by a @c struct @c device. The struct aggregates the libslash + * control and QDMA handles, per-BAR metadata and mmap'd file regions, + * and per-device subsystems (design writer, clock driver, memory allocator). + * + * PCI BARs are indexed 0-5, matching the PCI specification. Not all BARs + * may be present on every device; absent BARs have NULL entries. + */ + +#ifndef VRTD_DEVICE_H +#define VRTD_DEVICE_H + +#include + +#include +#include + +#include "array.h" +#include "buffer.h" + +struct design_writer; +struct clock_driver; +struct device_memory_map; + +/** + * @brief Represents a single discovered SLASH FPGA device. + * + * Owns all per-device resources: libslash handles, BAR mappings, subsystem + * drivers, DMA buffers, and the HBM/DDR memory map allocator. + */ +struct device { + /** @brief Sysfs path of this device (e.g. "/sys/bus/pci/devices/0000:03:00.0"). + * Heap-allocated, owning. */ + char *path; /* owning */ + /** @brief libslash control device handle for ioctl operations (owning). */ + struct slash_ctldev *ctl; + /** @brief libslash QDMA subsystem handle for DMA queue management (owning). */ + struct slash_qdma *qdma; + /** @brief BAR metadata (size, flags, physical address) for each of the 6 PCI BARs. + * NULL if the BAR is not present or not mapped. Owning pointers. */ + struct slash_ioctl_bar_info *bar_info[6]; + /** @brief Memory-mapped BAR file regions for each of the 6 PCI BARs. + * NULL if the BAR is not present or not mapped. Owning pointers. */ + struct slash_bar_file *bar_files[6]; + /** @brief Asynchronous FPGA bitstream writer subsystem (owning, may be NULL). */ + struct design_writer *design_writer; + /** @brief Clock frequency control subsystem via AXI clock wizard (owning, may be NULL). */ + struct clock_driver *clock_driver; + /** @brief HBM/DDR address-range allocator for DMA buffer placement (owning, may be NULL). */ + struct device_memory_map *memory_map; + /** @brief Currently allocated DMA buffers on this device (owning array). */ + struct buffer_ptr_array buffers; + /** @brief PCI identity (vendor/device ID, BDF address) reported to clients. */ + struct vrtd_pci_info pci_info; +}; + +/** + * @brief Release all resources owned by a device (handles, mappings, subsystems, buffers). + * @param d Pointer to the device to clean up. + */ +void cleanup_device(struct device *d); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * @param d Address of a @c struct @c device pointer. + */ +static inline +void cleanup_devicep(struct device **d) +{ + cleanup_device(*d); + + *d = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(device_ptr_array, struct device *, cleanup_device); + +/** + * @brief Discover all SLASH FPGA devices on the system and open them. + * + * Enumerates PCI devices via sysfs, opens libslash control and QDMA handles, + * maps BARs, and initializes per-device subsystems (design writer, clock + * driver, memory allocator). + * + * @param[out] devices Array to populate with discovered device pointers. + * The array takes ownership of all allocated devices. + * @return 0 on success, -1 on error (partially discovered devices are cleaned up). + */ +int devices_discover_and_open(struct device_ptr_array *devices); + +/** + * @brief Find the current /dev/slash_ctlN path for a PF2 device by its full BDF. + * + * The /dev node suffix is assigned by an incrementing kernel counter and changes + * after each hotplug remove+rescan cycle. This function resolves the current + * path by reading the stable sysfs uevent file at + * /sys/class/misc/slash_ctl_/uevent. + * + * @param bdf Full PCI BDF including function number (e.g. "0000:61:00.2"). + * @param out_path On success, receives a heap-allocated /dev/ path string, or + * NULL if the device is not yet registered. Caller must free. + * @return 0 on success (device found or absent), -1 on I/O or allocation error. + */ +int find_slash_ctl_dev_path_by_bdf(const char *bdf, char **out_path); + +#endif // VRTD_DEVICE_H diff --git a/vrt/vrtd/src/hotplug.c b/vrt/vrtd/src/hotplug.c new file mode 100644 index 00000000..c767b1b9 --- /dev/null +++ b/vrt/vrtd/src/hotplug.c @@ -0,0 +1,197 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file hotplug.c + * @brief PCIe hotplug operations wrapper and PCI BDF string utilities. + * + * This module manages the global slash_hotplug handle used to perform PCIe + * hotplug operations (secondary bus reset, device removal/rescan) on V80 + * FPGA cards. Because the hotplug subsystem operates on the host's PCIe + * topology (not a per-device resource), a single global handle is sufficient. + * + * The file also provides helper functions for manipulating PCI Bus/Device/ + * Function (BDF) address strings (e.g. "0000:65:00.2"), which are used + * throughout vrtd when addressing specific PCIe functions of a multi-function + * FPGA device. + */ + +#define _GNU_SOURCE + +#include "hotplug.h" +#include "utils.h" + +#include +#include +#include + +/* Global hotplug handle -- singleton because the hotplug subsystem is + * host-wide, not per-device. */ +struct slash_hotplug *g_hotplug = NULL; + +/** + * Open the global hotplug handle. Called once at daemon startup from + * globals_init(). The NULL argument requests the default hotplug + * provider (sysfs-based on Linux). + */ +void hotplug_global_init(void) +{ + g_hotplug = slash_hotplug_open(NULL); + if (g_hotplug == NULL) + LOG(LOG_ERR, "Failed to open hotplug device: %m"); +} + +/** + * Close the global hotplug handle and NULL the pointer. Called once at + * daemon shutdown from globals_destroy(). + */ +void hotplug_global_destroy(void) +{ + slash_hotplug_close(g_hotplug); + g_hotplug = NULL; +} + +/** + * Translate a POSIX errno from the hotplug subsystem into a vrtd wire + * protocol return code. This keeps the errno-to-wire mapping in one + * place so that all hotplug-related request handlers return consistent + * error codes to clients. + */ +uint16_t hotplug_errno_to_vrtd_ret(int err) +{ + switch (err) { + case EINVAL: + return VRTD_RET_INVALID_ARGUMENT; + case ENODEV: + return VRTD_RET_NOEXIST; + case EBUSY: + return VRTD_RET_BUSY; + case EPERM: + case EACCES: + return VRTD_RET_AUTH_ERROR; + default: + return VRTD_RET_INTERNAL_ERROR; + } +} + +/** + * Extract the BDF prefix (domain:bus:device) from a full BDF string, + * stripping the ".function" suffix. + * + * Examples: + * "0000:65:00.2" -> "0000:65:00" + * "0000:65:00" -> "0000:65:00" (already board-level, returned as-is) + * + * This is used when operating on the PCIe slot as a whole (e.g. secondary + * bus reset affects all functions under the same bus:device). + * + * @param bdf NUL-terminated BDF string (with or without .F suffix). + * @param out_prefix Output buffer of at least VRTD_PCI_BDF_LEN bytes. + * @return 0 on success, -1 with errno set on failure. + */ +int pci_bdf_prefix(const char *bdf, char out_prefix[VRTD_PCI_BDF_LEN]) +{ + if (bdf == NULL || out_prefix == NULL) { + errno = EINVAL; + return -1; + } + + const char *dot = strrchr(bdf, '.'); + if (dot == NULL || dot == bdf) { + /* No dot — input is already board-level (DDDD:BB:DD). Copy as-is. */ + size_t len = strlen(bdf); + if (len == 0 || len >= VRTD_PCI_BDF_LEN) { + errno = (len == 0) ? EINVAL : ENAMETOOLONG; + return -1; + } + memcpy(out_prefix, bdf, len); + out_prefix[len] = '\0'; + return 0; + } + + size_t prefix_len = (size_t)(dot - bdf); + if (prefix_len >= VRTD_PCI_BDF_LEN) { + errno = ENAMETOOLONG; + return -1; + } + + memcpy(out_prefix, bdf, prefix_len); + out_prefix[prefix_len] = '\0'; + + return 0; +} + +/** + * Produce a new BDF string with a specific function number. + * + * Accepts both full BDF ("0000:65:00.0") and board-level ("0000:65:00") input. + * In both cases, the output is "DDDD:BB:DD.F" with the requested function digit. + * + * Examples: + * pci_bdf_set_function("0000:65:00.0", 2, out) -> out = "0000:65:00.2" + * pci_bdf_set_function("0000:65:00", 2, out) -> out = "0000:65:00.2" + * + * V80 FPGA devices expose multiple PCIe functions (e.g. function 0 for QDMA, + * function 1 for management). This helper lets the daemon address a specific + * function given a board-level or PF-level BDF. + * + * @param bdf NUL-terminated source BDF string (with or without .F). + * @param func New function number (0-7). + * @param out_bdf Output buffer of at least VRTD_PCI_BDF_LEN bytes. + * @return 0 on success, -1 with errno set on failure. + */ +int pci_bdf_set_function(const char *bdf, uint8_t func, char out_bdf[VRTD_PCI_BDF_LEN]) +{ + if (bdf == NULL || out_bdf == NULL || func > 7) { + errno = EINVAL; + return -1; + } + + size_t len = strnlen(bdf, VRTD_PCI_BDF_LEN); + if (len == 0 || len >= VRTD_PCI_BDF_LEN) { + errno = EINVAL; + return -1; + } + + /* Find the "domain:bus:device" prefix length. If the input contains + * a '.', the prefix is everything before it. Otherwise the entire + * string is the prefix (board-level BDF without function digit). */ + const char *dot = strrchr(bdf, '.'); + size_t prefix_len; + if (dot != NULL && dot != bdf) { + prefix_len = (size_t)(dot - bdf); + } else { + prefix_len = len; + } + + if (prefix_len + 2 >= VRTD_PCI_BDF_LEN) { + errno = ENAMETOOLONG; + return -1; + } + + /* Reconstruct: copy the "domain:bus:device" prefix, then append + * ".N" where N is the requested function number. */ + memcpy(out_bdf, bdf, prefix_len); + out_bdf[prefix_len] = '.'; + out_bdf[prefix_len + 1] = (char)('0' + func); + out_bdf[prefix_len + 2] = '\0'; + + return 0; +} diff --git a/vrt/vrtd/src/hotplug.h b/vrt/vrtd/src/hotplug.h new file mode 100644 index 00000000..de1720c2 --- /dev/null +++ b/vrt/vrtd/src/hotplug.h @@ -0,0 +1,41 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_HOTPLUG_H +#define VRTD_HOTPLUG_H + +#include +#include + +// Hotplug is a single device so it can be a global. +extern struct slash_hotplug *g_hotplug; + +void hotplug_global_init(void); +void hotplug_global_destroy(void); + +uint16_t hotplug_errno_to_vrtd_ret(int err); + +// Helper function but useful and generally used with hotplug +int pci_bdf_set_function(const char *bdf, uint8_t func, char out_bdf[VRTD_PCI_BDF_LEN]); + +// Extract BDF prefix (bus:device without function), e.g. "0000:65:00.2" -> "0000:65:00" +int pci_bdf_prefix(const char *bdf, char out_prefix[VRTD_PCI_BDF_LEN]); + +#endif diff --git a/vrt/vrtd/src/main.c b/vrt/vrtd/src/main.c new file mode 100644 index 00000000..05fe2d18 --- /dev/null +++ b/vrt/vrtd/src/main.c @@ -0,0 +1,351 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "config.h" +#include "array.h" +#include "utils.h" +#include "state.h" +#include "accept.h" +#include "device.h" +#include "signals.h" +#include "hotplug.h" + +/* + * The deferred work timer fires every 20ms to poll for completion of + * asynchronous design writes (e.g. bitstream loads to the FPGA fabric). + * These operations are initiated by client requests but complete + * asynchronously via the QDMA subsystem; a 20ms polling interval strikes + * a balance between responsiveness and CPU overhead -- fast enough that + * clients see sub-frame latency, slow enough to avoid busy-spinning. + */ +#define VRTD_DEFERRED_WORK_INTERVAL_USEC (20ULL * 1000ULL) + +static void check_journal_and_abort_if_needed(void); +static int configure_watchdog(sd_event *ev); +static int configure_signals(sd_event *ev, struct vrtd *state); +static int configure_sockets(sd_event *ev, struct vrtd *state); +static int configure_background_tasks(sd_event *ev, struct vrtd *state); +static int block_signals(const int *signals, size_t n); + +void globals_init(); +void globals_destroy(); + +int main(void) +{ + struct vrtd state = {0}; + + /* + * Verify the systemd journal is reachable before doing anything else. + * If logging is broken we want to fail *before* sd_notify(READY=1), + * so the service never appears started and the sysadmin gets a clear + * error from systemctl. See the detailed rationale above + * check_journal_and_abort_if_needed(). + */ + check_journal_and_abort_if_needed(); + + globals_init(); + + int ret = config_load(&state.config); + if (ret == -1) { + LOG(LOG_CRIT, "Failed to load config"); + exit(EXIT_FAILURE); + } + + ret = devices_discover_and_open(&state.devices); + if (ret == -1) { + LOG(LOG_CRIT, "Failed to load devices"); + exit(EXIT_FAILURE); + } + + LOG(LOG_INFO, "Discovered %zu device(s)", state.devices.len); + + _cleanup_(sd_event_unrefp) + sd_event *ev = NULL; + ret = sd_event_default(&ev); + if (ret < 0) { + LOG(LOG_CRIT, "Failed to allocate event loop: %s", strerrordesc_np(-ret)); + exit(EXIT_FAILURE); + } + + /* + * Enable the systemd watchdog so that systemd can detect if vrtd + * becomes unresponsive (e.g. blocked on a stuck QDMA ioctl or + * deadlocked). sd_event_set_watchdog() automatically sends + * keepalive pings at half the interval configured in the unit file + * (WatchdogSec=); if we stop pinging, systemd will restart us. + */ + ret = configure_watchdog(ev); + if (ret == -1) { + LOG(LOG_CRIT, "Failed to configure watchdog"); + exit(EXIT_FAILURE); + } + + ret = configure_signals(ev, &state); + if (ret == -1) { + LOG(LOG_CRIT, "Failed to configure signals"); + exit(EXIT_FAILURE); + } + + ret = configure_sockets(ev, &state); + if (ret == -1) { + LOG(LOG_CRIT, "Failed to configure sockets"); + exit(EXIT_FAILURE); + } + + ret = configure_background_tasks(ev, &state); + if (ret == -1) { + LOG(LOG_CRIT, "Failed to configure background tasks"); + exit(EXIT_FAILURE); + } + + ret = sd_notify(0, "READY=1"); + if (ret < 0) { + LOG(LOG_CRIT, "Failed to notify ready: %s", strerrordesc_np(-ret)); + exit(EXIT_FAILURE); + } else if (ret == 0) { + LOG(LOG_INFO, "No notification socket"); + } + + ret = sd_event_loop(ev); + if (ret < 0) { + LOG(LOG_CRIT, "Critical error: %s", strerrordesc_np(-ret)); + exit(EXIT_FAILURE); + } + + (void) sd_notify(0, "STOPPING=1"); + + globals_destroy(); + + return ret; +} + + +/** + * In vrtd we do all our logging through the systemd-journal. + * This is very convenient as it allows inspecting with journalctl -u + * in the usual way, saves us from having to manage our own files in + * /var/log (with rotation, compression etc.) and is nice QoL all around. + * + * The problem is that logging can fail, which raises the question about + * how we are to handle that failure. + * + * It is important to note that if the systemd-journal is not active, + * the logging functions will succeed, and silently do nothing. This is + * a systemd design choice. For now, we simply accept this behaviour. + * + * The logging functions can fail if: + * + * 1) We call them with invalid parameters (EINVAL). + * 2) We send a message that's too big. + * 3) We run out of memory (ENOMEM). + * 4) Some other process limit is reached. + * 5) An I/O error occurs. + * 6) The internal sendmsg syscall is interrupted by a signal (EINTR). + * + * Aborting the program if logging fails is not a good idea. We are left + * with two choices: + * + * a) generally ignore logging errors + * b) generally check logging errors + * + * Our current approach is to generally ignore logging errors, checking + * only once (in the function below) at the very beginning of the program, + * mostly to catch errors of type (5), and failing if we cannot log anything + * at all. Because this happens before we notify READY=1, the service will + * never appear started and systemctl start will fail, making it obvious to + * the sysadmin that something is wrong. + * + * If we decide to check (which would massively increase complexity and may + * slightly affect performance), we should assert against (1); assert against (2) + * when there is no user-provided parameters (and fall back to a message without them + * if there are); ignore (3); fall back to some other (stderr?) logging if (4) or (5) + * and quietly retry (6). + * + * The reason to ignore (3) is because logging code is not a structurally sane + * place to recover from ENOMEM. If we're limited, we'll hit ENOMEM again later + * and we can do a better job at recovering then. + */ +static void check_journal_and_abort_if_needed() +{ + int ret = sd_journal_print(LOG_INFO, "Starting vrtd..."); + if (ret < 0) { + (void) fprintf(stderr, "Failed to access systemd journal\n"); + exit(EXIT_FAILURE); + } +} + +static int configure_signals(sd_event *ev, struct vrtd *state) +{ + struct sigaction sa_ignore = { .sa_handler = SIG_IGN }; + int ret = sigemptyset(&sa_ignore.sa_mask); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Error manipulating signal set"); + + ret = sigaction(SIGPIPE, &sa_ignore, NULL); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to ignore SIGPIPE"); + + int signals[] = {SIGINT, SIGTERM, SIGQUIT, SIGHUP}; + + ret = block_signals(signals, SIZEOF_ARRAY(signals)); + PROPAGATE_ERROR(ret); + + for (size_t i = 0; i < SIZEOF_ARRAY(signals); i++) { + ret = sd_event_add_signal(ev, NULL, signals[i], on_event_signal, state); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to add event source: %s", sigabbrev_np(signals[i])); + } + + return 0; +} + +static int block_signals(const int *signals, size_t n) +{ + sigset_t set; + sigemptyset(&set); + for (size_t i = 0; i < n; i++) { + sigaddset(&set, signals[i]); + } + + int ret = sigprocmask(SIG_BLOCK, &set, NULL); + PROPAGATE_ERROR_STDC_LOG(ret,LOG_CRIT, "Failed to mask signals"); + + return 0; +} + +static int configure_sockets(sd_event *ev, struct vrtd *state) +{ + _cleanup_(cleanup_argv) + char **names = NULL; + + int ret = sd_listen_fds_with_names(1, &names); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Could not list listen fds"); + if (ret == 0) { + LOG(LOG_ERR, "No socket provided"); + return -1; + } + + for (int i = 0; i < ret; i++) { + int fd = SD_LISTEN_FDS_START + i; + + ret = sd_is_socket(fd, AF_UNIX, SOCK_SEQPACKET, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to get state of socket %s", names[i]); + if (ret == 0) { + LOG(LOG_ERR, "Bad socket type %s", names[i]); + return -1; + } + + int flags = fcntl(fd, F_GETFL, 0); + PROPAGATE_ERROR_STDC_LOG(flags, LOG_ERR, "Failed to get fcntl for fd=%d (%s)", fd, names[i]); + ret = fcntl(fd, F_SETFL, flags | O_NONBLOCK); + PROPAGATE_ERROR_STDC_LOG(ret, LOG_ERR, "Failed to set fcntl for fd=%d (%s)", fd, names[i]); + + _cleanup_(sd_event_source_unrefp) + sd_event_source *source = NULL; + ret = sd_event_add_io(ev, &source, fd, EPOLLIN, on_event_new_connection, state); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up listening for socket %s", names[i]); + + _cleanup_(cleanup_free) + char *description = NULL; + + ret = asprintf(&description, "Unix socket %s", names[i]); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Could not allocate description for socket %s", names[i]); + + ret = sd_event_source_set_description(source, description); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Could not set description for socket %s", names[i]); + + ret = sd_event_source_set_io_fd_own(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up fd ownership for socket %s", names[i]); + + ret = sd_event_source_set_floating(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up floating source for socket %s", names[i]); + + ret = sd_event_source_set_exit_on_failure(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set up exit on failure for socket %s", names[i]); + + LOG(LOG_INFO, "Listening on unix socket %s", names[i]); + } + + return 0; +} + +static int configure_watchdog(sd_event *ev) +{ + int ret = sd_event_set_watchdog(ev, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to enable watchdog"); + + return 0; +} + +static int configure_background_tasks(sd_event *ev, struct vrtd *state) +{ + uint64_t now = 0; + int ret = sd_event_now(ev, CLOCK_MONOTONIC, &now); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to read event loop clock"); + + _cleanup_(sd_event_source_unrefp) + sd_event_source *source = NULL; + ret = sd_event_add_time( + ev, + &source, + CLOCK_MONOTONIC, + now + VRTD_DEFERRED_WORK_INTERVAL_USEC, + VRTD_DEFERRED_WORK_INTERVAL_USEC / 2, + on_event_deferred_work, + state + ); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to add deferred work timer"); + + ret = sd_event_source_set_description(source, "Deferred request poll"); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set deferred work timer description"); + + ret = sd_event_source_set_floating(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to float deferred work timer source"); + + ret = sd_event_source_set_exit_on_failure(source, 1); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set exit-on-failure for deferred work timer"); + + return 0; +} + +void globals_init(void) +{ + hotplug_global_init(); +} + +void globals_destroy(void) +{ + hotplug_global_destroy(); +} diff --git a/vrt/vrtd/src/reset.c b/vrt/vrtd/src/reset.c new file mode 100644 index 00000000..9003968c --- /dev/null +++ b/vrt/vrtd/src/reset.c @@ -0,0 +1,391 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file reset.c + * @brief Device reset sequence for AMD Alveo V80 using AMI + PCIe Secondary Bus Reset. + * + * This module implements the full reset-and-reconfiguration sequence for a + * SLASH FPGA device. The sequence combines two mechanisms: + * + * 1. AMI (Alveo Management Interface) -- a firmware-level management + * interface exposed through the AVED (Alveo Versal Example Design) + * driver on PF0. AMI provides ioctls for device management operations + * such as programming boot partitions and triggering firmware-level + * reconfiguration. + * TODO(vserbu): explain AMI protocol details + * + * 2. PCIe hotplug via the SLASH kernel module -- after the firmware has been + * told to reconfigure, the PCIe device must be removed from the bus, + * a Secondary Bus Reset (SBR) must be toggled on the upstream bridge, + * and the bus must be rescanned so the newly-configured device is + * re-enumerated by the kernel. + * + * Multi-PF handling + * ----------------- + * The Alveo V80 exposes three PCIe Physical Functions (PFs) under the same + * bus:device address: + * + * - PF0: AVED/AMI management function (used for firmware ioctls) + * - PF1: QDMA function (used for DMA data transfers) + * - PF2: Additional function + * TODO(vserbu): clarify PF2 role (CMC? user PF?) + * + * Before performing a Secondary Bus Reset, ALL three PFs must be removed from + * the Linux PCI subsystem. If any PF is left attached while the SBR is + * toggled, the kernel may attempt to access a device whose configuration + * space is no longer valid, leading to machine checks or hangs. After the + * SBR and a settling delay, a PCI bus rescan brings all three functions back. + * + * Reset sequence (step by step) + * ----------------------------- + * 1. Compute BDF strings for PF0, PF1, PF2 from the device's BDF. + * 2. Remove the device from vrtd's tracked device list (it is about to + * disappear from the bus). + * 3. Open the AMI device on PF0, request access. + * 4. Issue AMI_IOC_DEVICE_BOOT ioctl to tell the AMC firmware to boot + * from partition 1 on the next reset. + * 5. Write a trigger value to BAR0 offset 0x1040000 to initiate the + * firmware-level reconfiguration. + * TODO(vserbu): explain what BAR0 register 0x1040000 controls in AMI + * 6. Close the AMI device handle. + * 7. Remove PF0, PF1, PF2 from the PCI bus via slash_hotplug_remove(). + * ENODEV is tolerated (device may already have been removed by firmware). + * 8. Toggle Secondary Bus Reset on the upstream PCIe bridge via + * slash_hotplug_toggle_sbr(). + * 9. Wait 5 seconds for the device to complete reconfiguration and + * re-train the PCIe link. + * 10. Rescan the PCI bus via slash_hotplug_rescan() to re-enumerate all PFs. + * 11. Verify the device is back by calling ami_dev_find() on PF0. + * 12. Run device discovery to re-add the reset device to vrtd's tracked + * device list. + */ + +#define _GNU_SOURCE + +#include "reset.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "device.h" +#include "hotplug.h" +#include "utils.h" + +#define GPIO_ALLOW_SBR 0x1040000 + +/** + * Perform a full device reset using AMI firmware commands and PCIe hotplug. + * + * This function executes the complete reset sequence described in the file + * header. It takes ownership of @device (removes it from @devices) because + * the device will be physically removed from the PCI bus during the reset. + * After the reset and rescan, devices_discover_and_open() re-populates the + * device list with the newly-enumerated device. + * + * @param device The device to reset. The caller must not use this pointer + * after the call, as the device is removed from the tracked + * list and freed. + * @param devices The global array of tracked device pointers. The target + * device is removed at the start; after a successful reset, + * the newly-discovered device is added back. + * @return VRTD_RET_OK on success, or a VRTD_RET_* error code on failure. + */ +uint16_t reset_with_ami(struct device *device, struct device_ptr_array *devices) +{ + /* + * Step 1: Compute BDF (Bus:Device.Function) strings for all three PFs. + * All PFs share the same bus:device but have different function numbers. + */ + char pf0_bdf[VRTD_PCI_BDF_LEN] = {0}; + char pf1_bdf[VRTD_PCI_BDF_LEN] = {0}; + char pf2_bdf[VRTD_PCI_BDF_LEN] = {0}; + + struct ami_device *ami_device = NULL; + + int ret = pci_bdf_set_function(device->pci_info.bdf, 0, pf0_bdf); + if (ret != 0) { + LOG(LOG_ERR, "reset_with_ami: failed to compute PF0 BDF from %s", device->pci_info.bdf); + return VRTD_RET_INTERNAL_ERROR; + } + ret = pci_bdf_set_function(device->pci_info.bdf, 1, pf1_bdf); + if (ret != 0) { + LOG(LOG_ERR, "reset_with_ami: failed to compute PF1 BDF from %s", device->pci_info.bdf); + return VRTD_RET_INTERNAL_ERROR; + } + ret = pci_bdf_set_function(device->pci_info.bdf, 2, pf2_bdf); + if (ret != 0) { + LOG(LOG_ERR, "reset_with_ami: failed to compute PF2 BDF from %s", device->pci_info.bdf); + return VRTD_RET_INTERNAL_ERROR; + } + + /* + * Step 2: Remove the device from vrtd's tracked device list. + * The device is about to be reset and will disappear from the PCI bus, + * so we must stop tracking it before proceeding. After this point, + * the @device pointer is invalid and must not be dereferenced. + */ + // We are now removing this device. + device_ptr_array_rm_by_reference(devices, device); + device = NULL; + + /* + * Step 3: Open the AMI management device on PF0 and request access. + * AMI (Alveo Management Interface) runs on PF0 (the AVED function). + * ami_dev_find() locates the AMI character device by PCI BDF, and + * ami_dev_request_access() acquires exclusive access for management + * operations. + * TODO(vserbu): explain AMI access model -- is this a lock? exclusive open? capability grant? + */ + // PF0 is AVED/AMI bdf + ret = ami_dev_find(pf0_bdf, &ami_device); + if (ret != AMI_STATUS_OK) { + LOG(LOG_ERR, "reset_with_ami: ami_dev_find(%s) failed: %s", pf0_bdf, ami_get_last_error()); + return VRTD_RET_INTERNAL_ERROR; + } + + ret = ami_dev_request_access(ami_device); + if (ret != AMI_STATUS_OK) { + LOG(LOG_ERR, "reset_with_ami: ami_dev_request_access(%s) failed: %s", pf0_bdf, ami_get_last_error()); + ami_dev_delete(&ami_device); + return VRTD_RET_INTERNAL_ERROR; + } + + /* + * Step 4: Issue AMI_IOC_DEVICE_BOOT ioctl to select boot partition 1. + * + * We issue AMI_IOC_DEVICE_BOOT directly rather than calling + * ami_prog_device_boot(), even though the latter is the intended public + * API for this operation. The reason is that ami_prog_device_boot() + * unconditionally calls ami_dev_hot_reset() after the ioctl succeeds. + * ami_dev_hot_reset() performs its own full remove-device / toggle-SBR / + * rescan cycle by opening the PCIe bridge config-space sysfs file + * (/sys/bus/pci/devices//config) with O_RDWR. That file is mode + * 0600 and owned by root; vrtd runs as the unprivileged 'vrtd' user, so + * the open always fails with EBADF regardless of any Linux capabilities + * granted to the process. + * + * More fundamentally, even if the open succeeded, ami_dev_hot_reset would + * conflict with vrtd's own hotplug reset sequence that follows immediately + * below. vrtd drives hotplug through the slash kernel module + * (slash_hotplug_remove / slash_hotplug_toggle_sbr / slash_hotplug_rescan), + * which is the authoritative hotplug path for SLASH devices. Letting both + * ami_dev_hot_reset and the slash hotplug sequence run would reset the + * device twice and leave the AMI device handle in an inconsistent state. + * + * The correct behaviour is to issue only the AMI_IOC_DEVICE_BOOT ioctl to + * inform the AMC firmware of the desired boot partition, then hand control + * back to vrtd to drive the full hotplug sequence itself. We set + * cap_override from the device handle (populated earlier by + * ami_dev_request_access) so that the kernel driver's per-ioctl permission + * check passes for the unprivileged vrtd user without requiring + * CAP_DAC_OVERRIDE or root. + */ + { + struct ami_ioc_data_payload boot_payload = { 0 }; + boot_payload.partition = 0; + boot_payload.cap_override = ami_device->cap_override; + + if (ami_open_cdev(ami_device) != AMI_STATUS_OK) { + LOG(LOG_ERR, "reset_with_ami: ami_open_cdev(%s) failed: %s", pf0_bdf, ami_get_last_error()); + ami_dev_delete(&ami_device); + return VRTD_RET_INTERNAL_ERROR; + } + + errno = 0; + if (ioctl(ami_device->cdev, AMI_IOC_DEVICE_BOOT, &boot_payload) != 0) { + LOG(LOG_ERR, "reset_with_ami: AMI_IOC_DEVICE_BOOT(%s) failed: errno %d (%s)", + pf0_bdf, errno, strerror(errno)); + ami_dev_delete(&ami_device); + return VRTD_RET_INTERNAL_ERROR; + } + } + LOG(LOG_INFO, "reset_with_ami: AMI_IOC_DEVICE_BOOT(%s) OK", pf0_bdf); + + /* + * Step 5: Write a trigger value to BAR0 register at offset 0x1040000 + * to initiate the firmware-level reconfiguration. + * + * This is a GPIO pin in the programmed logic that forms an AND gate + * with the PCIe SBR signal, and needs to be turned on in order to + * perform a scondary bus reset. + */ + ret = ami_mem_bar_write(ami_device, 0, GPIO_ALLOW_SBR, 1); + if (ret != AMI_STATUS_OK) { + LOG(LOG_ERR, "reset_with_ami: ami_mem_bar_write(%s) failed: %s", pf0_bdf, ami_get_last_error()); + ami_dev_delete(&ami_device); + return VRTD_RET_INTERNAL_ERROR; + } + + LOG(LOG_INFO, "reset_with_ami: GPIO_ALLOW_SBR set on %s", pf0_bdf); + + /* Step 6: Close the AMI device handle -- we are done with firmware commands. */ + ami_dev_delete(&ami_device); + + /* + * Step 7: Remove ALL three PFs from the Linux PCI subsystem. + * + * Every PF must be removed before we toggle SBR on the upstream bridge. + * If any function remains bound while the bus is reset, the kernel may + * attempt MMIO or config-space accesses to a device whose link is down, + * which can cause machine checks or system hangs. + * + * ENODEV is tolerated because the firmware reconfiguration triggered in + * step 5 may have already caused the device to disappear from the bus. + */ + if (g_hotplug == NULL) { + LOG(LOG_ERR, "reset_with_ami: hotplug handle not available (is slash_hotplug loaded?)"); + return VRTD_RET_INTERNAL_ERROR; + } + + ret = slash_hotplug_remove(g_hotplug, pf0_bdf); + LOG(LOG_INFO, "reset_with_ami: removed %s (ret=%d, errno=%d)", pf0_bdf, ret, errno); + if (ret != 0 && errno != ENODEV) { + LOG(LOG_ERR, "reset_with_ami: hotplug remove(%s) failed: %m", pf0_bdf); + return hotplug_errno_to_vrtd_ret(errno); + } + ret = slash_hotplug_remove(g_hotplug, pf1_bdf); + LOG(LOG_INFO, "reset_with_ami: removed %s (ret=%d, errno=%d)", pf1_bdf, ret, errno); + if (ret != 0 && errno != ENODEV) { + LOG(LOG_ERR, "reset_with_ami: hotplug remove(%s) failed: %m", pf1_bdf); + return hotplug_errno_to_vrtd_ret(errno); + } + ret = slash_hotplug_remove(g_hotplug, pf2_bdf); + LOG(LOG_INFO, "reset_with_ami: removed %s (ret=%d, errno=%d)", pf2_bdf, ret, errno); + if (ret != 0 && errno != ENODEV) { + LOG(LOG_ERR, "reset_with_ami: hotplug remove(%s) failed: %m", pf2_bdf); + return hotplug_errno_to_vrtd_ret(errno); + } + + /* + * Step 7a: Brief settle after PF removal, before toggling SBR. + * + * The AMI library's ami_dev_hot_reset() inserts a 1 ms delay here. + * Its comment notes that "on some systems, the device that is being + * reset disappears from the host, forcing a system reboot — adding a + * delay before setting the SBR seems to mitigate this issue." + */ + usleep(20000); + + /* + * Step 8: Toggle Secondary Bus Reset (SBR) on the upstream PCIe bridge. + * + * SBR asserts the reset signal on the secondary side of the PCIe bridge, + * forcing all downstream devices (our FPGA) to re-initialize. This is + * the mechanism that causes the FPGA to load the new configuration from + * the boot partition selected in step 4. + */ + LOG(LOG_INFO, "reset_with_ami: toggling SBR for %s", pf0_bdf); + ret = slash_hotplug_toggle_sbr(g_hotplug, pf0_bdf); + if (ret != 0) { + LOG(LOG_ERR, "reset_with_ami: hotplug toggle_sbr(%s) failed: %m", pf0_bdf); + return hotplug_errno_to_vrtd_ret(errno); + } + LOG(LOG_INFO, "reset_with_ami: SBR toggle complete for %s", pf0_bdf); + + /* + * Step 9: Wait for the FPGA to complete reconfiguration and re-train + * the PCIe link. 5 seconds is a conservative estimate that accounts for + * bitstream loading time and link training, mentioned in a AVED sw comment. + */ + usleep(5000000); + + /* + * Step 10-12: Rescan the PCI bus and verify the device reappears. + * The rescan re-enumerates all functions (PF0, PF1, PF2), then we wait + * for the kernel, drivers, and udev to fully initialize device nodes. + * If the device has not reappeared, retry the rescan after 3 seconds, + * up to 5 attempts total. + */ + #define RESCAN_MAX_RETRIES 5 + #define RESCAN_RETRY_DELAY_US 3000000 + + for (int attempt = 1; attempt <= RESCAN_MAX_RETRIES; attempt++) { + ret = slash_hotplug_rescan(g_hotplug); + if (ret != 0) { + LOG(LOG_ERR, "reset_with_ami: hotplug rescan failed: %m"); + return hotplug_errno_to_vrtd_ret(errno); + } + LOG(LOG_INFO, "reset_with_ami: rescan complete (attempt %d/%d)", + attempt, RESCAN_MAX_RETRIES); + + /* + * After a rescan the following things need to happen: + * + * * The kernel needs to detect the device on the PCIe bus. + * * The kernel needs to hand that device to the slash and ami drivers. + * * The slash and ami drivers need to create device nodes. + * * The kernel needs to signal to userspace systemd-udev that the device node was created. + * * systemd-udev needs to set permisions on the device node. + * + * That all takes time, so we wait a generous 10 seconds for all of that to occur. + * + * TODO: A much more robust method would be to remove all the code bellow this + * and rework how devices are discovered. We could bring in libudev. + * This would allow us to get netlink notifications on device events, such as new devices + * appearing. Then we could attempt to open these devices only after the userspace has configured them. + */ + usleep(10000000); + + ret = ami_dev_find(pf0_bdf, &ami_device); + if (ret == AMI_STATUS_OK) { + LOG(LOG_INFO, "reset_with_ami: device %s found after reset", pf0_bdf); + break; + } + + if (attempt < RESCAN_MAX_RETRIES) { + LOG(LOG_WARNING, "reset_with_ami: ami_dev_find(%s) failed (attempt %d/%d): %s, retrying in 3s", + pf0_bdf, attempt, RESCAN_MAX_RETRIES, ami_get_last_error()); + usleep(RESCAN_RETRY_DELAY_US); + } else { + LOG(LOG_ERR, "reset_with_ami: post-reset ami_dev_find(%s) failed after %d attempts: %s", + pf0_bdf, RESCAN_MAX_RETRIES, ami_get_last_error()); + return VRTD_RET_INTERNAL_ERROR; + } + } + + #undef RESCAN_MAX_RETRIES + #undef RESCAN_RETRY_DELAY_US + + ami_dev_delete(&ami_device); + + /* + * Step 13: Run device discovery to re-add the reset device to vrtd's + * tracked device list. This opens the QDMA function, sets up queues, + * and makes the device available for user requests again. + */ + // We now rescan for the reset device + ret = devices_discover_and_open(devices); + if (ret != 0) { + LOG(LOG_ERR, "reset_with_ami: devices_discover_and_open failed after reset"); + return VRTD_RET_INTERNAL_ERROR; + } + + return VRTD_RET_OK; +} diff --git a/vrt/vrtd/src/reset.h b/vrt/vrtd/src/reset.h new file mode 100644 index 00000000..b88a3f98 --- /dev/null +++ b/vrt/vrtd/src/reset.h @@ -0,0 +1,31 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VRTD_RESET_H +#define VRTD_RESET_H + +#include + +struct device; +struct device_ptr_array; + +uint16_t reset_with_ami(struct device *device, struct device_ptr_array *devices); + +#endif /* VRTD_RESET_H */ diff --git a/vrt/vrtd/src/serve.c b/vrt/vrtd/src/serve.c new file mode 100644 index 00000000..c11c4d32 --- /dev/null +++ b/vrt/vrtd/src/serve.c @@ -0,0 +1,2911 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file serve.c + * @brief Event-driven request dispatcher and client I/O engine for vrtd. + * + * This file implements the core request/response loop for the V80 Runtime + * Daemon (vrtd). vrtd multiplexes access to SLASH FPGA devices on behalf of + * multiple unprivileged clients. Clients connect over AF_UNIX SOCK_SEQPACKET + * sockets and exchange record-oriented messages defined in wire.h. + * + * ## Architecture + * + * The daemon runs a single-threaded sd_event loop (systemd event loop). Each + * connected client is represented by a `struct client` whose socket fd is + * registered as an sd_event I/O source. The main callback, on_client_io(), + * is invoked whenever a client socket becomes readable or writable, and drives + * the per-client state machine described below. + * + * ## Client state machine + * + * Each client processes one request at a time. Four boolean flags track + * the progress of that single in-flight request: + * + * have_request -- A complete request message has been received into + * client->inb and is ready for dispatch. + * have_response -- A response message has been serialized into + * client->outb and is ready to be sent. + * have_new_response -- Set together with have_response so that we + * attempt an immediate send in the same event + * callback rather than waiting for the next + * EPOLLOUT wakeup. + * pending_design_write -- The DESIGN_WRITE request has been submitted + * asynchronously and the client is blocked until + * the transfer completes. While this flag is set, + * have_request remains true and no new EPOLLIN + * events are armed, so the client cannot send + * another request. Completion is polled by + * on_event_deferred_work() every 20 ms. + * + * Typical synchronous request lifecycle: + * + * 1. EPOLLIN fires -> client_handle_in() -> have_request = true + * 2. (same callback) -> client_handle_request() dispatches the opcode + * -> have_response = true, have_request = false + * 3. EPOLLOUT fires -> client_handle_out() -> have_response = false + * (or immediately via have_new_response in the same callback) + * + * Asynchronous DESIGN_WRITE lifecycle: + * + * 1. EPOLLIN fires -> client_handle_in() -> have_request = true + * 2. client_handle_request() submits async write + * -> pending_design_write = true, response deferred + * 3. on_event_deferred_work() polls completion every 20 ms + * -> on completion: have_response = true, have_request = false, + * pending_design_write = false + * 4. EPOLLOUT fires -> client_handle_out() -> have_response = false + * + * ## FD passing via SCM_RIGHTS + * + * Several operations pass file descriptors out-of-band using the Unix + * SCM_RIGHTS ancillary-data mechanism: + * + * Inbound (client -> daemon): + * - DESIGN_WRITE: The client sends an fd to the bitstream file that the + * daemon reads from asynchronously. client_handle_in() extracts exactly + * one fd from the cmsg ancillary data and stores it in client->in_fd. + * + * Outbound (daemon -> client): + * - GET_BAR_FD: Sends a BAR mmap-able fd. + * - QDMA_QPAIR_GET_FD: Sends a QDMA queue pair character-device fd. + * - BUFFER_OPEN: Sends the fd for the newly allocated buffer's qpair. + * client_handle_out() attaches client->out_fd as SCM_RIGHTS ancillary + * data on the sendmsg() call when client->have_out_fd is true. + * + * ## Authorization + * + * Every request handler calls an auth_request_*() function before doing any + * work. These functions (defined in auth.c) check the client's uid and + * group memberships against the daemon's role-based access control policy. + * A return of 0 means "denied" (-> VRTD_RET_AUTH_ERROR), -1 means "internal + * error", and 1 means "permitted". + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "array.h" +#include "auth.h" +#include "clock.h" +#include "design_writer.h" +#include "hotplug.h" +#include "reset.h" +#include "serve.h" +#include "utils.h" +#include "state.h" +#include "vrtd/wire.h" + +/** + * Polling interval (in microseconds) for the deferred-work timer. + * on_event_deferred_work() fires every 20 ms to check whether any pending + * asynchronous design writes have completed. + */ +#define VRTD_DEFERRED_WORK_INTERVAL_USEC (20ULL * 1000ULL) + +/* ---- Forward declarations ------------------------------------------------ */ + +static int client_update_wanted_epoll_events(struct client *client, sd_event_source *s); +static int client_handle_in(struct client *client); +static int client_handle_out(struct client *client); +static int client_handle_request(struct client *client); +static int client_finalize_pending_design_write(struct client *client); +static uint16_t client_handle_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_device_info *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_device_by_bdf( + struct client *client, + const struct vrtd_req_get_device_by_bdf *req_body, + uint16_t req_size, + struct vrtd_resp_get_device_by_bdf *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body, + uint16_t req_size, + struct vrtd_resp_get_num_devices *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_info *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +); +static uint16_t client_handle_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_get_info *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_add *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_op *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_get_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +); +static uint16_t client_handle_request_buffer_open( + struct client *client, + const struct vrtd_req_buffer_open *req_body, + uint16_t req_size, + struct vrtd_resp_buffer_open *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +); +static uint16_t client_handle_request_buffer_open_raw( + struct client *client, + const struct vrtd_req_buffer_open_raw *req_body, + uint16_t req_size, + struct vrtd_resp_buffer_open_raw *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +); +static uint16_t client_handle_request_buffer_close( + struct client *client, + const struct vrtd_req_buffer_close *req_body, + uint16_t req_size, + struct vrtd_resp_buffer_close *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_design_write( + struct client *client, + const struct vrtd_req_design_write *req_body, + uint16_t req_size, + struct vrtd_resp_design_write *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_device_hotplug_op( + struct client *client, + const struct vrtd_req_device_hotplug_op *req_body, + uint16_t req_size, + struct vrtd_resp_device_hotplug_op *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_clock_op( + struct client *client, + const struct vrtd_req_clock_op *req_body, + uint16_t req_size, + struct vrtd_resp_clock_op *resp_body, + uint16_t *resp_size +); +static uint16_t client_handle_request_get_sensor_info( + struct client *client, + const struct vrtd_req_get_sensor_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_sensor_info *resp_body, + uint16_t *resp_size +); + +static uint16_t device_refresh_pf2_after_design_write(struct device *d); +static void cleanup_client_buffers(struct client *client); + +/* ---- Helper: opcode / hotplug-op to human-readable string --------------- */ + +/** + * Returns the human-readable name of a vrtd wire opcode. + * Used for diagnostic log messages. + * + * @param opcode One of the VRTD_REQ_* constants from wire.h. + * @return Static string; "UNKNOWN" for unrecognized values. + */ +static const char *vrtd_opcode_to_string(uint16_t opcode) +{ + switch (opcode) { + case VRTD_REQ_GET_NUM_DEVICES: return "GET_NUM_DEVICES"; + case VRTD_REQ_GET_DEVICE_INFO: return "GET_DEVICE_INFO"; + case VRTD_REQ_GET_DEVICE_BY_BDF: return "GET_DEVICE_BY_BDF"; + case VRTD_REQ_GET_BAR_INFO: return "GET_BAR_INFO"; + case VRTD_REQ_GET_BAR_FD: return "GET_BAR_FD"; + case VRTD_REQ_QDMA_GET_INFO: return "QDMA_GET_INFO"; + case VRTD_REQ_QDMA_QPAIR_ADD: return "QDMA_QPAIR_ADD"; + case VRTD_REQ_QDMA_QPAIR_OP: return "QDMA_QPAIR_OP"; + case VRTD_REQ_QDMA_QPAIR_GET_FD:return "QDMA_QPAIR_GET_FD"; + case VRTD_REQ_DESIGN_WRITE: return "DESIGN_WRITE"; + case VRTD_REQ_CLOCK_OP: return "CLOCK_OP"; + case VRTD_REQ_BUFFER_OPEN: return "BUFFER_OPEN"; + case VRTD_REQ_BUFFER_CLOSE: return "BUFFER_CLOSE"; + case VRTD_REQ_DEVICE_HOTPLUG_OP: return "DEVICE_HOTPLUG_OP"; + case VRTD_REQ_GET_SENSOR_INFO: return "GET_SENSOR_INFO"; + default: return "UNKNOWN"; + } +} + +/** + * Returns the human-readable name of a hotplug operation. + * + * @param op One of the VRTD_DEVICE_HOTPLUG_OP_* constants from wire.h. + * @return Static string; "unknown" for unrecognized values. + */ +static const char *vrtd_hotplug_op_to_string(uint32_t op) +{ + switch (op) { + case VRTD_DEVICE_HOTPLUG_OP_RESCAN: return "rescan"; + case VRTD_DEVICE_HOTPLUG_OP_REMOVE: return "remove"; + case VRTD_DEVICE_HOTPLUG_OP_TOGGLE_SBR: return "toggle_sbr"; + case VRTD_DEVICE_HOTPLUG_OP_HOTPLUG: return "hotplug"; + case VRTD_DEVICE_HOTPLUG_OP_RESET_SEQUENCE: return "reset_sequence"; + default: return "unknown"; + } +} + +/* ---- Post-design-write device refresh ----------------------------------- */ + +/** + * Refreshes PCI function 2 (PF2) after a design write completes. + * + * After a new bitstream is loaded, the PF2 device may have changed identity + * or capabilities. This function removes the old PF2 from the PCI bus and + * triggers a rescan so that the kernel re-enumerates it with updated + * configuration. + * + * @param d The device whose PF2 should be refreshed. + * @return VRTD_RET_OK on success, or an appropriate VRTD_RET_* error code. + */ +static uint16_t device_refresh_pf2_after_design_write(struct device *d) +{ + char pf2_bdf[VRTD_PCI_BDF_LEN] = {0}; + if (pci_bdf_set_function(d->pci_info.bdf, 2, pf2_bdf) != 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + struct slash_hotplug *hotplug = slash_hotplug_open(NULL); + if (hotplug == NULL) { + return hotplug_errno_to_vrtd_ret(errno); + } + + /* Remove the old PF2 device; ENODEV is tolerated (already absent). */ + int ret = slash_hotplug_remove(hotplug, pf2_bdf); + if (ret != 0 && errno != ENODEV) { + int err = errno; + (void) slash_hotplug_close(hotplug); + return hotplug_errno_to_vrtd_ret(err); + } + + /* Rescan the PCI bus so the kernel discovers the new PF2. */ + if (slash_hotplug_rescan(hotplug) != 0) { + int err = errno; + (void) slash_hotplug_close(hotplug); + return hotplug_errno_to_vrtd_ret(err); + } + + if (slash_hotplug_close(hotplug) != 0) { + return VRTD_RET_INTERNAL_ERROR; + } + + /* + * The BAR dma-buf fds in d->bar_files[] were opened against the pre-PDI + * PF2. After partial reconfiguration the AXI fabric behind PF2's BAR + * has changed; clients that mmap the old fd will hit an unresponsive AXI + * slave and trigger a fatal PCIe completion timeout. Close the stale + * fds and reopen them against the freshly-probed PF2 so that subsequent + * GET_BAR_FD requests return a valid mapping. + */ + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_files); i++) { + if (d->bar_files[i] != NULL) { + (void) slash_bar_file_close(d->bar_files[i]); + d->bar_files[i] = NULL; + } + if (d->bar_info[i] != NULL) { + slash_bar_info_free(d->bar_info[i]); + d->bar_info[i] = NULL; + } + } + + /* + * The /dev/slash_ctlN suffix is assigned by an incrementing kernel counter + * and changes after each hotplug remove+rescan. d->path still holds the + * path from daemon startup (e.g. /dev/slash_ctl0); that node no longer + * exists. Resolve the new path via the stable sysfs name + * /sys/class/misc/slash_ctl_/uevent and update d->path in-place so + * that subsequent GET_BAR_FD and devices_discover_and_open deduplication + * both see the current path. + */ + _cleanup_(cleanup_free) char *new_ctl_path = NULL; + if (find_slash_ctl_dev_path_by_bdf(pf2_bdf, &new_ctl_path) != 0 || new_ctl_path == NULL) { + LOG(LOG_ERR, "device_refresh_pf2: cannot find slash_ctl device for %s in sysfs", pf2_bdf); + return VRTD_RET_INTERNAL_ERROR; + } + + LOG(LOG_INFO, "device_refresh_pf2: new slash_ctl path for %s is %s", pf2_bdf, new_ctl_path); + + slash_ctldev_close(d->ctl); + free(d->path); + d->path = new_ctl_path; + new_ctl_path = NULL; /* ownership transferred — prevent cleanup_free from freeing */ + + /* + * After a hotplug rescan the kernel creates the device node immediately + * but udev sets ownership (vrtd:vrtd) asynchronously. Opening the node + * before udev acts yields EACCES. Retry with a short backoff to let udev + * catch up; any other error is fatal immediately. + */ + #define CTL_OPEN_RETRIES 10 + #define CTL_OPEN_RETRY_US 500000 /* 500 ms per attempt, 5 s total */ + for (int attempt = 1; attempt <= CTL_OPEN_RETRIES; attempt++) { + d->ctl = slash_ctldev_open(d->path); + if (d->ctl != NULL) + break; + if (errno != EACCES) { + LOG(LOG_ERR, "device_refresh_pf2: failed to reopen ctl device %s: %m", d->path); + return VRTD_RET_INTERNAL_ERROR; + } + LOG(LOG_INFO, "device_refresh_pf2: waiting for udev to set permissions on %s " + "(attempt %d/%d)", d->path, attempt, CTL_OPEN_RETRIES); + usleep(CTL_OPEN_RETRY_US); + } + if (d->ctl == NULL) { + LOG(LOG_ERR, "device_refresh_pf2: timed out waiting for permissions on %s: %m", d->path); + return VRTD_RET_INTERNAL_ERROR; + } + #undef CTL_OPEN_RETRIES + #undef CTL_OPEN_RETRY_US + + for (size_t i = 0; i < SIZEOF_ARRAY(d->bar_info); i++) { + d->bar_info[i] = slash_bar_info_read(d->ctl, i); + if (d->bar_info[i] != NULL && d->bar_info[i]->usable) { + d->bar_files[i] = slash_bar_file_open(d->ctl, i, O_CLOEXEC); + if (d->bar_files[i] == NULL) { + LOG(LOG_ERR, "device_refresh_pf2: failed to reopen bar_file %zu on %s: %m", + i, d->path); + } + } + } + + return VRTD_RET_OK; +} + +/* ---- Client cleanup ----------------------------------------------------- */ + +/** + * Releases all buffers owned by a disconnecting client. + * + * When a client disconnects (gracefully or not), any QDMA buffers it opened + * via BUFFER_OPEN must be freed so that device memory is not leaked. This + * function iterates over all devices and removes buffers whose client_id + * matches the disconnecting client's conn_id. + * + * @param client The client being torn down. May be NULL (no-op). + */ +static void cleanup_client_buffers(struct client *client) +{ + if (client == NULL || client->state == NULL || client->conn_id == 0) { + return; + } + + LOG(LOG_DEBUG, "Cleaning up buffers for disconnecting client uid=%u conn_id=%llu", + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + for (size_t dev_idx = 0; dev_idx < client->state->devices.len; ++dev_idx) { + struct device *d = client->state->devices.d[dev_idx]; + if (d == NULL) { + continue; + } + + size_t i = 0; + while (i < d->buffers.len) { + struct buffer *buf = d->buffers.d[i]; + if (buf == NULL || buf->client_id != client->conn_id) { + i++; + continue; + } + + /* + * buffer_ptr_array_rm_by_reference() frees the buffer and + * shrinks the array, so we do not increment i -- the next + * element slides into position i. + */ + buffer_ptr_array_rm_by_reference(&d->buffers, buf); + } + } +} + +/** + * Tears down a client: releases buffers, closes fds, unregisters the event + * source, and frees memory. + * + * Called when the client disconnects (EPOLLHUP / EPOLLRDHUP / EPOLLERR) or + * when the daemon shuts down. Safe to call with a NULL pointer. + * + * @param client The client to destroy. + */ +void cleanup_client(struct client *client) +{ + if (client == NULL) { + return; + } + + cleanup_client_buffers(client); + + gid_t_array_free(&client->gids); + + /* Close the inbound SCM_RIGHTS fd if one was received but not consumed. */ + if (client->in_fd >= 0) { + (void) close(client->in_fd); + client->in_fd = -1; + } + + /* Close the client's SOCK_SEQPACKET connection fd. */ + if (client->fd >= 0) { + (void) close(client->fd); + client->fd = -1; + } + + (void) sd_event_source_disable_unrefp(&client->event_source); + + free(client); +} + +/* ---- sd_event I/O callback ---------------------------------------------- */ + +/** + * Main sd_event I/O callback for a connected client. + * + * This function is registered with sd_event_add_io() for each client socket + * and is invoked whenever the socket has pending I/O events. It drives the + * client state machine: + * + * 1. If the socket has error/hangup events, the client is disconnected + * and removed from the client list (which frees it via the owning + * array destructor). + * 2. If EPOLLIN is set and we have no pending request, we receive the + * next message (client_handle_in). + * 3. If a request is pending and no response has been prepared yet, + * we dispatch it (client_handle_request). + * 4. If a response is ready and EPOLLOUT is set (or the response was + * just prepared in step 3, flagged by have_new_response), we send + * the response (client_handle_out). + * 5. Update the epoll event mask so that we only wake up for events + * relevant to the current state. + * + * @param s The sd_event_source for this client's fd. + * @param fd The client's socket fd. + * @param revents The epoll event bitmask that triggered this callback. + * @param user Pointer to the `struct client`. + * @return 0 on success, negative errno on fatal error. + */ +int on_client_io(sd_event_source *s, int fd, uint32_t revents, void *user) +{ + struct client *client = user; + (void) s; + + assert(client->fd == fd); + + int ret; + + /* Disconnect on error / hangup / remote close. */ + if (revents & (EPOLLERR | EPOLLHUP | EPOLLRDHUP)) { + LOG(LOG_DEBUG, "Client disconnected uid=%u conn_id=%llu fd=%d", + (unsigned int)client->uid, (unsigned long long)client->conn_id, client->fd); + client_ptr_array_rm_by_reference(&client->state->clients, client); + return 0; + } + + /* Step 1: Receive a new request if the slot is free. */ + if (!client->have_request && (revents & EPOLLIN)) { + ret = client_handle_in(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to handle client input"); + } + + /* Step 2: Dispatch the request synchronously (unless async design write). */ + if (client->have_request && !client->have_response) { + ret = client_handle_request(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to handle client request"); + } + + /* + * Step 3: Send the response. + * have_new_response allows an immediate send attempt even if EPOLLOUT + * was not in revents -- this avoids a round-trip through the event loop + * when the socket is writable and we just prepared the response above. + */ + if ((client->have_response && (revents & EPOLLOUT)) || + client->have_new_response) { + client->have_new_response = false; + + ret = client_handle_out(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to handle client output"); + } + + /* Step 4: Adjust EPOLLIN/EPOLLOUT based on current state. */ + ret = client_update_wanted_epoll_events(client, s); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to update epoll events"); + + return 0; +} + +/* ---- Deferred work timer ------------------------------------------------ */ + +/** + * Timer callback that polls for completion of asynchronous design writes. + * + * Registered as a monotonic sd_event timer source. Fires every + * VRTD_DEFERRED_WORK_INTERVAL_USEC (20 ms). For each client that has + * pending_design_write == true, it calls client_finalize_pending_design_write() + * to check whether the async write has finished. If it has, that function + * prepares the response and transitions the client state machine so the + * response can be sent on the next I/O event. + * + * @param s The sd_event_source for this timer. + * @param usec The monotonic timestamp at which this callback was scheduled. + * @param user Pointer to the global `struct vrtd` daemon state. + * @return 0 on success, negative errno on fatal error. + */ +int on_event_deferred_work(sd_event_source *s, uint64_t usec, void *user) +{ + struct vrtd *state = user; + + if (state == NULL) { + return -1; + } + + /* Re-arm the timer for the next interval. */ + uint64_t next_usec = usec + VRTD_DEFERRED_WORK_INTERVAL_USEC; + int ret = sd_event_source_set_time(s, next_usec); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set deferred work timer"); + + ret = sd_event_source_set_enabled(s, SD_EVENT_ON); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to re-enable deferred work timer"); + + /* Check each client for a completed async design write. */ + for (size_t i = 0; i < state->clients.len; i++) { + struct client *client = state->clients.d[i]; + if (client == NULL) { + continue; + } + + ret = client_finalize_pending_design_write(client); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to finalize deferred design write"); + + /* + * client_finalize_pending_design_write() returns 1 when the write + * finished and the response was prepared. In that case, re-arm the + * client's epoll events so that EPOLLOUT triggers a send. + */ + if (ret == 1) { + ret = client_update_wanted_epoll_events(client, client->event_source); + PROPAGATE_ERROR_LOG(ret, LOG_ERR, "Failed to update epoll events for deferred response"); + } + } + + return 0; +} + +/* ---- Epoll event management --------------------------------------------- */ + +/** + * Recalculates and applies the set of epoll events we want for a client. + * + * The desired event set depends on the client's state machine position: + * - EPOLLRDHUP is always armed so we detect remote close. + * - EPOLLIN is armed only when we have no pending request (ready to + * receive the next one). + * - EPOLLOUT is armed only when we have a response to send. + * + * To avoid unnecessary sd_event_source_set_io_events() syscalls, the + * previously applied mask is cached in client->wanted_epoll_events and + * the call is skipped when nothing changed. + * + * @param client The client whose epoll mask should be updated. + * @param s The client's sd_event I/O source. + * @return 0 on success, negative errno on failure. + */ +static int client_update_wanted_epoll_events(struct client *client, sd_event_source *s) +{ + uint32_t events = + EPOLLRDHUP | + (!client->have_request ? EPOLLIN : 0) | + (client->have_response ? EPOLLOUT : 0) + ; + + if (events == client->wanted_epoll_events) { + return 0; + } + client->wanted_epoll_events = events; + + int ret = sd_event_source_set_io_events(s, events); + PROPAGATE_ERROR_SD_LOG(ret, LOG_ERR, "Failed to set io source io events"); + + return 0; +} + +/* ---- Inbound message reception (SCM_RIGHTS extraction) ------------------ */ + +/** + * Receives the next request message from a client's socket. + * + * Uses recvmsg() to read both the message payload (into client->inb) and any + * ancillary data carrying SCM_RIGHTS file descriptors (into client->in_fd). + * + * ## SCM_RIGHTS handling + * + * The cmsg ancillary-data buffer is sized for exactly one fd. The loop over + * CMSG_FIRSTHDR / CMSG_NXTHDR extracts fds as follows: + * - If the ancillary data is malformed (fractional fd size), all received + * fds are closed and the function returns -1. + * - If more than one fd was sent, or if a second SCM_RIGHTS header appears, + * all fds are closed and the function returns -1. The daemon expects at + * most one inbound fd per message (currently only DESIGN_WRITE uses it). + * - On success the single fd is stored in client->in_fd and + * client->have_in_fd is set to true. + * + * ## Message validation + * + * After a successful recvmsg(), the function validates the framing: + * - The received byte count must be at least sizeof(vrtd_req_header). + * - header->size + sizeof(header) must equal the byte count. + * - header->size must not overflow the buffer. + * + * On success, client->have_request is set to true and the caller (on_client_io) + * proceeds to dispatch. + * + * @param client The client to receive from. + * @return 0 on success (including EAGAIN -- no data ready yet), + * -1 on protocol error or I/O error. + */ +static int client_handle_in(struct client *client) +{ + assert(!client->have_request); + + /* Close any leftover inbound fd from a previous request cycle. */ + if (client->in_fd >= 0) { + (void) close(client->in_fd); + client->in_fd = -1; + client->have_in_fd = false; + } + + /* Set up the iovec to receive the message payload. */ + struct iovec iovec[1] = { + { .iov_base = client->inb, .iov_len = VRTD_MSG_MAX_SIZE }, + }; + + /* + * Allocate a cmsg buffer large enough for one fd. + * CMSG_SPACE includes alignment padding required by the kernel. + */ + char cbuf[CMSG_SPACE(sizeof(int))]; + struct msghdr msg = { + .msg_name = NULL, + .msg_namelen = 0, + .msg_iov = iovec, + .msg_iovlen = SIZEOF_ARRAY(iovec), + .msg_control = cbuf, + .msg_controllen = sizeof(cbuf), + .msg_flags = 0, + }; + + ssize_t n; +retry: + n = recvmsg(client->fd, &msg, MSG_DONTWAIT); + if (n == -1) { + switch (errno) { + case EINTR: + goto retry; + case EAGAIN: +#if EAGAIN != EWOULDBLOCK + case EWOULDBLOCK: +#endif + return 0; + default: + return -1; + } + } + + /* Reject truncated messages -- this should not happen with SEQPACKET. */ + if (msg.msg_flags & (MSG_TRUNC | MSG_CTRUNC)) { + // TODO: handle error from client + return -1; + } + + /* + * Walk the cmsg chain to extract any SCM_RIGHTS file descriptors. + * We expect at most one fd; anything else is a protocol violation. + */ + client->in_fd = -1; + client->have_in_fd = false; + for (struct cmsghdr *cmsg = CMSG_FIRSTHDR(&msg); + cmsg != NULL; + cmsg = CMSG_NXTHDR(&msg, cmsg)) { + if (cmsg->cmsg_level != SOL_SOCKET || cmsg->cmsg_type != SCM_RIGHTS) { + continue; + } + + size_t data_len = cmsg->cmsg_len - CMSG_LEN(0); + size_t count = data_len / sizeof(int); + int *fds = (int *) CMSG_DATA(cmsg); + + /* Reject malformed ancillary data (fractional fd). */ + if (data_len < sizeof(int) || (data_len % sizeof(int)) != 0) { + for (size_t i = 0; i < count; ++i) { + (void) close(fds[i]); + } + return -1; + } + + /* Reject multiple fds or multiple SCM_RIGHTS headers. */ + if (count != 1 || client->have_in_fd) { + for (size_t i = 0; i < count; ++i) { + (void) close(fds[i]); + } + return -1; + } + + client->in_fd = fds[0]; + client->have_in_fd = true; + } + + /* Validate request framing. */ + struct vrtd_req_header *header = (struct vrtd_req_header *) client->inb; + if (n < sizeof(struct vrtd_req_header) || header->size + sizeof(struct vrtd_req_header) != n || header->size > VRTD_MSG_MAX_SIZE - sizeof *header) { + // TODO: handle error from client + return -1; + } + + client->have_request = true; + + return 0; +} + +/* ---- Outbound message transmission (SCM_RIGHTS attachment) -------------- */ + +/** + * Sends the prepared response message to a client. + * + * Uses sendmsg() to transmit the response from client->outb. If a file + * descriptor needs to be passed to the client (client->have_out_fd is true), + * the fd stored in client->out_fd is attached as SCM_RIGHTS ancillary data. + * + * ## SCM_RIGHTS construction + * + * When have_out_fd is set: + * 1. A cmsg control buffer (cbuf) is zeroed and attached to the msghdr. + * 2. A single cmsghdr is constructed with level=SOL_SOCKET, type=SCM_RIGHTS, + * and len=CMSG_LEN(sizeof(int)). + * 3. The fd is copied into the cmsg data area via memcpy. + * 4. sendmsg() delivers both the response payload and the fd atomically. + * + * After a successful send, have_response and have_out_fd are cleared, + * allowing the client to send a new request. + * + * @param client The client to send to. + * @return 0 on success (including EAGAIN), -1 on error. + */ +static int client_handle_out(struct client *client) +{ + assert(client->have_response); + + size_t size = sizeof(struct vrtd_resp_header) + ((struct vrtd_resp_header *) client->outb)->size; + + struct iovec iovec[1] = { + { .iov_base = client->outb, .iov_len = size }, + }; + + struct msghdr msg = { + .msg_name = NULL, + .msg_namelen = 0, + .msg_iov = iovec, + .msg_iovlen = SIZEOF_ARRAY(iovec), + .msg_control = NULL, + .msg_controllen = 0, + .msg_flags = 0, + }; + + char cbuf[CMSG_SPACE(sizeof(int))]; + + /* + * If we have an outbound fd, construct SCM_RIGHTS ancillary data. + * The cbuf is zeroed to satisfy kernel expectations about padding. + */ + if (client->have_out_fd) { + memset(cbuf, 0, sizeof cbuf); + + msg.msg_control = cbuf; + msg.msg_controllen = sizeof cbuf; + + struct cmsghdr *cmsg = CMSG_FIRSTHDR(&msg); + cmsg->cmsg_level = SOL_SOCKET; + cmsg->cmsg_type = SCM_RIGHTS; + cmsg->cmsg_len = CMSG_LEN(sizeof(int)); + + memcpy(CMSG_DATA(cmsg), &client->out_fd, sizeof(int)); + } + + ssize_t n; +retry: + n = sendmsg(client->fd, &msg, MSG_DONTWAIT | MSG_NOSIGNAL); + if (n == -1) { + switch (errno) { + case EINTR: + goto retry; + case EAGAIN: +#if EAGAIN != EWOULDBLOCK + case EWOULDBLOCK: +#endif + return 0; + default: + return -1; + } + } + + /* + * SOCK_SEQPACKET guarantees atomic delivery; a short write means + * something went wrong. + */ + if (n != size) { + LOG(LOG_ERR, "Message truncated"); + return -1; + } + + /* Response sent -- clear state so the client can send a new request. */ + client->have_response = false; + client->have_out_fd = false; + + return 0; +} + +/* ---- Request dispatch (opcode switch) ----------------------------------- */ + +/** + * Dispatches a received request to the appropriate handler. + * + * Reads the opcode from the request header, logs the request, and switches + * on the opcode to invoke the correct handler function. Each handler follows + * a uniform signature: + * + * uint16_t handler(client, req_body, req_size, resp_body, resp_size + * [, out_fd, have_out_fd]) + * + * The handler returns a VRTD_RET_* status code which is stored in the + * response header. Handlers that pass an fd to the client (GET_BAR_FD, + * QDMA_QPAIR_GET_FD, BUFFER_OPEN) also write to client->out_fd and + * client->have_out_fd. + * + * Special case -- DESIGN_WRITE: + * The handler submits the write asynchronously and sets + * client->pending_design_write. In that case this function returns early + * *without* marking have_response or clearing have_request. The response + * is deferred until client_finalize_pending_design_write() detects + * completion. + * + * For all other (synchronous) opcodes, after the handler returns: + * - have_request is cleared + * - have_response and have_new_response are set + * - Any unconsumed inbound fd is closed + * + * @param client The client whose request should be dispatched. + * @return 0 on success, negative on fatal error. + */ +static int client_handle_request(struct client *client) +{ + assert(client->have_request); + assert(!client->have_response); + + struct vrtd_req_header *req_header = CLIENT_IN_HEADER(*client); + struct vrtd_resp_header *resp_header = CLIENT_OUT_HEADER(*client); + + /* Echo the client's sequence number back in the response. */ + resp_header->seqno = req_header->seqno; + + LOG(LOG_DEBUG, "Request opcode=%u(%s) uid=%u conn_id=%llu", + (unsigned int)req_header->opcode, vrtd_opcode_to_string(req_header->opcode), + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + // Separate variable for allignment reasons + uint16_t size = 0; + + switch (req_header->opcode) { + case VRTD_REQ_GET_NUM_DEVICES: + resp_header->ret = + client_handle_request_get_num_devices( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_num_devices), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_num_devices), + &size + ); + break; + case VRTD_REQ_GET_DEVICE_INFO: + resp_header->ret = + client_handle_request_get_device_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_device_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_device_info), + &size + ); + break; + case VRTD_REQ_GET_DEVICE_BY_BDF: + resp_header->ret = + client_handle_request_get_device_by_bdf( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_device_by_bdf), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_device_by_bdf), + &size + ); + break; + case VRTD_REQ_GET_BAR_INFO: + resp_header->ret = + client_handle_request_get_bar_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_bar_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_bar_info), + &size + ); + break; + case VRTD_REQ_GET_BAR_FD: + resp_header->ret = + client_handle_request_get_bar_fd( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_bar_fd), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_bar_fd), + &size, + &client->out_fd, + &client->have_out_fd + ); + break; + case VRTD_REQ_QDMA_GET_INFO: + resp_header->ret = + client_handle_request_qdma_get_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_get_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_get_info), + &size + ); + break; + case VRTD_REQ_QDMA_QPAIR_ADD: + resp_header->ret = + client_handle_request_qdma_qpair_add( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_qpair_add), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_qpair_add), + &size + ); + break; + case VRTD_REQ_QDMA_QPAIR_OP: + resp_header->ret = + client_handle_request_qdma_qpair_op( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_qpair_op), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_qpair_op), + &size + ); + break; + case VRTD_REQ_QDMA_QPAIR_GET_FD: + resp_header->ret = + client_handle_request_qdma_qpair_get_fd( + client, + CLIENT_IN_BODY(*client, vrtd_req_qdma_qpair_get_fd), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_qdma_qpair_get_fd), + &size, + &client->out_fd, + &client->have_out_fd + ); + break; + case VRTD_REQ_BUFFER_OPEN: + resp_header->ret = + client_handle_request_buffer_open( + client, + CLIENT_IN_BODY(*client, vrtd_req_buffer_open), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_buffer_open), + &size, + &client->out_fd, + &client->have_out_fd + ); + break; + case VRTD_REQ_BUFFER_OPEN_RAW: + resp_header->ret = + client_handle_request_buffer_open_raw( + client, + CLIENT_IN_BODY(*client, vrtd_req_buffer_open_raw), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_buffer_open_raw), + &size, + &client->out_fd, + &client->have_out_fd + ); + break; + case VRTD_REQ_BUFFER_CLOSE: + resp_header->ret = + client_handle_request_buffer_close( + client, + CLIENT_IN_BODY(*client, vrtd_req_buffer_close), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_buffer_close), + &size + ); + break; + case VRTD_REQ_DESIGN_WRITE: + resp_header->ret = + client_handle_request_design_write( + client, + CLIENT_IN_BODY(*client, vrtd_req_design_write), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_design_write), + &size + ); + break; + case VRTD_REQ_CLOCK_OP: + resp_header->ret = + client_handle_request_clock_op( + client, + CLIENT_IN_BODY(*client, vrtd_req_clock_op), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_clock_op), + &size + ); + break; + case VRTD_REQ_DEVICE_HOTPLUG_OP: + resp_header->ret = + client_handle_request_device_hotplug_op( + client, + CLIENT_IN_BODY(*client, vrtd_req_device_hotplug_op), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_device_hotplug_op), + &size + ); + break; + case VRTD_REQ_GET_SENSOR_INFO: + resp_header->ret = + client_handle_request_get_sensor_info( + client, + CLIENT_IN_BODY(*client, vrtd_req_get_sensor_info), + req_header->size, + CLIENT_OUT_BODY(*client, vrtd_resp_get_sensor_info), + &size + ); + break; + + default: + LOG(LOG_WARNING, "Unknown opcode=%u from uid=%u conn_id=%llu", + (unsigned int)req_header->opcode, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + resp_header->ret = VRTD_RET_BAD_REQUEST; + resp_header->size = 0; + + break; + } + + /* + * DESIGN_WRITE is asynchronous: the handler sets pending_design_write + * and the response will be prepared later by + * client_finalize_pending_design_write(). Do not transition the state + * machine yet. + */ + if (client->pending_design_write) { + return 0; + } + + if (resp_header->ret != VRTD_RET_OK) { + LOG(LOG_DEBUG, "Request opcode=%u(%s) failed ret=%u uid=%u conn_id=%llu", + (unsigned int)req_header->opcode, vrtd_opcode_to_string(req_header->opcode), + (unsigned int)resp_header->ret, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + } + + resp_header->size = size; + + /* Close the inbound fd if the handler did not consume it. */ + if (client->have_in_fd) { + (void) close(client->in_fd); + client->in_fd = -1; + client->have_in_fd = false; + } + + /* + * Transition the state machine: mark the request as consumed and the + * response as ready. have_new_response triggers an immediate send + * attempt in the same on_client_io() invocation. + */ + client->have_request = false; + client->have_response = true; + client->have_new_response = true; + + return 0; +} + +/* ---- Async design-write completion -------------------------------------- */ + +/** + * Checks whether a pending asynchronous design write has completed and, + * if so, prepares the response. + * + * Called from on_event_deferred_work() every 20 ms for each client that has + * pending_design_write == true. + * + * If the design_writer reports completion (success or failure): + * - The response header is populated with the appropriate status. + * - The client state machine is transitioned: pending_design_write is + * cleared, have_request is cleared, have_response and have_new_response + * are set. + * - Returns 1 to signal the caller that the epoll events need updating. + * + * If the write is still in progress, returns 0 (no-op). + * + * @param client The client whose pending write should be checked. + * @return 0 if still in progress or not applicable, 1 if the write completed + * and the response was prepared, negative on fatal error. + */ +static int client_finalize_pending_design_write(struct client *client) +{ + if (client == NULL || !client->pending_design_write) { + return 0; + } + + struct device *d = client->pending_design_write_device; + bool done = false; + int transfer_error = 0; + if (d == NULL || d->design_writer == NULL) { + done = true; + transfer_error = EIO; + } else { + int ret = design_writer_poll_result(d->design_writer, &done, &transfer_error); + if (ret != 0) { + done = true; + transfer_error = (errno != 0) ? errno : EIO; + } + } + + if (!done) { + return 0; + } + + /* Build the deferred response now that the async write has finished. */ + uint16_t design_write_ret = VRTD_RET_OK; + if (transfer_error == 0) { + design_write_ret = device_refresh_pf2_after_design_write(d); + LOG(LOG_INFO, "Design write completed successfully for uid=%u conn_id=%llu", + (unsigned int)client->uid, (unsigned long long)client->conn_id); + } else { + LOG(LOG_WARNING, "Design write failed (error=%d) for uid=%u conn_id=%llu", + transfer_error, (unsigned int)client->uid, (unsigned long long)client->conn_id); + design_write_ret = VRTD_RET_INTERNAL_ERROR; + } + + struct vrtd_req_header *req_header = CLIENT_IN_HEADER(*client); + struct vrtd_resp_header *resp_header = CLIENT_OUT_HEADER(*client); + struct vrtd_resp_design_write *resp_body = CLIENT_OUT_BODY(*client, vrtd_resp_design_write); + + resp_header->seqno = req_header->seqno; + resp_header->ret = design_write_ret; + + if (design_write_ret == VRTD_RET_OK) { + resp_body->zero = 0; + resp_header->size = sizeof(*resp_body); + } else { + resp_header->size = 0; + } + + /* + * Transition the state machine: the async operation is done, so clear + * the blocking flag and allow the response to be sent. + */ + client->pending_design_write = false; + client->pending_design_write_device = NULL; + client->have_request = false; + client->have_response = true; + client->have_new_response = true; + + return 1; +} + +/* ======================================================================== */ +/* Request handler functions */ +/* */ +/* Each handler follows a uniform pattern: */ +/* 1. Authorize the request via auth_request_*(). */ +/* 2. Validate req_size and request-specific parameters. */ +/* 3. Perform the operation (device lookup, ioctl, etc.). */ +/* 4. Populate resp_body and *resp_size. */ +/* 5. Return a VRTD_RET_* status code. */ +/* */ +/* Handlers that pass an fd back to the client additionally accept out_fd */ +/* and have_out_fd output parameters. The fd is delivered via SCM_RIGHTS */ +/* in client_handle_out(). */ +/* ======================================================================== */ + +/** + * Handles VRTD_REQ_GET_NUM_DEVICES. + * + * Returns the number of SLASH devices currently known to the daemon. + * Devices are numbered 0..n-1 and the count may be used by clients to + * enumerate them. + * + * Auth: auth_request_get_num_devices (typically unrestricted). + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_get_num_devices (placeholder zero byte) + * Response body: vrtd_resp_get_num_devices { uint32_t num_devices } + * + * @return VRTD_RET_OK on success, or VRTD_RET_AUTH_ERROR / VRTD_RET_BAD_REQUEST. + */ +static uint16_t client_handle_request_get_num_devices( + struct client *client, + const struct vrtd_req_get_num_devices *req_body, + uint16_t req_size, + struct vrtd_resp_get_num_devices *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_num_devices(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "get_num_devices: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + resp_body->num_devices = client->state->devices.len; + + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "get_num_devices: count=%zu uid=%u conn_id=%llu", + (size_t)resp_body->num_devices, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- DESIGN_WRITE ------------------------------------------------------- */ + +/** + * Handles VRTD_REQ_DESIGN_WRITE -- initiates an asynchronous bitstream load. + * + * The client sends a file descriptor (via SCM_RIGHTS in the request message) + * pointing to the bitstream file. This handler takes ownership of that fd, + * submits it to the device's design_writer for asynchronous DMA transfer, + * and sets the pending_design_write flag. + * + * Because the transfer is asynchronous, this handler does NOT prepare a + * response. The response is deferred until on_event_deferred_work() detects + * completion via client_finalize_pending_design_write(). While + * pending_design_write is true the client is blocked from sending further + * requests (EPOLLIN is disarmed). + * + * Auth: auth_request_design_write (typically requires elevated privileges). + * FD passing: inbound -- the client sends the bitstream fd via SCM_RIGHTS. + * + * Wire format: + * Request body: vrtd_req_design_write { uint32_t dev_number } + * Response body: vrtd_resp_design_write { uint8_t zero } (deferred) + * + * @return VRTD_RET_OK if the write was successfully submitted, + * VRTD_RET_BUSY if the design writer is already active, + * or other VRTD_RET_* codes on error. + */ +static uint16_t client_handle_request_design_write( + struct client *client, + const struct vrtd_req_design_write *req_body, + uint16_t req_size, + struct vrtd_resp_design_write *resp_body, + uint16_t *resp_size +) +{ + (void)resp_body; + + int ret = auth_request_design_write(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "design_write: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "design_write: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->design_writer == NULL) { + LOG(LOG_NOTICE, "design_write: device %u has no design writer", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + if (!client->have_in_fd || client->in_fd < 0) { + LOG(LOG_WARNING, "design_write: no input fd provided"); + return VRTD_RET_BAD_REQUEST; + } + + /* + * Submit the fd for asynchronous DMA. design_writer_submit_fd_async() + * takes ownership of the fd -- we must not close it on success. + */ + int fd = client->in_fd; + bool writer_busy_before = design_writer_is_busy(d->design_writer); + ret = design_writer_submit_fd_async(d->design_writer, fd); + if (ret != 0) { + if (writer_busy_before || design_writer_is_busy(d->design_writer)) { + LOG(LOG_NOTICE, "design_write: writer busy for device %u", (unsigned int)req_body->dev_number); + return VRTD_RET_BUSY; + } + LOG(LOG_WARNING, "design_write: failed to submit async write for device %u", (unsigned int)req_body->dev_number); + return VRTD_RET_INTERNAL_ERROR; + } + + /* The design writer now owns the fd; clear our reference. */ + client->in_fd = -1; + client->have_in_fd = false; + + /* + * Enter the async-waiting state. client_handle_request() will see + * pending_design_write and skip the normal response path. + */ + client->pending_design_write = true; + client->pending_design_write_device = d; + + LOG(LOG_INFO, "Design write submitted dev=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + *resp_size = 0; + return VRTD_RET_OK; +} + +/* ---- DEVICE_HOTPLUG_OP -------------------------------------------------- */ + +/** + * Handles VRTD_REQ_DEVICE_HOTPLUG_OP -- performs a PCIe hotplug operation. + * + * Dispatches one of several PCIe topology-management operations on the + * specified device: + * + * RESCAN -- Triggers a PCI bus rescan (all devices). + * REMOVE -- Removes the device from the PCI bus. + * TOGGLE_SBR -- Toggles Secondary Bus Reset on the device's upstream + * bridge. + * HOTPLUG -- Performs a full hotplug cycle (remove + SBR + rescan). + * RESET_SEQUENCE -- Performs a reset using the AMI-based reset flow + * (reset_with_ami), which includes SBR, device removal, + * rescan, and re-enumeration. + * + * Auth: auth_request_device_hotplug_op (typically requires elevated + * privileges, as these operations can disrupt other users). + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_device_hotplug_op { uint32_t dev_number, + * uint8_t op } + * Response body: vrtd_resp_device_hotplug_op { uint8_t zero } + * + * @return VRTD_RET_OK on success, VRTD_RET_INVALID_ARGUMENT for unknown ops. + */ +static uint16_t client_handle_request_device_hotplug_op( + struct client *client, + const struct vrtd_req_device_hotplug_op *req_body, + uint16_t req_size, + struct vrtd_resp_device_hotplug_op *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_device_hotplug_op(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "hotplug_op: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "hotplug_op: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL) { + LOG(LOG_NOTICE, "hotplug_op: device %u is null", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + LOG(LOG_INFO, "Hotplug op=%s(%u) bdf=%s dev=%u uid=%u conn_id=%llu", + vrtd_hotplug_op_to_string(req_body->op), (unsigned int)req_body->op, + d->pci_info.bdf, (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + switch (req_body->op) { + case VRTD_DEVICE_HOTPLUG_OP_RESCAN: + ret = slash_hotplug_rescan(g_hotplug); + break; + case VRTD_DEVICE_HOTPLUG_OP_REMOVE: + case VRTD_DEVICE_HOTPLUG_OP_TOGGLE_SBR: + case VRTD_DEVICE_HOTPLUG_OP_HOTPLUG: { + /* Individual hotplug operations are PCI-function-level (the hotplug + * interface is SLASH-agnostic). Construct a full DDDD:BB:DD.F BDF + * from the device's board-level address and the requested function. */ + if (req_body->function > 7) { + LOG(LOG_ERR, "hotplug_op: %s: invalid function number %u", + vrtd_hotplug_op_to_string(req_body->op), + (unsigned int)req_body->function); + return VRTD_RET_INVALID_ARGUMENT; + } + + char pf_bdf[VRTD_PCI_BDF_LEN]; + if (pci_bdf_set_function(d->pci_info.bdf, req_body->function, pf_bdf) != 0) { + LOG(LOG_ERR, "hotplug_op: %s: failed to construct PF%u BDF from %s", + vrtd_hotplug_op_to_string(req_body->op), + (unsigned int)req_body->function, d->pci_info.bdf); + return VRTD_RET_INTERNAL_ERROR; + } + + switch (req_body->op) { + case VRTD_DEVICE_HOTPLUG_OP_REMOVE: + ret = slash_hotplug_remove(g_hotplug, pf_bdf); + break; + case VRTD_DEVICE_HOTPLUG_OP_TOGGLE_SBR: + ret = slash_hotplug_toggle_sbr(g_hotplug, pf_bdf); + break; + case VRTD_DEVICE_HOTPLUG_OP_HOTPLUG: + ret = slash_hotplug_hotplug(g_hotplug, pf_bdf); + break; + default: + break; + } + break; + } + case VRTD_DEVICE_HOTPLUG_OP_RESET_SEQUENCE: { + uint16_t reset_ret = reset_with_ami(d, &client->state->devices); + if (reset_ret != VRTD_RET_OK) { + return reset_ret; + } + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; + } + default: + LOG(LOG_WARNING, "hotplug_op: invalid op %u for device %u", + (unsigned int)req_body->op, (unsigned int)req_body->dev_number); + return VRTD_RET_INVALID_ARGUMENT; + } + + if (ret != 0) { + LOG(LOG_WARNING, "hotplug_op: %s failed for device %u bdf=%s: %m", + vrtd_hotplug_op_to_string(req_body->op), + (unsigned int)req_body->dev_number, d->pci_info.bdf); + return hotplug_errno_to_vrtd_ret(errno); + } + + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +/* ---- QDMA_GET_INFO ------------------------------------------------------ */ + +/** + * Handles VRTD_REQ_QDMA_GET_INFO -- queries QDMA capabilities of a device. + * + * Reads the QDMA information structure (slash_qdma_info) from the device's + * QDMA subsystem and returns it to the client. + * + * Auth: auth_request_qdma_get_info. + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_qdma_get_info { uint32_t dev_number } + * Response body: vrtd_resp_qdma_get_info { slash_qdma_info info } + * + * @return VRTD_RET_OK on success, VRTD_RET_NOEXIST if the device has no QDMA. + */ +static uint16_t client_handle_request_qdma_get_info( + struct client *client, + const struct vrtd_req_qdma_get_info *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_get_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_qdma_get_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "qdma_get_info: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "qdma_get_info: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + LOG(LOG_NOTICE, "qdma_get_info: device %u has no QDMA", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + /* resp_body is packed; libslash expects a normally-aligned pointer. */ + struct slash_qdma_info info; + if (slash_qdma_info_read(d->qdma, &info) != 0) { + LOG(LOG_WARNING, "qdma_get_info: failed to read info for device %u: %m", (unsigned int)req_body->dev_number); + return VRTD_RET_INTERNAL_ERROR; + } + memcpy(&resp_body->info, &info, sizeof(info)); + + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "qdma_get_info: dev=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- QDMA_QPAIR_ADD ----------------------------------------------------- */ + +/** + * Handles VRTD_REQ_QDMA_QPAIR_ADD -- creates a QDMA queue pair on a device. + * + * Creates a new queue pair with the parameters specified in the request. + * The kernel allocates a queue ID (qid) which is returned in the response + * body. The caller can then start the queue pair and obtain its fd. + * + * Auth: auth_request_qdma_qpair_add. + * FD passing: none (use QDMA_QPAIR_GET_FD after starting the queue). + * + * Wire format: + * Request body: vrtd_req_qdma_qpair_add { uint32_t dev_number, + * slash_qdma_qpair_add add } + * Response body: vrtd_resp_qdma_qpair_add { slash_qdma_qpair_add add } + * (with qid filled in by the kernel) + * + * @return VRTD_RET_OK on success. + */ +static uint16_t client_handle_request_qdma_qpair_add( + struct client *client, + const struct vrtd_req_qdma_qpair_add *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_add *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_qdma_qpair_add(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "qdma_qpair_add: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "qdma_qpair_add: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + LOG(LOG_NOTICE, "qdma_qpair_add: device %u has no QDMA", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + /* resp_body is packed; libslash expects a normally-aligned pointer. */ + struct slash_qdma_qpair_add add = req_body->add; + + if (slash_qdma_qpair_add(d->qdma, &add) != 0) { + LOG(LOG_WARNING, "qdma_qpair_add: failed for device %u: %m", (unsigned int)req_body->dev_number); + return VRTD_RET_INTERNAL_ERROR; + } + memcpy(&resp_body->add, &add, sizeof(add)); + + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "qdma_qpair_add: dev=%u qid=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, (unsigned int)add.qid, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- QDMA_QPAIR_OP ----------------------------------------------------- */ + +/** + * Handles VRTD_REQ_QDMA_QPAIR_OP -- performs an operation on a QDMA queue pair. + * + * Dispatches one of the following operations on the specified queue pair: + * - SLASH_QDMA_QUEUE_OP_START: Activates the queue for DMA transfers. + * - SLASH_QDMA_QUEUE_OP_STOP: Halts the queue. + * - SLASH_QDMA_QUEUE_OP_DEL: Deletes the queue pair and releases its + * resources. + * + * Auth: auth_request_qdma_qpair_op. + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_qdma_qpair_op { uint32_t dev_number, + * uint32_t qid, uint32_t op } + * Response body: vrtd_resp_qdma_qpair_op { uint8_t zero } + * + * @return VRTD_RET_OK on success, VRTD_RET_INVALID_ARGUMENT for unknown ops. + */ +static uint16_t client_handle_request_qdma_qpair_op( + struct client *client, + const struct vrtd_req_qdma_qpair_op *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_op *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_qdma_qpair_op(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "qdma_qpair_op: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "qdma_qpair_op: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + LOG(LOG_NOTICE, "qdma_qpair_op: device %u has no QDMA", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + switch (req_body->op) { + case SLASH_QDMA_QUEUE_OP_START: + ret = slash_qdma_qpair_start(d->qdma, req_body->qid); + break; + case SLASH_QDMA_QUEUE_OP_STOP: + ret = slash_qdma_qpair_stop(d->qdma, req_body->qid); + break; + case SLASH_QDMA_QUEUE_OP_DEL: + ret = slash_qdma_qpair_del(d->qdma, req_body->qid); + break; + default: + LOG(LOG_WARNING, "qdma_qpair_op: invalid op %u for device %u qid=%u", + (unsigned int)req_body->op, (unsigned int)req_body->dev_number, (unsigned int)req_body->qid); + return VRTD_RET_INVALID_ARGUMENT; + } + + if (ret != 0) { + LOG(LOG_WARNING, "qdma_qpair_op: op %u failed for device %u qid=%u: %m", + (unsigned int)req_body->op, (unsigned int)req_body->dev_number, (unsigned int)req_body->qid); + return VRTD_RET_INTERNAL_ERROR; + } + + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "qdma_qpair_op: dev=%u qid=%u op=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, (unsigned int)req_body->qid, + (unsigned int)req_body->op, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- QDMA_QPAIR_GET_FD ------------------------------------------------- */ + +/** + * Handles VRTD_REQ_QDMA_QPAIR_GET_FD -- obtains the character-device fd for + * a QDMA queue pair. + * + * Returns a file descriptor that the client can read/write to perform DMA + * transfers through the specified queue pair. The fd is delivered to the + * client via SCM_RIGHTS in the response message. + * + * Auth: auth_request_qdma_qpair_get_fd. + * FD passing: outbound -- the qpair fd is sent via SCM_RIGHTS. + * + * Wire format: + * Request body: vrtd_req_qdma_qpair_get_fd { uint32_t dev_number, + * uint32_t qid, + * uint32_t flags } + * Response body: vrtd_resp_qdma_qpair_get_fd { uint8_t zero } + * + SCM_RIGHTS fd + * + * @return VRTD_RET_OK on success. + */ +static uint16_t client_handle_request_qdma_qpair_get_fd( + struct client *client, + const struct vrtd_req_qdma_qpair_get_fd *req_body, + uint16_t req_size, + struct vrtd_resp_qdma_qpair_get_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +) +{ + int ret = auth_request_qdma_qpair_get_fd(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + *have_out_fd = false; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "qdma_qpair_get_fd: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "qdma_qpair_get_fd: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + LOG(LOG_NOTICE, "qdma_qpair_get_fd: device %u has no QDMA", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + int fd = slash_qdma_qpair_get_fd(d->qdma, req_body->qid, (int)req_body->flags); + if (fd < 0) { + LOG(LOG_WARNING, "qdma_qpair_get_fd: failed for device %u qid=%u: %m", + (unsigned int)req_body->dev_number, (unsigned int)req_body->qid); + return VRTD_RET_INTERNAL_ERROR; + } + + /* Schedule this fd for delivery via SCM_RIGHTS in client_handle_out(). */ + *out_fd = fd; + *have_out_fd = true; + + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "qdma_qpair_get_fd: dev=%u qid=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, (unsigned int)req_body->qid, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- BUFFER_OPEN -------------------------------------------------------- */ + +/** + * Handles VRTD_REQ_BUFFER_OPEN -- allocates a DMA buffer and returns its fd. + * + * Creates a new buffer on the specified device with the requested allocation + * type (DDR, HBM, HBM_VNOC), direction, and size. The buffer consists of a + * device-memory allocation and an associated QDMA queue pair. The qpair fd + * is returned to the client via SCM_RIGHTS so the client can read/write + * directly to perform DMA. + * + * The buffer is tracked in the device's buffer list with the client's conn_id + * so that it can be automatically freed if the client disconnects without + * calling BUFFER_CLOSE (see cleanup_client_buffers). + * + * Auth: auth_request_buffer_open. + * FD passing: outbound -- the buffer qpair fd is sent via SCM_RIGHTS. + * + * Wire format: + * Request body: vrtd_req_buffer_open { uint32_t dev_number, + * uint32_t alloc_type, + * uint32_t alloc_dir, + * uint64_t alloc_arg, + * uint64_t size } + * Response body: vrtd_resp_buffer_open { uint64_t size, + * uint64_t phys_addr } + * + SCM_RIGHTS fd + * + * @return VRTD_RET_OK on success, VRTD_RET_BUSY if memory is exhausted, + * VRTD_RET_INVALID_ARGUMENT for bad allocation parameters. + */ +static uint16_t client_handle_request_buffer_open( + struct client *client, + const struct vrtd_req_buffer_open *req_body, + uint16_t req_size, + struct vrtd_resp_buffer_open *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +) +{ + int ret = auth_request_buffer_open(client, req_body); + if (ret == -1) { + char pwbuf[1024]; + LOG(LOG_WARNING, "Failed to authorize buffer open request for uid %u(%s): %m", + (unsigned int) client->uid, uid_to_username(client->uid, pwbuf, sizeof(pwbuf))); + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + *have_out_fd = false; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "Received malformed buffer open request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_WARNING, "Received buffer open request for non-existent device"); + return VRTD_RET_NOEXIST; + } + + if (req_body->size == 0) { + LOG(LOG_WARNING, "Received buffer open request with zero size"); + return VRTD_RET_INVALID_ARGUMENT; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL || d->memory_map == NULL) { + LOG(LOG_WARNING, "Received buffer open request for non-existent or non-functional device"); + return VRTD_RET_NOEXIST; + } + + uint64_t client_id = client->conn_id; + if (client_id == 0) { + LOG(LOG_ERR, "Invalid client connection id"); + return VRTD_RET_INTERNAL_ERROR; + } + + /* + * Create the buffer (allocation + qpair). _cleanup_(cleanup_bufferp) + * ensures the buffer is freed if we return early before transferring + * ownership to the device's buffer array. + */ + _cleanup_(cleanup_bufferp) + struct buffer *buf = buffer_create( + d->qdma, + d->memory_map, + (enum allocation_type) req_body->alloc_type, + (enum vrtd_alloc_dir) req_body->alloc_dir, + req_body->size, + req_body->alloc_arg, + client_id, + NULL + ); + if (buf == NULL) { + if (errno == EINVAL) { + LOG(LOG_WARNING, "buffer_open: invalid allocation arguments for device %u", (unsigned int)req_body->dev_number); + return VRTD_RET_INVALID_ARGUMENT; + } + if (errno == ENOMEM) { + LOG(LOG_NOTICE, "buffer_open: out of memory for device %u size=%llu", + (unsigned int)req_body->dev_number, (unsigned long long)req_body->size); + return VRTD_RET_BUSY; + } + + LOG(LOG_ERR, "Failed to create buffer for buffer open request: %m"); + return VRTD_RET_INTERNAL_ERROR; + } + + if (buf->fd < 0) { + LOG(LOG_ERR, "Buffer created without valid fd"); + return VRTD_RET_INTERNAL_ERROR; + } + + uint64_t real_size = buf->size; + int fd = buf->fd; + uint64_t phys_addr = buf->addr; + + /* + * Transfer ownership of the buffer into the device's buffer list. + * buffer_ptr_array_push_move() nullifies our local pointer so that the + * _cleanup_ destructor becomes a no-op. + */ + if (buffer_ptr_array_push_move(&d->buffers, &buf) != 0) { + LOG(LOG_ERR, "Failed to add buffer to device buffer list"); + return VRTD_RET_INTERNAL_ERROR; + } + + resp_body->size = real_size; + resp_body->phys_addr = phys_addr; + *out_fd = fd; + *have_out_fd = true; + *resp_size = sizeof(*resp_body); + + LOG(LOG_INFO, "Buffer opened size=%llu phys_addr=0x%llx dev=%u uid=%u conn_id=%llu", + (unsigned long long)real_size, (unsigned long long)phys_addr, + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- BUFFER_OPEN_RAW ---------------------------------------------------- */ + +/** + * Handles VRTD_REQ_BUFFER_OPEN_RAW -- creates a QDMA qpair at a caller-specified + * device address, bypassing the allocator entirely. + * + * The caller is responsible for ensuring the address is valid and not in use. + * Requires the raw-mem-access permission. The qpair fd is returned to the client + * via SCM_RIGHTS. The buffer is tracked in the device's buffer list so the qpair + * is torn down automatically if the client disconnects. + * + * Auth: auth_request_buffer_open_raw. + * FD passing: outbound -- the qpair fd is sent via SCM_RIGHTS. + * + * Wire format: + * Request body: vrtd_req_buffer_open_raw { uint32_t dev_number, + * uint32_t alloc_dir, + * uint64_t phys_addr, + * uint64_t size } + * Response body: vrtd_resp_buffer_open_raw { uint8_t zero } + * + SCM_RIGHTS fd + * + * @return VRTD_RET_OK on success, error code otherwise. + */ +static uint16_t client_handle_request_buffer_open_raw( + struct client *client, + const struct vrtd_req_buffer_open_raw *req_body, + uint16_t req_size, + struct vrtd_resp_buffer_open_raw *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +) +{ + int ret = auth_request_buffer_open_raw(client, req_body); + if (ret == -1) { + char pwbuf[1024]; + LOG(LOG_WARNING, "Failed to authorize raw buffer open request for uid %u(%s): %m", + (unsigned int) client->uid, uid_to_username(client->uid, pwbuf, sizeof(pwbuf))); + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + *have_out_fd = false; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "Received malformed raw buffer open request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_WARNING, "Received raw buffer open request for non-existent device"); + return VRTD_RET_NOEXIST; + } + + if (req_body->size == 0) { + LOG(LOG_WARNING, "Received raw buffer open request with zero size"); + return VRTD_RET_INVALID_ARGUMENT; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->qdma == NULL) { + LOG(LOG_WARNING, "Received raw buffer open request for non-existent or non-functional device"); + return VRTD_RET_NOEXIST; + } + + _cleanup_(cleanup_bufferp) + struct buffer *buf = buffer_create_raw( + d->qdma, + req_body->phys_addr, + req_body->size, + (enum vrtd_alloc_dir) req_body->alloc_dir + ); + if (buf == NULL) { + if (errno == EINVAL) { + LOG(LOG_WARNING, "buffer_open_raw: invalid arguments for device %u", (unsigned int)req_body->dev_number); + return VRTD_RET_INVALID_ARGUMENT; + } + LOG(LOG_ERR, "Failed to create raw buffer: %m"); + return VRTD_RET_INTERNAL_ERROR; + } + + if (buf->fd < 0) { + LOG(LOG_ERR, "Raw buffer created without valid fd"); + return VRTD_RET_INTERNAL_ERROR; + } + + int fd = buf->fd; + + if (buffer_ptr_array_push_move(&d->buffers, &buf) != 0) { + LOG(LOG_ERR, "Failed to add raw buffer to device buffer list"); + return VRTD_RET_INTERNAL_ERROR; + } + + resp_body->zero = 0; + *out_fd = fd; + *have_out_fd = true; + *resp_size = sizeof(*resp_body); + + LOG(LOG_WARNING, "Raw buffer opened phys_addr=0x%llx size=%llu dev=%u uid=%u conn_id=%llu", + (unsigned long long)req_body->phys_addr, (unsigned long long)req_body->size, + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- BUFFER_CLOSE ------------------------------------------------------- */ + +/** + * Handles VRTD_REQ_BUFFER_CLOSE -- releases a previously opened DMA buffer. + * + * Looks up the buffer by its physical address on the specified device, + * verifies that the requesting client is the owner (by conn_id), checks + * that the size matches, and then removes and frees the buffer. + * + * Auth: auth_request_buffer_close, plus ownership check (conn_id must match). + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_buffer_close { uint32_t dev_number, + * uint64_t phys_addr, + * uint64_t size } + * Response body: vrtd_resp_buffer_close { uint8_t zero } + * + * @return VRTD_RET_OK on success, VRTD_RET_AUTH_ERROR if the client does not + * own the buffer, VRTD_RET_NOEXIST if no buffer was found at that + * address. + */ +static uint16_t client_handle_request_buffer_close( + struct client *client, + const struct vrtd_req_buffer_close *req_body, + uint16_t req_size, + struct vrtd_resp_buffer_close *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_buffer_close(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "buffer_close: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "buffer_close: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + if (req_body->size == 0) { + LOG(LOG_WARNING, "buffer_close: zero size"); + return VRTD_RET_INVALID_ARGUMENT; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL) { + LOG(LOG_NOTICE, "buffer_close: device %u is null", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + /* Search for the buffer by physical address. */ + struct buffer *found = NULL; + for (size_t i = 0; i < d->buffers.len; ++i) { + struct buffer *buf = d->buffers.d[i]; + if (buf == NULL) { + continue; + } + if (buf->addr != req_body->phys_addr) { + continue; + } + /* Found a buffer at the right address -- verify size. */ + if (buf->size != req_body->size) { + LOG(LOG_WARNING, "buffer_close: size mismatch at addr=0x%llx (expected %llu, got %llu)", + (unsigned long long)req_body->phys_addr, + (unsigned long long)buf->size, (unsigned long long)req_body->size); + return VRTD_RET_INVALID_ARGUMENT; + } + /* Verify ownership: only the client that opened the buffer may close it. */ + if (buf->client_id != client->conn_id) { + char pwbuf[1024]; + LOG( + LOG_WARNING, + "Permission denied for uid %u(%s): 'buffer_close' requires buffer ownership", + (unsigned int) client->uid, + uid_to_username(client->uid, pwbuf, sizeof(pwbuf)) + ); + return VRTD_RET_AUTH_ERROR; + } + found = buf; + break; + } + + if (found == NULL) { + LOG(LOG_NOTICE, "buffer_close: no buffer at addr=0x%llx on device %u", + (unsigned long long)req_body->phys_addr, (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + LOG(LOG_INFO, "Buffer closed addr=0x%llx size=%llu dev=%u uid=%u conn_id=%llu", + (unsigned long long)found->addr, (unsigned long long)found->size, + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + /* Remove and free the buffer (owning array destructor handles cleanup). */ + buffer_ptr_array_rm_by_reference(&d->buffers, found); + + resp_body->zero = 0; + *resp_size = sizeof(*resp_body); + return VRTD_RET_OK; +} + +/* ---- CLOCK_OP ----------------------------------------------------------- */ + +/** + * Handles VRTD_REQ_CLOCK_OP -- gets or sets a clock rate for a device region. + * + * Supports two clock regions (service and user) and two operations (get and + * set). For SET operations, the requested rate must be non-zero. The + * response always contains the current (or achieved) rate. + * + * Auth: auth_request_clock_op. + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_clock_op { uint32_t dev_number, + * uint32_t rate_hz, + * uint8_t op, uint8_t region } + * Response body: vrtd_resp_clock_op { uint32_t rate_hz } + * + * @return VRTD_RET_OK on success, VRTD_RET_INVALID_ARGUMENT for bad op/region. + */ +static uint16_t client_handle_request_clock_op( + struct client *client, + const struct vrtd_req_clock_op *req_body, + uint16_t req_size, + struct vrtd_resp_clock_op *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_clock_op(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "clock_op: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "clock_op: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + if (d == NULL || d->clock_driver == NULL) { + LOG(LOG_NOTICE, "clock_op: device %u has no clock driver", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + uint32_t rate = req_body->rate_hz; + + switch (req_body->region) { + case VRTD_CLOCK_REGION_SERVICE: + if (req_body->op == VRTD_CLOCK_OP_GET) { + if (clock_driver_get_service_region_rate_hz(d->clock_driver, &rate) != 0) { + LOG(LOG_WARNING, "clock_op: failed to get service region rate for device %u: %m", + (unsigned int)req_body->dev_number); + return VRTD_RET_INTERNAL_ERROR; + } + } else if (req_body->op == VRTD_CLOCK_OP_SET) { + if (rate == 0) { + LOG( + LOG_WARNING, + "Received set frequency request with zero rate for service region" + ); + return VRTD_RET_INVALID_ARGUMENT; + } + if (clock_driver_set_service_region_rate_hz(d->clock_driver, &rate) != 0) { + LOG( + LOG_ERR, + "Failed to set service region frequency to %u Hz: %m", + req_body->rate_hz + ); + return VRTD_RET_INTERNAL_ERROR; + } + } else { + LOG( + LOG_WARNING, + "Received invalid clock op %u for service region", + (unsigned int)req_body->op + ); + return VRTD_RET_INVALID_ARGUMENT; + } + break; + case VRTD_CLOCK_REGION_USER: + if (req_body->op == VRTD_CLOCK_OP_GET) { + if (clock_driver_get_user_region_rate_hz(d->clock_driver, &rate) != 0) { + LOG(LOG_WARNING, "clock_op: failed to get user region rate for device %u: %m", + (unsigned int)req_body->dev_number); + return VRTD_RET_INTERNAL_ERROR; + } + } else if (req_body->op == VRTD_CLOCK_OP_SET) { + if (rate == 0) { + LOG( + LOG_WARNING, + "Received set frequency request with zero rate for user region" + ); + return VRTD_RET_INVALID_ARGUMENT; + } + if (clock_driver_set_user_region_rate_hz(d->clock_driver, &rate) != 0) { + LOG( + LOG_ERR, + "Failed to set user region frequency to %u Hz: %m", + req_body->rate_hz + ); + return VRTD_RET_INTERNAL_ERROR; + } + } else { + LOG( + LOG_WARNING, + "Received invalid clock op %u for user region", + (unsigned int)req_body->op + ); + return VRTD_RET_INVALID_ARGUMENT; + } + break; + default: + LOG( + LOG_WARNING, + "Received clock request with invalid region %u", + (unsigned int)req_body->region + ); + return VRTD_RET_INVALID_ARGUMENT; + } + + resp_body->rate_hz = rate; + *resp_size = sizeof(*resp_body); + + LOG(LOG_INFO, "clock_op: op=%u region=%u rate_hz=%u dev=%u uid=%u conn_id=%llu", + (unsigned int)req_body->op, (unsigned int)req_body->region, rate, + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- GET_DEVICE_INFO ---------------------------------------------------- */ + +/** + * Handles VRTD_REQ_GET_DEVICE_INFO -- returns name and PCI metadata for a + * device. + * + * Populates a vrtd_device_info structure containing: + * - name: the basename of the device's sysfs path (e.g. "0000:65:00.0"). + * - pci: BDF string, vendor/device/subsystem IDs. + * + * Auth: auth_request_get_device_info. + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_get_device_info { uint32_t dev_number } + * Response body: vrtd_resp_get_device_info { vrtd_device_info info } + * + * @return VRTD_RET_OK on success, VRTD_RET_NOEXIST if dev_number is invalid. + */ +static uint16_t client_handle_request_get_device_info( + struct client *client, + const struct vrtd_req_get_device_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_device_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_device_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "get_device_info: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "get_device_info: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + + /* + * basename() may modify its argument, so we duplicate the path first. + * The _cleanup_ attribute ensures the copy is freed on all return paths. + */ + _cleanup_(cleanup_free) + char *path = strdup(d->path); + if (unlikely(path == NULL)) { + LOG(LOG_WARNING, "get_device_info: allocation failure"); + return VRTD_RET_INTERNAL_ERROR; + } + + memset(resp_body, 0, sizeof(*resp_body)); + snprintf(resp_body->info.name, sizeof(resp_body->info.name), "%s", basename(path)); + memcpy(&resp_body->info.pci, &d->pci_info, sizeof(struct vrtd_pci_info)); + + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "get_device_info: dev=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- GET_DEVICE_BY_BDF -------------------------------------------------- */ + +/** + * Handles VRTD_REQ_GET_DEVICE_BY_BDF -- looks up a device index by PCI BDF + * string. + * + * Iterates over all known devices and compares their BDF against the + * client-provided string. Returns the 0-based device index on match. + * + * Auth: auth_request_get_device_by_bdf. + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_get_device_by_bdf { char bdf[32] } + * Response body: vrtd_resp_get_device_by_bdf { uint32_t dev_number } + * + * @return VRTD_RET_OK on match, VRTD_RET_NOEXIST if no device has the BDF. + */ +static uint16_t client_handle_request_get_device_by_bdf( + struct client *client, + const struct vrtd_req_get_device_by_bdf *req_body, + uint16_t req_size, + struct vrtd_resp_get_device_by_bdf *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_device_by_bdf(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "get_device_by_bdf: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + /* Defensively NUL-terminate the BDF string to prevent overreads. */ + char bdf[VRTD_PCI_BDF_LEN]; + memcpy(bdf, req_body->bdf, sizeof(bdf)); + bdf[sizeof(bdf) - 1] = '\0'; + + if (bdf[0] == '\0') { + LOG(LOG_WARNING, "get_device_by_bdf: empty BDF string"); + return VRTD_RET_INVALID_ARGUMENT; + } + + /* Normalize to board-level BDF (DDDD:BB:DD) for matching. + * Strip any function suffix (.F) since devices are stored board-level. + * Prepend domain 0000: if only one colon is present (short BDF). */ + { + char *dot = strrchr(bdf, '.'); + if (dot != NULL) { + LOG(LOG_WARNING, + "get_device_by_bdf: client sent PF-level BDF '%s'; " + "stripping function %s — use board address instead", + req_body->bdf, dot); + *dot = '\0'; + } + + /* Count colons to detect short BDF (BB:DD vs DDDD:BB:DD). */ + int colons = 0; + for (const char *p = bdf; *p != '\0'; ++p) { + if (*p == ':') colons++; + } + if (colons == 1) { + /* Short BDF — prepend default domain. */ + char tmp[VRTD_PCI_BDF_LEN]; + int n = snprintf(tmp, sizeof(tmp), "0000:%s", bdf); + if (n > 0 && (size_t)n < sizeof(tmp)) { + memcpy(bdf, tmp, (size_t)n + 1); + } + } + } + + /* Linear scan; the device count is small (single digits). */ + for (size_t i = 0; i < client->state->devices.len; ++i) { + struct device *d = client->state->devices.d[i]; + + if (strcmp(d->pci_info.bdf, bdf) == 0) { + resp_body->dev_number = (uint32_t) i; + *resp_size = sizeof(*resp_body); + LOG(LOG_DEBUG, "get_device_by_bdf: bdf=%s -> dev=%u uid=%u conn_id=%llu", + bdf, (unsigned int)i, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + return VRTD_RET_OK; + } + } + + LOG(LOG_NOTICE, "get_device_by_bdf: no device found for bdf=%s", bdf); + return VRTD_RET_NOEXIST; +} + +/* ---- GET_BAR_INFO ------------------------------------------------------- */ + +/** + * Handles VRTD_REQ_GET_BAR_INFO -- returns metadata about a device BAR. + * + * Returns the slash_ioctl_bar_info structure for the specified BAR, which + * contains the BAR's size and resource type. PCI devices have at most 6 + * BARs (indices 0-5). + * + * Auth: auth_request_get_bar_info. + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_get_bar_info { uint32_t dev_number, + * uint8_t bar_number } + * Response body: vrtd_resp_get_bar_info { slash_ioctl_bar_info bar_info } + * + * @return VRTD_RET_OK on success, VRTD_RET_NOEXIST if the BAR is not present. + */ +static uint16_t client_handle_request_get_bar_info( + struct client *client, + const struct vrtd_req_get_bar_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_bar_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "get_bar_info: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "get_bar_info: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + if (req_body->bar_number >= 6) { + LOG(LOG_WARNING, "get_bar_info: invalid BAR number %u", (unsigned int)req_body->bar_number); + return VRTD_RET_BAD_REQUEST; + } + + // TODO: Free this + struct slash_ioctl_bar_info *bar_info = client->state->devices.d[req_body->dev_number]->bar_info[req_body->bar_number]; + if (bar_info == NULL) { + LOG(LOG_NOTICE, "get_bar_info: BAR %u not available on device %u", + (unsigned int)req_body->bar_number, (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + resp_body->bar_info = *bar_info; + + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "get_bar_info: dev=%u bar=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, (unsigned int)req_body->bar_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- GET_BAR_FD --------------------------------------------------------- */ + +/** + * Handles VRTD_REQ_GET_BAR_FD -- returns a mmap-able fd for a device BAR. + * + * The returned file descriptor can be mmap'd by the client to obtain direct + * userspace access to the BAR's MMIO region. The fd and the BAR's length + * are delivered together: the length in the response body and the fd via + * SCM_RIGHTS ancillary data. + * + * Auth: auth_request_get_bar_fd. + * FD passing: outbound -- the BAR fd is sent via SCM_RIGHTS. + * + * Wire format: + * Request body: vrtd_req_get_bar_fd { uint32_t dev_number, + * uint8_t bar_number } + * Response body: vrtd_resp_get_bar_fd { uint64_t len } + * + SCM_RIGHTS fd + * + * @return VRTD_RET_OK on success, VRTD_RET_NOEXIST if the BAR is not present. + */ +static uint16_t client_handle_request_get_bar_fd( + struct client *client, + const struct vrtd_req_get_bar_fd *req_body, + uint16_t req_size, + struct vrtd_resp_get_bar_fd *resp_body, + uint16_t *resp_size, + int *out_fd, + bool *have_out_fd +) +{ + int ret = auth_request_get_bar_fd(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + *have_out_fd = false; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "get_bar_fd: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "get_bar_fd: device %u does not exist", (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + if (req_body->bar_number >= 6) { + LOG(LOG_WARNING, "get_bar_fd: invalid BAR number %u", (unsigned int)req_body->bar_number); + return VRTD_RET_BAD_REQUEST; + } + + struct slash_bar_file *bar_file = client->state->devices.d[req_body->dev_number]->bar_files[req_body->bar_number]; + if (bar_file == NULL) { + LOG(LOG_NOTICE, "get_bar_fd: BAR %u not available on device %u", + (unsigned int)req_body->bar_number, (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + resp_body->len = bar_file->len; + + /* Schedule this fd for delivery via SCM_RIGHTS in client_handle_out(). */ + *out_fd = bar_file->fd; + *have_out_fd = true; + + *resp_size = sizeof(*resp_body); + + LOG(LOG_DEBUG, "get_bar_fd: dev=%u bar=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, (unsigned int)req_body->bar_number, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} + +/* ---- GET_SENSOR_INFO ---------------------------------------------------- */ + +/** + * Helper: read one sensor type's value and unit modifier, populate an entry. + * + * @return true if the entry was populated, false on error (entry is skipped). + */ +static bool sensor_read_type( + ami_device *ami_dev, + const char *sensor_name, + enum ami_sensor_type type, + struct vrtd_sensor_entry *entry +) +{ + long value = 0; + enum ami_sensor_status status = AMI_SENSOR_STATUS_INVALID; + enum ami_sensor_unit_mod mod = AMI_SENSOR_UNIT_MOD_NONE; + int ret; + + switch (type) { + case AMI_SENSOR_TYPE_TEMP: + ret = ami_sensor_get_temp_value(ami_dev, sensor_name, &value, &status); + if (ret != AMI_STATUS_OK) return false; + ami_sensor_get_temp_unit_mod(ami_dev, sensor_name, &mod); + break; + case AMI_SENSOR_TYPE_CURRENT: + ret = ami_sensor_get_current_value(ami_dev, sensor_name, &value, &status); + if (ret != AMI_STATUS_OK) return false; + ami_sensor_get_current_unit_mod(ami_dev, sensor_name, &mod); + break; + case AMI_SENSOR_TYPE_VOLTAGE: + ret = ami_sensor_get_voltage_value(ami_dev, sensor_name, &value, &status); + if (ret != AMI_STATUS_OK) return false; + ami_sensor_get_voltage_unit_mod(ami_dev, sensor_name, &mod); + break; + case AMI_SENSOR_TYPE_POWER: + ret = ami_sensor_get_power_value(ami_dev, sensor_name, &value, &status); + if (ret != AMI_STATUS_OK) return false; + ami_sensor_get_power_unit_mod(ami_dev, sensor_name, &mod); + break; + default: + return false; + } + + memset(entry, 0, sizeof(*entry)); + snprintf(entry->name, sizeof(entry->name), "%s", sensor_name); + entry->type = (uint8_t)type; + entry->status = (uint8_t)status; + entry->unit_mod = (int8_t)mod; + entry->value = (int32_t)value; + + return true; +} + +/** + * Handles VRTD_REQ_GET_SENSOR_INFO -- queries all sensors for a device via + * the AMI (Alveo Management Interface) library and returns their current + * values and statuses. + * + * The AMI device handle is opened on-demand for PF0 (the AVED management + * function), sensors are discovered and read, then the handle is closed. + * + * Auth: auth_request_get_sensor_info (query-only). + * FD passing: none. + * + * Wire format: + * Request body: vrtd_req_get_sensor_info { uint32_t dev_number } + * Response body: vrtd_resp_get_sensor_info { uint32_t num_sensors, + * vrtd_sensor_entry sensors[] } + * + * @return VRTD_RET_OK on success, or an appropriate error code. + */ +static uint16_t client_handle_request_get_sensor_info( + struct client *client, + const struct vrtd_req_get_sensor_info *req_body, + uint16_t req_size, + struct vrtd_resp_get_sensor_info *resp_body, + uint16_t *resp_size +) +{ + int ret = auth_request_get_sensor_info(client, req_body); + if (ret == -1) { + return VRTD_RET_INTERNAL_ERROR; + } else if (ret == 0) { + return VRTD_RET_AUTH_ERROR; + } + + *resp_size = 0; + + if (req_size < sizeof(*req_body)) { + LOG(LOG_WARNING, "get_sensor_info: malformed request"); + return VRTD_RET_BAD_REQUEST; + } + + if (req_body->dev_number >= client->state->devices.len) { + LOG(LOG_NOTICE, "get_sensor_info: device %u does not exist", + (unsigned int)req_body->dev_number); + return VRTD_RET_NOEXIST; + } + + struct device *d = client->state->devices.d[req_body->dev_number]; + + /* Compute PF0 BDF for AMI (AMI runs on PF0, the AVED function). */ + char pf0_bdf[VRTD_PCI_BDF_LEN] = {0}; + if (pci_bdf_set_function(d->pci_info.bdf, 0, pf0_bdf) != 0) { + LOG(LOG_ERR, "get_sensor_info: failed to compute PF0 BDF from %s", + d->pci_info.bdf); + return VRTD_RET_INTERNAL_ERROR; + } + + /* Open AMI device handle on PF0. */ + ami_device *ami_dev = NULL; + ret = ami_dev_find(pf0_bdf, &ami_dev); + if (ret != AMI_STATUS_OK) { + LOG(LOG_ERR, "get_sensor_info: ami_dev_find(%s) failed: %s", + pf0_bdf, ami_get_last_error()); + return VRTD_RET_INTERNAL_ERROR; + } + + /* Discover sensors on the device. */ + ret = ami_sensor_discover(ami_dev); + if (ret != AMI_STATUS_OK) { + LOG(LOG_ERR, "get_sensor_info: ami_sensor_discover(%s) failed: %s", + pf0_bdf, ami_get_last_error()); + ami_dev_delete(&ami_dev); + return VRTD_RET_INTERNAL_ERROR; + } + + /* Get the list of sensors (grouped by name). */ + struct ami_sensor *sensors = NULL; + int num_sensors = 0; + ret = ami_sensor_get_sensors(ami_dev, &sensors, &num_sensors); + if (ret != AMI_STATUS_OK) { + LOG(LOG_ERR, "get_sensor_info: ami_sensor_get_sensors(%s) failed: %s", + pf0_bdf, ami_get_last_error()); + ami_dev_delete(&ami_dev); + return VRTD_RET_INTERNAL_ERROR; + } + + /* + * Iterate over each sensor name and each sensor type (temp, current, + * voltage, power). For each combination that exists, read the value + * and populate an entry in the response. + */ + static const enum ami_sensor_type sensor_types[] = { + AMI_SENSOR_TYPE_TEMP, + AMI_SENSOR_TYPE_CURRENT, + AMI_SENSOR_TYPE_VOLTAGE, + AMI_SENSOR_TYPE_POWER, + }; + + uint32_t count = 0; + + for (struct ami_sensor *s = sensors; s != NULL; s = s->next) { + /* Check which types this sensor supports. */ + uint32_t type_mask = 0; + if (ami_sensor_get_type(ami_dev, s->name, &type_mask) != AMI_STATUS_OK) { + continue; + } + + for (size_t t = 0; t < sizeof(sensor_types) / sizeof(sensor_types[0]); t++) { + if (!(type_mask & sensor_types[t])) { + continue; + } + + if (count >= VRTD_SENSOR_MAX_ENTRIES) { + LOG(LOG_WARNING, "get_sensor_info: sensor count exceeds message limit, " + "truncating at %u entries", count); + goto done; + } + + if (sensor_read_type(ami_dev, s->name, sensor_types[t], + &resp_body->sensors[count])) { + count++; + } + } + } + +done: + ami_dev_delete(&ami_dev); + + resp_body->num_sensors = count; + *resp_size = (uint16_t)(sizeof(resp_body->num_sensors) + + count * sizeof(struct vrtd_sensor_entry)); + + LOG(LOG_DEBUG, "get_sensor_info: dev=%u sensors=%u uid=%u conn_id=%llu", + (unsigned int)req_body->dev_number, count, + (unsigned int)client->uid, (unsigned long long)client->conn_id); + + return VRTD_RET_OK; +} diff --git a/vrt/vrtd/src/serve.h b/vrt/vrtd/src/serve.h new file mode 100644 index 00000000..55cdd9ba --- /dev/null +++ b/vrt/vrtd/src/serve.h @@ -0,0 +1,192 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file serve.h + * @brief Client connection state and I/O handling for the vrtd daemon. + * + * Each connected userspace application is represented by a @c struct @c client. + * The daemon communicates with clients over AF_UNIX sockets using a simple + * request/response protocol defined in vrtd/wire.h. File descriptors (e.g. + * BAR mmap regions, QDMA queue-pair fds) are passed out-of-band via + * SCM_RIGHTS ancillary data. + * + * The client I/O state machine is driven by the systemd sd-event loop: + * 1. A complete request is read into @c inb. + * 2. The request is dispatched (auth-checked, then executed). + * 3. The response is written from @c outb. + * + * Return codes from request handlers use the SERVE_CONTINUE / SERVE_DISCONNECT + * convention to tell the I/O loop whether to keep or drop the connection. + */ + +#ifndef VRTD_SERVE_H +#define VRTD_SERVE_H + +#include +#include + +#include +#include + +#include "array.h" + +struct device; + +/** + * @brief Per-client connection state for the vrtd daemon. + * + * One instance exists for every connected userspace application. The struct + * owns the socket fd, the message buffers, and holds the credentials and + * role resolved at connection time. + */ +struct client { + /** @brief Inbound message buffer (request from client). + * Sized to VRTD_MSG_MAX_SIZE bytes. */ + uint8_t inb[VRTD_MSG_MAX_SIZE]; + /** @brief Outbound message buffer (response to client). + * Sized to VRTD_MSG_MAX_SIZE bytes. */ + uint8_t outb[VRTD_MSG_MAX_SIZE]; + + /** @brief Client AF_UNIX socket file descriptor. */ + int fd; + + /** @brief File descriptor received from the client via SCM_RIGHTS ancillary data. */ + int in_fd; + /** @brief True when @c in_fd contains a valid received file descriptor. */ + bool have_in_fd; + + /** @brief File descriptor to send back to the client via SCM_RIGHTS ancillary data. */ + int out_fd; + /** @brief True when @c out_fd contains a valid file descriptor to transmit. */ + bool have_out_fd; + + /** @brief True when a complete request has been read into @c inb and is awaiting dispatch. */ + bool have_request; + /** @brief True when a response in @c outb is ready (or partially written) for the client. */ + bool have_response; + /** @brief True when a new response has just been prepared and needs initial write. */ + bool have_new_response; + /** @brief True while an asynchronous bitstream design write is in progress for this client. */ + bool pending_design_write; + /** @brief The device on which the pending asynchronous design write is running (non-owning). */ + struct device *pending_design_write_device; + + /** @brief Bitmask of epoll events currently requested for this client's fd. */ + uint32_t wanted_epoll_events; + + /** @brief UID of the connected client process, obtained via SO_PEERCRED. */ + uid_t uid; + /** @brief Unique monotonically increasing connection identifier assigned at accept time. */ + uint64_t conn_id; + /** @brief Supplementary group IDs of the connected client process, obtained via SO_PEERCRED. */ + struct gid_t_array gids; + + /** @brief Back-pointer to the global daemon state (non-owning). */ + struct vrtd *state; + /** @brief Role assigned to this client based on UID/GID credential lookup (non-owning). */ + struct role *role; + + /** @brief Systemd event source registration for this client's socket I/O. */ + sd_event_source *event_source; +}; + +/** + * @brief Cast the inbound buffer of client @p C to a request header pointer. + * @param C A @c struct @c client (by value or lvalue). + */ +#define CLIENT_IN_HEADER(C) ((struct vrtd_req_header *) (C).inb) +/** + * @brief Cast the outbound buffer of client @p C to a response header pointer. + * @param C A @c struct @c client (by value or lvalue). + */ +#define CLIENT_OUT_HEADER(C) ((struct vrtd_resp_header *) (C).outb) + +/** + * @brief Cast the inbound buffer of client @p C to a request body of type @p T. + * @param C A @c struct @c client (by value or lvalue). + * @param T The struct type name of the request body (without "struct" prefix in the macro argument). + */ +#define CLIENT_IN_BODY(C, T) ((struct T *) ((C).inb + sizeof(struct vrtd_req_header))) +/** + * @brief Cast the outbound buffer of client @p C to a response body of type @p T. + * @param C A @c struct @c client (by value or lvalue). + * @param T The struct type name of the response body (without "struct" prefix in the macro argument). + */ +#define CLIENT_OUT_BODY(C, T) ((struct T *) ((C).outb + sizeof(struct vrtd_resp_header))) + +/** + * @brief Release all resources owned by a client (socket, event source, buffers). + * @param client Pointer to the client to clean up. Fields are zeroed after release. + */ +void cleanup_client(struct client *client); + +/** + * @brief Cleanup helper for use with __attribute__((cleanup)). + * + * Calls cleanup_client on the pointed-to client pointer, then NULLs it. + * + * @param clientp Address of a @c struct @c client pointer. + */ +static inline +void cleanup_clientp(struct client **clientp) +{ + if (clientp == NULL) { + return; + } + + cleanup_client(*clientp); + + *clientp = NULL; +} + +DECLARE_OWNING_PTR_ARRAY(client_ptr_array, struct client *, cleanup_client) + +/** + * @brief Callback invoked by the systemd event loop when a client socket is ready for I/O. + * + * Drives the per-client state machine: reads requests, dispatches them through + * the auth and handler layers, and writes responses. File descriptors are + * exchanged via SCM_RIGHTS ancillary messages. + * + * @param s The event source that fired. + * @param fd The client socket file descriptor. + * @param revents The epoll event mask (EPOLLIN, EPOLLOUT, ...). + * @param user Opaque pointer to the owning @c struct @c client. + * @return 0 on success (SERVE_CONTINUE), or a negative errno on fatal error + * (SERVE_DISCONNECT causes the event source to be removed and the + * client to be freed). + */ +int on_client_io(sd_event_source *s, int fd, uint32_t revents, void *user); + +/** + * @brief Deferred-work timer callback for completing asynchronous operations. + * + * Invoked by the systemd event loop after a short delay to poll for completion + * of asynchronous design writes and finalize the response to the client. + * + * @param s The timer event source that fired. + * @param usec The scheduled wakeup time in microseconds. + * @param user Opaque pointer to the owning @c struct @c client. + * @return 0 on success, or a negative errno on error. + */ +int on_event_deferred_work(sd_event_source *s, uint64_t usec, void *user); + +#endif // VRTD_SERVE_H diff --git a/vrt/vrtd/src/signals.c b/vrt/vrtd/src/signals.c new file mode 100644 index 00000000..522c8777 --- /dev/null +++ b/vrt/vrtd/src/signals.c @@ -0,0 +1,132 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file signals.c + * @brief Signal handling for graceful shutdown and live configuration reload. + * + * vrtd uses sd_event_add_signal() to receive signals through the event loop + * (via signalfd) rather than traditional async signal handlers. This avoids + * the usual signal-safety pitfalls and lets us call arbitrary library + * functions from the handler. + * + * Handled signals: + * - SIGINT / SIGTERM -- Initiate graceful shutdown by exiting the event loop. + * - SIGHUP -- Reload the configuration file without restarting the + * daemon (all connected clients have their resolved + * roles invalidated so they are re-evaluated against + * the new config on the next request). + * - SIGPIPE -- Ignored (set to SIG_IGN in main.c/configure_signals) + * because clients can disconnect at any time and we + * must not be killed by a write to a broken socket. + */ + +#define _GNU_SOURCE + +#include "signals.h" + +#include +#include +#include +#include + +#include "state.h" +#include "config.h" +#include "utils.h" + +int reload_config(struct vrtd *state); + +/** + * sd_event signal callback dispatched when SIGINT, SIGTERM, SIGHUP, or + * SIGQUIT is received via the signalfd. + * + * - SIGINT / SIGTERM: request a clean exit from the event loop so that + * destructors run and STOPPING=1 is sent to systemd. + * - SIGHUP: live-reload the configuration from disk. + * - Others: logged as unhandled (should not occur given the signal mask + * set up in main.c). + */ +int on_event_signal(sd_event_source *s, const struct signalfd_siginfo *si, void *userdata) +{ + int sig = si->ssi_signo; + + struct vrtd *state = userdata; + assert(state != NULL); + + // Log or act based on the signal + switch (sig) { + case SIGINT: + case SIGTERM: { + // Stop the event loop gracefully + LOG(LOG_INFO, "Received signal %s (%d), shutting down", sigabbrev_np(sig), sig); + sd_event *event = sd_event_source_get_event(s); + if (event) { + sd_event_exit(event, 0); + } + break; + } + + case SIGHUP: { + LOG(LOG_INFO, "Received SIGHUP, reloading configuration"); + reload_config(state); + break; + } + + default: { + LOG(LOG_WARNING, "Unhandled signal: %s (%d)\n", sigabbrev_np(sig), sig); + + break; + } + } + + return 0; +} + +/** + * Reload the daemon's configuration from disk. + * + * Existing client role assignments are invalidated (cleaned up) so that each + * client's role is re-resolved from the new configuration on its next request. + * This avoids disconnecting clients simply because the config file changed. + * + * If loading the new configuration fails, the old config has already been + * freed -- the daemon continues to run but all role lookups will fail until + * a subsequent successful reload or restart. + */ +int reload_config(struct vrtd *state) +{ + /* Invalidate cached roles for every connected client so they are + * re-evaluated against the incoming configuration. */ + for (size_t i = 0; i < state->clients.len; i++) { + struct client *client = state->clients.d[i]; + assert(client != NULL); + + cleanup_rolep(&client->role); + } + + cleanup_configp(&state->config); + + int ret = config_load(&state->config); + PROPAGATE_ERROR(ret); + + LOG(LOG_INFO, "Configuration reloaded successfully"); + + return 0; +} diff --git a/smi/src/commands/reload_command.cpp b/vrt/vrtd/src/signals.h similarity index 69% rename from smi/src/commands/reload_command.cpp rename to vrt/vrtd/src/signals.h index 45acb7cb..b4aceaba 100644 --- a/smi/src/commands/reload_command.cpp +++ b/vrt/vrtd/src/signals.h @@ -18,15 +18,11 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "commands/reload_command.hpp" +#ifndef VRTD_SIGNALS_H +#define VRTD_SIGNALS_H -ReloadCommand::ReloadCommand(const std::string& device) : device(device) {} +#include -void ReloadCommand::execute() { - PcieDriverHandler driver(device + ":00.0"); - std::cout << "Reloading device " << device << ":00.0" << std::endl; - driver.execute(PcieDriverHandler::Command::REMOVE); - driver.execute(PcieDriverHandler::Command::RESCAN); - driver.execute(PcieDriverHandler::Command::HOTPLUG); - std::cout << "Device " << device << ":00.0 reloaded" << std::endl; -} \ No newline at end of file +int on_event_signal(sd_event_source *s, const struct signalfd_siginfo *si, void *userdata); + +#endif // VRTD_SIGNALS_H diff --git a/submodules/v80-vitis-flow/src/xml_parser/resource.cpp b/vrt/vrtd/src/state.h similarity index 72% rename from submodules/v80-vitis-flow/src/xml_parser/resource.cpp rename to vrt/vrtd/src/state.h index 7f785022..a341d2f8 100644 --- a/submodules/v80-vitis-flow/src/xml_parser/resource.cpp +++ b/vrt/vrtd/src/state.h @@ -18,17 +18,22 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "resource.hpp" +#ifndef VRTD_STATE_H +#define VRTD_STATE_H -std::string Resource::getName() { return this->name; } +#include -void Resource::setName(const std::string& name) { this->name = name; } +#include "device.h" +#include "config.h" +#include "serve.h" -uint32_t Resource::getValue() { return this->value; } +struct vrtd { + struct config *config; -void Resource::setValue(uint32_t value) { this->value = value; } + struct client_ptr_array clients; + uint64_t next_conn_id; -void Resource::print() { - utils::Logger::log(utils::LogLevel::INFO, __PRETTY_FUNCTION__, "Resource: {}, Value: {}", - this->name, this->value); -} \ No newline at end of file + struct device_ptr_array devices; +}; + +#endif // VRTD_STATE_H diff --git a/vrt/vrtd/src/utils.c b/vrt/vrtd/src/utils.c new file mode 100644 index 00000000..b20f6882 --- /dev/null +++ b/vrt/vrtd/src/utils.c @@ -0,0 +1,34 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "utils.h" + +#include +#include + +const char *uid_to_username(uid_t uid, char *buf, size_t bufsz) +{ + struct passwd pwent, *pw = NULL; + if (getpwuid_r(uid, &pwent, buf, bufsz, &pw) != 0 || pw == NULL) { + buf[0] = '\0'; + return buf; + } + return pw->pw_name; +} diff --git a/vrt/vrtd/src/utils.h b/vrt/vrtd/src/utils.h new file mode 100644 index 00000000..acab1504 --- /dev/null +++ b/vrt/vrtd/src/utils.h @@ -0,0 +1,380 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * @file utils.h + * @brief Utility macros and helpers used throughout the vrtd daemon. + * + * This header provides several categories of utilities: + * + * @section error_prop Error-propagation macros + * + * The PROPAGATE_ERROR family of macros provides concise, consistent error + * handling for functions that return -1 (POSIX), NULL (allocation), or + * negative errno (systemd). Each macro evaluates an expression, checks + * the result against a type-specific failure condition, and if the check + * fails, optionally logs a message via sd_journal and returns -1 from the + * calling function. + * + * Variants: + * - @c PROPAGATE_ERROR(expr) -- fails on -1, no log. + * - @c PROPAGATE_ERROR_NULL(expr) -- fails on NULL, no log. + * - @c PROPAGATE_ERROR_SD(expr) -- fails on < 0 (systemd convention), no log. + * - @c PROPAGATE_ERROR_LOG(...) -- fails on -1, logs a formatted message. + * - @c PROPAGATE_ERROR_NULL_LOG(...) -- fails on NULL, logs a formatted message. + * - @c PROPAGATE_ERROR_STDC_LOG(...) -- fails on -1, logs with appended strerror (%m). + * - @c PROPAGATE_ERROR_NULL_STDC_LOG(...) -- fails on NULL, logs with appended strerror. + * - @c PROPAGATE_ERROR_SD_LOG(...) -- fails on < 0, logs with systemd error string. + * + * @section cleanup Cleanup attribute helpers + * + * The @c _cleanup_(fn) macro wraps GCC/Clang's @c __attribute__((cleanup)) + * to automatically call @p fn when the annotated variable goes out of scope. + * Combined with @c cleanup_free (generic heap pointer) and @c cleanup_argv + * (NULL-terminated string array), this enables RAII-style resource management + * in C. + * + * @section misc Miscellaneous + * + * - @c LOG -- shorthand for sd_journal_print (cast to void to suppress + * unused-result warnings). + * - @c NODISCARD -- portable warn_unused_result attribute. + * - @c bit_ceil -- type-generic smallest power-of-two >= n. + * - @c max / @c min -- type-safe comparisons using GCC statement expressions. + * - @c SIZEOF_ARRAY -- element count for statically-sized arrays. + * - @c unlikely / @c likely -- branch-prediction hints. + * - @c string_to_bool -- lenient boolean parser ("1", "y", "yes", "true"). + * - @c glob_err_to_string -- human-readable glob(3) error descriptions. + * - @c uid_to_username -- resolve a UID to a username string. + */ + +#ifndef VRTD_UTILS_H +#define VRTD_UTILS_H + +#include +#include +#include +#include +#include +#include + +#include +#include + +/** @brief Shorthand for sd_journal_print, cast to void to suppress unused-result warnings. */ +#define LOG (void) sd_journal_print + +/* + * Look up the username for @uid. Writes the name into @buf (size @bufsz). + * Returns @buf on success, or an empty string if the lookup fails. + */ +const char *uid_to_username(uid_t uid, char *buf, size_t bufsz); + +#if defined(__has_include) +# if __has_include() +# include +# define HAVE_STDBIT 1 +# endif +#endif + +/** @brief Portable attribute to warn if a function's return value is discarded. */ +#define NODISCARD __attribute__((warn_unused_result)) + +/* ---- type-specific helpers ---- */ +#if HAVE_STDBIT +/** + * @brief Return the smallest power of two >= @p n (32-bit). + * @param n Input value. + * @return Smallest power of two >= n, or 0 if not representable. + */ +static inline uint32_t bit_ceil_u32(uint32_t n) { + return stdc_bit_ceil((unsigned int)(n)); +} +/** + * @brief Return the smallest power of two >= @p n (64-bit). + * @param n Input value. + * @return Smallest power of two >= n, or 0 if not representable. + */ +static inline uint64_t bit_ceil_u64(uint64_t n) { + return stdc_bit_ceil((unsigned long long)(n)); +} +#else +/** + * @brief Return the smallest power of two >= @p n (32-bit, GCC/Clang fallback). + * @param n Input value. + * @return Smallest power of two >= n, or 0 if not representable. + */ +static inline uint32_t bit_ceil_u32(uint32_t n) { + if (n == 0) return 1u; + if (n > 0x80000000u) return 0u; // not representable + return 1u << (32 - __builtin_clz(n - 1)); // GCC/Clang +} +/** + * @brief Return the smallest power of two >= @p n (64-bit, GCC/Clang fallback). + * @param n Input value. + * @return Smallest power of two >= n, or 0 if not representable. + */ +static inline uint64_t bit_ceil_u64(uint64_t n) { + if (n == 0) return 1ull; + if (n > 0x8000000000000000ull) return 0ull; // not representable + return 1ull << (64 - __builtin_clzll(n - 1)); +} +#endif + +/** + * @brief Type-generic smallest power-of-two >= n. + * + * Dispatches to bit_ceil_u32 or bit_ceil_u64 based on the argument type. + */ +/* ---- generic front-end ---- */ +#ifdef __cplusplus +#define bit_ceil(n) \ + (sizeof(n) <= sizeof(uint32_t) ? bit_ceil_u32(static_cast(n)) \ + : bit_ceil_u64(static_cast(n))) +#else +#define bit_ceil(n) _Generic((n), \ + uint32_t: bit_ceil_u32, \ + uint64_t: bit_ceil_u64 \ +)(n) +#endif + +/** + * @brief Type-safe maximum of two values (GCC statement expression). + * @param a First value. + * @param b Second value. + * @return The larger of @p a and @p b. + */ +#define max(a,b) \ + ({ __auto_type _a = (a); \ + __auto_type _b = (b); \ + _a > _b ? _a : _b; }) + +/** + * @brief Type-safe minimum of two values (GCC statement expression). + * @param a First value. + * @param b Second value. + * @return The smaller of @p a and @p b. + */ +#define min(a,b) \ + ({ __auto_type _a = (a); \ + __auto_type _b = (b); \ + _a < _b ? _a : _b; }) + +/** @brief Number of elements in a statically-sized array. */ +#define SIZEOF_ARRAY(X) (sizeof(X) / sizeof(X[0])) + +/** @brief No-operation statement (void expression). */ +#define NOP() ((void) 0) + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L + #define NODISCARD [[nodiscard]] +#elif defined(__GNUC__) || defined(__clang__) + #define NODISCARD __attribute__((warn_unused_result)) +#else + #define NODISCARD +#endif + +/** @brief Branch-prediction hint: expression is expected to be false. */ +#ifndef unlikey +#define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +/** @brief Branch-prediction hint: expression is expected to be true. */ +#ifndef likely +#define likely(x) __builtin_expect(!!(x), 1) +#endif + +/** + * @brief Shorthand for __attribute__((cleanup(FOO))). + * + * Automatically calls @p FOO on the annotated variable when it goes out of + * scope, enabling RAII-style resource management in C. + * + * @param FOO Cleanup function taking a pointer to the variable's type. + */ +#ifndef _cleanup_ +#define _cleanup_(FOO) __attribute__((cleanup(FOO))) +#endif + +/* + * Internal error-propagation building blocks. + * Do not use directly -- use the PROPAGATE_ERROR_* macros below. + */ +#define _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, CMP, JUMP) \ + ({ \ + __auto_type _ret = RET; \ + if (CMP) { \ + JUMP; \ + } \ + }) + +#define _PROPAGATE_ERROR_INTERNAL_LOG(RET, CMP, JUMP, LOGLEVEL, FMT, ...) \ + ({ \ + __auto_type _ret = RET; \ + if (CMP) { \ + sd_journal_print(LOGLEVEL, FMT, ##__VA_ARGS__); \ + JUMP; \ + } \ + }) + +/** @brief Propagate error: return -1 if @p RET == -1 (POSIX convention). No logging. */ +#define PROPAGATE_ERROR(RET) \ + _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, (_ret == -1), return -1) +/** @brief Propagate error: return -1 if @p RET == NULL (allocation failure). No logging. */ +#define PROPAGATE_ERROR_NULL(RET) \ + _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, (_ret == NULL), return -1) +/** @brief Propagate error: return -1 if @p RET < 0 (systemd/negative-errno convention). No logging. */ +#define PROPAGATE_ERROR_SD(RET) \ + _PROPAGATE_ERROR_INTERNAL_NOLOG(RET, (_ret < 0), return -1) + +/** @brief Propagate error with logging: return -1 if @p RET == -1. */ +#define PROPAGATE_ERROR_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == -1), return -1, LOGLEVEL, FMT, ##__VA_ARGS__) +/** @brief Propagate error with logging: return -1 if @p RET == NULL. */ +#define PROPAGATE_ERROR_NULL_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == NULL), return -1, LOGLEVEL, FMT, ##__VA_ARGS__) +/** @brief Propagate error with strerror logging: return -1 if @p RET == -1. Appends ": ". */ +#define PROPAGATE_ERROR_STDC_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == -1), return -1, LOGLEVEL, FMT ": %m", ##__VA_ARGS__) +/** @brief Propagate error with strerror logging: return -1 if @p RET == NULL. Appends ": ". */ +#define PROPAGATE_ERROR_NULL_STDC_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret == NULL), return -1, LOGLEVEL, FMT ": %m", ##__VA_ARGS__) +/** @brief Propagate error with systemd error logging: return -1 if @p RET < 0. Appends ": ". */ +#define PROPAGATE_ERROR_SD_LOG(RET, LOGLEVEL, FMT, ...) \ + _PROPAGATE_ERROR_INTERNAL_LOG(RET, (_ret < 0), return -1, LOGLEVEL, FMT ": %s", ##__VA_ARGS__, strerrordesc_np(-_ret)) + +/** + * @brief Convert a glob(3) error code to a human-readable string. + * @param err The glob error code (0, GLOB_NOSPACE, GLOB_ABORTED, or GLOB_NOMATCH). + * @return A static string describing the error. + */ +static inline const char *glob_err_to_string(int err) +{ + switch (err) { + case 0: + return "OK"; + case GLOB_NOSPACE: + return "out of memory"; + case GLOB_ABORTED: + return "read error"; + case GLOB_NOMATCH: + return "no matches found"; + default: + return "unknown glob(3) error"; + } +} + +/** + * @brief Generic cleanup function for heap-allocated pointers. + * + * Suitable for use with @c _cleanup_. Frees the pointer and sets it to NULL. + * + * @param p Address of a @c void* variable to free. + */ +static inline +void cleanup_free(void *p) { + void **ptr = (void**)p; + free(*ptr); + + *ptr = NULL; +} + +/** + * @brief Cleanup function for a NULL-terminated array of heap-allocated strings. + * + * Frees each string in the array, then frees the array itself. + * Suitable for use with @c _cleanup_. + * + * @param p Address of a @c char** variable (NULL-terminated string array). + */ +static inline +void cleanup_argv(char ***p) { + char **ptr = *p; + char **ptrel = ptr; + + if (!ptr) { + return; + } + + while (*ptrel) { + free(*ptrel); + ptrel++; + } + + free(ptr); + + *p = NULL; +} + +/** + * @brief Parse a string as a boolean value (lenient). + * + * Recognizes (case-insensitive, whitespace-trimmed): + * "1", "y", "Y" -> true + * "yes" -> true + * "true" -> true + * Everything else -> false + * + * @param s The string to parse (may be NULL). + * @return true if the string represents a truthy value, false otherwise. + */ +static inline +bool string_to_bool(const char *s) +{ + if (unlikely(!s)) { + return false; + } + + // Trim leading/trailing ASCII whitespace (locale-agnostic) + while (isspace(*s)) { + s++; + } + size_t n = strlen(s); + while (n && isspace(s[n-1])) { + n--; + } + + if (unlikely(n == 0)) { + return false; + } + + // Fast-path single-char cases + if (n == 1) { + char c = s[0]; + if (c == '1' || c == 'y' || c == 'Y') { + return true; + } + return false; + } + + // "yes" + if (n == 3 && strncasecmp(s, "yes", 3) == 0) { + return true; + } + + // "true" + if (n == 4 && strncasecmp(s, "true", 4) == 0) { + return true; + } + + return false; +} + +#endif // VRTD_UTILS_H diff --git a/examples/03_multiple_boards/Makefile b/vrt/vrtd/systemd/vrtd.service similarity index 60% rename from examples/03_multiple_boards/Makefile rename to vrt/vrtd/systemd/vrtd.service index fd315bab..0bf7a320 100644 --- a/examples/03_multiple_boards/Makefile +++ b/vrt/vrtd/systemd/vrtd.service @@ -1,16 +1,16 @@ # ################################################################################################## # The MIT License (MIT) -# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. -# +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# # Permission is hereby granted, free of charge, to any person obtaining a copy of this software # and associated documentation files (the "Software"), to deal in the Software without restriction, # including without limitation the rights to use, copy, modify, merge, publish, distribute, # sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: -# +# # The above copyright notice and this permission notice shall be included in all copies or # substantial portions of the Software. -# +# # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT # NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, @@ -18,31 +18,47 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # ################################################################################################## -HLS_BUILD_DIR_ACCUMULATE=build_accumulate.xcv80-lsva4737-2MHP-e-S -HLS_BUILD_DIR_INCREMENT=build_increment.xcv80-lsva4737-2MHP-e-S -DESIGN_NAME=00_example -HOME_DIR=$(shell realpath .) -BUILD_DIR=$(shell realpath ./build) -HLS_DIR=$(shell realpath ./hls) -V80PP_PATH=$(shell realpath ../../submodules/v80-vitis-flow) -VPP_DIR=$(BUILD_DIR)/v80-vitis-flow - -.PHONY: all setup app clean - -all: setup app - -setup: - mkdir -p $(BUILD_DIR) - -app: setup - @echo "Running user app build step" - mkdir -p $(BUILD_DIR) && cd $(BUILD_DIR) && \ - cmake .. && \ - make -j9 - @echo "Setting LD_LIBRARY_PATH" - export LD_LIBRARY_PATH=$$(dirname $$(which vivado))/../lib/lnx64.o:$$LD_LIBRARY_PATH - @echo "Setting PATH" - export PATH=$$PATH:/usr/local/sbin - -clean: - rm -rf $(BUILD_DIR) \ No newline at end of file +[Unit] +Description=vrtd daemon for SLASH +Requires=vrtd.socket +After=vrtd.socket + +[Service] +LogLevelMax=info + + +Type=notify +ExecStart=/usr/lib/vrt/vrtd +User=vrtd +Group=vrtd + +WatchdogSec=60s + +DevicePolicy=auto +PrivateDevices=false + +# Create a writable runtime dir for any transient files +RuntimeDirectory=vrtd +RuntimeDirectoryMode=0755 + +# Hardening +NoNewPrivileges=true +ProtectSystem=full +ProtectHome=true +PrivateTmp=true +ProtectKernelTunables=true +ProtectKernelModules=true +ProtectControlGroups=true +LockPersonality=true +MemoryDenyWriteExecute=true +RestrictRealtime=true +RestrictSUIDSGID=true +SystemCallArchitectures=native +RestrictAddressFamilies=AF_UNIX +ReadWritePaths=/run/vrtd + +Restart=on-failure +RestartSec=2s + +[Install] +WantedBy=multi-user.target diff --git a/vrt/vrtd/systemd/vrtd.socket b/vrt/vrtd/systemd/vrtd.socket new file mode 100644 index 00000000..97718ce4 --- /dev/null +++ b/vrt/vrtd/systemd/vrtd.socket @@ -0,0 +1,33 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +[Unit] +Description=vrtd UNIX SEQPACKET socket + +[Socket] +ListenSequentialPacket=/run/vrtd.sock +FileDescriptorName=api +SocketMode=0666 +SocketGroup=vrt +RemoveOnStop=yes +DirectoryMode=0755 + +[Install] +WantedBy=sockets.target diff --git a/vrt/vrtd/sysusers/vrtd.conf b/vrt/vrtd/sysusers/vrtd.conf new file mode 100644 index 00000000..95773ecd --- /dev/null +++ b/vrt/vrtd/sysusers/vrtd.conf @@ -0,0 +1,23 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +u vrtd - "VRTd daemon user" +g vrt - +g vrtadmin - diff --git a/vrt/vrtd/tests/CMakeLists.txt b/vrt/vrtd/tests/CMakeLists.txt new file mode 100644 index 00000000..f5197f45 --- /dev/null +++ b/vrt/vrtd/tests/CMakeLists.txt @@ -0,0 +1,33 @@ +include(FetchContent) +FetchContent_Declare( + googletest + URL https://github.com/google/googletest/archive/refs/tags/v1.17.0.zip +) +FetchContent_MakeAvailable(googletest) + +enable_testing() + +include(GoogleTest) + +add_custom_target(unit_tests) + +macro(add_vrtd_test test_name test_source) + add_executable(${test_name} ${test_source}) + target_link_libraries(${test_name} PRIVATE GTest::gtest_main GTest::gmock vrtd_core) + set_target_properties(${test_name} PROPERTIES + CXX_STANDARD 20 + CXX_STANDARD_REQUIRED YES + ) + gtest_discover_tests(${test_name}) + add_dependencies(unit_tests ${test_name}) +endmacro() + +add_vrtd_test(allocator_test allocator_test.cpp) +add_vrtd_test(array_test array_test.cpp) +add_vrtd_test(utils_test utils_test.cpp) +add_vrtd_test(hotplug_test hotplug_test.cpp) +add_vrtd_test(config_test config_test.cpp) +add_vrtd_test(auth_test auth_test.cpp) +add_vrtd_test(buffer_test buffer_test.cpp) +add_vrtd_test(design_writer_test design_writer_test.cpp) +add_vrtd_test(device_test device_test.cpp) diff --git a/vrt/vrtd/tests/allocator_test.cpp b/vrt/vrtd/tests/allocator_test.cpp new file mode 100644 index 00000000..e6970ce0 --- /dev/null +++ b/vrt/vrtd/tests/allocator_test.cpp @@ -0,0 +1,361 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +extern "C" { +#include "allocator.h" +} + +class AllocatorTest : public ::testing::Test { + protected: + struct device_memory_map *map = nullptr; + + void SetUp() override { + map = device_memory_map_create(); + ASSERT_NE(map, nullptr); + } + + void TearDown() override { + device_memory_map_cleanup(map); + } +}; + +// --- Create / Destroy --- + +TEST_F(AllocatorTest, CreateReturnsNonNull) { + EXPECT_NE(map, nullptr); +} + +TEST_F(AllocatorTest, FreshMapHasAllRegionsFree) { + for (int r = 0; r < DDR_REGIONS; r++) { + for (int s = 0; s < (int)SUBREGIONS_PER_REGION; s++) { + EXPECT_EQ(map->ddr_regions[r].client_id[s], 0u); + } + } + for (int r = 0; r < HBM_REGIONS; r++) { + for (int s = 0; s < (int)SUBREGIONS_PER_REGION; s++) { + EXPECT_EQ(map->hbm_regions[r].client_id[s], 0u); + } + } +} + +TEST_F(AllocatorTest, CleanupNullIsSafe) { + device_memory_map_cleanup(nullptr); +} + +// --- Argument validation --- + +TEST_F(AllocatorTest, AllocateNullMap) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(nullptr, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, AllocateNullSize) { + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, nullptr, 0, 1, &addr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, AllocateNullAddrOut) { + uint64_t size = SUBREGION_SIZE; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, nullptr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, AllocateZeroSize) { + uint64_t size = 0; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, AllocateZeroClientId) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 0, &addr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, FreeNullMap) { + EXPECT_EQ(device_memory_map_free(nullptr, ALLOCATION_TYPE_DDR, DDR_START_ADDRESS, SUBREGION_SIZE, 1), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, FreeZeroSize) { + EXPECT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, DDR_START_ADDRESS, 0, 1), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, FreeZeroClientId) { + EXPECT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, DDR_START_ADDRESS, SUBREGION_SIZE, 0), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +// --- DDR allocation --- + +TEST_F(AllocatorTest, DdrSingleSubregion) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, DDR_START_ADDRESS); + EXPECT_EQ(size, SUBREGION_SIZE); +} + +TEST_F(AllocatorTest, DdrSizeRoundsUp) { + uint64_t size = 1; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(size, SUBREGION_SIZE); +} + +TEST_F(AllocatorTest, DdrMultiSubregion) { + uint64_t size = 3 * SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, DDR_START_ADDRESS); + EXPECT_EQ(size, 3 * SUBREGION_SIZE); + + for (int i = 0; i < 3; i++) { + EXPECT_EQ(map->ddr_regions[0].client_id[i], 1u); + } + for (int i = 3; i < (int)SUBREGIONS_PER_REGION; i++) { + EXPECT_EQ(map->ddr_regions[0].client_id[i], 0u); + } +} + +TEST_F(AllocatorTest, DdrFullRegion) { + uint64_t size = SUBREGIONS_PER_REGION * SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, DDR_START_ADDRESS); +} + +TEST_F(AllocatorTest, DdrExceedsSingleRegion) { + uint64_t size = (SUBREGIONS_PER_REGION + 1) * SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, DdrSecondAllocationFollowsFirst) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr1, addr2; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr1), + ALLOCATION_RESULT_SUCCESS); + size = SUBREGION_SIZE; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr2), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr2, DDR_START_ADDRESS + SUBREGION_SIZE); +} + +TEST_F(AllocatorTest, DdrSpillsToNextRegion) { + uint64_t size = SUBREGIONS_PER_REGION * SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + + size = SUBREGION_SIZE; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 2, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, DDR_START_ADDRESS + REGION_SIZE); +} + +TEST_F(AllocatorTest, DdrExhaustAllRegions) { + for (int r = 0; r < DDR_REGIONS; r++) { + uint64_t size = SUBREGIONS_PER_REGION * SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + } + + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_NO_MEMORY); +} + +// --- HBM allocation (pinned region) --- + +TEST_F(AllocatorTest, HbmPinnedRegion) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM, &size, 5, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, HBM_START_ADDRESS + 5 * REGION_SIZE); +} + +TEST_F(AllocatorTest, HbmRegionOutOfRange) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM, &size, HBM_REGIONS, 1, &addr), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, HbmPinnedRegionExhaustion) { + for (int s = 0; s < (int)SUBREGIONS_PER_REGION; s++) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + } + + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM, &size, 0, 1, &addr), + ALLOCATION_RESULT_NO_MEMORY); +} + +// --- HBM_VNOC allocation (auto-region) --- + +TEST_F(AllocatorTest, HbmVnocAutoSelection) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + EXPECT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM_VNOC, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, HBM_START_ADDRESS); +} + +TEST_F(AllocatorTest, HbmVnocFirstFitAcrossRegions) { + for (int s = 0; s < (int)SUBREGIONS_PER_REGION; s++) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM_VNOC, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + } + + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM_VNOC, &size, 0, 2, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, HBM_START_ADDRESS + REGION_SIZE); +} + +// --- Free --- + +TEST_F(AllocatorTest, FreeAndReallocate) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + ASSERT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, addr, size, 1), + ALLOCATION_RESULT_SUCCESS); + + EXPECT_EQ(map->ddr_regions[0].client_id[0], 0u); + + size = SUBREGION_SIZE; + uint64_t addr2; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 2, &addr2), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr2, addr); +} + +TEST_F(AllocatorTest, FreeWrongClientIdDenied) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + + EXPECT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, addr, size, 99), + ALLOCATION_RESULT_BAD_ARGUMENT); + + EXPECT_EQ(map->ddr_regions[0].client_id[0], 1u); +} + +TEST_F(AllocatorTest, FreeUnalignedAddress) { + EXPECT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, DDR_START_ADDRESS + 1, SUBREGION_SIZE, 1), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, FreeAddressOutOfRange) { + EXPECT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, 0, SUBREGION_SIZE, 1), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, FreeCrossRegionSpan) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr = DDR_START_ADDRESS + (SUBREGIONS_PER_REGION - 1) * SUBREGION_SIZE; + uint64_t free_size = 2 * SUBREGION_SIZE; + EXPECT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, addr, free_size, 1), + ALLOCATION_RESULT_BAD_ARGUMENT); +} + +TEST_F(AllocatorTest, FreeHbm) { + uint64_t size = 2 * SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM, &size, 3, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + ASSERT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_HBM, addr, size, 1), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(map->hbm_regions[3].client_id[0], 0u); + EXPECT_EQ(map->hbm_regions[3].client_id[1], 0u); +} + +// --- Multi-client isolation --- + +TEST_F(AllocatorTest, MultiClientIsolation) { + uint64_t size = SUBREGION_SIZE; + uint64_t addr1, addr2; + + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 100, &addr1), + ALLOCATION_RESULT_SUCCESS); + size = SUBREGION_SIZE; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 200, &addr2), + ALLOCATION_RESULT_SUCCESS); + + EXPECT_EQ(map->ddr_regions[0].client_id[0], 100u); + EXPECT_EQ(map->ddr_regions[0].client_id[1], 200u); + + ASSERT_EQ(device_memory_map_free(map, ALLOCATION_TYPE_DDR, addr1, SUBREGION_SIZE, 100), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(map->ddr_regions[0].client_id[0], 0u); + EXPECT_EQ(map->ddr_regions[0].client_id[1], 200u); +} + +// --- Address math verification --- + +TEST_F(AllocatorTest, DdrAddressMath) { + for (int r = 0; r < 3; r++) { + uint64_t size = SUBREGIONS_PER_REGION * SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_DDR, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, DDR_START_ADDRESS + (uint64_t)r * REGION_SIZE); + } +} + +TEST_F(AllocatorTest, HbmVnocAddressMath) { + uint64_t size = 2 * SUBREGION_SIZE; + uint64_t addr; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM_VNOC, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, HBM_START_ADDRESS); + + size = 2 * SUBREGION_SIZE; + ASSERT_EQ(device_memory_map_allocate(map, ALLOCATION_TYPE_HBM_VNOC, &size, 0, 1, &addr), + ALLOCATION_RESULT_SUCCESS); + EXPECT_EQ(addr, HBM_START_ADDRESS + 2 * SUBREGION_SIZE); +} diff --git a/vrt/vrtd/tests/array_test.cpp b/vrt/vrtd/tests/array_test.cpp new file mode 100644 index 00000000..8984f57b --- /dev/null +++ b/vrt/vrtd/tests/array_test.cpp @@ -0,0 +1,222 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +extern "C" { +#include "array.h" +} + +// --- Value array (int_array) --- + +TEST(IntArrayTest, InitIsEmpty) { + struct int_array arr = int_array_init(); + EXPECT_EQ(arr.len, 0u); + EXPECT_EQ(arr.cap, 0u); + EXPECT_EQ(arr.d, nullptr); + int_array_free(&arr); +} + +TEST(IntArrayTest, PushAndAccess) { + struct int_array arr = int_array_init(); + ASSERT_EQ(int_array_push(&arr, 42), 0); + ASSERT_EQ(int_array_push(&arr, 99), 0); + EXPECT_EQ(arr.len, 2u); + EXPECT_EQ(arr.d[0], 42); + EXPECT_EQ(arr.d[1], 99); + int_array_free(&arr); +} + +TEST(IntArrayTest, CapacityGrowsPowerOfTwo) { + struct int_array arr = int_array_init(); + for (int i = 0; i < 5; i++) { + ASSERT_EQ(int_array_push(&arr, i), 0); + } + EXPECT_EQ(arr.len, 5u); + EXPECT_GE(arr.cap, 5u); + EXPECT_EQ(arr.cap & (arr.cap - 1), 0u); + int_array_free(&arr); +} + +TEST(IntArrayTest, PopLifo) { + struct int_array arr = int_array_init(); + ASSERT_EQ(int_array_push(&arr, 10), 0); + ASSERT_EQ(int_array_push(&arr, 20), 0); + ASSERT_EQ(int_array_push(&arr, 30), 0); + + int val; + EXPECT_EQ(int_array_pop(&arr, &val), 0); + EXPECT_EQ(val, 30); + EXPECT_EQ(int_array_pop(&arr, &val), 0); + EXPECT_EQ(val, 20); + EXPECT_EQ(int_array_pop(&arr, &val), 0); + EXPECT_EQ(val, 10); + int_array_free(&arr); +} + +TEST(IntArrayTest, PopEmptyReturnsError) { + struct int_array arr = int_array_init(); + int val; + EXPECT_EQ(int_array_pop(&arr, &val), -1); + int_array_free(&arr); +} + +TEST(IntArrayTest, PopSafeEmptyIsNoop) { + struct int_array arr = int_array_init(); + int val = -1; + int_array_pop_safe(&arr, &val); + EXPECT_EQ(val, -1); + int_array_free(&arr); +} + +TEST(IntArrayTest, RmByValue) { + struct int_array arr = int_array_init(); + ASSERT_EQ(int_array_push(&arr, 1), 0); + ASSERT_EQ(int_array_push(&arr, 2), 0); + ASSERT_EQ(int_array_push(&arr, 3), 0); + ASSERT_EQ(int_array_push(&arr, 2), 0); + + int_array_rm_by_value(&arr, 2); + EXPECT_EQ(arr.len, 2u); + EXPECT_EQ(arr.d[0], 1); + EXPECT_EQ(arr.d[1], 3); + int_array_free(&arr); +} + +TEST(IntArrayTest, ShrinkToFit) { + struct int_array arr = int_array_init(); + for (int i = 0; i < 16; i++) { + ASSERT_EQ(int_array_push(&arr, i), 0); + } + // pop_safe doesn't call resize, so capacity stays at 16 + int val; + for (int i = 0; i < 8; i++) { + int_array_pop_safe(&arr, &val); + } + EXPECT_EQ(arr.len, 8u); + EXPECT_EQ(arr.cap, 16u); + + ASSERT_EQ(int_array_shrink_to_fit(&arr), 0); + EXPECT_EQ(arr.cap, 8u); + int_array_free(&arr); +} + +TEST(IntArrayTest, Zero) { + struct int_array arr = int_array_init(); + ASSERT_EQ(int_array_push(&arr, 42), 0); + ASSERT_EQ(int_array_push(&arr, 99), 0); + + int_array_zero(&arr); + EXPECT_EQ(arr.d[0], 0); + EXPECT_EQ(arr.d[1], 0); + EXPECT_EQ(arr.len, 2u); + int_array_free(&arr); +} + +TEST(IntArrayTest, Resize) { + struct int_array arr = int_array_init(); + ASSERT_EQ(int_array_resize(&arr, 10), 0); + EXPECT_GE(arr.cap, 10u); + int_array_free(&arr); +} + +TEST(IntArrayTest, FreeResetsState) { + struct int_array arr = int_array_init(); + ASSERT_EQ(int_array_push(&arr, 1), 0); + int_array_free(&arr); + EXPECT_EQ(arr.len, 0u); + EXPECT_EQ(arr.cap, 0u); + EXPECT_EQ(arr.d, nullptr); +} + +// --- Owning pointer array (str_array) --- + +static int g_cleanup_count = 0; + +struct dummy { + int value; +}; + +static void cleanup_dummy(struct dummy *d) { + g_cleanup_count++; + free(d); +} + +DECLARE_OWNING_PTR_ARRAY(dummy_ptr_array, struct dummy *, cleanup_dummy) + +TEST(OwningArrayTest, PushMoveNullifiesSource) { + struct dummy_ptr_array arr = dummy_ptr_array_init(); + auto *d = static_cast(calloc(1, sizeof(struct dummy))); + d->value = 42; + + struct dummy *src = d; + ASSERT_EQ(dummy_ptr_array_push_move(&arr, &src), 0); + EXPECT_EQ(src, nullptr); + EXPECT_EQ(arr.d[0]->value, 42); + dummy_ptr_array_free(&arr); +} + +TEST(OwningArrayTest, FreeCallsCleanup) { + struct dummy_ptr_array arr = dummy_ptr_array_init(); + for (int i = 0; i < 3; i++) { + auto *d = static_cast(calloc(1, sizeof(struct dummy))); + d->value = i; + struct dummy *src = d; + ASSERT_EQ(dummy_ptr_array_push_move(&arr, &src), 0); + } + + g_cleanup_count = 0; + dummy_ptr_array_free(&arr); + EXPECT_EQ(g_cleanup_count, 3); +} + +TEST(OwningArrayTest, RmByReferenceCallsCleanup) { + struct dummy_ptr_array arr = dummy_ptr_array_init(); + auto *d1 = static_cast(calloc(1, sizeof(struct dummy))); + auto *d2 = static_cast(calloc(1, sizeof(struct dummy))); + d1->value = 1; + d2->value = 2; + + struct dummy *src = d1; + ASSERT_EQ(dummy_ptr_array_push_move(&arr, &src), 0); + src = d2; + ASSERT_EQ(dummy_ptr_array_push_move(&arr, &src), 0); + + g_cleanup_count = 0; + dummy_ptr_array_rm_by_reference(&arr, d1); + EXPECT_EQ(g_cleanup_count, 1); + EXPECT_EQ(arr.len, 1u); + EXPECT_EQ(arr.d[0]->value, 2); + dummy_ptr_array_free(&arr); +} + +TEST(StrArrayTest, PushAndFree) { + struct str_array arr = str_array_init(); + char *s1 = strdup("hello"); + char *s2 = strdup("world"); + ASSERT_EQ(str_array_push_move(&arr, &s1), 0); + ASSERT_EQ(str_array_push_move(&arr, &s2), 0); + EXPECT_EQ(s1, nullptr); + EXPECT_EQ(s2, nullptr); + EXPECT_EQ(arr.len, 2u); + EXPECT_STREQ(arr.d[0], "hello"); + EXPECT_STREQ(arr.d[1], "world"); + str_array_free(&arr); +} diff --git a/vrt/vrtd/tests/auth_test.cpp b/vrt/vrtd/tests/auth_test.cpp new file mode 100644 index 00000000..c3fd3cc3 --- /dev/null +++ b/vrt/vrtd/tests/auth_test.cpp @@ -0,0 +1,379 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include + +extern "C" { +#include "auth.h" +#include "config.h" +#include "device.h" +#include "state.h" +} + +static struct device_policy *make_dp(const char *bdf, bool bar, bool qdma, bool buffer, + bool design_write, bool clock, bool pcie_hotplug, + bool raw_mem) { + auto *dp = static_cast(calloc(1, sizeof(struct device_policy))); + dp->bdf = strdup(bdf); + dp->bar = bar; + dp->qdma = qdma; + dp->buffer = buffer; + dp->design_write = design_write; + dp->clock = clock; + dp->pcie_hotplug = pcie_hotplug; + dp->raw_mem_access = raw_mem; + return dp; +} + +class AuthTest : public ::testing::Test { + protected: + struct config cfg{}; + struct device dev{}; + struct vrtd state{}; + struct client cl{}; + struct user_config default_user{}; + struct role *fullaccess_role = nullptr; + struct role *info_role = nullptr; + + void SetUp() override { + memset(&cfg, 0, sizeof(cfg)); + memset(&dev, 0, sizeof(dev)); + memset(&state, 0, sizeof(state)); + memset(&cl, 0, sizeof(cl)); + memset(&default_user, 0, sizeof(default_user)); + + strncpy(dev.pci_info.bdf, "0000:03:00", sizeof(dev.pci_info.bdf) - 1); + + ASSERT_EQ(role_merge_new(&fullaccess_role, "fullaccess"), 0); + fullaccess_role->query = true; + struct device_policy *dp = make_dp("any", true, true, true, true, true, true, true); + struct device_policy *dp_ptr = dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&fullaccess_role->device_policies, &dp_ptr), 0); + + ASSERT_EQ(role_merge_new(&info_role, "info"), 0); + info_role->query = true; + + struct role *fa_ref = fullaccess_role; + ASSERT_EQ(role_ptr_array_push_move(&cfg.roles, &fa_ref), 0); + struct role *info_ref = info_role; + ASSERT_EQ(role_ptr_array_push_move(&cfg.roles, &info_ref), 0); + + default_user.name = strdup("*"); + cfg.default_user = &default_user; + + struct device *dev_ptr = &dev; + ASSERT_EQ(device_ptr_array_push(&state.devices, dev_ptr), 0); + + state.config = &cfg; + + cl.uid = getuid(); + cl.state = &state; + cl.role = nullptr; + cl.fd = -1; + } + + void TearDown() override { + if (cl.role != nullptr) { + cleanup_role(cl.role); + cl.role = nullptr; + } + gid_t_array_free(&cl.gids); + + // dev is stack-allocated, so we must not call the owning + // device_ptr_array_free (which would free(dev)). + free(state.devices.d); + state.devices.d = nullptr; + state.devices.len = 0; + state.devices.cap = 0; + + role_ptr_array_free(&cfg.roles); + + str_array_free(&default_user.role_names); + role_ref_array_free(&default_user.roles); + free(default_user.name); + + user_config_ptr_array_free(&cfg.users); + group_config_ptr_array_free(&cfg.groups); + } + + void assignRole(struct role *role_template) { + struct role *merged = nullptr; + ASSERT_EQ(role_merge_new(&merged, "merged"), 0); + ASSERT_EQ(role_merge_add_role(merged, role_template), 0); + cl.role = merged; + } +}; + +// --- Query-only operations --- + +TEST_F(AuthTest, GetNumDevicesAllowedWithQuery) { + assignRole(info_role); + struct vrtd_req_get_num_devices req{}; + EXPECT_EQ(auth_request_get_num_devices(&cl, &req), 1); +} + +TEST_F(AuthTest, GetNumDevicesDeniedWithoutQuery) { + struct role *empty = nullptr; + ASSERT_EQ(role_merge_new(&empty, "empty"), 0); + cl.role = empty; + struct vrtd_req_get_num_devices req{}; + EXPECT_EQ(auth_request_get_num_devices(&cl, &req), 0); +} + +TEST_F(AuthTest, GetDeviceInfoAllowed) { + assignRole(info_role); + struct vrtd_req_get_device_info req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_device_info(&cl, &req), 1); +} + +TEST_F(AuthTest, GetDeviceByBdfAllowed) { + assignRole(info_role); + struct vrtd_req_get_device_by_bdf req{}; + EXPECT_EQ(auth_request_get_device_by_bdf(&cl, &req), 1); +} + +TEST_F(AuthTest, GetBarInfoAllowed) { + assignRole(info_role); + struct vrtd_req_get_bar_info req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_bar_info(&cl, &req), 1); +} + +TEST_F(AuthTest, QdmaGetInfoAllowed) { + assignRole(info_role); + struct vrtd_req_qdma_get_info req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_qdma_get_info(&cl, &req), 1); +} + +TEST_F(AuthTest, GetSensorInfoAllowed) { + assignRole(info_role); + struct vrtd_req_get_sensor_info req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_sensor_info(&cl, &req), 1); +} + +// --- Device-access operations: fullaccess role --- + +TEST_F(AuthTest, GetBarFdAllowedFullaccess) { + assignRole(fullaccess_role); + struct vrtd_req_get_bar_fd req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_bar_fd(&cl, &req), 1); +} + +TEST_F(AuthTest, QdmaQpairAddAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_qdma_qpair_add req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_qdma_qpair_add(&cl, &req), 1); +} + +TEST_F(AuthTest, BufferOpenAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_buffer_open req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_buffer_open(&cl, &req), 1); +} + +TEST_F(AuthTest, BufferCloseAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_buffer_close req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_buffer_close(&cl, &req), 1); +} + +TEST_F(AuthTest, DesignWriteAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_design_write req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_design_write(&cl, &req), 1); +} + +TEST_F(AuthTest, ClockOpAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_clock_op req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_clock_op(&cl, &req), 1); +} + +TEST_F(AuthTest, HotplugOpAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_device_hotplug_op req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_device_hotplug_op(&cl, &req), 1); +} + +TEST_F(AuthTest, BufferOpenRawAllowed) { + assignRole(fullaccess_role); + struct vrtd_req_buffer_open_raw req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_buffer_open_raw(&cl, &req), 1); +} + +// --- Device-access denied with info-only role --- + +TEST_F(AuthTest, GetBarFdDeniedInfoOnly) { + assignRole(info_role); + struct vrtd_req_get_bar_fd req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_bar_fd(&cl, &req), 0); +} + +TEST_F(AuthTest, BufferOpenDeniedInfoOnly) { + assignRole(info_role); + struct vrtd_req_buffer_open req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_buffer_open(&cl, &req), 0); +} + +TEST_F(AuthTest, DesignWriteDeniedInfoOnly) { + assignRole(info_role); + struct vrtd_req_design_write req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_design_write(&cl, &req), 0); +} + +TEST_F(AuthTest, ClockOpDeniedInfoOnly) { + assignRole(info_role); + struct vrtd_req_clock_op req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_clock_op(&cl, &req), 0); +} + +TEST_F(AuthTest, HotplugOpDeniedInfoOnly) { + assignRole(info_role); + struct vrtd_req_device_hotplug_op req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_device_hotplug_op(&cl, &req), 0); +} + +// --- Exact BDF match vs "any" wildcard --- + +TEST_F(AuthTest, ExactBdfMatchTakesPriority) { + struct role *role = nullptr; + ASSERT_EQ(role_merge_new(&role, "mixed"), 0); + role->query = true; + + struct device_policy *any_dp = make_dp("any", false, false, false, false, false, false, false); + struct device_policy *any_ptr = any_dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&role->device_policies, &any_ptr), 0); + + struct device_policy *exact_dp = make_dp("0000:03:00", true, true, true, true, true, true, true); + struct device_policy *exact_ptr = exact_dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&role->device_policies, &exact_ptr), 0); + + cl.role = role; + + struct vrtd_req_get_bar_fd req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_bar_fd(&cl, &req), 1); +} + +TEST_F(AuthTest, WildcardFallbackWhenNoExactMatch) { + struct role *role = nullptr; + ASSERT_EQ(role_merge_new(&role, "wildcard_only"), 0); + role->query = true; + + struct device_policy *any_dp = make_dp("any", true, false, false, false, false, false, false); + struct device_policy *any_ptr = any_dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&role->device_policies, &any_ptr), 0); + + cl.role = role; + + struct vrtd_req_get_bar_fd req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_bar_fd(&cl, &req), 1); +} + +TEST_F(AuthTest, NoPolicyMatchDenied) { + struct role *role = nullptr; + ASSERT_EQ(role_merge_new(&role, "no_devices"), 0); + role->query = true; + + struct device_policy *other_dp = make_dp("0000:99:00", true, true, true, true, true, true, true); + struct device_policy *other_ptr = other_dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&role->device_policies, &other_ptr), 0); + + cl.role = role; + + struct vrtd_req_get_bar_fd req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_get_bar_fd(&cl, &req), 0); +} + +// --- Invalid device index --- + +TEST_F(AuthTest, DeviceIndexOutOfRange) { + assignRole(fullaccess_role); + struct vrtd_req_get_bar_fd req{}; + req.dev_number = 999; + EXPECT_EQ(auth_request_get_bar_fd(&cl, &req), 0); +} + +// --- ensure_role: lazy role merging via default_user --- + +TEST_F(AuthTest, EnsureRoleMergesDefaultUser) { + ASSERT_EQ(role_ref_array_push(&default_user.roles, fullaccess_role), 0); + + struct vrtd_req_get_num_devices req{}; + EXPECT_EQ(auth_request_get_num_devices(&cl, &req), 1); + EXPECT_NE(cl.role, nullptr); + EXPECT_TRUE(cl.role->query); +} + +TEST_F(AuthTest, EnsureRoleMergesUidUser) { + auto *uid_user = static_cast(calloc(1, sizeof(struct user_config))); + uid_user->name = strdup("testuser"); + uid_user->uid = getuid(); + ASSERT_EQ(role_ref_array_push(&uid_user->roles, fullaccess_role), 0); + + struct user_config *uid_ptr = uid_user; + ASSERT_EQ(user_config_ptr_array_push_move(&cfg.users, &uid_ptr), 0); + + struct vrtd_req_buffer_open req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_buffer_open(&cl, &req), 1); +} + +TEST_F(AuthTest, EnsureRoleMergesGidGroup) { + gid_t gid = getgid(); + ASSERT_EQ(gid_t_array_push(&cl.gids, gid), 0); + + auto *grp = static_cast(calloc(1, sizeof(struct group_config))); + grp->name = strdup("testgroup"); + grp->gid = gid; + ASSERT_EQ(role_ref_array_push(&grp->roles, fullaccess_role), 0); + + struct group_config *grp_ptr = grp; + ASSERT_EQ(group_config_ptr_array_push_move(&cfg.groups, &grp_ptr), 0); + + struct vrtd_req_design_write req{}; + req.dev_number = 0; + EXPECT_EQ(auth_request_design_write(&cl, &req), 1); +} + +TEST_F(AuthTest, EnsureRoleEmptyDefaultDeniesAll) { + struct vrtd_req_get_num_devices req{}; + EXPECT_EQ(auth_request_get_num_devices(&cl, &req), 0); +} diff --git a/vrt/vrtd/tests/buffer_test.cpp b/vrt/vrtd/tests/buffer_test.cpp new file mode 100644 index 00000000..078f5819 --- /dev/null +++ b/vrt/vrtd/tests/buffer_test.cpp @@ -0,0 +1,229 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include +#include +#include +#include + +extern "C" { +#include +#include "allocator.h" +#include "buffer.h" +} + +static constexpr const char *REAL_QDMA_PATH = "/dev/slash_qdma_ctl0"; +static constexpr uint64_t XFER_SIZE = 4096; +static constexpr uint64_t CLIENT_ID = 42; + +// ─── Null / argument validation (no hardware needed, always run) ────────────── + +TEST(BufferNullTest, NullQdma) { + struct device_memory_map *map = device_memory_map_create(); + ASSERT_NE(map, nullptr); + struct buffer *buf = buffer_create(nullptr, map, ALLOCATION_TYPE_DDR, + VRTD_ALLOC_DIR_HOST_TO_DEVICE, + XFER_SIZE, 0, CLIENT_ID, nullptr); + EXPECT_EQ(buf, nullptr); + device_memory_map_cleanup(map); +} + +TEST(BufferNullTest, NullMap) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct buffer *buf = buffer_create(qdma, nullptr, ALLOCATION_TYPE_DDR, + VRTD_ALLOC_DIR_HOST_TO_DEVICE, + XFER_SIZE, 0, CLIENT_ID, nullptr); + EXPECT_EQ(buf, nullptr); + slash_qdma_close(qdma); +} + +TEST(BufferNullTest, ZeroSize) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct device_memory_map *map = device_memory_map_create(); + ASSERT_NE(map, nullptr); + struct buffer *buf = buffer_create(qdma, map, ALLOCATION_TYPE_DDR, + VRTD_ALLOC_DIR_HOST_TO_DEVICE, + 0, 0, CLIENT_ID, nullptr); + EXPECT_EQ(buf, nullptr); + device_memory_map_cleanup(map); + slash_qdma_close(qdma); +} + +TEST(BufferNullTest, ZeroClientId) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct device_memory_map *map = device_memory_map_create(); + ASSERT_NE(map, nullptr); + struct buffer *buf = buffer_create(qdma, map, ALLOCATION_TYPE_DDR, + VRTD_ALLOC_DIR_HOST_TO_DEVICE, + XFER_SIZE, 0, 0, nullptr); + EXPECT_EQ(buf, nullptr); + device_memory_map_cleanup(map); + slash_qdma_close(qdma); +} + +TEST(BufferNullTest, InvalidDirection) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct device_memory_map *map = device_memory_map_create(); + ASSERT_NE(map, nullptr); + struct buffer *buf = buffer_create(qdma, map, ALLOCATION_TYPE_DDR, + static_cast(99), + XFER_SIZE, 0, CLIENT_ID, nullptr); + EXPECT_EQ(buf, nullptr); + device_memory_map_cleanup(map); + slash_qdma_close(qdma); +} + +TEST(BufferNullTest, CleanupNull) { + cleanup_buffer(nullptr); +} + +TEST(BufferNullTest, RawNullQdma) { + struct buffer *buf = buffer_create_raw(nullptr, DDR_START_ADDRESS, XFER_SIZE, + VRTD_ALLOC_DIR_HOST_TO_DEVICE); + EXPECT_EQ(buf, nullptr); + EXPECT_EQ(errno, EINVAL); +} + +TEST(BufferNullTest, RawZeroSize) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct buffer *buf = buffer_create_raw(qdma, DDR_START_ADDRESS, 0, + VRTD_ALLOC_DIR_HOST_TO_DEVICE); + EXPECT_EQ(buf, nullptr); + EXPECT_EQ(errno, EINVAL); + slash_qdma_close(qdma); +} + +// ─── Parameterized fixture (mock + real hardware) ──────────────────────────── + +class BufferTest : public ::testing::TestWithParam { + protected: + bool mock; + struct slash_qdma *qdma_ = nullptr; + struct device_memory_map *map_ = nullptr; + + void SetUp() override { + mock = GetParam(); + if (mock) { + qdma_ = slash_qdma_open("@mock"); + ASSERT_NE(qdma_, nullptr); + } else { + qdma_ = slash_qdma_open(REAL_QDMA_PATH); + if (qdma_ == nullptr) { + GTEST_SKIP() << REAL_QDMA_PATH << " not available (errno=" << errno << ")"; + } + } + map_ = device_memory_map_create(); + ASSERT_NE(map_, nullptr); + } + + void TearDown() override { + device_memory_map_cleanup(map_); + map_ = nullptr; + if (qdma_) { + slash_qdma_close(qdma_); + qdma_ = nullptr; + } + } +}; + +TEST_P(BufferTest, LifecycleBidirectional) { + struct buffer *buf = buffer_create(qdma_, map_, ALLOCATION_TYPE_DDR, + VRTD_ALLOC_DIR_BIDIRECTIONAL, + XFER_SIZE, 0, CLIENT_ID, nullptr); + ASSERT_NE(buf, nullptr); + EXPECT_GE(buf->fd, 0); + + uint8_t src[XFER_SIZE]; + for (size_t i = 0; i < XFER_SIZE; ++i) + src[i] = static_cast(i & 0xFF); + + ssize_t written = pwrite(buf->fd, src, XFER_SIZE, static_cast(buf->addr)); + EXPECT_EQ(written, static_cast(XFER_SIZE)); + + uint8_t dst[XFER_SIZE]{}; + ssize_t read_bytes = pread(buf->fd, dst, XFER_SIZE, static_cast(buf->addr)); + EXPECT_EQ(read_bytes, static_cast(XFER_SIZE)); + EXPECT_EQ(std::memcmp(src, dst, XFER_SIZE), 0); + + cleanup_buffer(buf); +} + +TEST_P(BufferTest, RawCreateAndIO) { + struct buffer *buf = buffer_create_raw(qdma_, DDR_START_ADDRESS, XFER_SIZE, + VRTD_ALLOC_DIR_BIDIRECTIONAL); + ASSERT_NE(buf, nullptr); + EXPECT_GE(buf->fd, 0); + EXPECT_EQ(buf->addr, DDR_START_ADDRESS); + EXPECT_FALSE(buf->allocation_valid); + + uint8_t src[XFER_SIZE]; + std::memset(src, 0xCD, sizeof(src)); + ssize_t written = pwrite(buf->fd, src, XFER_SIZE, static_cast(DDR_START_ADDRESS)); + EXPECT_EQ(written, static_cast(XFER_SIZE)); + + uint8_t dst[XFER_SIZE]{}; + ssize_t n = pread(buf->fd, dst, XFER_SIZE, static_cast(DDR_START_ADDRESS)); + EXPECT_EQ(n, static_cast(XFER_SIZE)); + EXPECT_EQ(std::memcmp(src, dst, XFER_SIZE), 0); + + cleanup_buffer(buf); +} + +TEST_P(BufferTest, QueueExhaustion) { + /* The mock QDMA supports 64 queues (QDMA_MOCK_MAX_QUEUES). + * Real hardware queue limits vary and exhaustion may not be reachable, + * so this test is restricted to mock mode. */ + if (!mock) { + GTEST_SKIP() << "Queue exhaustion test is mock-only"; + } + + static constexpr int MAX_QUEUES = 64; + std::vector bufs; + bufs.reserve(MAX_QUEUES); + + for (int i = 0; i < MAX_QUEUES; ++i) { + struct buffer *buf = buffer_create_raw(qdma_, DDR_START_ADDRESS + i * XFER_SIZE, + XFER_SIZE, VRTD_ALLOC_DIR_HOST_TO_DEVICE); + ASSERT_NE(buf, nullptr) << "Expected success for queue " << i; + bufs.push_back(buf); + } + + /* 65th allocation must fail */ + struct buffer *overflow = buffer_create_raw(qdma_, DDR_START_ADDRESS, + XFER_SIZE, VRTD_ALLOC_DIR_HOST_TO_DEVICE); + EXPECT_EQ(overflow, nullptr); + EXPECT_EQ(errno, ENOSPC); + + for (struct buffer *b : bufs) + cleanup_buffer(b); +} + +INSTANTIATE_TEST_SUITE_P(BufferTest, BufferTest, testing::Values(true, false), + [](const testing::TestParamInfo &info) { + return info.param ? "Mock" : "RealHardware"; + }); diff --git a/vrt/vrtd/tests/config_test.cpp b/vrt/vrtd/tests/config_test.cpp new file mode 100644 index 00000000..bb4416b5 --- /dev/null +++ b/vrt/vrtd/tests/config_test.cpp @@ -0,0 +1,223 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include + +extern "C" { +#include "config.h" +} + +static struct device_policy *make_device_policy(const char *bdf, bool bar, bool qdma, bool buffer, + bool design_write, bool clock, bool pcie_hotplug, + bool raw_mem_access) { + auto *dp = static_cast(calloc(1, sizeof(struct device_policy))); + dp->bdf = strdup(bdf); + dp->bar = bar; + dp->qdma = qdma; + dp->buffer = buffer; + dp->design_write = design_write; + dp->clock = clock; + dp->pcie_hotplug = pcie_hotplug; + dp->raw_mem_access = raw_mem_access; + return dp; +} + +// --- role_merge_new --- + +TEST(RoleMergeTest, NewCreatesEmptyRole) { + struct role *r = nullptr; + ASSERT_EQ(role_merge_new(&r, "test_role"), 0); + ASSERT_NE(r, nullptr); + EXPECT_STREQ(r->name, "test_role"); + EXPECT_FALSE(r->query); + EXPECT_EQ(r->device_policies.len, 0u); + cleanup_role(r); +} + +// --- role_merge_add_role --- + +TEST(RoleMergeTest, MergeQueryFlag) { + struct role *dst = nullptr; + struct role *src = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + ASSERT_EQ(role_merge_new(&src, "src"), 0); + + EXPECT_FALSE(dst->query); + src->query = true; + + ASSERT_EQ(role_merge_add_role(dst, src), 0); + EXPECT_TRUE(dst->query); + + cleanup_role(src); + cleanup_role(dst); +} + +TEST(RoleMergeTest, MergeQueryOrSemantics) { + struct role *dst = nullptr; + struct role *src = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + ASSERT_EQ(role_merge_new(&src, "src"), 0); + + dst->query = true; + src->query = false; + + ASSERT_EQ(role_merge_add_role(dst, src), 0); + EXPECT_TRUE(dst->query); + + cleanup_role(src); + cleanup_role(dst); +} + +TEST(RoleMergeTest, MergeDevicePolicies) { + struct role *dst = nullptr; + struct role *src = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + ASSERT_EQ(role_merge_new(&src, "src"), 0); + + struct device_policy *dp = make_device_policy("0000:03:00", true, false, true, false, false, false, false); + struct device_policy *src_ptr = dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&src->device_policies, &src_ptr), 0); + + ASSERT_EQ(role_merge_add_role(dst, src), 0); + + ASSERT_EQ(dst->device_policies.len, 1u); + EXPECT_STREQ(dst->device_policies.d[0]->bdf, "0000:03:00"); + EXPECT_TRUE(dst->device_policies.d[0]->bar); + EXPECT_FALSE(dst->device_policies.d[0]->qdma); + EXPECT_TRUE(dst->device_policies.d[0]->buffer); + + cleanup_role(src); + cleanup_role(dst); +} + +TEST(RoleMergeTest, MergeDevicePoliciesOrPerField) { + struct role *dst = nullptr; + struct role *src = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + ASSERT_EQ(role_merge_new(&src, "src"), 0); + + struct device_policy *dp1 = make_device_policy("0000:03:00", true, false, false, false, false, false, false); + struct device_policy *ptr1 = dp1; + ASSERT_EQ(device_policy_ptr_array_push_move(&dst->device_policies, &ptr1), 0); + + struct device_policy *dp2 = make_device_policy("0000:03:00", false, true, false, false, true, false, false); + struct device_policy *ptr2 = dp2; + ASSERT_EQ(device_policy_ptr_array_push_move(&src->device_policies, &ptr2), 0); + + ASSERT_EQ(role_merge_add_role(dst, src), 0); + + ASSERT_EQ(dst->device_policies.len, 1u); + EXPECT_TRUE(dst->device_policies.d[0]->bar); + EXPECT_TRUE(dst->device_policies.d[0]->qdma); + EXPECT_TRUE(dst->device_policies.d[0]->clock); + + cleanup_role(src); + cleanup_role(dst); +} + +TEST(RoleMergeTest, MergeDevicePoliciesDifferentBdf) { + struct role *dst = nullptr; + struct role *src = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + ASSERT_EQ(role_merge_new(&src, "src"), 0); + + struct device_policy *dp1 = make_device_policy("0000:03:00", true, false, false, false, false, false, false); + struct device_policy *ptr1 = dp1; + ASSERT_EQ(device_policy_ptr_array_push_move(&dst->device_policies, &ptr1), 0); + + struct device_policy *dp2 = make_device_policy("0000:04:00", false, true, false, false, false, false, false); + struct device_policy *ptr2 = dp2; + ASSERT_EQ(device_policy_ptr_array_push_move(&src->device_policies, &ptr2), 0); + + ASSERT_EQ(role_merge_add_role(dst, src), 0); + + ASSERT_EQ(dst->device_policies.len, 2u); + + cleanup_role(src); + cleanup_role(dst); +} + +TEST(RoleMergeTest, MergeWildcardPolicy) { + struct role *dst = nullptr; + struct role *src = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + ASSERT_EQ(role_merge_new(&src, "src"), 0); + + struct device_policy *dp = make_device_policy("any", true, true, true, true, true, true, true); + struct device_policy *ptr = dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&src->device_policies, &ptr), 0); + + ASSERT_EQ(role_merge_add_role(dst, src), 0); + + ASSERT_EQ(dst->device_policies.len, 1u); + EXPECT_STREQ(dst->device_policies.d[0]->bdf, "any"); + EXPECT_TRUE(dst->device_policies.d[0]->bar); + EXPECT_TRUE(dst->device_policies.d[0]->raw_mem_access); + + cleanup_role(src); + cleanup_role(dst); +} + +// --- role_merge_add_array --- + +TEST(RoleMergeTest, MergeArray) { + struct role *dst = nullptr; + ASSERT_EQ(role_merge_new(&dst, "dst"), 0); + + struct role *r1 = nullptr; + struct role *r2 = nullptr; + ASSERT_EQ(role_merge_new(&r1, "r1"), 0); + ASSERT_EQ(role_merge_new(&r2, "r2"), 0); + + r1->query = true; + + struct device_policy *dp = make_device_policy("any", false, true, false, false, false, false, false); + struct device_policy *ptr = dp; + ASSERT_EQ(device_policy_ptr_array_push_move(&r2->device_policies, &ptr), 0); + + struct role_ref_array roles = role_ref_array_init(); + ASSERT_EQ(role_ref_array_push(&roles, r1), 0); + ASSERT_EQ(role_ref_array_push(&roles, r2), 0); + + ASSERT_EQ(role_merge_add_array(dst, &roles), 0); + + EXPECT_TRUE(dst->query); + ASSERT_EQ(dst->device_policies.len, 1u); + EXPECT_TRUE(dst->device_policies.d[0]->qdma); + + role_ref_array_free(&roles); + cleanup_role(r2); + cleanup_role(r1); + cleanup_role(dst); +} + +// --- Cleanup functions --- + +TEST(ConfigCleanupTest, CleanupDevicePolicyZeroed) { + auto *dp = static_cast(calloc(1, sizeof(struct device_policy))); + cleanup_device_policy(dp); +} + +TEST(ConfigCleanupTest, CleanupRoleZeroed) { + auto *r = static_cast(calloc(1, sizeof(struct role))); + cleanup_role(r); +} diff --git a/vrt/vrtd/tests/design_writer_test.cpp b/vrt/vrtd/tests/design_writer_test.cpp new file mode 100644 index 00000000..b45c1cf7 --- /dev/null +++ b/vrt/vrtd/tests/design_writer_test.cpp @@ -0,0 +1,253 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * All tests here run against the mock QDMA only. Writing an arbitrary payload to + * a real FPGA via QDMA at the design-writer address risks corrupting the device + * bitstream, so real-hardware execution is intentionally excluded. + * + * The mock QDMA fd is a memfd_create() file, so lseek()+write() at the fixed + * QDMA bitstream address (0x102100000) works via sparse pages — no hardware needed. + */ + +#include + +#include +#include +#include +#include +#include + +extern "C" { +#include +#include "design_writer.h" +} + +// ─── Helper: create a small in-memory bitstream fd ─────────────────────────── + +static int make_bitstream_fd(uint8_t fill, size_t len) +{ + int fd = memfd_create("bitstream", MFD_CLOEXEC); + if (fd < 0) + return -1; + + std::vector buf(len, fill); + if (write(fd, buf.data(), len) != static_cast(len)) { + close(fd); + return -1; + } + + if (lseek(fd, 0, SEEK_SET) < 0) { + close(fd); + return -1; + } + + return fd; +} + +// ─── Null / argument validation (always run, no fixture needed) ─────────────── + +TEST(DesignWriterNullTest, CreateNullQdma) { + EXPECT_EQ(design_writer_create(nullptr), nullptr); +} + +TEST(DesignWriterNullTest, SubmitFdNullWriter) { + int fd = make_bitstream_fd(0xAB, 4096); + ASSERT_GE(fd, 0); + EXPECT_EQ(design_writer_submit_fd(nullptr, fd), -1); + close(fd); +} + +TEST(DesignWriterNullTest, SubmitAsyncNullWriter) { + int fd = make_bitstream_fd(0xAB, 4096); + ASSERT_GE(fd, 0); + EXPECT_EQ(design_writer_submit_fd_async(nullptr, fd), -1); + close(fd); +} + +TEST(DesignWriterNullTest, SubmitAsyncInvalidFd) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct design_writer *dw = design_writer_create(qdma); + ASSERT_NE(dw, nullptr); + + EXPECT_EQ(design_writer_submit_fd_async(dw, -1), -1); + + cleanup_design_writer(dw); + slash_qdma_close(qdma); +} + +TEST(DesignWriterNullTest, PollResultNullWriter) { + bool done = false; + int last_error = 0; + EXPECT_EQ(design_writer_poll_result(nullptr, &done, &last_error), -1); +} + +TEST(DesignWriterNullTest, PollResultNullDone) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct design_writer *dw = design_writer_create(qdma); + ASSERT_NE(dw, nullptr); + + int last_error = 0; + EXPECT_EQ(design_writer_poll_result(dw, nullptr, &last_error), -1); + + cleanup_design_writer(dw); + slash_qdma_close(qdma); +} + +TEST(DesignWriterNullTest, PollResultNullLastError) { + struct slash_qdma *qdma = slash_qdma_open("@mock"); + ASSERT_NE(qdma, nullptr); + struct design_writer *dw = design_writer_create(qdma); + ASSERT_NE(dw, nullptr); + + bool done = false; + EXPECT_EQ(design_writer_poll_result(dw, &done, nullptr), -1); + + cleanup_design_writer(dw); + slash_qdma_close(qdma); +} + +TEST(DesignWriterNullTest, IsBusyNullWriter) { + EXPECT_FALSE(design_writer_is_busy(nullptr)); +} + +// ─── Mock-only fixture ──────────────────────────────────────────────────────── + +class DesignWriterTest : public ::testing::Test { + protected: + struct slash_qdma *qdma_ = nullptr; + struct design_writer *writer_ = nullptr; + + void SetUp() override { + qdma_ = slash_qdma_open("@mock"); + ASSERT_NE(qdma_, nullptr); + writer_ = design_writer_create(qdma_); + ASSERT_NE(writer_, nullptr); + } + + void TearDown() override { + cleanup_design_writer(writer_); + writer_ = nullptr; + slash_qdma_close(qdma_); + qdma_ = nullptr; + } +}; + +TEST_F(DesignWriterTest, CreateDestroy) { + /* Fixture already creates and will destroy — just verify the handle is valid. */ + EXPECT_NE(writer_, nullptr); + EXPECT_TRUE(writer_->thread_started); + EXPECT_TRUE(writer_->qpair_created); + EXPECT_TRUE(writer_->qpair_started); + EXPECT_GE(writer_->fd, 0); +} + +TEST_F(DesignWriterTest, NotBusyInitially) { + EXPECT_FALSE(design_writer_is_busy(writer_)); +} + +TEST_F(DesignWriterTest, SyncTransfer) { + int fd = make_bitstream_fd(0xAB, 4096); + ASSERT_GE(fd, 0); + + /* design_writer_submit_fd closes fd on completion — do not close it ourselves. */ + EXPECT_EQ(design_writer_submit_fd(writer_, fd), 0); + EXPECT_FALSE(design_writer_is_busy(writer_)); +} + +TEST_F(DesignWriterTest, AsyncTransferPoll) { + int fd = make_bitstream_fd(0xCD, 8192); + ASSERT_GE(fd, 0); + + ASSERT_EQ(design_writer_submit_fd_async(writer_, fd), 0); + + bool done = false; + int last_error = 0; + /* Spin until the worker thread finishes (should be very fast on memfd). */ + for (int attempts = 0; attempts < 10000 && !done; ++attempts) { + ASSERT_EQ(design_writer_poll_result(writer_, &done, &last_error), 0); + if (!done) + usleep(1000); + } + + EXPECT_TRUE(done); + EXPECT_EQ(last_error, 0); +} + +TEST_F(DesignWriterTest, IsBusyTransitions) { + int fd = make_bitstream_fd(0xEF, 4096); + ASSERT_GE(fd, 0); + + EXPECT_FALSE(design_writer_is_busy(writer_)); + + ASSERT_EQ(design_writer_submit_fd_async(writer_, fd), 0); + + /* Spin until done, verifying is_busy is false afterwards. */ + bool done = false; + int last_error = 0; + for (int i = 0; i < 10000 && !done; ++i) { + ASSERT_EQ(design_writer_poll_result(writer_, &done, &last_error), 0); + if (!done) + usleep(1000); + } + ASSERT_TRUE(done); + EXPECT_FALSE(design_writer_is_busy(writer_)); +} + +TEST_F(DesignWriterTest, DoubleSubmitRejected) { + /* Submit a large payload so the first transfer is still running when we try again. */ + int fd1 = make_bitstream_fd(0x11, 64 * 1024); + ASSERT_GE(fd1, 0); + ASSERT_EQ(design_writer_submit_fd_async(writer_, fd1), 0); + + /* Second submit while busy must fail. */ + int fd2 = make_bitstream_fd(0x22, 4096); + ASSERT_GE(fd2, 0); + int ret = design_writer_submit_fd_async(writer_, fd2); + if (ret != -1) { + /* Transfer finished before we got here — acceptable, clean up fd2. */ + /* fd2 is now owned by the writer; wait for it to finish. */ + bool done = false; int err = 0; + for (int i = 0; i < 10000 && !done; ++i) { + design_writer_poll_result(writer_, &done, &err); + if (!done) usleep(1000); + } + } else { + /* Got the expected rejection — fd2 was not consumed, close it ourselves. */ + EXPECT_EQ(ret, -1); + close(fd2); + /* Let fd1's transfer finish before TearDown. */ + bool done = false; int err = 0; + for (int i = 0; i < 10000 && !done; ++i) { + design_writer_poll_result(writer_, &done, &err); + if (!done) usleep(1000); + } + } +} + +TEST_F(DesignWriterTest, CleanupWhileIdle) { + /* Immediate cleanup after create — TearDown does this, but we exercise it + * explicitly here with a freshly created writer to confirm no deadlock. */ + struct design_writer *dw = design_writer_create(qdma_); + ASSERT_NE(dw, nullptr); + cleanup_design_writer(dw); +} diff --git a/vrt/vrtd/tests/device_test.cpp b/vrt/vrtd/tests/device_test.cpp new file mode 100644 index 00000000..36518c10 --- /dev/null +++ b/vrt/vrtd/tests/device_test.cpp @@ -0,0 +1,184 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * Tests for device.c. + * + * device_open() and devices_contains_path() are static, so they are not + * directly callable from tests. The testable public surface is: + * + * cleanup_device() — exercised by constructing struct device + * instances manually with mock handles. + * devices_discover_and_open() — exercised only when /dev/slash_ctl* nodes + * are present; skipped otherwise. + * + * All cleanup tests use mock ctldev/qdma handles and are hardware-independent. + */ + +#include + +#include +#include + +extern "C" { +#include +#include +#include +#include "allocator.h" +#include "buffer.h" +#include "design_writer.h" +#include "device.h" +} + +// ─── Helpers ───────────────────────────────────────────────────────────────── + +/** Allocate a zeroed struct device and set a mock path string. */ +static struct device *alloc_mock_device(void) +{ + struct device *d = static_cast(calloc(1, sizeof(*d))); + if (d == nullptr) + return nullptr; + d->path = strdup("@mock"); + d->buffers = buffer_ptr_array_init(); + return d; +} + +// ─── cleanup_device() tests (always run, mock handles only) ────────────────── + +TEST(DeviceCleanupTest, CleanupNull) { + /* Must be a silent no-op. */ + cleanup_device(nullptr); +} + +TEST(DeviceCleanupTest, CleanupMinimal) { + /* A calloc'd device with only a path set — all subsystem pointers are NULL. */ + struct device *d = alloc_mock_device(); + ASSERT_NE(d, nullptr); + /* Ownership of d passes to cleanup_device (it calls free). */ + cleanup_device(d); +} + +TEST(DeviceCleanupTest, CleanupWithCtl) { + struct device *d = alloc_mock_device(); + ASSERT_NE(d, nullptr); + + d->ctl = slash_ctldev_open("@mock"); + ASSERT_NE(d->ctl, nullptr); + + cleanup_device(d); +} + +TEST(DeviceCleanupTest, CleanupWithCtlAndQdma) { + struct device *d = alloc_mock_device(); + ASSERT_NE(d, nullptr); + + d->ctl = slash_ctldev_open("@mock"); + ASSERT_NE(d->ctl, nullptr); + d->qdma = slash_qdma_open("@mock"); + ASSERT_NE(d->qdma, nullptr); + + cleanup_device(d); +} + +TEST(DeviceCleanupTest, CleanupWithDesignWriter) { + struct device *d = alloc_mock_device(); + ASSERT_NE(d, nullptr); + + d->ctl = slash_ctldev_open("@mock"); + ASSERT_NE(d->ctl, nullptr); + d->qdma = slash_qdma_open("@mock"); + ASSERT_NE(d->qdma, nullptr); + d->design_writer = design_writer_create(d->qdma); + ASSERT_NE(d->design_writer, nullptr); + + cleanup_device(d); +} + +TEST(DeviceCleanupTest, CleanupWithBars) { + struct device *d = alloc_mock_device(); + ASSERT_NE(d, nullptr); + + d->ctl = slash_ctldev_open("@mock"); + ASSERT_NE(d->ctl, nullptr); + d->qdma = slash_qdma_open("@mock"); + ASSERT_NE(d->qdma, nullptr); + + /* Mock ctldev provides a usable BAR 0 (64 MB, backed by a temp file). */ + d->bar_info[0] = slash_bar_info_read(d->ctl, 0); + ASSERT_NE(d->bar_info[0], nullptr); + EXPECT_TRUE(d->bar_info[0]->usable); + + d->bar_files[0] = slash_bar_file_open(d->ctl, 0, O_CLOEXEC); + ASSERT_NE(d->bar_files[0], nullptr); + + /* BARs 1-5 are not usable in the mock — populate bar_info only (no bar_file). */ + for (int i = 1; i < 6; ++i) { + d->bar_info[i] = slash_bar_info_read(d->ctl, i); + ASSERT_NE(d->bar_info[i], nullptr); + EXPECT_FALSE(d->bar_info[i]->usable); + } + + cleanup_device(d); +} + +TEST(DeviceCleanupTest, CleanupWithBuffers) { + struct device *d = alloc_mock_device(); + ASSERT_NE(d, nullptr); + + d->ctl = slash_ctldev_open("@mock"); + ASSERT_NE(d->ctl, nullptr); + d->qdma = slash_qdma_open("@mock"); + ASSERT_NE(d->qdma, nullptr); + + /* Allocate a raw buffer on the mock QDMA and hand ownership to d->buffers. */ + struct buffer *buf = buffer_create_raw(d->qdma, DDR_START_ADDRESS, 4096, + VRTD_ALLOC_DIR_HOST_TO_DEVICE); + ASSERT_NE(buf, nullptr); + + int ret = buffer_ptr_array_push_move(&d->buffers, &buf); + ASSERT_EQ(ret, 0); + EXPECT_EQ(buf, nullptr); /* ownership transferred */ + EXPECT_EQ(d->buffers.len, 1u); + + cleanup_device(d); +} + +// ─── devices_discover_and_open() — real hardware only ──────────────────────── + +TEST(DeviceDiscoveryTest, DiscoverAndOpen) { + struct device_ptr_array devices = device_ptr_array_init(); + int ret = devices_discover_and_open(&devices); + + if (devices.len == 0) { + device_ptr_array_free(&devices); + GTEST_SKIP() << "No /dev/slash_ctl* devices found — skipping hardware test"; + } + + EXPECT_EQ(ret, 0); + EXPECT_GT(devices.len, 0u); + + /* Each discovered device must have at least a control handle. */ + for (size_t i = 0; i < devices.len; ++i) { + EXPECT_NE(devices.d[i], nullptr); + EXPECT_NE(devices.d[i]->ctl, nullptr); + } + + device_ptr_array_free(&devices); +} diff --git a/vrt/vrtd/tests/hotplug_test.cpp b/vrt/vrtd/tests/hotplug_test.cpp new file mode 100644 index 00000000..0e2abd85 --- /dev/null +++ b/vrt/vrtd/tests/hotplug_test.cpp @@ -0,0 +1,141 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include + +extern "C" { +#include "hotplug.h" +} + +// --- pci_bdf_prefix --- + +TEST(PciBdfPrefixTest, StripsFunctionSuffix) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_prefix("0000:65:00.2", out), 0); + EXPECT_STREQ(out, "0000:65:00"); +} + +TEST(PciBdfPrefixTest, AlreadyBoardLevel) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_prefix("0000:65:00", out), 0); + EXPECT_STREQ(out, "0000:65:00"); +} + +TEST(PciBdfPrefixTest, NullBdf) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_prefix(nullptr, out), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(PciBdfPrefixTest, NullOutput) { + EXPECT_EQ(pci_bdf_prefix("0000:65:00.2", nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(PciBdfPrefixTest, EmptyString) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_prefix("", out), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(PciBdfPrefixTest, DotAtStart) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_prefix(".2", out), 0); + EXPECT_STREQ(out, ".2"); +} + +// --- pci_bdf_set_function --- + +TEST(PciBdfSetFunctionTest, ReplacesFunction) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function("0000:65:00.0", 2, out), 0); + EXPECT_STREQ(out, "0000:65:00.2"); +} + +TEST(PciBdfSetFunctionTest, BoardLevelInput) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function("0000:65:00", 3, out), 0); + EXPECT_STREQ(out, "0000:65:00.3"); +} + +TEST(PciBdfSetFunctionTest, FunctionZero) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function("0000:65:00.7", 0, out), 0); + EXPECT_STREQ(out, "0000:65:00.0"); +} + +TEST(PciBdfSetFunctionTest, FunctionSeven) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function("0000:65:00.0", 7, out), 0); + EXPECT_STREQ(out, "0000:65:00.7"); +} + +TEST(PciBdfSetFunctionTest, FunctionTooLarge) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function("0000:65:00.0", 8, out), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(PciBdfSetFunctionTest, NullBdf) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function(nullptr, 0, out), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(PciBdfSetFunctionTest, NullOutput) { + EXPECT_EQ(pci_bdf_set_function("0000:65:00.0", 0, nullptr), -1); + EXPECT_EQ(errno, EINVAL); +} + +TEST(PciBdfSetFunctionTest, EmptyString) { + char out[VRTD_PCI_BDF_LEN]; + EXPECT_EQ(pci_bdf_set_function("", 0, out), -1); + EXPECT_EQ(errno, EINVAL); +} + +// --- hotplug_errno_to_vrtd_ret --- + +TEST(HotplugErrnoTest, Einval) { + EXPECT_EQ(hotplug_errno_to_vrtd_ret(EINVAL), VRTD_RET_INVALID_ARGUMENT); +} + +TEST(HotplugErrnoTest, Enodev) { + EXPECT_EQ(hotplug_errno_to_vrtd_ret(ENODEV), VRTD_RET_NOEXIST); +} + +TEST(HotplugErrnoTest, Ebusy) { + EXPECT_EQ(hotplug_errno_to_vrtd_ret(EBUSY), VRTD_RET_BUSY); +} + +TEST(HotplugErrnoTest, Eperm) { + EXPECT_EQ(hotplug_errno_to_vrtd_ret(EPERM), VRTD_RET_AUTH_ERROR); +} + +TEST(HotplugErrnoTest, Eacces) { + EXPECT_EQ(hotplug_errno_to_vrtd_ret(EACCES), VRTD_RET_AUTH_ERROR); +} + +TEST(HotplugErrnoTest, UnknownErrno) { + EXPECT_EQ(hotplug_errno_to_vrtd_ret(ENOMEM), VRTD_RET_INTERNAL_ERROR); + EXPECT_EQ(hotplug_errno_to_vrtd_ret(EIO), VRTD_RET_INTERNAL_ERROR); +} diff --git a/vrt/vrtd/tests/test_helpers.hpp b/vrt/vrtd/tests/test_helpers.hpp new file mode 100644 index 00000000..a621583c --- /dev/null +++ b/vrt/vrtd/tests/test_helpers.hpp @@ -0,0 +1,82 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef VRTD_TEST_HELPERS_HPP +#define VRTD_TEST_HELPERS_HPP + +#include +#include +#include +#include +#include + +class ScopedEnv { + public: + explicit ScopedEnv(const char* name, std::optional value = std::nullopt) + : name_(name) { + const char* prev = std::getenv(name); + if (prev) { + oldValue_ = prev; + } + if (value) { + setenv(name, value->c_str(), 1); + } else { + unsetenv(name); + } + } + + ~ScopedEnv() { + if (oldValue_) { + setenv(name_.c_str(), oldValue_->c_str(), 1); + } else { + unsetenv(name_.c_str()); + } + } + + ScopedEnv(const ScopedEnv&) = delete; + ScopedEnv& operator=(const ScopedEnv&) = delete; + + private: + std::string name_; + std::optional oldValue_; +}; + +inline std::filesystem::path makeTempDir(const std::string& prefix) { + std::string tmpl = (std::filesystem::temp_directory_path() / (prefix + "-XXXXXX")).string(); + char* result = mkdtemp(tmpl.data()); + if (!result) { + throw std::runtime_error("Failed to create temp directory"); + } + return result; +} + +inline std::string writeTempFile(const std::filesystem::path& dir, const std::string& name, + const std::string& content) { + auto path = dir / name; + std::filesystem::create_directories(path.parent_path()); + std::ofstream ofs(path); + if (!ofs) { + throw std::runtime_error("Failed to create temp file: " + path.string()); + } + ofs << content; + ofs.close(); + return path.string(); +} + +#endif // VRTD_TEST_HELPERS_HPP diff --git a/vrt/vrtd/tests/utils_test.cpp b/vrt/vrtd/tests/utils_test.cpp new file mode 100644 index 00000000..ad81ff7d --- /dev/null +++ b/vrt/vrtd/tests/utils_test.cpp @@ -0,0 +1,127 @@ +/** + * The MIT License (MIT) + * Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT + * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +extern "C" { +#include "utils.h" +} + +// --- string_to_bool --- + +TEST(StringToBoolTest, TruthyValues) { + EXPECT_TRUE(string_to_bool("1")); + EXPECT_TRUE(string_to_bool("y")); + EXPECT_TRUE(string_to_bool("Y")); + EXPECT_TRUE(string_to_bool("yes")); + EXPECT_TRUE(string_to_bool("YES")); + EXPECT_TRUE(string_to_bool("Yes")); + EXPECT_TRUE(string_to_bool("true")); + EXPECT_TRUE(string_to_bool("TRUE")); + EXPECT_TRUE(string_to_bool("True")); +} + +TEST(StringToBoolTest, FalsyValues) { + EXPECT_FALSE(string_to_bool("0")); + EXPECT_FALSE(string_to_bool("n")); + EXPECT_FALSE(string_to_bool("N")); + EXPECT_FALSE(string_to_bool("no")); + EXPECT_FALSE(string_to_bool("false")); + EXPECT_FALSE(string_to_bool("FALSE")); + EXPECT_FALSE(string_to_bool("")); + EXPECT_FALSE(string_to_bool("2")); + EXPECT_FALSE(string_to_bool("maybe")); +} + +TEST(StringToBoolTest, NullReturnsFalse) { + EXPECT_FALSE(string_to_bool(nullptr)); +} + +TEST(StringToBoolTest, WhitespaceTrimming) { + EXPECT_TRUE(string_to_bool(" yes ")); + EXPECT_TRUE(string_to_bool("\ttrue\n")); + EXPECT_TRUE(string_to_bool(" 1 ")); + EXPECT_FALSE(string_to_bool(" ")); +} + +// --- bit_ceil_u32 --- + +TEST(BitCeilU32Test, Zero) { + EXPECT_EQ(bit_ceil_u32(0u), 1u); +} + +TEST(BitCeilU32Test, One) { + EXPECT_EQ(bit_ceil_u32(1u), 1u); +} + +TEST(BitCeilU32Test, PowersOfTwo) { + EXPECT_EQ(bit_ceil_u32(2u), 2u); + EXPECT_EQ(bit_ceil_u32(4u), 4u); + EXPECT_EQ(bit_ceil_u32(8u), 8u); + EXPECT_EQ(bit_ceil_u32(0x80000000u), 0x80000000u); +} + +TEST(BitCeilU32Test, NonPowersRoundUp) { + EXPECT_EQ(bit_ceil_u32(3u), 4u); + EXPECT_EQ(bit_ceil_u32(5u), 8u); + EXPECT_EQ(bit_ceil_u32(7u), 8u); + EXPECT_EQ(bit_ceil_u32(9u), 16u); + EXPECT_EQ(bit_ceil_u32(100u), 128u); +} + +TEST(BitCeilU32Test, Overflow) { + EXPECT_EQ(bit_ceil_u32(0x80000001u), 0u); + EXPECT_EQ(bit_ceil_u32(0xFFFFFFFFu), 0u); +} + +// --- bit_ceil_u64 --- + +TEST(BitCeilU64Test, Zero) { + EXPECT_EQ(bit_ceil_u64(0ull), 1ull); +} + +TEST(BitCeilU64Test, One) { + EXPECT_EQ(bit_ceil_u64(1ull), 1ull); +} + +TEST(BitCeilU64Test, PowersOfTwo) { + EXPECT_EQ(bit_ceil_u64(2ull), 2ull); + EXPECT_EQ(bit_ceil_u64(0x100000000ull), 0x100000000ull); +} + +TEST(BitCeilU64Test, NonPowersRoundUp) { + EXPECT_EQ(bit_ceil_u64(3ull), 4ull); + EXPECT_EQ(bit_ceil_u64(5ull), 8ull); + EXPECT_EQ(bit_ceil_u64(0x100000001ull), 0x200000000ull); +} + +TEST(BitCeilU64Test, Overflow) { + EXPECT_EQ(bit_ceil_u64(0x8000000000000001ull), 0ull); +} + +// --- glob_err_to_string --- + +TEST(GlobErrTest, AllCodes) { + EXPECT_STREQ(glob_err_to_string(0), "OK"); + EXPECT_STREQ(glob_err_to_string(GLOB_NOSPACE), "out of memory"); + EXPECT_STREQ(glob_err_to_string(GLOB_ABORTED), "read error"); + EXPECT_STREQ(glob_err_to_string(GLOB_NOMATCH), "no matches found"); + EXPECT_STREQ(glob_err_to_string(999), "unknown glob(3) error"); +} diff --git a/vrt/vrtd/udev/99-vrtd.rules b/vrt/vrtd/udev/99-vrtd.rules new file mode 100644 index 00000000..eca2e0e5 --- /dev/null +++ b/vrt/vrtd/udev/99-vrtd.rules @@ -0,0 +1,24 @@ +# ################################################################################################## +# The MIT License (MIT) +# Copyright (c) 2025-2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy of this software +# and associated documentation files (the "Software"), to deal in the Software without restriction, +# including without limitation the rights to use, copy, modify, merge, publish, distribute, +# sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all copies or +# substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT +# NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################################## + +KERNEL=="slash", MODE="0600", OWNER="vrtd", GROUP="vrtd" +KERNEL=="slash_hotplug", MODE="0600", OWNER="vrtd", GROUP="vrtd" +KERNEL=="slash_ctl*", MODE="0600", OWNER="vrtd", GROUP="vrtd" +KERNEL=="slash_qdma_ctl*", MODE="0600", OWNER="vrtd", GROUP="vrtd"