From 0822c383e412438dd64ab57e686cf0760317ffc2 Mon Sep 17 00:00:00 2001 From: Anastasios Bakogiannis Date: Mon, 11 May 2026 11:15:33 +0200 Subject: [PATCH] fix: correct assetion logic --- datasketches/src/hll/array4.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/datasketches/src/hll/array4.rs b/datasketches/src/hll/array4.rs index b8e5b36..f0f6132 100644 --- a/datasketches/src/hll/array4.rs +++ b/datasketches/src/hll/array4.rs @@ -230,10 +230,10 @@ impl Array4 { let mut new_aux = None; for (slot, old_actual_val) in old_aux.into_iter() { - debug_assert_ne!( + debug_assert_eq!( self.get_raw(slot), AUX_TOKEN, - "AuxMap contains slow without AUX_TOKEN" + "AuxMap contains slot != AUX_TOKEN" ); let new_shifted = old_actual_val - new_cur_min;