[P0] Memory Placement in Mapping

[n0thingNoob]

@ShangkunLi
Do we have this function, like considering the external memory placement to do the mapping?

[ShangkunLi]

I only support this functionality based on the CGRA-Mapper. Please refer to https://github.com/ShangkunLi/CMD.

And it is for distributed memory, not detailed multi-bank SRAM placement.

[tancheng]

Hi @n0thingNoob @ShangkunLi, I think @n0thingNoob's question is simply meaning whether we support load/store on left-most or any tile for now.

dataflow/include/NeuraDialect/Architecture/Architecture.h

Lines 80 to 87 in e05ca6a

	bool canSupportOperation(OperationKind operation) const {
	for (const auto &op : supported_operations) {
	if (op == operation) {
	return true;
	}
	}
	return false;
	}

dataflow/lib/NeuraDialect/Mapping/mapping_util.cpp

Lines 19 to 31 in e05ca6a

	OperationKind getOperationKindFromMlirOp(Operation *op) {
	if (isa<neura::AddOp>(op))
	return IAdd;
	if (isa<neura::MulOp>(op))
	return IMul;
	if (isa<neura::FAddOp>(op))
	return FAdd;
	if (isa<neura::FMulOp>(op))
	return FMul;
	// TODO: Complete the list here.
	// @Jackcuii, https://github.com/coredac/dataflow/issues/82.
	return IAdd;
	}

So the current implementation is like for all operations, no matter what type it is, we assume we support it, which is wrong.

I left the issue assigned to @Jackcuii here:

dataflow/lib/NeuraDialect/Architecture/Architecture.cpp

Lines 18 to 20 in e05ca6a

	// TODO: Add function units based on architecture specs.
	// @Jackcuii, https://github.com/coredac/dataflow/issues/82.
	addFunctionUnit(std::make_unique<FixedPointAdder>(0));

, so if we want to support load/store only exist on left-most tiles, we need to initialize each tile based on the architecture_spec.yaml.

[tancheng]

@n0thingNoob How do we support load/store constraints? via following?

dataflow/test/arch_spec/arch_spec_example.yaml

Lines 58 to 66 in dc75783

	fu_types: ["mem", "mem_indexed"]
	num_registers: 32
	existence: true
	- cgra_x: 1
	cgra_y: 0
	tile_x: 3
	tile_y: 0
	fu_types: ["mem", "mem_indexed"]

CCing @Jackcuii. But above is just single one tile can access memory, and load/store would overwrite all the other FUs on tile 0? (i.e., no other operations can be performed?)

[n0thingNoob]

@n0thingNoob How do we support load/store constraints? via following?

dataflow/test/arch_spec/arch_spec_example.yaml

Lines 58 to 66 in dc75783

fu_types: ["mem", "mem_indexed"]
num_registers: 32
existence: true

• cgra_x: 1
  cgra_y: 0
  tile_x: 3
  tile_y: 0
  fu_types: ["mem", "mem_indexed"]
  CCing @Jackcuii. But above is just single one tile can access memory, and load/store would overwrite all the other FUs on tile 0? (i.e., no other operations can be performed?)

Is this only for a single tile? I think we can directly specify which side the memory is on. I’d prefer not to dedicate one tile entirely as a memory functional unit. I don't quite remember the initial state of this fu_types part.

[tancheng]

@n0thingNoob you initialized all tiles with mem access:

dataflow/test/arch_spec/arch_spec_example.yaml

Line 22 in dc75783

fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "mem", "return", "mem_indexed", "alloca", "shift"] # comprehensive function unit types

[n0thingNoob]

I think my original assumption was that each tile has on-chip memory, which is why I thought we needed a memory FU. But for the current design, what we really need to determine is which side connects to off-chip memory. We probably don’t need a dedicated memory FU for this. Maybe we just need to add another field to specify the memory side.

[tancheng]

I think my original assumption was that each tile has on-chip memory, which is why I thought we needed a memory FU. But for the current design, what we really need to determine is which side connects to off-chip memory. We probably don’t need a dedicated memory FU for this. Maybe we just need to add another field to specify the memory side.

That sounds okay. But we do need support the most basic method to enable mem access, i.e., list all tiles on the left, and provide the overwritten FU list (including the mem_unit). Should we update the arch_spec (or provide another one) for the simulation vs. verilog comparison?

[n0thingNoob]

ok, I think we can update a new arch_spec. let me see.

[tancheng]

Fixed by #282