@@ -173,6 +173,39 @@ pub(crate) const VIRTUALIZED_MSRS: &[(u32, u64, bool)] = &[
173173 ( 0x26D , 0 , true ) , // MTRRfix4K_E8000
174174 ( 0x26E , 0 , true ) , // MTRRfix4K_F0000
175175 ( 0x26F , 0 , true ) , // MTRRfix4K_F8000
176+
177+ // ── MSHV/WHP additional virtualizations ─────────────────────────
178+ // These MSRs are handled internally by the Microsoft Hypervisor
179+ // without generating VM exits, even when MSR intercepts are enabled.
180+ // On KVM, the deny-all MSR filter traps them instead.
181+
182+ // Read-only MSRs (no reset needed)
183+ ( 0x17 , 0 , false ) , // IA32_PLATFORM_ID (read-only)
184+ ( 0x8B , 0 , false ) , // IA32_BIOS_SIGN_ID (read-only)
185+ ( 0x10A , 0 , false ) , // IA32_ARCH_CAPABILITIES (read-only)
186+ ( 0x179 , 0 , false ) , // IA32_MCG_CAP (read-only)
187+ ( 0x17A , 0 , false ) , // IA32_MCG_STATUS (read-only in guest)
188+ ( 0x4D0 , 0 , false ) , // Platform-specific (read-only in guest)
189+
190+ // Speculative execution control
191+ ( 0x48 , 0 , true ) , // IA32_SPEC_CTRL
192+
193+ // CET (Control-flow Enforcement Technology) MSRs
194+ ( 0x6A0 , 0 , true ) , // IA32_U_CET
195+ ( 0x6A2 , 0 , true ) , // IA32_S_CET
196+ ( 0x6A4 , 0 , true ) , // IA32_PL0_SSP
197+ ( 0x6A5 , 0 , true ) , // IA32_PL1_SSP
198+ ( 0x6A6 , 0 , true ) , // IA32_PL2_SSP
199+ ( 0x6A7 , 0 , true ) , // IA32_PL3_SSP
200+ ( 0x6A8 , 0 , true ) , // IA32_INTERRUPT_SSP_TABLE_ADDR
201+
202+ // Extended supervisor state
203+ ( 0xDA0 , 0 , true ) , // IA32_XSS
204+
205+ // AMD-specific MSRs (read-only in guest context under MSHV)
206+ ( 0xC001_0010 , 0 , false ) , // AMD SYSCFG
207+ ( 0xC001_0114 , 0 , false ) , // AMD VM_CR
208+ ( 0xC001_0131 , 0 , false ) , // AMD (platform-specific)
176209] ;
177210
178211/// Returns `true` if the given MSR index is in [`VIRTUALIZED_MSRS`].
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