173173 "expression" : " ([UNC_C_TOR_INSERTS.OPCODE.0x1c8] + [UNC_C_TOR_INSERTS.OPCODE.0x180]) * 64 / 1000000"
174174 },
175175 {
176- "name" : " metric_TMAM_Info_cycles_both_threads_active (%)" ,
176+ "name" : " metric_TMA_Info_cycles_both_threads_active (%)" ,
177177 "expression" : " 100 * ( (1 - ([CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE] / ([CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY] / 2)) ) if [const_thread_count] > 1 else 0)"
178178 },
179179 {
180- "name" : " metric_TMAM_Info_CoreIPC " ,
180+ "name" : " metric_TMA_Info_CoreIPC " ,
181181 "expression" : " [instructions] / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
182182 },
183183 {
184- "name" : " metric_TMAM_Frontend_Bound (%)" ,
184+ "name" : " metric_TMA_Frontend_Bound (%)" ,
185185 "expression" : " 100 * [IDQ_UOPS_NOT_DELIVERED.CORE] / (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))"
186186 },
187187 {
188- "name" : " metric_TMAM_ ..Frontend_Latency(%)" ,
188+ "name" : " metric_TMA_ ..Frontend_Latency(%)" ,
189189 "expression" : " 100 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
190190 },
191191 {
192- "name" : " metric_TMAM_ ....ICache_Misses(%)" ,
192+ "name" : " metric_TMA_ ....ICache_Misses(%)" ,
193193 "expression" : " 100 * [ICACHE.IFDATA_STALL] / [cpu-cycles]"
194194 },
195195 {
196- "name" : " metric_TMAM_ ....ITLB_Misses(%)" ,
196+ "name" : " metric_TMA_ ....ITLB_Misses(%)" ,
197197 "expression" : " 100 * ((14 * [ITLB_MISSES.STLB_HIT]) + [ITLB_MISSES.WALK_DURATION_c1] + (7 * [ITLB_MISSES.WALK_COMPLETED] )) / [cpu-cycles]"
198198 },
199199 {
200- "name" : " metric_TMAM_ ....Branch_Resteers(%)" ,
200+ "name" : " metric_TMA_ ....Branch_Resteers(%)" ,
201201 "expression" : " 100 * (([RS_EVENTS.EMPTY_CYCLES] - [ICACHE.IFDATA_STALL] - (14 * [ITLB_MISSES.STLB_HIT] + [ITLB_MISSES.WALK_DURATION_c1] + 7 * [ITLB_MISSES.WALK_COMPLETED])) / [RS_EVENTS.EMPTY_END]) * ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] + [BACLEARS.ANY]) / [cpu-cycles]"
202202 },
203203 {
204- "name" : " metric_TMAM_ ....DSB_Switches(%)" ,
204+ "name" : " metric_TMA_ ....DSB_Switches(%)" ,
205205 "expression" : " 100 * 2 * [DSB2MITE_SWITCHES.PENALTY_CYCLES] / [cpu-cycles]"
206206 },
207207 {
208- "name" : " metric_TMAM_ ....MS_Switches(%)" ,
208+ "name" : " metric_TMA_ ....MS_Switches(%)" ,
209209 "expression" : " 100 * 2 * [IDQ.MS_SWITCHES] / [cpu-cycles]"
210210 },
211211 {
212- "name" : " metric_TMAM_ ..Frontend_Bandwidth(%)" ,
212+ "name" : " metric_TMA_ ..Frontend_Bandwidth(%)" ,
213213 "expression" : " 100 * ([IDQ_UOPS_NOT_DELIVERED.CORE] - (4 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE])) / (4 * [CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
214214 },
215215 {
216- "name" : " metric_TMAM_Bad_Speculation (%)" ,
216+ "name" : " metric_TMA_Bad_Speculation (%)" ,
217217 "expression" : " 100 * ([UOPS_ISSUED.ANY] - [UOPS_RETIRED.RETIRE_SLOTS] + ((4 * [INT_MISC.RECOVERY_CYCLES_ANY]) / [const_thread_count])) / (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])) "
218218 },
219219 {
220- "name" : " metric_TMAM_ ..Branch_Mispredicts(%)" ,
220+ "name" : " metric_TMA_ ..Branch_Mispredicts(%)" ,
221221 "expression" : " ([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * 100 * ([UOPS_ISSUED.ANY] - [UOPS_RETIRED.RETIRE_SLOTS] + (4 * [INT_MISC.RECOVERY_CYCLES_ANY] / [const_thread_count])) / (4 * [CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
222222 },
223223 {
224- "name" : " metric_TMAM_ ..Machine_Clears(%)" ,
224+ "name" : " metric_TMA_ ..Machine_Clears(%)" ,
225225 "expression" : " ([MACHINE_CLEARS.COUNT] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * 100 * ([UOPS_ISSUED.ANY] - [UOPS_RETIRED.RETIRE_SLOTS] + (4 * [INT_MISC.RECOVERY_CYCLES_ANY] / [const_thread_count])) / (4 * [CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
226226 },
227227 {
228- "name" : " metric_TMAM_Backend_bound (%)" ,
228+ "name" : " metric_TMA_Backend_Bound (%)" ,
229229 "expression" : " 100 - (100 * ([UOPS_ISSUED.ANY] - [UOPS_RETIRED.RETIRE_SLOTS] + 4 * ([INT_MISC.RECOVERY_CYCLES_ANY] / [const_thread_count]) + [IDQ_UOPS_NOT_DELIVERED.CORE] + [UOPS_RETIRED.RETIRE_SLOTS]) / (4 * [CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])) "
230230 },
231231 {
232- "name" : " metric_TMAM_ ..Memory_Bound(%)" ,
232+ "name" : " metric_TMA_ ..Memory_Bound(%)" ,
233233 "expression" : " 100 * (1 - (([UOPS_ISSUED.ANY] - [UOPS_RETIRED.RETIRE_SLOTS] + 4 * ([INT_MISC.RECOVERY_CYCLES_ANY] / [const_thread_count]) + [IDQ_UOPS_NOT_DELIVERED.CORE] + [UOPS_RETIRED.RETIRE_SLOTS]) / (4 * [CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))) * ([CYCLE_ACTIVITY.STALLS_MEM_ANY] + [RESOURCE_STALLS.SB]) / ([CYCLE_ACTIVITY.STALLS_TOTAL] + [UOPS_EXECUTED.CYCLES_GE_1_UOPS_EXEC] - ( [UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC] if ([instructions] / [cpu-cycles]) > 1.8 else [UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC]) - ( [RS_EVENTS.EMPTY_CYCLES] if ([IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [CPU_CLK_UNHALTED.THREAD_ANY]) > 0.1 else 0) + [RESOURCE_STALLS.SB])"
234234 },
235235 {
236- "name" : " metric_TMAM_ ....L1_Bound(%)" ,
236+ "name" : " metric_TMA_ ....L1_Bound(%)" ,
237237 "expression" : " 100 * ([CYCLE_ACTIVITY.STALLS_MEM_ANY] - [CYCLE_ACTIVITY.STALLS_L1D_MISS]) / [cpu-cycles]"
238238 },
239239 {
240- "name" : " metric_TMAM_ ......DTLB_Load(%)" ,
240+ "name" : " metric_TMA_ ......DTLB_Load(%)" ,
241241 "expression" : " 100 * ([DTLB_LOAD_MISSES.STLB_HIT] * 8 + [DTLB_LOAD_MISSES.WALK_DURATION_c1] + 7 * [DTLB_LOAD_MISSES.WALK_COMPLETED]) / [cpu-cycles]"
242242 },
243243 {
244- "name" : " metric_TMAM_ ......Store_Fwd_Blk(%)" ,
244+ "name" : " metric_TMA_ ......Store_Fwd_Blk(%)" ,
245245 "expression" : " 100 * (13 * [LD_BLOCKS.STORE_FORWARD]) / [cpu-cycles]"
246246 },
247247 {
248- "name" : " metric_TMAM_ ....L2_Bound(%)" ,
248+ "name" : " metric_TMA_ ....L2_Bound(%)" ,
249249 "expression" : " 100 * ([CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS]) / [cpu-cycles]"
250250 },
251251 {
252- "name" : " metric_TMAM_ ....L3_Bound(%)" ,
252+ "name" : " metric_TMA_ ....L3_Bound(%)" ,
253253 "expression" : " 100 * [MEM_LOAD_UOPS_RETIRED.L3_HIT] / ([MEM_LOAD_UOPS_RETIRED.L3_HIT] + 7 * [MEM_LOAD_UOPS_RETIRED.L3_MISS]) * ([CYCLE_ACTIVITY.STALLS_L2_MISS] / [cpu-cycles])"
254254 },
255255 {
256- "name" : " metric_TMAM_ ......L3_Latency(%)" ,
256+ "name" : " metric_TMA_ ......L3_Latency(%)" ,
257257 "expression" : " 100 * 41 * [MEM_LOAD_UOPS_RETIRED.L3_HIT] * ( 1 + [MEM_LOAD_UOPS_RETIRED.HIT_LFB] / ( [MEM_LOAD_UOPS_RETIRED.L2_HIT] + [MEM_LOAD_UOPS_RETIRED.L3_HIT] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD] ) ) / [cpu-cycles] "
258258 },
259259 {
260- "name" : " metric_TMAM_ ......Contested_Accesses(%)" ,
260+ "name" : " metric_TMA_ ......Contested_Accesses(%)" ,
261261 "expression" : " 100 * 60 * ([MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS]) * ( 1 + [MEM_LOAD_UOPS_RETIRED.HIT_LFB] / ( [MEM_LOAD_UOPS_RETIRED.L2_HIT] + [MEM_LOAD_UOPS_RETIRED.L3_HIT] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD] ) ) / [cpu-cycles] "
262262 },
263263 {
264- "name" : " metric_TMAM_ ......Data_Sharing(%)" ,
264+ "name" : " metric_TMA_ ......Data_Sharing(%)" ,
265265 "expression" : " 100 * 43 * [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT] * ( 1 + [MEM_LOAD_UOPS_RETIRED.HIT_LFB] / ( [MEM_LOAD_UOPS_RETIRED.L2_HIT] + [MEM_LOAD_UOPS_RETIRED.L3_HIT] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM] + [MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM] + [MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD] ) ) / [cpu-cycles] "
266266 },
267267 {
268- "name" : " metric_TMAM_ ......SQ_Full(%)" ,
268+ "name" : " metric_TMA_ ......SQ_Full(%)" ,
269269 "expression" : " 100 * ([OFFCORE_REQUESTS_BUFFER.SQ_FULL] / [const_thread_count]) / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
270270 },
271271 {
272- "name" : " metric_TMAM_ ....MEM_Bound(%)" ,
272+ "name" : " metric_TMA_ ....MEM_Bound(%)" ,
273273 "expression" : " 100 * (1 - ( [MEM_LOAD_UOPS_RETIRED.L3_HIT] / ([MEM_LOAD_UOPS_RETIRED.L3_HIT] + 7 * [MEM_LOAD_UOPS_RETIRED.L3_MISS])) ) * ([CYCLE_ACTIVITY.STALLS_L2_MISS] / [cpu-cycles])"
274274 },
275275 {
276- "name" : " metric_TMAM_ ......MEM_Bandwidth(%)" ,
276+ "name" : " metric_TMA_ ......MEM_Bandwidth(%)" ,
277277 "expression" : " 100 * (min([OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD_c4], [cpu-cycles])) / [cpu-cycles]"
278278 },
279279 {
280- "name" : " metric_TMAM_ ......MEM_Latency(%)" ,
280+ "name" : " metric_TMA_ ......MEM_Latency(%)" ,
281281 "expression" : " 100 * (min([OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD], [cpu-cycles]) - min([OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD_c4], [cpu-cycles])) / [cpu-cycles]"
282282 },
283283 {
284- "name" : " metric_TMAM_ ....Stores_Bound (%)" ,
284+ "name" : " metric_TMA_ ....Store_Bound (%)" ,
285285 "expression" : " 100 * [RESOURCE_STALLS.SB] / [cpu-cycles]"
286286 },
287287 {
288- "name" : " metric_TMAM_ ......DTLB_Store(%)" ,
288+ "name" : " metric_TMA_ ......DTLB_Store(%)" ,
289289 "expression" : " 100 * (7 * [DTLB_STORE_MISSES.STLB_HIT] + [DTLB_STORE_MISSES.WALK_DURATION_c1]) / [cpu-cycles]"
290290 },
291291 {
292- "name" : " metric_TMAM_ ..Core_Bound(%)" ,
292+ "name" : " metric_TMA_ ..Core_Bound(%)" ,
293293 "expression" : " 100 * ( 1 - (( [UOPS_ISSUED.ANY] - [UOPS_RETIRED.RETIRE_SLOTS] + 4 * ([INT_MISC.RECOVERY_CYCLES_ANY] / [const_thread_count]) + [IDQ_UOPS_NOT_DELIVERED.CORE] + [UOPS_RETIRED.RETIRE_SLOTS] ) / ( 4 * [CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))) * (1 - (([CYCLE_ACTIVITY.STALLS_MEM_ANY] + [RESOURCE_STALLS.SB]) / ([CYCLE_ACTIVITY.STALLS_TOTAL] + [UOPS_EXECUTED.CYCLES_GE_1_UOPS_EXEC] - ( [UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC] if ([instructions] / [cpu-cycles]) > 1.8 else [UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC]) - ([RS_EVENTS.EMPTY_CYCLES] if ([IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [CPU_CLK_UNHALTED.THREAD_ANY]) > 0.1 else 0) + [RESOURCE_STALLS.SB])))"
294294 },
295295 {
296- "name" : " metric_TMAM_ ....Divider(%)" ,
296+ "name" : " metric_TMA_ ....Divider(%)" ,
297297 "expression" : " 100 * [ARITH.FPU_DIV_ACTIVE] / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
298298 },
299299 {
300- "name" : " metric_TMAM_ ....Ports_Utilization(%)" ,
300+ "name" : " metric_TMA_ ....Ports_Utilization(%)" ,
301301 "expression" : " 100 * (( [CYCLE_ACTIVITY.STALLS_TOTAL] + [UOPS_EXECUTED.CYCLES_GE_1_UOPS_EXEC] - ([UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC] if ([instructions] / [cpu-cycles]) > 1.8 else [UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC]) - ([RS_EVENTS.EMPTY_CYCLES] if ([IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [CPU_CLK_UNHALTED.THREAD_ANY]) > 0.1 else 0) + [RESOURCE_STALLS.SB]) - [RESOURCE_STALLS.SB] - [CYCLE_ACTIVITY.STALLS_MEM_ANY] ) /[cpu-cycles]"
302302 },
303303 {
304- "name" : " metric_TMAM_ ......0_Port_Utilized(%)" ,
304+ "name" : " metric_TMA_ ......0_Port_Utilized(%)" ,
305305 "expression" : " 100 * (([UOPS_EXECUTED.CORE_i1_c1] / [const_thread_count]) if ([const_thread_count] > 1) else ([RS_EVENTS.EMPTY_CYCLES] if ([CYCLE_ACTIVITY.STALLS_TOTAL] - ([IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])) ) > 0.1 else 0)) / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]) "
306306 },
307307 {
308- "name" : " metric_TMAM_ ......1_Port_Utilized(%)" ,
308+ "name" : " metric_TMA_ ......1_Port_Utilized(%)" ,
309309 "expression" : " 100 * (([UOPS_EXECUTED.CORE_c1] - [UOPS_EXECUTED.CORE_c2]) / [const_thread_count]) / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
310310 },
311311 {
312- "name" : " metric_TMAM_ ......2_Port_Utilized(%)" ,
312+ "name" : " metric_TMA_ ......2_Port_Utilized(%)" ,
313313 "expression" : " 100 * (([UOPS_EXECUTED.CORE_c2] - [UOPS_EXECUTED.CORE_c3]) / [const_thread_count]) / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
314314 },
315315 {
316- "name" : " metric_TMAM_ ......3m_Ports_Utilized(%)" ,
316+ "name" : " metric_TMA_ ......3m_Ports_Utilized(%)" ,
317317 "expression" : " 100 * ([UOPS_EXECUTED.CORE_c3] / [const_thread_count]) / ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count])"
318318 },
319319 {
320- "name" : " metric_TMAM_Retiring (%)" ,
320+ "name" : " metric_TMA_Retiring (%)" ,
321321 "expression" : " 100 * [UOPS_RETIRED.RETIRE_SLOTS] / (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))"
322322 },
323323 {
324- "name" : " metric_TMAM_ ..Base(%)" ,
324+ "name" : " metric_TMA_ ..Base(%)" ,
325325 "expression" : " 100 *(([UOPS_RETIRED.RETIRE_SLOTS] / (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))) - (([UOPS_RETIRED.RETIRE_SLOTS] / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))))"
326326 },
327327 {
328- "name" : " metric_TMAM_ ..Microcode_Sequencer(%)" ,
328+ "name" : " metric_TMA_ ..Microcode_Sequencer(%)" ,
329329 "expression" : " 100 * (([UOPS_RETIRED.RETIRE_SLOTS] / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] )/ (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))"
330330 }
331331]
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