Removed python 2.7 compatibility

Author: jmgc

doc/source/manual/conversion.rst

@@ -12,7 +12,7 @@ Conversion to Verilog and VHDL
 Introduction
 ============
 
-Subject to some limitations, 
+Subject to some limitations,
 MyHDL supports the automatic conversion of MyHDL code to
 Verilog or VHDL code. This feature provides a path from MyHDL into a
 standard Verilog or VHDL based design environment.
@@ -30,8 +30,8 @@ defined as the :dfn:`convertible subset`. This is described
 in detail in :ref:`conv-subset`.
 
 A convertible design can be converted to an equivalent model in Verilog
-or VHDL, using the function :func:`toVerilog` or :func:`toVHDL`  from the MyHDL 
-library. 
+or VHDL, using the function :func:`toVerilog` or :func:`toVHDL`  from the MyHDL
+library.
 
 When the design is intended for implementation
 a third-party :dfn:`synthesis tool` is used to compile the Verilog or VHDL
@@ -77,7 +77,7 @@ The module ports are inferred from signal usage
   declared. The converter investigates signal usage in the design hierarchy to
   infer whether a signal is used as input, output, or as an internal signal.
 
-Interfaces are convertible 
+Interfaces are convertible
   An *interface*: an object that has a number of :class:`Signal` objects as its
   attributes. The convertor supports this by name expansion and mangling.
 
@@ -190,8 +190,8 @@ Supported types
 ---------------
 
 The most important restriction regards object types.  Only a limited
-amount of types can be converted. Python :class:`int` and
-:class:`long` objects are mapped to Verilog or VHDL integers. All
+amount of types can be converted. Python :class:`int` is mapped
+to Verilog or VHDL integers. All
 other supported types need to have a defined bit width. The
 supported types are the Python :class:`bool` type, the MyHDL
 :class:`intbv` type, and MyHDL enumeration types returned by function
@@ -246,7 +246,7 @@ MyHDL types is summarized in the following table.
 
 Notes:
 
-(1) 
+(1)
    The VHDL ``std_logic`` type is defined in the standard VHDL package
    ``IEEE.std_logic_1164``.
 
@@ -262,9 +262,9 @@ Notes:
 (4)
    All list members should have identical value constraints.
 
-  
+
 (5)
-   Lists are mapped to Verilog memories. 
+   Lists are mapped to Verilog memories.
 
 
 The table as presented applies to MyHDL variables. The convertor also
@@ -340,7 +340,7 @@ converter, possibly qualified with restrictions or usage notes.
 
   is not supported.
 
- 
+
 :keyword:`raise`
    This statement is mapped to statements that end the simulation with an
    error message.
@@ -440,7 +440,7 @@ objects as its attributes.  Grouping signals into an interface simplifies the
 code, improves efficiency, and reduces errors.
 
 The convertor supports interface using hierarchical name expansion and name
-mangling. 
+mangling.
 
 .. _conv-meth-assign:
 
@@ -574,15 +574,15 @@ The value of :attr:`verilog_code` or :attr:`vhdl_code` should be a Python
 template string. A template string supports ``$``-based substitutions.
 The ``$name`` notation can be used to refer to the
 variable names in the context of the string. The convertor will
-substitute the appropriate values in the string and then insert it 
+substitute the appropriate values in the string and then insert it
 instead of the regular converted output.
 
 There is one more issue with user-defined code.
 Normally, the converter infers inputs, internal signals,
 and outputs. It also detects undriven and multiple driven signals. To
 do this, it assumes that signals are not driven by default. It then
 processes the code to find out which signals are driven from
-where. 
+where.
 
 Proper signal usage inference cannot be done with user-defined code. Without
 user help, this will result in warnings or errors during the
@@ -710,7 +710,7 @@ non-synthesizable feature that are of interest for test benches.
 
 the :keyword:`while` loop
  :keyword:`while` loops can be used for high-level control structures.
- 
+
 the :keyword:`raise` statement
    A :keyword:`raise` statement can stop the simulation on an error condition.
 
@@ -795,7 +795,7 @@ Known issues
 Verilog and VHDL integers are 32 bit wide
    Usually, Verilog and VHDL integers are 32 bit wide. In contrast,
    Python is moving toward integers with undefined width. Python
-   :class:`int` and :class:`long` variables are mapped to Verilog
+   :class:`int` is mapped to Verilog
    integers; so for values wider than 32 bit this mapping is
    incorrect.
 

doc/source/manual/reference.rst

@@ -173,7 +173,7 @@ Regular signals
 
 
     .. attribute:: driven
-    
+
        Writable attribute that can be used to indicate that the signal is supposed to
        be driven from the MyHDL code, and possibly how it should be declared in Verilog after
        conversion. The allowed values are ``'reg'``, ``'wire'``, ``True`` and ``False``.
@@ -182,9 +182,9 @@ Regular signals
        whether and how a signal is driven. This occurs when the signal is driven from
        user-defined code. ``'reg'`` and ``'wire'`` are "true" values that
        permit finer control for the Verilog case.
-  
+
     .. attribute:: read
-    
+
        Writable boolean attribute that can be used to indicate that the signal is read.
 
        This attribute is useful when the converter cannot infer automatically
@@ -195,7 +195,7 @@ Regular signals
 
     .. method:: Signal.__call__(left[, right=None])
 
-	This method returns a :class:`_SliceSignal` shadow signal. 
+	This method returns a :class:`_SliceSignal` shadow signal.
 
 
 .. class:: ResetSignal(val, active, async)
@@ -210,7 +210,7 @@ Regular signals
     This class should be used in conjunction with the :func:`always_seq`
     decorator.
 
- 
+
 Shadow signals
 ^^^^^^^^^^^^^^
 
@@ -234,21 +234,21 @@ Shadow signals
 
 .. class:: ConcatSignal(*args)
 
-   This class creates a new shadow signal of the concatenation of its arguments. 
+   This class creates a new shadow signal of the concatenation of its arguments.
 
    You can pass an arbitrary number of arguments to the constructor.  The
    arguments should be bit-oriented with a defined number of bits.  The following
    argument types are supported: :class:`intbv` objects with a defined bit width,
-   :class:`bool` objects, signals of the previous objects, and bit strings. 
+   :class:`bool` objects, signals of the previous objects, and bit strings.
 
    The new signal follows the value changes of the signal arguments. The non-signal
-   arguments are used to define constant values in the concatenation.  
+   arguments are used to define constant values in the concatenation.
 
 .. class:: TristateSignal(val)
 
     This class is used to construct a new tristate signal. The
     underlying type is specified by the *val*
-    parameter. 
+    parameter.
     It is a Signal subclass and has the usual attributes, with
     one exception: it doesn't support the ``next``
     attribute. Consequently, direct signal assignment to a tristate
@@ -389,7 +389,7 @@ generators from local generator functions.
 
           def _gen_func()
               while True:
-                  yield event1, event2, ... 
+                  yield event1, event2, ...
                   _func()
           ...
           inst = _gen_func()
@@ -439,10 +439,10 @@ The :class:`intbv` class
 
     This class represents :class:`int`\ -like objects with some
     additional features that make it suitable for hardware
-    design. 
+    design.
 
-    The *val* argument can be an :class:`int`, a
-    :class:`long`, an :class:`intbv` or a bit string (a string with
+    The *val* argument can be an :class:`int`, an :class:`intbv`
+or a bit string (a string with
     only '0's or '1's). For a bit string argument, the value is
     calculated as in ``int(bitstring, 2)``.  The optional *min* and
     *max* arguments can be used to specify the minimum and maximum
@@ -484,10 +484,10 @@ logical, and conversion operations as :class:`int` objects. See
 http://www.python.org/doc/current/lib/typesnumeric.html for more information on
 such operations. In all binary operations, :class:`intbv` objects can work
 together with :class:`int` objects. For mixed-type numeric operations, the
-result type is an :class:`int` or a :class:`long`. For mixed-type bitwise
+result type is an :class:`int`. For mixed-type bitwise
 operations, the result type is an :class:`intbv`.
 
-In addition, :class:`intbv` supports a number of sequence operators. 
+In addition, :class:`intbv` supports a number of sequence operators.
 In particular, the :func:`len` function returns the object's bit width. Furthermore,
 :class:`intbv` objects support indexing and slicing operations:
 
@@ -552,11 +552,11 @@ The :class:`modbv` class
    Instead of throwing an exception when those constraints are exceeded,
    the value of :class:`modbv` objects wraps around according to the
    following formula::
-  
+
        val = (val - min) % (max - min) + min
-       
+
    This formula is a generalization of modulo wrap-around behavior that
-   is often useful when describing hardware system behavior. 
+   is often useful when describing hardware system behavior.
 
 The :func:`enum` factory function
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -610,12 +610,12 @@ useful for hardware description.
 
    The following argument types are supported: :class:`intbv` objects with a
    defined bit width, :class:`bool` objects, signals of the previous objects, and
-   bit strings. All these objects have a defined bit width. 
+   bit strings. All these objects have a defined bit width.
 
-   The first argument *base* is special as it does not need to have a 
+   The first argument *base* is special as it does not need to have a
    defined bit width. In addition to
-   the previously mentioned objects, unsized :class:`intbv`, :class:`int` and
-   :class:`long` objects are supported, as well as signals of such objects.
+   the previously mentioned objects, unsized :class:`intbv` and :class:`int`
+    objects are supported, as well as signals of such objects.
 
    :rtype: :class:`intbv`
 
@@ -748,7 +748,7 @@ Conversion
     ``func(*args, **kwargs)``. It can be assigned to an instance name.
     The top-level instance name and the basename of the Verilog
     output filename is ``func.func_name`` by default.
-	
+
     :func:`toVHDL` has the following attributes:
 
     .. attribute:: name
@@ -767,17 +767,17 @@ Conversion
        VHDL output. When a string is assigned to it, it will be copied
        to the appropriate place in the output file.
 
-    .. attribute:: library 
+    .. attribute:: library
 
        This attribute can be used to set the library in the VHDL output
-       file. The assigned value should be a string. The default 
+       file. The assigned value should be a string. The default
        library is ``work``.
 
     .. attribute:: std_logic_ports
 
        This boolean attribute can be used to have only ``std_logic`` type
        ports on the top-level interface (when ``True``) instead of the
-       default ``signed/unsigned`` types (when ``False``, the default). 
+       default ``signed/unsigned`` types (when ``False``, the default).
 
 
 
@@ -819,7 +819,7 @@ Conversion output verification
 
 .. module:: myhdl.conversion
 
-MyHDL provides an interface to verify converted designs. 
+MyHDL provides an interface to verify converted designs.
 This is used extensively in the package itself to verify the conversion
 functionality. This capability is exported by the package so that users
 can use it also.
@@ -846,7 +846,7 @@ the :mod:`myhdl.conversion` package.
 .. function:: analyze(func[, *args][, **kwargs])
 
     Used like :func:`toVHDL()` and :func:`toVerilog()`. It converts MyHDL code, and analyzes the
-    resulting HDL. 
+    resulting HDL.
     Used to verify whether the HDL output is syntactically correct.
 
     This function has the following attribute:

doc/source/whatsnew/0.3.rst

@@ -124,7 +124,7 @@ For example, suppose that we have a mux module described as follows:
 
     def mux(z, a, b, sel):
         """ Multiplexer.
-        
+
         z -- mux output
         a, b -- data inputs
         sel -- control input
@@ -146,7 +146,7 @@ Using :func:`always_comb()`, we can describe it as follows instead:
 
     def mux(z, a, b, sel):
         """ Multiplexer.
-        
+
         z -- mux output
         a, b -- data inputs
         sel -- control input
@@ -182,7 +182,7 @@ returned explicitly. The following is a schematic example:
         instance_2 = module_2(...)
         ...
         instance_n = module_n(...)
-        ... 
+        ...
         return instance_1, instance_2, ... , instance_n
 
 It may be convenient to assemble the list of instances automatically,
@@ -255,7 +255,7 @@ be used as follows:
         ...
         def process_n():
             ...
-        ... 
+        ...
         return processes()
 
 To conclude, a top level function with both instances and processes can
@@ -340,7 +340,7 @@ returned a new :class:`intbv` object, even in mixed-mode operations with
 :class:`int`, and bitwise operations return a :class:`intbv`. In this
 way, the return value corresponds better to the nature of the operation.
 
-Function :func:`concat()` 
+Function :func:`concat()`
 ==========================
 
 In previous versions, the :class:`intbv` class provided a method. This
@@ -352,7 +352,7 @@ concatenated: :class:`intbv` objects with a defined bit width,
 :class:`bool` objects, the corresponding signal objects, and bit
 strings. All these objects have a defined bit width. Moreover, the first
 argument doesn’t need to have a defined bit width. It can also be an
-unsized :class:`intbv`, an :class:`int`, a :class:`long`, or a
+unsized :class:`intbv`, an :class:`int`, or a
 corresponding signal object. Function :func:`concat()` returns an
 :class:`intbv` object.