From 836a2e2af348d1bd8fe6db9b04a880160d093273 Mon Sep 17 00:00:00 2001
From: Martin Kobetic <magh@kobetic.ca>
Date: Tue, 31 Mar 2026 09:37:31 -0400
Subject: [PATCH 1/3] ARM: interrupts

---
 arm/amforth.s              |   3 +-
 arm/isr.s                  |   2 +
 arm/macros.inc             |   4 +-
 arm/mcu/ra4m1/amforth.s    |   3 +-
 arm/mcu/ra4m1/interrupts.f |   6 --
 arm/mcu/ra4m1/isr.s        |  21 +----
 arm/mcu/ra4m1/vectors.s    | 175 +++++++++----------------------------
 arm/system.s               |  35 ++++++++
 arm/vectors.s              |  20 ++---
 9 files changed, 97 insertions(+), 172 deletions(-)
 delete mode 100644 arm/mcu/ra4m1/interrupts.f
 create mode 100644 arm/system.s

diff --git a/arm/amforth.s b/arm/amforth.s
index 2902b7db..cd630d03 100644
--- a/arm/amforth.s
+++ b/arm/amforth.s
@@ -26,10 +26,11 @@ The default (custom) section flags seem to be CONTENTS and READONLY so not ALLOC
 .include "vectors.s" 
 
 .section amforth, "ax"
-.include "isr.s"
 
 STARTDICT
 
+.include "isr.s"
+.include "system.s"
 .include "dict_prims.inc"
 .include "dict_secs.inc"
 .include "dict_env.inc"
diff --git a/arm/isr.s b/arm/isr.s
index f20eb8ed..d857e351 100644
--- a/arm/isr.s
+++ b/arm/isr.s
@@ -1,3 +1,4 @@
+.thumb_func
 nullhandler:
    push {lr}
    push {r1}
@@ -10,6 +11,7 @@ nullhandler:
    pop {r1}
    pop {pc}
 
+.thumb_func
 faulthandler:
    push {lr}
    push {r1}
diff --git a/arm/macros.inc b/arm/macros.inc
index c9112a34..6fa061f9 100644
--- a/arm/macros.inc
+++ b/arm/macros.inc
@@ -7,8 +7,8 @@
 DEBUG   .req r6 @ used when WANT_DEBUGGER == YES
 TOS     .req r7
 DSP     .req r8
-FW  .req r9
-FIP .req r10
+FW      .req r9
+FIP     .req r10
 UP      .req r11
 
 @ default register mapping
diff --git a/arm/mcu/ra4m1/amforth.s b/arm/mcu/ra4m1/amforth.s
index fd779d2b..be27d3d7 100644
--- a/arm/mcu/ra4m1/amforth.s
+++ b/arm/mcu/ra4m1/amforth.s
@@ -19,10 +19,11 @@
 .p2align 2
 
 .section amforth, "ax"
-.include "mcu/ra4m1/isr.s"
 
 STARTDICT
 
+.include "isr.s"
+.include "system.s"
 .include "dict_prims.inc"
 .include "dict_secs.inc"
 .include "dict_env.inc"
diff --git a/arm/mcu/ra4m1/interrupts.f b/arm/mcu/ra4m1/interrupts.f
deleted file mode 100644
index 671067f9..00000000
--- a/arm/mcu/ra4m1/interrupts.f
+++ /dev/null
@@ -1,6 +0,0 @@
-\ Interrupt Controller Type Register, ICTR
-\ INTLINESNUM, bits[3:0]
-\   The total number of interrupt lines supported by an implementation, defined in groups of
-\   32. That is, the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
-\   However,the absolute maximum number of interrupts is 496
-$E000E004
diff --git a/arm/mcu/ra4m1/isr.s b/arm/mcu/ra4m1/isr.s
index ab7e0bb2..9186c7e6 100644
--- a/arm/mcu/ra4m1/isr.s
+++ b/arm/mcu/ra4m1/isr.s
@@ -1,22 +1,3 @@
-irq_vektor_porta:
-irq_vektor_portb:
-irq_vektor_portc:
-irq_vektor_portd:
-irq_vektor_porte:
-irq_vektor_portf:
-irq_vektor_terminal:
-
-irq_vektor_adc0seq0:
-irq_vektor_adc0seq1:
-irq_vektor_adc0seq2:
-irq_vektor_adc0seq3:
-
-irq_vektor_timer0a:
-irq_vektor_timer0b:
-irq_vektor_timer1a:
-irq_vektor_timer1b:
-irq_vektor_timer2a:
-irq_vektor_timer2b:
-
 # fall back to nullhandler
 .include "arm/isr.s"
+
diff --git a/arm/mcu/ra4m1/vectors.s b/arm/mcu/ra4m1/vectors.s
index 8e968c24..d0a394c8 100644
--- a/arm/mcu/ra4m1/vectors.s
+++ b/arm/mcu/ra4m1/vectors.s
@@ -2,136 +2,47 @@
 IRQ_VECTORS:
 .include "arm/vectors.s"
 
-@ Special interrupt handlers for this particular chip:
-
-.word irq_vektor_porta+1   @ 16: GPIO Port A
-.word irq_vektor_portb+1   @ 17: GPIO Port B
-.word irq_vektor_portc+1   @ 18: GPIO Port C
-.word irq_vektor_portd+1   @ 19: GPIO Port D
-.word irq_vektor_porte+1   @ 20: GPIO Port E
-.word irq_vektor_terminal+1   @ 21: UART0 Rx and Tx
-
-.word nullhandler+1   @ 22: UART1 Rx and Tx
-.word nullhandler+1   @ 23: SSI0 Rx and Tx
-.word nullhandler+1   @ 24: I2C0 Master and Slave
-
-.word 0  @ 25: Reserved
-.word 0  @ 26: Reserved
-.word 0  @ 27: Reserved
-.word 0  @ 28: Reserved
-.word 0  @ 29: Reserved
-
-.word irq_vektor_adc0seq0+1   @ 30: ADC Sequence 0
-.word irq_vektor_adc0seq1+1   @ 31: ADC Sequence 1
-.word irq_vektor_adc0seq2+1   @ 32: ADC Sequence 2
-.word irq_vektor_adc0seq3+1   @ 33: ADC Sequence 3
-
-.word nullhandler+1   @ 34: Watchdog timers 0 and 1
-
-.word irq_vektor_timer0a+1   @ 35: Timer 0 subtimer A
-.word irq_vektor_timer0b+1   @ 36: Timer 0 subtimer B
-.word irq_vektor_timer1a+1   @ 37: Timer 1 subtimer A
-.word irq_vektor_timer1b+1   @ 38: Timer 1 subtimer B
-.word irq_vektor_timer2a+1   @ 39: Timer 2 subtimer A
-.word irq_vektor_timer2b+1   @ 40: Timer 2 subtimer B
-
-.word nullhandler+1   @ 41: Analog Comparator 0
-.word nullhandler+1   @ 42: Analog Comparator 1
-
-.word 0  @ 43: Reserved
-
-.word nullhandler+1   @ 44: System Control (PLL, OSC, BO)
-.word nullhandler+1   @ 45: FLASH Control
-
-.word irq_vektor_portf+1   @ 46: GPIO Port F
-
-
-.word 0  @ 47: Reserved
-.word 0  @ 48: Reserved
-.word nullhandler+1   @ 49:
-.word nullhandler+1   @ 50:
-.word nullhandler+1   @ 51:
-.word nullhandler+1   @ 52:
-.word nullhandler+1   @ 53:
-.word 0  @ 54: Reserved
-.word nullhandler+1   @ 55:
-.word 0  @ 56: Reserved
-.word 0  @ 57: Reserved
-.word 0  @ 58: Reserved
-.word nullhandler+1   @ 59:
-.word nullhandler+1   @ 60:
-.word 0  @ 61: Reserved
-
-.word nullhandler+1   @ 62:
-.word nullhandler+1   @ 63:
-.word nullhandler+1   @ 64:
-.word nullhandler+1   @ 65:
-.word nullhandler+1   @ 66:
-.word nullhandler+1   @ 67:
-
-.word 0  @ 68: Reserved
-.word 0  @ 69: Reserved
-.word 0  @ 70: Reserved
-.word 0  @ 71: Reserved
-.word 0  @ 72: Reserved
-
-.word nullhandler+1   @ 73:
-.word nullhandler+1   @ 74:
-.word nullhandler+1   @ 75:
-.word nullhandler+1   @ 76:
-.word nullhandler+1   @ 77:
-.word nullhandler+1   @ 78:
-.word nullhandler+1   @ 79:
-
-.word 0  @ 80: Reserved
-.word 0  @ 81: Reserved
-.word 0  @ 82: Reserved
-.word 0  @ 83: Reserved
-
-.word nullhandler+1   @ 84:
-.word nullhandler+1   @ 85:
-.word nullhandler+1   @ 86:
-.word nullhandler+1   @ 87:
-
-.word 0  @ 88: Reserved
-.word 0  @ 89: Reserved
-.word 0  @ 90: Reserved
-.word 0  @ 91: Reserved
-.word 0  @ 92: Reserved
-.word 0  @ 93: Reserved
-.word 0  @ 94: Reserved
-.word 0  @ 95: Reserved
-.word 0  @ 96: Reserved
-.word 0  @ 97: Reserved
-.word 0  @ 98: Reserved
-.word 0  @ 99: Reserved
-.word 0  @ 100: Reserved
-.word 0  @ 101: Reserved
-.word 0  @ 102: Reserved
-.word 0  @ 103: Reserved
-.word 0  @ 104: Reserved
-.word 0  @ 105: Reserved
-.word 0  @ 106: Reserved
-.word 0  @ 107: Reserved
-
-.word nullhandler+1   @ 108:
-.word nullhandler+1   @ 109:
-.word nullhandler+1   @ 110:
-.word nullhandler+1   @ 111:
-.word nullhandler+1   @ 112:
-.word nullhandler+1   @ 113:
-.word nullhandler+1   @ 114:
-.word nullhandler+1   @ 115:
-.word nullhandler+1   @ 116:
-.word nullhandler+1   @ 117:
-.word nullhandler+1   @ 118:
-.word nullhandler+1   @ 119:
-.word nullhandler+1   @ 120:
-.word nullhandler+1   @ 121:
-.word nullhandler+1   @ 122:
-
-@ 123-154 reserved, space can be used for core instead.
-
-@ move past the vector table space
-.org 0x400
+/*  RA4M1 User Manual
+    13.3.1 Interrupt Vector Table
+
+    13.2.6 ICU Event Link Setting Register n (IELSRn)
+    Address: 0x40006300 + 4n :
+    * IELS[7:0] - ICU Event Link Select ; 0 = disabled, otherwise Event Table 13.4.
+    * IR[16] - Interrupt Status Flag ; write 0 to clear request
+    * DTCE[24] - DTC Activation Enable ; activates DTC instead of NVIC
+    
+*/
+
+.word 0 @ 16: ICU.IELSR0
+.word 0 @ 17: ICU.IELSR1
+.word 0 @ 18: ICU.IELSR2
+.word 0 @ 19: ICU.IELSR3
+.word 0 @ 20: ICU.IELSR4
+.word 0 @ 21: ICU.IELSR5
+.word 0 @ 22: ICU.IELSR6
+.word 0 @ 23: ICU.IELSR7
+.word 0 @ 24: ICU.IELSR8
+.word 0 @ 25: ICU.IELSR9
+.word 0 @ 26: ICU.IELSR10
+.word 0 @ 27: ICU.IELSR11
+.word 0 @ 28: ICU.IELSR12
+.word 0 @ 29: ICU.IELSR13
+.word 0 @ 30: ICU.IELSR14
+.word 0 @ 31: ICU.IELSR15
+.word 0 @ 32: ICU.IELSR16
+.word 0 @ 33: ICU.IELSR17
+.word 0 @ 34: ICU.IELSR18
+.word 0 @ 35: ICU.IELSR19
+.word 0 @ 36: ICU.IELSR20
+.word 0 @ 37: ICU.IELSR21
+.word 0 @ 38: ICU.IELSR22
+.word 0 @ 39: ICU.IELSR23
+.word 0 @ 40: ICU.IELSR24
+.word 0 @ 41: ICU.IELSR25
+.word 0 @ 42: ICU.IELSR26
+.word 0 @ 43: ICU.IELSR27
+.word 0 @ 44: ICU.IELSR28
+.word 0 @ 45: ICU.IELSR29
+.word 0 @ 46: ICU.IELSR30
+.word 0 @ 47: ICU.IELSR31
 
diff --git a/arm/system.s b/arm/system.s
new file mode 100644
index 00000000..d27b6c2d
--- /dev/null
+++ b/arm/system.s
@@ -0,0 +1,35 @@
+/*  ARMv7M System Memory Region 0xE0000000-0xFFFFFFFF
+    Ref: ARMv7-M Architecture Reference Manual */
+
+/* B3.2.2 System control and ID registers (System Control Space SCS) */
+ARM_CONSTANT "CPUID", CPUID, 0xE000ED00 /* CPUID Base Register */
+ARM_CONSTANT "ICSR", ICSR, 0xE000ED04 /* Interrupt Control Register */
+ARM_CONSTANT "VTOR", VTOR, 0xE000ED08 /* Vector Table Offset Register */
+ARM_CONSTANT "AIRCR", AIRCR , 0xE000ED0C /* Application Interrupt and Reset Control Register */
+ARM_CONSTANT "SCR", SCR, 0xE000ED10 /* System Control Register */
+ARM_CONSTANT "CCR", CCR, 0xE000ED14 /* Configuration and Control Register */
+ARM_CONSTANT "SHPR1", SHPR1 , 0xE000ED18 /* System Handler Priority Register */
+ARM_CONSTANT "SHPR2", SHPR2 , 0xE000ED1C /* System Handler Priority Register */
+ARM_CONSTANT "SHPR3", SHPR3 , 0xE000ED20 /* System Handler Priority Register */
+ARM_CONSTANT "SHCSR", SHCSR , 0xE000ED24 /* System Handler Control and State Register */
+ARM_CONSTANT "CFSR", CFSR, 0xE000ED28 /* Configurable Fault Status Register */
+ARM_CONSTANT "HFSR", HFSR, 0xE000ED2C /* HardFault Status Register */
+ARM_CONSTANT "DFSR", DFSR, 0xE000ED30 /* Debug Fault Status Register */
+ARM_CONSTANT "MMFAR", MMFAR, 0xE000ED34 /* MemManage Fault Address Register */
+ARM_CONSTANT "BFAR", BFAR, 0xE000ED38 /* BusFault Address Register */
+ARM_CONSTANT "AFSR", AFSR, 0xE000ED3C /* Auxiliary Fault Status Register */
+
+ARM_CONSTANT "ICTR", ICTR , 0xE000E004 /* Interrupt Controller Type Register */
+ARM_CONSTANT "ACTLR", ACTLR, 0xE000E008 /* Auxiliary Control Register */
+ARM_CONSTANT "STIR", STIR, 0xE000EF00 /* Software Triggered Interrupt Register */
+
+
+/* B3.4 Nested Vectored Interrupt Controller, NVIC
+   ICTR.INTLINESNUM[5:0] (INTLINESNUM+1)*32 = number of implemented interrupts (max 496)  */
+ARM_CONSTANT "NVIC_ISER", NVIC_ISER, 0xE000E100 /* Interrupt Set-Enable Registers (0-15), bit per interrupt */
+ARM_CONSTANT "NVIC_ICER", NVIC_ICER, 0xE000E180 /* Interrupt Clear-Enable Registers (0-15), bit per interrupt */
+ARM_CONSTANT "NVIC_ISPR", NVIC_ISPR, 0xE000E200 /* Interrupt Set-Pending Registers (0-15), bit per interrupt */
+ARM_CONSTANT "NVIC_ICPR", NVIC_ICPR, 0xE000E280 /* Interrupt Clear-Pending Registers (0-15), bit per interrupt */
+ARM_CONSTANT "NVIC_IABR", NVIC_IABR, 0xE000E300 /* Interrupt Active Bit Registers (0-15), bit per interrupt */
+ARM_CONSTANT "NVIC_IPR", NVIC_IPR, 0xE000E400 /* Interrupt Priority Registers (0-123), byte per interrupt */
+
diff --git a/arm/vectors.s b/arm/vectors.s
index cb755e09..69d74d90 100644
--- a/arm/vectors.s
+++ b/arm/vectors.s
@@ -1,17 +1,17 @@
 .word RAM_upper_returnstack @ 00: Stack top address
-.word PFA_COLD+1            @ 01: Reset Vector  +1 wegen des Thumb-Einsprunges
 
-.word nullhandler+1   @ 02: NMI
-.word faulthandler+1  @ 03: HARD fault
-.word nullhandler+1   @ 04: MPU fault
-.word nullhandler+1   @ 05: bus fault
-.word nullhandler+1   @ 06: usage fault
+.word PFA_COLD        @ 01: Reset Vector
+.word nullhandler     @ 02: NMI
+.word faulthandler    @ 03: HARD fault
+.word nullhandler     @ 04: MPU fault
+.word nullhandler     @ 05: bus fault
+.word nullhandler     @ 06: usage fault
 .word 0               @ 07: Reserved
 .word 0               @ 08: Reserved
 .word 0               @ 09: Reserved
 .word 0               @ 10: Reserved
-.word nullhandler+1   @ 11: SVCall handler
-.word nullhandler+1   @ 12: Debug monitor handler
+.word nullhandler     @ 11: SVCall handler
+.word nullhandler     @ 12: Debug monitor handler
 .word 0               @ 13: Reserved
-.word nullhandler+1   @ 14: The PendSV handler
-.word nullhandler+1   @ 15: systick handler
+.word nullhandler     @ 14: PendSV handler
+.word nullhandler     @ 15: SysTick handler

From 23e03618fb52282864f1f34e57ef5e61fee3784c Mon Sep 17 00:00:00 2001
From: Martin Kobetic <magh@kobetic.ca>
Date: Tue, 14 Apr 2026 10:39:31 -0400
Subject: [PATCH 2/3] prefix constants with ARM_ or RA4_

---
 arm/mcu/ra4m1/words/at-usart.s | 12 ++++----
 arm/mcu/ra4m1/words/clock.s    |  8 +++---
 arm/mcu/ra4m1/words/delay.s    | 34 +++++++++++------------
 arm/mcu/ra4m1/words/led.s      | 10 +++----
 arm/mcu/ra4m1/words/sci.s      | 10 +++----
 arm/mcu/ra4m1/words/usart.s    | 20 +++++++-------
 arm/system.s                   | 50 +++++++++++++++++-----------------
 7 files changed, 72 insertions(+), 72 deletions(-)

diff --git a/arm/mcu/ra4m1/words/at-usart.s b/arm/mcu/ra4m1/words/at-usart.s
index b4bce26c..9e4f2ea2 100644
--- a/arm/mcu/ra4m1/words/at-usart.s
+++ b/arm/mcu/ra4m1/words/at-usart.s
@@ -6,19 +6,19 @@
 # * RA4M1 Group: User's Manual (32-bit): 28. Serial Communications Interface (SCI)
 
 # SCI1 Pins 
-.equ RA4M1_P501PFS, 0x40040940 + 4 * 1  @ TXD1
-.equ RA4M1_P502PFS, 0x40040940 + 4 * 2  @ RXD1
+.equ RA4_P501PFS, 0x40040940 + 4 * 1  @ TXD1
+.equ RA4_P502PFS, 0x40040940 + 4 * 2  @ RXD1
 
 # UART pins and registers SCI1
 .equ AT_UART_BASE, SCI1_BASE
-.equ AT_UART_TXD, RA4M1_P501PFS
-.equ AT_UART_RXD, RA4M1_P502PFS
-.equ AT_UART_STOP, RA4M1_MSTPCRB30
+.equ AT_UART_TXD, RA4_P501PFS
+.equ AT_UART_RXD, RA4_P502PFS
+.equ AT_UART_STOP, RA4_MSTPCRB30
 
 CODEWORD  "at-uart-init", AT_UART_INIT
 
 @ Make sure SCI1 module is not stopped
-  ldr r0, =RA4M1_MSTPCRB
+  ldr r0, =RA4_MSTPCRB
   ldr r1, [r0]
   bic r1, r1, #AT_UART_STOP
   str r1, [r0]
diff --git a/arm/mcu/ra4m1/words/clock.s b/arm/mcu/ra4m1/words/clock.s
index 84669bd2..b8a50fde 100644
--- a/arm/mcu/ra4m1/words/clock.s
+++ b/arm/mcu/ra4m1/words/clock.s
@@ -15,12 +15,12 @@
 # * PCLKB, FCLK = 24 MHz
 
 # Option Setting Memory Registers (6. Option Setting Memory)
-.equ RA4M1_OFS0, 0x00000400 @ Option Function Select Register 0 (32-bit) I/WDT
-.equ RA4M1_OFS1, 0x00000404 @ Option Function Select Register 1 (32-bit) HOCO & voltage detection
+.equ RA4_OFS0, 0x00000400 @ Option Function Select Register 0 (32-bit) I/WDT
+.equ RA4_OFS1, 0x00000404 @ Option Function Select Register 1 (32-bit) HOCO & voltage detection
 # [08]    HOCOEN = HOCO Oscillation Enable ;  UNOR4 = 1 => enabled
 # [14:12] HOCOFRQ = 24MHz(0), 32MHz(2), 48Mhz(4), 64Mhz(5) ; UNOR4 = 4 => 48MHz
 
-.equ RA4M1_SCKDIVCR , 0x4001E020    @ System Clock Division Control Register (32-bit)
+.equ RA4_SCKDIVCR , 0x4001E020    @ System Clock Division Control Register (32-bit)
 # for each clock below n = 0..6 => 1/2^n, i.e 1/1 ... 1/64
 # reset => 4 i.e. 1/16 division
 # [30:28] FCLK (Flash interface clock) UNOR4 = 1
@@ -31,7 +31,7 @@
 # [06:04] PCLKC (ADC14 conversion clock) UNOR4 = 0
 # [02:00] PCLKD (GPT count clock) UNOR4 = 0
 
-.equ RA4M1_SCKSCR, 0x4001E026   @ System Clock Source Control Register (8-bit)
+.equ RA4_SCKSCR, 0x4001E026   @ System Clock Source Control Register (8-bit)
 # [02:00] CKSEL = HOCO(0), MOCO(1), LOCO(2), MOSC(3), SOSC(4), PLL(5) ; UNOR4 = 0 => HOCO
 # reset => MOCO
 
diff --git a/arm/mcu/ra4m1/words/delay.s b/arm/mcu/ra4m1/words/delay.s
index 9db362b8..fa3724b8 100644
--- a/arm/mcu/ra4m1/words/delay.s
+++ b/arm/mcu/ra4m1/words/delay.s
@@ -5,7 +5,7 @@
 # Ref: Cortex-M4 User Guide: 4.4 System timer, SysTick
 # Ref: Renesas RA4M1 User Manual: 2.9 SysTick System Timer
 
-ARM_CONSTANT "SYST_CSR", SYST_CSR, 0xE000E010 
+ARM_CONSTANT "ARM_SYST_CSR", ARM_SYST_CSR, 0xE000E010 
 # SYST_CSR SysTick Control and Status Register
 # Bits   | Name     | Function
 # ----------------------------
@@ -19,7 +19,7 @@ ARM_CONSTANT "SYST_CSR", SYST_CSR, 0xE000E010
 # and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the
 # SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting.
 
-ARM_CONSTANT "SYST_RVR", SYST_RVR, 0xE000E014
+ARM_CONSTANT "ARM_SYST_RVR", ARM_SYST_RVR, 0xE000E014
 # SYST_RVR SysTick Reload Value Register (lower 24 bits only)
 # The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible,
 # but has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0.
@@ -27,43 +27,43 @@ ARM_CONSTANT "SYST_RVR", SYST_RVR, 0xE000E014
 # timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick
 # interrupt is required every 100 clock pulses, set RELOAD to 99.
 
-ARM_CONSTANT "SYST_CVR", SYST_CVR, 0xE000E018
+ARM_CONSTANT "ARM_SYST_CVR", ARM_SYST_CVR, 0xE000E018
 # SYST_CVR SysTick Current Value Register (lower 24 bits only)
 # Reads return the current value of the SysTick counter.
 # A write of any value clears the field to 0, and also clears the SYST_CSR COUNTFLAG bit to 0.
 
-.equ RA4M1_TIMER_RELOAD_VALUE, 0x00FFFFFF
+.equ RA4_TIMER_RELOAD_VALUE, 0x00FFFFFF
 
 ARM_COLON "delay-init", DELAY_INIT
     @ Disable SysTick during setup
-    .word XT_ZERO, XT_SYST_CSR, XT_STORE
+    .word XT_ZERO, XT_ARM_SYST_CSR, XT_STORE
 
     @ Maximum reload value for 24 bit timer
-    .word XT_DOLITERAL, RA4M1_TIMER_RELOAD_VALUE, XT_SYST_RVR, XT_STORE
+    .word XT_DOLITERAL, RA4_TIMER_RELOAD_VALUE, XT_ARM_SYST_RVR, XT_STORE
 
     @ Any write to current clears it
-    .word XT_ZERO, XT_SYST_CVR, XT_STORE
+    .word XT_ZERO, XT_ARM_SYST_CVR, XT_STORE
 
     @ Enable SysTick with SYSTICCLK = 32.768kHz clock
-    .word XT_ONE, XT_SYST_CSR, XT_STORE
+    .word XT_ONE, XT_ARM_SYST_CSR, XT_STORE
 .word XT_EXIT
 
 # Wait for n ticks of the SysTick timer.
 # tick = 1/32.768 kHz = 0.00003051757812 s ~ 30.5 us
-# Clamps n to be no more than RA4M1_TIMER_RELOAD_VALUE
+# Clamps n to be no more than RA4_TIMER_RELOAD_VALUE
 # which translates to about 512 seconds max delay
 ARM_COLON "delay-ticks", DELAY_TICKS
 @ ( n -- ) waits for n ticks of the timer, tick ~ 30 microseconds
-    # make sure n is no more than RA4M1_TIMER_RELOAD_VALUE
-    .word XT_DOLITERAL, RA4M1_TIMER_RELOAD_VALUE, XT_AND
-    .word XT_SYST_CVR, XT_FETCH     @ ( n start-ticks )
+    # make sure n is no more than RA4_TIMER_RELOAD_VALUE
+    .word XT_DOLITERAL, RA4_TIMER_RELOAD_VALUE, XT_AND
+    .word XT_ARM_SYST_CVR, XT_FETCH     @ ( n start-ticks )
 DELAY_TICKS_LOOP:
       .word XT_PAUSE, XT_2DUP
-      .word XT_SYST_CVR, XT_FETCH, XT_MINUS     @ ( n start-ticks n elapsed-ticks )
+      .word XT_ARM_SYST_CVR, XT_FETCH, XT_MINUS     @ ( n start-ticks n elapsed-ticks )
       # need to handle timer wrapping around zero, i.e elapsed ticks is negative
       .word XT_DUP, XT_ZEROLESS, XT_DOCONDBRANCH, DELAY_CHECK_ELAPSED_TICKS
       # if elapsed ticks are negative, add the reload value
-      .word XT_DOLITERAL, RA4M1_TIMER_RELOAD_VALUE, XT_PLUS
+      .word XT_DOLITERAL, RA4_TIMER_RELOAD_VALUE, XT_PLUS
 DELAY_CHECK_ELAPSED_TICKS:
       # otherwise if n < elapsed-ticks exit
       .word XT_UGREATER, XT_NOT, XT_DOCONDBRANCH, DELAY_TICKS_LOOP
@@ -71,7 +71,7 @@ DELAY_CHECK_ELAPSED_TICKS:
 .word XT_EXIT
 
 
-.equ RA4M1_MS_TICKS, 33
+.equ RA4_MS_TICKS, 33
 # Number of timer ticks per millisecond
 #   1 tick = 30.5 us
 #   1 ms = 1000 us / 30.5 us = 32.78 ticks
@@ -81,8 +81,8 @@ COLON "ms", MS
 MS_LOOP:
         @ if n <= 0 leave
         .word XT_DUP, XT_ZEROLESS, XT_NOT, XT_DOCONDBRANCH, MS_LEAVE
-        @ wait RA4M1_MS_TICKS ticks
-        .word XT_DOLITERAL, RA4M1_MS_TICKS, XT_DELAY_TICKS
+        @ wait RA4_MS_TICKS ticks
+        .word XT_DOLITERAL, RA4_MS_TICKS, XT_DELAY_TICKS
         @ decrement n, repeat
         .word XT_1MINUS, XT_DOBRANCH, MS_LOOP
 MS_LEAVE:
diff --git a/arm/mcu/ra4m1/words/led.s b/arm/mcu/ra4m1/words/led.s
index 6ff1c387..57d08b1c 100644
--- a/arm/mcu/ra4m1/words/led.s
+++ b/arm/mcu/ra4m1/words/led.s
@@ -5,11 +5,11 @@
 
 # Write-Protect Register (PWPR)
 # Have to unlock writing to PFS registers before they can be used
-.equ RA4M1_PWPR, 0x40040D03
+.equ RA4_PWPR, 0x40040D03
 
 # 19.2.5 Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 9; n = 00 to 15)
 # PFS.P100PFS 4004 0840h to PFS.P115PFS 4004 087Ch (32-bits)
-.equ RA4M1_P102PFS, 0x40040848
+.equ RA4_P102PFS, 0x40040848
 # BITS:
 # [0]  PODR   Port Output Data
 # [1]  PIDR.  Port Input Data/State
@@ -17,7 +17,7 @@
 # ...
 
 CODEWORD  "led-init", LED_INIT
-   ldr r0, =RA4M1_PWPR
+   ldr r0, =RA4_PWPR
    ldr r1, =0   @ clear B0WI bit
    strb r1, [r0]
    ldr r1, =64   @ set PFSWE bit
@@ -26,12 +26,12 @@ CODEWORD  "led-init", LED_INIT
 
 CODEWORD "led-off", LED_OFF
    ldr r1, =4
-   ldr r0, =RA4M1_P102PFS
+   ldr r0, =RA4_P102PFS
    str r1, [r0]
 NEXT
 
 CODEWORD  "led-on", LED_ON
    ldr r1, =5
-   ldr r0, =RA4M1_P102PFS
+   ldr r0, =RA4_P102PFS
    str r1, [r0]
 NEXT
diff --git a/arm/mcu/ra4m1/words/sci.s b/arm/mcu/ra4m1/words/sci.s
index 5f77e3c8..fa46ee7c 100644
--- a/arm/mcu/ra4m1/words/sci.s
+++ b/arm/mcu/ra4m1/words/sci.s
@@ -1,11 +1,11 @@
 # From RA4M1 Group: User's Manual (32-bit): 28 Serial Communications Interface (SCI)
 #   * only SCI0 and SCI1 support FIFO
 
-.equ RA4M1_MSTPCRB, 0x40047000 @ Module Stop Control Register B
-.equ RA4M1_MSTPCRB22, 1 << 22  @ [22] SCI9 Module Stop (reset = 1)
-.equ RA4M1_MSTPCRB29, 1 << 29  @ [29] SCI2 Module Stop (reset = 1)
-.equ RA4M1_MSTPCRB30, 1 << 30  @ [30] SCI1 Module Stop (reset = 1)
-.equ RA4M1_MSTPCRB31, 1 << 31  @ [31] SCI0 Module Stop (reset = 1)
+.equ RA4_MSTPCRB, 0x40047000 @ Module Stop Control Register B
+.equ RA4_MSTPCRB22, 1 << 22  @ [22] SCI9 Module Stop (reset = 1)
+.equ RA4_MSTPCRB29, 1 << 29  @ [29] SCI2 Module Stop (reset = 1)
+.equ RA4_MSTPCRB30, 1 << 30  @ [30] SCI1 Module Stop (reset = 1)
+.equ RA4_MSTPCRB31, 1 << 31  @ [31] SCI0 Module Stop (reset = 1)
 
 # with FIFO
 .equ SCI0_BASE, 0x40070000   @ base address of the SCI0 registers
diff --git a/arm/mcu/ra4m1/words/usart.s b/arm/mcu/ra4m1/words/usart.s
index 2f1b4543..bd496a8c 100644
--- a/arm/mcu/ra4m1/words/usart.s
+++ b/arm/mcu/ra4m1/words/usart.s
@@ -16,17 +16,17 @@
 #   atLoop() listens for AT commands at SERIAL_AT
 
 # SCI9
-.equ RA4M1_P109PFS, 0x40040840 + 4 * 9  @ TXD9 pin
-.equ RA4M1_P110PFS, 0x40040840 + 4 * 10 @ RXD9 pin
+.equ RA4_P109PFS, 0x40040840 + 4 * 9  @ TXD9 pin
+.equ RA4_P110PFS, 0x40040840 + 4 * 10 @ RXD9 pin
 
 # SCI1 Pins 
-@ .equ RA4M1_P501PFS, 0x40040940 + 4 * 1  @ TXD1
-@ .equ RA4M1_P502PFS, 0x40040940 + 4 * 2  @ RXD1
+@ .equ RA4_P501PFS, 0x40040940 + 4 * 1  @ TXD1
+@ .equ RA4_P502PFS, 0x40040940 + 4 * 2  @ RXD1
 
 # UART pins and registers for SCI9
-.equ UART_TXD, RA4M1_P109PFS
-.equ UART_RXD, RA4M1_P110PFS
-.equ UART_STOP, RA4M1_MSTPCRB22
+.equ UART_TXD, RA4_P109PFS
+.equ UART_RXD, RA4_P110PFS
+.equ UART_STOP, RA4_MSTPCRB22
 .equ UART_SCR, SCI9_SCR
 .equ UART_BRR, SCI9_BRR
 .equ UART_RDR, SCI9_RDR
@@ -34,8 +34,8 @@
 .equ UART_SSR, SCI9_SSR
 
 # UART pins and registers SCI1
-@ .equ UART_TXD, RA4M1_P501PFS
-@ .equ UART_RXD, RA4M1_P502PFS
+@ .equ UART_TXD, RA4_P501PFS
+@ .equ UART_RXD, RA4_P502PFS
 @ .equ UART_SCR, SCI1_SCR
 @ .equ UART_BRR, SCI1_BRR
 @ .equ UART_RDR, SCI1_RDR
@@ -46,7 +46,7 @@
 CODEWORD  "uart-init", UART_INIT
 
 @ Make sure SCI9 module is not stopped
-  ldr r0, =RA4M1_MSTPCRB
+  ldr r0, =RA4_MSTPCRB
   ldr r1, [r0]
   bic r1, r1, #UART_STOP
   str r1, [r0]
diff --git a/arm/system.s b/arm/system.s
index d27b6c2d..63981f5c 100644
--- a/arm/system.s
+++ b/arm/system.s
@@ -2,34 +2,34 @@
     Ref: ARMv7-M Architecture Reference Manual */
 
 /* B3.2.2 System control and ID registers (System Control Space SCS) */
-ARM_CONSTANT "CPUID", CPUID, 0xE000ED00 /* CPUID Base Register */
-ARM_CONSTANT "ICSR", ICSR, 0xE000ED04 /* Interrupt Control Register */
-ARM_CONSTANT "VTOR", VTOR, 0xE000ED08 /* Vector Table Offset Register */
-ARM_CONSTANT "AIRCR", AIRCR , 0xE000ED0C /* Application Interrupt and Reset Control Register */
-ARM_CONSTANT "SCR", SCR, 0xE000ED10 /* System Control Register */
-ARM_CONSTANT "CCR", CCR, 0xE000ED14 /* Configuration and Control Register */
-ARM_CONSTANT "SHPR1", SHPR1 , 0xE000ED18 /* System Handler Priority Register */
-ARM_CONSTANT "SHPR2", SHPR2 , 0xE000ED1C /* System Handler Priority Register */
-ARM_CONSTANT "SHPR3", SHPR3 , 0xE000ED20 /* System Handler Priority Register */
-ARM_CONSTANT "SHCSR", SHCSR , 0xE000ED24 /* System Handler Control and State Register */
-ARM_CONSTANT "CFSR", CFSR, 0xE000ED28 /* Configurable Fault Status Register */
-ARM_CONSTANT "HFSR", HFSR, 0xE000ED2C /* HardFault Status Register */
-ARM_CONSTANT "DFSR", DFSR, 0xE000ED30 /* Debug Fault Status Register */
-ARM_CONSTANT "MMFAR", MMFAR, 0xE000ED34 /* MemManage Fault Address Register */
-ARM_CONSTANT "BFAR", BFAR, 0xE000ED38 /* BusFault Address Register */
-ARM_CONSTANT "AFSR", AFSR, 0xE000ED3C /* Auxiliary Fault Status Register */
+ARM_CONSTANT "ARM_CPUID", CPUID, 0xE000ED00 /* CPUID Base Register */
+ARM_CONSTANT "ARM_ICSR", ICSR, 0xE000ED04 /* Interrupt Control Register */
+ARM_CONSTANT "ARM_VTOR", VTOR, 0xE000ED08 /* Vector Table Offset Register */
+ARM_CONSTANT "ARM_AIRCR", AIRCR , 0xE000ED0C /* Application Interrupt and Reset Control Register */
+ARM_CONSTANT "ARM_SCR", SCR, 0xE000ED10 /* System Control Register */
+ARM_CONSTANT "ARM_CCR", CCR, 0xE000ED14 /* Configuration and Control Register */
+ARM_CONSTANT "ARM_SHPR1", SHPR1 , 0xE000ED18 /* System Handler Priority Register */
+ARM_CONSTANT "ARM_SHPR2", SHPR2 , 0xE000ED1C /* System Handler Priority Register */
+ARM_CONSTANT "ARM_SHPR3", SHPR3 , 0xE000ED20 /* System Handler Priority Register */
+ARM_CONSTANT "ARM_SHCSR", SHCSR , 0xE000ED24 /* System Handler Control and State Register */
+ARM_CONSTANT "ARM_CFSR", CFSR, 0xE000ED28 /* Configurable Fault Status Register */
+ARM_CONSTANT "ARM_HFSR", HFSR, 0xE000ED2C /* HardFault Status Register */
+ARM_CONSTANT "ARM_DFSR", DFSR, 0xE000ED30 /* Debug Fault Status Register */
+ARM_CONSTANT "ARM_MMFAR", MMFAR, 0xE000ED34 /* MemManage Fault Address Register */
+ARM_CONSTANT "ARM_BFAR", BFAR, 0xE000ED38 /* BusFault Address Register */
+ARM_CONSTANT "ARM_AFSR", AFSR, 0xE000ED3C /* Auxiliary Fault Status Register */
 
-ARM_CONSTANT "ICTR", ICTR , 0xE000E004 /* Interrupt Controller Type Register */
-ARM_CONSTANT "ACTLR", ACTLR, 0xE000E008 /* Auxiliary Control Register */
-ARM_CONSTANT "STIR", STIR, 0xE000EF00 /* Software Triggered Interrupt Register */
+ARM_CONSTANT "ARM_ICTR", ICTR , 0xE000E004 /* Interrupt Controller Type Register */
+ARM_CONSTANT "ARM_ACTLR", ACTLR, 0xE000E008 /* Auxiliary Control Register */
+ARM_CONSTANT "ARM_STIR", STIR, 0xE000EF00 /* Software Triggered Interrupt Register */
 
 
 /* B3.4 Nested Vectored Interrupt Controller, NVIC
    ICTR.INTLINESNUM[5:0] (INTLINESNUM+1)*32 = number of implemented interrupts (max 496)  */
-ARM_CONSTANT "NVIC_ISER", NVIC_ISER, 0xE000E100 /* Interrupt Set-Enable Registers (0-15), bit per interrupt */
-ARM_CONSTANT "NVIC_ICER", NVIC_ICER, 0xE000E180 /* Interrupt Clear-Enable Registers (0-15), bit per interrupt */
-ARM_CONSTANT "NVIC_ISPR", NVIC_ISPR, 0xE000E200 /* Interrupt Set-Pending Registers (0-15), bit per interrupt */
-ARM_CONSTANT "NVIC_ICPR", NVIC_ICPR, 0xE000E280 /* Interrupt Clear-Pending Registers (0-15), bit per interrupt */
-ARM_CONSTANT "NVIC_IABR", NVIC_IABR, 0xE000E300 /* Interrupt Active Bit Registers (0-15), bit per interrupt */
-ARM_CONSTANT "NVIC_IPR", NVIC_IPR, 0xE000E400 /* Interrupt Priority Registers (0-123), byte per interrupt */
+ARM_CONSTANT "ARM_NVIC_ISER", NVIC_ISER, 0xE000E100 /* Interrupt Set-Enable Registers (0-15), bit per interrupt */
+ARM_CONSTANT "ARM_NVIC_ICER", NVIC_ICER, 0xE000E180 /* Interrupt Clear-Enable Registers (0-15), bit per interrupt */
+ARM_CONSTANT "ARM_NVIC_ISPR", NVIC_ISPR, 0xE000E200 /* Interrupt Set-Pending Registers (0-15), bit per interrupt */
+ARM_CONSTANT "ARM_NVIC_ICPR", NVIC_ICPR, 0xE000E280 /* Interrupt Clear-Pending Registers (0-15), bit per interrupt */
+ARM_CONSTANT "ARM_NVIC_IABR", NVIC_IABR, 0xE000E300 /* Interrupt Active Bit Registers (0-15), bit per interrupt */
+ARM_CONSTANT "ARM_NVIC_IPR", NVIC_IPR, 0xE000E400 /* Interrupt Priority Registers (0-123), byte per interrupt */
 

From ed26755b93b016bcdfd1be34bf73c2b14ff6df86 Mon Sep 17 00:00:00 2001
From: Martin Kobetic <magh@kobetic.ca>
Date: Wed, 15 Apr 2026 08:39:30 -0400
Subject: [PATCH 3/3] tweaks

---
 arm/mcu/ra4m1/words/at-usart.s |  2 +-
 arm/mcu/ra4m1/words/clock.s    |  2 +-
 arm/mcu/ra4m1/words/sci.s      |  2 +-
 arm/mcu/ra4m1/words/usart.s    |  2 +-
 arm/system.s                   | 50 +++++++++++++++++-----------------
 5 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/arm/mcu/ra4m1/words/at-usart.s b/arm/mcu/ra4m1/words/at-usart.s
index 9e4f2ea2..d35be4f9 100644
--- a/arm/mcu/ra4m1/words/at-usart.s
+++ b/arm/mcu/ra4m1/words/at-usart.s
@@ -3,7 +3,7 @@
 # using non-FIFO async mode for now.
 # TODO: try FIFO
 # References:
-# * RA4M1 Group: User's Manual (32-bit): 28. Serial Communications Interface (SCI)
+# * RA4M1 Group: User Manual (32-bit): 28. Serial Communications Interface (SCI)
 
 # SCI1 Pins 
 .equ RA4_P501PFS, 0x40040940 + 4 * 1  @ TXD1
diff --git a/arm/mcu/ra4m1/words/clock.s b/arm/mcu/ra4m1/words/clock.s
index b8a50fde..b30bb655 100644
--- a/arm/mcu/ra4m1/words/clock.s
+++ b/arm/mcu/ra4m1/words/clock.s
@@ -1,5 +1,5 @@
 # System Clock Support
-# RA4M1 Group: User's Manual (32-bit): 8. Clock Generation Circuit
+# RA4M1 Group: User Manual (32-bit): 8. Clock Generation Circuit
 # Table 8.1 Clock sources:
 # * Main clock oscillator (MOSC): 1-20MHz (2.4V < VCC <= 5.5V => 1 - 20 MHz)
 # * Sub-clock oscillator (SOSC): 32768Hz
diff --git a/arm/mcu/ra4m1/words/sci.s b/arm/mcu/ra4m1/words/sci.s
index fa46ee7c..7c5c8301 100644
--- a/arm/mcu/ra4m1/words/sci.s
+++ b/arm/mcu/ra4m1/words/sci.s
@@ -1,4 +1,4 @@
-# From RA4M1 Group: User's Manual (32-bit): 28 Serial Communications Interface (SCI)
+# From RA4M1 Group: User Manual (32-bit): 28 Serial Communications Interface (SCI)
 #   * only SCI0 and SCI1 support FIFO
 
 .equ RA4_MSTPCRB, 0x40047000 @ Module Stop Control Register B
diff --git a/arm/mcu/ra4m1/words/usart.s b/arm/mcu/ra4m1/words/usart.s
index bd496a8c..ecc11e95 100644
--- a/arm/mcu/ra4m1/words/usart.s
+++ b/arm/mcu/ra4m1/words/usart.s
@@ -1,6 +1,6 @@
 # Implement serial host connection via SCI9, using non-FIFO async mode
 # References:
-# * RA4M1 Group: User's Manual (32-bit): 28. Serial Communications Interface (SCI)
+# * RA4M1 Group: User Manual (32-bit): 28. Serial Communications Interface (SCI)
 
 # From github.com/arduino/uno-r4-wifi-usb-bridge/UNOR4USBBridge/UNOR4USBBridge.ino
 #   Serial refers to tinyUSB CDC port
diff --git a/arm/system.s b/arm/system.s
index 63981f5c..c443d16c 100644
--- a/arm/system.s
+++ b/arm/system.s
@@ -2,34 +2,34 @@
     Ref: ARMv7-M Architecture Reference Manual */
 
 /* B3.2.2 System control and ID registers (System Control Space SCS) */
-ARM_CONSTANT "ARM_CPUID", CPUID, 0xE000ED00 /* CPUID Base Register */
-ARM_CONSTANT "ARM_ICSR", ICSR, 0xE000ED04 /* Interrupt Control Register */
-ARM_CONSTANT "ARM_VTOR", VTOR, 0xE000ED08 /* Vector Table Offset Register */
-ARM_CONSTANT "ARM_AIRCR", AIRCR , 0xE000ED0C /* Application Interrupt and Reset Control Register */
-ARM_CONSTANT "ARM_SCR", SCR, 0xE000ED10 /* System Control Register */
-ARM_CONSTANT "ARM_CCR", CCR, 0xE000ED14 /* Configuration and Control Register */
-ARM_CONSTANT "ARM_SHPR1", SHPR1 , 0xE000ED18 /* System Handler Priority Register */
-ARM_CONSTANT "ARM_SHPR2", SHPR2 , 0xE000ED1C /* System Handler Priority Register */
-ARM_CONSTANT "ARM_SHPR3", SHPR3 , 0xE000ED20 /* System Handler Priority Register */
-ARM_CONSTANT "ARM_SHCSR", SHCSR , 0xE000ED24 /* System Handler Control and State Register */
-ARM_CONSTANT "ARM_CFSR", CFSR, 0xE000ED28 /* Configurable Fault Status Register */
-ARM_CONSTANT "ARM_HFSR", HFSR, 0xE000ED2C /* HardFault Status Register */
-ARM_CONSTANT "ARM_DFSR", DFSR, 0xE000ED30 /* Debug Fault Status Register */
-ARM_CONSTANT "ARM_MMFAR", MMFAR, 0xE000ED34 /* MemManage Fault Address Register */
-ARM_CONSTANT "ARM_BFAR", BFAR, 0xE000ED38 /* BusFault Address Register */
-ARM_CONSTANT "ARM_AFSR", AFSR, 0xE000ED3C /* Auxiliary Fault Status Register */
+.equ ARM_CPUID, 0xE000ED00 /* CPUID Base Register */
+.equ ARM_ICSR, 0xE000ED04 /* Interrupt Control Register */
+.equ ARM_VTOR, 0xE000ED08 /* Vector Table Offset Register */
+.equ ARM_AIRCR, 0xE000ED0C /* Application Interrupt and Reset Control Register */
+.equ ARM_SCR, 0xE000ED10 /* System Control Register */
+.equ ARM_CCR, 0xE000ED14 /* Configuration and Control Register */
+.equ ARM_SHPR1, 0xE000ED18 /* System Handler Priority Register */
+.equ ARM_SHPR2, 0xE000ED1C /* System Handler Priority Register */
+.equ ARM_SHPR3, 0xE000ED20 /* System Handler Priority Register */
+.equ ARM_SHCSR, 0xE000ED24 /* System Handler Control and State Register */
+.equ ARM_CFSR, 0xE000ED28 /* Configurable Fault Status Register */
+.equ ARM_HFSR, 0xE000ED2C /* HardFault Status Register */
+.equ ARM_DFSR, 0xE000ED30 /* Debug Fault Status Register */
+.equ ARM_MMFAR, 0xE000ED34 /* MemManage Fault Address Register */
+.equ ARM_BFAR, 0xE000ED38 /* BusFault Address Register */
+.equ ARM_AFSR, 0xE000ED3C /* Auxiliary Fault Status Register */
 
-ARM_CONSTANT "ARM_ICTR", ICTR , 0xE000E004 /* Interrupt Controller Type Register */
-ARM_CONSTANT "ARM_ACTLR", ACTLR, 0xE000E008 /* Auxiliary Control Register */
-ARM_CONSTANT "ARM_STIR", STIR, 0xE000EF00 /* Software Triggered Interrupt Register */
+.equ ARM_ICTR, 0xE000E004 /* Interrupt Controller Type Register */
+.equ ARM_ACTLR, 0xE000E008 /* Auxiliary Control Register */
+.equ ARM_STIR, 0xE000EF00 /* Software Triggered Interrupt Register */
 
 
 /* B3.4 Nested Vectored Interrupt Controller, NVIC
    ICTR.INTLINESNUM[5:0] (INTLINESNUM+1)*32 = number of implemented interrupts (max 496)  */
-ARM_CONSTANT "ARM_NVIC_ISER", NVIC_ISER, 0xE000E100 /* Interrupt Set-Enable Registers (0-15), bit per interrupt */
-ARM_CONSTANT "ARM_NVIC_ICER", NVIC_ICER, 0xE000E180 /* Interrupt Clear-Enable Registers (0-15), bit per interrupt */
-ARM_CONSTANT "ARM_NVIC_ISPR", NVIC_ISPR, 0xE000E200 /* Interrupt Set-Pending Registers (0-15), bit per interrupt */
-ARM_CONSTANT "ARM_NVIC_ICPR", NVIC_ICPR, 0xE000E280 /* Interrupt Clear-Pending Registers (0-15), bit per interrupt */
-ARM_CONSTANT "ARM_NVIC_IABR", NVIC_IABR, 0xE000E300 /* Interrupt Active Bit Registers (0-15), bit per interrupt */
-ARM_CONSTANT "ARM_NVIC_IPR", NVIC_IPR, 0xE000E400 /* Interrupt Priority Registers (0-123), byte per interrupt */
+.equ ARM_NVIC_ISER, 0xE000E100 /* Interrupt Set-Enable Registers (0-15), bit per interrupt */
+.equ ARM_NVIC_ICER, 0xE000E180 /* Interrupt Clear-Enable Registers (0-15), bit per interrupt */
+.equ ARM_NVIC_ISPR, 0xE000E200 /* Interrupt Set-Pending Registers (0-15), bit per interrupt */
+.equ ARM_NVIC_ICPR, 0xE000E280 /* Interrupt Clear-Pending Registers (0-15), bit per interrupt */
+.equ ARM_NVIC_IABR, 0xE000E300 /* Interrupt Active Bit Registers (0-15), bit per interrupt */
+.equ ARM_NVIC_IPR, 0xE000E400 /* Interrupt Priority Registers (0-123), byte per interrupt */