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CacheController.pcf
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961 lines (959 loc) · 53.2 KB
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//! **************************************************************************
// Written by: Map O.87xd on Wed Oct 30 11:58:32 2019
//! **************************************************************************
SCHEMATIC START;
COMP "clk" LOCATE = SITE "C9" LEVEL 1;
NET "clk_BUFGP/IBUFG" BEL "clk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
PIN
mySRAM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram.A_pins<10>
= BEL
"mySRAM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram.A"
PINNAME CLKA;
PIN
mySRAM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram.B_pins<10>
= BEL
"mySRAM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram.B"
PINNAME CLKB;
PIN
myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>
= BEL
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B"
PINNAME CLKB;
PIN
myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>
= BEL
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B"
PINNAME CLKB;
PIN
myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>
= BEL
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B"
PINNAME CLKB;
PIN
myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[3].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>
= BEL
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[3].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B"
PINNAME CLKB;
TIMEGRP D_CLK = BEL "sADD_0" BEL "sADD_3" BEL "sADD_4" BEL "SDRAM_ADD_0" BEL
"SDRAM_ADD_1" BEL "CPU_Din_0" BEL "CPU_Din_1" BEL "CPU_Din_2" BEL
"CPU_Din_3" BEL "CPU_Din_4" BEL "CPU_Din_5" BEL "CPU_Din_6" BEL
"CPU_Din_7" BEL "SDRAM_ADD_2" BEL "Dbit_0" BEL "SDRAM_ADD_3" BEL
"Dbit_2" BEL "SDRAM_ADD_4" BEL "counter_0" BEL "counter_1" BEL
"counter_2" BEL "counter_3" BEL "counter_4" BEL "counter_5" BEL
"counter_6" BEL "counter_7" BEL "counter_8" BEL "counter_9" BEL
"counter_10" BEL "counter_11" BEL "counter_12" BEL "counter_13" BEL
"counter_14" BEL "counter_15" BEL "counter_16" BEL "counter_17" BEL
"counter_18" BEL "counter_19" BEL "counter_20" BEL "counter_21" BEL
"counter_22" BEL "counter_23" BEL "counter_24" BEL "counter_25" BEL
"counter_26" BEL "counter_27" BEL "counter_28" BEL "counter_29" BEL
"counter_30" BEL "counter_31" BEL "sdoffset_0" BEL "sdoffset_1" BEL
"sdoffset_2" BEL "sdoffset_3" BEL "sdoffset_4" BEL "SDRAM_W_R" BEL
"index_1" BEL "cpu_tag_0" BEL "cpu_tag_1" BEL "cpu_tag_2" BEL
"SDRAM_Din_0" BEL "SDRAM_Din_1" BEL "SDRAM_Din_2" BEL "SDRAM_Din_3"
BEL "SDRAM_Din_4" BEL "SDRAM_Din_5" BEL "SDRAM_Din_6" BEL
"SDRAM_Din_7" BEL "Mram_memtag2.SLICEM_F" BEL "Mram_memtag2.SLICEM_G"
BEL "Mram_memtag1.SLICEM_F" BEL "Mram_memtag1.SLICEM_G" BEL
"Mram_memtag3.SLICEM_F" BEL "Mram_memtag3.SLICEM_G" BEL
"Mram_memtag4.SLICEM_F" BEL "Mram_memtag4.SLICEM_G" PIN
"mySRAM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram.A_pins<10>"
PIN
"mySRAM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram.B_pins<10>"
BEL "myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1" BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR"
BEL
"myILA/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR"
BEL "myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL2" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL3" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_CR" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[8].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[7].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[6].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[5].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[4].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[3].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[2].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[1].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/G_NS[0].U_NSQ" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_STATE1" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_STATE0" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_ARM" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_TRIGGER" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_FULL" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_ECR" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_RISING" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL1/U_RFDRE" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL1/U_DOUT" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL1/U_DOUT1" BEL
"myILA/U0/I_YES_D.U_ILA/U_STAT/U_DSL1/U_DOUT0" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_POR" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[0].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[1].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[2].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[3].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[4].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[5].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[6].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/G_RST[7].U_RST" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1" BEL
"myILA/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0" BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_SRL16.U_GANDX_SRL16/I_YES_IREG.F_TW[0].U_IREG"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_SRL16.U_GANDX_SRL16/F_TW[0].U_TREG"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_SRL16.U_GANDX_SRL16/I_TWMOD4_NE0.I_YES_RPM.I_OREG.U_OREG"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[28].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[29].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[30].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[31].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[32].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[33].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[34].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[35].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[36].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[37].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[38].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[39].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[40].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[41].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[42].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[43].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[44].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[45].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[46].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[47].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[48].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[49].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[50].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[51].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[52].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[53].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[54].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[55].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[56].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[57].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[58].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[59].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[60].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[61].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[62].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[63].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[64].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[65].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[66].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[67].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[68].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[69].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[70].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[71].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[72].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[73].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[74].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[75].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[76].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[77].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[78].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[79].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[80].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[81].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[82].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[83].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[84].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[85].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[86].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[87].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[88].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[89].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[90].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[91].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[92].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[93].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[94].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[95].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[96].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[97].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[98].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[99].I_SRLT_NE_0.FF"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[28].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[29].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[30].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[31].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[32].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[33].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[34].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[35].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[36].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[37].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[38].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[39].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[40].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[41].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[42].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[43].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[44].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[45].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[46].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[47].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[48].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[49].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[50].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[51].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[52].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[53].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[54].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[55].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[56].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[57].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[58].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[59].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[60].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[61].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[62].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[63].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[64].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[65].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[66].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[67].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[68].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[69].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[70].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[71].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[72].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[73].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[74].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[75].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[76].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[77].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[78].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[79].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[80].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[81].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[82].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[83].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[84].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[85].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[86].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[87].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[88].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[89].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[90].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[91].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[92].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[93].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[94].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[95].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[96].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[97].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[98].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[99].I_SRLT_NE_0.DLY9/SRL16E"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG"
BEL "myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY" BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT"
BEL
"myILA/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ"
BEL "myILA/U0/I_YES_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR" BEL
"myILA/U0/I_DQ.G_DW[99].U_DQ" BEL "myILA/U0/I_DQ.G_DW[98].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[97].U_DQ" BEL "myILA/U0/I_DQ.G_DW[96].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[95].U_DQ" BEL "myILA/U0/I_DQ.G_DW[94].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[93].U_DQ" BEL "myILA/U0/I_DQ.G_DW[92].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[91].U_DQ" BEL "myILA/U0/I_DQ.G_DW[90].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[89].U_DQ" BEL "myILA/U0/I_DQ.G_DW[88].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[87].U_DQ" BEL "myILA/U0/I_DQ.G_DW[86].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[85].U_DQ" BEL "myILA/U0/I_DQ.G_DW[84].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[83].U_DQ" BEL "myILA/U0/I_DQ.G_DW[82].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[81].U_DQ" BEL "myILA/U0/I_DQ.G_DW[80].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[79].U_DQ" BEL "myILA/U0/I_DQ.G_DW[78].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[77].U_DQ" BEL "myILA/U0/I_DQ.G_DW[76].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[75].U_DQ" BEL "myILA/U0/I_DQ.G_DW[74].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[73].U_DQ" BEL "myILA/U0/I_DQ.G_DW[72].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[71].U_DQ" BEL "myILA/U0/I_DQ.G_DW[70].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[69].U_DQ" BEL "myILA/U0/I_DQ.G_DW[68].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[67].U_DQ" BEL "myILA/U0/I_DQ.G_DW[66].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[65].U_DQ" BEL "myILA/U0/I_DQ.G_DW[64].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[63].U_DQ" BEL "myILA/U0/I_DQ.G_DW[62].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[61].U_DQ" BEL "myILA/U0/I_DQ.G_DW[60].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[59].U_DQ" BEL "myILA/U0/I_DQ.G_DW[58].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[57].U_DQ" BEL "myILA/U0/I_DQ.G_DW[56].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[55].U_DQ" BEL "myILA/U0/I_DQ.G_DW[54].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[53].U_DQ" BEL "myILA/U0/I_DQ.G_DW[52].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[51].U_DQ" BEL "myILA/U0/I_DQ.G_DW[50].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[49].U_DQ" BEL "myILA/U0/I_DQ.G_DW[48].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[47].U_DQ" BEL "myILA/U0/I_DQ.G_DW[46].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[45].U_DQ" BEL "myILA/U0/I_DQ.G_DW[44].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[43].U_DQ" BEL "myILA/U0/I_DQ.G_DW[42].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[41].U_DQ" BEL "myILA/U0/I_DQ.G_DW[40].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[39].U_DQ" BEL "myILA/U0/I_DQ.G_DW[38].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[37].U_DQ" BEL "myILA/U0/I_DQ.G_DW[36].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[35].U_DQ" BEL "myILA/U0/I_DQ.G_DW[34].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[33].U_DQ" BEL "myILA/U0/I_DQ.G_DW[32].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[31].U_DQ" BEL "myILA/U0/I_DQ.G_DW[30].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[29].U_DQ" BEL "myILA/U0/I_DQ.G_DW[28].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[27].U_DQ" BEL "myILA/U0/I_DQ.G_DW[26].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[25].U_DQ" BEL "myILA/U0/I_DQ.G_DW[24].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[23].U_DQ" BEL "myILA/U0/I_DQ.G_DW[22].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[21].U_DQ" BEL "myILA/U0/I_DQ.G_DW[20].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[19].U_DQ" BEL "myILA/U0/I_DQ.G_DW[18].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[17].U_DQ" BEL "myILA/U0/I_DQ.G_DW[16].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[15].U_DQ" BEL "myILA/U0/I_DQ.G_DW[14].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[13].U_DQ" BEL "myILA/U0/I_DQ.G_DW[12].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[11].U_DQ" BEL "myILA/U0/I_DQ.G_DW[10].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[9].U_DQ" BEL "myILA/U0/I_DQ.G_DW[8].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[7].U_DQ" BEL "myILA/U0/I_DQ.G_DW[6].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[5].U_DQ" BEL "myILA/U0/I_DQ.G_DW[4].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[3].U_DQ" BEL "myILA/U0/I_DQ.G_DW[2].U_DQ" BEL
"myILA/U0/I_DQ.G_DW[1].U_DQ" BEL "myILA/U0/I_DQ.G_DW[0].U_DQ" BEL
"myILA/U0/I_TQ0.G_TW[0].U_TQ" PIN
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>"
PIN
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>"
PIN
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>"
PIN
"myILA/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[3].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i.B_pins<10>"
BEL "state_FSM_FFd1" BEL "state_FSM_FFd4" BEL "state_FSM_FFd6" BEL
"myCPU_gen/st1_FSM_FFd1" BEL "myCPU_gen/st1_FSM_FFd2" BEL
"myCPU_gen/st1_FSM_FFd3" BEL "myCPU_gen/st1_FSM_FFd4" BEL
"myCPU_gen/patCtrl_2" BEL "myCPU_gen/patCtrl_1" BEL
"myCPU_gen/patCtrl_0" BEL "myCPU_gen/rReg2" BEL "myCPU_gen/rReg1" BEL
"SDRAM/DOUT_7" BEL "SDRAM/DOUT_6" BEL "SDRAM/DOUT_5" BEL
"SDRAM/DOUT_4" BEL "SDRAM/DOUT_3" BEL "SDRAM/DOUT_2" BEL
"SDRAM/DOUT_1" BEL "SDRAM/DOUT_0" BEL "SDRAM/RAM_SIG<0>_10_7" BEL
"SDRAM/RAM_SIG<0>_10_6" BEL "SDRAM/RAM_SIG<0>_10_5" BEL
"SDRAM/RAM_SIG<0>_10_4" BEL "SDRAM/RAM_SIG<0>_10_3" BEL
"SDRAM/RAM_SIG<0>_10_2" BEL "SDRAM/RAM_SIG<0>_10_1" BEL
"SDRAM/RAM_SIG<0>_10_0" BEL "SDRAM/RAM_SIG<2>_9_7" BEL
"SDRAM/RAM_SIG<2>_9_6" BEL "SDRAM/RAM_SIG<2>_9_5" BEL
"SDRAM/RAM_SIG<2>_9_4" BEL "SDRAM/RAM_SIG<2>_9_3" BEL
"SDRAM/RAM_SIG<2>_9_2" BEL "SDRAM/RAM_SIG<2>_9_1" BEL
"SDRAM/RAM_SIG<2>_9_0" BEL "SDRAM/RAM_SIG<2>_8_7" BEL
"SDRAM/RAM_SIG<2>_8_6" BEL "SDRAM/RAM_SIG<2>_8_5" BEL
"SDRAM/RAM_SIG<2>_8_4" BEL "SDRAM/RAM_SIG<2>_8_3" BEL
"SDRAM/RAM_SIG<2>_8_2" BEL "SDRAM/RAM_SIG<2>_8_1" BEL
"SDRAM/RAM_SIG<2>_8_0" BEL "SDRAM/RAM_SIG<2>_7_7" BEL
"SDRAM/RAM_SIG<2>_7_6" BEL "SDRAM/RAM_SIG<2>_7_5" BEL
"SDRAM/RAM_SIG<2>_7_4" BEL "SDRAM/RAM_SIG<2>_7_3" BEL
"SDRAM/RAM_SIG<2>_7_2" BEL "SDRAM/RAM_SIG<2>_7_1" BEL
"SDRAM/RAM_SIG<2>_7_0" BEL "SDRAM/RAM_SIG<2>_6_7" BEL
"SDRAM/RAM_SIG<2>_6_6" BEL "SDRAM/RAM_SIG<2>_6_5" BEL
"SDRAM/RAM_SIG<2>_6_4" BEL "SDRAM/RAM_SIG<2>_6_3" BEL
"SDRAM/RAM_SIG<2>_6_2" BEL "SDRAM/RAM_SIG<2>_6_1" BEL
"SDRAM/RAM_SIG<2>_6_0" BEL "SDRAM/RAM_SIG<2>_5_7" BEL
"SDRAM/RAM_SIG<2>_5_6" BEL "SDRAM/RAM_SIG<2>_5_5" BEL
"SDRAM/RAM_SIG<2>_5_4" BEL "SDRAM/RAM_SIG<2>_5_3" BEL
"SDRAM/RAM_SIG<2>_5_2" BEL "SDRAM/RAM_SIG<2>_5_1" BEL
"SDRAM/RAM_SIG<2>_5_0" BEL "SDRAM/RAM_SIG<2>_4_7" BEL
"SDRAM/RAM_SIG<2>_4_6" BEL "SDRAM/RAM_SIG<2>_4_5" BEL
"SDRAM/RAM_SIG<2>_4_4" BEL "SDRAM/RAM_SIG<2>_4_3" BEL
"SDRAM/RAM_SIG<2>_4_2" BEL "SDRAM/RAM_SIG<2>_4_1" BEL
"SDRAM/RAM_SIG<2>_4_0" BEL "SDRAM/RAM_SIG<2>_3_7" BEL
"SDRAM/RAM_SIG<2>_3_6" BEL "SDRAM/RAM_SIG<2>_3_5" BEL
"SDRAM/RAM_SIG<2>_3_4" BEL "SDRAM/RAM_SIG<2>_3_3" BEL
"SDRAM/RAM_SIG<2>_3_2" BEL "SDRAM/RAM_SIG<2>_3_1" BEL
"SDRAM/RAM_SIG<2>_3_0" BEL "SDRAM/RAM_SIG<2>_1_7" BEL
"SDRAM/RAM_SIG<2>_1_6" BEL "SDRAM/RAM_SIG<2>_1_5" BEL
"SDRAM/RAM_SIG<2>_1_4" BEL "SDRAM/RAM_SIG<2>_1_3" BEL
"SDRAM/RAM_SIG<2>_1_2" BEL "SDRAM/RAM_SIG<2>_1_1" BEL
"SDRAM/RAM_SIG<2>_1_0" BEL "SDRAM/RAM_SIG<2>_0_7" BEL
"SDRAM/RAM_SIG<2>_0_6" BEL "SDRAM/RAM_SIG<2>_0_5" BEL
"SDRAM/RAM_SIG<2>_0_4" BEL "SDRAM/RAM_SIG<2>_0_3" BEL
"SDRAM/RAM_SIG<2>_0_2" BEL "SDRAM/RAM_SIG<2>_0_1" BEL
"SDRAM/RAM_SIG<2>_0_0" BEL "SDRAM/RAM_SIG<2>_2_7" BEL
"SDRAM/RAM_SIG<2>_2_6" BEL "SDRAM/RAM_SIG<2>_2_5" BEL
"SDRAM/RAM_SIG<2>_2_4" BEL "SDRAM/RAM_SIG<2>_2_3" BEL
"SDRAM/RAM_SIG<2>_2_2" BEL "SDRAM/RAM_SIG<2>_2_1" BEL
"SDRAM/RAM_SIG<2>_2_0" BEL "SDRAM/RAM_SIG<0>_9_7" BEL
"SDRAM/RAM_SIG<0>_9_6" BEL "SDRAM/RAM_SIG<0>_9_5" BEL
"SDRAM/RAM_SIG<0>_9_4" BEL "SDRAM/RAM_SIG<0>_9_3" BEL
"SDRAM/RAM_SIG<0>_9_2" BEL "SDRAM/RAM_SIG<0>_9_1" BEL
"SDRAM/RAM_SIG<0>_9_0" BEL "SDRAM/RAM_SIG<0>_8_7" BEL
"SDRAM/RAM_SIG<0>_8_6" BEL "SDRAM/RAM_SIG<0>_8_5" BEL
"SDRAM/RAM_SIG<0>_8_4" BEL "SDRAM/RAM_SIG<0>_8_3" BEL
"SDRAM/RAM_SIG<0>_8_2" BEL "SDRAM/RAM_SIG<0>_8_1" BEL
"SDRAM/RAM_SIG<0>_8_0" BEL "SDRAM/RAM_SIG<0>_7_7" BEL
"SDRAM/RAM_SIG<0>_7_6" BEL "SDRAM/RAM_SIG<0>_7_5" BEL
"SDRAM/RAM_SIG<0>_7_4" BEL "SDRAM/RAM_SIG<0>_7_3" BEL
"SDRAM/RAM_SIG<0>_7_2" BEL "SDRAM/RAM_SIG<0>_7_1" BEL
"SDRAM/RAM_SIG<0>_7_0" BEL "SDRAM/RAM_SIG<0>_6_7" BEL
"SDRAM/RAM_SIG<0>_6_6" BEL "SDRAM/RAM_SIG<0>_6_5" BEL
"SDRAM/RAM_SIG<0>_6_4" BEL "SDRAM/RAM_SIG<0>_6_3" BEL
"SDRAM/RAM_SIG<0>_6_2" BEL "SDRAM/RAM_SIG<0>_6_1" BEL
"SDRAM/RAM_SIG<0>_6_0" BEL "SDRAM/RAM_SIG<0>_5_7" BEL
"SDRAM/RAM_SIG<0>_5_6" BEL "SDRAM/RAM_SIG<0>_5_5" BEL
"SDRAM/RAM_SIG<0>_5_4" BEL "SDRAM/RAM_SIG<0>_5_3" BEL
"SDRAM/RAM_SIG<0>_5_2" BEL "SDRAM/RAM_SIG<0>_5_1" BEL
"SDRAM/RAM_SIG<0>_5_0" BEL "SDRAM/RAM_SIG<0>_4_7" BEL
"SDRAM/RAM_SIG<0>_4_6" BEL "SDRAM/RAM_SIG<0>_4_5" BEL
"SDRAM/RAM_SIG<0>_4_4" BEL "SDRAM/RAM_SIG<0>_4_3" BEL
"SDRAM/RAM_SIG<0>_4_2" BEL "SDRAM/RAM_SIG<0>_4_1" BEL
"SDRAM/RAM_SIG<0>_4_0" BEL "SDRAM/RAM_SIG<0>_2_7" BEL
"SDRAM/RAM_SIG<0>_2_6" BEL "SDRAM/RAM_SIG<0>_2_5" BEL
"SDRAM/RAM_SIG<0>_2_4" BEL "SDRAM/RAM_SIG<0>_2_3" BEL
"SDRAM/RAM_SIG<0>_2_2" BEL "SDRAM/RAM_SIG<0>_2_1" BEL
"SDRAM/RAM_SIG<0>_2_0" BEL "SDRAM/RAM_SIG<0>_3_7" BEL
"SDRAM/RAM_SIG<0>_3_6" BEL "SDRAM/RAM_SIG<0>_3_5" BEL
"SDRAM/RAM_SIG<0>_3_4" BEL "SDRAM/RAM_SIG<0>_3_3" BEL
"SDRAM/RAM_SIG<0>_3_2" BEL "SDRAM/RAM_SIG<0>_3_1" BEL
"SDRAM/RAM_SIG<0>_3_0" BEL "SDRAM/counter_0" BEL
"SDRAM/RAM_SIG<0>_1_7" BEL "SDRAM/RAM_SIG<0>_1_6" BEL
"SDRAM/RAM_SIG<0>_1_5" BEL "SDRAM/RAM_SIG<0>_1_4" BEL
"SDRAM/RAM_SIG<0>_1_3" BEL "SDRAM/RAM_SIG<0>_1_2" BEL
"SDRAM/RAM_SIG<0>_1_1" BEL "SDRAM/RAM_SIG<0>_1_0" BEL
"SDRAM/RAM_SIG<0>_0_7" BEL "SDRAM/RAM_SIG<0>_0_6" BEL
"SDRAM/RAM_SIG<0>_0_5" BEL "SDRAM/RAM_SIG<0>_0_4" BEL
"SDRAM/RAM_SIG<0>_0_3" BEL "SDRAM/RAM_SIG<0>_0_2" BEL
"SDRAM/RAM_SIG<0>_0_1" BEL "SDRAM/RAM_SIG<0>_0_0" BEL
"SDRAM/RAM_SIG<2>_29_7" BEL "SDRAM/RAM_SIG<2>_29_6" BEL
"SDRAM/RAM_SIG<2>_29_5" BEL "SDRAM/RAM_SIG<2>_29_4" BEL
"SDRAM/RAM_SIG<2>_29_3" BEL "SDRAM/RAM_SIG<2>_29_2" BEL
"SDRAM/RAM_SIG<2>_29_1" BEL "SDRAM/RAM_SIG<2>_29_0" BEL
"SDRAM/RAM_SIG<2>_28_7" BEL "SDRAM/RAM_SIG<2>_28_6" BEL
"SDRAM/RAM_SIG<2>_28_5" BEL "SDRAM/RAM_SIG<2>_28_4" BEL
"SDRAM/RAM_SIG<2>_28_3" BEL "SDRAM/RAM_SIG<2>_28_2" BEL
"SDRAM/RAM_SIG<2>_28_1" BEL "SDRAM/RAM_SIG<2>_28_0" BEL
"SDRAM/RAM_SIG<2>_27_7" BEL "SDRAM/RAM_SIG<2>_27_6" BEL
"SDRAM/RAM_SIG<2>_27_5" BEL "SDRAM/RAM_SIG<2>_27_4" BEL
"SDRAM/RAM_SIG<2>_27_3" BEL "SDRAM/RAM_SIG<2>_27_2" BEL
"SDRAM/RAM_SIG<2>_27_1" BEL "SDRAM/RAM_SIG<2>_27_0" BEL
"SDRAM/RAM_SIG<2>_26_7" BEL "SDRAM/RAM_SIG<2>_26_6" BEL
"SDRAM/RAM_SIG<2>_26_5" BEL "SDRAM/RAM_SIG<2>_26_4" BEL
"SDRAM/RAM_SIG<2>_26_3" BEL "SDRAM/RAM_SIG<2>_26_2" BEL
"SDRAM/RAM_SIG<2>_26_1" BEL "SDRAM/RAM_SIG<2>_26_0" BEL
"SDRAM/RAM_SIG<2>_31_7" BEL "SDRAM/RAM_SIG<2>_31_6" BEL
"SDRAM/RAM_SIG<2>_31_5" BEL "SDRAM/RAM_SIG<2>_31_4" BEL
"SDRAM/RAM_SIG<2>_31_3" BEL "SDRAM/RAM_SIG<2>_31_2" BEL
"SDRAM/RAM_SIG<2>_31_1" BEL "SDRAM/RAM_SIG<2>_31_0" BEL
"SDRAM/RAM_SIG<2>_25_7" BEL "SDRAM/RAM_SIG<2>_25_6" BEL
"SDRAM/RAM_SIG<2>_25_5" BEL "SDRAM/RAM_SIG<2>_25_4" BEL
"SDRAM/RAM_SIG<2>_25_3" BEL "SDRAM/RAM_SIG<2>_25_2" BEL
"SDRAM/RAM_SIG<2>_25_1" BEL "SDRAM/RAM_SIG<2>_25_0" BEL
"SDRAM/RAM_SIG<2>_30_7" BEL "SDRAM/RAM_SIG<2>_30_6" BEL
"SDRAM/RAM_SIG<2>_30_5" BEL "SDRAM/RAM_SIG<2>_30_4" BEL
"SDRAM/RAM_SIG<2>_30_3" BEL "SDRAM/RAM_SIG<2>_30_2" BEL
"SDRAM/RAM_SIG<2>_30_1" BEL "SDRAM/RAM_SIG<2>_30_0" BEL
"SDRAM/RAM_SIG<2>_19_7" BEL "SDRAM/RAM_SIG<2>_19_6" BEL
"SDRAM/RAM_SIG<2>_19_5" BEL "SDRAM/RAM_SIG<2>_19_4" BEL
"SDRAM/RAM_SIG<2>_19_3" BEL "SDRAM/RAM_SIG<2>_19_2" BEL
"SDRAM/RAM_SIG<2>_19_1" BEL "SDRAM/RAM_SIG<2>_19_0" BEL
"SDRAM/RAM_SIG<2>_24_7" BEL "SDRAM/RAM_SIG<2>_24_6" BEL
"SDRAM/RAM_SIG<2>_24_5" BEL "SDRAM/RAM_SIG<2>_24_4" BEL
"SDRAM/RAM_SIG<2>_24_3" BEL "SDRAM/RAM_SIG<2>_24_2" BEL
"SDRAM/RAM_SIG<2>_24_1" BEL "SDRAM/RAM_SIG<2>_24_0" BEL
"SDRAM/RAM_SIG<0>_29_7" BEL "SDRAM/RAM_SIG<0>_29_6" BEL
"SDRAM/RAM_SIG<0>_29_5" BEL "SDRAM/RAM_SIG<0>_29_4" BEL
"SDRAM/RAM_SIG<0>_29_3" BEL "SDRAM/RAM_SIG<0>_29_2" BEL
"SDRAM/RAM_SIG<0>_29_1" BEL "SDRAM/RAM_SIG<0>_29_0" BEL
"SDRAM/RAM_SIG<2>_18_7" BEL "SDRAM/RAM_SIG<2>_18_6" BEL
"SDRAM/RAM_SIG<2>_18_5" BEL "SDRAM/RAM_SIG<2>_18_4" BEL
"SDRAM/RAM_SIG<2>_18_3" BEL "SDRAM/RAM_SIG<2>_18_2" BEL
"SDRAM/RAM_SIG<2>_18_1" BEL "SDRAM/RAM_SIG<2>_18_0" BEL
"SDRAM/RAM_SIG<2>_23_7" BEL "SDRAM/RAM_SIG<2>_23_6" BEL
"SDRAM/RAM_SIG<2>_23_5" BEL "SDRAM/RAM_SIG<2>_23_4" BEL
"SDRAM/RAM_SIG<2>_23_3" BEL "SDRAM/RAM_SIG<2>_23_2" BEL
"SDRAM/RAM_SIG<2>_23_1" BEL "SDRAM/RAM_SIG<2>_23_0" BEL
"SDRAM/RAM_SIG<0>_28_7" BEL "SDRAM/RAM_SIG<0>_28_6" BEL
"SDRAM/RAM_SIG<0>_28_5" BEL "SDRAM/RAM_SIG<0>_28_4" BEL
"SDRAM/RAM_SIG<0>_28_3" BEL "SDRAM/RAM_SIG<0>_28_2" BEL
"SDRAM/RAM_SIG<0>_28_1" BEL "SDRAM/RAM_SIG<0>_28_0" BEL
"SDRAM/RAM_SIG<2>_17_7" BEL "SDRAM/RAM_SIG<2>_17_6" BEL
"SDRAM/RAM_SIG<2>_17_5" BEL "SDRAM/RAM_SIG<2>_17_4" BEL
"SDRAM/RAM_SIG<2>_17_3" BEL "SDRAM/RAM_SIG<2>_17_2" BEL
"SDRAM/RAM_SIG<2>_17_1" BEL "SDRAM/RAM_SIG<2>_17_0" BEL
"SDRAM/RAM_SIG<2>_22_7" BEL "SDRAM/RAM_SIG<2>_22_6" BEL
"SDRAM/RAM_SIG<2>_22_5" BEL "SDRAM/RAM_SIG<2>_22_4" BEL
"SDRAM/RAM_SIG<2>_22_3" BEL "SDRAM/RAM_SIG<2>_22_2" BEL
"SDRAM/RAM_SIG<2>_22_1" BEL "SDRAM/RAM_SIG<2>_22_0" BEL
"SDRAM/RAM_SIG<0>_27_7" BEL "SDRAM/RAM_SIG<0>_27_6" BEL
"SDRAM/RAM_SIG<0>_27_5" BEL "SDRAM/RAM_SIG<0>_27_4" BEL
"SDRAM/RAM_SIG<0>_27_3" BEL "SDRAM/RAM_SIG<0>_27_2" BEL
"SDRAM/RAM_SIG<0>_27_1" BEL "SDRAM/RAM_SIG<0>_27_0" BEL
"SDRAM/RAM_SIG<2>_16_7" BEL "SDRAM/RAM_SIG<2>_16_6" BEL
"SDRAM/RAM_SIG<2>_16_5" BEL "SDRAM/RAM_SIG<2>_16_4" BEL
"SDRAM/RAM_SIG<2>_16_3" BEL "SDRAM/RAM_SIG<2>_16_2" BEL
"SDRAM/RAM_SIG<2>_16_1" BEL "SDRAM/RAM_SIG<2>_16_0" BEL
"SDRAM/RAM_SIG<2>_21_7" BEL "SDRAM/RAM_SIG<2>_21_6" BEL
"SDRAM/RAM_SIG<2>_21_5" BEL "SDRAM/RAM_SIG<2>_21_4" BEL
"SDRAM/RAM_SIG<2>_21_3" BEL "SDRAM/RAM_SIG<2>_21_2" BEL
"SDRAM/RAM_SIG<2>_21_1" BEL "SDRAM/RAM_SIG<2>_21_0" BEL
"SDRAM/RAM_SIG<0>_26_7" BEL "SDRAM/RAM_SIG<0>_26_6" BEL
"SDRAM/RAM_SIG<0>_26_5" BEL "SDRAM/RAM_SIG<0>_26_4" BEL
"SDRAM/RAM_SIG<0>_26_3" BEL "SDRAM/RAM_SIG<0>_26_2" BEL
"SDRAM/RAM_SIG<0>_26_1" BEL "SDRAM/RAM_SIG<0>_26_0" BEL
"SDRAM/RAM_SIG<0>_31_7" BEL "SDRAM/RAM_SIG<0>_31_6" BEL
"SDRAM/RAM_SIG<0>_31_5" BEL "SDRAM/RAM_SIG<0>_31_4" BEL
"SDRAM/RAM_SIG<0>_31_3" BEL "SDRAM/RAM_SIG<0>_31_2" BEL
"SDRAM/RAM_SIG<0>_31_1" BEL "SDRAM/RAM_SIG<0>_31_0" BEL
"SDRAM/RAM_SIG<2>_15_7" BEL "SDRAM/RAM_SIG<2>_15_6" BEL
"SDRAM/RAM_SIG<2>_15_5" BEL "SDRAM/RAM_SIG<2>_15_4" BEL
"SDRAM/RAM_SIG<2>_15_3" BEL "SDRAM/RAM_SIG<2>_15_2" BEL
"SDRAM/RAM_SIG<2>_15_1" BEL "SDRAM/RAM_SIG<2>_15_0" BEL
"SDRAM/RAM_SIG<2>_20_7" BEL "SDRAM/RAM_SIG<2>_20_6" BEL
"SDRAM/RAM_SIG<2>_20_5" BEL "SDRAM/RAM_SIG<2>_20_4" BEL
"SDRAM/RAM_SIG<2>_20_3" BEL "SDRAM/RAM_SIG<2>_20_2" BEL
"SDRAM/RAM_SIG<2>_20_1" BEL "SDRAM/RAM_SIG<2>_20_0" BEL
"SDRAM/RAM_SIG<0>_25_7" BEL "SDRAM/RAM_SIG<0>_25_6" BEL
"SDRAM/RAM_SIG<0>_25_5" BEL "SDRAM/RAM_SIG<0>_25_4" BEL
"SDRAM/RAM_SIG<0>_25_3" BEL "SDRAM/RAM_SIG<0>_25_2" BEL
"SDRAM/RAM_SIG<0>_25_1" BEL "SDRAM/RAM_SIG<0>_25_0" BEL
"SDRAM/RAM_SIG<0>_30_7" BEL "SDRAM/RAM_SIG<0>_30_6" BEL
"SDRAM/RAM_SIG<0>_30_5" BEL "SDRAM/RAM_SIG<0>_30_4" BEL
"SDRAM/RAM_SIG<0>_30_3" BEL "SDRAM/RAM_SIG<0>_30_2" BEL
"SDRAM/RAM_SIG<0>_30_1" BEL "SDRAM/RAM_SIG<0>_30_0" BEL
"SDRAM/RAM_SIG<2>_14_7" BEL "SDRAM/RAM_SIG<2>_14_6" BEL
"SDRAM/RAM_SIG<2>_14_5" BEL "SDRAM/RAM_SIG<2>_14_4" BEL
"SDRAM/RAM_SIG<2>_14_3" BEL "SDRAM/RAM_SIG<2>_14_2" BEL
"SDRAM/RAM_SIG<2>_14_1" BEL "SDRAM/RAM_SIG<2>_14_0" BEL
"SDRAM/RAM_SIG<0>_19_7" BEL "SDRAM/RAM_SIG<0>_19_6" BEL
"SDRAM/RAM_SIG<0>_19_5" BEL "SDRAM/RAM_SIG<0>_19_4" BEL
"SDRAM/RAM_SIG<0>_19_3" BEL "SDRAM/RAM_SIG<0>_19_2" BEL
"SDRAM/RAM_SIG<0>_19_1" BEL "SDRAM/RAM_SIG<0>_19_0" BEL
"SDRAM/RAM_SIG<0>_24_7" BEL "SDRAM/RAM_SIG<0>_24_6" BEL
"SDRAM/RAM_SIG<0>_24_5" BEL "SDRAM/RAM_SIG<0>_24_4" BEL
"SDRAM/RAM_SIG<0>_24_3" BEL "SDRAM/RAM_SIG<0>_24_2" BEL
"SDRAM/RAM_SIG<0>_24_1" BEL "SDRAM/RAM_SIG<0>_24_0" BEL
"SDRAM/RAM_SIG<2>_13_7" BEL "SDRAM/RAM_SIG<2>_13_6" BEL
"SDRAM/RAM_SIG<2>_13_5" BEL "SDRAM/RAM_SIG<2>_13_4" BEL
"SDRAM/RAM_SIG<2>_13_3" BEL "SDRAM/RAM_SIG<2>_13_2" BEL
"SDRAM/RAM_SIG<2>_13_1" BEL "SDRAM/RAM_SIG<2>_13_0" BEL
"SDRAM/RAM_SIG<0>_18_7" BEL "SDRAM/RAM_SIG<0>_18_6" BEL
"SDRAM/RAM_SIG<0>_18_5" BEL "SDRAM/RAM_SIG<0>_18_4" BEL
"SDRAM/RAM_SIG<0>_18_3" BEL "SDRAM/RAM_SIG<0>_18_2" BEL
"SDRAM/RAM_SIG<0>_18_1" BEL "SDRAM/RAM_SIG<0>_18_0" BEL
"SDRAM/RAM_SIG<0>_23_7" BEL "SDRAM/RAM_SIG<0>_23_6" BEL
"SDRAM/RAM_SIG<0>_23_5" BEL "SDRAM/RAM_SIG<0>_23_4" BEL
"SDRAM/RAM_SIG<0>_23_3" BEL "SDRAM/RAM_SIG<0>_23_2" BEL
"SDRAM/RAM_SIG<0>_23_1" BEL "SDRAM/RAM_SIG<0>_23_0" BEL
"SDRAM/RAM_SIG<0>_17_7" BEL "SDRAM/RAM_SIG<0>_17_6" BEL
"SDRAM/RAM_SIG<0>_17_5" BEL "SDRAM/RAM_SIG<0>_17_4" BEL
"SDRAM/RAM_SIG<0>_17_3" BEL "SDRAM/RAM_SIG<0>_17_2" BEL
"SDRAM/RAM_SIG<0>_17_1" BEL "SDRAM/RAM_SIG<0>_17_0" BEL
"SDRAM/RAM_SIG<0>_22_7" BEL "SDRAM/RAM_SIG<0>_22_6" BEL
"SDRAM/RAM_SIG<0>_22_5" BEL "SDRAM/RAM_SIG<0>_22_4" BEL
"SDRAM/RAM_SIG<0>_22_3" BEL "SDRAM/RAM_SIG<0>_22_2" BEL
"SDRAM/RAM_SIG<0>_22_1" BEL "SDRAM/RAM_SIG<0>_22_0" BEL
"SDRAM/RAM_SIG<2>_12_7" BEL "SDRAM/RAM_SIG<2>_12_6" BEL
"SDRAM/RAM_SIG<2>_12_5" BEL "SDRAM/RAM_SIG<2>_12_4" BEL
"SDRAM/RAM_SIG<2>_12_3" BEL "SDRAM/RAM_SIG<2>_12_2" BEL
"SDRAM/RAM_SIG<2>_12_1" BEL "SDRAM/RAM_SIG<2>_12_0" BEL
"SDRAM/RAM_SIG<2>_11_7" BEL "SDRAM/RAM_SIG<2>_11_6" BEL
"SDRAM/RAM_SIG<2>_11_5" BEL "SDRAM/RAM_SIG<2>_11_4" BEL
"SDRAM/RAM_SIG<2>_11_3" BEL "SDRAM/RAM_SIG<2>_11_2" BEL
"SDRAM/RAM_SIG<2>_11_1" BEL "SDRAM/RAM_SIG<2>_11_0" BEL
"SDRAM/RAM_SIG<0>_16_7" BEL "SDRAM/RAM_SIG<0>_16_6" BEL
"SDRAM/RAM_SIG<0>_16_5" BEL "SDRAM/RAM_SIG<0>_16_4" BEL
"SDRAM/RAM_SIG<0>_16_3" BEL "SDRAM/RAM_SIG<0>_16_2" BEL
"SDRAM/RAM_SIG<0>_16_1" BEL "SDRAM/RAM_SIG<0>_16_0" BEL
"SDRAM/RAM_SIG<0>_21_7" BEL "SDRAM/RAM_SIG<0>_21_6" BEL
"SDRAM/RAM_SIG<0>_21_5" BEL "SDRAM/RAM_SIG<0>_21_4" BEL
"SDRAM/RAM_SIG<0>_21_3" BEL "SDRAM/RAM_SIG<0>_21_2" BEL
"SDRAM/RAM_SIG<0>_21_1" BEL "SDRAM/RAM_SIG<0>_21_0" BEL
"SDRAM/RAM_SIG<2>_10_7" BEL "SDRAM/RAM_SIG<2>_10_6" BEL
"SDRAM/RAM_SIG<2>_10_5" BEL "SDRAM/RAM_SIG<2>_10_4" BEL
"SDRAM/RAM_SIG<2>_10_3" BEL "SDRAM/RAM_SIG<2>_10_2" BEL
"SDRAM/RAM_SIG<2>_10_1" BEL "SDRAM/RAM_SIG<2>_10_0" BEL
"SDRAM/RAM_SIG<0>_15_7" BEL "SDRAM/RAM_SIG<0>_15_6" BEL
"SDRAM/RAM_SIG<0>_15_5" BEL "SDRAM/RAM_SIG<0>_15_4" BEL
"SDRAM/RAM_SIG<0>_15_3" BEL "SDRAM/RAM_SIG<0>_15_2" BEL
"SDRAM/RAM_SIG<0>_15_1" BEL "SDRAM/RAM_SIG<0>_15_0" BEL
"SDRAM/RAM_SIG<0>_20_7" BEL "SDRAM/RAM_SIG<0>_20_6" BEL
"SDRAM/RAM_SIG<0>_20_5" BEL "SDRAM/RAM_SIG<0>_20_4" BEL
"SDRAM/RAM_SIG<0>_20_3" BEL "SDRAM/RAM_SIG<0>_20_2" BEL
"SDRAM/RAM_SIG<0>_20_1" BEL "SDRAM/RAM_SIG<0>_20_0" BEL
"SDRAM/RAM_SIG<0>_14_7" BEL "SDRAM/RAM_SIG<0>_14_6" BEL
"SDRAM/RAM_SIG<0>_14_5" BEL "SDRAM/RAM_SIG<0>_14_4" BEL
"SDRAM/RAM_SIG<0>_14_3" BEL "SDRAM/RAM_SIG<0>_14_2" BEL
"SDRAM/RAM_SIG<0>_14_1" BEL "SDRAM/RAM_SIG<0>_14_0" BEL
"SDRAM/RAM_SIG<0>_13_7" BEL "SDRAM/RAM_SIG<0>_13_6" BEL
"SDRAM/RAM_SIG<0>_13_5" BEL "SDRAM/RAM_SIG<0>_13_4" BEL
"SDRAM/RAM_SIG<0>_13_3" BEL "SDRAM/RAM_SIG<0>_13_2" BEL
"SDRAM/RAM_SIG<0>_13_1" BEL "SDRAM/RAM_SIG<0>_13_0" BEL
"SDRAM/RAM_SIG<0>_12_7" BEL "SDRAM/RAM_SIG<0>_12_6" BEL
"SDRAM/RAM_SIG<0>_12_5" BEL "SDRAM/RAM_SIG<0>_12_4" BEL
"SDRAM/RAM_SIG<0>_12_3" BEL "SDRAM/RAM_SIG<0>_12_2" BEL
"SDRAM/RAM_SIG<0>_12_1" BEL "SDRAM/RAM_SIG<0>_12_0" BEL
"SDRAM/RAM_SIG<0>_11_7" BEL "SDRAM/RAM_SIG<0>_11_6" BEL
"SDRAM/RAM_SIG<0>_11_5" BEL "SDRAM/RAM_SIG<0>_11_4" BEL
"SDRAM/RAM_SIG<0>_11_3" BEL "SDRAM/RAM_SIG<0>_11_2" BEL
"SDRAM/RAM_SIG<0>_11_1" BEL "SDRAM/RAM_SIG<0>_11_0" BEL "CPU_RDY" BEL
"sADD_1" BEL "sADD_2" BEL "sADD_6" BEL "SDRAM_MSTRB" BEL "sDin_0" BEL
"sDin_1" BEL "sDin_2" BEL "sDin_3" BEL "sDin_4" BEL "sDin_5" BEL
"sDin_6" BEL "sDin_7" BEL "Vbit_0" BEL "Vbit_2" BEL "sWen_0" BEL
"state_FSM_FFd2" BEL "state_FSM_FFd3" BEL "state_FSM_FFd5" BEL
"myCPU_gen/st1_FSM_FFd5" BEL "myCPU_gen/st1_FSM_FFd6" BEL
"state_FSM_FFd7" BEL "counter_0_1" BEL "SDRAM_ADD_3_1" BEL
"index_1_1";
TIMEGRP U_CLK = BEL "myIcon/U0/U_ICON/U_iDATA_CMD";
TIMEGRP D2_CLK = BEL "myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC";
TIMEGRP "FFS" = FFS(*);
PATH TS_D2_TO_T2_path = FROM TIMEGRP "D2_CLK" TO TIMEGRP "FFS";
PATH "TS_D2_TO_T2_path" TIG;
PATH TS_J2_TO_D2_path = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK";
PATH "TS_J2_TO_D2_path" TIG;
PATH TS_J3_TO_D2_path = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK";
PATH "TS_J3_TO_D2_path" TIG;
PATH TS_J4_TO_D2_path = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK";
PATH "TS_J4_TO_D2_path" TIG;
TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
PIN
myIcon/U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_pins<2>
= BEL
"myIcon/U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS"
PINNAME SHIFT;
PIN
"myIcon/U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_pins<2>"
TIG;
SCHEMATIC END;