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--------------------------------------------------------------------------------
Release 13.4 Trace (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
/CMC/tools/xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3
-s 5 -n 3 -fastpaths -xml CacheController.twx CacheController.ncd -o
CacheController.twr CacheController.pcf -ucf CacheController.ucf
Design file: CacheController.ncd
Physical constraint file: CacheController.pcf
Device,package,speed: xc3s500e,fg320,-5 (PRODUCTION 1.27 2012-01-07)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
================================================================================
Timing constraint: PATH "TS_D2_TO_T2_path" TIG;
3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X50Y20.G2), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 5.460ns (data path - clock path skew + uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Data Path Delay: 5.460ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y25.YQ Tcklo 0.580 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X50Y23.F2 net (fanout=1) 0.346 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X50Y23.X Tilo 0.660 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X48Y20.G1 net (fanout=2) 0.395 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X48Y20.X Tif5x 1.000 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X48Y18.G4 net (fanout=1) 0.325 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X48Y18.X Tif5x 1.000 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
SLICE_X50Y20.G2 net (fanout=1) 0.378 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
SLICE_X50Y20.CLK Tgck 0.776 myILA/U0/I_YES_D.U_ILA/iSTAT_DOUT
myILA/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O87
myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
Total 5.460ns (4.016ns logic, 1.444ns route)
(73.6% logic, 26.4% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (SLICE_X50Y22.BY), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 2.280ns (data path - clock path skew + uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (FF)
Data Path Delay: 2.280ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y25.YQ Tcklo 0.580 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X50Y23.F2 net (fanout=1) 0.346 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X50Y23.X Tilo 0.660 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X50Y22.BY net (fanout=2) 0.361 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X50Y22.CLK Tdick 0.333 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
------------------------------------------------- ---------------------------
Total 2.280ns (1.573ns logic, 0.707ns route)
(69.0% logic, 31.0% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (SLICE_X50Y23.F2), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 1.702ns (data path - clock path skew + uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (FF)
Data Path Delay: 1.702ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y25.YQ Tcklo 0.580 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X50Y23.F2 net (fanout=1) 0.346 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X50Y23.CLK Tfck 0.776 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
------------------------------------------------- ---------------------------
Total 1.702ns (1.356ns logic, 0.346ns route)
(79.7% logic, 20.3% route)
--------------------------------------------------------------------------------
Hold Paths: PATH "TS_D2_TO_T2_path" TIG;
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (SLICE_X50Y23.F2), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 1.228ns (datapath - clock path skew - uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (FF)
Data Path Delay: 1.228ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y25.YQ Tcklo 0.464 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X50Y23.F2 net (fanout=1) 0.277 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X50Y23.CLK Tckf (-Th) -0.487 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
------------------------------------------------- ---------------------------
Total 1.228ns (0.951ns logic, 0.277ns route)
(77.4% logic, 22.6% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (SLICE_X50Y22.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 1.690ns (datapath - clock path skew - uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (FF)
Data Path Delay: 1.690ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y25.YQ Tcklo 0.464 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X50Y23.F2 net (fanout=1) 0.277 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X50Y23.X Tilo 0.528 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X50Y22.BY net (fanout=2) 0.289 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X50Y22.CLK Tckdi (-Th) -0.132 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
------------------------------------------------- ---------------------------
Total 1.690ns (1.124ns logic, 0.566ns route)
(66.5% logic, 33.5% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X50Y20.G2), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 4.234ns (datapath - clock path skew - uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Data Path Delay: 4.234ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y25.YQ Tcklo 0.464 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X50Y23.F2 net (fanout=1) 0.277 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X50Y23.X Tilo 0.528 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X48Y20.G1 net (fanout=2) 0.316 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X48Y20.X Tif5x 0.800 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X48Y18.G4 net (fanout=1) 0.260 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X48Y18.X Tif5x 0.800 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
SLICE_X50Y20.G2 net (fanout=1) 0.302 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
SLICE_X50Y20.CLK Tckg (-Th) -0.487 myILA/U0/I_YES_D.U_ILA/iSTAT_DOUT
myILA/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O87
myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
Total 4.234ns (3.079ns logic, 1.155ns route)
(72.7% logic, 27.3% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_J2_TO_D2_path" TIG;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_J3_TO_D2_path" TIG;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_J4_TO_D2_path" TIG;
11 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (SLICE_X51Y25.CLK), 11 paths
--------------------------------------------------------------------------------
Delay (setup path): 5.708ns (data path)
Source: myIcon/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET (FF)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Data Path Delay: 5.708ns (Levels of Logic = 2)
Source Clock: control0<0> rising
Maximum Data Path: myIcon/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X54Y58.XQ Tcko 0.515 myIcon/U0/U_ICON/iCORE_ID<1>
myIcon/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET
SLICE_X54Y59.G1 net (fanout=5) 0.996 myIcon/U0/U_ICON/iCORE_ID<1>
SLICE_X54Y59.Y Tilo 0.660 myIcon/U0/U_ICON/iCORE_ID_SEL<15>
myIcon/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
SLICE_X50Y26.G3 net (fanout=29) 1.833 myIcon/U0/U_ICON/iCORE_ID_SEL<0>
SLICE_X50Y26.Y Tilo 0.660 myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
myIcon/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
SLICE_X51Y25.CLK net (fanout=5) 1.044 control0<13>
------------------------------------------------- ---------------------------
Total 5.708ns (1.835ns logic, 3.873ns route)
(32.1% logic, 67.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 5.704ns (data path)
Source: myIcon/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Data Path Delay: 5.704ns (Levels of Logic = 2)
Source Clock: control0<0> rising
Maximum Data Path: myIcon/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X55Y60.YQ Tcko 0.511 myIcon/U0/U_ICON/iCORE_ID<3>
myIcon/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
SLICE_X54Y59.G3 net (fanout=5) 0.996 myIcon/U0/U_ICON/iCORE_ID<2>
SLICE_X54Y59.Y Tilo 0.660 myIcon/U0/U_ICON/iCORE_ID_SEL<15>
myIcon/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
SLICE_X50Y26.G3 net (fanout=29) 1.833 myIcon/U0/U_ICON/iCORE_ID_SEL<0>
SLICE_X50Y26.Y Tilo 0.660 myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
myIcon/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
SLICE_X51Y25.CLK net (fanout=5) 1.044 control0<13>
------------------------------------------------- ---------------------------
Total 5.704ns (1.831ns logic, 3.873ns route)
(32.1% logic, 67.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 5.666ns (data path)
Source: myIcon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (FF)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Data Path Delay: 5.666ns (Levels of Logic = 2)
Source Clock: control0<0> rising
Maximum Data Path: myIcon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X55Y49.YQ Tcko 0.511 myIcon/U0/U_ICON/U_CMD/iTARGET<11>
myIcon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
SLICE_X51Y41.F1 net (fanout=17) 2.218 myIcon/U0/U_ICON/U_CMD/iTARGET<10>
SLICE_X51Y41.X Tilo 0.612 myIcon/U0/U_ICON/iCOMMAND_SEL<9>
myIcon/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT
SLICE_X50Y26.G4 net (fanout=1) 0.621 myIcon/U0/U_ICON/iCOMMAND_SEL<9>
SLICE_X50Y26.Y Tilo 0.660 myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
myIcon/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
SLICE_X51Y25.CLK net (fanout=5) 1.044 control0<13>
------------------------------------------------- ---------------------------
Total 5.666ns (1.783ns logic, 3.883ns route)
(31.5% logic, 68.5% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK"
15 ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 1.344ns.
--------------------------------------------------------------------------------
Paths for end point myIcon/U0/U_ICON/U_iDATA_CMD (SLICE_X67Y82.BY), 1 path
--------------------------------------------------------------------------------
Slack (setup paths): 13.656ns (requirement - (data path - clock path skew + uncertainty))
Source: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Destination: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Requirement: 15.000ns
Data Path Delay: 1.344ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: myIcon/U0/iUPDATE_OUT rising
Destination Clock: myIcon/U0/iUPDATE_OUT rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myIcon/U0/U_ICON/U_iDATA_CMD to myIcon/U0/U_ICON/U_iDATA_CMD
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X67Y82.YQ Tcko 0.511 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
SLICE_X67Y82.BY net (fanout=7) 0.519 myIcon/U0/U_ICON/iDATA_CMD
SLICE_X67Y82.CLK Tdick 0.314 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
------------------------------------------------- ---------------------------
Total 1.344ns (0.825ns logic, 0.519ns route)
(61.4% logic, 38.6% route)
--------------------------------------------------------------------------------
Fastest Paths: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
--------------------------------------------------------------------------------
Paths for end point myIcon/U0/U_ICON/U_iDATA_CMD (SLICE_X67Y82.BY), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.941ns (requirement - (clock path skew + uncertainty - data path))
Source: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Destination: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Requirement: 0.000ns
Data Path Delay: 0.941ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: myIcon/U0/iUPDATE_OUT rising
Destination Clock: myIcon/U0/iUPDATE_OUT rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myIcon/U0/U_ICON/U_iDATA_CMD to myIcon/U0/U_ICON/U_iDATA_CMD
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X67Y82.YQ Tcko 0.409 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
SLICE_X67Y82.BY net (fanout=7) 0.415 myIcon/U0/U_ICON/iDATA_CMD
SLICE_X67Y82.CLK Tckdi (-Th) -0.117 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
------------------------------------------------- ---------------------------
Total 0.941ns (0.526ns logic, 0.415ns route)
(55.9% logic, 44.1% route)
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 15 paths, 0 nets, and 22 connections
Design statistics:
Minimum period: 1.344ns{1} (Maximum frequency: 744.048MHz)
Maximum path delay from/to any node: 1.344ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Oct 30 11:58:50 2019
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 381 MB