From 13d023f58f0571ec1c4c3e06b67a1d29692a25e8 Mon Sep 17 00:00:00 2001 From: Frank Barchard Date: Tue, 28 Apr 2026 13:09:46 -0700 Subject: [PATCH 1/3] Add Cortex-A320 to MIDR decode table ARM Cortex-A320 (MIDR part 0xD8F) is an ARMv9.2-A efficiency core. Add its uarch enum and MIDR mapping. Co-authored-by: Nicolas Pitre --- include/cpuinfo.h | 2 ++ src/arm/uarch.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 321998c5..381018da 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -525,6 +525,8 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_a510 = 0x00300551, /** ARM Cortex-A520. */ cpuinfo_uarch_cortex_a520 = 0x00300552, + /** ARM Cortex-A320. */ + cpuinfo_uarch_cortex_a320 = 0x00300553, /** ARM Cortex-A710. */ cpuinfo_uarch_cortex_a710 = 0x00300571, /** ARM Cortex-A715. */ diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 6f92c7d2..83a0b439 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -141,6 +141,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD87: /* Cortex-A725 */ *uarch = cpuinfo_uarch_cortex_a725; break; + case 0xD8F: /* Cortex-A320 */ + *uarch = cpuinfo_uarch_cortex_a320; + break; case 0xD8C: *uarch = cpuinfo_uarch_lumex_c1_ultra; break; From 5e710ee15b9f2b61b3c9260d1a1ceb07814cd4e6 Mon Sep 17 00:00:00 2001 From: Frank Barchard Date: Tue, 28 Apr 2026 14:02:11 -0700 Subject: [PATCH 2/3] Add Apple M1/M2 Linux MIDR detection Fixes #380 by adding cpuinfo_arm_decode_vendor_uarch logic for Apple's implementer 'a' (0x61). --- src/arm/uarch.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 83a0b439..23384cfd 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -438,6 +438,35 @@ void cpuinfo_arm_decode_vendor_uarch( midr_get_part(midr)); } break; + case 'a': + *vendor = cpuinfo_vendor_apple; + switch (midr_get_part(midr)) { + case 0x022: + case 0x024: + case 0x028: + *uarch = cpuinfo_uarch_icestorm; + break; + case 0x023: + case 0x025: + case 0x029: + *uarch = cpuinfo_uarch_firestorm; + break; + case 0x032: + case 0x034: + case 0x038: + *uarch = cpuinfo_uarch_blizzard; + break; + case 0x033: + case 0x035: + case 0x039: + *uarch = cpuinfo_uarch_avalanche; + break; + default: + cpuinfo_log_warning( + "unknown Apple CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); + } + break; #if CPUINFO_ARCH_ARM case 'V': *vendor = cpuinfo_vendor_marvell; From 8373f61c87c181083463b28104d56c1ebed613e0 Mon Sep 17 00:00:00 2001 From: Frank Barchard Date: Tue, 28 Apr 2026 14:30:10 -0700 Subject: [PATCH 3/3] Add Apple M3/M4 Linux MIDR detection --- src/arm/uarch.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 23384cfd..0361d970 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -461,6 +461,22 @@ void cpuinfo_arm_decode_vendor_uarch( case 0x039: *uarch = cpuinfo_uarch_avalanche; break; + case 0x042: + case 0x044: + case 0x048: + *uarch = cpuinfo_uarch_coll_sawtooth; + break; + case 0x043: + case 0x045: + case 0x049: + *uarch = cpuinfo_uarch_coll_everest; + break; + case 0x052: + *uarch = cpuinfo_uarch_donan_sawtooth; + break; + case 0x053: + *uarch = cpuinfo_uarch_donan_everest; + break; default: cpuinfo_log_warning( "unknown Apple CPU part 0x%03" PRIx32 " ignored",