diff --git a/config.local/amd64/config.sonic b/config.local/amd64/config.sonic index 65eb60496..d67bd3bd7 100644 --- a/config.local/amd64/config.sonic +++ b/config.local/amd64/config.sonic @@ -83,6 +83,9 @@ CONFIG_MLXSW_CORE_HWMON=y CONFIG_MLXSW_I2C=m CONFIG_MLXSW_MINIMAL=m CONFIG_MLXSW_CORE_THERMAL=n +CONFIG_NVSW_HOST_L1=m +CONFIG_NVSW_HOST_SPC5=m +CONFIG_NVSW_HOST_SPC6=m CONFIG_MLXREG_HOTPLUG=m CONFIG_MLXREG_IO=m CONFIG_MLX_WDT=m @@ -103,6 +106,7 @@ CONFIG_SENSORS_MP2869=m CONFIG_SENSORS_MP29502=m CONFIG_SENSORS_MP2845=m CONFIG_SENSORS_MP5926=m +CONFIG_SENSORS_XDPE1A2G7B=m CONFIG_GPIO_ICH=m CONFIG_CPU_THERMAL=y CONFIG_IGB_HWMON=y diff --git a/patches-sonic/0043-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch b/patches-sonic/0043-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch index d09ca494e..54f32f8f0 100644 --- a/patches-sonic/0043-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch +++ b/patches-sonic/0043-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch @@ -102,7 +102,7 @@ index 00000000..3cffd09 + PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_VOUT | \ + PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_STATUS_INPUT | \ + PMBUS_HAVE_STATUS_TEMP) -+ ++ +#define MP2855_RAIL2_FUNC (PMBUS_HAVE_VOUT | PMBUS_HAVE_TEMP | PMBUS_HAVE_IOUT | \ + PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_STATUS_IOUT | \ + PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP) diff --git a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch index 8f6711267..3f3387824 100644 --- a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch +++ b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch @@ -1,4 +1,4 @@ -From e1efc50e70baeffd64fb6f233fc0b929a530b59e Mon Sep 17 00:00:00 2001 +From 7d0f9191f8e282b28411b21fd33d166c4efafc68 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 4 Jul 2024 23:50:27 +0300 Subject: [PATCH] platform/mellanox: nvsw-bmc: Add system control and @@ -19,18 +19,20 @@ This control includes: Signed-off-by: Vadim Pasternak --- .../devicetree/bindings/trivial-devices.yaml | 5 + - drivers/platform/mellanox/Kconfig | 28 + - drivers/platform/mellanox/Makefile | 3 + - drivers/platform/mellanox/nvsw-bmc-hid162.c | 2773 +++++++++++++++++ - drivers/platform/mellanox/nvsw-core.c | 685 ++++ - drivers/platform/mellanox/nvsw-host-l1.c | 744 +++++ - drivers/platform/mellanox/nvsw-host-spc5.c | 943 ++++++ - drivers/platform/mellanox/nvsw.h | 292 ++ - 8 files changed, 5473 insertions(+) + drivers/platform/mellanox/Kconfig | 38 + + drivers/platform/mellanox/Makefile | 4 + + drivers/platform/mellanox/nvsw-bmc-hid162.c | 3310 +++++++++++++++++ + drivers/platform/mellanox/nvsw-core.c | 693 ++++ + drivers/platform/mellanox/nvsw-host-l1.c | 770 ++++ + drivers/platform/mellanox/nvsw-host-spc5.c | 943 +++++ + drivers/platform/mellanox/nvsw-host-spc6.c | 852 +++++ + drivers/platform/mellanox/nvsw.h | 297 ++ + 9 files changed, 6912 insertions(+) create mode 100644 drivers/platform/mellanox/nvsw-bmc-hid162.c create mode 100644 drivers/platform/mellanox/nvsw-core.c create mode 100644 drivers/platform/mellanox/nvsw-host-l1.c create mode 100644 drivers/platform/mellanox/nvsw-host-spc5.c + create mode 100644 drivers/platform/mellanox/nvsw-host-spc6.c create mode 100644 drivers/platform/mellanox/nvsw.h diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -50,10 +52,10 @@ index a190c5676..14568bd0f 100644 - nuvoton,w83773g # OKI ML86V7667 video decoder diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig -index e3afbe62c..521423f4b 100644 +index e3afbe62c..6cbda147a 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig -@@ -105,6 +105,34 @@ config MLXBF_PMC +@@ -105,6 +105,44 @@ config MLXBF_PMC to performance monitoring counters within various blocks in the Mellanox BlueField SoC via a sysfs interface. @@ -84,28 +86,39 @@ index e3afbe62c..521423f4b 100644 + equipped on Nvidia SPC5 ethernet switches. + This driver can also be built as a module. If so the module + will be called nvsw-host-spc5. ++ ++config NVSW_HOST_SPC6 ++ tristate "Nvidia SPC6 host CPLD/FPGA Hardware Control and Monitoring" ++ depends on HWMON ++ select REGMAP_I2C ++ help ++ Say Y here to include support for the FPGA/CPLD logic by host CPU ++ equipped on Nvidia SPC6 ethernet switches. ++ This driver can also be built as a module. If so the module ++ will be called nvsw-host-spc6. + config NVSW_SN2201 tristate "Nvidia SN2201 platform driver support" depends on HWMON && I2C diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index e86723b44..a7c15b0aa 100644 +index e86723b44..123edaa99 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -11,4 +11,7 @@ obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o +@@ -11,4 +11,8 @@ obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o +obj-$(CONFIG_NVSW_BMC_HID162) += nvsw-bmc-hid162.o nvsw-core.o +obj-$(CONFIG_NVSW_HOST_L1) += nvsw-host-l1.o nvsw-core.o +obj-$(CONFIG_NVSW_HOST_SPC5) += nvsw-host-spc5.o nvsw-core.o ++obj-$(CONFIG_NVSW_HOST_SPC6) += nvsw-host-spc6.o nvsw-core.o obj-$(CONFIG_NVSW_SN2201) += nvsw-sn2201.o diff --git a/drivers/platform/mellanox/nvsw-bmc-hid162.c b/drivers/platform/mellanox/nvsw-bmc-hid162.c new file mode 100644 -index 000000000..fbc738231 +index 000000000..3c70e2979 --- /dev/null +++ b/drivers/platform/mellanox/nvsw-bmc-hid162.c -@@ -0,0 +1,2773 @@ +@@ -0,0 +1,3310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia BMC platform driver @@ -157,6 +170,11 @@ index 000000000..fbc738231 + 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, +}; + ++static int nvsw_bmc_hid185_chan2[] = { ++ 0x10, 0x11, ++}; ++ ++ +/* Mux configuration. */ +static struct i2c_mux_regmap_platform_data nvsw_bmc_hid162_mux_data[] = { + { @@ -195,6 +213,23 @@ index 000000000..fbc738231 + }, +}; + ++static struct i2c_mux_regmap_platform_data nvsw_bmc_hid185_mux_data[] = { ++ { ++ .parent = 14, ++ .chan_ids = nvsw_bmc_hid180_chan1, ++ .num_adaps = ARRAY_SIZE(nvsw_bmc_hid180_chan1), ++ .sel_reg_addr = NVSW_REG_MUX1_OFFSET, ++ .reg_size = 1, ++ }, ++ { ++ .parent = 12, ++ .chan_ids = nvsw_bmc_hid185_chan2, ++ .num_adaps = ARRAY_SIZE(nvsw_bmc_hid185_chan2), ++ .sel_reg_addr = NVSW_REG_MUX2_OFFSET, ++ .reg_size = 1, ++ }, ++}; ++ +static struct i2c_mux_regmap_platform_data *mux_data[NVSW_MUX_MAX]; +static struct i2c_board_info *mux_brdinfo[NVSW_MUX_MAX]; + @@ -770,7 +805,7 @@ index 000000000..fbc738231 + .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "3v3_clk_pg", ++ .label = "holder6_pg", + .reg = NVSW_REG_PG1_OFFSET, + .mask = BIT(1), + .hpdev.nr = NVSW_NR_NONE, @@ -806,7 +841,7 @@ index 000000000..fbc738231 + .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "vdrv_asic_1_2_pg", ++ .label = "holder7_pg", + .reg = NVSW_REG_PG1_OFFSET, + .mask = BIT(7), + .hpdev.nr = NVSW_NR_NONE, @@ -917,7 +952,7 @@ index 000000000..fbc738231 + +static struct mlxreg_core_data nvsw_bmc_hid180_pg4_events_items_data[] = { + { -+ .label = "mbus_alt_pwrconv_2", ++ .label = "smbus_alt_pwrconv_2", + .reg = NVSW_REG_PG3_OFFSET, + .mask = BIT(0), + .hpdev.nr = NVSW_NR_NONE, @@ -1124,23 +1159,41 @@ index 000000000..fbc738231 + .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "51v_usb", ++ .label = "5v_usb", + .reg = NVSW_REG_BRD1_OFFSET, + .mask = NVSW_5V_USB_MASK, + .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "ssd_pg", ++ .label = "holder1_alarm", + .reg = NVSW_REG_BRD1_OFFSET, + .mask = BIT(3), + .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "leakage_aggr", ++ .label = "holder2_alarm", + .reg = NVSW_REG_BRD1_OFFSET, + .mask = BIT(4), + .hpdev.nr = NVSW_NR_NONE, + }, ++ { ++ .label = "sgmii_pg", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "ssd_pg", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage_aggr", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, +}; + +static struct mlxreg_core_data nvsw_bmc_hid180_alarms2_items_data[] = { @@ -1170,6 +1223,27 @@ index 000000000..fbc738231 + }, +}; + ++static struct mlxreg_core_data nvsw_bmc_hid180_cpu_items_data[] = { ++ { ++ .label = "cpu_rst", ++ .reg = NVSW_REG_BRD2_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "bios_started", ++ .reg = NVSW_REG_BRD2_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "bios_ended", ++ .reg = NVSW_REG_BRD2_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ +static struct mlxreg_core_data nvsw_bmc_hid180_vr1_pwr_alert_items_data[] = { + { + .label = "asic1_vdd_pwr_alert", @@ -1363,7 +1437,7 @@ index 000000000..fbc738231 + .data = nvsw_bmc_hid180_alarms_items_data, + .aggr_mask = NVSW_AGGR_MASK, + .reg = NVSW_REG_BRD1_OFFSET, -+ .mask = GENMASK(4, 0), ++ .mask = GENMASK(7, 0), + .count = ARRAY_SIZE(nvsw_bmc_hid180_alarms_items_data), + .inversed = 0, + .health = false, @@ -1378,6 +1452,15 @@ index 000000000..fbc738231 + .health = false, + }, + { ++ .data = nvsw_bmc_hid180_cpu_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD2_OFFSET, ++ .mask = GENMASK(4, 2), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_cpu_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { + .data = nvsw_bmc_hid180_vr1_pwr_alert_items_data, + .aggr_mask = NVSW_AGGR_MASK, + .reg = NVSW_REG_VR1_ALERT_OFFSET, @@ -1436,643 +1519,671 @@ index 000000000..fbc738231 + .mask = NVSW_AGGR_MASK | NVSW_AGGR_MASK_COMEX, + .cell_low = NVSW_REG_AGGRLO_OFFSET, + .mask_low = GENMASK(6, 0), ++ .deferred_nr = 5, +}; + -+/* Platform register access data. */ -+static struct mlxreg_core_data nvsw_bmc_hid162_regio_data[] = { ++static struct mlxreg_core_data nvsw_bmc_hid185_pg1_events_items_data[] = { + { -+ .label = "cpld1_version", -+ .reg = NVSW_REG_CPLD1_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "swb1_ni_smbus_alt", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld2_version", -+ .reg = NVSW_REG_CPLD2_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "swb1_clk_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld3_version", -+ .reg = NVSW_REG_CPLD3_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asic1_vdd_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld4_version", -+ .reg = NVSW_REG_CPLD4_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asic1_dvdd_pl0_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld1_pn", -+ .reg = NVSW_REG_CPLD1_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, ++ .label = "asic1_dvdd_pl1_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld2_pn", -+ .reg = NVSW_REG_CPLD2_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, ++ .label = "asic1_hvdd_avcc_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld3_pn", -+ .reg = NVSW_REG_CPLD3_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, ++ .label = "swb1_1v8_vddio_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "swb1_vdrv_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, + }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid185_pg3_events_items_data[] = { + { -+ .label = "cpld4_pn", -+ .reg = NVSW_REG_CPLD4_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, ++ .label = "swb1_smbus_alt_hotswap", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld1_version_min", -+ .reg = NVSW_REG_CPLD1_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "swb1_3v3_pb_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld2_version_min", -+ .reg = NVSW_REG_CPLD2_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asic2_vdd_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld3_version_min", -+ .reg = NVSW_REG_CPLD3_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asic2_dvdd_pl0_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpld4_version_min", -+ .reg = NVSW_REG_CPLD4_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asic2_dvdd_pl1_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "fan_dir", -+ .reg = NVSW_REG_GP0_RO_OFFSET, -+ .mask = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asic2_hvdd_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "fan_present", -+ .reg = NVSW_REG_FAN_OFFSET, -+ .mask = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "swb1_1v8_cpld_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, + }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid185_pg4_events_items_data[] = { + { -+ .label = "cpu_mctp_ready", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, ++ .label = "swb2_ni_smbus_alt", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpu_shutdown_req", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0644, ++ .label = "swb2_clk_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "vpd_wp", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, -+ .secured = 1, ++ .label = "asic3_vdd_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "pcie_asic_reset_dis", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, ++ .label = "asic3_dvdd_pl0_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "shutdown_unlock", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, ++ .label = "asic3_dvdd_pl1_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "cpu_power_off_ready", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, ++ .label = "asic3_hvdd_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "ignore_next_reset", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, ++ .label = "swb2_1v8_vddio_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "leakage_conn_en", -+ .reg = NVSW_REG_GP6_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, ++ .label = "swb2_vdrv_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, + }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid185_pg5_events_items_data[] = { + { -+ .label = "bmc_reset_reg", -+ .reg = NVSW_REG_GP6_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, ++ .label = "swb2_smbus_alt_hotswap", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "spi_chnl_select", -+ .reg = NVSW_REG_SPI_CHNL_SELECT, -+ .mask = GENMASK(7, 0), -+ .bit = 1, -+ .mode = 0644, -+ }, -+ { -+ .label = "pwr_converter_prog_en", -+ .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, -+ .secured = 1, ++ .label = "swb2_3v3_pb_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "graceful_power_off", -+ .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, ++ .label = "asic4_vdd_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "bmc_perst_en", -+ .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0200, ++ .label = "asic4_dvdd_pl0_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "bmc_shutdown_unlock", -+ .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0200, ++ .label = "asic4_dvdd_pl1_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "platform_reset", -+ .reg = NVSW_REG_RESET_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, ++ .label = "asic4_hvdd_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, + }, + { -+ .label = "main_brd_reset", -+ .reg = NVSW_REG_RESET_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, ++ .label = "swb2_1v8_cpld_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, + }, ++}; ++ ++static struct mlxreg_core_item nvsw_bmc_hid185_hotplug_items_data[] = { + { -+ .label = "nic_reset", -+ .reg = NVSW_REG_RESET_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0200, ++ .data = nvsw_bmc_hid185_pg1_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid185_pg1_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, + }, + { -+ .label = "tpm_reset", -+ .reg = NVSW_REG_RESET_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0200, ++ .data = nvsw_bmc_hid180_pg2_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK_COMEX, ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_pg2_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, + }, + { -+ .label = "erot_asic3_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, ++ .data = nvsw_bmc_hid185_pg3_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid185_pg3_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, + }, + { -+ .label = "asics_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, ++ .data = nvsw_bmc_hid185_pg4_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = NVSW_AGGR_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid185_pg4_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, + }, + { -+ .label = "sgmii_phy_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0200, ++ .data = nvsw_bmc_hid185_pg5_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid185_pg5_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, + }, + { -+ .label = "erot_cpu_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0200, ++ .data = nvsw_bmc_hid180_asic_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASICS_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_asic_items_data), ++ .inversed = 0, ++ .health = true, + }, + { -+ .label = "erot_asic1_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0200, ++ .data = nvsw_bmc_hid180_asic_temp_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = NVSW_ASICS_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_asic_temp_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "erot_asic2_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0200, ++ .data = nvsw_bmc_hid180_leakage_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(1, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_leakage_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "jtag_enable", -+ .reg = NVSW_REG_FIELD_UPGRADE, -+ .mask = GENMASK(1, 0), -+ .bit = 1, -+ .mode = 0644, ++ .data = nvsw_bmc_hid180_alarms_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_alarms_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "non_active_bios_select", -+ .reg = NVSW_REG_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, ++ .data = nvsw_bmc_hid180_alarms2_items_data, ++ .aggr_mask = NVSW_AGGR_MASK_COMEX, ++ .reg = NVSW_REG_HEALTH_OFFSET, ++ .mask = GENMASK(3, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_alarms2_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "bios_upgrade_fail", -+ .reg = NVSW_REG_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, ++ .data = nvsw_bmc_hid180_cpu_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD2_OFFSET, ++ .mask = GENMASK(4, 2), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_cpu_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "bios_image_invert", -+ .reg = NVSW_REG_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, ++ .data = nvsw_bmc_hid180_vr1_pwr_alert_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_vr1_pwr_alert_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "erot_asic3_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, ++ .data = nvsw_bmc_hid180_vr2_pwr_alert_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_vr2_pwr_alert_items_data), ++ .inversed = 0, ++ .health = false, + }, + { -+ .label = "erot_cpu_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, ++ .data = nvsw_bmc_hid180_erot_error_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_erot_error_items_data), ++ .inversed = 1, ++ .health = false, + }, + { -+ .label = "erot_asic1_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, ++ .data = nvsw_bmc_hid162_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | ++ NVSW_CPU_UNEXP_POWER_OFF_MASK | NVSW_UID_PUSH_BUTTON_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, + }, + { -+ .label = "erot_asic2_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, ++ .data = nvsw_bmc_hid162_cartridge_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = NVSW_REG_FRU1_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_cartridge_items_data), ++ .inversed = 0, ++ .health = false, + }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data nvsw_bmc_hid185_hotplug = { ++ .items = nvsw_bmc_hid185_hotplug_items_data, ++ .count = ARRAY_SIZE(nvsw_bmc_hid185_hotplug_items_data), ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK | NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRLO_OFFSET, ++ .mask_low = GENMASK(6, 0), ++ .deferred_nr = 5, ++}; ++ ++/* Platform register access data. */ ++static struct mlxreg_core_data nvsw_bmc_hid162_regio_data[] = { + { -+ .label = "pwr_button_halt", -+ .reg = NVSW_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "pwr_cycle", -+ .reg = NVSW_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "pwr_down", -+ .reg = NVSW_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, ++ .label = "cpld3_version", ++ .reg = NVSW_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "aux_pwr_cycle", -+ .reg = NVSW_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0200, ++ .label = "cpld4_version", ++ .reg = NVSW_REG_CPLD4_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "bmc_to_cpu_ctrl", -+ .reg = NVSW_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "uart_sel", -+ .reg = NVSW_REG_GP1_OFFSET, -+ .mask = NVSW_UART_SEL_MASK, -+ .bit = 7, -+ .mode = 0644, ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "reset_long_pb", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), ++ .label = "cpld3_pn", ++ .reg = NVSW_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), + .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "reset_short_pb", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), ++ .label = "cpld4_pn", ++ .reg = NVSW_REG_CPLD4_PN_OFFSET, ++ .bit = GENMASK(15, 0), + .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "reset_aux_pwr_or_fu", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "reset_swb_pwr_fail", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "reset_pwr_button_or_leak_con", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), ++ .label = "cpld3_version_min", ++ .reg = NVSW_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "reset_swb_wd", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), ++ .label = "cpld4_version_min", ++ .reg = NVSW_REG_CPLD4_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "reset_asic_thermal", -+ .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), ++ .label = "fan_dir", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "reset_from_carrier", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), ++ .label = "fan_present", ++ .reg = NVSW_REG_FAN_OFFSET, ++ .mask = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "reset_aux_pwr_or_reload", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_comex_pwr_fail", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, ++ .mode = 0644, ++ .secured = 1, + }, + { -+ .label = "reset_platform", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_soc", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_from_erot", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_pwr", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .label = "ignore_next_reset", ++ .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_erot", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .label = "leakage_conn_en", ++ .reg = NVSW_REG_GP6_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_system", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .label = "bmc_reset_reg", ++ .reg = NVSW_REG_GP6_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_sw_pwr_off", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, + }, + { -+ .label = "reset_comex_thermal", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .label = "pwr_converter_prog_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "graceful_power_off", ++ .reg = NVSW_REG_GP7_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "reset_comex_power", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .label = "bmc_perst_en", ++ .reg = NVSW_REG_GP7_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, ++ .mode = 0200, + }, + { -+ .label = "reset_pwr_converter_fail", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .label = "bmc_shutdown_unlock", ++ .reg = NVSW_REG_GP7_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_main_51v", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0444, ++ .mode = 0200, + }, + { -+ .label = "reset_mgmt_pwr", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, ++ .label = "platform_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, + }, + { -+ .label = "port80", -+ .reg = NVSW_REG_GP1_RO_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "main_brd_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, + }, + { -+ .label = "bios_status", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = NVSW_BIOS_STATUS_MASK, -+ .bit = 2, -+ .mode = 0444, ++ .label = "nic_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0200, + }, + { -+ .label = "bios_start_retry", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, ++ .label = "tpm_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, + }, + { -+ .label = "bios_active_image", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, ++ .label = "erot_asic3_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, + }, + { -+ .label = "ufm_version", -+ .reg = NVSW_REG_UFM_VERSION_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, ++ .label = "asics_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, + }, + { -+ .label = "clk_brd1_boot_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, ++ .mode = 0200, + }, + { -+ .label = "clk_brd2_boot_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, ++ .label = "erot_cpu_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, + }, + { -+ .label = "clk_brd_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .label = "erot_asic1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0444, ++ .mode = 0200, + }, + { -+ .label = "asic_pg_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .label = "erot_asic2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, ++ .mode = 0200, + }, + { -+ .label = "geo_addr", -+ .reg = NVSW_REG_CONFIG2_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+}; -+ -+static struct mlxreg_core_platform_data nvsw_bmc_hid162_regio = { -+ .data = nvsw_bmc_hid162_regio_data, -+ .counter = ARRAY_SIZE(nvsw_bmc_hid162_regio_data), -+}; -+ -+static struct mlxreg_core_data nvsw_bmc_hid180_regio_data[] = { -+ { -+ .label = "cpld1_version", -+ .reg = NVSW_REG_CPLD1_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "cpld2_version", -+ .reg = NVSW_REG_CPLD2_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "cpld1_pn", -+ .reg = NVSW_REG_CPLD1_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, -+ }, -+ { -+ .label = "cpld2_pn", -+ .reg = NVSW_REG_CPLD2_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, -+ }, -+ { -+ .label = "cpld1_version_min", -+ .reg = NVSW_REG_CPLD1_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "cpld2_version_min", -+ .reg = NVSW_REG_CPLD2_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "bios_status", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(3, 1), -+ .bit = 3, -+ .mode = 0444, ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, + }, + { -+ .label = "bios_start_retry", -+ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .label = "non_active_bios_select", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, ++ .mode = 0644, + }, + { -+ .label = "bios_active_image", -+ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .label = "bios_upgrade_fail", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { -+ .label = "pwr_converter_prog_en", -+ .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), ++ .label = "bios_image_invert", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { -+ .label = "cpu_mctp_ready", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), ++ .label = "erot_asic3_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { -+ .label = "cpu_shutdown_req", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, -+ { -+ .label = "vpd_wp", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), ++ .label = "erot_cpu_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, -+ .secured = 1, + }, + { -+ .label = "pcie_asic_reset_dis", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), ++ .label = "erot_asic1_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { -+ .label = "shutdown_unlock", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), ++ .label = "erot_asic2_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, + { -+ .label = "cpu_power_off_ready", -+ .reg = NVSW_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), ++ .label = "pwr_button_halt", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "pwr_cycle", + .reg = NVSW_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0244, ++ .mode = 0200, + }, + { + .label = "pwr_down", + .reg = NVSW_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "aux_pwr_cycle", @@ -2094,36 +2205,6 @@ index 000000000..fbc738231 + .mode = 0644, + }, + { -+ .label = "asics_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, -+ }, -+ { -+ .label = "sgmii_phy_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, -+ }, -+ { -+ .label = "cpu_erot_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, -+ }, -+ { -+ .label = "mcu1_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, -+ }, -+ { -+ .label = "mcu2_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, -+ }, -+ { + .label = "reset_long_pb", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), @@ -2142,13 +2223,19 @@ index 000000000..fbc738231 + .mode = 0444, + }, + { -+ .label = "reset_swb_dc_dc_pwr_fail", ++ .label = "reset_swb_pwr_fail", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { -+ .label = "reset_pwr_button_or_leak_con", ++ .label = "reset_cpu", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_button", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, @@ -2166,7 +2253,13 @@ index 000000000..fbc738231 + .mode = 0444, + }, + { -+ .label = "reset_from_cpld", ++ .label = "reset_from_carrier", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_reload", + .reg = NVSW_REG_RESET_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, @@ -2190,6 +2283,18 @@ index 000000000..fbc738231 + .mode = 0444, + }, + { ++ .label = "reset_from_erot", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { + .label = "reset_erot", + .reg = NVSW_REG_RESET_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), @@ -2244,1338 +2349,2567 @@ index 000000000..fbc738231 + .mode = 0444, + }, + { -+ .label = "transport_status", -+ .reg = NVSW_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(1, 0), -+ .bit = 1, ++ .label = "bios_status", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = NVSW_BIOS_STATUS_MASK, ++ .bit = 2, + .mode = 0444, + }, + { -+ .label = "asics_pg_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), ++ .label = "bios_start_retry", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { -+ .label = "jtag_cap", -+ .reg = NVSW_REG_FU_CAP_OFFSET, -+ .mask = NVSW_FU_CAP_MASK, -+ .bit = 1, ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { -+ .label = "jtag_enable", -+ .reg = NVSW_REG_FIELD_UPGRADE, -+ .mask = GENMASK(1, 0), -+ .bit = 1, -+ .mode = 0644, ++ .label = "ufm_version", ++ .reg = NVSW_REG_UFM_VERSION_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "non_active_bios_select", -+ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .label = "clk_brd1_boot_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, ++ .mode = 0444, + }, + { -+ .label = "bios_upgrade_fail", -+ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .label = "clk_brd2_boot_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { -+ .label = "bios_image_invert", -+ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .label = "clk_brd_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, ++ .mode = 0444, + }, + { -+ .label = "erot_cpu_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, ++ .label = "asic_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, + }, + { -+ .label = "mcu1_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, ++ .label = "geo_addr", ++ .reg = NVSW_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid162_regio = { ++ .data = nvsw_bmc_hid162_regio_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid162_regio_data), ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_regio_data[] = { + { -+ .label = "mcu2_recovery", -+ .reg = NVSW_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "cpu_int_enable", -+ .reg = NVSW_REG_GP5_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "cpu_tps_upgrade", -+ .reg = NVSW_REG_GP5_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, ++ .label = "cpld3_version", ++ .reg = NVSW_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "cpu_spi_ctrl", -+ .reg = NVSW_REG_GP5_OFFSET, -+ .mask = GENMASK(4, 2), -+ .bit = 4, -+ .mode = 0644, ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "ignore_next_reset", -+ .reg = NVSW_REG_GP5_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "leakage_conn_en", -+ .reg = NVSW_REG_GP6_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, ++ .label = "cpld3_pn", ++ .reg = NVSW_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { -+ .label = "bmc_reset_reg", -+ .reg = NVSW_REG_GP6_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "asic_pg_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "spi_chnl_select", -+ .reg = NVSW_REG_SPI_CHNL_SELECT, -+ .mask = GENMASK(7, 0), -+ .bit = 1, -+ .mode = 0644, ++ .label = "cpld3_version_min", ++ .reg = NVSW_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { -+ .label = "config1", -+ .reg = NVSW_REG_CONFIG1_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "bios_status", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(3, 1), ++ .bit = 3, + .mode = 0444, + }, + { -+ .label = "config2", -+ .reg = NVSW_REG_CONFIG2_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "bios_start_retry", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { -+ .label = "config3", -+ .reg = NVSW_REG_CONFIG3_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { -+ .label = "graseful_pwr_off", ++ .label = "pwr_converter_prog_en", + .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, -+}; -+ -+static struct mlxreg_core_platform_data nvsw_bmc_hid180_regio = { -+ .data = nvsw_bmc_hid180_regio_data, -+ .counter = ARRAY_SIZE(nvsw_bmc_hid180_regio_data), -+}; -+ -+/* Platform fan data. */ -+static struct mlxreg_core_data nvsw_bmc_hid162_fan_data[] = { + { -+ .label = "pwm1", -+ .reg = NVSW_REG_PWM1_OFFSET, ++ .label = "graceful_power_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, + }, + { -+ .label = "tacho1", -+ .reg = NVSW_REG_TACHO1_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 1, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "bmc_perst_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, + }, + { -+ .label = "tacho2", -+ .reg = NVSW_REG_TACHO2_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 2, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "stby_pwr_en_unmask", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, + }, + { -+ .label = "tacho3", -+ .reg = NVSW_REG_TACHO3_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 3, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "i3c_mux_sel", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, + }, + { -+ .label = "tacho4", -+ .reg = NVSW_REG_TACHO4_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 4, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, + }, + { -+ .label = "tacho5", -+ .reg = NVSW_REG_TACHO5_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 5, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, + }, + { -+ .label = "tacho6", -+ .reg = NVSW_REG_TACHO6_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 6, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ .secured = 1, + }, + { -+ .label = "tacho7", -+ .reg = NVSW_REG_TACHO7_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 7, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, + }, + { -+ .label = "tacho8", -+ .reg = NVSW_REG_TACHO8_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 8, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, + }, + { -+ .label = "tacho9", -+ .reg = NVSW_REG_TACHO9_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 9, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, + }, + { -+ .label = "tacho10", -+ .reg = NVSW_REG_TACHO10_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 10, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "pwr_button_halt", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, + }, + { -+ .label = "tacho11", -+ .reg = NVSW_REG_TACHO11_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 11, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, + }, + { -+ .label = "tacho12", -+ .reg = NVSW_REG_TACHO12_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = NVSW_REG_FAN_CAP1_OFFSET, -+ .slot = 12, -+ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ .label = "pwr_down", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, + }, + { -+ .label = "conf", -+ .mask = NVSW_HID162_TACHO_SAMPLES, -+ .bit = NVSW_HID162_TACHO_DIV, -+ .capability = NVSW_REG_TACHO_SPEED_OFFSET, ++ .label = "aux_pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, + }, -+}; -+ -+static struct mlxreg_core_platform_data nvsw_bmc_hid162_fan = { -+ .data = nvsw_bmc_hid162_fan_data, -+ .counter = ARRAY_SIZE(nvsw_bmc_hid162_fan_data), -+ .capability = NVSW_REG_FAN_DRW_CAP_OFFSET, -+ .version = 1, -+}; -+ -+/* Platform led data for HI162 system type. */ -+static struct mlxreg_core_data nvsw_bmc_hid162_led_data[] = { + { -+ .label = "status:green", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "bmc_to_cpu_ctrl", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, + }, + { -+ .label = "status:amber", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "uart_sel", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = NVSW_UART_SEL_MASK, ++ .bit = 7, ++ .mode = 0644, + }, + { -+ .label = "power:green", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ .label = "asics_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, + }, + { -+ .label = "power:amber", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, + }, + { -+ .label = "uid:blue", -+ .reg = NVSW_REG_LED5_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "erot_cpu_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, + }, + { -+ .label = "fan:green", -+ .reg = NVSW_REG_LED6_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "mcu1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, + }, + { -+ .label = "fan:amber", -+ .reg = NVSW_REG_LED6_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "mcu2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, + }, -+}; -+ -+static struct mlxreg_core_platform_data nvsw_bmc_hid162_led = { -+ .data = nvsw_bmc_hid162_led_data, -+ .counter = ARRAY_SIZE(nvsw_bmc_hid162_led_data), -+}; -+ -+/* Platform led data for HI1676 system type. */ -+static struct mlxreg_core_data nvsw_bmc_hid176_led_data[] = { + { -+ .label = "status:green", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "platform_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, + }, + { -+ .label = "status:amber", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "cpld_phy_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0200, + }, + { -+ .label = "power:green", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ .label = "tpm_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, + }, + { -+ .label = "power:amber", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ .label = "reset_long_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, + }, + { -+ .label = "uid:blue", -+ .reg = NVSW_REG_LED5_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "reset_short_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, + }, + { -+ .label = "leakage:green", -+ .reg = NVSW_REG_LED7_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "reset_aux_pwr_or_fu", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, + }, + { -+ .label = "leakage:amber", -+ .reg = NVSW_REG_LED7_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, + }, -+}; -+ -+static struct mlxreg_core_platform_data nvsw_bmc_hid176_led = { -+ .data = nvsw_bmc_hid176_led_data, -+ .counter = ARRAY_SIZE(nvsw_bmc_hid176_led_data), -+}; -+ -+/* Platform led data for HI1676 system type. */ -+static struct mlxreg_core_data nvsw_bmc_hid177_led_data[] = { + { -+ .label = "status:green", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "reset_pwr_button_or_leak_con", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, + }, + { -+ .label = "status:amber", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "reset_swb_wd", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, + }, + { -+ .label = "power:green", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ .label = "reset_asic_thermal", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, + }, + { -+ .label = "power:amber", -+ .reg = NVSW_REG_LED1_OFFSET, -+ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ .label = "reset_soc", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, + }, + { -+ .label = "uid:blue", -+ .reg = NVSW_REG_LED5_OFFSET, -+ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ .label = "reset_erot", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, + }, -+}; -+ -+static struct mlxreg_core_platform_data nvsw_bmc_hid177_led = { -+ .data = nvsw_bmc_hid177_led_data, -+ .counter = ARRAY_SIZE(nvsw_bmc_hid177_led_data), -+}; -+ -+/* Mux init/exit callbacks. */ -+static int nvsw_bmc_hid162_mux_topology_init(struct nvsw_core *nvsw_core) -+{ -+ int i, err; -+ -+ /* Create mux infrastructure. */ -+ for (i = 0; i < nvsw_core->mux_num; i++) { -+ mux_data[i]->regmap = nvsw_core->regmap; -+ nvsw_core->mux[i] = platform_device_register_resndata(nvsw_core->dev, -+ "i2c-mux-regmap", i, NULL, 0, -+ mux_data[i], -+ sizeof(*mux_data[i])); -+ if (IS_ERR(nvsw_core->mux[i])) { -+ dev_err(nvsw_core->dev, "Failed to create mux infra\n"); -+ err = PTR_ERR(nvsw_core->mux[i]); -+ goto fail_platform_mux_register; -+ } -+ } -+ -+ return 0; -+fail_platform_mux_register: -+ while (--i >= 0) -+ platform_device_unregister(nvsw_core->mux[i]); -+ return err; -+} -+ -+static void nvsw_bmc_hid162_mux_topology_exit(struct nvsw_core *nvsw_core) -+{ -+ int i; -+ -+ for (i = 0; i < nvsw_core->mux_num; i++) { -+ if (nvsw_core->mux[i]) -+ platform_device_unregister(nvsw_core->mux[i]); -+ } -+} -+ -+/* Callbact to set initial values for specific registers. */ -+static int nvsw_bmc_hid162_set_reg_default(struct regmap *regmap) -+{ -+ u32 regval; -+ int err; -+ -+ err = regmap_read(regmap, NVSW_REG_GP6_OFFSET, ®val); -+ if (err) -+ return err; -+ -+ return regmap_write(regmap, NVSW_REG_GP6_OFFSET, regval | NVSW_REG_RESET_MASK); -+} -+ -+/* Callback is used to indicate that all adapter devices has been created. */ -+static int -+nvsw_bmc_hid162_completion_notify(void *handle, struct i2c_adapter *parent, -+ struct i2c_adapter *adapters[]) -+{ -+ /* struct nvsw_core *nvsw_core = handle; */ -+ -+ return 0; -+} -+ -+static int nvsw_bmc_hid162_platform_data_init(struct nvsw_core *nvsw_core) -+{ -+ int i; -+ -+ /* Set system configuration. */ -+ nvsw_core->hid = HID162; -+ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid162_mux_data); -+ for (i = 0; i < nvsw_core->mux_num; i++) { -+ mux_data[i] = &nvsw_bmc_hid162_mux_data[i]; -+ mux_data[i]->handle = nvsw_core; -+ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; -+ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; -+ mux_brdinfo[i]->platform_data = mux_data[i]; -+ } -+ -+ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; -+ nvsw_core->led_data = &nvsw_bmc_hid162_led; -+ nvsw_core->fan_data = &nvsw_bmc_hid162_fan; -+ nvsw_core->hotplug_data = &nvsw_bmc_hid162_hotplug; -+ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; -+ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; -+ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; -+ -+ return 0; -+} -+ -+static int nvsw_bmc_hid176_platform_data_init(struct nvsw_core *nvsw_core) -+{ -+ int i; -+ -+ /* Set system configuration. */ -+ nvsw_core->hid = HID176; -+ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid176_mux_data); -+ for (i = 0; i < nvsw_core->mux_num; i++) { -+ mux_data[i] = &nvsw_bmc_hid176_mux_data[i]; -+ mux_data[i]->handle = nvsw_core; -+ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; -+ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; -+ mux_brdinfo[i]->platform_data = mux_data[i]; -+ } -+ -+ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; -+ nvsw_core->led_data = &nvsw_bmc_hid176_led; -+ nvsw_core->hotplug_data = &nvsw_bmc_hid176_hotplug; -+ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; -+ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; -+ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; -+ -+ return 0; -+} -+ -+static int nvsw_bmc_hid177_platform_data_init(struct nvsw_core *nvsw_core) -+{ -+ int i; -+ -+ /* Set system configuration. */ -+ nvsw_core->hid = HID177; -+ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid176_mux_data); -+ for (i = 0; i < nvsw_core->mux_num; i++) { -+ mux_data[i] = &nvsw_bmc_hid176_mux_data[i]; -+ mux_data[i]->handle = nvsw_core; -+ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; -+ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; -+ mux_brdinfo[i]->platform_data = mux_data[i]; -+ } -+ -+ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; -+ nvsw_core->led_data = &nvsw_bmc_hid177_led; -+ nvsw_core->hotplug_data = &nvsw_bmc_hid177_hotplug; -+ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; -+ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; -+ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; -+ -+ return 0; -+} -+ -+static int nvsw_bmc_hid180_platform_data_init(struct nvsw_core *nvsw_core) -+{ -+ int i; -+ -+ /* Set system configuration. */ -+ nvsw_core->hid = HID180; -+ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid180_mux_data); -+ for (i = 0; i < nvsw_core->mux_num; i++) { -+ mux_data[i] = &nvsw_bmc_hid180_mux_data[i]; -+ mux_data[i]->handle = nvsw_core; -+ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; -+ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; -+ mux_brdinfo[i]->platform_data = mux_data[i]; -+ } -+ -+ nvsw_core->regio_data = &nvsw_bmc_hid180_regio; -+ nvsw_core->led_data = &nvsw_bmc_hid177_led; -+ nvsw_core->hotplug_data = &nvsw_bmc_hid180_hotplug; -+ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; -+ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; -+ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; -+ -+ return 0; -+} -+ -+static int nvsw_bmc_platform_data_init(struct nvsw_core *nvsw_core, enum nvsw_core_hid_type type) -+{ -+ switch (type) { -+ case HID162: -+ return nvsw_bmc_hid162_platform_data_init(nvsw_core); -+ case HID176: -+ return nvsw_bmc_hid176_platform_data_init(nvsw_core); -+ case HID177: -+ return nvsw_bmc_hid177_platform_data_init(nvsw_core); -+ case HID180: -+ return nvsw_bmc_hid180_platform_data_init(nvsw_core); -+ default: -+ return -ENODEV; -+ } -+} -+ -+static int nvsw_bmc_hid162_probe(struct i2c_client *client) -+{ -+ struct device_node *np = client->dev.of_node; -+ enum nvsw_core_hid_type type; -+ struct nvsw_core *nvsw_core; -+ int err; ++ { ++ .label = "leak_con", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_cpu_thermal", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_converter_fail", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_51v", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_mgmt_pwr", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "port80", ++ .reg = NVSW_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "transport_status", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "tpm_present", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "asics_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_cap", ++ .reg = NVSW_REG_FU_CAP_OFFSET, ++ .mask = NVSW_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "non_active_bios_select", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "bios_upgrade_fail", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_image_invert", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot_cpu_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu1_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu2_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_int_enable", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_tps_upgrade", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_spi_ctrl", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(4, 2), ++ .bit = 4, ++ .mode = 0644, ++ }, ++ { ++ .label = "ignore_next_reset", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "leakage_conn_en", ++ .reg = NVSW_REG_GP6_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "bmc_reset_reg", ++ .reg = NVSW_REG_GP6_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "config1", ++ .reg = NVSW_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config2", ++ .reg = NVSW_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config3", ++ .reg = NVSW_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++}; + -+ if (!np) -+ return -ENODEV; ++static struct mlxreg_core_platform_data nvsw_bmc_hid180_regio = { ++ .data = nvsw_bmc_hid180_regio_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid180_regio_data), ++}; + -+ if (of_device_is_compatible(np, "nvidia,hid162")) -+ type = HID162; -+ else if (of_device_is_compatible(np, "nvidia,hid176")) -+ type = HID176; -+ else if (of_device_is_compatible(np, "nvidia,hid177")) -+ type = HID177; -+ else if (of_device_is_compatible(np, "nvidia,hid180")) -+ type = HID180; -+ else -+ return -ENODEV; -+ -+ nvsw_core = devm_kzalloc(&client->dev, sizeof(*nvsw_core), GFP_KERNEL); -+ if (!nvsw_core) -+ return -ENOMEM; -+ -+ nvsw_core->dev = &client->dev; -+ nvsw_core->client = client; -+ nvsw_core->np = np; -+ nvsw_core->regmap_type = REGMAP_I2C; -+ i2c_set_clientdata(client, nvsw_core); -+ err = nvsw_bmc_platform_data_init(nvsw_core, type); -+ if (err) -+ return err; -+ -+ return nvsw_core_init(nvsw_core); -+} -+ -+static void nvsw_bmc_hid162_remove(struct i2c_client *client) -+{ -+ struct nvsw_core *nvsw_core = i2c_get_clientdata(client); ++/* Platform fan data. */ ++static struct mlxreg_core_data nvsw_bmc_hid162_fan_data[] = { ++ { ++ .label = "pwm1", ++ .reg = NVSW_REG_PWM1_OFFSET, ++ }, ++ { ++ .label = "tacho1", ++ .reg = NVSW_REG_TACHO1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 1, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho2", ++ .reg = NVSW_REG_TACHO2_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 2, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho3", ++ .reg = NVSW_REG_TACHO3_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 3, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho4", ++ .reg = NVSW_REG_TACHO4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 4, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho5", ++ .reg = NVSW_REG_TACHO5_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 5, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho6", ++ .reg = NVSW_REG_TACHO6_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 6, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho7", ++ .reg = NVSW_REG_TACHO7_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 7, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho8", ++ .reg = NVSW_REG_TACHO8_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 8, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho9", ++ .reg = NVSW_REG_TACHO9_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 9, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho10", ++ .reg = NVSW_REG_TACHO10_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 10, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho11", ++ .reg = NVSW_REG_TACHO11_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 11, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho12", ++ .reg = NVSW_REG_TACHO12_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 12, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "conf", ++ .mask = NVSW_HID162_TACHO_SAMPLES, ++ .bit = NVSW_HID162_TACHO_DIV, ++ .capability = NVSW_REG_TACHO_SPEED_OFFSET, ++ }, ++}; + -+ nvsw_core_exit(nvsw_core); -+} ++static struct mlxreg_core_platform_data nvsw_bmc_hid162_fan = { ++ .data = nvsw_bmc_hid162_fan_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid162_fan_data), ++ .capability = NVSW_REG_FAN_DRW_CAP_OFFSET, ++ .version = 1, ++}; + -+static const struct i2c_device_id nvsw_bmc_hid162_id[] = { -+ { "hid162", HID162 }, -+ { "hid176", HID176 }, -+ { "hid177", HID177 }, -+ { "hid180", HID180 }, -+ { }, ++/* Platform led data for HI162 system type. */ ++static struct mlxreg_core_data nvsw_bmc_hid162_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan:green", ++ .reg = NVSW_REG_LED6_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan:amber", ++ .reg = NVSW_REG_LED6_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, +}; -+MODULE_DEVICE_TABLE(i2c, nvsw_bmc_hid162_id); + -+static const struct of_device_id nvsw_bmc_hid162_dt_match[] = { -+ { .compatible = "nvidia,hid162" }, -+ { .compatible = "nvidia,hid176" }, -+ { .compatible = "nvidia,hid177" }, -+ { .compatible = "nvidia,hid180" }, -+ { }, ++static struct mlxreg_core_platform_data nvsw_bmc_hid162_led = { ++ .data = nvsw_bmc_hid162_led_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid162_led_data), +}; -+MODULE_DEVICE_TABLE(of, nvsw_bmc_hid162_dt_match); + -+static struct i2c_driver nvsw_bmc_hid162_driver = { -+ .driver = { -+ .name = "nvsw-bmc-hid162", -+ .of_match_table = of_match_ptr(nvsw_bmc_hid162_dt_match), ++/* Platform led data for HI1676 system type. */ ++static struct mlxreg_core_data nvsw_bmc_hid176_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "leakage:green", ++ .reg = NVSW_REG_LED7_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "leakage:amber", ++ .reg = NVSW_REG_LED7_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, + }, -+ .probe = nvsw_bmc_hid162_probe, -+ .remove = nvsw_bmc_hid162_remove, -+ .id_table = nvsw_bmc_hid162_id, +}; + -+module_i2c_driver(nvsw_bmc_hid162_driver); ++static struct mlxreg_core_platform_data nvsw_bmc_hid176_led = { ++ .data = nvsw_bmc_hid176_led_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid176_led_data), ++}; + -+MODULE_AUTHOR("Vadim Pasternak "); -+MODULE_DESCRIPTION("Nvidia platform driver"); -+MODULE_LICENSE("Dual BSD/GPL"); -diff --git a/drivers/platform/mellanox/nvsw-core.c b/drivers/platform/mellanox/nvsw-core.c -new file mode 100644 -index 000000000..1012da6a6 ---- /dev/null -+++ b/drivers/platform/mellanox/nvsw-core.c -@@ -0,0 +1,685 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Nvidia BMC platform driver -+ * -+ * Copyright (C) 2025 Nvidia Technologies Ltd. -+ */ ++/* Platform led data for HI1676 system type. */ ++static struct mlxreg_core_data nvsw_bmc_hid177_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++}; + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "nvsw.h" ++static struct mlxreg_core_platform_data nvsw_bmc_hid177_led = { ++ .data = nvsw_bmc_hid177_led_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid177_led_data), ++}; + -+static bool nvsw_writeable_reg(struct device *dev, unsigned int reg) ++/* Mux init/exit callbacks. */ ++static int nvsw_bmc_hid162_mux_topology_init(struct nvsw_core *nvsw_core) +{ -+ switch (reg) { -+ case NVSW_REG_PG1_EVENT_OFFSET: -+ case NVSW_REG_PG1_MASK_OFFSET: -+ case NVSW_REG_PG2_EVENT_OFFSET: -+ case NVSW_REG_PG2_MASK_OFFSET: -+ case NVSW_REG_PG3_EVENT_OFFSET: -+ case NVSW_REG_PG3_MASK_OFFSET: -+ case NVSW_REG_PG4_EVENT_OFFSET: -+ case NVSW_REG_PG4_MASK_OFFSET: -+ case NVSW_REG_RESET_GP1_OFFSET: -+ case NVSW_REG_FIELD_UPGRADE: -+ case NVSW_REG_GP0_OFFSET: -+ case NVSW_REG_GP1_OFFSET: -+ case NVSW_REG_GP7_OFFSET: -+ case NVSW_REG_PWM_CONTROL_OFFSET: -+ case NVSW_REG_RESET_GP2_OFFSET: -+ case NVSW_REG_GP4_OFFSET: -+ case NVSW_REG_GP5_OFFSET: -+ case NVSW_REG_GP6_OFFSET: -+ case NVSW_REG_LED1_OFFSET: -+ case NVSW_REG_LED5_OFFSET: -+ case NVSW_REG_LED6_OFFSET: -+ case NVSW_REG_LED7_OFFSET: -+ case NVSW_REG_AGGRCO_MASK_OFFSET: -+ case NVSW_REG_HEALTH_EVENT_OFFSET: -+ case NVSW_REG_HEALTH_MASK_OFFSET: -+ case NVSW_REG_AGGR_MASK_OFFSET: -+ case NVSW_REG_FU_CAP_OFFSET: -+ case NVSW_REG_BRD4_EVENT_OFFSET: -+ case NVSW_REG_BRD4_MASK_OFFSET: -+ case NVSW_REG_AGGRLO_MASK_OFFSET: -+ case NVSW_REG_BRD1_EVENT_OFFSET: -+ case NVSW_REG_BRD1_MASK_OFFSET: -+ case NVSW_REG_ASIC1_EVENT_OFFSET: -+ case NVSW_REG_ASIC1_MASK_OFFSET: -+ case NVSW_REG_ASIC2_EVENT_OFFSET: -+ case NVSW_REG_ASIC2_MASK_OFFSET: -+ case NVSW_REG_ASIC3_EVENT_OFFSET: -+ case NVSW_REG_ASIC3_MASK_OFFSET: -+ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: -+ case NVSW_REG_VR1_ALERT_MASK_OFFSET: -+ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: -+ case NVSW_REG_VR2_ALERT_MASK_OFFSET: -+ case NVSW_REG_FAN_EVENT_OFFSET: -+ case NVSW_REG_FAN_MASK_OFFSET: -+ case NVSW_REG_PWRB_EVENT_OFFSET: -+ case NVSW_REG_PWRB_MASK_OFFSET: -+ case NVSW_REG_EROT_EVENT_OFFSET: -+ case NVSW_REG_EROT_MASK_OFFSET: -+ case NVSW_REG_EROT_ERR_EVENT_OFFSET: -+ case NVSW_REG_EROT_ERR_MASK_OFFSET: -+ case NVSW_REG_FRU1_EVENT_OFFSET: -+ case NVSW_REG_FRU1_MASK_OFFSET: -+ case NVSW_REG_LEAK_EVENT_OFFSET: -+ case NVSW_REG_LEAK_MASK_OFFSET: -+ case NVSW_REG_SPI_CHNL_SELECT: -+ case NVSW_REG_WD2_TMR_OFFSET: -+ case NVSW_REG_WD2_TLEFT_OFFSET: -+ case NVSW_REG_WD2_ACT_OFFSET: -+ case NVSW_REG_WD3_TMR_OFFSET: -+ case NVSW_REG_WD3_TLEFT_OFFSET: -+ case NVSW_REG_WD3_ACT_OFFSET: -+ case NVSW_REG_PWM1_OFFSET: -+ case NVSW_REG_MUX0_OFFSET: -+ case NVSW_REG_MUX1_OFFSET: -+ case NVSW_REG_MUX2_OFFSET: -+ return true; ++ int i, err; ++ ++ /* Create mux infrastructure. */ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i]->regmap = nvsw_core->regmap; ++ nvsw_core->mux[i] = platform_device_register_resndata(nvsw_core->dev, ++ "i2c-mux-regmap", i, NULL, 0, ++ mux_data[i], ++ sizeof(*mux_data[i])); ++ if (IS_ERR(nvsw_core->mux[i])) { ++ dev_err(nvsw_core->dev, "Failed to create mux infra\n"); ++ err = PTR_ERR(nvsw_core->mux[i]); ++ goto fail_platform_mux_register; ++ } + } -+ return false; ++ ++ return 0; ++fail_platform_mux_register: ++ while (--i >= 0) ++ platform_device_unregister(nvsw_core->mux[i]); ++ return err; +} + -+static bool nvsw_readable_reg(struct device *dev, unsigned int reg) ++static void nvsw_bmc_hid162_mux_topology_exit(struct nvsw_core *nvsw_core) +{ -+ switch (reg) { -+ case NVSW_REG_CPLD1_VER_OFFSET: -+ case NVSW_REG_CPLD1_PN_OFFSET: -+ case NVSW_REG_CPLD1_PN1_OFFSET: -+ case NVSW_REG_CPLD2_VER_OFFSET: -+ case NVSW_REG_CPLD2_PN_OFFSET: -+ case NVSW_REG_CPLD2_PN1_OFFSET: -+ case NVSW_REG_CPLD3_VER_OFFSET: -+ case NVSW_REG_CPLD3_PN_OFFSET: -+ case NVSW_REG_CPLD3_PN1_OFFSET: -+ case NVSW_REG_CPLD4_VER_OFFSET: -+ case NVSW_REG_CPLD4_PN_OFFSET: -+ case NVSW_REG_CPLD4_PN1_OFFSET: -+ case NVSW_REG_CPLD7_VER_OFFSET: -+ case NVSW_REG_PG1_OFFSET: -+ case NVSW_REG_PG1_EVENT_OFFSET: -+ case NVSW_REG_PG1_MASK_OFFSET: -+ case NVSW_REG_PG2_OFFSET: -+ case NVSW_REG_PG2_EVENT_OFFSET: -+ case NVSW_REG_PG2_MASK_OFFSET: -+ case NVSW_REG_PG3_OFFSET: -+ case NVSW_REG_PG3_EVENT_OFFSET: -+ case NVSW_REG_PG3_MASK_OFFSET: -+ case NVSW_REG_PG4_OFFSET: -+ case NVSW_REG_PG4_EVENT_OFFSET: -+ case NVSW_REG_PG4_MASK_OFFSET: -+ case NVSW_REG_CPLD6_VER_OFFSET: -+ case NVSW_REG_CPLD6_PN_OFFSET: -+ case NVSW_REG_CPLD6_PN1_OFFSET: -+ case NVSW_REG_CPLD9_VER_OFFSET: -+ case NVSW_REG_CPLD10_PN_OFFSET: -+ case NVSW_REG_CPLD10_PN1_OFFSET: -+ case NVSW_REG_RESET_GP1_OFFSET: -+ case NVSW_REG_FIELD_UPGRADE: -+ case NVSW_REG_SAFE_BIOS_OFFSET: -+ case NVSW_REG_RESET_CAUSE_OFFSET: -+ case NVSW_REG_RESET_CAUSE1_OFFSET: -+ case NVSW_REG_RESET_CAUSE2_OFFSET: -+ case NVSW_REG_LED1_OFFSET: -+ case NVSW_REG_LED5_OFFSET: -+ case NVSW_REG_LED6_OFFSET: -+ case NVSW_REG_LED7_OFFSET: -+ case NVSW_REG_CPLD7_PN_OFFSET: -+ case NVSW_REG_CPLD7_PN1_OFFSET: -+ case NVSW_REG_RESET_GP2_OFFSET: -+ case NVSW_REG_GP0_RO_OFFSET: -+ case NVSW_REG_GP1_RO_OFFSET: -+ case NVSW_REG_GP4_RO_OFFSET: -+ case NVSW_REG_GP5_RO_OFFSET: -+ case NVSW_REG_GPCOM0_OFFSET: -+ case NVSW_REG_GP0_OFFSET: -+ case NVSW_REG_GP1_OFFSET: -+ case NVSW_REG_GP7_OFFSET: -+ case NVSW_REG_PWM_CONTROL_OFFSET: -+ case NVSW_REG_GP4_OFFSET: -+ case NVSW_REG_GP5_OFFSET: -+ case NVSW_REG_GP6_OFFSET: -+ case NVSW_REG_AGGRCO_OFFSET: -+ case NVSW_REG_AGGRCO_MASK_OFFSET: -+ case NVSW_REG_HEALTH_OFFSET: -+ case NVSW_REG_HEALTH_EVENT_OFFSET: -+ case NVSW_REG_HEALTH_MASK_OFFSET: -+ case NVSW_REG_AGGR_OFFSET: -+ case NVSW_REG_AGGR_MASK_OFFSET: -+ case NVSW_REG_FU_CAP_OFFSET: -+ case NVSW_REG_BRD4_OFFSET: -+ case NVSW_REG_BRD4_EVENT_OFFSET: -+ case NVSW_REG_BRD4_MASK_OFFSET: -+ case NVSW_REG_AGGRLO_OFFSET: -+ case NVSW_REG_AGGRLO_MASK_OFFSET: -+ case NVSW_REG_BRD1_OFFSET: -+ case NVSW_REG_BRD1_EVENT_OFFSET: -+ case NVSW_REG_BRD1_MASK_OFFSET: -+ case NVSW_REG_ASIC1_HEALTH_OFFSET: -+ case NVSW_REG_ASIC1_EVENT_OFFSET: -+ case NVSW_REG_ASIC1_MASK_OFFSET: -+ case NVSW_REG_ASIC2_HEALTH_OFFSET: -+ case NVSW_REG_ASIC2_EVENT_OFFSET: -+ case NVSW_REG_ASIC2_MASK_OFFSET: -+ case NVSW_REG_ASIC3_HEALTH_OFFSET: -+ case NVSW_REG_ASIC3_EVENT_OFFSET: -+ case NVSW_REG_ASIC3_MASK_OFFSET: -+ case NVSW_REG_VR1_ALERT_OFFSET: -+ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: -+ case NVSW_REG_VR1_ALERT_MASK_OFFSET: -+ case NVSW_REG_VR2_ALERT_OFFSET: -+ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: -+ case NVSW_REG_VR2_ALERT_MASK_OFFSET: -+ case NVSW_REG_CPLD8_PN_OFFSET: -+ case NVSW_REG_CPLD8_PN1_OFFSET: -+ case NVSW_REG_CPLD8_VER_OFFSET: -+ case NVSW_REG_FAN_OFFSET: -+ case NVSW_REG_FAN_EVENT_OFFSET: -+ case NVSW_REG_FAN_MASK_OFFSET: -+ case NVSW_REG_CPLD5_VER_OFFSET: -+ case NVSW_REG_CPLD5_PN_OFFSET: -+ case NVSW_REG_CPLD5_PN1_OFFSET: -+ case NVSW_REG_EROT_OFFSET: -+ case NVSW_REG_EROT_EVENT_OFFSET: -+ case NVSW_REG_EROT_MASK_OFFSET: -+ case NVSW_REG_EROT_ERR_OFFSET: -+ case NVSW_REG_EROT_ERR_EVENT_OFFSET: -+ case NVSW_REG_EROT_ERR_MASK_OFFSET: -+ case NVSW_REG_PWRB_OFFSET: -+ case NVSW_REG_PWRB_EVENT_OFFSET: -+ case NVSW_REG_PWRB_MASK_OFFSET: -+ case NVSW_REG_FRU1_OFFSET: -+ case NVSW_REG_FRU1_EVENT_OFFSET: -+ case NVSW_REG_FRU1_MASK_OFFSET: -+ case NVSW_REG_LEAK_OFFSET: -+ case NVSW_REG_LEAK_EVENT_OFFSET: -+ case NVSW_REG_LEAK_MASK_OFFSET: -+ case NVSW_REG_CPLD1_MVER_OFFSET: -+ case NVSW_REG_CPLD2_MVER_OFFSET: -+ case NVSW_REG_CPLD3_MVER_OFFSET: -+ case NVSW_REG_CPLD4_MVER_OFFSET: -+ case NVSW_REG_PWM1_OFFSET: -+ case NVSW_REG_TACHO1_OFFSET: -+ case NVSW_REG_TACHO2_OFFSET: -+ case NVSW_REG_TACHO3_OFFSET: -+ case NVSW_REG_TACHO4_OFFSET: -+ case NVSW_REG_TACHO5_OFFSET: -+ case NVSW_REG_TACHO6_OFFSET: -+ case NVSW_REG_TACHO7_OFFSET: -+ case NVSW_REG_TACHO8_OFFSET: -+ case NVSW_REG_TACHO9_OFFSET: -+ case NVSW_REG_TACHO10_OFFSET: -+ case NVSW_REG_TACHO11_OFFSET: -+ case NVSW_REG_TACHO12_OFFSET: -+ case NVSW_REG_FAN_CAP1_OFFSET: -+ case NVSW_REG_FAN_DRW_CAP_OFFSET: -+ case NVSW_REG_TACHO_SPEED_OFFSET: -+ case NVSW_REG_CONFIG1_OFFSET: -+ case NVSW_REG_CONFIG2_OFFSET: -+ case NVSW_REG_CONFIG3_OFFSET: -+ case NVSW_REG_SPI_CHNL_SELECT: -+ case NVSW_REG_CPLD5_MVER_OFFSET: -+ case NVSW_REG_CPLD9_PN_OFFSET: -+ case NVSW_REG_CPLD9_PN1_OFFSET: -+ case NVSW_REG_CPLD10_VER_OFFSET: -+ case NVSW_REG_WD2_TMR_OFFSET: -+ case NVSW_REG_WD2_TLEFT_OFFSET: -+ case NVSW_REG_WD2_ACT_OFFSET: -+ case NVSW_REG_WD3_TMR_OFFSET: -+ case NVSW_REG_WD3_TLEFT_OFFSET: -+ case NVSW_REG_WD3_ACT_OFFSET: -+ case NVSW_REG_CPLD7_MVER_OFFSET: -+ case NVSW_REG_CPLD8_MVER_OFFSET: -+ case NVSW_REG_CPLD9_MVER_OFFSET: -+ case NVSW_REG_CPLD10_MVER_OFFSET: -+ case NVSW_REG_CPLD6_MVER_OFFSET: -+ case NVSW_REG_MUX0_OFFSET: -+ case NVSW_REG_MUX1_OFFSET: -+ case NVSW_REG_MUX2_OFFSET: -+ case NVSW_REG_UFM_VERSION_OFFSET: -+ case NVSW_REG_PSU_I2C_CAP_OFFSET: -+ return true; ++ int i; ++ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ if (nvsw_core->mux[i]) ++ platform_device_unregister(nvsw_core->mux[i]); + } -+ return false; +} + -+static bool nvsw_volatile_reg(struct device *dev, unsigned int reg) ++/* Callback to set initial values for specific registers. */ ++static int nvsw_bmc_hid162_set_reg_default(struct regmap *regmap) +{ -+ switch (reg) { -+ case NVSW_REG_CPLD1_VER_OFFSET: -+ case NVSW_REG_CPLD1_PN_OFFSET: -+ case NVSW_REG_CPLD1_PN1_OFFSET: -+ case NVSW_REG_CPLD2_VER_OFFSET: -+ case NVSW_REG_CPLD2_PN_OFFSET: -+ case NVSW_REG_CPLD2_PN1_OFFSET: -+ case NVSW_REG_CPLD3_VER_OFFSET: -+ case NVSW_REG_CPLD3_PN_OFFSET: -+ case NVSW_REG_CPLD3_PN1_OFFSET: -+ case NVSW_REG_CPLD4_VER_OFFSET: -+ case NVSW_REG_CPLD4_PN_OFFSET: -+ case NVSW_REG_CPLD4_PN1_OFFSET: -+ case NVSW_REG_CPLD7_VER_OFFSET: -+ case NVSW_REG_PG1_OFFSET: -+ case NVSW_REG_PG1_EVENT_OFFSET: -+ case NVSW_REG_PG1_MASK_OFFSET: -+ case NVSW_REG_PG2_OFFSET: -+ case NVSW_REG_PG2_EVENT_OFFSET: -+ case NVSW_REG_PG2_MASK_OFFSET: -+ case NVSW_REG_PG3_OFFSET: -+ case NVSW_REG_PG3_EVENT_OFFSET: -+ case NVSW_REG_PG3_MASK_OFFSET: -+ case NVSW_REG_PG4_OFFSET: -+ case NVSW_REG_PG4_EVENT_OFFSET: -+ case NVSW_REG_PG4_MASK_OFFSET: -+ case NVSW_REG_CPLD6_VER_OFFSET: -+ case NVSW_REG_CPLD6_PN_OFFSET: -+ case NVSW_REG_CPLD6_PN1_OFFSET: -+ case NVSW_REG_CPLD9_VER_OFFSET: -+ case NVSW_REG_CPLD10_PN_OFFSET: -+ case NVSW_REG_CPLD10_PN1_OFFSET: -+ case NVSW_REG_RESET_GP1_OFFSET: -+ case NVSW_REG_FIELD_UPGRADE: -+ case NVSW_REG_SAFE_BIOS_OFFSET: -+ case NVSW_REG_RESET_CAUSE_OFFSET: -+ case NVSW_REG_RESET_CAUSE1_OFFSET: -+ case NVSW_REG_RESET_CAUSE2_OFFSET: -+ case NVSW_REG_LED1_OFFSET: -+ case NVSW_REG_LED5_OFFSET: -+ case NVSW_REG_LED6_OFFSET: -+ case NVSW_REG_LED7_OFFSET: -+ case NVSW_REG_CPLD7_PN_OFFSET: -+ case NVSW_REG_CPLD7_PN1_OFFSET: -+ case NVSW_REG_RESET_GP2_OFFSET: -+ case NVSW_REG_GP0_RO_OFFSET: -+ case NVSW_REG_GP1_RO_OFFSET: -+ case NVSW_REG_GPCOM0_OFFSET: -+ case NVSW_REG_GP0_OFFSET: -+ case NVSW_REG_GP1_OFFSET: -+ case NVSW_REG_GP7_OFFSET: -+ case NVSW_REG_PWM_CONTROL_OFFSET: -+ case NVSW_REG_GP4_OFFSET: -+ case NVSW_REG_GP5_OFFSET: -+ case NVSW_REG_GP6_OFFSET: -+ case NVSW_REG_AGGRCO_OFFSET: -+ case NVSW_REG_AGGRCO_MASK_OFFSET: -+ case NVSW_REG_HEALTH_OFFSET: -+ case NVSW_REG_HEALTH_EVENT_OFFSET: -+ case NVSW_REG_HEALTH_MASK_OFFSET: -+ case NVSW_REG_AGGR_OFFSET: -+ case NVSW_REG_AGGR_MASK_OFFSET: -+ case NVSW_REG_FU_CAP_OFFSET: -+ case NVSW_REG_BRD4_OFFSET: -+ case NVSW_REG_BRD4_EVENT_OFFSET: -+ case NVSW_REG_BRD4_MASK_OFFSET: -+ case NVSW_REG_AGGRLO_OFFSET: -+ case NVSW_REG_AGGRLO_MASK_OFFSET: -+ case NVSW_REG_BRD1_OFFSET: -+ case NVSW_REG_BRD1_EVENT_OFFSET: -+ case NVSW_REG_BRD1_MASK_OFFSET: -+ case NVSW_REG_ASIC1_HEALTH_OFFSET: -+ case NVSW_REG_ASIC1_EVENT_OFFSET: -+ case NVSW_REG_ASIC1_MASK_OFFSET: -+ case NVSW_REG_ASIC2_HEALTH_OFFSET: -+ case NVSW_REG_ASIC2_EVENT_OFFSET: -+ case NVSW_REG_ASIC2_MASK_OFFSET: -+ case NVSW_REG_ASIC3_HEALTH_OFFSET: -+ case NVSW_REG_ASIC3_EVENT_OFFSET: -+ case NVSW_REG_ASIC3_MASK_OFFSET: -+ case NVSW_REG_VR1_ALERT_OFFSET: -+ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: -+ case NVSW_REG_VR1_ALERT_MASK_OFFSET: -+ case NVSW_REG_VR2_ALERT_OFFSET: -+ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: -+ case NVSW_REG_VR2_ALERT_MASK_OFFSET: -+ case NVSW_REG_CPLD8_PN_OFFSET: -+ case NVSW_REG_CPLD8_PN1_OFFSET: -+ case NVSW_REG_CPLD8_VER_OFFSET: -+ case NVSW_REG_FAN_OFFSET: -+ case NVSW_REG_FAN_EVENT_OFFSET: -+ case NVSW_REG_FAN_MASK_OFFSET: -+ case NVSW_REG_CPLD5_VER_OFFSET: -+ case NVSW_REG_CPLD5_PN_OFFSET: -+ case NVSW_REG_CPLD5_PN1_OFFSET: -+ case NVSW_REG_EROT_OFFSET: -+ case NVSW_REG_EROT_EVENT_OFFSET: -+ case NVSW_REG_EROT_MASK_OFFSET: -+ case NVSW_REG_EROT_ERR_OFFSET: -+ case NVSW_REG_EROT_ERR_EVENT_OFFSET: -+ case NVSW_REG_EROT_ERR_MASK_OFFSET: -+ case NVSW_REG_PWRB_OFFSET: -+ case NVSW_REG_PWRB_EVENT_OFFSET: -+ case NVSW_REG_PWRB_MASK_OFFSET: -+ case NVSW_REG_FRU1_OFFSET: -+ case NVSW_REG_FRU1_EVENT_OFFSET: -+ case NVSW_REG_FRU1_MASK_OFFSET: -+ case NVSW_REG_LEAK_OFFSET: -+ case NVSW_REG_LEAK_EVENT_OFFSET: -+ case NVSW_REG_LEAK_MASK_OFFSET: -+ case NVSW_REG_GP4_RO_OFFSET: -+ case NVSW_REG_GP5_RO_OFFSET: -+ case NVSW_REG_CPLD1_MVER_OFFSET: -+ case NVSW_REG_CPLD2_MVER_OFFSET: -+ case NVSW_REG_CPLD3_MVER_OFFSET: -+ case NVSW_REG_CPLD4_MVER_OFFSET: -+ case NVSW_REG_PWM1_OFFSET: -+ case NVSW_REG_TACHO1_OFFSET: -+ case NVSW_REG_TACHO2_OFFSET: -+ case NVSW_REG_TACHO3_OFFSET: -+ case NVSW_REG_TACHO4_OFFSET: -+ case NVSW_REG_TACHO5_OFFSET: -+ case NVSW_REG_TACHO6_OFFSET: -+ case NVSW_REG_TACHO7_OFFSET: -+ case NVSW_REG_TACHO8_OFFSET: -+ case NVSW_REG_TACHO9_OFFSET: -+ case NVSW_REG_TACHO10_OFFSET: -+ case NVSW_REG_TACHO11_OFFSET: -+ case NVSW_REG_TACHO12_OFFSET: -+ case NVSW_REG_FAN_CAP1_OFFSET: -+ case NVSW_REG_FAN_DRW_CAP_OFFSET: -+ case NVSW_REG_TACHO_SPEED_OFFSET: -+ case NVSW_REG_CONFIG1_OFFSET: -+ case NVSW_REG_CONFIG2_OFFSET: -+ case NVSW_REG_CONFIG3_OFFSET: -+ case NVSW_REG_SPI_CHNL_SELECT: -+ case NVSW_REG_CPLD5_MVER_OFFSET: -+ case NVSW_REG_CPLD9_PN_OFFSET: -+ case NVSW_REG_CPLD9_PN1_OFFSET: -+ case NVSW_REG_CPLD10_VER_OFFSET: -+ case NVSW_REG_WD2_TMR_OFFSET: -+ case NVSW_REG_WD2_TLEFT_OFFSET: -+ case NVSW_REG_WD2_ACT_OFFSET: -+ case NVSW_REG_CPLD7_MVER_OFFSET: -+ case NVSW_REG_CPLD8_MVER_OFFSET: -+ case NVSW_REG_CPLD9_MVER_OFFSET: -+ case NVSW_REG_CPLD10_MVER_OFFSET: -+ case NVSW_REG_CPLD6_MVER_OFFSET: -+ case NVSW_REG_WD3_TMR_OFFSET: -+ case NVSW_REG_WD3_TLEFT_OFFSET: -+ case NVSW_REG_WD3_ACT_OFFSET: -+ case NVSW_REG_MUX0_OFFSET: -+ case NVSW_REG_MUX1_OFFSET: -+ case NVSW_REG_MUX2_OFFSET: -+ case NVSW_REG_UFM_VERSION_OFFSET: -+ case NVSW_REG_PSU_I2C_CAP_OFFSET: -+ return true; -+ } -+ return false; ++ u32 regval; ++ int err; ++ ++ err = regmap_read(regmap, NVSW_REG_GP6_OFFSET, ®val); ++ if (err) ++ return err; ++ ++ return regmap_write(regmap, NVSW_REG_GP6_OFFSET, regval | NVSW_REG_RESET_MASK); +} + -+/* Configuration for the register map of a device with 2 bytes address space. */ -+static const struct reg_default nvsw_core_reg_def[] = { -+ { NVSW_REG_AGGRCO_MASK_OFFSET, GENMASK(1, 0)}, -+ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, ++static int nvsw_bmc_hid180_set_reg_default(struct regmap *regmap) ++{ ++ return regmap_write(regmap, NVSW_REG_AGGRCO_MASK_OFFSET, GENMASK(5, 0)); ++} ++ ++/* Callback is used to indicate that all adapter devices has been created. */ ++static int ++nvsw_bmc_hid162_completion_notify(void *handle, struct i2c_adapter *parent, ++ struct i2c_adapter *adapters[]) ++{ ++ /* struct nvsw_core *nvsw_core = handle; */ ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid162_mux_access_grant(void *handle) ++{ ++ struct nvsw_core *nvsw_core = handle; ++ u32 regval; ++ int err; ++ ++ err = regmap_read(nvsw_core->regmap, NVSW_REG_GP1_OFFSET, ®val); ++ if (err) ++ return err; ++ ++ return regval & NVSW_MASTER_MASK; ++} ++ ++static int nvsw_bmc_hid162_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID162; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid162_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid162_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_data[i]->mux_access_grant = nvsw_bmc_hid162_mux_access_grant; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid162_led; ++ nvsw_core->fan_data = &nvsw_bmc_hid162_fan; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid162_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid176_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID176; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid176_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid176_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_data[i]->mux_access_grant = nvsw_bmc_hid162_mux_access_grant; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid176_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid176_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid177_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID177; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid176_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid176_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_data[i]->mux_access_grant = nvsw_bmc_hid162_mux_access_grant; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid177_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid177_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid180_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID180; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid180_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid180_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_data[i]->mux_access_grant = nvsw_bmc_hid162_mux_access_grant; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid180_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid177_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid180_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid180_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid185_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID180; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid185_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid185_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ mux_data[0]->mux_access_grant = nvsw_bmc_hid162_mux_access_grant; ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid180_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid177_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid185_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid180_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_platform_data_init(struct nvsw_core *nvsw_core, enum nvsw_core_hid_type type) ++{ ++ switch (type) { ++ case HID162: ++ return nvsw_bmc_hid162_platform_data_init(nvsw_core); ++ case HID176: ++ return nvsw_bmc_hid176_platform_data_init(nvsw_core); ++ case HID177: ++ return nvsw_bmc_hid177_platform_data_init(nvsw_core); ++ case HID180: ++ return nvsw_bmc_hid180_platform_data_init(nvsw_core); ++ case HID185: ++ return nvsw_bmc_hid185_platform_data_init(nvsw_core); ++ default: ++ return -ENODEV; ++ } ++} ++ ++static int nvsw_bmc_hid162_probe(struct i2c_client *client) ++{ ++ struct device_node *np = client->dev.of_node; ++ enum nvsw_core_hid_type type; ++ struct nvsw_core *nvsw_core; ++ int err; ++ ++ if (!np) ++ return -ENODEV; ++ ++ if (of_device_is_compatible(np, "nvidia,hid162")) ++ type = HID162; ++ else if (of_device_is_compatible(np, "nvidia,hid176")) ++ type = HID176; ++ else if (of_device_is_compatible(np, "nvidia,hid177")) ++ type = HID177; ++ else if (of_device_is_compatible(np, "nvidia,hid180")) ++ type = HID180; ++ else if (of_device_is_compatible(np, "nvidia,hid185")) ++ type = HID185; ++ else ++ return -ENODEV; ++ ++ nvsw_core = devm_kzalloc(&client->dev, sizeof(*nvsw_core), GFP_KERNEL); ++ if (!nvsw_core) ++ return -ENOMEM; ++ ++ nvsw_core->dev = &client->dev; ++ nvsw_core->client = client; ++ nvsw_core->np = np; ++ nvsw_core->regmap_type = REGMAP_I2C; ++ i2c_set_clientdata(client, nvsw_core); ++ err = nvsw_bmc_platform_data_init(nvsw_core, type); ++ if (err) ++ return err; ++ ++ return nvsw_core_init(nvsw_core); ++} ++ ++static void nvsw_bmc_hid162_remove(struct i2c_client *client) ++{ ++ struct nvsw_core *nvsw_core = i2c_get_clientdata(client); ++ ++ nvsw_core_exit(nvsw_core); ++} ++ ++static const struct i2c_device_id nvsw_bmc_hid162_id[] = { ++ { "hid162", HID162 }, ++ { "hid176", HID176 }, ++ { "hid177", HID177 }, ++ { "hid180", HID180 }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(i2c, nvsw_bmc_hid162_id); ++ ++static const struct of_device_id nvsw_bmc_hid162_dt_match[] = { ++ { .compatible = "nvidia,hid162" }, ++ { .compatible = "nvidia,hid176" }, ++ { .compatible = "nvidia,hid177" }, ++ { .compatible = "nvidia,hid180" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, nvsw_bmc_hid162_dt_match); ++ ++static struct i2c_driver nvsw_bmc_hid162_driver = { ++ .driver = { ++ .name = "nvsw-bmc-hid162", ++ .of_match_table = of_match_ptr(nvsw_bmc_hid162_dt_match), ++ }, ++ .probe = nvsw_bmc_hid162_probe, ++ .remove = nvsw_bmc_hid162_remove, ++ .id_table = nvsw_bmc_hid162_id, ++}; ++ ++module_i2c_driver(nvsw_bmc_hid162_driver); ++ ++MODULE_AUTHOR("Vadim Pasternak "); ++MODULE_DESCRIPTION("Nvidia platform driver"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/platform/mellanox/nvsw-core.c b/drivers/platform/mellanox/nvsw-core.c +new file mode 100644 +index 000000000..0dae7e076 +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw-core.c +@@ -0,0 +1,693 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "nvsw.h" ++ ++static bool nvsw_writeable_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case NVSW_REG_PG1_EVENT_OFFSET: ++ case NVSW_REG_PG1_MASK_OFFSET: ++ case NVSW_REG_PG2_EVENT_OFFSET: ++ case NVSW_REG_PG2_MASK_OFFSET: ++ case NVSW_REG_PG3_EVENT_OFFSET: ++ case NVSW_REG_PG3_MASK_OFFSET: ++ case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_RESET_GP1_OFFSET: ++ case NVSW_REG_FIELD_UPGRADE: ++ case NVSW_REG_GP0_OFFSET: ++ case NVSW_REG_GP1_OFFSET: ++ case NVSW_REG_GP7_OFFSET: ++ case NVSW_REG_PWM_CONTROL_OFFSET: ++ case NVSW_REG_RESET_GP2_OFFSET: ++ case NVSW_REG_GP4_OFFSET: ++ case NVSW_REG_GP5_OFFSET: ++ case NVSW_REG_GP6_OFFSET: ++ case NVSW_REG_LED1_OFFSET: ++ case NVSW_REG_LED5_OFFSET: ++ case NVSW_REG_LED6_OFFSET: ++ case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_AGGRCO_MASK_OFFSET: ++ case NVSW_REG_HEALTH_EVENT_OFFSET: ++ case NVSW_REG_HEALTH_MASK_OFFSET: ++ case NVSW_REG_AGGR_MASK_OFFSET: ++ case NVSW_REG_FU_CAP_OFFSET: ++ case NVSW_REG_BRD4_EVENT_OFFSET: ++ case NVSW_REG_BRD4_MASK_OFFSET: ++ case NVSW_REG_AGGRLO_MASK_OFFSET: ++ case NVSW_REG_BRD1_EVENT_OFFSET: ++ case NVSW_REG_BRD1_MASK_OFFSET: ++ case NVSW_REG_ASIC1_EVENT_OFFSET: ++ case NVSW_REG_ASIC1_MASK_OFFSET: ++ case NVSW_REG_ASIC2_EVENT_OFFSET: ++ case NVSW_REG_ASIC2_MASK_OFFSET: ++ case NVSW_REG_ASIC3_EVENT_OFFSET: ++ case NVSW_REG_ASIC3_MASK_OFFSET: ++ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR1_ALERT_MASK_OFFSET: ++ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_PS_DC_OK_EVENT_OFFSET: ++ case NVSW_REG_PS_DC_OK_MASK_OFFSET: ++ case NVSW_REG_FAN_EVENT_OFFSET: ++ case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_PWRB_EVENT_OFFSET: ++ case NVSW_REG_PWRB_MASK_OFFSET: ++ case NVSW_REG_EROT_EVENT_OFFSET: ++ case NVSW_REG_EROT_MASK_OFFSET: ++ case NVSW_REG_EROT_ERR_EVENT_OFFSET: ++ case NVSW_REG_EROT_ERR_MASK_OFFSET: ++ case NVSW_REG_FRU1_EVENT_OFFSET: ++ case NVSW_REG_FRU1_MASK_OFFSET: ++ case NVSW_REG_LEAK_EVENT_OFFSET: ++ case NVSW_REG_LEAK_MASK_OFFSET: ++ case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_WD2_TMR_OFFSET: ++ case NVSW_REG_WD2_TLEFT_OFFSET: ++ case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_WD3_TMR_OFFSET: ++ case NVSW_REG_WD3_TLEFT_OFFSET: ++ case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_PWM1_OFFSET: ++ case NVSW_REG_MUX0_OFFSET: ++ case NVSW_REG_MUX1_OFFSET: ++ case NVSW_REG_MUX2_OFFSET: ++ return true; ++ } ++ return false; ++} ++ ++static bool nvsw_readable_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case NVSW_REG_CPLD1_VER_OFFSET: ++ case NVSW_REG_CPLD1_PN_OFFSET: ++ case NVSW_REG_CPLD1_PN1_OFFSET: ++ case NVSW_REG_CPLD2_VER_OFFSET: ++ case NVSW_REG_CPLD2_PN_OFFSET: ++ case NVSW_REG_CPLD2_PN1_OFFSET: ++ case NVSW_REG_CPLD3_VER_OFFSET: ++ case NVSW_REG_CPLD3_PN_OFFSET: ++ case NVSW_REG_CPLD3_PN1_OFFSET: ++ case NVSW_REG_CPLD4_VER_OFFSET: ++ case NVSW_REG_CPLD4_PN_OFFSET: ++ case NVSW_REG_CPLD4_PN1_OFFSET: ++ case NVSW_REG_CPLD7_VER_OFFSET: ++ case NVSW_REG_PG1_OFFSET: ++ case NVSW_REG_PG1_EVENT_OFFSET: ++ case NVSW_REG_PG1_MASK_OFFSET: ++ case NVSW_REG_PG2_OFFSET: ++ case NVSW_REG_PG2_EVENT_OFFSET: ++ case NVSW_REG_PG2_MASK_OFFSET: ++ case NVSW_REG_PG3_OFFSET: ++ case NVSW_REG_PG3_EVENT_OFFSET: ++ case NVSW_REG_PG3_MASK_OFFSET: ++ case NVSW_REG_PG4_OFFSET: ++ case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_CPLD6_VER_OFFSET: ++ case NVSW_REG_CPLD6_PN_OFFSET: ++ case NVSW_REG_CPLD6_PN1_OFFSET: ++ case NVSW_REG_CPLD9_VER_OFFSET: ++ case NVSW_REG_CPLD10_PN_OFFSET: ++ case NVSW_REG_CPLD10_PN1_OFFSET: ++ case NVSW_REG_RESET_GP1_OFFSET: ++ case NVSW_REG_FIELD_UPGRADE: ++ case NVSW_REG_SAFE_BIOS_OFFSET: ++ case NVSW_REG_RESET_CAUSE_OFFSET: ++ case NVSW_REG_RESET_CAUSE1_OFFSET: ++ case NVSW_REG_RESET_CAUSE2_OFFSET: ++ case NVSW_REG_LED1_OFFSET: ++ case NVSW_REG_LED5_OFFSET: ++ case NVSW_REG_LED6_OFFSET: ++ case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_CPLD7_PN_OFFSET: ++ case NVSW_REG_CPLD7_PN1_OFFSET: ++ case NVSW_REG_RESET_GP2_OFFSET: ++ case NVSW_REG_GP0_RO_OFFSET: ++ case NVSW_REG_GP1_RO_OFFSET: ++ case NVSW_REG_GP4_RO_OFFSET: ++ case NVSW_REG_GP5_RO_OFFSET: ++ case NVSW_REG_GPCOM0_OFFSET: ++ case NVSW_REG_GP0_OFFSET: ++ case NVSW_REG_GP1_OFFSET: ++ case NVSW_REG_GP7_OFFSET: ++ case NVSW_REG_PWM_CONTROL_OFFSET: ++ case NVSW_REG_GP4_OFFSET: ++ case NVSW_REG_GP5_OFFSET: ++ case NVSW_REG_GP6_OFFSET: ++ case NVSW_REG_AGGRCO_OFFSET: ++ case NVSW_REG_AGGRCO_MASK_OFFSET: ++ case NVSW_REG_HEALTH_OFFSET: ++ case NVSW_REG_HEALTH_EVENT_OFFSET: ++ case NVSW_REG_HEALTH_MASK_OFFSET: ++ case NVSW_REG_AGGR_OFFSET: ++ case NVSW_REG_AGGR_MASK_OFFSET: ++ case NVSW_REG_FU_CAP_OFFSET: ++ case NVSW_REG_BRD4_OFFSET: ++ case NVSW_REG_BRD4_EVENT_OFFSET: ++ case NVSW_REG_BRD4_MASK_OFFSET: ++ case NVSW_REG_AGGRLO_OFFSET: ++ case NVSW_REG_AGGRLO_MASK_OFFSET: ++ case NVSW_REG_BRD1_OFFSET: ++ case NVSW_REG_BRD1_EVENT_OFFSET: ++ case NVSW_REG_BRD1_MASK_OFFSET: ++ case NVSW_REG_ASIC1_HEALTH_OFFSET: ++ case NVSW_REG_ASIC1_EVENT_OFFSET: ++ case NVSW_REG_ASIC1_MASK_OFFSET: ++ case NVSW_REG_ASIC2_HEALTH_OFFSET: ++ case NVSW_REG_ASIC2_EVENT_OFFSET: ++ case NVSW_REG_ASIC2_MASK_OFFSET: ++ case NVSW_REG_ASIC3_HEALTH_OFFSET: ++ case NVSW_REG_ASIC3_EVENT_OFFSET: ++ case NVSW_REG_ASIC3_MASK_OFFSET: ++ case NVSW_REG_VR1_ALERT_OFFSET: ++ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR1_ALERT_MASK_OFFSET: ++ case NVSW_REG_VR2_ALERT_OFFSET: ++ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_PS_DC_OK_OFFSET: ++ case NVSW_REG_PS_DC_OK_EVENT_OFFSET: ++ case NVSW_REG_PS_DC_OK_MASK_OFFSET: ++ case NVSW_REG_CPLD8_PN_OFFSET: ++ case NVSW_REG_CPLD8_PN1_OFFSET: ++ case NVSW_REG_CPLD8_VER_OFFSET: ++ case NVSW_REG_FAN_OFFSET: ++ case NVSW_REG_FAN_EVENT_OFFSET: ++ case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_CPLD5_VER_OFFSET: ++ case NVSW_REG_CPLD5_PN_OFFSET: ++ case NVSW_REG_CPLD5_PN1_OFFSET: ++ case NVSW_REG_EROT_OFFSET: ++ case NVSW_REG_EROT_EVENT_OFFSET: ++ case NVSW_REG_EROT_MASK_OFFSET: ++ case NVSW_REG_EROT_ERR_OFFSET: ++ case NVSW_REG_EROT_ERR_EVENT_OFFSET: ++ case NVSW_REG_EROT_ERR_MASK_OFFSET: ++ case NVSW_REG_PWRB_OFFSET: ++ case NVSW_REG_PWRB_EVENT_OFFSET: ++ case NVSW_REG_PWRB_MASK_OFFSET: ++ case NVSW_REG_FRU1_OFFSET: ++ case NVSW_REG_FRU1_EVENT_OFFSET: ++ case NVSW_REG_FRU1_MASK_OFFSET: ++ case NVSW_REG_LEAK_OFFSET: ++ case NVSW_REG_LEAK_EVENT_OFFSET: ++ case NVSW_REG_LEAK_MASK_OFFSET: ++ case NVSW_REG_CPLD1_MVER_OFFSET: ++ case NVSW_REG_CPLD2_MVER_OFFSET: ++ case NVSW_REG_CPLD3_MVER_OFFSET: ++ case NVSW_REG_CPLD4_MVER_OFFSET: ++ case NVSW_REG_PWM1_OFFSET: ++ case NVSW_REG_TACHO1_OFFSET: ++ case NVSW_REG_TACHO2_OFFSET: ++ case NVSW_REG_TACHO3_OFFSET: ++ case NVSW_REG_TACHO4_OFFSET: ++ case NVSW_REG_TACHO5_OFFSET: ++ case NVSW_REG_TACHO6_OFFSET: ++ case NVSW_REG_TACHO7_OFFSET: ++ case NVSW_REG_TACHO8_OFFSET: ++ case NVSW_REG_TACHO9_OFFSET: ++ case NVSW_REG_TACHO10_OFFSET: ++ case NVSW_REG_TACHO11_OFFSET: ++ case NVSW_REG_TACHO12_OFFSET: ++ case NVSW_REG_FAN_CAP1_OFFSET: ++ case NVSW_REG_FAN_DRW_CAP_OFFSET: ++ case NVSW_REG_TACHO_SPEED_OFFSET: ++ case NVSW_REG_CONFIG1_OFFSET: ++ case NVSW_REG_CONFIG2_OFFSET: ++ case NVSW_REG_CONFIG3_OFFSET: ++ case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_CPLD5_MVER_OFFSET: ++ case NVSW_REG_CPLD9_PN_OFFSET: ++ case NVSW_REG_CPLD9_PN1_OFFSET: ++ case NVSW_REG_CPLD10_VER_OFFSET: ++ case NVSW_REG_WD2_TMR_OFFSET: ++ case NVSW_REG_WD2_TLEFT_OFFSET: ++ case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_WD3_TMR_OFFSET: ++ case NVSW_REG_WD3_TLEFT_OFFSET: ++ case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_CPLD7_MVER_OFFSET: ++ case NVSW_REG_CPLD8_MVER_OFFSET: ++ case NVSW_REG_CPLD9_MVER_OFFSET: ++ case NVSW_REG_CPLD10_MVER_OFFSET: ++ case NVSW_REG_CPLD6_MVER_OFFSET: ++ case NVSW_REG_MUX0_OFFSET: ++ case NVSW_REG_MUX1_OFFSET: ++ case NVSW_REG_MUX2_OFFSET: ++ case NVSW_REG_UFM_VERSION_OFFSET: ++ case NVSW_REG_PSU_I2C_CAP_OFFSET: ++ return true; ++ } ++ return false; ++} ++ ++static bool nvsw_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case NVSW_REG_CPLD1_VER_OFFSET: ++ case NVSW_REG_CPLD1_PN_OFFSET: ++ case NVSW_REG_CPLD1_PN1_OFFSET: ++ case NVSW_REG_CPLD2_VER_OFFSET: ++ case NVSW_REG_CPLD2_PN_OFFSET: ++ case NVSW_REG_CPLD2_PN1_OFFSET: ++ case NVSW_REG_CPLD3_VER_OFFSET: ++ case NVSW_REG_CPLD3_PN_OFFSET: ++ case NVSW_REG_CPLD3_PN1_OFFSET: ++ case NVSW_REG_CPLD4_VER_OFFSET: ++ case NVSW_REG_CPLD4_PN_OFFSET: ++ case NVSW_REG_CPLD4_PN1_OFFSET: ++ case NVSW_REG_CPLD7_VER_OFFSET: ++ case NVSW_REG_PG1_OFFSET: ++ case NVSW_REG_PG1_EVENT_OFFSET: ++ case NVSW_REG_PG1_MASK_OFFSET: ++ case NVSW_REG_PG2_OFFSET: ++ case NVSW_REG_PG2_EVENT_OFFSET: ++ case NVSW_REG_PG2_MASK_OFFSET: ++ case NVSW_REG_PG3_OFFSET: ++ case NVSW_REG_PG3_EVENT_OFFSET: ++ case NVSW_REG_PG3_MASK_OFFSET: ++ case NVSW_REG_PG4_OFFSET: ++ case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_CPLD6_VER_OFFSET: ++ case NVSW_REG_CPLD6_PN_OFFSET: ++ case NVSW_REG_CPLD6_PN1_OFFSET: ++ case NVSW_REG_CPLD9_VER_OFFSET: ++ case NVSW_REG_CPLD10_PN_OFFSET: ++ case NVSW_REG_CPLD10_PN1_OFFSET: ++ case NVSW_REG_RESET_GP1_OFFSET: ++ case NVSW_REG_FIELD_UPGRADE: ++ case NVSW_REG_SAFE_BIOS_OFFSET: ++ case NVSW_REG_RESET_CAUSE_OFFSET: ++ case NVSW_REG_RESET_CAUSE1_OFFSET: ++ case NVSW_REG_RESET_CAUSE2_OFFSET: ++ case NVSW_REG_LED1_OFFSET: ++ case NVSW_REG_LED5_OFFSET: ++ case NVSW_REG_LED6_OFFSET: ++ case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_CPLD7_PN_OFFSET: ++ case NVSW_REG_CPLD7_PN1_OFFSET: ++ case NVSW_REG_RESET_GP2_OFFSET: ++ case NVSW_REG_GP0_RO_OFFSET: ++ case NVSW_REG_GP1_RO_OFFSET: ++ case NVSW_REG_GPCOM0_OFFSET: ++ case NVSW_REG_GP0_OFFSET: ++ case NVSW_REG_GP1_OFFSET: ++ case NVSW_REG_GP7_OFFSET: ++ case NVSW_REG_PWM_CONTROL_OFFSET: ++ case NVSW_REG_GP4_OFFSET: ++ case NVSW_REG_GP5_OFFSET: ++ case NVSW_REG_GP6_OFFSET: ++ case NVSW_REG_AGGRCO_OFFSET: ++ case NVSW_REG_AGGRCO_MASK_OFFSET: ++ case NVSW_REG_HEALTH_OFFSET: ++ case NVSW_REG_HEALTH_EVENT_OFFSET: ++ case NVSW_REG_HEALTH_MASK_OFFSET: ++ case NVSW_REG_AGGR_OFFSET: ++ case NVSW_REG_AGGR_MASK_OFFSET: ++ case NVSW_REG_FU_CAP_OFFSET: ++ case NVSW_REG_BRD4_OFFSET: ++ case NVSW_REG_BRD4_EVENT_OFFSET: ++ case NVSW_REG_BRD4_MASK_OFFSET: ++ case NVSW_REG_AGGRLO_OFFSET: ++ case NVSW_REG_AGGRLO_MASK_OFFSET: ++ case NVSW_REG_BRD1_OFFSET: ++ case NVSW_REG_BRD1_EVENT_OFFSET: ++ case NVSW_REG_BRD1_MASK_OFFSET: ++ case NVSW_REG_ASIC1_HEALTH_OFFSET: ++ case NVSW_REG_ASIC1_EVENT_OFFSET: ++ case NVSW_REG_ASIC1_MASK_OFFSET: ++ case NVSW_REG_ASIC2_HEALTH_OFFSET: ++ case NVSW_REG_ASIC2_EVENT_OFFSET: ++ case NVSW_REG_ASIC2_MASK_OFFSET: ++ case NVSW_REG_ASIC3_HEALTH_OFFSET: ++ case NVSW_REG_ASIC3_EVENT_OFFSET: ++ case NVSW_REG_ASIC3_MASK_OFFSET: ++ case NVSW_REG_VR1_ALERT_OFFSET: ++ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR1_ALERT_MASK_OFFSET: ++ case NVSW_REG_VR2_ALERT_OFFSET: ++ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_PS_DC_OK_OFFSET: ++ case NVSW_REG_PS_DC_OK_EVENT_OFFSET: ++ case NVSW_REG_PS_DC_OK_MASK_OFFSET: ++ case NVSW_REG_CPLD8_PN_OFFSET: ++ case NVSW_REG_CPLD8_PN1_OFFSET: ++ case NVSW_REG_CPLD8_VER_OFFSET: ++ case NVSW_REG_FAN_OFFSET: ++ case NVSW_REG_FAN_EVENT_OFFSET: ++ case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_CPLD5_VER_OFFSET: ++ case NVSW_REG_CPLD5_PN_OFFSET: ++ case NVSW_REG_CPLD5_PN1_OFFSET: ++ case NVSW_REG_EROT_OFFSET: ++ case NVSW_REG_EROT_EVENT_OFFSET: ++ case NVSW_REG_EROT_MASK_OFFSET: ++ case NVSW_REG_EROT_ERR_OFFSET: ++ case NVSW_REG_EROT_ERR_EVENT_OFFSET: ++ case NVSW_REG_EROT_ERR_MASK_OFFSET: ++ case NVSW_REG_PWRB_OFFSET: ++ case NVSW_REG_PWRB_EVENT_OFFSET: ++ case NVSW_REG_PWRB_MASK_OFFSET: ++ case NVSW_REG_FRU1_OFFSET: ++ case NVSW_REG_FRU1_EVENT_OFFSET: ++ case NVSW_REG_FRU1_MASK_OFFSET: ++ case NVSW_REG_LEAK_OFFSET: ++ case NVSW_REG_LEAK_EVENT_OFFSET: ++ case NVSW_REG_LEAK_MASK_OFFSET: ++ case NVSW_REG_GP4_RO_OFFSET: ++ case NVSW_REG_GP5_RO_OFFSET: ++ case NVSW_REG_CPLD1_MVER_OFFSET: ++ case NVSW_REG_CPLD2_MVER_OFFSET: ++ case NVSW_REG_CPLD3_MVER_OFFSET: ++ case NVSW_REG_CPLD4_MVER_OFFSET: ++ case NVSW_REG_PWM1_OFFSET: ++ case NVSW_REG_TACHO1_OFFSET: ++ case NVSW_REG_TACHO2_OFFSET: ++ case NVSW_REG_TACHO3_OFFSET: ++ case NVSW_REG_TACHO4_OFFSET: ++ case NVSW_REG_TACHO5_OFFSET: ++ case NVSW_REG_TACHO6_OFFSET: ++ case NVSW_REG_TACHO7_OFFSET: ++ case NVSW_REG_TACHO8_OFFSET: ++ case NVSW_REG_TACHO9_OFFSET: ++ case NVSW_REG_TACHO10_OFFSET: ++ case NVSW_REG_TACHO11_OFFSET: ++ case NVSW_REG_TACHO12_OFFSET: ++ case NVSW_REG_FAN_CAP1_OFFSET: ++ case NVSW_REG_FAN_DRW_CAP_OFFSET: ++ case NVSW_REG_TACHO_SPEED_OFFSET: ++ case NVSW_REG_CONFIG1_OFFSET: ++ case NVSW_REG_CONFIG2_OFFSET: ++ case NVSW_REG_CONFIG3_OFFSET: ++ case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_CPLD5_MVER_OFFSET: ++ case NVSW_REG_CPLD9_PN_OFFSET: ++ case NVSW_REG_CPLD9_PN1_OFFSET: ++ case NVSW_REG_CPLD10_VER_OFFSET: ++ case NVSW_REG_WD2_TMR_OFFSET: ++ case NVSW_REG_WD2_TLEFT_OFFSET: ++ case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_CPLD7_MVER_OFFSET: ++ case NVSW_REG_CPLD8_MVER_OFFSET: ++ case NVSW_REG_CPLD9_MVER_OFFSET: ++ case NVSW_REG_CPLD10_MVER_OFFSET: ++ case NVSW_REG_CPLD6_MVER_OFFSET: ++ case NVSW_REG_WD3_TMR_OFFSET: ++ case NVSW_REG_WD3_TLEFT_OFFSET: ++ case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_MUX0_OFFSET: ++ case NVSW_REG_MUX1_OFFSET: ++ case NVSW_REG_MUX2_OFFSET: ++ case NVSW_REG_UFM_VERSION_OFFSET: ++ case NVSW_REG_PSU_I2C_CAP_OFFSET: ++ return true; ++ } ++ return false; ++} ++ ++/* Configuration for the register map of a device with 2 bytes address space. */ ++static const struct reg_default nvsw_core_reg_def[] = { ++ { NVSW_REG_AGGRCO_MASK_OFFSET, GENMASK(1, 0)}, ++ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, ++}; ++ ++static const struct regmap_config nvsw_regmap_i2c_conf = { ++ .reg_bits = 16, ++ .val_bits = 8, ++ .max_register = NVSW_REG_MAX, ++ .cache_type = REGCACHE_FLAT, ++ .reg_defaults = nvsw_core_reg_def, ++ .num_reg_defaults = ARRAY_SIZE(nvsw_core_reg_def), ++ .writeable_reg = nvsw_writeable_reg, ++ .readable_reg = nvsw_readable_reg, ++ .volatile_reg = nvsw_volatile_reg, ++}; ++ ++static const struct reg_default nvsw_reg_def_l1[] = { ++ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, ++ { NVSW_REG_WD2_ACT_OFFSET, 0x00 }, ++ { NVSW_REG_WD3_ACT_OFFSET, 0x00 }, ++ { NVSW_REG_LEAK_MASK_OFFSET, 0x3f }, ++}; ++ ++struct nvsw_io_regmap_context { ++ void __iomem *base; ++}; ++ ++static struct nvsw_io_regmap_context nvsw_io_regmap_ctx; ++ ++static int nvsw_reg_read(void *context, unsigned int reg, unsigned int *val) ++{ ++ struct nvsw_io_regmap_context *ctx = context; ++ ++ *val = ioread8(ctx->base - NVSW_REG_MIN + reg); ++ return 0; ++} ++ ++static int nvsw_reg_write(void *context, unsigned int reg, unsigned int val) ++{ ++ struct nvsw_io_regmap_context *ctx = context; ++ ++ iowrite8(val, ctx->base - NVSW_REG_MIN + reg); ++ return 0; ++} ++ ++static const struct regmap_config nvsw_regmap_conf_l1 = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = NVSW_REG_MAX, ++ .cache_type = REGCACHE_FLAT, ++ .writeable_reg = nvsw_writeable_reg, ++ .readable_reg = nvsw_readable_reg, ++ .volatile_reg = nvsw_volatile_reg, ++ .reg_defaults = nvsw_reg_def_l1, ++ .num_reg_defaults = ARRAY_SIZE(nvsw_reg_def_l1), ++ .reg_read = nvsw_reg_read, ++ .reg_write = nvsw_reg_write, ++}; ++ ++static int nvsw_core_platform_init(struct nvsw_core *nvsw_core) ++{ ++ int i, err; ++ ++ /* Add registers io access driver. */ ++ if (nvsw_core->regio_data) { ++ nvsw_core->regio_data->regmap = nvsw_core->regmap; ++ nvsw_core->regio = ++ platform_device_register_resndata(nvsw_core->dev, "mlxreg-io", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->regio_data, ++ sizeof(*nvsw_core->regio_data)); ++ if (IS_ERR(nvsw_core->regio)) { ++ err = PTR_ERR(nvsw_core->regio); ++ dev_err(nvsw_core->dev, "Failed to register mlxreg-io driver\n"); ++ goto fail_platform_io_register; ++ } ++ } ++ ++ /* Add FAN driver. */ ++ if (nvsw_core->fan_data) { ++ nvsw_core->fan_data->regmap = nvsw_core->regmap; ++ nvsw_core->fan = platform_device_register_resndata(nvsw_core->dev, "mlxreg-fan", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->fan_data, ++ sizeof(*nvsw_core->fan_data)); ++ if (IS_ERR(nvsw_core->fan)) { ++ err = PTR_ERR(nvsw_core->fan); ++ dev_err(nvsw_core->dev, "Failed to register mlxreg-fan driver\n"); ++ goto fail_platform_fan_register; ++ } ++ } ++ ++ /* Add LED driver. */ ++ if (nvsw_core->led_data) { ++ nvsw_core->led_data->regmap = nvsw_core->regmap; ++ nvsw_core->led = platform_device_register_resndata(nvsw_core->dev, "leds-mlxreg", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->led_data, ++ sizeof(*nvsw_core->led_data)); ++ if (IS_ERR(nvsw_core->led)) { ++ err = PTR_ERR(nvsw_core->led); ++ dev_err(nvsw_core->dev, "Failed to register leds-mlxreg driver\n"); ++ goto fail_platform_leds_register; ++ } ++ } ++ ++ /* Add hotplug driver. */ ++ if (nvsw_core->hotplug_data && nvsw_core->np) { ++ nvsw_core->hotplug_data->irq = nvsw_core->client->irq; ++ dev_info(nvsw_core->dev, "irq %d\n", nvsw_core->hotplug_data->irq); ++ nvsw_core->hotplug_data->regmap = nvsw_core->regmap; ++ nvsw_core->hotplug = ++ platform_device_register_resndata(nvsw_core->dev, "mlxreg-hotplug", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->hotplug_data, ++ sizeof(*nvsw_core->hotplug_data)); ++ if (IS_ERR(nvsw_core->hotplug)) { ++ err = PTR_ERR(nvsw_core->hotplug); ++ dev_err(nvsw_core->dev, "Failed to register mlxreg-hotplug driver\n"); ++ goto fail_platform_hotplug_register; ++ } ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(nvsw_core->wd_data); i++) { ++ if (nvsw_core->wd_data[i]) { ++ nvsw_core->wd_data[i]->regmap = nvsw_core->regmap; ++ nvsw_core->wd[i] = ++ platform_device_register_resndata(nvsw_core->dev, "mlx-wdt", i, ++ NULL, 0, nvsw_core->wd_data[i], ++ sizeof(*nvsw_core->wd_data[i])); ++ if (IS_ERR(nvsw_core->wd[i])) { ++ err = PTR_ERR(nvsw_core->wd[i]); ++ dev_err(nvsw_core->dev, "Failed to register mlx-wdt driver\n"); ++ goto fail_platform_wd_register; ++ } ++ } ++ } ++ ++ return 0; ++ ++fail_platform_wd_register: ++ while (i--) ++ platform_device_unregister(nvsw_core->wd[i]); ++ if (nvsw_core->hotplug_data) ++ platform_device_unregister(nvsw_core->hotplug); ++fail_platform_hotplug_register: ++ if (nvsw_core->led_data) ++ platform_device_unregister(nvsw_core->led); ++fail_platform_leds_register: ++ if (nvsw_core->fan_data) ++ platform_device_unregister(nvsw_core->fan); ++fail_platform_fan_register: ++ if (nvsw_core->regio_data) ++ platform_device_unregister(nvsw_core->regio); ++fail_platform_io_register: ++ return err; ++} ++ ++static void nvsw_core_platform_exit(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ for (i = NVSW_WD_MAX - 1; i >= 0; i--) ++ platform_device_unregister(nvsw_core->wd[i]); ++ if (nvsw_core->hotplug_data) ++ platform_device_unregister(nvsw_core->hotplug); ++ if (nvsw_core->led_data) ++ platform_device_unregister(nvsw_core->led); ++ if (nvsw_core->fan_data) ++ platform_device_unregister(nvsw_core->fan); ++ if (nvsw_core->regio_data) ++ platform_device_unregister(nvsw_core->regio); ++} ++ ++static int nvsw_core_mux_topology_init(struct nvsw_core *nvsw_core) ++{ ++ return nvsw_core->mux_init(nvsw_core); ++} ++ ++static void nvsw_core_mux_topology_exit(struct nvsw_core *nvsw_core) ++{ ++ nvsw_core->mux_exit(nvsw_core); ++} ++ ++static int nvsw_core_regmap_init(struct nvsw_core *nvsw_core) ++{ ++ int err; ++ ++ switch (nvsw_core->regmap_type) { ++ case REGMAP_I2C: ++ nvsw_core->regmap = devm_regmap_init_i2c(nvsw_core->client, &nvsw_regmap_i2c_conf); ++ break; ++ case REGMAP_IO: ++ if (nvsw_core->port_map) { ++ nvsw_io_regmap_ctx.base = nvsw_core->port_map(nvsw_core); ++ if (!nvsw_io_regmap_ctx.base) ++ return -ENOMEM; ++ } ++ nvsw_core->regmap = devm_regmap_init(nvsw_core->dev, NULL, &nvsw_io_regmap_ctx, ++ &nvsw_regmap_conf_l1); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (IS_ERR(nvsw_core->regmap)) { ++ dev_err(nvsw_core->dev, "Failed to create regmap\n"); ++ return PTR_ERR(nvsw_core->regmap); ++ } ++ ++ /* Sync registers with hardware. */ ++ regcache_mark_dirty(nvsw_core->regmap); ++ err = regcache_sync(nvsw_core->regmap); ++ if (err) { ++ dev_err(nvsw_core->dev, "Failed to sync regmap\n"); ++ return err; ++ } ++ ++ /* Set registers default values. */ ++ if (nvsw_core->set_reg_default) { ++ err = nvsw_core->set_reg_default(nvsw_core->regmap); ++ if (err) { ++ dev_err(nvsw_core->dev, "Failed to set default regmap\n"); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++int nvsw_core_init(struct nvsw_core *nvsw_core) ++{ ++ int err; ++ ++ err = nvsw_core_regmap_init(nvsw_core); ++ if (err) ++ return err; ++ ++ err = nvsw_core_mux_topology_init(nvsw_core); ++ if (err) ++ goto nvsw_core_mux_topology_init_fail; ++ ++ err = nvsw_core_platform_init(nvsw_core); ++ if (err) ++ goto nvsw_core_platform_init_fail; ++ ++ return 0; ++nvsw_core_platform_init_fail: ++ nvsw_core_mux_topology_exit(nvsw_core); ++nvsw_core_mux_topology_init_fail: ++ return err; ++} ++EXPORT_SYMBOL(nvsw_core_init); ++ ++void nvsw_core_exit(struct nvsw_core *nvsw_core) ++{ ++ nvsw_core_platform_exit(nvsw_core); ++ nvsw_core_mux_topology_exit(nvsw_core); ++ if (nvsw_core->set_reg_default) ++ nvsw_core->set_reg_default(nvsw_core->regmap); ++} ++EXPORT_SYMBOL(nvsw_core_exit); ++ ++MODULE_AUTHOR("Vadim Pasternak "); ++MODULE_DESCRIPTION("Nvidia platform driver"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/platform/mellanox/nvsw-host-l1.c b/drivers/platform/mellanox/nvsw-host-l1.c +new file mode 100644 +index 000000000..83d305080 +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw-host-l1.c +@@ -0,0 +1,770 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "nvsw.h" ++ ++#define NVSW_HOST_DEVICE_NAME "mlxplat" ++ ++/* LPC bus IO offsets */ ++#define NVSW_I2C_BASE_ADRR 0x2000 ++#define NVSW_REG_BASE_ADRR 0x2500 ++#define NVSW_LPC_IO_RANGE 0x100 ++#define NVSW_LPC_PIO_OFFSET 0x10000UL ++#define NVSW_REG_MUX1 (NVSW_REG_MUX1_OFFSET | NVSW_LPC_PIO_OFFSET) ++#define NVSW_REG_MUX2 (NVSW_REG_MUX0_OFFSET | NVSW_LPC_PIO_OFFSET) ++ ++/* Start channel numbers */ ++#define NVSW_PARENT_CH_L1 0 ++#define NVSW_CH1_L1 5 ++ ++/* Regions for LPC I2C controller and LPC base register space */ ++static const struct resource nvsw_host_io_resources[] = { ++ [0] = DEFINE_RES_NAMED(NVSW_I2C_BASE_ADRR, NVSW_LPC_IO_RANGE, ++ "nvsw_cpld_lpc_i2c_ctrl", IORESOURCE_IO), ++ [1] = DEFINE_RES_NAMED(NVSW_REG_BASE_ADRR, NVSW_LPC_IO_RANGE, ++ "nvsw_cpld_lpc_regs", IORESOURCE_IO), ++}; ++ ++/* Platform channels for L1 scale out system family */ ++static const int nvsw_host_l1_mgmt_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, ++ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 48, 49, ++ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, ++ 65, 66, 67, 68, 69, 70, 71, ++}; ++ ++/* Platform L1 scale out mux data */ ++static struct i2c_mux_reg_platform_data nvsw_host_l1_mux_data[] = { ++ { ++ .parent = NVSW_PARENT_CH_L1, ++ .base_nr = NVSW_CH1_L1, ++ .write_only = 1, ++ .reg = (void __iomem *)NVSW_REG_MUX1, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = nvsw_host_l1_mgmt_channels, ++ .n_values = ARRAY_SIZE(nvsw_host_l1_mgmt_channels), ++ }, ++}; ++ ++static struct platform_device *nvsw_host_dev; ++static struct i2c_mux_reg_platform_data *nvsw_host_mux_data[NVSW_MUX_MAX]; ++static struct mlxreg_core_platform_data *nvsw_led_data; ++static struct mlxreg_core_platform_data *nvsw_regs_io_data; ++static struct mlxreg_core_platform_data *nvsw_wd_data[NVSW_WD_MAX]; ++static int mux_num; ++static enum nvsw_core_hid_type nvsw_host_hid; ++ ++/* Platform register access for l1 systems families data */ ++static struct mlxreg_core_data nvsw_host_l1_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version", ++ .reg = NVSW_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld3_pn", ++ .reg = NVSW_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version_min", ++ .reg = NVSW_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_status", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(3, 1), ++ .bit = 3, ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_start_retry", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "pwr_converter_prog_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0244, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "aux_pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "bmc_to_cpu_ctrl", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "uart_sel", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = NVSW_UART_SEL_MASK, ++ .bit = 7, ++ .mode = 0644, ++ }, ++ { ++ .label = "hotswap_alert", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge1", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge2", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge3", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge4", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge_status_clear", ++ .reg = NVSW_REG_FRU1_EVENT_OFFSET, ++ .bit = GENMASK(3, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "leakage1", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage2", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage_status_clear", ++ .reg = NVSW_REG_LEAK_EVENT_OFFSET, ++ .bit = GENMASK(1, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_fu", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_button_or_leak_con", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_wd", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_platform", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_soc", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_thermal", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_power", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_converter_fail", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_51v", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_mgmt_pwr", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "port80", ++ .reg = NVSW_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_cap", ++ .reg = NVSW_REG_FU_CAP_OFFSET, ++ .mask = NVSW_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic2_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC2_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic3_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC3_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic4_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC4_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "config1", ++ .reg = NVSW_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config2", ++ .reg = NVSW_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config3", ++ .reg = NVSW_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "sgmii_phy", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "graseful_pwr_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "power_button_evt", ++ .reg = NVSW_REG_PWRB_EVENT_OFFSET, ++ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, ++ .mode = 0644, ++ }, ++ { ++ .label = "power_button_mask", ++ .reg = NVSW_REG_PWRB_MASK_OFFSET, ++ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, ++ .mode = 0644, ++ }, ++ { ++ .label = "amb_sens", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, +}; + -+static const struct regmap_config nvsw_regmap_i2c_conf = { -+ .reg_bits = 16, -+ .val_bits = 8, -+ .max_register = NVSW_REG_MAX, -+ .cache_type = REGCACHE_FLAT, -+ .reg_defaults = nvsw_core_reg_def, -+ .num_reg_defaults = ARRAY_SIZE(nvsw_core_reg_def), -+ .writeable_reg = nvsw_writeable_reg, -+ .readable_reg = nvsw_readable_reg, -+ .volatile_reg = nvsw_volatile_reg, ++static struct mlxreg_core_platform_data nvsw_host_l1_regs_io = { ++ .data = nvsw_host_l1_regs_io_data, ++ .counter = ARRAY_SIZE(nvsw_host_l1_regs_io_data), +}; + -+static const struct reg_default nvsw_reg_def_l1[] = { -+ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, -+ { NVSW_REG_WD2_ACT_OFFSET, 0x00 }, -+ { NVSW_REG_WD3_ACT_OFFSET, 0x00 }, -+ { NVSW_REG_LEAK_MASK_OFFSET, 0x3f }, ++/* Platform led data for L1 switch systems with liquid cooling (without FANs) */ ++static struct mlxreg_core_data nvsw_host_l1_liquid_coling_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "power:green", ++ .mode = 0444, ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, +}; + -+struct nvsw_io_regmap_context { -+ void __iomem *base; ++static struct mlxreg_core_platform_data nvsw_host_l1_liquid_coling_led = { ++ .data = nvsw_host_l1_liquid_coling_led_data, ++ .counter = ARRAY_SIZE(nvsw_host_l1_liquid_coling_led_data), +}; + -+static struct nvsw_io_regmap_context nvsw_io_regmap_ctx; -+ -+static int nvsw_reg_read(void *context, unsigned int reg, unsigned int *val) -+{ -+ struct nvsw_io_regmap_context *ctx = context; -+ -+ *val = ioread8(ctx->base - NVSW_REG_MIN + reg); -+ return 0; -+} -+ -+static int nvsw_reg_write(void *context, unsigned int reg, unsigned int val) -+{ -+ struct nvsw_io_regmap_context *ctx = context; -+ -+ iowrite8(val, ctx->base - NVSW_REG_MIN + reg); -+ return 0; -+} -+ -+static const struct regmap_config nvsw_regmap_conf_l1 = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = NVSW_REG_MAX, -+ .cache_type = REGCACHE_FLAT, -+ .writeable_reg = nvsw_writeable_reg, -+ .readable_reg = nvsw_readable_reg, -+ .volatile_reg = nvsw_volatile_reg, -+ .reg_defaults = nvsw_reg_def_l1, -+ .num_reg_defaults = ARRAY_SIZE(nvsw_reg_def_l1), -+ .reg_read = nvsw_reg_read, -+ .reg_write = nvsw_reg_write, ++/* Watchdog type3 platform data */ ++static struct mlxreg_core_data nvsw_host_wd_main_regs_type3[] = { ++ { ++ .label = "action", ++ .reg = NVSW_REG_WD2_ACT_OFFSET, ++ .mask = NVSW_WD_RESET_ACT_MASK, ++ .bit = 0, ++ }, ++ { ++ .label = "timeout", ++ .reg = NVSW_REG_WD2_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ .health_cntr = NVSW_WD3_DFLT_TIMEOUT, ++ }, ++ { ++ .label = "timeleft", ++ .reg = NVSW_REG_WD2_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ }, ++ { ++ .label = "ping", ++ .reg = NVSW_REG_WD2_ACT_OFFSET, ++ .mask = NVSW_WD_RESET_ACT_MASK, ++ .bit = 0, ++ }, ++ { ++ .label = "reset", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .bit = 6, ++ }, +}; + -+static int nvsw_core_platform_init(struct nvsw_core *nvsw_core) -+{ -+ int i, err; -+ -+ /* Add registers io access driver. */ -+ if (nvsw_core->regio_data) { -+ nvsw_core->regio_data->regmap = nvsw_core->regmap; -+ nvsw_core->regio = -+ platform_device_register_resndata(nvsw_core->dev, "mlxreg-io", -+ PLATFORM_DEVID_NONE, NULL, 0, -+ nvsw_core->regio_data, -+ sizeof(*nvsw_core->regio_data)); -+ if (IS_ERR(nvsw_core->regio)) { -+ err = PTR_ERR(nvsw_core->regio); -+ dev_err(nvsw_core->dev, "Failed to register mlxreg-io driver\n"); -+ goto fail_platform_io_register; -+ } -+ } -+ -+ /* Add FAN driver. */ -+ if (nvsw_core->fan_data) { -+ nvsw_core->fan_data->regmap = nvsw_core->regmap; -+ nvsw_core->fan = platform_device_register_resndata(nvsw_core->dev, "mlxreg-fan", -+ PLATFORM_DEVID_NONE, NULL, 0, -+ nvsw_core->fan_data, -+ sizeof(*nvsw_core->fan_data)); -+ if (IS_ERR(nvsw_core->fan)) { -+ err = PTR_ERR(nvsw_core->fan); -+ dev_err(nvsw_core->dev, "Failed to register mlxreg-fan driver\n"); -+ goto fail_platform_fan_register; -+ } -+ } ++static struct mlxreg_core_data nvsw_host_wd_aux_regs_type3[] = { ++ { ++ .label = "action", ++ .reg = NVSW_REG_WD3_ACT_OFFSET, ++ .mask = NVSW_WD_FAN_ACT_MASK, ++ .bit = 4, ++ }, ++ { ++ .label = "timeout", ++ .reg = NVSW_REG_WD3_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ .health_cntr = NVSW_WD3_DFLT_TIMEOUT, ++ }, ++ { ++ .label = "timeleft", ++ .reg = NVSW_REG_WD3_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ }, ++ { ++ .label = "ping", ++ .reg = NVSW_REG_WD3_ACT_OFFSET, ++ .mask = NVSW_WD_FAN_ACT_MASK, ++ .bit = 4, ++ }, ++}; + -+ /* Add LED driver. */ -+ if (nvsw_core->led_data) { -+ nvsw_core->led_data->regmap = nvsw_core->regmap; -+ nvsw_core->led = platform_device_register_resndata(nvsw_core->dev, "leds-mlxreg", -+ PLATFORM_DEVID_NONE, NULL, 0, -+ nvsw_core->led_data, -+ sizeof(*nvsw_core->led_data)); -+ if (IS_ERR(nvsw_core->led)) { -+ err = PTR_ERR(nvsw_core->led); -+ dev_err(nvsw_core->dev, "Failed to register leds-mlxreg driver\n"); -+ goto fail_platform_leds_register; -+ } -+ } ++static struct mlxreg_core_platform_data nvsw_host_wd_set_type3[] = { ++ { ++ .data = nvsw_host_wd_main_regs_type3, ++ .counter = ARRAY_SIZE(nvsw_host_wd_main_regs_type3), ++ .version = MLX_WDT_TYPE3, ++ .identity = "mlx-wdt-main", ++ }, ++ { ++ .data = nvsw_host_wd_aux_regs_type3, ++ .counter = ARRAY_SIZE(nvsw_host_wd_aux_regs_type3), ++ .version = MLX_WDT_TYPE3, ++ .identity = "mlx-wdt-aux", ++ }, ++}; + -+ /* Add hotplug driver. */ -+ if (nvsw_core->hotplug_data && nvsw_core->np) { -+ nvsw_core->hotplug_data->irq = nvsw_core->client->irq; -+ dev_info(nvsw_core->dev, "irq %d\n", nvsw_core->hotplug_data->irq); -+ nvsw_core->hotplug_data->regmap = nvsw_core->regmap; -+ nvsw_core->hotplug = -+ platform_device_register_resndata(nvsw_core->dev, "mlxreg-hotplug", -+ PLATFORM_DEVID_NONE, NULL, 0, -+ nvsw_core->hotplug_data, -+ sizeof(*nvsw_core->hotplug_data)); -+ if (IS_ERR(nvsw_core->hotplug)) { -+ err = PTR_ERR(nvsw_core->hotplug); -+ dev_err(nvsw_core->dev, "Failed to register mlxreg-hotplug driver\n"); -+ goto fail_platform_hotplug_register; -+ } -+ } ++/* IO port mapping callback. */ ++static void __iomem *nvsw_host_l1_port_map(struct nvsw_core *nvsw_core) ++{ ++ return devm_ioport_map(nvsw_core->dev, nvsw_host_io_resources[1].start, 1); ++} + -+ for (i = 0; i < ARRAY_SIZE(nvsw_core->wd_data); i++) { -+ if (nvsw_core->wd_data[i]) { -+ nvsw_core->wd_data[i]->regmap = nvsw_core->regmap; -+ nvsw_core->wd[i] = -+ platform_device_register_resndata(nvsw_core->dev, "mlx-wdt", i, -+ NULL, 0, nvsw_core->wd_data[i], -+ sizeof(*nvsw_core->wd_data[i])); -+ if (IS_ERR(nvsw_core->wd[i])) { -+ err = PTR_ERR(nvsw_core->wd[i]); -+ dev_err(nvsw_core->dev, "Failed to register mlx-wdt driver\n"); -+ goto fail_platform_wd_register; -+ } ++/* Mux init/exit callbacks. */ ++static int nvsw_host_l1_mux_topology_init(struct nvsw_core *nvsw_core) ++{ ++ int i, err; ++ ++ /* Create mux infrastructure. */ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ nvsw_core->mux[i] = ++ platform_device_register_resndata(nvsw_core->dev, "i2c-mux-reg", i, NULL, ++ 0, nvsw_host_mux_data[i], ++ sizeof(*nvsw_host_mux_data[i])); ++ if (IS_ERR(nvsw_core->mux[i])) { ++ dev_err(nvsw_core->dev, "Failed to create mux infra\n"); ++ err = PTR_ERR(nvsw_core->mux[i]); ++ goto fail_platform_mux_register; + } + } + + return 0; -+ -+fail_platform_wd_register: -+ while (i--) -+ platform_device_unregister(nvsw_core->wd[i]); -+ if (nvsw_core->hotplug_data) -+ platform_device_unregister(nvsw_core->hotplug); -+fail_platform_hotplug_register: -+ if (nvsw_core->led_data) -+ platform_device_unregister(nvsw_core->led); -+fail_platform_leds_register: -+ if (nvsw_core->fan_data) -+ platform_device_unregister(nvsw_core->fan); -+fail_platform_fan_register: -+ if (nvsw_core->regio_data) -+ platform_device_unregister(nvsw_core->regio); -+fail_platform_io_register: ++fail_platform_mux_register: ++ while (--i >= 0) ++ platform_device_unregister(nvsw_core->mux[i]); + return err; +} + -+static void nvsw_core_platform_exit(struct nvsw_core *nvsw_core) ++static void nvsw_host_l1_mux_topology_exit(struct nvsw_core *nvsw_core) +{ + int i; + -+ for (i = NVSW_WD_MAX - 1; i >= 0; i--) -+ platform_device_unregister(nvsw_core->wd[i]); -+ if (nvsw_core->hotplug_data) -+ platform_device_unregister(nvsw_core->hotplug); -+ if (nvsw_core->led_data) -+ platform_device_unregister(nvsw_core->led); -+ if (nvsw_core->fan_data) -+ platform_device_unregister(nvsw_core->fan); -+ if (nvsw_core->regio_data) -+ platform_device_unregister(nvsw_core->regio); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ if (nvsw_core->mux[i]) ++ platform_device_unregister(nvsw_core->mux[i]); ++ } +} + -+static int nvsw_core_mux_topology_init(struct nvsw_core *nvsw_core) ++static int __init nvsw_host_register_platform_device(void) +{ -+ return nvsw_core->mux_init(nvsw_core); ++ nvsw_host_dev = platform_device_register_simple(NVSW_HOST_DEVICE_NAME, -1, ++ nvsw_host_io_resources, ++ ARRAY_SIZE(nvsw_host_io_resources)); ++ if (IS_ERR(nvsw_host_dev)) ++ return PTR_ERR(nvsw_host_dev); ++ return 1; +} + -+static void nvsw_core_mux_topology_exit(struct nvsw_core *nvsw_core) ++static int __init nvsw_host_dmi_l1_switch_matched(const struct dmi_system_id *dmi) +{ -+ nvsw_core->mux_exit(nvsw_core); ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_host_hid = HID180; ++ mux_num = ARRAY_SIZE(nvsw_host_l1_mux_data); ++ for (i = 0; i < mux_num; i++) ++ nvsw_host_mux_data[i] = &nvsw_host_l1_mux_data[i]; ++ nvsw_led_data = &nvsw_host_l1_liquid_coling_led; ++ nvsw_regs_io_data = &nvsw_host_l1_regs_io; ++ for (i = 0; i < ARRAY_SIZE(nvsw_host_wd_set_type3); i++) ++ nvsw_wd_data[i] = &nvsw_host_wd_set_type3[i]; ++ ++ return nvsw_host_register_platform_device(); +} + -+static int nvsw_core_regmap_init(struct nvsw_core *nvsw_core) -+{ -+ int err; ++static const struct dmi_system_id nvsw_host_dmi_table[] __initconst = { ++ { ++ .callback = nvsw_host_dmi_l1_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0023"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI180"), ++ }, ++ }, ++ { ++ .callback = nvsw_host_dmi_l1_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0023"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI185"), ++ }, ++ }, ++ { } ++}; + -+ switch (nvsw_core->regmap_type) { -+ case REGMAP_I2C: -+ nvsw_core->regmap = devm_regmap_init_i2c(nvsw_core->client, &nvsw_regmap_i2c_conf); -+ break; -+ case REGMAP_IO: -+ if (nvsw_core->port_map) { -+ nvsw_io_regmap_ctx.base = nvsw_core->port_map(nvsw_core); -+ if (!nvsw_io_regmap_ctx.base) -+ return -ENOMEM; -+ } -+ nvsw_core->regmap = devm_regmap_init(nvsw_core->dev, NULL, &nvsw_io_regmap_ctx, -+ &nvsw_regmap_conf_l1); -+ break; -+ default: -+ return -EINVAL; -+ } ++MODULE_DEVICE_TABLE(dmi, nvsw_host_dmi_table); + -+ if (IS_ERR(nvsw_core->regmap)) { -+ dev_err(nvsw_core->dev, "Failed to create regmap\n"); -+ return PTR_ERR(nvsw_core->regmap); -+ } ++static int nvsw_host_probe(struct platform_device *pdev) ++{ ++ struct nvsw_core *nvsw_core; ++ int i; + -+ /* Sync registers with hardware. */ -+ regcache_mark_dirty(nvsw_core->regmap); -+ err = regcache_sync(nvsw_core->regmap); -+ if (err) { -+ dev_err(nvsw_core->dev, "Failed to sync regmap\n"); -+ return err; -+ } ++ nvsw_core = devm_kzalloc(&nvsw_host_dev->dev, sizeof(*nvsw_core), GFP_KERNEL); ++ if (!nvsw_core) ++ return -ENOMEM; + -+ /* Set registers default values. */ -+ if (nvsw_core->set_reg_default) { -+ err = nvsw_core->set_reg_default(nvsw_core->regmap); -+ if (err) { -+ dev_err(nvsw_core->dev, "Failed to set default regmap\n"); -+ return err; -+ } -+ } ++ /* Set system configuration. */ ++ nvsw_core->dev = &nvsw_host_dev->dev; ++ nvsw_core->hid = nvsw_host_hid; ++ nvsw_core->regmap_type = REGMAP_IO; ++ nvsw_core->mux_num = mux_num; ++ for (i = 0; i < ARRAY_SIZE(nvsw_wd_data); i++) ++ nvsw_core->wd_data[i] = nvsw_wd_data[i]; ++ nvsw_core->regio_data = nvsw_regs_io_data; ++ nvsw_core->led_data = nvsw_led_data; ++ nvsw_core->port_map = nvsw_host_l1_port_map; ++ nvsw_core->mux_init = nvsw_host_l1_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_host_l1_mux_topology_exit; ++ platform_set_drvdata(nvsw_host_dev, nvsw_core); + -+ return 0; ++ return nvsw_core_init(nvsw_core); +} + -+int nvsw_core_init(struct nvsw_core *nvsw_core) ++static void nvsw_host_remove(struct platform_device *pdev) +{ -+ int err; ++ struct nvsw_core *nvsw_core = platform_get_drvdata(nvsw_host_dev); + -+ err = nvsw_core_regmap_init(nvsw_core); -+ if (err) -+ return err; ++ return nvsw_core_exit(nvsw_core); ++} + -+ err = nvsw_core_mux_topology_init(nvsw_core); -+ if (err) -+ goto nvsw_core_mux_topology_init_fail; ++static struct platform_driver nvsw_host_driver = { ++ .driver = { ++ .name = NVSW_HOST_DEVICE_NAME, ++ .probe_type = PROBE_FORCE_SYNCHRONOUS, ++ }, ++ .probe = nvsw_host_probe, ++ .remove = nvsw_host_remove, ++}; + -+ err = nvsw_core_platform_init(nvsw_core); -+ if (err) -+ goto nvsw_core_platform_init_fail; ++static int __init nvsw_host_init(void) ++{ ++ if (!dmi_check_system(nvsw_host_dmi_table)) ++ return -ENODEV; + -+ return 0; -+nvsw_core_platform_init_fail: -+ nvsw_core_mux_topology_exit(nvsw_core); -+nvsw_core_mux_topology_init_fail: -+ return err; ++ return platform_driver_register(&nvsw_host_driver); +} -+EXPORT_SYMBOL(nvsw_core_init); ++module_init(nvsw_host_init); + -+void nvsw_core_exit(struct nvsw_core *nvsw_core) -+{ -+ nvsw_core_platform_exit(nvsw_core); -+ nvsw_core_mux_topology_exit(nvsw_core); -+ if (nvsw_core->set_reg_default) -+ nvsw_core->set_reg_default(nvsw_core->regmap); ++static void __exit nvsw_host_exit(void) ++{ ++ if (nvsw_host_dev) ++ platform_device_unregister(nvsw_host_dev); ++ ++ platform_driver_unregister(&nvsw_host_driver); +} -+EXPORT_SYMBOL(nvsw_core_exit); ++module_exit(nvsw_host_exit); + +MODULE_AUTHOR("Vadim Pasternak "); +MODULE_DESCRIPTION("Nvidia platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); -diff --git a/drivers/platform/mellanox/nvsw-host-l1.c b/drivers/platform/mellanox/nvsw-host-l1.c +diff --git a/drivers/platform/mellanox/nvsw-host-spc5.c b/drivers/platform/mellanox/nvsw-host-spc5.c new file mode 100644 -index 000000000..46022cb99 +index 000000000..e54bd4109 --- /dev/null -+++ b/drivers/platform/mellanox/nvsw-host-l1.c -@@ -0,0 +1,744 @@ ++++ b/drivers/platform/mellanox/nvsw-host-spc5.c +@@ -0,0 +1,943 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia BMC platform driver @@ -3607,9 +4941,14 @@ index 000000000..46022cb99 +#define NVSW_REG_MUX1 (NVSW_REG_MUX1_OFFSET | NVSW_LPC_PIO_OFFSET) +#define NVSW_REG_MUX2 (NVSW_REG_MUX0_OFFSET | NVSW_LPC_PIO_OFFSET) + ++/* Default I2C parent bus number */ ++#define NVSW_CPLD_PHYS_ADAPTER_DEF_NR 5 ++ +/* Start channel numbers */ -+#define NVSW_PARENT_CH_L1 0 -+#define NVSW_CH1_L1 5 ++#define NVSW_PARENT_CH NVSW_CPLD_PHYS_ADAPTER_DEF_NR ++#define NVSW_MUX1_CH NVSW_CPLD_PHYS_ADAPTER_DEF_NR + 1 ++#define NVSW_MUX2_CH 64 ++ + +/* Regions for LPC I2C controller and LPC base register space */ +static const struct resource nvsw_host_io_resources[] = { @@ -3619,39 +4958,79 @@ index 000000000..46022cb99 + "nvsw_cpld_lpc_regs", IORESOURCE_IO), +}; + -+/* Platform channels for L1 scale out system family */ -+static const int nvsw_host_l1_mgmt_channels[] = { ++/* SPC5 platform mgmt board mux channels */ ++static const int nvsw_host_spc5_mgmt_channels[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, -+ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 48, 49, -+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, -+ 65, 66, 67, 68, 69, 70, 71, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 +}; + -+/* Platform L1 scale out mux data */ -+static struct i2c_mux_reg_platform_data nvsw_host_l1_mux_data[] = { ++/* SPC5 platform ComEx board mux channels */ ++static const int nvsw_host_spc5_comex_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8 ++}; ++ ++/* SPC5 platform mux data */ ++static struct i2c_mux_reg_platform_data nvsw_host_spc5_mux_data[] = { + { -+ .parent = NVSW_PARENT_CH_L1, -+ .base_nr = NVSW_CH1_L1, ++ .parent = NVSW_PARENT_CH, ++ .base_nr = NVSW_MUX1_CH, + .write_only = 1, + .reg = (void __iomem *)NVSW_REG_MUX1, + .reg_size = 1, + .idle_in_use = 1, -+ .values = nvsw_host_l1_mgmt_channels, -+ .n_values = ARRAY_SIZE(nvsw_host_l1_mgmt_channels), ++ .values = nvsw_host_spc5_mgmt_channels, ++ .n_values = ARRAY_SIZE(nvsw_host_spc5_mgmt_channels), ++ }, ++ { ++ .parent = NVSW_PARENT_CH, ++ .base_nr = NVSW_MUX2_CH, ++ .write_only = 1, ++ .reg = (void __iomem *)NVSW_REG_MUX2, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = nvsw_host_spc5_comex_channels, ++ .n_values = ARRAY_SIZE(nvsw_host_spc5_comex_channels), ++ }, ++}; ++ ++/* SPC5 platform i2c frequency data */ ++static struct mlxreg_core_data nvsw_mlxcpld_i2c_items_data[] = { ++ { ++ .reg = NVSW_REG_PSU_I2C_CAP_OFFSET, ++ .mask = NVSW_I2C_CAP_MASK, ++ .bit = NVSW_I2C_CAP_BIT, ++ }, ++}; ++ ++static struct mlxreg_core_item nvsw_mlxcpld_i2c_items[] = { ++ { ++ .data = nvsw_mlxcpld_i2c_items_data, + }, +}; + ++/* SPC5 platform i2c data */ ++static struct mlxreg_core_hotplug_platform_data nvsw_mlxcpld_i2c_data = { ++ .items = nvsw_mlxcpld_i2c_items, ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRCO_OFFSET, ++ .mask_low = NVSW_LOW_AGGR_MASK_I2C, ++}; ++ +static struct platform_device *nvsw_host_dev; ++static struct platform_device *nvsw_i2c_dev; +static struct i2c_mux_reg_platform_data *nvsw_host_mux_data[NVSW_MUX_MAX]; +static struct mlxreg_core_platform_data *nvsw_led_data; +static struct mlxreg_core_platform_data *nvsw_regs_io_data; ++static struct mlxreg_core_hotplug_platform_data *nvsw_i2c_data; +static struct mlxreg_core_platform_data *nvsw_wd_data[NVSW_WD_MAX]; +static int mux_num; +static enum nvsw_core_hid_type nvsw_host_hid; + -+/* Platform register access for l1 systems families data */ -+static struct mlxreg_core_data nvsw_host_l1_regs_io_data[] = { ++/* Platform register access for SPC5 systems families data */ ++static struct mlxreg_core_data nvsw_host_spc5_regs_io_data[] = { + { + .label = "cpld1_version", + .reg = NVSW_REG_CPLD1_VER_OFFSET, @@ -3665,6 +5044,54 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { ++ .label = "cpld3_version", ++ .reg = NVSW_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version", ++ .reg = NVSW_REG_CPLD4_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld5_version", ++ .reg = NVSW_REG_CPLD5_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld6_version", ++ .reg = NVSW_REG_CPLD6_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld7_version", ++ .reg = NVSW_REG_CPLD7_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld8_version", ++ .reg = NVSW_REG_CPLD8_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld9_version", ++ .reg = NVSW_REG_CPLD9_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld10_version", ++ .reg = NVSW_REG_CPLD10_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { + .label = "cpld1_pn", + .reg = NVSW_REG_CPLD1_PN_OFFSET, + .bit = GENMASK(15, 0), @@ -3679,6 +5106,62 @@ index 000000000..46022cb99 + .regnum = 2, + }, + { ++ .label = "cpld3_pn", ++ .reg = NVSW_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld4_pn", ++ .reg = NVSW_REG_CPLD4_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld5_pn", ++ .reg = NVSW_REG_CPLD5_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld6_pn", ++ .reg = NVSW_REG_CPLD6_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld7_pn", ++ .reg = NVSW_REG_CPLD7_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld8_pn", ++ .reg = NVSW_REG_CPLD8_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld9_pn", ++ .reg = NVSW_REG_CPLD9_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld10_pn", ++ .reg = NVSW_REG_CPLD10_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { + .label = "cpld1_version_min", + .reg = NVSW_REG_CPLD1_MVER_OFFSET, + .bit = GENMASK(7, 0), @@ -3691,22 +5174,51 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { -+ .label = "bios_status", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(3, 1), -+ .bit = 3, ++ .label = "cpld3_version_min", ++ .reg = NVSW_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "bios_start_retry", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), ++ .label = "cpld4_version_min", ++ .reg = NVSW_REG_CPLD4_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { -+ .label = "bios_active_image", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), ++ .label = "cpld5_version_min", ++ .reg = NVSW_REG_CPLD5_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld6_version_min", ++ .reg = NVSW_REG_CPLD6_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld7_version_min", ++ .reg = NVSW_REG_CPLD7_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld8_version_min", ++ .reg = NVSW_REG_CPLD8_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld9_version_min", ++ .reg = NVSW_REG_CPLD9_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld10_version_min", ++ .reg = NVSW_REG_CPLD10_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { @@ -3716,6 +5228,12 @@ index 000000000..46022cb99 + .mode = 0644, + }, + { ++ .label = "graceful_pwr_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { + .label = "cpu_mctp_ready", + .reg = NVSW_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), @@ -3784,63 +5302,63 @@ index 000000000..46022cb99 + .mode = 0644, + }, + { -+ .label = "hotswap_alert", -+ .reg = NVSW_REG_BRD4_OFFSET, ++ .label = "leakage1", ++ .reg = NVSW_REG_LEAK_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { -+ .label = "cartridge1", -+ .reg = NVSW_REG_FRU1_OFFSET, -+ .mask = BIT(0), ++ .label = "leakage2", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { -+ .label = "cartridge2", -+ .reg = NVSW_REG_FRU1_OFFSET, -+ .mask = BIT(1), ++ .label = "leakage3", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { -+ .label = "cartridge3", -+ .reg = NVSW_REG_FRU1_OFFSET, -+ .mask = BIT(2), ++ .label = "leakage4", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { -+ .label = "cartridge4", -+ .reg = NVSW_REG_FRU1_OFFSET, -+ .mask = BIT(3), ++ .label = "leakage5", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { -+ .label = "cartridge_status_clear", -+ .reg = NVSW_REG_FRU1_EVENT_OFFSET, -+ .bit = GENMASK(3, 0), ++ .label = "asic_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { -+ .label = "leakage1", -+ .reg = NVSW_REG_LEAK_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, ++ .label = "asic1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, + }, + { -+ .label = "leakage2", -+ .reg = NVSW_REG_LEAK_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, ++ .label = "asic2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, + }, + { -+ .label = "leakage_status_clear", -+ .reg = NVSW_REG_LEAK_EVENT_OFFSET, -+ .bit = GENMASK(1, 0), ++ .label = "asic3_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { -+ .label = "asic_reset", ++ .label = "asic4_reset", + .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { @@ -3862,7 +5380,7 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { -+ .label = "reset_aux_pwr_or_fu", ++ .label = "reset_aux_pwr_or_reload", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, @@ -3874,9 +5392,9 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { -+ .label = "reset_pwr_button_or_leak_con", ++ .label = "reset_platform", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { @@ -3898,12 +5416,6 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { -+ .label = "reset_platform", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, -+ }, -+ { + .label = "reset_soc", + .reg = NVSW_REG_RESET_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), @@ -3928,12 +5440,6 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { -+ .label = "reset_comex_power", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, -+ }, -+ { + .label = "reset_pwr_converter_fail", + .reg = NVSW_REG_RESET_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), @@ -3958,6 +5464,12 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { + .label = "jtag_cap", + .reg = NVSW_REG_FU_CAP_OFFSET, + .mask = NVSW_FU_CAP_MASK, @@ -4000,75 +5512,69 @@ index 000000000..46022cb99 + .mode = 0444, + }, + { -+ .label = "asic_pg_fail", ++ .label = "asic1_pg_fail", + .reg = NVSW_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { -+ .label = "spi_chnl_select", -+ .reg = NVSW_REG_SPI_CHNL_SELECT, -+ .mask = GENMASK(7, 0), -+ .bit = 1, -+ .mode = 0644, -+ }, -+ { -+ .label = "config1", -+ .reg = NVSW_REG_CONFIG1_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "asic2_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { -+ .label = "config2", -+ .reg = NVSW_REG_CONFIG2_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "asic3_pg_fail", ++ .reg = NVSW_REG_GP5_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { -+ .label = "config3", -+ .reg = NVSW_REG_CONFIG3_OFFSET, -+ .bit = GENMASK(7, 0), ++ .label = "asic4_pg_fail", ++ .reg = NVSW_REG_GP5_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { -+ .label = "sgmii_phy", -+ .reg = NVSW_REG_BRD1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, + }, + { -+ .label = "graseful_pwr_off", -+ .reg = NVSW_REG_GP7_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), ++ .label = "pdb1_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { -+ .label = "power_button_evt", -+ .reg = NVSW_REG_PWRB_EVENT_OFFSET, -+ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, ++ .label = "pdb2_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { -+ .label = "power_button_mask", -+ .reg = NVSW_REG_PWRB_MASK_OFFSET, -+ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, ++ .label = "pdb3_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { -+ .label = "amb_sens", -+ .reg = NVSW_REG_PWRB_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, ++ .label = "pdb4_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, + }, +}; + -+static struct mlxreg_core_platform_data nvsw_host_l1_regs_io = { -+ .data = nvsw_host_l1_regs_io_data, -+ .counter = ARRAY_SIZE(nvsw_host_l1_regs_io_data), ++static struct mlxreg_core_platform_data nvsw_host_spc5_regs_io = { ++ .data = nvsw_host_spc5_regs_io_data, ++ .counter = ARRAY_SIZE(nvsw_host_spc5_regs_io_data), +}; + -+/* Platform led data for L1 switch systems with liquid cooling (without FANs) */ -+static struct mlxreg_core_data nvsw_host_l1_liquid_coling_led_data[] = { ++/* SPC5 platform led data */ ++static struct mlxreg_core_data nvsw_host_spc5_led_data[] = { + { + .label = "status:green", + .reg = NVSW_REG_LED1_OFFSET, @@ -4097,9 +5603,9 @@ index 000000000..46022cb99 + }, +}; + -+static struct mlxreg_core_platform_data nvsw_host_l1_liquid_coling_led = { -+ .data = nvsw_host_l1_liquid_coling_led_data, -+ .counter = ARRAY_SIZE(nvsw_host_l1_liquid_coling_led_data), ++static struct mlxreg_core_platform_data nvsw_host_spc5_led = { ++ .data = nvsw_host_spc5_led_data, ++ .counter = ARRAY_SIZE(nvsw_host_spc5_led_data), +}; + +/* Watchdog type3 platform data */ @@ -4177,16 +5683,31 @@ index 000000000..46022cb99 +}; + +/* IO port mapping callback. */ -+static void __iomem *nvsw_host_l1_port_map(struct nvsw_core *nvsw_core) ++static void __iomem *nvsw_host_spc5_port_map(struct nvsw_core *nvsw_core) +{ + return devm_ioport_map(nvsw_core->dev, nvsw_host_io_resources[1].start, 1); +} + +/* Mux init/exit callbacks. */ -+static int nvsw_host_l1_mux_topology_init(struct nvsw_core *nvsw_core) ++static int nvsw_host_spc5_mux_topology_init(struct nvsw_core *nvsw_core) +{ + int i, err; + ++ if (!nvsw_i2c_data) ++ return 0; ++ ++ /* Create i2c infrastructure. */ ++ nvsw_i2c_data->regmap = nvsw_core->regmap; ++ nvsw_i2c_data->handle = nvsw_core; ++ ++ nvsw_i2c_dev = platform_device_register_resndata(nvsw_core->dev, "i2c_mlxcpld", ++ NVSW_CPLD_PHYS_ADAPTER_DEF_NR, NULL, 0, ++ nvsw_i2c_data, sizeof(*nvsw_i2c_data)); ++ if (IS_ERR(nvsw_i2c_dev)) { ++ err = PTR_ERR(nvsw_i2c_dev); ++ return err; ++ } ++ + /* Create mux infrastructure. */ + for (i = 0; i < nvsw_core->mux_num; i++) { + nvsw_core->mux[i] = @@ -4207,7 +5728,7 @@ index 000000000..46022cb99 + return err; +} + -+static void nvsw_host_l1_mux_topology_exit(struct nvsw_core *nvsw_core) ++static void nvsw_host_spc5_mux_topology_exit(struct nvsw_core *nvsw_core) +{ + int i; + @@ -4215,6 +5736,9 @@ index 000000000..46022cb99 + if (nvsw_core->mux[i]) + platform_device_unregister(nvsw_core->mux[i]); + } ++ ++ if (nvsw_i2c_dev) ++ platform_device_unregister(nvsw_i2c_dev); +} + +static int __init nvsw_host_register_platform_device(void) @@ -4227,29 +5751,37 @@ index 000000000..46022cb99 + return 1; +} + -+static int __init nvsw_host_dmi_l1_switch_matched(const struct dmi_system_id *dmi) ++static int __init nvsw_host_dmi_spc5_switch_matched(const struct dmi_system_id *dmi) +{ + int i; + + /* Set system configuration. */ -+ nvsw_host_hid = HID180; -+ mux_num = ARRAY_SIZE(nvsw_host_l1_mux_data); ++ nvsw_host_hid = HID181; ++ mux_num = ARRAY_SIZE(nvsw_host_spc5_mux_data); + for (i = 0; i < mux_num; i++) -+ nvsw_host_mux_data[i] = &nvsw_host_l1_mux_data[i]; -+ nvsw_led_data = &nvsw_host_l1_liquid_coling_led; -+ nvsw_regs_io_data = &nvsw_host_l1_regs_io; ++ nvsw_host_mux_data[i] = &nvsw_host_spc5_mux_data[i]; ++ nvsw_led_data = &nvsw_host_spc5_led; ++ nvsw_regs_io_data = &nvsw_host_spc5_regs_io; + for (i = 0; i < ARRAY_SIZE(nvsw_host_wd_set_type3); i++) + nvsw_wd_data[i] = &nvsw_host_wd_set_type3[i]; ++ nvsw_i2c_data = &nvsw_mlxcpld_i2c_data; + + return nvsw_host_register_platform_device(); +} + +static const struct dmi_system_id nvsw_host_dmi_table[] __initconst = { + { -+ .callback = nvsw_host_dmi_l1_switch_matched, ++ .callback = nvsw_host_dmi_spc5_switch_matched, + .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0023"), -+ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI180"), ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0024"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI181"), ++ }, ++ }, ++ { ++ .callback = nvsw_host_dmi_spc5_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0024"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI182"), + }, + }, + { } @@ -4275,9 +5807,9 @@ index 000000000..46022cb99 + nvsw_core->wd_data[i] = nvsw_wd_data[i]; + nvsw_core->regio_data = nvsw_regs_io_data; + nvsw_core->led_data = nvsw_led_data; -+ nvsw_core->port_map = nvsw_host_l1_port_map; -+ nvsw_core->mux_init = nvsw_host_l1_mux_topology_init; -+ nvsw_core->mux_exit = nvsw_host_l1_mux_topology_exit; ++ nvsw_core->port_map = nvsw_host_spc5_port_map; ++ nvsw_core->mux_init = nvsw_host_spc5_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_host_spc5_mux_topology_exit; + platform_set_drvdata(nvsw_host_dev, nvsw_core); + + return nvsw_core_init(nvsw_core); @@ -4287,7 +5819,7 @@ index 000000000..46022cb99 +{ + struct nvsw_core *nvsw_core = platform_get_drvdata(nvsw_host_dev); + -+ return nvsw_core_exit(nvsw_core); ++ nvsw_core_exit(nvsw_core); +} + +static struct platform_driver nvsw_host_driver = { @@ -4320,17 +5852,18 @@ index 000000000..46022cb99 +MODULE_AUTHOR("Vadim Pasternak "); +MODULE_DESCRIPTION("Nvidia platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); -diff --git a/drivers/platform/mellanox/nvsw-host-spc5.c b/drivers/platform/mellanox/nvsw-host-spc5.c ++ +diff --git a/drivers/platform/mellanox/nvsw-host-spc6.c b/drivers/platform/mellanox/nvsw-host-spc6.c new file mode 100644 -index 000000000..e54bd4109 +index 000000000..449ba5ffd --- /dev/null -+++ b/drivers/platform/mellanox/nvsw-host-spc5.c -@@ -0,0 +1,943 @@ ++++ b/drivers/platform/mellanox/nvsw-host-spc6.c +@@ -0,0 +1,852 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * Nvidia BMC platform driver ++ * Nvidia SPC6 host platform driver + * -+ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ * Copyright (C) 2025-2026 Nvidia Technologies Ltd. + */ + +#include @@ -4339,114 +5872,58 @@ index 000000000..e54bd4109 +#include +#include +#include -+#include ++#include +#include -+#include ++#include +#include -+#include + +#include "nvsw.h" + +#define NVSW_HOST_DEVICE_NAME "mlxplat" + -+/* LPC bus IO offsets */ -+#define NVSW_I2C_BASE_ADRR 0x2000 -+#define NVSW_REG_BASE_ADRR 0x2500 -+#define NVSW_LPC_IO_RANGE 0x100 -+#define NVSW_LPC_PIO_OFFSET 0x10000UL -+#define NVSW_REG_MUX1 (NVSW_REG_MUX1_OFFSET | NVSW_LPC_PIO_OFFSET) -+#define NVSW_REG_MUX2 (NVSW_REG_MUX0_OFFSET | NVSW_LPC_PIO_OFFSET) -+ -+/* Default I2C parent bus number */ -+#define NVSW_CPLD_PHYS_ADAPTER_DEF_NR 5 -+ -+/* Start channel numbers */ -+#define NVSW_PARENT_CH NVSW_CPLD_PHYS_ADAPTER_DEF_NR -+#define NVSW_MUX1_CH NVSW_CPLD_PHYS_ADAPTER_DEF_NR + 1 -+#define NVSW_MUX2_CH 64 -+ -+ -+/* Regions for LPC I2C controller and LPC base register space */ -+static const struct resource nvsw_host_io_resources[] = { -+ [0] = DEFINE_RES_NAMED(NVSW_I2C_BASE_ADRR, NVSW_LPC_IO_RANGE, -+ "nvsw_cpld_lpc_i2c_ctrl", IORESOURCE_IO), -+ [1] = DEFINE_RES_NAMED(NVSW_REG_BASE_ADRR, NVSW_LPC_IO_RANGE, -+ "nvsw_cpld_lpc_regs", IORESOURCE_IO), -+}; -+ -+/* SPC5 platform mgmt board mux channels */ -+static const int nvsw_host_spc5_mgmt_channels[] = { -+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, -+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, -+ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, -+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 -+}; -+ -+/* SPC5 platform ComEx board mux channels */ -+static const int nvsw_host_spc5_comex_channels[] = { -+ 1, 2, 3, 4, 5, 6, 7, 8 -+}; ++/* Bus number of mux parent device */ ++#define NVSW_I2C_MUX_PARENT_BUS_NR 2 + -+/* SPC5 platform mux data */ -+static struct i2c_mux_reg_platform_data nvsw_host_spc5_mux_data[] = { -+ { -+ .parent = NVSW_PARENT_CH, -+ .base_nr = NVSW_MUX1_CH, -+ .write_only = 1, -+ .reg = (void __iomem *)NVSW_REG_MUX1, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = nvsw_host_spc5_mgmt_channels, -+ .n_values = ARRAY_SIZE(nvsw_host_spc5_mgmt_channels), -+ }, -+ { -+ .parent = NVSW_PARENT_CH, -+ .base_nr = NVSW_MUX2_CH, -+ .write_only = 1, -+ .reg = (void __iomem *)NVSW_REG_MUX2, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = nvsw_host_spc5_comex_channels, -+ .n_values = ARRAY_SIZE(nvsw_host_spc5_comex_channels), -+ }, -+}; ++/* Bus number of the last host I2C bus */ ++#define NVSW_I2C_LAST_HOST_BUS_NR 3 + -+/* SPC5 platform i2c frequency data */ -+static struct mlxreg_core_data nvsw_mlxcpld_i2c_items_data[] = { -+ { -+ .reg = NVSW_REG_PSU_I2C_CAP_OFFSET, -+ .mask = NVSW_I2C_CAP_MASK, -+ .bit = NVSW_I2C_CAP_BIT, -+ }, ++/* Platform mux channels */ ++static int nvsw_host_spc6_mux_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, ++ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, ++ 63, 64, 65, 66, 67, +}; + -+static struct mlxreg_core_item nvsw_mlxcpld_i2c_items[] = { ++/* Platform mux data */ ++static struct mlxcpld_mux_plat_data nvsw_host_spc6_mux_data[] = { + { -+ .data = nvsw_mlxcpld_i2c_items_data, ++ .chan_ids = nvsw_host_spc6_mux_channels, ++ .num_adaps = ARRAY_SIZE(nvsw_host_spc6_mux_channels), ++ .sel_reg_addr = NVSW_REG_MUX1_OFFSET, ++ .reg_size = 2, + }, +}; + -+/* SPC5 platform i2c data */ -+static struct mlxreg_core_hotplug_platform_data nvsw_mlxcpld_i2c_data = { -+ .items = nvsw_mlxcpld_i2c_items, -+ .cell = NVSW_REG_AGGR_OFFSET, -+ .mask = NVSW_AGGR_MASK_COMEX, -+ .cell_low = NVSW_REG_AGGRCO_OFFSET, -+ .mask_low = NVSW_LOW_AGGR_MASK_I2C, ++/* Platform mux board info */ ++static struct i2c_board_info nvsw_host_spc6_mux_brdinfo = { ++ I2C_BOARD_INFO("i2c-mux-mlxcpld", 0x33), +}; + -+static struct platform_device *nvsw_host_dev; -+static struct platform_device *nvsw_i2c_dev; -+static struct i2c_mux_reg_platform_data *nvsw_host_mux_data[NVSW_MUX_MAX]; ++static struct i2c_adapter *nvsw_host_mux_i2c_adapter; ++static struct i2c_client *nvsw_host_mux_i2c_client; ++static struct mlxcpld_mux_plat_data *nvsw_host_mux_data[NVSW_MUX_MAX]; ++static struct i2c_board_info *nvsw_host_mux_brdinfo; +static struct mlxreg_core_platform_data *nvsw_led_data; +static struct mlxreg_core_platform_data *nvsw_regs_io_data; -+static struct mlxreg_core_hotplug_platform_data *nvsw_i2c_data; +static struct mlxreg_core_platform_data *nvsw_wd_data[NVSW_WD_MAX]; +static int mux_num; +static enum nvsw_core_hid_type nvsw_host_hid; ++static struct platform_device *nvsw_host_pdev; + -+/* Platform register access for SPC5 systems families data */ -+static struct mlxreg_core_data nvsw_host_spc5_regs_io_data[] = { ++/* Platform register access data */ ++static struct mlxreg_core_data nvsw_host_spc6_regs_io_data[] = { + { + .label = "cpld1_version", + .reg = NVSW_REG_CPLD1_VER_OFFSET, @@ -4754,36 +6231,6 @@ index 000000000..e54bd4109 + .mode = 0644, + }, + { -+ .label = "asic1_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, -+ }, -+ { -+ .label = "asic2_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, -+ }, -+ { -+ .label = "asic3_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, -+ }, -+ { -+ .label = "asic4_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0644, -+ }, -+ { -+ .label = "sgmii_phy_reset", -+ .reg = NVSW_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, -+ }, -+ { + .label = "reset_long_pb", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), @@ -4826,12 +6273,6 @@ index 000000000..e54bd4109 + .mode = 0444, + }, + { -+ .label = "reset_comex_pwr_fail", -+ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, -+ { + .label = "reset_soc", + .reg = NVSW_REG_RESET_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), @@ -4850,7 +6291,7 @@ index 000000000..e54bd4109 + .mode = 0444, + }, + { -+ .label = "reset_comex_thermal", ++ .label = "reset_cpu_thermal", + .reg = NVSW_REG_RESET_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, @@ -4874,18 +6315,6 @@ index 000000000..e54bd4109 + .mode = 0444, + }, + { -+ .label = "port80", -+ .reg = NVSW_REG_GP1_RO_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "bios_active_image", -+ .reg = NVSW_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { + .label = "jtag_cap", + .reg = NVSW_REG_FU_CAP_OFFSET, + .mask = NVSW_FU_CAP_MASK, @@ -4907,51 +6336,12 @@ index 000000000..e54bd4109 + .mode = 0444, + }, + { -+ .label = "asic2_health", -+ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, -+ .mask = NVSW_ASIC2_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, -+ { -+ .label = "asic3_health", -+ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, -+ .mask = NVSW_ASIC3_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, -+ { -+ .label = "asic4_health", -+ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, -+ .mask = NVSW_ASIC4_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, -+ { -+ .label = "asic1_pg_fail", -+ .reg = NVSW_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, -+ { -+ .label = "asic2_pg_fail", ++ .label = "asic_pg_fail", + .reg = NVSW_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, -+ { -+ .label = "asic3_pg_fail", -+ .reg = NVSW_REG_GP5_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { -+ .label = "asic4_pg_fail", -+ .reg = NVSW_REG_GP5_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, -+ { + .label = "spi_chnl_select", + .reg = NVSW_REG_SPI_CHNL_SELECT, + .mask = GENMASK(7, 0), @@ -4960,37 +6350,37 @@ index 000000000..e54bd4109 + }, + { + .label = "pdb1_pwr_status", -+ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .reg = NVSW_REG_PS_DC_OK_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { + .label = "pdb2_pwr_status", -+ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .reg = NVSW_REG_PS_DC_OK_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "pdb3_pwr_status", -+ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .reg = NVSW_REG_PS_DC_OK_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { + .label = "pdb4_pwr_status", -+ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .reg = NVSW_REG_PS_DC_OK_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, +}; + -+static struct mlxreg_core_platform_data nvsw_host_spc5_regs_io = { -+ .data = nvsw_host_spc5_regs_io_data, -+ .counter = ARRAY_SIZE(nvsw_host_spc5_regs_io_data), ++static struct mlxreg_core_platform_data nvsw_host_spc6_regs_io = { ++ .data = nvsw_host_spc6_regs_io_data, ++ .counter = ARRAY_SIZE(nvsw_host_spc6_regs_io_data), +}; + -+/* SPC5 platform led data */ -+static struct mlxreg_core_data nvsw_host_spc5_led_data[] = { ++/* Platform led data */ ++static struct mlxreg_core_data nvsw_host_spc6_lc_led_data[] = { + { + .label = "status:green", + .reg = NVSW_REG_LED1_OFFSET, @@ -5019,9 +6409,9 @@ index 000000000..e54bd4109 + }, +}; + -+static struct mlxreg_core_platform_data nvsw_host_spc5_led = { -+ .data = nvsw_host_spc5_led_data, -+ .counter = ARRAY_SIZE(nvsw_host_spc5_led_data), ++static struct mlxreg_core_platform_data nvsw_host_spc6_lc_led = { ++ .data = nvsw_host_spc6_lc_led_data, ++ .counter = ARRAY_SIZE(nvsw_host_spc6_lc_led_data), +}; + +/* Watchdog type3 platform data */ @@ -5098,53 +6488,48 @@ index 000000000..e54bd4109 + }, +}; + -+/* IO port mapping callback. */ -+static void __iomem *nvsw_host_spc5_port_map(struct nvsw_core *nvsw_core) ++/* Callback is used to indicate that all adapter devices have been created. */ ++static int ++nvsw_host_spc6_completion_notify(void *handle, struct i2c_adapter *parent, ++ struct i2c_adapter *adapters[]) +{ -+ return devm_ioport_map(nvsw_core->dev, nvsw_host_io_resources[1].start, 1); ++ return 0; +} + +/* Mux init/exit callbacks. */ -+static int nvsw_host_spc5_mux_topology_init(struct nvsw_core *nvsw_core) ++static int nvsw_host_spc6_mux_topology_init(struct nvsw_core *nvsw_core) +{ + int i, err; + -+ if (!nvsw_i2c_data) -+ return 0; -+ -+ /* Create i2c infrastructure. */ -+ nvsw_i2c_data->regmap = nvsw_core->regmap; -+ nvsw_i2c_data->handle = nvsw_core; -+ -+ nvsw_i2c_dev = platform_device_register_resndata(nvsw_core->dev, "i2c_mlxcpld", -+ NVSW_CPLD_PHYS_ADAPTER_DEF_NR, NULL, 0, -+ nvsw_i2c_data, sizeof(*nvsw_i2c_data)); -+ if (IS_ERR(nvsw_i2c_dev)) { -+ err = PTR_ERR(nvsw_i2c_dev); -+ return err; -+ } -+ + /* Create mux infrastructure. */ + for (i = 0; i < nvsw_core->mux_num; i++) { ++ nvsw_host_mux_data[i]->handle = nvsw_core; ++ nvsw_host_mux_data[i]->completion_notify = ++ nvsw_host_spc6_completion_notify; + nvsw_core->mux[i] = -+ platform_device_register_resndata(nvsw_core->dev, "i2c-mux-reg", i, NULL, ++ platform_device_register_resndata(&nvsw_host_mux_i2c_client->dev, ++ "i2c-mux-mlxcpld", i, NULL, + 0, nvsw_host_mux_data[i], + sizeof(*nvsw_host_mux_data[i])); + if (IS_ERR(nvsw_core->mux[i])) { + dev_err(nvsw_core->dev, "Failed to create mux infra\n"); + err = PTR_ERR(nvsw_core->mux[i]); -+ goto fail_platform_mux_register; ++ goto platform_mux_register_fail; + } + } + + return 0; -+fail_platform_mux_register: ++ ++platform_mux_register_fail: + while (--i >= 0) + platform_device_unregister(nvsw_core->mux[i]); ++ i2c_unregister_device(nvsw_host_mux_i2c_client); ++ nvsw_host_mux_i2c_client = NULL; ++ + return err; +} + -+static void nvsw_host_spc5_mux_topology_exit(struct nvsw_core *nvsw_core) ++static void nvsw_host_spc6_mux_topology_exit(struct nvsw_core *nvsw_core) +{ + int i; + @@ -5153,51 +6538,51 @@ index 000000000..e54bd4109 + platform_device_unregister(nvsw_core->mux[i]); + } + -+ if (nvsw_i2c_dev) -+ platform_device_unregister(nvsw_i2c_dev); ++ if (nvsw_core->client) { ++ i2c_unregister_device(nvsw_core->client); ++ nvsw_host_mux_i2c_client = NULL; ++ i2c_put_adapter(nvsw_host_mux_i2c_adapter); ++ nvsw_host_mux_i2c_adapter = NULL; ++ } +} + -+static int __init nvsw_host_register_platform_device(void) ++static int __init nvsw_host_dmi_spc6_switch_matched(const struct dmi_system_id *dmi) +{ -+ nvsw_host_dev = platform_device_register_simple(NVSW_HOST_DEVICE_NAME, -1, -+ nvsw_host_io_resources, -+ ARRAY_SIZE(nvsw_host_io_resources)); -+ if (IS_ERR(nvsw_host_dev)) -+ return PTR_ERR(nvsw_host_dev); -+ return 1; -+} ++ int i, err; + -+static int __init nvsw_host_dmi_spc5_switch_matched(const struct dmi_system_id *dmi) -+{ -+ int i; ++ /* Allocate the platform device structure */ ++ nvsw_host_pdev = ++ platform_device_alloc(NVSW_HOST_DEVICE_NAME, PLATFORM_DEVID_NONE); ++ if (!nvsw_host_pdev) ++ return -ENOMEM; ++ ++ /* Register the device with the platform bus */ ++ err = platform_device_add(nvsw_host_pdev); ++ if (err) { ++ platform_device_put(nvsw_host_pdev); ++ return err; ++ } + + /* Set system configuration. */ -+ nvsw_host_hid = HID181; -+ mux_num = ARRAY_SIZE(nvsw_host_spc5_mux_data); ++ nvsw_host_hid = HID193; ++ mux_num = ARRAY_SIZE(nvsw_host_spc6_mux_data); + for (i = 0; i < mux_num; i++) -+ nvsw_host_mux_data[i] = &nvsw_host_spc5_mux_data[i]; -+ nvsw_led_data = &nvsw_host_spc5_led; -+ nvsw_regs_io_data = &nvsw_host_spc5_regs_io; ++ nvsw_host_mux_data[i] = &nvsw_host_spc6_mux_data[i]; ++ nvsw_host_mux_brdinfo = &nvsw_host_spc6_mux_brdinfo; ++ nvsw_led_data = &nvsw_host_spc6_lc_led; ++ nvsw_regs_io_data = &nvsw_host_spc6_regs_io; + for (i = 0; i < ARRAY_SIZE(nvsw_host_wd_set_type3); i++) + nvsw_wd_data[i] = &nvsw_host_wd_set_type3[i]; -+ nvsw_i2c_data = &nvsw_mlxcpld_i2c_data; + -+ return nvsw_host_register_platform_device(); ++ return 0; +} + +static const struct dmi_system_id nvsw_host_dmi_table[] __initconst = { + { -+ .callback = nvsw_host_dmi_spc5_switch_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0024"), -+ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI181"), -+ }, -+ }, -+ { -+ .callback = nvsw_host_dmi_spc5_switch_matched, ++ .callback = nvsw_host_dmi_spc6_switch_matched, + .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0024"), -+ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI182"), ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0025"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI193"), + }, + }, + { } @@ -5207,35 +6592,84 @@ index 000000000..e54bd4109 + +static int nvsw_host_probe(struct platform_device *pdev) +{ ++ struct i2c_adapter *last_host_adapter; + struct nvsw_core *nvsw_core; -+ int i; ++ int i, err; + -+ nvsw_core = devm_kzalloc(&nvsw_host_dev->dev, sizeof(*nvsw_core), GFP_KERNEL); -+ if (!nvsw_core) -+ return -ENOMEM; ++ /* Ensure the I2C host driver has finished registering ++ * all 4 buses (0-3) to prevent the mux from stealing bus 3 ++ */ ++ last_host_adapter = i2c_get_adapter(NVSW_I2C_LAST_HOST_BUS_NR); ++ if (!last_host_adapter) { ++ dev_info(&pdev->dev, ++ "I2C adapter for bus %d is not ready, deferring probe\n", ++ NVSW_I2C_LAST_HOST_BUS_NR); ++ return -EPROBE_DEFER; ++ } ++ i2c_put_adapter(last_host_adapter); ++ ++ /* Get I2C mux parent adapter */ ++ nvsw_host_mux_i2c_adapter = i2c_get_adapter(NVSW_I2C_MUX_PARENT_BUS_NR); ++ if (!nvsw_host_mux_i2c_adapter) { ++ dev_err(&pdev->dev, ++ "I2C adapter for bus %d is not available\n", ++ NVSW_I2C_MUX_PARENT_BUS_NR); ++ return -ENODEV; ++ } ++ ++ /* Create device at the top of host I2C tree */ ++ nvsw_host_mux_brdinfo->platform_data = nvsw_host_mux_data; ++ nvsw_host_mux_i2c_client = i2c_new_client_device(nvsw_host_mux_i2c_adapter, ++ nvsw_host_mux_brdinfo); ++ if (IS_ERR(nvsw_host_mux_i2c_client)) { ++ dev_err(&pdev->dev, ++ "Failed to create client %s at bus %d at addr 0x%02x\n", ++ nvsw_host_mux_brdinfo->type, NVSW_I2C_MUX_PARENT_BUS_NR, ++ nvsw_host_mux_brdinfo->addr); ++ err = PTR_ERR(nvsw_host_mux_i2c_client); ++ goto i2c_new_client_device_fail; ++ } ++ ++ nvsw_core = devm_kzalloc(&pdev->dev, sizeof(*nvsw_core), GFP_KERNEL); ++ if (!nvsw_core) { ++ err = -ENOMEM; ++ goto nvsw_host_probe_fail; ++ } + + /* Set system configuration. */ -+ nvsw_core->dev = &nvsw_host_dev->dev; ++ nvsw_core->dev = &pdev->dev; + nvsw_core->hid = nvsw_host_hid; -+ nvsw_core->regmap_type = REGMAP_IO; ++ nvsw_core->regmap_type = REGMAP_I2C; ++ nvsw_core->client = nvsw_host_mux_i2c_client; + nvsw_core->mux_num = mux_num; + for (i = 0; i < ARRAY_SIZE(nvsw_wd_data); i++) + nvsw_core->wd_data[i] = nvsw_wd_data[i]; + nvsw_core->regio_data = nvsw_regs_io_data; + nvsw_core->led_data = nvsw_led_data; -+ nvsw_core->port_map = nvsw_host_spc5_port_map; -+ nvsw_core->mux_init = nvsw_host_spc5_mux_topology_init; -+ nvsw_core->mux_exit = nvsw_host_spc5_mux_topology_exit; -+ platform_set_drvdata(nvsw_host_dev, nvsw_core); ++ nvsw_core->mux_init = nvsw_host_spc6_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_host_spc6_mux_topology_exit; ++ platform_set_drvdata(pdev, nvsw_core); + -+ return nvsw_core_init(nvsw_core); ++ err = nvsw_core_init(nvsw_core); ++ if (!err) ++ return 0; ++ ++nvsw_host_probe_fail: ++ i2c_unregister_device(nvsw_host_mux_i2c_client); ++i2c_new_client_device_fail: ++ i2c_put_adapter(nvsw_host_mux_i2c_adapter); ++ nvsw_host_mux_i2c_adapter = NULL; ++ return err; +} + +static void nvsw_host_remove(struct platform_device *pdev) +{ -+ struct nvsw_core *nvsw_core = platform_get_drvdata(nvsw_host_dev); ++ struct nvsw_core *nvsw_core = platform_get_drvdata(pdev); + + nvsw_core_exit(nvsw_core); ++ i2c_unregister_device(nvsw_host_mux_i2c_client); ++ i2c_put_adapter(nvsw_host_mux_i2c_adapter); ++ nvsw_host_mux_i2c_adapter = NULL; +} + +static struct platform_driver nvsw_host_driver = { @@ -5249,19 +6683,27 @@ index 000000000..e54bd4109 + +static int __init nvsw_host_init(void) +{ ++ int err; ++ + if (!dmi_check_system(nvsw_host_dmi_table)) + return -ENODEV; + -+ return platform_driver_register(&nvsw_host_driver); ++ err = platform_driver_register(&nvsw_host_driver); ++ if (err) { ++ if (nvsw_host_pdev) ++ platform_device_unregister(nvsw_host_pdev); ++ } ++ ++ return err; +} +module_init(nvsw_host_init); + +static void __exit nvsw_host_exit(void) +{ -+ if (nvsw_host_dev) -+ platform_device_unregister(nvsw_host_dev); -+ + platform_driver_unregister(&nvsw_host_driver); ++ ++ if (nvsw_host_pdev) ++ platform_device_unregister(nvsw_host_pdev); +} +module_exit(nvsw_host_exit); + @@ -5271,10 +6713,10 @@ index 000000000..e54bd4109 + diff --git a/drivers/platform/mellanox/nvsw.h b/drivers/platform/mellanox/nvsw.h new file mode 100644 -index 000000000..9a0b48409 +index 000000000..91bdbc2ce --- /dev/null +++ b/drivers/platform/mellanox/nvsw.h -@@ -0,0 +1,292 @@ +@@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Nvidia BMC platform driver @@ -5357,6 +6799,9 @@ index 000000000..9a0b48409 +#define NVSW_REG_VR2_ALERT_OFFSET 0x255e +#define NVSW_REG_VR2_ALERT_EVENT_OFFSET 0x255f +#define NVSW_REG_VR2_ALERT_MASK_OFFSET 0x2560 ++#define NVSW_REG_PS_DC_OK_OFFSET 0x2567 ++#define NVSW_REG_PS_DC_OK_EVENT_OFFSET 0x2568 ++#define NVSW_REG_PS_DC_OK_MASK_OFFSET 0x2569 +#define NVSW_REG_CPLD8_PN_OFFSET 0x2573 +#define NVSW_REG_CPLD8_PN1_OFFSET 0x2574 +#define NVSW_REG_CPLD6_VER_OFFSET 0x2575 @@ -5504,6 +6949,8 @@ index 000000000..9a0b48409 + HID180, + HID181, + HID182, ++ HID185, ++ HID193, +}; + + /* The system register map type. */ diff --git a/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch b/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch index d6776c203..e17e68ccf 100644 --- a/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch +++ b/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch @@ -1,8 +1,8 @@ -From cb4bbd807ddd09b237809ac19e120ee3235f27e6 Mon Sep 17 00:00:00 2001 +From 270544d85808eae4a873cd2506451a3d96f23678 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 30 Jul 2025 20:41:33 +0300 -Subject: [PATCH 47/78] hwmon: mlxreg-fan: Prevent fans from getting stuck at 0 - RPM +Subject: [PATCH hwmon 2/2] hwmon: mlxreg-fan: Prevent fans from getting stuck + at 0 RPM The fans controlled by the driver can get stuck at 0 RPM if they are configured below a 20% duty cycle. The driver tries to avoid this by @@ -20,12 +20,11 @@ Tested-by: Nikolay Aleksandrov Signed-off-by: Ido Schimmel Signed-off-by: Vadim Pasternak --- - drivers/hwmon/mlxreg-fan.c | 5 ++--- - drivers/platform/mellanox/nvsw-bmc-hid162.c | 2 +- - 2 files changed, 3 insertions(+), 4 deletions(-) + drivers/hwmon/mlxreg-fan.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c -index 0e9ce70..2cd0b9c 100644 +index 0e9ce70a..2cd0b9cc 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -581,15 +581,14 @@ static int mlxreg_fan_cooling_config(struct device *dev, struct mlxreg_fan *fan) @@ -46,19 +45,6 @@ index 0e9ce70..2cd0b9c 100644 } return 0; -diff --git a/drivers/platform/mellanox/nvsw-bmc-hid162.c b/drivers/platform/mellanox/nvsw-bmc-hid162.c -index fbc7382..6ebe5be 100644 ---- a/drivers/platform/mellanox/nvsw-bmc-hid162.c -+++ b/drivers/platform/mellanox/nvsw-bmc-hid162.c -@@ -2012,7 +2012,7 @@ static struct mlxreg_core_data nvsw_bmc_hid180_regio_data[] = { - { - .label = "mcu2_reset", - .reg = NVSW_REG_RESET_GP2_OFFSET, -- .mask = GENMASK(7, 0) & ~BIT(6), -+ .mask = GENMASK(7, 0) & ~BIT(7), - .mode = 0644, - }, - { -- -2.8.4 +2.34.1 diff --git a/patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch b/patches-sonic/0054-1-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch similarity index 94% rename from patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch rename to patches-sonic/0054-1-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch index 7f058ea7b..7abef897d 100644 --- a/patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch +++ b/patches-sonic/0054-1-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch @@ -1,7 +1,7 @@ -From a209121e8dc093705e0f3fcc3aad27d4c28d949d Mon Sep 17 00:00:00 2001 +From e9caf9cf3e69dff922c98c0e5e0ffe7a2fd0a7c7 Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Mon, 9 Dec 2024 11:42:37 +0200 -Subject: [PATCH 69/78] platform: mellanox: Downstream: Add support for new +Subject: [PATCH 17/40] platform: mellanox: Downstream: Add support for new Nvidia IB DGX system based on class VMOD0010 This system is based on Nvidia QM9700 64x400G QTM-2 IB switch, with the @@ -18,15 +18,15 @@ Reviewed-by: Vadim Pasternak 1 file changed, 454 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 9203ed8..710c21d 100644 +index b2ea7e8..4c1073b 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c -@@ -825,6 +825,16 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { +@@ -824,6 +824,16 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { }, }; +/* Platform hotplug dgx data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_dgx_psu_items_data[] = { ++static struct mlxreg_core_data mlxplat_mlxcpld_dgx_pdb_items_data[] = { + { + .label = "pdb1", + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, @@ -38,7 +38,7 @@ index 9203ed8..710c21d 100644 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { { .label = "pwr1", -@@ -874,6 +884,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = +@@ -873,6 +883,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = }, }; @@ -54,17 +54,17 @@ index 9203ed8..710c21d 100644 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { { .label = "fan1", -@@ -1497,6 +1516,45 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { +@@ -1496,6 +1515,45 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { } }; +static struct mlxreg_core_item mlxplat_mlxcpld_ext_dgx_items[] = { + { -+ .data = mlxplat_mlxcpld_dgx_psu_items_data, ++ .data = mlxplat_mlxcpld_dgx_pdb_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = MLXPLAT_CPLD_PSU_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_psu_items_data), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_pdb_items_data), + .inversed = 1, + .health = false, + }, @@ -100,7 +100,7 @@ index 9203ed8..710c21d 100644 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { { .data = mlxplat_mlxcpld_default_ng_psu_items_data, -@@ -1549,6 +1607,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { +@@ -1548,6 +1606,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { }; static @@ -117,7 +117,7 @@ index 9203ed8..710c21d 100644 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { .items = mlxplat_mlxcpld_ng800_items, .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), -@@ -5048,6 +5116,359 @@ static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { +@@ -5037,6 +5105,359 @@ static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), }; @@ -477,7 +477,7 @@ index 9203ed8..710c21d 100644 /* Platform register access for modular systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { { -@@ -7799,6 +8220,32 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) +@@ -7787,6 +8208,32 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) return mlxplat_register_platform_device(); } @@ -510,7 +510,7 @@ index 9203ed8..710c21d 100644 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) { int i; -@@ -8095,6 +8542,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { +@@ -8060,6 +8507,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { }, }, { diff --git a/patches-sonic/0055-1-platform-mellanox-mlx-platform-Add-support-DGX-flavo.patch b/patches-sonic/0055-1-platform-mellanox-mlx-platform-Add-support-DGX-flavo.patch new file mode 100644 index 000000000..1b399ac53 --- /dev/null +++ b/patches-sonic/0055-1-platform-mellanox-mlx-platform-Add-support-DGX-flavo.patch @@ -0,0 +1,63 @@ +From ef65e699e5077b48a501e965d19f750bd23f6a27 Mon Sep 17 00:00:00 2001 +From: Oleksandr Shamray +Date: Fri, 5 Dec 2025 12:07:48 +0200 +Subject: [PATCH 08/30] platform: mellanox: mlx-platform: Add support DGX + flavor of 400GB/s ethernet switch. + +This system is based on Nvidia SN4700 Spectrum-3 Based 32x400Gb/s ETH +Switch System, with the +following key changes: + +Key changes: +- New Power Supply: AC/DC PSUs power replaced by rack busbar input power + ORv3 DC 48V-54V. +- Dimensions MGX/DGX 1U compliance Tool-less top cover (fast cover + opening) + +System class: VMOD0010 +System SKU: HI184 + +Reviewed-by: Vadim Pasternak vadimp@mellanox.com + +Signed-off-by: Oleksandr Shamray +--- + drivers/platform/mellanox/mlx-platform.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index ed1e33cb01f4..7e5d18700e1c 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -8185,6 +8185,7 @@ static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) + static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) + { + int i; ++ const char *sku; + + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; + mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); +@@ -8194,11 +8195,19 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) + mlxplat_mux_data[i].n_values = + ARRAY_SIZE(mlxplat_msn21xx_channels); + } +- mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; ++ ++ sku = dmi_get_system_info(DMI_PRODUCT_SKU); ++ if (sku && !strcmp(sku, "HI184")) { ++ mlxplat_hotplug = &mlxplat_mlxcpld_dgx_ext_data; ++ mlxplat_regs_io = &mlxplat_dgx_ng_regs_io_data; ++ } else { ++ mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ } ++ + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; + mlxplat_led = &mlxplat_default_ng_led_data; +- mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; + mlxplat_fan = &mlxplat_default_fan_data; + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; +-- +2.47.3 + diff --git a/patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch b/patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch index 4a3c62055..5774a87da 100644 --- a/patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch +++ b/patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch @@ -1,7 +1,7 @@ -From 817b5cfab9f1eef11a244020caf1987bb37f682e Mon Sep 17 00:00:00 2001 +From a6c422c8a1a6416e34590988537f993b4b36e0ea Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Mon, 9 Dec 2024 13:38:05 +0200 -Subject: [PATCH 55/78] platform: mellanox: Downstream: Add support DGX flavor +Subject: [PATCH 18/40] platform: mellanox: Downstream: Add support DGX flavor of next-generation 800GB/s ethernet switch. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -20,10 +20,10 @@ Signed-off-by: Oleksandr Shamray 1 file changed, 28 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index de3dbaf..3472c99 100644 +index 4c1073b..54f52d7 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c -@@ -7871,6 +7871,27 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) +@@ -8318,6 +8318,27 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) return mlxplat_register_platform_device(); } @@ -51,7 +51,7 @@ index de3dbaf..3472c99 100644 static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) { int i; -@@ -8072,6 +8093,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { +@@ -8526,6 +8547,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { }, }, { diff --git a/patches-sonic/0058-PCI-DOE-Poll-DOE-Busy-bit-for-up-to-1-second-in-pci.patch b/patches-sonic/0058-PCI-DOE-Poll-DOE-Busy-bit-for-up-to-1-second-in-pci.patch new file mode 100644 index 000000000..c8e71f722 --- /dev/null +++ b/patches-sonic/0058-PCI-DOE-Poll-DOE-Busy-bit-for-up-to-1-second-in-pci.patch @@ -0,0 +1,86 @@ +From 86efc62d031307e53ad4011e0aa8898e029cef47 Mon Sep 17 00:00:00 2001 +From: Gregory Price +Date: Fri, 4 Oct 2024 12:28:28 -0400 +Subject: [PATCH] PCI/DOE: Poll DOE Busy bit for up to 1 second in + pci_doe_send_req() + +During initial device probe, the PCI DOE busy bit for some CXL devices may +be left set for a longer period than expected by the current driver logic. +Despite local comments stating DOE Busy is unlikely to be detected, it +appears commonly specifically during boot when CXL devices are being +probed. + +The symptom was messages like this: + + endpoint6: DOE failed -EBUSY + +produced by cxl_cdat_get_length() or cxl_cdat_read_table(). + +This was observed on a single socket AMD platform with 2 CXL memory +expanders attached to the single socket. It was not the case that +concurrent accesses were being made, as validated by monitoring mailbox +commands on the device side. + +This behavior has been observed with multiple CXL memory expanders from +different vendors - so it appears unrelated to the model. + +In all observed tests, only a small period of the retry window is actually +used - typically only a handful of loop iterations. + +Polling on the PCI DOE Busy Bit for (at max) one PCI DOE timeout interval +(1 second), resolves this issue cleanly. + +Per PCIe r6.2 sec 6.30.3, the DOE Busy Bit being cleared does not raise an +interrupt, so polling is the best option in this scenario. + +Subsequent code in doe_statemachine_work() and abort paths also wait for up +to 1 PCI DOE timeout interval, so this order of (potential) additional +delay is presumed acceptable. + +Suggested-by: Lukas Wunner +Link: https://lore.kernel.org/r/20241004162828.314-1-gourry@gourry.net +Signed-off-by: Gregory Price +[bhelgaas: fix nits and add error message to commit log] +Signed-off-by: Bjorn Helgaas +Reviewed-by: Lukas Wunner +Reviewed-by: Jonathan Cameron +--- + drivers/pci/doe.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c +index 652d63df9d22..7bd7892c5222 100644 +--- a/drivers/pci/doe.c ++++ b/drivers/pci/doe.c +@@ -146,6 +146,7 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb, + { + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; ++ unsigned long timeout_jiffies; + size_t length, remainder; + u32 val; + int i; +@@ -155,8 +156,19 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb, + * someone other than Linux (e.g. firmware) is using the mailbox. Note + * it is expected that firmware and OS will negotiate access rights via + * an, as yet to be defined, method. ++ * ++ * Wait up to one PCI_DOE_TIMEOUT period to allow the prior command to ++ * finish. Otherwise, simply error out as unable to field the request. ++ * ++ * PCIe r6.2 sec 6.30.3 states no interrupt is raised when the DOE Busy ++ * bit is cleared, so polling here is our best option for the moment. + */ +- pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); ++ timeout_jiffies = jiffies + PCI_DOE_TIMEOUT; ++ do { ++ pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); ++ } while (FIELD_GET(PCI_DOE_STATUS_BUSY, val) && ++ !time_after(jiffies, timeout_jiffies)); ++ + if (FIELD_GET(PCI_DOE_STATUS_BUSY, val)) + return -EBUSY; + +-- +2.34.1 + diff --git a/patches-sonic/0059-hwmon-pmbus-xdpe1a2g7b-Add-support-for-XDPE1A2G7B-5B.patch b/patches-sonic/0059-hwmon-pmbus-xdpe1a2g7b-Add-support-for-XDPE1A2G7B-5B.patch new file mode 100644 index 000000000..4412fc995 --- /dev/null +++ b/patches-sonic/0059-hwmon-pmbus-xdpe1a2g7b-Add-support-for-XDPE1A2G7B-5B.patch @@ -0,0 +1,199 @@ +From 880de7f04e7066f8c86f8ee3914e35de09404830 Mon Sep 17 00:00:00 2001 +From: Vasily Vityukov +Date: Tue, 10 Feb 2026 15:29:17 +0200 +Subject: [PATCH] hwmon: (pmbus/xdpe1a2g7b) Add support for XDPE1A2G7B/5B + devices + +--- + drivers/hwmon/pmbus/Kconfig | 9 +++ + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/pmbus.h | 2 +- + drivers/hwmon/pmbus/pmbus_core.c | 4 ++ + drivers/hwmon/pmbus/xdpe1a2g7b.c | 116 +++++++++++++++++++++++++++++++ + 5 files changed, 131 insertions(+), 1 deletion(-) + create mode 100644 drivers/hwmon/pmbus/xdpe1a2g7b.c + +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index 08c9e7b6e9b0..5ddb715fad8b 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -621,6 +621,15 @@ config SENSORS_XDPE152 + This driver can also be built as a module. If so, the module will + be called xdpe152c4. + ++config SENSORS_XDPE1A2G7B ++ tristate "Infineon XDPE1A2G7B" ++ help ++ If you say yes here you get hardware monitoring support for Infineon ++ XDPE1A2G7B and XDPE1A2G5B. ++ ++ This driver can also be built as a module. If so, the module will ++ be called xdpe1a2g7b. ++ + config SENSORS_XDPE122 + tristate "Infineon XDPE122 family" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index 1a641d9a1819..9ebd0524a958 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -64,5 +64,6 @@ obj-$(CONFIG_SENSORS_UCD9200) += ucd9200.o + obj-$(CONFIG_SENSORS_XDP710) += xdp710.o + obj-$(CONFIG_SENSORS_XDPE122) += xdpe12284.o + obj-$(CONFIG_SENSORS_XDPE152) += xdpe152c4.o ++obj-$(CONFIG_SENSORS_XDPE1A2G7B) += xdpe1a2g7b.o + obj-$(CONFIG_SENSORS_ZL6100) += zl6100.o + obj-$(CONFIG_SENSORS_PIM4328) += pim4328.o +diff --git a/drivers/hwmon/pmbus/pmbus.h b/drivers/hwmon/pmbus/pmbus.h +index d605412a3173..1f6c46ed597b 100644 +--- a/drivers/hwmon/pmbus/pmbus.h ++++ b/drivers/hwmon/pmbus/pmbus.h +@@ -416,7 +416,7 @@ enum pmbus_sensor_classes { + #define PMBUS_PAGE_VIRTUAL BIT(31) /* Page is virtual */ + + enum pmbus_data_format { linear = 0, ieee754, direct, vid }; +-enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv }; ++enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv, nvidia195mv }; + + /* PMBus revision identifiers */ + #define PMBUS_REV_10 0x00 /* PMBus revision 1.0 */ +diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c +index 943118e5d3a8..dfab7f5506d5 100644 +--- a/drivers/hwmon/pmbus/pmbus_core.c ++++ b/drivers/hwmon/pmbus/pmbus_core.c +@@ -884,6 +884,10 @@ static s64 pmbus_reg2data_vid(struct pmbus_data *data, + if (val >= 0x0 && val <= 0xd8) + rv = DIV_ROUND_CLOSEST(155000 - val * 625, 100); + break; ++ case nvidia195mv: ++ if (val >= 0x01) ++ rv = 195 + (val - 1) * 5; /* VID step is 5mv */ ++ break; + } + return rv; + } +diff --git a/drivers/hwmon/pmbus/xdpe1a2g7b.c b/drivers/hwmon/pmbus/xdpe1a2g7b.c +new file mode 100644 +index 000000000000..8bd0ba0abb72 +--- /dev/null ++++ b/drivers/hwmon/pmbus/xdpe1a2g7b.c +@@ -0,0 +1,116 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Hardware monitoring driver for Infineon Multi-phase Digital XDPE1A2G7B ++ * and XDPE1A2G5B Controllers ++ * ++ * Copyright (c) 2026 Infineon Technologies. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "pmbus.h" ++ ++#define XDPE1A2G7B_PAGE_NUM 2 ++#define XDPE1A2G7B_NVIDIA_195MV 0x1E /* NVIDIA mode 1.95mV, VID step is 5mV */ ++ ++static int xdpe1a2g7b_identify(struct i2c_client *client, ++ struct pmbus_driver_info *info) ++{ ++ u8 vout_params; ++ int i, ret, vout_mode; ++ ++ vout_mode = pmbus_read_byte_data(client, 0, PMBUS_VOUT_MODE); ++ if (vout_mode >= 0 && vout_mode != 0xff) { ++ switch (vout_mode >> 5) { ++ case 0: ++ info->format[PSC_VOLTAGE_OUT] = linear; ++ return 0; ++ case 1: ++ info->format[PSC_VOLTAGE_OUT] = vid; ++ break; ++ default: ++ return -ENODEV; ++ } ++ } ++ ++ for (i = 0; i < info->pages; i++) { ++ /* Read the VOUT_MODE register for VID Code Type. */ ++ ret = pmbus_read_byte_data(client, i, PMBUS_VOUT_MODE); ++ if (ret < 0) ++ return ret; ++ ++ vout_params = ret & GENMASK(4, 0); ++ switch (vout_params) { ++ case XDPE1A2G7B_NVIDIA_195MV: ++ info->vrm_version[i] = nvidia195mv; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct pmbus_driver_info xdpe1a2g7b_info = { ++ .pages = XDPE1A2G7B_PAGE_NUM, ++ .identify = xdpe1a2g7b_identify, ++ .format[PSC_VOLTAGE_IN] = linear, ++ .format[PSC_VOLTAGE_OUT] = linear, ++ .format[PSC_TEMPERATURE] = linear, ++ .format[PSC_CURRENT_IN] = linear, ++ .format[PSC_CURRENT_OUT] = linear, ++ .format[PSC_POWER] = linear, ++ .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | ++ PMBUS_HAVE_IIN | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | ++ PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2 | PMBUS_HAVE_STATUS_TEMP | ++ PMBUS_HAVE_POUT | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT, ++ .func[1] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_IIN | ++ PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_PIN | ++ PMBUS_HAVE_POUT | PMBUS_HAVE_STATUS_INPUT, ++}; ++ ++static int xdpe1a2g7b_probe(struct i2c_client *client) ++{ ++ struct pmbus_driver_info *info; ++ ++ info = devm_kmemdup(&client->dev, &xdpe1a2g7b_info, sizeof(*info), ++ GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ return pmbus_do_probe(client, info); ++} ++ ++static const struct i2c_device_id xdpe1a2g7b_id[] = { { "xdpe1a2g7b" }, ++ { "xdpe1a2g5b" }, ++ {} }; ++ ++MODULE_DEVICE_TABLE(i2c, xdpe1a2g7b_id); ++ ++static const struct of_device_id __maybe_unused xdpe1a2g7b_of_match[] = { ++ { .compatible = "infineon,xdpe1a2g7b" }, ++ { .compatible = "infineon,xdpe1a2g5b" }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, xdpe1a2g7b_of_match); ++ ++static struct i2c_driver xdpe1a2g7b_driver = { ++ .driver = { ++ .name = "xdpe1a2g7b", ++ .of_match_table = of_match_ptr(xdpe1a2g7b_of_match), ++ }, ++ .probe = xdpe1a2g7b_probe, ++ .id_table = xdpe1a2g7b_id, ++}; ++ ++module_i2c_driver(xdpe1a2g7b_driver); ++ ++MODULE_AUTHOR("Ashish Yadav "); ++MODULE_DESCRIPTION("PMBus driver for Infineon XDPE1A2G7B/5B"); ++MODULE_LICENSE("GPL"); ++MODULE_IMPORT_NS(PMBUS); +-- +2.34.1 + diff --git a/patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch b/patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch deleted file mode 100644 index 94bab3943..000000000 --- a/patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch +++ /dev/null @@ -1,92 +0,0 @@ -From e598aed4536365af75ab5543364c79123d243104 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 2 Aug 2023 07:58:51 +0000 -Subject: [PATCH 57/78] platform: mlx-platform: Downstream: Add SPI path for - rack switch for EROT access - -Create spidev for OOB access to External Root of Trusts devices. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/mellanox/mlx-platform.c | 17 +++++++++++++++++ - drivers/spi/spi.c | 1 + - 2 files changed, 18 insertions(+) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 3472c99..9203ed8 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #define MLX_PLAT_DEVICE_NAME "mlxplat" - -@@ -3336,6 +3337,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, - }; - -+static struct spi_board_info rack_switch_switch_spi_board_info[] = { -+ { -+ .modalias = "spidev", -+ .irq = -1, -+ .max_speed_hz = 20000000, -+ .bus_num = 0, -+ .chip_select = 0, -+ }, -+}; -+ - /* Platform hotplug for 800G systems family data */ - static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { - { -@@ -7524,6 +7535,7 @@ static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; - static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; -+static struct spi_board_info *mlxplat_spi; - static struct pci_dev *lpc_bridge; - static struct pci_dev *i2c_bridge; - static struct pci_dev *jtag_bridge; -@@ -7846,6 +7858,7 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm - mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; -+ mlxplat_spi = rack_switch_switch_spi_board_info; - - return mlxplat_register_platform_device(); - } -@@ -7911,6 +7924,7 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; - pm_power_off = mlxplat_poweroff; - mlxplat_reboot_nb = &mlxplat_reboot_default_nb; -+ mlxplat_spi = rack_switch_switch_spi_board_info; - - return mlxplat_register_platform_device(); - } -@@ -8511,6 +8525,9 @@ static int mlxplat_platdevs_init(struct mlxplat_priv *priv) - } - } - -+ if (mlxplat_spi) -+ spi_register_board_info(mlxplat_spi, 1); -+ - /* Add WD drivers. */ - err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); - if (err) -diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c -index 0f3e6e2..1e35969 100644 ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -952,6 +952,7 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n) - - return 0; - } -+EXPORT_SYMBOL(spi_register_board_info); - - /*-------------------------------------------------------------------------*/ - --- -2.8.4 - diff --git a/patches-sonic/series b/patches-sonic/series index 657538f1e..3b81458a1 100644 --- a/patches-sonic/series +++ b/patches-sonic/series @@ -111,11 +111,14 @@ driver-i2c-smbus-add-disable_spd-module-parameter.patch 0052-platform-mellanox-Introduce-support-for-switches-equ.patch 0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch 0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch +0054-1-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch 0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch +0055-1-platform-mellanox-mlx-platform-Add-support-DGX-flavo.patch 0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch 0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch +0058-PCI-DOE-Poll-DOE-Busy-bit-for-up-to-1-second-in-pci.patch +0059-hwmon-pmbus-xdpe1a2g7b-Add-support-for-XDPE1A2G7B-5B.patch 8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch -8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch 8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch 8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch 8004-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch @@ -127,7 +130,6 @@ driver-i2c-smbus-add-disable_spd-module-parameter.patch 8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch 8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch 8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch -9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch ###-> mellanox_hw_mgmt-end # Cisco patches for 5.10 kernel