Now first before you start reading first clone this repo: https://github.com/CTSRD-CHERI/cheribuild.
And run ./cheribuild.py run-riscv64-purecap -d -f, you probably would have finished reading before
it has finished building.
This first most important thing that is needed would ideally be the CHERI ISA spec from Cambridge. Even when working on Morello it explains the motivation behind all the work: link. I would recommend starting with the Design Goals [p. 19] then reading through the chapter on the CHERI Protection Model [p. 41] until the end of Architectural Capabilities [p. 59]. Most of the other stuff can be read later.
The next thing to go through is: link. It's main purpose is to explain how CHERI capabilities can be used in C/C++, but all the examples are very basic. This document describes the functions defined in the llvm header files (link) but it is also recommended to check the ones described in the cheribsd repo (link).
The last thing would be then to go back to the ISA specification for the arch you will target (Morello Cheri) and see which instruction are not represented by the intrinsics in the header files.
If you are interested about the different trains of thought throughout the 10 year life of the project I would recommend reading this in that order:
- The first 5 years of the project
- Efficient Tagged Memory The citations here are particularly interesting to trace the origins of tagged memory as a whole.
- Go thought the
Version Historysection in each of the CHERI ISA spec document versions, all of them can be found here: techreports. There can also be found the Introduction To CHERI which isn't a very good place to start.