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Move "vector maximum" intrinsics to the appropriate section #429

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44 changes: 22 additions & 22 deletions neon_intrinsics/advsimd.md
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Expand Up @@ -923,24 +923,28 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.

#### Maximum

| Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures |
|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--------------------------------|-----------------------------|--------------------|---------------------------|
| <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8" target="_blank">vmax_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x8_t b)</code> | `a -> Vn.8B`<br>`b -> Vm.8B` | `SMAX Vd.8B,Vn.8B,Vm.8B` | `Vd.8B -> result` | `v7/A32/A64` |
| <code>int8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8" target="_blank">vmaxq_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t b)</code> | `a -> Vn.16B`<br>`b -> Vm.16B` | `SMAX Vd.16B,Vn.16B,Vm.16B` | `Vd.16B -> result` | `v7/A32/A64` |
| <code>int16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16" target="_blank">vmax_s16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x4_t b)</code> | `a -> Vn.4H`<br>`b -> Vm.4H` | `SMAX Vd.4H,Vn.4H,Vm.4H` | `Vd.4H -> result` | `v7/A32/A64` |
| <code>int16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16" target="_blank">vmaxq_s16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x8_t b)</code> | `a -> Vn.8H`<br>`b -> Vm.8H` | `SMAX Vd.8H,Vn.8H,Vm.8H` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>int32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32" target="_blank">vmax_s32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `SMAX Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>int32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32" target="_blank">vmaxq_s32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `SMAX Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8" target="_blank">vmax_u8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x8_t b)</code> | `a -> Vn.8B`<br>`b -> Vm.8B` | `UMAX Vd.8B,Vn.8B,Vm.8B` | `Vd.8B -> result` | `v7/A32/A64` |
| <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8" target="_blank">vmaxq_u8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x16_t b)</code> | `a -> Vn.16B`<br>`b -> Vm.16B` | `UMAX Vd.16B,Vn.16B,Vm.16B` | `Vd.16B -> result` | `v7/A32/A64` |
| <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16" target="_blank">vmax_u16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x4_t b)</code> | `a -> Vn.4H`<br>`b -> Vm.4H` | `UMAX Vd.4H,Vn.4H,Vm.4H` | `Vd.4H -> result` | `v7/A32/A64` |
| <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16" target="_blank">vmaxq_u16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x8_t b)</code> | `a -> Vn.8H`<br>`b -> Vm.8H` | `UMAX Vd.8H,Vn.8H,Vm.8H` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32" target="_blank">vmax_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `UMAX Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32" target="_blank">vmaxq_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `UMAX Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32" target="_blank">vmax_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `FMAX Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32" target="_blank">vmaxq_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `FMAX Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64" target="_blank">vmax_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t b)</code> | `a -> Dn`<br>`b -> Dm` | `FMAX Dd,Dn,Dm` | `Dd -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64" target="_blank">vmaxq_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t b)</code> | `a -> Vn.2D`<br>`b -> Vm.2D` | `FMAX Vd.2D,Vn.2D,Vm.2D` | `Vd.2D -> result` | `A64` |
| Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures |
|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--------------------------------|-----------------------------|--------------------|---------------------------|
| <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8" target="_blank">vmax_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x8_t b)</code> | `a -> Vn.8B`<br>`b -> Vm.8B` | `SMAX Vd.8B,Vn.8B,Vm.8B` | `Vd.8B -> result` | `v7/A32/A64` |
| <code>int8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8" target="_blank">vmaxq_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t b)</code> | `a -> Vn.16B`<br>`b -> Vm.16B` | `SMAX Vd.16B,Vn.16B,Vm.16B` | `Vd.16B -> result` | `v7/A32/A64` |
| <code>int16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16" target="_blank">vmax_s16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x4_t b)</code> | `a -> Vn.4H`<br>`b -> Vm.4H` | `SMAX Vd.4H,Vn.4H,Vm.4H` | `Vd.4H -> result` | `v7/A32/A64` |
| <code>int16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16" target="_blank">vmaxq_s16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int16x8_t b)</code> | `a -> Vn.8H`<br>`b -> Vm.8H` | `SMAX Vd.8H,Vn.8H,Vm.8H` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>int32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32" target="_blank">vmax_s32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `SMAX Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>int32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32" target="_blank">vmaxq_s32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; int32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `SMAX Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8" target="_blank">vmax_u8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x8_t b)</code> | `a -> Vn.8B`<br>`b -> Vm.8B` | `UMAX Vd.8B,Vn.8B,Vm.8B` | `Vd.8B -> result` | `v7/A32/A64` |
| <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8" target="_blank">vmaxq_u8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x16_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint8x16_t b)</code> | `a -> Vn.16B`<br>`b -> Vm.16B` | `UMAX Vd.16B,Vn.16B,Vm.16B` | `Vd.16B -> result` | `v7/A32/A64` |
| <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16" target="_blank">vmax_u16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x4_t b)</code> | `a -> Vn.4H`<br>`b -> Vm.4H` | `UMAX Vd.4H,Vn.4H,Vm.4H` | `Vd.4H -> result` | `v7/A32/A64` |
| <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16" target="_blank">vmaxq_u16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x8_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint16x8_t b)</code> | `a -> Vn.8H`<br>`b -> Vm.8H` | `UMAX Vd.8H,Vn.8H,Vm.8H` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32" target="_blank">vmax_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `UMAX Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32" target="_blank">vmaxq_u32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; uint32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `UMAX Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32" target="_blank">vmax_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `FMAX Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32" target="_blank">vmaxq_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `FMAX Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64" target="_blank">vmax_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t b)</code> | `a -> Dn`<br>`b -> Dm` | `FMAX Dd,Dn,Dm` | `Dd -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64" target="_blank">vmaxq_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t b)</code> | `a -> Vn.2D`<br>`b -> Vm.2D` | `FMAX Vd.2D,Vn.2D,Vm.2D` | `Vd.2D -> result` | `A64` |
| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32" target="_blank">vmaxnm_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `FMAXNM Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `A32/A64` |
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32" target="_blank">vmaxnmq_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `FMAXNM Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64" target="_blank">vmaxnm_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t b)</code> | `a -> Dn`<br>`b -> Dm` | `FMAXNM Dd,Dn,Dm` | `Dd -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64" target="_blank">vmaxnmq_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t b)</code> | `a -> Vn.2D`<br>`b -> Vm.2D` | `FMAXNM Vd.2D,Vn.2D,Vm.2D` | `Vd.2D -> result` | `A64` |

#### Minimum

Expand All @@ -962,10 +966,6 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32" target="_blank">vminq_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `FMIN Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64" target="_blank">vmin_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t b)</code> | `a -> Dn`<br>`b -> Dm` | `FMIN Dd,Dn,Dm` | `Dd -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64" target="_blank">vminq_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t b)</code> | `a -> Vn.2D`<br>`b -> Vm.2D` | `FMIN Vd.2D,Vn.2D,Vm.2D` | `Vd.2D -> result` | `A64` |
| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32" target="_blank">vmaxnm_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `FMAXNM Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `A32/A64` |
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32" target="_blank">vmaxnmq_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `FMAXNM Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64" target="_blank">vmaxnm_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t b)</code> | `a -> Dn`<br>`b -> Dm` | `FMAXNM Dd,Dn,Dm` | `Dd -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64" target="_blank">vmaxnmq_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x2_t b)</code> | `a -> Vn.2D`<br>`b -> Vm.2D` | `FMAXNM Vd.2D,Vn.2D,Vm.2D` | `Vd.2D -> result` | `A64` |
| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32" target="_blank">vminnm_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x2_t b)</code> | `a -> Vn.2S`<br>`b -> Vm.2S` | `FMINNM Vd.2S,Vn.2S,Vm.2S` | `Vd.2S -> result` | `A32/A64` |
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32" target="_blank">vminnmq_f32</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float32x4_t b)</code> | `a -> Vn.4S`<br>`b -> Vm.4S` | `FMINNM Vd.4S,Vn.4S,Vm.4S` | `Vd.4S -> result` | `A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64" target="_blank">vminnm_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t a,<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t b)</code> | `a -> Dn`<br>`b -> Dm` | `FMINNM Dd,Dn,Dm` | `Dd -> result` | `A64` |
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