In this project, single-cycle RISC-V processor is designed and implemented using Verilog HDL. The processor is based on the RV32I instruction set and executes each instruction in a single clock cycle. The main aim of the project is to understand how a basic CPU works internally, including instruction fetch, decoding, execution, memory access, and write-back.
The design supports a subset of the RISC-V instruction set, mainly arithmetic, logical, load, and store instructions. All components of the processor are designed as separate modules and then integrated at the top level to form a complete working system.